CDC913 PC MOTHERBOARD CLOCK GENERATOR WITH DUAL 1-TO-4 BUFFERS AND 3-STATE OUTPUTS SCAS502C – APRIL 1995 – REVISED MAY 1996 D D D D D D D D Generates Programmable CPU Clock Output (50 MHz, 60 MHz, or 66 MHz) Generates 33-MHz Clock for Asynchronous PCI One 14.318-MHz Reference Clock Output All Output Clock Frequencies Derived From a Single 14.31818-MHz Crystal Input LVTTL-Compatible Inputs and Outputs Internal Loop Filters for Phase-Lock Loops Eliminate the Need for External Components Operates at 3.3-V VCC Package Options Include Plastic Small-Outline (DW) and Shrink Small-Outline (DB) Packages DB OR DW PACKAGE (TOP VIEW) X1 X2 AGND VCC 1Y1 1Y2 1Y3 1Y4 GND 1A CPUCLK SEL0 1 24 2 23 3 22 4 21 5 20 6 19 7 18 8 17 9 16 10 15 11 14 12 13 AVCC REFCLK OE VCC 2Y1 2Y2 2Y3 2Y4 GND 2A PCICLK SEL1 description The CDC913 is a high-performance clock generator with integrated dual 1-to-4 buffers, which simplifies clock system design for PC motherboards. The CDC913 consists of a crystal oscillator, two phase-locked loops (PLL), and two 1-to-4 buffers. The CDC913 generates all frequencies using a single 14.318-MHz crystal. The CPUCLK output is programmable to one of three frequencies (50 MHz, 60 MHz, or 66 MHz) via the SEL0 and SEL1 inputs. PCICLK outputs a 33-MHz clock, independent of the CPUCLK frequency. REFCLK provides a buffered copy of the 14.318-MHz reference. The oscillator and PLLs in the CDC913 are bypassed when in the TEST mode, i.e., SEL1 = SEL0 = H. When in the TEST mode, a test clock can be driven over the X1 input and buffered out from the PCICLK, CPUCLK, and REFCLK outputs. Outputs 1Yn and 2Yn are 3-state outputs and are enabled via OE. When OE is high, the outputs are in the high-impedance state. When OE is low, the outputs are enabled. Since the CDC913 is based on PLL circuitry, it requires a stabilization time to achieve phase lock of the PLL. This stabilization time is required following power up and application of a fixed-frequency, fixed-phase signal at the X1 input, and following any changes to the SELn inputs. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1996, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 CDC913 PC MOTHERBOARD CLOCK GENERATOR WITH DUAL 1-TO-4 BUFFERS AND 3-STATE OUTPUTS SCAS502C – APRIL 1995 – REVISED MAY 1996 Function Tables SEL0 SEL1 X1 CPUCLK PCICLK REFCLK L L 14.318 MHz 50 MHz 33 MHz 14.318 MHz H L 14.318 MHz 60 MHz 33 MHz 14.318 MHz L H 14.318 MHz TCLK† 66 MHz TCLK† 33 MHz TCLK† 14.318 MHz TCLK† H H † Test clock (TCLK) is driven over X1 when the CDC913 is in the TEST mode; i.e., SEL1 = SEL0 = H. 2 OE 1A 2A 1Yn 2Yn H X X Hi-Z Hi-Z L L L L L L L H L H L H L H L L H H H H POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CDC913 PC MOTHERBOARD CLOCK GENERATOR WITH DUAL 1-TO-4 BUFFERS AND 3-STATE OUTPUTS SCAS502C – APRIL 1995 – REVISED MAY 1996 functional block diagram X1 23 1 REFCLK OSC X2 2 14 PCICLK 33-MHz PLL 11 CPUCLK CPU-CLK PLL SEL0 SEL1 OE 12 13 Select Logic 22 5 6 1A 10 7 8 20 19 2A 15 18 17 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1Y1 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 3 CDC913 PC MOTHERBOARD CLOCK GENERATOR WITH DUAL 1-TO-4 BUFFERS AND 3-STATE OUTPUTS SCAS502C – APRIL 1995 – REVISED MAY 1996 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Voltage range applied to any output in the high state or power-off state, VO . . . . . . . . –0.5 V to VCC + 0.5 V Current into any output in the low state, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 IOHmax Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA Maximum power dissipation at TA = 55°C (in still air) (see Note 2): DB package . . . . . . . . . . . . . . . . . 0.65 W DW package . . . . . . . . . . . . . . . . . . 1.7 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils. For more information, refer to the Package Thermal Considerations application note in the ABT Advanced BiCMOS Technology Data Book, literature number SCBD002. recommended operating conditions (see Note 3) VCC VIH Supply voltage VIL VI Low-level input voltage High-level input voltage MIN MAX 3.135 3.6 2 Input voltage 0 REFCLK PCICLK IOH IOL High-level output current 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 V 0.8 V VCC –12 V –6 1Yn –12 2Yn –12 REFCLK 12 PCICLK 6 CPUCLK TA Operating free-air temperature NOTE 3: Unused inputs must be held high or low to prevent them from floating. V –6 CPUCLK Low-level output current UNIT 6 1Yn 12 2Yn 12 0 70 mA mA °C CDC913 PC MOTHERBOARD CLOCK GENERATOR WITH DUAL 1-TO-4 BUFFERS AND 3-STATE OUTPUTS SCAS502C – APRIL 1995 – REVISED MAY 1996 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH VOL II IOZ ICC Ci TEST CONDITIONS VCC = 3.135 V, VCC = 3.135 V VCC = 3.135 V VCC = 3.6 V, VCC = 3.6 V, VCC = 3.6 3 6 V, V VI = VCC or GND II = –18 mA IOH = –12 mA MIN TA = 25°C TYP† MAX MIN TYP† –1.2 MAX UNIT –1.2 V REFCLK 2.5 2.4 IOH = – 6 mA IOH = – 6 mA PCICLK 2.5 2.4 CPUCLK 2.5 2.4 IOH = –12 mA 1Yn 2.5 2.4 12 mA IOH = –12 2Yn 25 2.5 IOL = 12 mA IOL = 6 mA REFCLK 0.4 0.5 PCICLK 0.4 0.5 IOL = 6 mA IOL = 12 mA CPUCLK 0.4 0.5 1Yn 0.4 0.5 IOL = 12 mA 2Yn 04 0.4 05 0.5 ±1 ±1 µA ±1 ±1 µA VI = VCC or GND VO = 3 V or 0 IO = 0 0, V 24 2.4 Outputs high 1 Outputs low 1 Outputs disabled 1 VI = 3.135 V or 0 VI = 3.135 V or 0 Co † All typical values are at VCC = 3.3 V, TA = 25_C. V mA 6 pF 6 pF timing requirements over recommended ranges of supply voltage and operating free-air temperature MIN Stabilization time‡ MAX After SEL1, SEL0 5 After power up 5 UNIT ms ‡ Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at X1. Until phase lock is obtained, the specifications for propagation delay and skew parameters given in the switching characteristics table are not applicable. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 CDC913 PC MOTHERBOARD CLOCK GENERATOR WITH DUAL 1-TO-4 BUFFERS AND 3-STATE OUTPUTS SCAS502C – APRIL 1995 – REVISED MAY 1996 switching characteristics (see Figures 1 and 2) PARAMETER tPLH tPHL FROM (INPUT) TO (OUTPUT) 1A 1Yn 2A 2Yn 1A 2A tPZH OE tPZL OE tPHZ OE tPLZ OE Jitter(pk-pk) (pk pk)† MIN TYP MAX MIN MAX 1.5 3.5 1.2 3.8 1.5 3.5 1.2 3.8 1Yn 1.5 3.5 1.2 3.8 2Yn 1.5 3.5 1.2 3.8 1Yn 2.5 7 2 7.5 2Yn 2.5 7 2 7.5 1Yn 2.5 7 2 7.5 2Yn 2.5 7 2 7.5 1Yn 2.5 7 2 7.5 2Yn 2.5 7 2 7.5 1Yn 2.5 7 2 7.5 2Yn 2.5 7 2 7.5 350 350 2Yn 350 350 Any Y 500 500 1 1 1Yn and 2Yn CPUCLK ±250 PCICLK ±350 D t ccycle Duty cle† CPUCLK SEL0 = L, SEL1 = L 20 SEL0 = H, SEL1 = L 16.7 SEL0 = L, SEL1 = H 15 ns ns ns ns ns ns ps ns pss ns CPUCLK 45% 55% PCICLK 45% 55% tr‡ tf‡ † Specifications are applicable only after the PLL stabilization time has elapsed. ‡ Rise and fall times are characterized using the load circuits shown in Figure 1. 6 UNIT 30 PCICLK tc(period)† VCC = 3.135 V to 3.6 V, TA = 0°C to 70°C 1Yn tsk(o) ( ) tsk(p) VCC = 3.3 V, TA = 25°C POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2 ns 2 ns CDC913 PC MOTHERBOARD CLOCK GENERATOR WITH DUAL 1-TO-4 BUFFERS AND 3-STATE OUTPUTS SCAS502C – APRIL 1995 – REVISED MAY 1996 PARAMETER MEASUREMENT INFORMATION VCC S1 500 Ω From Output Under Test TEST tPLH /tPHL tPLZ /tPZL tPHZ /tPZH Open GND CL = 15 pF (see Note A) S1 Open 2X VCC GND 500 Ω LOAD CIRCUIT 3V 3V Input Output Control (low-level enabling) 1.5 V 1.5 V 1.5 V 0V 0V tPZL 1.5 V tPLH tPHL tPLZ 2.4 V VCC Output Waveform 1 S1 at VCC (see Note B) Output Waveform 2 S1 at GND (see Note B) 1.5 V tPZH VOL + 0.3 V Output VOL tr tPHZ VOH – 0.3 V 1.5 V 0.4 V 1.5 V VOH 2.4 V 0.4 V VOL tf VOLTAGE WAVEFORMS VOH ≈0V VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 CDC913 PC MOTHERBOARD CLOCK GENERATOR WITH DUAL 1-TO-4 BUFFERS AND 3-STATE OUTPUTS SCAS502C – APRIL 1995 – REVISED MAY 1996 PARAMETER MEASUREMENT INFORMATION 1A, 2A 1Y1 tPLH1 tPHL1 tPLH2 tPHL2 tPLH3 tPHL3 tPLH4 tPHL4 tPLH5 tPHL5 tPLH6 tPHL6 tPLH7 tPHL7 tPLH8 tPHL8 1Y2 1Y3 1Y4 2Y1 2Y2 2Y3 2Y4 NOTE A: Output skew, tsk(o), is calculated as the greater of: The difference between the fastest and slowest of tPLHn (n = 1, 2, . . . , 8). The difference between the fastest and slowest of tPHLn (n = 1, 2, . . . , 8). Pulse skew, tsk(p), is calculated as the greater of | tPLHn – tPLHn | (n = 1, 2, . . . , 8). Figure 2. Waveforms for Calculation of tsk(o) and tsk(p) 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 24-Jun-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing CDC913DW OBSOLETE SOIC DW Pins Package Eco Plan (2) Qty 24 TBD Lead/Ball Finish Call TI MSL Peak Temp (3) Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. 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