AD AD8555ACPZ-R21 Zero-drift, digitally programmable sensor signal amplifier Datasheet

Zero-Drift, Digitally Programmable
Sensor Signal Amplifier
AD8555
FUNCTIONAL BLOCK DIAGRAM
FEATURES
Very low offset voltage: 10 μV maximum over temperature
Very low input offset voltage drift: 60 nV/°C maximum
High CMRR: 96 dB minimum
Digitally programmable gain and output offset voltage
Single-wire serial interface
Open and short wire fault detection
Low-pass filtering
Stable with any capacitive load
Externally programmable output clamp voltage for driving
low voltage ADCs
LFCSP-16 and SOIC-8 packages
2.7 V to 5.5 V operation
−40°C to +125°C operation
VDD
VCLAMP
VDD
A5
VNEG
A1
R4
P3
R6
VSS
R1
VSS
VDD
VDD
P1
A3
R3
RF
VOUT
A4
VDD
A2
VPOS
P2
VSS
R2
R5
VDD
FILT/
DIGOUT
VSS
R7
P4
VSS
04598-0-001
DAC
APPLICATIONS
Automotive sensors
Pressure and position sensors
Thermocouple amplifiers
Industrial weigh scales
Precision current sensing
Strain gages
GENERAL DESCRIPTION
The AD8555 is a zero-drift, sensor signal amplifier with digitally programmable gain and output offset. Designed to easily and
accurately convert variable pressure sensor and strain bridge
outputs to a well-defined output voltage range, the AD8555 also
accurately amplifies many other differential or single-ended
sensor outputs. The AD8555 uses the ADI patented low noise
auto-zero and DigiTrim® technologies to create an incredibly
accurate and flexible signal processing solution in a very compact footprint.
Gain is digitally programmable in a wide range from 70 to 1,280
through a serial data interface. Gain adjustment can be fully
simulated in-circuit and then permanently programmed with
proven and reliable poly-fuse technology. Output offset voltage
is also digitally programmable and is ratiometric to the supply
voltage.
VSS
Figure 1.
In addition to extremely low input offset voltage and input offset voltage drift and very high dc and ac CMRR, the AD8555
also includes a pull-up current source at the input pins and a
pull-down current source at the VCLAMP pin. This allows
open wire and shorted wire fault detection. A low-pass filter
function is implemented via a single low cost external capacitor.
Output clamping set via an external reference voltage allows the
AD8555 to drive lower voltage ADCs safely and accurately.
When used in conjunction with an ADC referenced to the same
supply, the system accuracy becomes immune to normal supply
voltage variations. Output offset voltage can be adjusted with a
resolution of better than 0.4% of the difference between VDD
and VSS. A lockout trim after gain and offset adjustment further ensures field reliability.
The AD8555 is fully specified over the extended industrial temperature range of −40°C to +125°C. Operating from single-supply
voltages of 2.7 V to 5.5 V, the AD8555 is offered in the narrow
8-lead SOIC package and the 4 mm × 4 mm 16-lead LFCSP.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703©2004–2009 Analog Devices, Inc. All rights reserved.
AD8555
TABLE OF CONTENTS
Electrical Specifications ................................................................... 3
Device Programming ................................................................. 19
Absolute Maximum Ratings ............................................................ 7
Filtering Function....................................................................... 25
Pin Configurations and Function Descriptions ........................... 8
Driving Capacitive Loads .......................................................... 25
Typical Performance Characteristics ............................................. 9
RF Interference ........................................................................... 26
Theory of Operation ...................................................................... 17
Single-Supply Data Acquisition System .................................. 26
Gain Values.................................................................................. 18
Using the AD8555 with Capacitive Sensors ........................... 27
Open Wire Fault Detection ....................................................... 19
Outline Dimensions ....................................................................... 28
Shorted Wire Fault Detection ................................................... 19
Ordering Guide .......................................................................... 28
Floating VPOS, VNEG, or VCLAMP Fault Detection ......... 19
REVISION HISTORY
6/09—Rev. 0 to Rev A
Changes to General Description .................................................... 1
Changes to Figure 3 and Table 5 ..................................................... 8
Updated Outline Dimensions ....................................................... 28
Changes to Ordering Guide .......................................................... 28
4/04—Revision 0: Initial Version
Rev. A | Page 2 of 28
AD8555
ELECTRICAL SPECIFICATIONS
At VDD = 5.0 V, VSS = 0.0 V, VCM = 2.5 V, VO = 2.5 V, −40°C ≤ TA ≤ +125°C, unless otherwise specified.
Table 1.
Parameter
INPUT STAGE
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
Symbol
Conditions
VOS
TCVOS
IB
TA = 25°C
Input Offset Current
IOS
TA = 25°C
Input Voltage Range
Common-Mode Rejection Ratio
CMRR
VCM = 0.9 V to 3.6 V, AV = 70
VCM = 0.9 V to 3.6 V, AV = 1,280
VO = 0.2 V to 3.4 V
VO = 0.2 V to 4.8 V
Second Stage Gain = 17.5 to 100
Second Stage Gain = 140 to 200
Second Stage Gain = 17.5 to 100
Second Stage Gain = 140 to 200
Linearity
Differential Gain Accuracy
Differential Gain Temperature Coefficient
RF
RF Temperature Coefficient
DAC
Accuracy
Ratiometricity
Output Offset
Temperature Coefficient
VCLAMP
Input Bias Current
Input Voltage Range
OUTPUT BUFFER STAGE
Buffer Offset
Short-Circuit Current
Output Voltage, Low
Output Voltage, High
POWER SUPPLY
Supply Current
Power Supply Rejection Ratio
DYNAMIC PERFORMANCE
Gain Bandwidth Product
Output Buffer Slew Rate
Settling Time
NOISE PERFORMANCE
Input Referred Noise
Low Frequency Noise
Total Harmonic Distortion
Min
Typ
Max
Unit
12
2
25
16
10
65
22
25
1
1.5
3.8
μV
nV/°C
nA
nA
nA
nA
V
dB
dB
ppm
ppm
%
%
ppm/°C
ppm/°C
0.2
0.6
80
96
14
92
112
20
1000
0.35
0.5
15
40
18
700
22
kΩ
ppm/°C
AV = 70, Offset Codes = 8 to 248
AV = 70, Offset Codes = 8 to 248
AV = 70, Offset Codes = 8 to 248
0.7
50
5
3.3
0.8
35
15
%
ppm
mV
ppm FS/°C
TA = 25°C, VCLAMP = 5 V
200
500
4.94
nA
nA
V
1.25
ISC
VOL
VOH
ISY
PSRR
1.6
2.5
40
100
7
15
10
30
mV
mA
mV
V
2.0
2.5
mA
5
RL = 10 kΩ to 5 V
RL = 10 kΩ to 0 V
VO = 2.5 V, VPOS = VNEG = 2.5V,
VDAC Code = 128
AV = 70
4.94
125
dB
SR
ts
First Gain Stage, TA = 25°C
Second Gain Stage, TA = 25°C
Output Buffer Stage
AV = 70, RL = 10 kΩ, C L = 100 pF
To 0.1%, AV = 70, 4 V Output Step
2
8
1.5
1.2
8
MHz
MHz
MHz
V/μs
μs
en p-p
THD
TA = 25°C, f = 1 kHz
f = 0.1 Hz to 10 Hz
VIN = 16.75 mV rms, f = 1 kHz, AV = 100
32
0.5
−100
nV/√Hz
μV p-p
dB
GBP
Rev. A | Page 3 of 28
109
AD8555
Parameter
DIGITAL INTERFACE
Input Current
DIGIN Pulse Width to Load 0
DIGIN Pulse Width to Load 1
Time between Pulses at DIGIN
DIGIN Low
DIGIN High
DIGOUT Logic 0
DIGOUT Logic 1
Symbol
Conditions
Min
tw0
tw1
tws
TA = 25°C
TA = 25°C
TA = 25°C
TA = 25°C
TA = 25°C
TA = 25°C
TA = 25°C
0.05
50
10
Typ
Max
2
Rev. A | Page 4 of 28
10
1
4
1
4
Unit
μA
μs
μs
μs
V
V
V
V
AD8555
At VDD = 2.7 V, VSS = 0.0 V, VCM = 1.35 V, VO = 1.35 V, −40°C ≤ TA ≤ +125°C, unless otherwise specified.
Table 2.
Parameter
INPUT STAGE
Input Offset Voltage
Input Offset Voltage Drift
Input Bias Current
Input Offset Current
Input Voltage Range
Common-Mode Rejection Ratio
Symbol
VOS
TCVOS
IB
IOS
CMRR
Linearity
Differential Gain Accuracy
Differential Gain Temperature Coefficient
RF
RF Temperature Coefficient
DAC
Accuracy
Ratiometricity
Output Offset
Temperature Coefficient
VCLAMP
Input Bias Current
Input Voltage Range
OUTPUT BUFFER STAGE
Buffer Offset
Short-Circuit Current
Output Voltage, Low
Output Voltage, High
POWER SUPPLY
Supply Current
Power Supply Rejection Ratio
DYNAMIC PERFORMANCE
Gain Bandwidth Product
Output Buffer Slew Rate
Settling Time
NOISE PERFORMANCE
Input Referred Noise
Low Frequency Noise
Total Harmonic Distortion
Conditions
TA = 25°C
TA = 25°C
VCM = 0.9 V to 1.3 V, AV = 70
VCM = 0.9 V to 1.3 V, AV = 1,280
VO = 0.2 V to 3.4 V
VO = 0.2 V to 4.8 V
Second Stage Gain = 17.5 to 100
Second Stage Gain = 140 to 200
Second Stage Gain = 17.5 to 100
Second Stage Gain = 140 to 200
Min
12
0.5
80
96
14
Typ
Max
Unit
2
25
16
0.2
10
60
μV
nV/°C
nA
nA
nA
V
dB
dB
ppm
ppm
%
%
ppm/°C
92
112
20
1000
0.35
0.5
15
40
18
700
AV = 70, Offset Codes = 8 to 248
AV = 70, Offset Codes = 8 to 248
AV = 70, Offset Codes = 8 to 248
0.7
50
5
3.3
TA = 25°C, VCLAMP = 2.7 V
200
500
1.25
4.5
RL = 10 kΩ to 5 V
RL = 10 kΩ to 0 V
ppm/°C
22
35
2.64
7
ISC
VOL
VOH
1
1.5
1.6
2.64
15
9.5
30
kΩ
ppm/°C
%
ppm
mV
ppm FS/°C
nA
nA
V
mV
mA
mV
V
2.0
mA
125
dB
SR
ts
First Gain Stage, TA = 25°C
Second Gain Stage, TA = 25°C
Output Buffer Stage
AV = 70, RL = 10 kΩ, CL = 100 pF
To 0.1%, AV = 70, 4 V Output Step
2
8
1.5
1.2
8
MHz
MHz
MHz
V/μs
μs
en p-p
THD
TA = 25°C, f = 1 kHz
f = 0.1 Hz to 10 Hz
VIN = 16.75 mV rms, f = 1 kHz, AV = 100
32
0.3
−100
nV/√Hz
μV p-p
dB
ISY
PSRR
GBP
VO = 1.35 V, VPOS = VNEG = 1.35 V,
VDAC Code = 128
AV = 70
Rev. A | Page 5 of 28
109
AD8555
Parameter
DIGITAL INTERFACE
Input Current
DIGIN Pulse Width to Load 0
DIGIN Pulse Width to Load 1
Time between Pulses at DIGIN
Symbol
Conditions
Min
tw0
tw1
tws
TA = 25°C
TA = 25°C
TA = 25°C
0.05
50
10
Typ
Max
2
Rev. A | Page 6 of 28
10
Unit
μA
μs
μs
μs
AD8555
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Supply Voltage
Input Voltage
Differential Input Voltage 1
Output Short-Circuit
Duration to VSS or VDD
Storage Temperature Range
Operating Temperature Range
Junction Temperature Range
Lead Temperature Range
(Soldering, 10 sec)
Table 4.
Rating
6V
VSS − 0.3 V to VDD + 0.3 V
±5.0 V
Indefinite
−65°C to +150°C
−40°C to +125°C
−65°C to +150°C
300°C
Package Type
8-Lead SOIC (R)
16-Lead LFCSP (CP)
1
2
θJA 2
158
44
θJC
43
31.5
Unit
°C/W
°C/W
Differential input voltage is limited to ±5.0 V or ± the supply voltage, whichever is less.
θJA is specified for the worst-case conditions, i.e., θJA is specified for device
soldered in circuit board for SOIC and LFCSP packages.
Rev. A | Page 7 of 28
AD8555
Figure 2. 8-Lead SOIC (Not Drawn to Scale)
13 DVSS
14 AVSS
AD8555
TOP VIEW
12 VOUT
11
NC
10 VCLAMP
9
NC 5
DIGIN 4
PIN 1
INDICATOR
NC
NOTES
1. NC = NO CONNECT.
2. THE EXPOSED PAD MUST BE CONNECTED
TO AVSS (PIN 14).
04598-0-050
NC 1
FILT/DIGOUT 2
NC 3
VPOS 8
VOUT
TOP VIEW
DIGIN 3 (Not to Scale) 6 VCLAMP
5 VPOS
VNEG 4
15 DVDD
VSS
7
VNEG 6
NC 7
8
AD8555
04598-0-049
VDD 1
FILT/DIGOUT 2
16 AVDD
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 3. 16-Lead LFCSP (Not Drawn to Scale)
Table 5. Pin Configuration
Pin No.
N/A
1
2
SOIC
Mnemonic
LFCSP
Mnemonic
EPAD
N/A
FILTDIGOUT
VDD
FILT/DIGOUT
Pin No.
0
N/A
2
3
4
5
6
7
DIGIN
VNEG
VPOS
VCLAMP
VOUT
4
6
8
10
12
DIGIN
VNEG
VPOS
VCLAMP
VOUT
8
N/A
N/A
N/A
VSS
N/A
N/A
N/A
N/A
13, 14
15, 16
1, 3, 5, 7, 9, 11
N/A
DVSS, AVSS
DVDD, AVDD
NC
Description
Exposed Pad. The exposed pad must be connected to AVSS (Pin 14)
Positive Supply Voltage.
Unbuffered Amplifier Output In Series with a Resistor RF. Adding a capacitor
between FILT and VDD or VSS implements a low-pass filtering function. In
read mode, this pin functions as a digital output.
Digital Input.
Negative Amplifier Input (Inverting Input).
Positive Amplifier Input (Noninverting Input).
Set Clamp Voltage at Output.
Buffered Amplifier Output. Buffered version of the signal at the FILT/DIGOUT
pin. In read mode, VOUT is a buffered digital output.
Negative Supply Voltage.
Negative Supply Voltage.
Positive Supply Voltage.
Do Not Connect.
Rev. A | Page 8 of 28
AD8555
TYPICAL PERFORMANCE CHARACTERISTICS
40
VS = 5V
NUMBER OF AMPLIFIERS
NUMBER OF AMPLIFIERS
VS = 5V
35
40
30
20
10
30
25
20
15
10
–9
–6
–3
0
VOS (μV)
3
6
9
0
0
12.5
25.0
Figure 4. Input Offset Voltage Distribution
50
0.5
45
0
40
NUMBER OF AMPLIFIERS
1.0
–1.0
75.0
–1.5
–2.0
–2.5
–3.0
–3.5
62.5
75.0
35
30
25
20
15
10
0.5
1.0
1.5
2.0
2.5
VCM (V)
3.0
3.5
4.0
4.5
0
0
12.5
Figure 5. Input Offset Voltage vs. Common-Mode Voltage
25.0
37.5
50.0
TCVOS (nV/°C)
04598-0-007
0
04598-0-061
5
–4.0
Figure 8. TCVOS @ VS = 2.7 V
10
10.0
8
VS = 5V
7.5
6
5.0
4
BUF VOS (mV)
2
0
–2
2.5
VOUT = 0.3V
0
–2.5
VOUT = 4.7V
–4
–5.0
–6
–7.5
–10
–50
–25
0
25
50
75
TEMPERATURE (°C)
100
125
150
04598-0-062
–8
Figure 6. Input Offset Voltage vs. Temperature
–10.0
–50
–25
0
25
50
75
TEMPERATURE (°C)
100
125
Figure 9. Output Buffer Offset vs. Temperature
Rev. A | Page 9 of 28
150
04598-0-008
VOS (μV)
62.5
Figure 7. TCVOS @ VS = 5 V
–0.5
INPUT OFFSET VOLTAGE (μV)
37.5
50.0
TCVOS (nV/°C)
04598-0-006
0
04598-0-005
5
AD8555
2.5
10
1
–75
–25
25
75
TEMPERATURE (°C)
125
175
2.0
1.5
1.0
0.5
0
0
Figure 10. Input Bias Current at VPOS, VNEG vs. Temperature
100
VS = 5.5V
1
2
3
4
DIGITAL INPUT VOLTAGE (V)
5
6
04598-0-011
DIGITAL INPUT CURRENT (μA)
VS = 5V
04598-0-009
IB (nA)
100
Figure 13. Digital Input Current vs. Digital Input Voltage (Pin 3)
1000
VS = 5V
VS = 5V
1
0
1
2
3
4
5
VCM (V)
Figure 11. Input Bias Current at VPOS, VNEG vs. Common-Mode Voltage
+25°C
–40°C
100
10
0
1
2
3
4
VCLAMP VOLTAGE (V)
5
6
04598-0-012
CLAMP CURRENT (nA)
10
04598-0-010
IB (nA)
+125°C
Figure 14. VCLAMP Current Over Temperature at VS = 5 V vs. VCLAMP Voltage
0.5
1000
VS = 2.7V
0.4
0.3
CLAMP CURRENT (nA)
0.2
0
–0.1
–0.2
+125
+25
–40
100
–0.3
–0.5
–50
–25
0
25
50
75
TEMPERATURE (°C)
100
125
Figure 12. Input Offset Current vs. Temperature
150
10
0
1
VCLAMP VOLTAGE (V)
2
2.7
04598-0-013
–0.4
04598-0-063
IOS (nA)
0.1
Figure 15. VCLAMP Current Over Temperature at VS = 2.7 vs. VCLAMP Voltage
Rev. A | Page 10 of 28
AD8555
3
VS = ±2.5V
GAIN = 1280
CMRR (dB)
80
1
0
0
1
2
3
4
SUPPLY VOLTAGE (V)
5
6
0
100
1k
Figure 16. Supply Current (ISY) vs. Supply Voltage
10k
FREQUENCY (Hz)
100k
1M
04598-0-017
40
04598-0-014
SUPPLY CURRENT (mA)
120
2
Figure 19. CMRR vs. Frequency
3.0
VS = 5V
145
135
2.5
125 1280
2.7V
2.0
CMRR (dB)
SUPPLY CURRENT (mA)
5V
1.5
115
800
400
200
105
100
70
95
1.0
–25
0
25
50
75
TEMPERATURE (°C)
100
125
150
75
–75
Figure 17. Supply Current (ISY) vs. Temperature
–50
–25
0
25
50
75
TEMPERATURE (°C)
VOLTAGE NOISE DENSITY (nV/ Hz)
40
100k
Figure 18. CMRR vs. Frequency
1M
04598-0-016
CMRR (dB)
80
10k
FREQUENCY (Hz)
150
VS = ±2.5V
GAIN = 70
120
1k
125
Figure 20. CMRR vs. Temperature at Different Gains
VS = ±2.5V
GAIN = 70
0
100
100
60
50
40
30
20
10
0
5
FREQUENCY (kHz)
10
04598-0-019
–50
04598-0-015
0.5
–75
04598-0-018
85
Figure 21. Input Voltage Noise Density vs. Frequency (0 Hz to 10 kHz)
Rev. A | Page 11 of 28
AD8555
VS = ±2.5V
CL = 40PF
GAIN = 1280
60
CLOSED-LOOP GAIN (dB)
35
30
25
20
15
40
GAIN = 70
20
0
10
04598-0-025
VOLTAGE NOISE DENSITY (nV/ Hz)
VS = ±2.5V
GAIN = 70
5
0
250
FREQUENCY (kHz)
500
04598-0-021
1k
10k
100k
FREQUENCY (Hz)
1M
Figure 25. Closed-Loop Gain vs. Frequency Measured at Filter Pin
Figure 22. Input Voltage Noise Density vs. Frequency (0 Hz to 500 kHz)
VS = ±2.5V
VS = ±2.5V
GAIN = 1000
0.6
GAIN = 1280
CLOSED-LOOP GAIN (dB)
60
0.2
0
–0.2
–0.4
40
GAIN = 70
20
0
TIME (1s/DIV)
1k
10k
100k
FREQUENCY (Hz)
04598-0-026
–0.6
04598-0-023
1M
Figure 26. Closed-Loop Gain vs. Frequency Measured at Output Pin
Figure 23. Low Frequency Input Voltage Noise (0.1 Hz to 10 Hz)
VS = ±2.5V
8
4
GAIN (dB)
0
–4
–8
1k
10k
100k
FREQUENCY (Hz)
1M
Figure 27. Output Buffer Gain vs. Frequency
Figure 24. Low Frequency Input Voltage Noise (0.1 Hz to 10 Hz)
Rev. A | Page 12 of 28
10M
04598-0-027
NOISE (μV)
0.4
AD8555
60
15
VS = ±2.5V
RS
12
RS = 0
SINK 5V
50
OVERSHOOT (%)
OUTPUT SHORT CIRCUIT (mA)
CL = 1nF
OUTPUT
BUFFER
40
30
RS = 10
20
RS = 20
RS = 50
10
9
SINK 2.7V
6
3
0
–3
–6
SOURCE 5V
–9
SOURCE 2.7V
100.0
–15
–75
Figure 28. Output Buffer Positive Overshoot
60
–25
0
25
50
75
100
TEMPERATURE (°C)
125
175
Figure 31. Output Short Circuit vs. Temperature
SUPPLY VOLTAGE
RS
RS = 0
CL
4
40
30
VOLTAGE
2
RS = 10
0
3
20
RS = 20
2
10
1.0
10.0
LOAD CAPACITANCE (nF)
100.0
0
04598-0-029
0
0.1
RS = 50
RS = 100
TIME (100μs/DIV)
Figure 29. Output Buffer Negative Overshoot
1.000
Figure 32. Power-On Response at 25°C
VS = ±2.5V
6
SOURCE
VOLTAGE (1V/DIV)
0.100
04598-0-032
1
VOUT
SINK
0.010
SUPPLY VOLTAGE
5
4
3
2
VOUT
0.001
0.01
0.10
1.00
LOAD CURRENT (mA)
10.0
Figure 30. Output Voltage to Supply Rail vs. Load Current
0
TIME (100μs/DIV)
Figure 33. Power-On Response at 125°C
Rev. A | Page 13 of 28
04598-0-033
1
04598-0-030
VDD – OUTPUT VOLTAGE (V)
150
VS = ±2.5V
50
OVERSHOOT (%)
–50
04598-0-031
1.0
10.0
LOAD CAPACITANCE (nF)
04598-0-028
–12
RS = 100
0
0.1
AD8555
T
VOLTAGE (1V/DIV)
6
VS = ±2.5V
GAIN = 70
CL = 0.1μF
FIN = 10kHz
SUPPLY VOLTAGE
VOUT (50mV/DIV)
5
4
3
2
2
1
TIME (100μs/DIV)
04598-0-036
04598-0-034
VOUT
0
TIME (100μs/DIV)
Figure 34. Power-On Response at −40°C
150
Figure 37. Small Signal Response
VS = 2.7V TO 5.5V
T
145
VS = ±2.5V
GAIN = 70
CL = 100pF
FIN = 1kHz
140
VOUT (50mV/DIV)
PSRR (dB)
135
130
125
120
115
2
110
–50
–25
0
25
50
75
TEMPERATURE (°C)
100
125
150
04598-0-037
100
–75
04598-0-035
105
TIME (100μs/DIV)
Figure 35. PSRR vs. Temperature
Figure 38. Small Signal Response
140
T
VS = ±2.5V
GAIN = 70
CL = 100pF
120
VOUT (1V/DIV)
80
60
2
40
0
0.01
0.1
1
FREQUENCY (kHz)
10
100
Figure 36. PSRR vs. Frequency
TIME (10μs/DIV)
Figure 39. Large Signal Response
Rev. A | Page 14 of 28
04598-0-038
20
04598-0-068
PSRR (dB)
100
AD8555
VOUT (1V/DIV)
T
VS = ±2.5V
GAIN = 70
CL = 0.05μF
VIN
0V
2
VOUT
04598-0-039
04598-0-070
0V
TIME (10μs/DIV)
Figure 40. Large Signal Response
1k
Figure 43. Positive Overload Recovery (Gain = 70)
VSY = ±2.5V
AV = 70
0V
VIN
IMPEDANCE (Ω)
100
0V
10
1
10
100
FREQUENCY (kHz)
04598-0-046
1
0.1
04598-0-071
–2.5V
1M
Figure 41. Output Impedance vs. Frequency
Figure 44. Negative Overload Recovery (Gain = 1280)
0V
VIN
0V
VIN
0V
VOUT
VOUT
04598-0-069
04598-0-072
0V
Figure 45. Positive Overload Recovery (Gain = 1280)
Figure 42. Negative Overload Recovery (Gain = 70)
Rev. A | Page 15 of 28
AD8555
1.00
GAIN = 70
OFFSET = 128
VS = ±2.5V
0.20
294Ω
0.1μF
1
6
7
AD8555
5
8
0.05
0.1μF
–V
1kΩ
10kΩ
10kΩ
0.02
OUT
0.01
20
Figure 46. Settling Time 0.1%
+V
4
294Ω
0.1μF
1
6
5
8
10kΩ
7
AD8555
0.1μF
–V
1kΩ
10kΩ
OUT
04598-0-074
20.5Ω
50
100
200
500
1k
2k
FREQUENCY (Hz)
Figure 48. THD vs. Frequency
GAIN = 70
OFFSET = 128
VS = ±2.5V
4V pp
0.10
Figure 47. Settling Time 0.01%
Rev. A | Page 16 of 28
5k
10k
20k
04598-0-075
4
04598-0-073
20.5Ω
THD (%)
+V
4V pp
VS = ±2.5V
0.50
AD8555
THEORY OF OPERATION
VDD. The input to A5, VCLAMP, has a very high input resistance. It should be connected to a known voltage and not left
floating. However, the high input impedance allows the clamp
voltage to be set using a high impedance source, e.g., a potential
divider. If the maximum value of VOUT does not need to be
limited, VCLAMP should be connected to VDD.
A1, A2, R1, R2, R3, P1, and P2 form the first gain stage of the
differential amplifier. A1 and A2 are auto-zeroed op amps that
minimize input offset errors. P1 and P2 are digital potentiometers, guaranteed to be monotonic. Programming P1 and P2
allows the first stage gain to be varied from 4.0 to 6.4 with 7-bit
resolution (see Table 6 and Equation 3), giving a fine gain
adjustment resolution of 0.37%. R1, R2, R3, P1, and P2 each
have a similar temperature coefficient, so the first stage gain
temperature coefficient is lower than 100 ppm/°C.
A4 implements a rail-to-rail input and output unity-gain voltage buffer. The output stage of A4 is supplied from a buffered
version of VCLAMP instead of VDD, allowing the positive
swing to be limited. The maximum output current is limited
between 5 mA to 10 mA.
A3, R4, R5, R6, R7, P3, and P4 form the second gain stage of the
differential amplifier. A3 is also an auto-zeroed op amp that
minimize input offset errors. P3 and P4 are digital potentiometers, allowing the second stage gain to be varied from 17.5 to
200 in eight steps (see Table 7); they allow the gain to be varied
over a wide range. R4, R5, R6, R7, P3, and P4 each have a similar temperature coefficient, so the second stage gain temperature coefficient is lower than 100 ppm/°C.
An 8-bit digital-to-analog converter (DAC) is used to generate a
variable offset for the amplifier output. This DAC is guaranteed
to be monotonic. To preserve the ratiometric nature of the input
signal, the DAC references are driven from VSS and VDD, and
the DAC output can swing from VSS (Code 0) to VDD (Code
255). The 8-bit resolution is equivalent to 0.39% of the difference between VDD and VSS, e.g., 19.5 mV with a 5 V supply.
The DAC output voltage (VDAC) is given approximately by
RF together with an external capacitor connected between
FILT/DIGOUT and VSS or VDD form a low-pass filter. The
filtered signal is buffered by A4 to give a low impedance output
at VOUT. RF is nominally 16 kΩ, allowing a 1 kHz low-pass
filter to be implemented by connecting a 10 nF external
capacitor between FILT/DIGOUT and VSS or between
FILT/DIGOUT and VDD. If low-pass filtering is not needed,
then the FILT/DIGOUT pin must be left floating.
⎛ Code + 0.5 ⎞
VDAC ≈ ⎜
⎟(VDD − VSS ) + VSS
⎝ 256
⎠
The temperature coefficient of VDAC is lower than
200 ppm/°C.
The amplifier output voltage (VOUT) is given by
A5 implements a voltage buffer, which provides the positive
supply to the amplifier output buffer A4. Its function is to limit
VOUT to a maximum value, useful for driving analog-to-digital
converters (ADC) operating on supply voltages lower than
VOUT = GAIN (VPOS − VNEG ) + VDAC
VCLAMP
VDD
A5
A1
R4
P3
R6
VSS
R1
VSS
VDD
VDD
P1
A3
R3
RF
VOUT
A4
VDD
A2
VPOS
P2
VSS
R2
R5
VDD
(2)
where GAIN is the product of the first and second stage gains.
VDD
VNEG
(1)
FILT/
DIGOUT
VSS
R7
P4
VSS
04598-0-001
DAC
VSS
Figure 49. AD8555 Functional Schematic
Rev. A | Page 17 of 28
AD8555
GAIN VALUES
Table 6. First Stage Gain vs. Gain Code
First Stage
Gain Code
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
First Stage Gain
4.000
4.015
4.030
4.045
4.060
4.075
4.090
4.105
4.120
4.135
4.151
4.166
4.182
4.197
4.213
4.228
4.244
4.260
4.276
4.291
4.307
4.323
4.339
4.355
4.372
4.388
4.404
4.420
4.437
4.453
4.470
4.486
⎛ Code ⎞
⎜
⎟
127 ⎠
6.4 ⎞ ⎝
GAIN1 ≈ 4 × ⎛⎜
⎟
⎝ 4 ⎠
First Stage
Gain Code
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
First Stage Gain
4.503
4.520
4.536
4.553
4.570
4.587
4.604
4.621
4.638
4.655
4.673
4.690
4.707
4.725
4.742
4.760
4.778
4.795
4.813
4.831
4.849
4.867
4.885
4.903
4.921
4.939
4.958
4.976
4.995
5.013
5.032
5.050
First Stage
Gain Code
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
First Stage Gain
5.069
5.088
5.107
5.126
5.145
5.164
5.183
5.202
5.221
5.241
5.260
5.280
5.299
5.319
5.339
5.358
5.378
5.398
5.418
5.438
5.458
5.479
5.499
5.519
5.540
5.560
5.581
5.602
5.622
5.643
5.664
5.685
First Stage
Gain Code
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
First Stage Gain
5.706
5.727
5.749
5.770
5.791
5.813
5.834
5.856
5.878
5.900
5.921
5.943
5.965
5.988
6.010
6.032
6.054
6.077
6.099
6.122
6.145
6.167
6.190
6.213
6.236
6.259
6.283
6.306
6.329
6.353
6.376
6.400
Table 7. Second Stage Gain and Gain Ranges vs. Gain Code
(3)
Second
Stage Gain
Code
0
1
2
3
4
5
6
7
Rev. A | Page 18 of 28
Second
Stage
Gain
17.5
25
35
50
70
100
140
200
Minimum
Combined
Gain
70
100
140
200
280
400
560
800
Maximum
Combined
Gain
112
160
224
320
448
640
896
1280
AD8555
OPEN WIRE FAULT DETECTION
The inputs to A1 and A2, VNEG and VPOS, each have a comparator to detect whether VNEG or VPOS exceeds a threshold
voltage, nominally VDD − 1.1 V. If (VNEG > VDD − 1.1 V) or
(VPOS > VDD − 1.1 V), VOUT is clamped to VSS. The output
current limit circuit is disabled in this mode, but the maximum
sink current is approximately 50 mA when VDD = 5 V. The
inputs to A1 and A2, VNEG and VPOS, are also pulled up to
VDD by currents IP1 and IP2. These are both nominally 18 nA
and matched to within 5 nA. If the inputs to A1 or A2 are accidentally left floating, e.g., an open wire fault, IP1 and IP2 pull
them to VDD, which would cause VOUT to swing to VSS, allowing this fault to be detected. It is not possible to disable IP1
and IP2, nor the clamping of VOUT to VSS, when VNEG or
VPOS approaches VDD.
FLOATING VPOS, VNEG, OR VCLAMP FAULT
DETECTION
A floating fault condition at the VPOS, VNEG, or VCLAMP
pins is detected by using a low current to pull a floating input
into an error voltage range, which is defined in the previous
section. In this way, the VOUT pin is shorted to VSS when a
floating input is detected. Table 9 lists the currents used.
Table 9. Floating Fault Detection at VPOS, VNEG, and
VCLAMP
Pin
VPOS
VNEG
VCLAMP
Typical Current
16 nA pull-up
16 nA pull-up
0.2 μA pull-down
Goal of Current
Pull VPOS above VINH
Pull VNEG above VINH
Pull VCLAMP below VCLL
DEVICE PROGRAMMING
SHORTED WIRE FAULT DETECTION
Digital Interface
The AD8555 provides fault detection, in the case where VPOS,
VNEG, or VCLAMP shorts to VDD and VSS. Figure 50 shows
the voltage regions at VPOS, VNEG, and VCLAMP that trigger
an error condition. When an error condition occurs, the VOUT
pin is shorted to VSS. Table 8 lists the voltage levels shown in
Figure 50.
The digital interface allows the first stage gain, second stage
gain, and output offset to be adjusted and allows desired values
for these parameters to be permanently stored by selectively
blowing polysilicon fuses. To minimize pin count and board
space, a single-wire digital interface is used. The digital input
pin, DIGIN, has hysteresis to minimize the possibility of inadvertent triggering with slow signals. It also has a pull-down
current sink to allow it to be left floating when programming is
not being performed. The pull-down ensures inactive status of
the digital input by forcing a dc low voltage on DIGIN.
VPOS
VCLAMP
VNEG
VDD
VDD
VDD
ERROR
ERROR
VINH
VINH
NORMAL
NORMAL
VCLL
VINL
VSS
ERROR
ERROR
VINL
VSS
ERROR
VSS
04598-0-002
NORMAL
Figure 50. Voltage Regions at VPOS, VNEG, and VCLAMP
That Trigger a Fault Condition
Table 8. Typical VINL, VINH, and VCLL Values (VDD = 5 V)
Voltage
VINH
Typical Min
3.9 V
Typical Max
4.2 V
VINL
0.195 V
0.55 V
VCLL
1V
1.2 V
Purpose
Short to VDD
Fault Detection
Short to VSS
Fault Detection
Short to VSS
Fault Detection
A short pulse at DIGIN from low to high and back to low again,
e.g., between 50 ns and 10 μs long, loads a 0 into a shift register.
A long pulse at DIGIN, e.g., 50 μs or longer, loads a 1 into the
shift register. The time between pulses should be at least 10 μs.
Assuming VSS = 0 V, voltages at DIGIN between VSS and 0.2 ×
VDD are recognized as a low, and voltages at DIGIN between
0.8 × VDD and VDD are recognized as a high. A timing diagram example showing the waveform for entering code 010011
into the shift register is shown in Figure 51.
Rev. A | Page 19 of 28
AD8555
tW1
tWS
tWS
tWS
tW0
tW1
tW0
tW0
tWS
tWS
tW1
CODE
0
1
0
0
1
1
04598-0-003
WAVEFORM
Figure 51. Timing Diagram for Code 010011
Table 10. Timing Specifications
Timing Parameter
tw0
tw1
tws
Description
Pulse Width for Loading 0 into Shift Register
Pulse Width for Loading 1 into Shift Register
Width between Pulses
Specification
Between 50 ns and 10 μs
≥50 μs
≥10 μs
Table 11. 38-Bit Serial Word Format
Field No.
Field 0
Field 1
Bits
Bits 0 to 11
Bits 12 to 13
Field 2
Bits 14 to 15
Field 3
Field 4
Bits 16 to 17
Bits 18 to 25
Field 5
Bits 26 to 37
Description
12-Bit Start of Packet 1000 0000 0001
2-Bit Function
00: Change Sense Current
01: Simulate Parameter Value
10: Program Parameter Value
11: Read Parameter Value
2-Bit Parameter
00: Second Stage Gain Code
01: First Stage Gain Code
10: Output Offset Code
11: Other Functions
2-Bit Dummy 10
8-Bit Value
Parameter 00 (Second Stage Gain Code): 3 LSBs Used
Parameter 01 (First Stage Gain Code): 7 LSBs Used
Parameter 10 (Output Offset Code): All 8 Bits Used
Parameter 11 (Other Functions)
Bit 0 (LSB): Master Fuse
Bit 1: Fuse for Production Test at Analog Devices
Bit 2: Parity Fuse
12-Bit End of Packet 0111 1111 1110
A 38-bit serial word is used, divided into 6 fields. Assuming
each bit can be loaded in 60 μs, the 38-bit serial word transfers
in 2.3 ms. Table 11 summarizes the word format.
Fields 0 and 5 are the start of packet and end of packet field,
respectively. Matching the start of packet field with 1000 0000
0001 and the end of packet field with 0111 1111 1110 ensures
that the serial word is valid and enables decoding of the other
fields. Field 3 breaks up the data and ensures that no data combination can inadvertently trigger the start of packet and end of
packet fields. Field 0 should be written first and Field 5 written
last. Within each field, the MSB must be written first and the
LSB written last. The shift register features power-on reset to
minimize the risk of inadvertent programming; power-on reset
occurs when VDD is between 0.7 V and 2.2 V.
Rev. A | Page 20 of 28
AD8555
Initial State
Initially, all the polysilicon fuses are intact. Each parameter has
the value 0 assigned (see Table 12).
Table 12. Initial State before Programming
Second Stage Gain Code = 0
First Stage Gain Code = 0
Output Offset Code = 0
Master Fuse = 0
Second Stage Gain = 17.5
First Stage Gain = 4.0
Output Offset = VSS
Master Fuse Not Blown
When power is applied to a device, parameter values are taken
either from internal registers if the master fuse is not blown or
from the polysilicon fuses if the master fuse is blown.
Programmed values have no effect until the master fuse is
blown. The internal registers feature power-on reset so that
unprogrammed devices enter a known state after power-up;
power-on reset occurs when VDD is between 0.7 V and 2.2 V.
Simulation Mode
The simulation mode allows any parameter to be changed temporarily. These changes are retained until the simulated value is
reprogrammed, the power is removed, or the master fuse is
blown. Parameters are simulated by setting Field 1 to 01, selecting the desired parameter in Field 2, and the desired value for
the parameter in Field 4. Note that a value of 11 for Field 2 is
ignored during the simulation mode. Examples of temporary
settings follow:
• By setting the second stage gain code (Parameter 00) to 011
and the second stage gain to 50, 1000 0000 0001 01 00 10
0000 0011 0111 1111 1110 is the result.
• By setting the first stage gain code (Parameter 01) to 000 1011
and the first stage gain to 4.166, 1000 0000 0001 01 01 10
0000 1011 0111 1111 1110 is the result.
A first stage gain of 4.166 with a second stage gain of 50 gives
a total gain of 208.3. This gain has a maximum tolerance of
2.5%.
• Set the output offset code (Parameter 10) to 0100 0000 and
the output offset to 1.260 V when VDD = 5 V and VSS = 0 V.
This output offset has a maximum tolerance of 0.8%: 1000
0000 0001 01 10 10 0100 0000 0111 1111 1110.
Programming Mode
Intact fuses give a bit value of 0. Bits with a desired value of 1
need to have the associated fuse blown. Since a relatively large
current is needed to blow a fuse, only one fuse can be reliably
blown at a time. Thus, a given parameter value may need several 38-bit words to allow reliable programming. A 5.5 V supply is
required when blowing fuses to minimize the on resistance of
the internal MOS switches that blow the fuse. The power supply
must be able to deliver 250 mA of current, and at least 0.1 μF of
decoupling capacitance is needed across the power pins of the
device. A minimum period of 1 ms should be allowed for each
fuse to blow. There is no need to measure the supply current
during programming; the best way to verify correct programming is to use the read mode to read back the programmed
values and to remeasure the gain and offset to verify these
values. Programmed fuses have no effect on the gain and output
offset until the master fuse is blown; after blowing the master
fuse, the gain and output offset are determined solely by the
blown fuses and the simulation mode is permanently deactivated.
Parameters are programmed by setting Field 1 to 10, selecting
the desired parameter in Field 2, and selecting a single bit with
the value 1 in Field 4.
As an example, suppose the user wants to permanently set the
second stage gain to 50. Parameter 00 needs to have the value
0000 0011 assigned. Two bits have the value 1, so two fuses need
to be blown. Since only one fuse can be blown at a time, the
code 1000 0000 0001 10 00 10 0000 0010 0111 1111 1110 can be
used to blow one fuse. The MOS switch that blows the fuse
closes when the complete packet is recognized and opens when
the start-of-packet, dummy, or end-of-packet fields are no longer valid. After 1 ms, the second code 1000 0000 0001 10 00 10
0000 0001 0111 1111 1110 can be entered to blow the second
fuse.
To set the first stage gain permanently to a nominal value of
4.151, Parameter 01 needs to have the value 000 1011 assigned.
Three fuses need to be blown, and the following codes can be
used, with a 1 ms delay after each code:
1000 0000 0001 10 01 10 0000 1000 0111 1111 1110
1000 0000 0001 10 01 10 0000 0010 0111 1111 1110
1000 0000 0001 10 01 10 0000 0001 0111 1111 1110
To set the output offset permanently to a nominal value of
1.260 V when VDD = 5 V and VSS = 0 V, Parameter 10 needs to
have the value 0100 0000 assigned. One fuse needs to be blown,
and the following code can be used: 1000 0000 0001 10 10 10
0100 0000 0111 1111 1110.
Finally, to blow the master fuse to deactivate the simulation
mode and prevent further programming, the code 1000 0000
0001 10 11 10 0000 0001 0111 1111 1110 can be used.
There are a total of 20 programmable fuses. Since each fuse
requires 1 ms to blow, and each serial word can be loaded in
2.3 ms, the maximum time needed to program the fuses can be as
low as 66 ms.
Parity Error Detection
A parity check is used to determine whether the programmed
data of an AD8555 is valid, or whether data corruption has
occurred in the nonvolatile memory. Figure 52 shows the schematic implemented in the AD8555.
Rev. A | Page 21 of 28
AD8555
I0
IN01
VA1
IN02
VA2
IN03
VB0
IN04
VB1
IN05
VB2
IN06
VB3
IN07
VB4
IN08
VB5
IN09
VB6
IN10
VC0
IN11
VC1
IN12
VC2
IN13
VC3
IN14
VC4
IN15
VC5
IN16
VC6
IN17
VC7
IN18
DOT_SUM
EOR18
OUT
IN1
I1
OUT
IN2
EOR2
PFUSE
PAR_SUM
MFUSE
IN1
I2
OUT
IN2
AND2
PARITY_ERROR
04598-0-004
VA0
Figure 52. Functional Circuit of AD8555 Parity Check
Table 13. Examples of DAT_SUM
Second Stage Gain Code
000
000
000
000
000
001
001
111
First Stage Gain Code
000 0000
000 0000
000 0000
000 0001
100 0001
000 0000
000 0001
111 1111
Output Offset Code
0000 0000
1000 0000
1000 0001
0000 0000
0000 0000
0000 0000
1000 0000
1111 1111
VA0 to VA2 is the 3-bit control signal for the second stage gain,
VB0 to VB6 is the 7-bit control signal for the first stage gain,
and VC0 to VC7 is the 8-bit control signal for the output offset.
PFUSE is the signal from the parity fuse, and MFUSE is the
signal from the master fuse.
The function of the 2-input AND gate (cell and2) is to ignore
the output of the parity circuit (signal PAR_SUM) when the
master fuse has not been blown. PARITY_ERROR is set to 0
when MFUSE = 0. In the simulation mode, for example, parity
check is disabled. After the master fuse has been blown, i.e.,
after the AD8555 has been programmed, the output from the
parity circuit (signal PAR_SUM) is fed to PARITY_ERROR.
Number of Bits with 1
0
1
2
1
2
1
3
18
DAT_SUM
0
1
0
1
0
1
1
0
When PARITY_ERROR is 0, the AD8555 behaves as a programmed amplifier. When PARITY_ERROR is 1, a parity error
has been detected, and VOUT is connected to VSS.
The 18-bit data signal (VA0 to VA2, VB0 to VB6, and VC0 to
VC7) is fed to an 18-input exclusive-OR gate (Cell EOR18). The
output of Cell EOR18 is the signal DAT_SUM. DAT_SUM = 0 if
there is an even number of 1s in the 18-bit word; DAT_SUM =
1 if there is an odd number of 1s in the 18-bit word. Examples
are given in Table 13.
Rev. A | Page 22 of 28
AD8555
After the second stage gain, first stage gain, and output offset
have been programmed, DAT_SUM should be computed and
the parity bit should be set equal to DAT_SUM. If DAT_SUM is
0, the parity fuse should not be blown in order for the PFUSE
signal to be 0. If DAT_SUM is 1, the parity fuse should be
blown to set the PFUSE signal to 1. The code to blow the parity
fuse is
1000 0000 0001 10 11 10 0000 0100 0111 1111 1110.
After setting the parity bit, the master fuse can be blown to prevent further programming, using the code 1000 0000 0001 10
11 10 0000 0001 0111 1111 1110.
Signal PAR_SUM is the output of the 2-input exclusive-OR
gate (Cell EOR2). After the master fuse has been blown,
PARITY_ERROR is set to PAR_SUM. As mentioned earlier,
the AD8555 behaves as a programmed amplifier when
PARITY_ERROR = 0 (no parity error). On the other hand,
VOUT is connected to VSS when a parity error has been
detected, i.e., when PARITY_ERROR = 1.
Read Mode
The values stored by the polysilicon fuses can be sent to the
FILT/DIGOUT pin to verify correct programming. Normally,
the FILT/DIGOUT pin is connected to only the second gain
stage output via RF. During read mode, however, the
FILT/DIGOUT pin is also connected to the output of a shift
register to allow the polysilicon fuse contents to be read. Since
VOUT is a buffered version of FILT/DIGOUT, VOUT also outputs a digital signal during read mode.
Read mode is entered by setting Field 1 to 11 and selecting the
desired parameter in Field 2; Field 4 is ignored. The parameter
value, stored in the polysilicon fuses, is loaded into an internal
shift register, and the MSB of the shift register is connected to
the FILT/DIGOUT pin. Pulses at DIGIN shift the shift register
contents out to the FILT/DIGOUT pin, allowing the 8‒bit
parameter value to be read after seven additional pulses; shifting occurs on the falling edge of DIGIN. An eighth pulse at
DIGIN disconnects FILT/DIGOUT from the shift register and
terminates the read mode. If a parameter value is less than 8 bits
long, the MSBs of the shift register are padded with 0s.
Sense Current
A sense current is sent across each polysilicon fuse to determine
whether it has been blown or not. When the voltage across the
fuse is less than approximately 1.5 V, the fuse is considered not
blown and Logic 0 is output from the OTP cell. When the voltage across the fuse is greater than approximately 1.5 V, the fuse
is considered blown and Logic 1 is output.
When the AD8555 is manufactured, all fuses have a low resistance. When a sense current is sent through the fuse, a voltage
less than 0.1 V is developed across the fuse. This is much lower
than 1.5 V, so Logic 0 is output from the OTP cell. When a fuse
is electrically blown, it should have a very high resistance.
When the sense current is applied to the blown fuse, the voltage
across the fuse should be larger than 1.5 V, so Logic 1 is output
from the OTP cell.
It is theoretically possible (though very unlikely) for a fuse
to be incompletely blown during programming, assuming the
required conditions are met. In this situation, the fuse could
have a medium resistance (neither low nor high), and a voltage
of approximately 1.5 V could be developed across the fuse.
Thus, the OTP cell could sometimes output Logic 0 or a Logic
1, depending on temperature, supply voltage, and other variables. To detect this undesirable situation, the sense current
can be lowered by a factor of 4 using a special code. The voltage
developed across the fuse would then change from 1.5 V to 0.38
V, and the output of the OTP would be a Logic 0 instead of the
Logic 1 expected from a blown fuse. Correctly blown fuses
would still output a Logic 1. In this way, incorrectly blown fuses
can be detected. Another special code would return the sense
current to the normal (larger) value. The sense current cannot
be permanently programmed to the low value. When the
AD8555 is powered up, the sense current defaults to the high
value.
The code to use the low sense current is 1000 0000 0001 00 00
10 XXXX XXX1 0111 1111 1110.
The code to use the normal (high) sense current is 1000 0000
0001 00 00 10 XXXX XXX0 0111 1111 1110.
For example, to read the second stage gain, the code 1000 0000
0001 11 00 10 0000 0000 0111 1111 1110 can be used. Since the
second stage gain parameter value is only three bits long, the
FILT/DIGOUT pin has a value of 0 when this code is entered
and remains 0 during four additional pulses at DIGIN. The
fifth, sixth, and seventh pulse at DIGIN returns the 3-bit value
at FILT/DIGOUT, the seventh pulse returning the LSB. An
eighth pulse at DIGIN terminates the read mode.
Rev. A | Page 23 of 28
AD8555
Suggested Programming Procedure
1.
Set VDD and VSS to the desired values in the application.
Use simulation mode to test and determine the desired
codes for the second stage gain, first stage gain, and output
offset. The nominal values for these parameters are shown
in Table 6, Table 7, Equation 1, and Equation 2; the codes
corresponding to these values can be used as a starting
point. However, since actual parameter values for given
codes vary from device to device, some fine tuning is necessary for the best possible accuracy.
One way to choose these values is to set the output offset
to an approximate value, e.g., Code 128 for midsupply, to
allow the required gain to be determined. Then set the
second stage gain such that the minimum first stage gain
(Code 0) gives a lower gain than required, and the maximum first stage gain (Code 127) gives a higher gain than
required. After choosing the second stage gain, the first
stage gain can be chosen to fine tune the total gain. Finally,
the output offset can be adjusted to give the desired value.
After determining the desired codes for second stage gain,
first stage gain, and output offset, the device is ready for
permanent programming.
2.
3.
4.
Set VSS to 0 V and VDD to 5.5 V. Use program mode to
permanently enter the desired codes for the second stage
gain, first stage gain, and output offset. Blow the master
fuse to allow the AD8555 to read data from the fuses and
to prevent further programming.
Set VDD and VSS to the desired values in the application.
Use read mode with low sense current followed by high
sense current to verify programmed codes.
Measure gain and offset to verify correct functionality.
Suggested Algorithm to Determine
Optimal Gain and Offset Codes
1.
2a.
2b.
3a.
3b.
3c.
3d.
3e.
3f.
3g.
3h.
3i.
3j.
4a.
4b.
4c.
4d.
4e.
4f.
4g.
4h.
4i.
4j.
Rev. A | Page 24 of 28
Determine the desired gain, GA (e.g., using measurements).
Use Table 7 to determine the second stage gain G2 such
that (4.00 × 1.04) < (GA/G2) < (6.4/1.04). This ensures
that the first and last codes for the first stage gain are not
used, thereby allowing enough first stage gain codes
within each second stage gain range to adjust for the 3%
accuracy.
Use simulation mode to set the second stage gain to G2.
Set the output offset to allow the AD8555 gain to be
measured, e.g., use Code 128 to set it to midsupply.
Use Table 6 or Equation 3 to set the first stage gain code
CG1 such that the first stage gain is nominally GA/G2.
Measure the resulting gain GB. GB should be within
3% of GA.
Calculate the first stage gain error (in relative terms)
EG1 = GB/GA − 1.
Calculate the error (in the number of the first stage gain
codes) CEG1 = EG1/0.00370.
Set the first stage gain code to CG1 − CEG1.
Measure the gain GC. GC should be closer to GA than to GB.
Calculate the error (in relative terms) EG2 = GC/GA − 1.
Calculate the error (in the number of the first stage gain
codes) CEG2 = EG2/0.00370.
Set the first stage gain code to CG1 − CEG1 − CEG2. The
resulting gain should be within one code of GA.
Determine the desired output offset OA, e.g., using the
measurements.
Use Equation 1 to set the output offset code CO1 such
that the output offset is nominally OA.
Measure the output offset OB. OB should be within
3% of OA.
Calculate the error (in relative terms) EO1 = OB/OA − 1.
Calculate the error (in the number of the output offset
codes) CEO1 = EO1/0.00392.
Set the output offset code to CO1 − CEO1.
Measure the output offset OC. OC should be closer to OA
than to OB.
Calculate the error (in relative terms) EO2 = OC/OA − 1.
Calculate the error (in the number of the output offset
codes) CEO2 = EO2/0.00392.
Set the output offset code to CO1 − CEO1 − CEO2. The
resulting offset should be within one code of OA.
AD8555
FILTERING FUNCTION
DRIVING CAPACITIVE LOADS
The AD8555’s FILT/DIGOUT pin can be used to create a simple low-pass filter. The AD8555’s internal 18 kΩ resistor can be
used with an external capacitor for this purpose. Typical
responses of the AD8555, configured for a gain of 70 and gain
of 1280, are shown in Figure 54 and Figure 55, respectively. This
filtering feature can be used to pass the signals within the filter’s
pass band while limiting the out-of-band signals bandwidth
and, therefore, reducing the noise of the overall solution.
The AD8555 can drive large capacitive loads. This feature is
useful when the amplifier, placed close to the sensor, has to
drive long cables. Most instrumentation amplifiers have difficulty driving capacitance due to the degradation of the phase
margin caused by the additional phase lag from the capacitive
load. Higher capacitance at the output can increase the amount
of overshoot and ringing in the amplifier’s step response and
could even affect the stability of the device. Additionally, the
value of the capacitive load that an amplifier can drive before
oscillation varies with gain, supply voltage, input signal, and
temperature. Figure 57 and Figure 58 show the overshoot
response of AD8555 versus the capacitive load with a different
value isolation resistor (RS) in Figure 56. Similar to all amplifiers, the AD8555 responds with overshoot when driving large
CL, but after a point (approximately 22 nF), the overshoot decreases. This is because the pole created by CL dominates at
first; however, at some point, the pole is farther in than the pole
setting of the buffer amplifier and is ignored by AD8555.
VSS
VSS 8
1 VDD
2
CFILTER
FILT/DIGOUT VOUT 7
3 DIGIN
VCLAMP 6
4 VNEG
VPOS 5
VDD
04598-0-051
VOUT
AD8555
VIN
Figure 53. AD8555 Configured to Filter Noise
VDD
VSS
CFILTER
CFILTER = 0.010μF
CFILTER = 0.001μF
40
VSS 8
1
VDD
2
FILT/DIGOUT VOUT 7
3
DIGIN
VCLAMP 6
4
VNEG
VPOS 5
RS
VOUT
CL
VDD
04598-0-054
VDD
dB
AD8555
20
CFILTER = 0.100μF
Figure 56. Test Circuit for Driving Capacitive Loads
0
60
VS = ±2.5V
RS
1k
10k
50k
Figure 54. Typical Response of the AD8555 at FILT/DIGOUT Pin (Gain = 70)
CFILTER = 0.001μF
OUTPUT
BUFFER
OVERSHOOT (%)
100
04598-0-052
10
RS = 0
50
CL = 1nF
40
30
RS = 10
20
RS = 50
RS = 20
60
dB
40
0
0.1
CFILTER = 0.010μF
20
1
10
LOAD CAPACITANCE (nF)
Figure 57. Positive Overshoot Graph vs. CL
0
CFILTER = 0.100μF
100
1k
10k
100k
04598-0-053
10
RS = 100
Figure 55. Typical Response of the AD8555 at FILT/DIGOUT Pin (Gain = 1280)
Rev. A | Page 25 of 28
100
04598-0-028
10
AD8555
60
needed to maintain common-mode rejection at low frequencies. This introduces a second low-pass network, R1 + R2 and
C3 that has a −3 dB frequency equal to 1/(2 π × (R1 + R2)(C3)).
This circuit’s −3 dB signal bandwidth is approximately 4 kHz
when a C3 value of 0.047 μF is used (see Figure 59).
VS = ±2.5V
RS
RS = 0
CL
40
VDD
30
VSS
RS = 10
1 VDD
20
RS = 20
R2
4.02kΩ
10
RS = 50
1.0
10.0
LOAD CAPACITANCE (nF)
100.0
C2
1nF
C3
0.047μF
04598-0-029
0
0.1
VNEG
RS = 100
VSS 8
2 FILT/DIGOUT
VOUT 7
3 DIGIN
VCLAMP 6
4 VNEG
VPOS 5
AD8555
VDD
C1
1nF
04598-0-057
OVERSHOOT (%)
50
VPOS
R1
4.02kΩ
Figure 58. Negative Overshoot Graph vs. CL
Figure 59. RFI Suppression Method
RF INTERFERENCE
SINGLE-SUPPLY DATA ACQUISITION SYSTEM
All instrumentation amplifiers show dc offset as the result of
rectification of high frequency out-of-band signals that appear
at their inputs. The circuit in Figure 59 provides good RFI suppression without reducing performance within the AD8555
pass band. Resistor R1 and Capacitor C1, and likewise Resistor
R2 and Capacitor C2, form a low-pass RC filter that has a −3 dB
bandwidth equal to f(−3 dB) = 1/2 π × R1 × C1. It can be seen that
R1, R2 and C1, C2 form a bridge circuit whose output appears
across the amplifier’s input pins. Any mismatch between C1, C2
unbalances the bridge and reduce the common-mode rejection.
Using the component values shown, this filter has a bandwidth
of approximately 40 kHz. To preserve common-mode rejection
in the AD8555’s pass band, capacitors need to be 5% (silver
mica) or better and should be placed as close to its inputs as
possible. Resistors should be 1% metal film. Capacitor C3 is
Interfacing bipolar signals to single-supply analog-to-digital
converters (ADCs) presents a challenge. The bipolar signal
must be mapped into the input range of the ADC. Figure 60
shows how this translation can be achieved. The output offset
can be programmed to a desirable level to accommodate the
input voltage requirement of the ADC.
VDD
4
VDD
10nF
100Ω
100Ω
100Ω
100Ω
1
VDD
2
FILT/DIGOUT
VSS 8
3
DIGIN
VCLAMP 6
4
VNEG
VPOS 5
VOUT 7
2
VDD
AIN
12 BIT
AD7476
AD8555
04598-0-058
0
SDIGIN
Figure 60. A Single-Supply Data Acquisition Circuit Using the AD8555
Rev. A | Page 26 of 28
AD8555
The bridge circuit with a sensitivity of 2 mV/V is excited by a
5 V supply. The full-scale output voltage from the bridge
(±10 mV) therefore has a common-mode level of 2.5 V. The
AD8555 removes the common-mode component and amplifies
the input signal by a factor of 200 (G1 = 4, G2 = 50, Offset =
128). This results in an output signal of ±2.0 V. In order to prevent this signal from running into the AD8555’s ground rail, the
output offset voltage has to be raised to 2.5 V. This signal is
within the input voltage range of the ADC.
USING THE AD8555 WITH CAPACITIVE SENSORS
Figure 61 shows a crude way of using the AD8555 with capacitive sensors. RP1 and RP2 are resistors implementing a potential
divider to bias VNEG to VDD/2. Recommended values range
from 1 kΩ to 1 MΩ. CS is the capacitive sensor, and RS is a shunt
resistor used to prevent leakage currents from integrating on
the sensor. The value of RS is application specific.
Note that although VNEG is tied to a dc voltage, the only
impedance across the capacitive sensor is RS. Therefore, the
only way for charge to leak away from CS is through RS, assuming the input bias currents at VPOS and VNEG are negligible.
tial offset voltage between VPOS and VNEG. This differential
offset voltage is amplified by the AD8555. The input bias current at VNEG, on the other hand, flows into RP1 and create a
common-mode shift. This has little impact on VOUT. Despite
this weakness, the arrangement in Figure 61 should work if the
user wants to minimize the number of components around the
sensor, and if the error introduced by the input bias current at
VPOS is considered negligible.
If greater accuracy is needed, the circuit in Figure 62 is recommended. RP1, RP2, and CS are the same as in Figure 61; RP1 and
RP2 should be between 1 kΩ to 1 MΩ. RS in Figure 61 has been
split into two resistors, RS1 and RS2, in Figure 62. Again, the only
way for the capacitive sensor to discharge is through (RS1 + RS2).
The input bias current at VPOS flows through RS2 and RP1, and
the input bias current at VNEG flows through RS1 and RP1. If RS1
is made equal to RS2 and if the input bias currents are equal, the
input bias currents give a common-mode shift at VPOS and
VNEG with no differential offset. This common-mode shift is
attenuated by the AD8555 common-mode rejection. Furthermore, changes in input bias current, e.g., with temperature,
manifest as an input common-mode change, also rejected by
the AD8555.
RP2
RS2
AD8555
04598-0-059
VNEG
RP1
RP2
VOUT
RS
RS1
RP1
Figure 61. Crude Way of Using the AD8555 with Capacitive Sensors
The weakness of the circuit in Figure 61 is that the AD8555
input bias current at VPOS flows into RS and creates a differen-
VPOS
VOUT
CS
VDD
VNEG
AD8555
04598-0-060
VPOS
CS
VDD
Figure 62. Recommended Way of Using the AD8555 with Capacitive Sensors
Rev. A | Page 27 of 28
AD8555
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
5
1
4
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
6.20 (0.2441)
5.80 (0.2284)
0.50 (0.0196)
0.25 (0.0099)
1.75 (0.0688)
1.35 (0.0532)
8°
0°
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
SEATING
PLANE
45°
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
COMPLIANT TO JEDEC STANDARDS MS-012-A A
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
012407-A
8
4.00 (0.1574)
3.80 (0.1497)
Figure 63. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters (inches)
4.00
BSC SQ
0.60 MAX
0.60 MAX
13
12° MAX
1.00
0.85
0.80
0.65 BSC
TOP
VIEW
12
0.50
0.40
0.30
(BOTTOM VIEW)
9
8
5
4
0.25 MIN
1.95 BSC
0.05 MAX
0.02 NOM
0.35
0.30
0.25
2.50
2.35 SQ
2.20
EXPOSED
PAD
3.75
BSC SQ
0.80 MAX
0.65 TYP
SEATING
PLANE
PIN 1
INDICATOR
1
0.20 REF
COPLANARITY
0.08
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-VGGC
082008-A
PIN 1
INDICATOR
16
Figure 64. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4 mm Body, Very Thin Quad
(CP-16-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD8555ARZ 1
AD8555ARZ-REEL1
AD8555ARZ-REEL71
AD8555ACPZ-R21
AD8555ACPZ-REEL1
AD8555ACPZ-REEL71
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
8-Lead SOIC_N
8-Lead SOIC_N
8-Lead SOIC_N
16-Lead LFCSP_VQ
16-Lead LFCSP_VQ
16-Lead LFCSP_VQ
Z = RoHS Compliant Part.
©2004–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04598–0–6/09(A)
Rev. A | Page 28 of 28
Package Option
R-8
R-8
R-8
CP-16-10
CP-16-10
CP-16-10