ASAHI KASEI
[AK8815/16]
AK8815/16
NTSC/PAL Digital Video Encoder
GENERAL DESCRIPTION
The AK8815/16 is a digital video encoder which is developed for portable apparatus applications such as cellular
phone etc.. ITU-R BT.601 level compatible Y, Cb,and Cr signals which correspond to square pixel are encoded
into either NTSC or PAL compatible composite video signal. Interface is made in HSYNC-, VSYNC- synchronized
slave-mode operation. It is controlled via a 4-wire serial interface.
FEATURES
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NTSC-M, PAL-B, D, G, H, I encoding
Composite Video Output
Y:Cb:Cr 4:2:2 Square Pixel Data Input
H/V Slave Operation
Y filtering: 2 x over-sampling
C filtering: 4 x over-sampling
9-bit DAC
Macrovision Copy Protection Rev. 7.1 * (only AK8815 )
VBID ( CGMS-A ) Compatible
WSS Compatible
On-chip Quartz Crystal Oscillator circuit
Clock: Square Pixel data rate 24.5454 MHz ( NTSC ), 29.50 MHz ( PAL )
Device Control I / F : 4- wire Serial Bus Interface
On-chip Color Bar Output
Black Burst Output
Internal Operating Voltage: 2.7 V ~ 3.3 V
supplying Interface Power Supply ( 1.6 V ~ 2.0 V or 2.7 V ~ 3.3 V )
Power-down function
Monolithic CMOS
57 pin FBGA ( 5 mm sq ) ( lead-free package )
(*Note) This device is protected by U.S. patent numbers 4,631,603, 4,577,216, and 4,819,098, and other
intellectual rights. The use of Macrovision’s copy protection technology in the device must be authorized by
Macrovision and is intended for home and other limited pay-per -view use only, unless otherwise authorized in
written by Macrovision. Reverse engineering or disassembly is prohibited.
MS0331-E-00
1
2004 / 08
ASAHI KASEI
[AK8815/16]
BLOCK DIAGRAM
XTI/CLKIN
XTO
CLKINV
RSTN PDN
CS
SCLK
SDO
SDI
VREF
CLK
Generator
CLKMD
u-p I/F
Register
Timing Controller
D[7:0]
CLKOUT
Input Data Control
Synchronization Control
VSYNC
HSYNC
SYNC
Generator
Y
VBID & WSS
Macrovision
Y
LPF Filter
(x 2 Interpolator)
Cb
Cr
U
Cb/Cr
LPF Filter
(x 2 Interpolator)
Cos
SubCarrier
Generator
Color Bar &
Background
Color Control
C
PVDD2 PVSS2 PVDD1 PVSS1
Sin
DVDD DVSS XVDD
AVDD AVSS
2
9-bit
DAC
VIDEOOUT
TEST
Logic
UD[4:0]
Chroma
LPF Filter
(x 2 Interpolator)
V
MS0331-E-00
IREF
VREF
Generator
TEST ATPG
2004 / 08
ASAHI KASEI
[AK8815/16]
ORDERING GUIDE
AK8815/16VG 57 pin FBGA
PIN LAYOUT
57pin FBGA
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
G
H
J
Bottom View
MS0331-E-00
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2004 / 08
ASAHI KASEI
[AK8815/16]
PIN FUNCTIONAL DESCRIPTION (preliminary)
No.
Pin Name
I/O
A7
XTI/CLKIN
I
B6
XTO
O
B5
CLKMD
I
B9
CLKOUT
O
B7
CLKINV
I
J6
PDN
I
J5
RSTN
I
J4
SCLK
I
H4
SDI
I
H3
SDO
O
H5
CS
I
H8
D7
I
G8
D6
I
H9
D5
I
G9
D4
I
F8
D3
I
E8
D2
I
D8
D1
I
D9
D0
I
J7
HSYNC
I
H7
VSYNC
I
B3
VREF
O
MS0331-E-00
Function
Quartz crystal resonator connection pin ( to be grounded via a 18 pF capacitor as shown
in the recommended circuit ).
NTSC: 24.5454 MHz / PAL: 29.50 MHz
Hi-Z input is acceptable to this pin at PDN = L.
Input from an external crystal oscillator should be connected to this pin.
Quartz crystal resonator connection pin ( to be grounded via a 22 pF capacitor as shown
in the recommended circuit ).
NTSC: 25.5454 MHz / PAL: 29.50 MHz
DVSS level is output on this pin at PDN = L.
Clock Mode setting pin. Should be connected to either DVDD or DGND.
GND connection: when a crystal resonator is used
XVDD connection: when an external crystal oscillator is used
Clock output pin. NTSC: 24.5454 MHz / PAL: 29.50 MHz
This becomes Hi-Z output at PDN =L.
“L “ : data is latched with rising edge.
“H” : data is latched with falling edge.
Internal clock is inverted (internal operation timing edge is inverted. CLKOUT is not
affected). Connect to either DVDD or DGND.
Power Down Pin. After returning from PD mode to normal operation, RESET Sequence
should be done to AK8815/16.
“L “(GND level): Power-down
“H “: normal operation
Reset input pin. In order to initialize the device , an initialization must be made in
accordance with the reset sequence.
“L “ : reset
“H “ : reset
Hi-Z input is acceptable to this pin at PDN = L.
Serial Data clock input pin. 15 MHz ( max )
Hi-Z input is acceptable to this pin at PDN = L.
Serial Data input pin.
Hi-Z input is acceptable to this pin at PDN = L.
Serial Data output pin.
This becomes high output at PDN = L.
This pin interfaces one-to-one with a controller through a dedicated pin.
Serial Data Chip Enable signal input pin.
This pin interfaces one-to-one with a controller through a dedicated pin.
L : disabled condition ( un-selected )
H : enabled condition ( selected )
Hi-Z input is acceptable to this pin at PDN = L.
Data Video Signal input pin (MSB).
Hi-Z input is acceptable to this pin at PDN = L.
Data Video Signal input pin.
Hi-Z input is acceptable to this pin at PDN = L.
Data Video Signal input pin.
Hi-Z input is acceptable to this pin at PDN = L.
Data Video Signal input pin.
Hi-Z input is acceptable to this pin at PDN = L.
Data Video Signal input pin.
Hi-Z input is acceptable to this pin at PDN = L.
Data Video Signal input pin.
Hi-Z input is acceptable to this pin at PDN = L.
Data Video Signal input pin.
Hi-Z input is acceptable to this pin at PDN = L.
Data Video Signal input pin (LSB).
Hi-Z input is acceptable to this pin at PDN = L.
Horizontal SYNC signal input pin.
Hi-Z input is acceptable to this pin at PDN = L.
Vertical SYNC signal input pin.
Hi-Z input is acceptable to this pin at PDN = L.
On-chip VREF output pin. AVSS level is output on this pin at PDN = L.
Connect this pin to Analog Ground via a 0.1 uF or larger capacitor.
4
2004 / 08
ASAHI KASEI
[AK8815/16]
IREF output pin. Connect this pin to Analog ground via a 12 Kohm resistor
( better than +/_ 1% accuracy ).
Video output pin. Connect this pin to Analog ground via a 390 ohm resistor
resistor ( better than +/_ 1% accuracy ).
Analog power supply pin.
Power supply pin for crystal ( for XTAL ).
Analog power supply pin.
Analog ground pin.
Digital ground pin.
Crystal ground connection pin ( set DVSS [0 V] ).
Analog ground pin.
Digital power supply ( digital core power supply )
Digital power supply ( digital core power supply )
Digital ground pin ( digital core ground )
Digital ground pin ( digital core ground )
A2
IREF
O
C1
VIDEOOUT
O
C2
A5
B2
B1
D1
A6
A3
F1
F9
E2
E9
AVDD
XVDD
AVDD
AVSS
DVSS
DVSS
AVSS
DVDD
DVDD
DVSS
DVSS
P
P
P
G
G
G
G
P
P
G
G
C8
PVDD1
P
C9
PVSS1
G
J3
PVDD2
P
H2
PVSS2
G
A4
AVSS
G
B8
A8
TEST
ATPG
I
I
For normal operation, connect to ground.
For normal operation, connect to ground.
H1
DVDD
P
Digital power supply
J2
G1
G2
E1
D2
UD4
UD3
UD2
UD1
UD0
O
O
O
I/O
I/O
A1
A9
J1
J9
B4
H6
J8
F2
C3
NC
NC
NC
NC
NC
NC
NC
NC
N.C.
-
MS0331-E-00
Power supply pin for chip pad.
I / F power supply for CLKOUT, D[7:0], HSYNC, VSYNC
Ground pin for PVDD1
Power supply pin for chip pad.
I / F power supply for PDN, RSTN, SDO, SDI, CS, SCLK.
Ground pin for PVDD2
Ground pin for the substrate biasing
Connect to Analog Ground.
Test output pin. For normal operation, left un-connected ( NC ).
Test output pin. For normal operation, left un-connected ( NC ).
Test output pin. For normal operation, left un-connected ( NC ).
Test I/O pin. For normal operation, left un-connected ( NC ).
Test I/O pin. For normal operation, left un-connected ( NC ).
NC pin.
NC pin.
NC pin.
NC pin.
NC pin
NC pin.
NC pin.
NC pin.
Index pin
5
2004 / 08
ASAHI KASEI
[AK8815/16]
ELECTRICAL CHARACTERISTICS
(1)Absolute Maximum Ratings
Parameter
Min
Max
Units
Supply voltage (VDD) (Note1)
DVDD, XVDD,AVDD, PVDD1, PVDD2
-0.3
4.6
V
Input pin voltage (Vin)
-0.3
VDD+0.3
V
-
+/- 10
mA
-40
+125
°C
Input pin current (Iin) (Note2)
Storage temperature
(Note1)
When each ground pin ( DVSS, AVSS, PVSS1, PVSS2 ) is at 0 V ( voltage reference ).
In this specification, PVDD1 and PVDD2 are expressed as PVDD ( as a general comment ) hereafter.
Similarly, DVDD, XVDD are expressed as DVCC, and AVDD and AVDD as AVDD.
Each ground pin is always kept to the same reference voltage, 0 V with no potential difference.
(Note2)
Exclude Power supply pin.
(2) Recommended Operating Conditions
Parameter
Power supply (DVDD = AVDD )
(Note1 )
Interface power supply (Note2)
(PVDD = DVCC ) at 3.0 V I/F
Interface power supply
(PVDD1, 2 ) at 1.8 V I/F
Operating temperature (Ta)
Min
Typ.
Max
Units
2.7
3.0
3.3
V
2.7
.3.0
3.3
V
1.6
1.8
2.0
V
-20
25
85
°C
Note 1) excluding interface power supply. 1.8 V power supply can be supplied only to the interface part.
Note 2) interface power supplies PVDD1, PVDD2 can be used as 3 V or 1.8 V power supply interface
each.
But when the 1.8 V interface is not selected, same potential as DVCC is used as interface power supply.
(Example PVDD1 = 1.8 V, PVDD2 = DVDD = 3 V)
Note 3) as described at the note in item ( 1 ) above, PVDD1 and PVDD2 are expressed as PVDD in this
table. Similarly, DVDD and XVDD are expressed as DVCC, and AVDD and AVDD as AVDD.
(3) DC Characteristics
[Operating voltages : DVDD 2.7 V ~ 3.3V / PVDD 2.7 V ~ 3.3 V / PVDD 1.6 V ~ 2.0 V, Temperature : -20 ~ 85°C]
Parameter
Digital input H voltage
Digital input L voltage
Digital input leakage
current
Digital output H voltage
( excluding XTO )
Digital output L voltage
( excluding XTO )
MS0331-E-00
Symbol
VIH1
VIH2
VIL1
VIL2
Min
0.7PVDD
0.8PVDD
Typ
2.2
VOH2
1.3
Units
V
IL
VOH1
Max
0.3PVDD
0.2PVDD
V
+/- 10
uA
V
VOL1
0.4
V
VOL2
0.4
V
6
Conditions
PVDD = 3.0V
PVDD = 1.8V
PVDD = 3.0V
PVDD = 1.8V
IOH= 1mA
I/O 3.0V
IOH= 600uA
I/O 1.8V
IOL= 2mA
I/O 3.0V
IOL= 1mA
I/O 1.8V
2004 / 08
ASAHI KASEI
[AK8815/16]
(4) Analog Characteristics
[Operating voltage : AVDD = DVCC=2.7 - 3.3 V, Temperature: -20 - 85°C]
Parameter
Resolution
Integral non-linearity ( error )
Differential non-linearity ( error )
Output full scale voltage
Output offset voltage
On-chip reference voltage
Min
1.21
Typ
9
+/- 0.6
+/- 0.4
1.28
1.17
1.23
-50
Reference voltage drift
Max
+/- 2.0
+/- 1.0
1.35
5.0
1.30
Units
bit
LSB
LSB
V
mV
V
ppm/°C
Conditions
Note1)
Note2)
Note1) values are when a 390 ohm output load, a 12 Kohm IREF pin resistor and on-chip VREF are used.
Full scale output current is calculated as Iout = full scale output voltage ( typ. 1.28 V ) / 390 ohm = typ. 3.28
mA.
Note2) A voltage referenced to VSS when a decimal zero voltage is input to DAC.
(5) Power Consumption
[Operating voltage : AVDD = DVCC=2.7 - 3.3 V, Temperature: -20 - 85°C]
Parameter
Total power consumption
Power-down current 1
Power-down current 2
XTAL part current
Analog part operating current 1
Analog part operating current 2
Min
Typ
24
10
1
2.0
6.5
1.6
Max
36
100
10
3.3
Units
mA
uA
uA
mA
mA
µA
Conditions
Note3)
Note4)
Note5)
Note6)
Note7)
Note8)
Note3) NTSC mode on-chip color bar output is enabled and DAC is “ on “ ( no external output loads are
connected , other than those recommended, connecting-components ).
Note4) measuring conditions :
input / output settings after power-down sequence are, PDN pin is at GND level, CLKOUT and SDO output
are at high level ( power supply voltage ) with no external connection, input voltage on those input pins is 1/2
level of power supply which are set to accept Hi-Z input at power-down, and TEST = ATPG = GND ( or left
open ).
Power supplies are AVDD = DVCC = PVDD.
Each ground pin ( DVSS, AVSS1, AVSS2, PVSS1, PVSS2 ) is always 0 V ( voltage reference ).
Note5) measuring conditions :
set AVDD = DVCC = 0 V ( potential difference with voltage reference ground is 0 V ) in power-down current 1
condition.Set those input pins to GND level which are set to accept Hi-Z input at power-down.
Power-down current 2 is PVDD power supply current at PVDD = 1.6 V ~ 1.8 V or 2.7 V ~ 3.3 V.
Note6) at RSTN = H, PDN = H
Note7) when DAC output is “ ON “.
Note8) when DAC output is “ OFF “.
MS0331-E-00
7
2004 / 08
ASAHI KASEI
[AK8815/16]
(6) Crystal Oscillator Circuit Part
Crystal resonator and externally connecting load capacitance
Parameter
Oscillating frequency
frequency accuracy
load capacitance
effective equivalent resistance
parallel capacitance
externally connecting load
capacitance on XTLI pin
externally connecting load
capacitance on XTLO pin
Symbol
Min
Typ
24.5454
29.5000
f0
∆f/f
CL
Re
C0
Max
Units
Conditions
[MHz]
+/-50
15
100
0.85
[ppm]
[pF]
[Ω]
[pF]
CXI
18
[pF]
CXO
22
[pF]
Note1)
Note 1 ) effective equivalent resistance is generally given as
Re = R1 x ( 1 + CO / CL ) square
Where R1 : equivalent series resistance of crystal resonator
CO : parallel capacitance of crystal resonator
Circuit connection example
gm
Rf
AK8815
XTLI
XTLO
Rd
CXO
=22pF
CXI
=18pF
rd: Please refer the X’tal specification
MS0331-E-00
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2004 / 08
ASAHI KASEI
[AK8815/16]
AC TIMING
( PVDD = 2.7 V ~ 3.3 V / PVDD = 1.6 V ~ 2.0 V, Temperature : –20 ~ 85°C)
loading condition : CL = 30 pF ( at 3.0 V I/F )
CL = 15 pF ( at 1.8 V I/F )
(1) CLK
( 1-1 ) CLKMD = DVSS : when a crystal resonator is connected ( +/_ 50 ppm )
fCLK
tCLKL
1/2 PVDD1
tCLKH
VIH1, VIH2
CLKOUT
Parameter
CLKOUT
VIL1, VIL2
Symbol
Min.
Typ.
Max
24.5454
fCLKO
Unit
MHz
29.500
Conditions
NTSC
PAL
tCLKIL, tCLKIH : minimum pulse width 10 nS guaranteed by design
External input clock AC timing ( DVCC = 2.7 V ~ 3.3 V : -20 ~ 85 °C )
( 1-2 ) CLKMMD = XVDD : when an external clock source is input ( +/_ 50 ppm )
fCLKI
tCLKIL
1/2 DVCC
tCLKIH
VIH1
CLKIN
Parameter
CLKIN
CLKIN Duty
VIL1
Symbol
Min.
Typ.
24.5454
fCLKI
pCLKID
Max
MHz
29.50
40
Unit
60
Conditions
NTSC
PAL
%
tCLKIL, tCLKIH : minimum pulse width 12 nS ( tr / tf = < 2 nS at 10 % - 90 % level of power supply )
MS0331-E-00
9
2004 / 08
ASAHI KASEI
[AK8815/16]
(2) Pixel Data Input Timing
VIH1, VIH2
VIL1, VIL2
CLKOUT
tDH
tDS
D7:D0
HSYNC
VSYNC
VIH1, VIH2
VIL1, VIL2
CLKINV = Low, -20 ~ 85 °C ( loading condition : CL = 30 pF at 3 V I/F / 15 pF at 1.8 V I/F )
Parameter
Symbol
Min.
Typ.
Max
Unit
Data Setup Time
tDS
8
nsec
Data Hold Time
tDH
5
nsec
Conditions
above values are specified at the AK8815/16 device pin terminal and do not include interconnection delays of
pc
board etc..
When CLKINV = High, similar tDS and tDH are specified at the falling edge of CLKOUT.
(3) HSYNC pulse width
pHSW
HSYCN
Parameter
HSYNC Pulse Width
Symbol
Min.
Typ.
15
115/16
15
139
pHSW
Max
Unit
Conditions
CLKs
NTSC
(24.5454MHz)
PAL
(29.50MHz)
* typical values are calculated by converting the HSYNC pulse width of Analog Video specification into number
of system clock pulses.
MS0331-E-00
10
2004 / 08
ASAHI KASEI
[AK8815/16]
(4) Reset
(4-1) Reset Timing
RSTN
pRES
1
2
99
100
CLKOUT
Parameter
RSTN Pulse Width
Symbol
Min.
pRES
100
Typ.
Max
Unit
SYSCLK
(4-2) Power Down Sequence / Reset Sequence
Before PDN setting ( PDN to low ), Reset must be enabled for a duration of longer-than-100 clock time.
After PDN release ( PDN to high ), Reset must be enabled for 10 mS or longer till analog part reference
voltage & current are stabilized.
(CLKOUT=H)
CLKIN
CLKOUT
sRES
hRES
RSTN
VIH1, VIH2
VIL1, VIL2
VIH1, VIH2
PDN
GND
SCLK, SCS
tSCLL
Hi-z ok
SDO
Low
(SDO=H)
Parameter
RSTN Pulse Width
Time from PDN to high to RSTN to
high
SCL low duration before RSTN to
rise
Symbol
Min.
Typ.
Max
Unit
sRES
100
SYSCLK
hRES
10
msec
tSCLL
50
nsec
at power-down, all control signals must surely be set to either power supply or ground level of the selected power
supply, and not to ViH / ViL levels.
MS0331-E-00
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2004 / 08
ASAHI KASEI
[AK8815/16]
( 5 ) Serial I / F Timing waveform
( 5-1 ) Write / Read data input timing
VIH1, VIH2
CS
tCLK
tCSS
tSCKH tSCKL
VIH1, VIH2
1/2 Level of VIH1(2)/VIL1(2)
VIL1, VIL2
SCLK
tSDS tSDH
SDI
A7
SDO
A6
A5
A4
High
( 5-2 ) Write data input timing
tCSW
VIH1, VIH2
CS
VIL1, VIL2
tCSL
SCLK
SDI
VIL1, VIL2
D3
D2
D1
SDO
MS0331-E-00
D0
High
12
2004 / 08
ASAHI KASEI
[AK8815/16]
( 5-3 ) Read data output timing
VIH1, VIH2
CS
SCLK
VIL1, VIL2
SDI
A1
A0
SDO
D7
D6
VIH1, VIH2
VIL1, VIL2
D5
tSDCO
( 5-4 ) Read data output timing 2
tCSW
VIH1, VIH2
CS
VIL1, VIL2
tCSL
SCLK
tSDZ
SDI
SDO
D3
Parameter
D2
D1
Symbol
Min
Time from CS to high to SCLK to high
tCSS
20
SCLK Frequency
tCLK
D0
Typ
Max
Unit
nsec
15
MHz
SCLK “high” duration
tSCKH
26
nsec
SCLK “low” duration
tSCKL
26
nsec
Data set-up time
tSDS
15
nsec
Data hold time
tSDH
10
nsec
Time from 15/16 SCLK to low to CS to low
tCSL
20
nsec
CS “low” duration
tCSW
60
nsec
SDO output delay time
tSDCO
SDO output hold time
tSDH
th
20
0
nsec
nsec
When to execute sequential write/read to/from register, CS must be kept to low once
MS0331-E-00
13
2004 / 08
ASAHI KASEI
[AK8815/16]
FUNCTIONAL OUTLINE
( 1 ) Reset
( 1-1 ) Reset of Serial Interface part ( asynchronous reset )
Reset is made by setting RSTN pin to low.
( 1-2 ) Reset of other than Serial Interface blocks
Reset is made by keeping RSTN pin low for a longer than 100 clock time, in normal operation.
( 1-3 ) at Power-On-Reset ( including power-down release case )
Follow the power-on-reset sequence.
At the completion of each initialization, all internal registers are set to default values ( refer to Register Map ).
Right after the reset, Video output of the AK8815/16 is put into Hi-Z condition.
( 2 ) Power-Down
It is possible to put the device into power-down mode by setting the AK8815/16 power-down pin to GND.
Transition to power-down mode should be followed by the power-down sequence. As for the recover from the
power-down mode, it should be followed by the power-down release sequence.
( 3 ) Master Clock
As a master clock of the AK8815/16, either a crystal resonator or a crystal oscillator can be used. Either of the
operation mode ( a crystal resonator or a crystal oscillator ) is selected by CLKMD pin.
Crystal resonator mode : CLKMD DVSS
Crystal oscillator mode : CLKMD XVDD
When a crystal resonator is used, connect a resonator between XTI pin and XTO pin.
An oscillating frequency to be used differs in NTSC encoding operation and in PAL encoding operation.
A clock frequency to be used is as follows :
in NTSC encoding operation : 24.5454 MHz
in PAL encoding operation : 29.50 MHz
When a crystal oscillator is used, connect it to XTI pin.
When CLKINV = L, same rising clock as CLKOUT rise is used as an internal encoder clock, but
when CLKINV = H,
internal encoder is operated by using an inverted clock.
Even when CLKINV is altered, clock phase of CLKOUT is not changed.
( 4 ) Video Signal Interface
Video input signal ( data ) is processed in slave operation mode which is synchronized with HSYNC / VSYNC.
When CLKINV = DVSS, external input is latched at the rising edge of clock
( 5 ) Pixel Data
Input data to the AK8815/16 is YCbCr ( 4:2:2 ).
Data with Y : 15/16 ~ 235 and CbCr : 15/16 ~ 240 should be input.
( 6 ) Video Signal Conversion
Video Re-Composition module converts the multiplexed data ( ITU-R BT.601 Level Y, Cb, Cr ) into interlaced
NTSC-M and PAL-B, D, G, H, I data. Video encoding setting is done by “ Mode Register “.
MS0331-E-00
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2004 / 08
ASAHI KASEI
[AK8815/16]
( 7 ) Luminance Signal Filter ( Luma Filter )
Luminance signal is output via LPF ( see x2 Luma Filter in the block diagram ).
10
0
Gain[dB]
-10
0.0 1.0 2.0
3.0 4.0 5.0 6.0 7.0 8.0
9.0 10.0 11.0 12.0 13.0
-20
-30
-40
-50
frequency[MHz]
( 8 ) Chroma Signal Filter ( Chroma Filter )
Chroma input signal components ( Cb, Cr ) prior to the modulation go through a 1.3 MHz Band Limiting Filter
( see 4:2:2 to 4:4:4 x2 interpolator in the block diagram ).
Chroma signal which is modulated by the sub-carrier is output via a low pass filter ( Chroma LPF in the block
diagram ).
Frequency response of each filter is shown below.
4:2:2 to 4:4:4 Interpolator Filter
10
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5
Gain[dB]
-10
-20
-30
-40
-50
Frequency[MHz]
x 2 Interpolator Filter
10
0
Gain[dB]
-10
0.0 1.0 2.0
3.0 4.0 5.0 6.0 7.0 8.0
9.0 10.0 11.0 12.0 13.0
-20
-30
-40
-50
frequency[MHz]
MS0331-E-00
15
2004 / 08
ASAHI KASEI
[AK8815/16]
( 9 ) Color Burst Signal
Burst signal is generated by a 32 bit digital frequency synthesizer.
Color Burst Frequency is selected by mode setting of NTSC / PAL.
Standerd
NTSC-M
Subcarrier Freq
(MHz)
3.57954545
PAL-B,D,G,H,I
4.43361875
Video Process 1
VMOD-bit
0
1
Burst Signal Table
( 10 ) Video DAC
The AK8815/16 has a 9 Bit resolution, current-drive DAC as a video DAC which runs at 29.5 / 24.5454 MHz clock
frequency.
This DAC is designed to output 1.28 V o-p at full scale under the following conditions –
loading resistance of 390 ohms, VREF at 1.23 V and IREF pin resistor of 12 Kohms.
Here IREF pin resistor means a resistor connected between [ IREF ] pin and ground. DAC output voltage can be
adjusted by adjusting IREF pin resistor.
[ VREF ] pin should be connected to ground via a 0.1 uF or larger capacitor.
DAC output can be turned “ON” or “OFF” by register setting and current consumption can be lowered.
When the output is turned off, it is put into high impedance condition.
On-chip VREF circuit is kept active and only the DAC output is turned off then.
MS0331-E-00
16
2004 / 08
ASAHI KASEI
[AK8815/16]
( 11 ) Video Data Interface timing
( 1-1 ) Video interface
The AK8815/16 operates in slave mode which is synchronized with the HSYNC / VSYNC sync signals.
A system operational outline is as follows –
Operation clock of the controller device which feeds data to the video encoder is fed from the video encoder. And
such timing signals as HSYNC and VSYNC of the controller are generated by the same clock timing.
The AK8815/16 synchronizes its operation with the generated HSYNC and VSYNC signals.
C LK
HSYNC
C o n t r o lle r
VSYNC
V id e o E n c o d e r
D a ta
In normal operation, the AK8815/16 checks HSYNC and VSYNC changes at each CLK edge ( CLK
synchronized ).
A Pixel when HSYNC is identified to get low is recognized to be H0 ( zero ), and the 236th data ( NTSC ) or the
310th data ( PAL ) is taken as Cb0 square pixel data.
Video field is recognized by VSYNC relation over HSYNC.
Field recognition is made as follows :
The AK8815/16 distinguishes at every Field if it is Odd Field ( 1st Field ) or not. Even Field Sync signal is not
usually
input.
1 ) When VSYNC timing pulse signal fed to the AK8815/16 becomes low from high while HSYNC input signal is at
low, this Field is interpreted as Odd Field.
The Horizontal line where Odd Field identification is made, functions as Line 4 in NTSC mode and Line 1 in PAL
mode ( even when both VSYNC and HSYNC are identified to get low simultaneously, it is processed as Odd
Field. But it is recommended to input those signals with more than a few clock margin ).
2 ) The AK8815/16 continues operation in self-running mode , based on the sync signals which are fed just before,
if Horizontal / Vertical Sync signals are not fed every time in such timing and pulse count as expected in the
Video Standard Specifications.
But it is recommended to input those sync signals in the specified timing every time in order to prevent
erroneous operation.
3 ) All other VSYNC than those identified to be Odd Field are processed as Even Field.
But a use of VSYNC pulse other than in ODD Field synchronization is not assumed for normal operation.
MS0331-E-00
17
2004 / 08
ASAHI KASEI
[AK8815/16]
( 1- 2 ) Pixel Data in each line
( 1 ) NTSC
1559
0
TBD
236
237
238
239
240
Y0
Cr0
Y1
Cb1
1514
1515
1516
CLKOUT
(24.5454MHz)
D[7:0]
(0x10) (0x80) (0x10) (0x80) (0x10) Cb0
Cr319 Y639 (0x80) (0x10)
H0
HSYNC
Active Video Area
640 2 Clock
* ) when D [7:0], HSYNC and CLKOUT are in same phase relation as a timing example above, the AK8815/16
takes input data at the falling edge of each CLKOUT if CLKINV = H.
* ) as an input data other than during active video period, Black level ( C / Y = 0x80 / 0x10 ) or other than 0x00 /
0xFF codes in non Hi-Z state should be input.
(2) PAL
1887
0
TBD
310
311
312
313
314
Cb0
Y0
Cr0
Y1
Cb1
1844
1845
1846
CLKOUT
(29.5MHz)
D[7:0]
(0x10? (0x80) (0x10) (0x80) (0x10)
Cr383 Y767 (0x80) (0x10)
H0
HSYNC
Active Video Area
768 2 Clock
* ) when D [7:0], HSYNC and CLKOUT are in same phase relation as a timing example above, the AK8815/16
takes input data at the falling edge of each CLKOUT if INV = H.
* ) as an input data other than during active video period, Black level ( C / Y = 0x80 / 0x10 ) or other than 0x00 /
0xFF codes in non Hi-Z state should be input.
MS0331-E-00
18
2004 / 08
ASAHI KASEI
[AK8815/16]
( 1-3 ) HSYNC and VSYNC relation in each Frame
( 1 ) NTSC ( Frame ) 525 Line 480 active lines
The First Field ( ODD )
263 lines
240 lines
525
1
2
3
4
5
6
7
22
23
261
262
263
264
1
2
HSYNC
VSYNC
* ) VSYNC negative-going occurs during HSYNC = L at Line 4.
VSYNC positive-going can occurs at arbitrary location, but keep VSYNC low for 3 line duration time as a rough idea.
The Second Field ( EVEN )
262 lines
240 lines
263
264
265
266
267
268
269
270
285
286
524
525
HSYNC
VSYNC
High
* ) VSYNC negative-going is not required for the Second Field. It is required for the First Field only.
When VSYNC is input in the specified timing (described below ) at the Second Field, the line and the field are set once as the Second Field.
But since the Burst cycle etc. is referenced to the First Field, VSYNC synchronization
cannot be made with the Second Field only. System synchronization must be made to reference the VSYNC synchronization at the First Field.
When to input VSYNC at the Second Field, it should be done after the first 1/2 H of the 266th Line and before the falling edge of the 267th HSYNC ( if HSYNC falling
edge timing of the 266th Line is counted as the 0th clock, VSYNC should be fallen after the 780th Clock and before the 1559th Clock ).
MS0331-E-00
19
2004 / 08
ASAHI KASEI
[AK8815/16]
( 2 ) PAL ( Frame ) 625 Line
The First Field ( ODD )
576 active lines
313 lines
288 lines
625
1
2
3
4
5
22
23
24
310
311
312
313
314
HSYNC
VSYNC
* ) VSYNC negative-going occurs during HSYNC = L at Line 1.
VSYNC positive-going can occur at arbitrary location, but as a rough idea, keep VSYNC low for 2.5, or 2 or 3 line duration time.
The Second Field ( EVEN )
313 lines
288 lines
313
314
315
316
317
318
335
336
337
623
624
625
1
2
HSYNC
VSYNC
High
* ) VSYNC negative-going is not required for the Second Field. It is required for the First Field only.
When VSYNC is input in the specified timing (described below) at the Second Field, the line and the field are set once as the Second Field.
But since the Burst cycle etc. is referenced to the First Field, VSYNC synchronization cannot be made at the Second Field only.
System synchronization must be made to reference the VSYNC synchronization at the First Field.
When to input VSYNC at the Second Field, it should be done after the first 1/2 H of the 313th Line and before the falling edge of the 314th HSYNC ( if HSYNC falling
edge timing of the 313th line is counted as the 0th clock, VSYNC should be fallen after the 944th clock and before the 1887th clock ).
MS0331-E-00
20
2004 / 08
ASAHI KASEI
[AK8815/16]
( 2-1 ) SYNC Signal waveform, Burst Waveform generator
( 2-1-1 ) NTSC-J
S y n c r is e t im e
50%
B u r s t H e ig h t
90%
B u rs t
H o r iz o n ta l
r e f e r e n c e p o in t
50%
50%
S ync Le ve l
10%
S yn c
H . r e f . t o B u r s t S ta r t
measurement
point
Total line period(derived)
Sync Level
Sync rise time
Horizontal Sync width
Horizontal reference point to
burst start
Burst *
Burst Height **
value
Consumer Quality
tolerance
units
10% - 90%
50%
63.556
40
140
4.7
+/- 3
Max 250
+/- 0.1
usec
IRE
nsec
usec
50%
19
defined by SC/H
cycles
50%
9
40
+/- 1
+/- 3
cycles
IRE
* there is a case where tolerance of Sync rise time is added to Sync width tolerance.
* Measurement of Burst time length is made between the Burst start point which is defined as the zero-cross
point, preceding the first half-cycle of the sub-carrier where Burst amplitude becomes higher than 50 % level and
the Burst end point, defined in the same manner.
19 cycles +/-40°
9 cycles +/- 1cycle
50%
NTSC Signal
MS0331-E-00
21
2004 / 08
ASAHI KASEI
[AK8815/16]
( 2-1-2 ) Vertical Sync Signal timing ( NTSC )
3H
3H
3H
0 .5 H
1
2
3
4
5
3H
6
7
8
3H
9
21
3H
0 .5 H
263
264
265
266
267
268
269
270
271
G
I
272
273
285
H
I
I
I
40IRE
+/-3IRE
Equalizing Pulse
Serration Pulse
Equalizing Pulse and Serration Pulse
Symbol
G
H
G
I
Pre-equalizing pulse width
Vertical serration pulse width
Post-equalizing pulse width
Sync rise time
Measurement
point
50%
50%
50%
Value
2.3
4.7
2.3
140
Recommended
tolerance
+/- 0.1
+/- 0.2
+/- 0.1
Max 250
units
usec
usec
usec
nsec
* there is a case where tolerance of Sync rise time is added to Pulse width tolerance.
MS0331-E-00
22
2004 / 08
ASAHI KASEI
[AK8815/16]
( 2-1-3 ) PAL-B, D, G, H, I
S y n c r is e t im e
50%
B u r s t H e ig h t
90%
B u rs t
H o r iz o n ta l
r e f e r e n c e p o in t
50%
50%
S yn c L e ve l
10%
H o r iz o n ta l S y n c
H . r e f . t o B u r s t S ta r t
measurement
point
Total line period(derived)
Sync Level
Sync rise time
Horizontal Sync width
Horizontal reference point to
burst start
Burst *
Burst Height **
value
Consumer Quality
tolerance
units
10% - 90%
50%
64.0
300
0.2
4.7
+/- 20
Max 0.3
+/- 0.2
usec
mV
usec
usec
50%
5.6
+/- 0.1
usec
50%
10
300
+/- 1
+/- 30
cycles
mV
* there is case where tolerance of Sync rise time is added to Sync width tolerance.
MS0331-E-00
23
2004 / 08
ASAHI KASEI
[AK8815/16]
( 2-1-4 ) Vertical Sync Signal timing and Burst Phase PAL-B, D, G, H, I
PAL-B,D,G,H,I
A
308
620
309
621
308
620
310
622
309
311
623
310
621
622
312
624
311
623
313
625
312
624
314
1
313
625
315
2
314
1
316
3
315
2
317
4
316
3
318
5
317
4
319
320
A
B
6
7
A
B
318
319
A
B
5
B
7
322
321
322
8
320
6
321
8
A : Phase of Burst : nominal Value + 135°
B : Phase of Burst : nominal Value - 135°
Since Burst frequency and Line frequency are not practically in integer-multiple relation, specified phase value is
not exactly 135 degrees.
Diagram below shows phase direction.
G
I
H
I
I
I
300mV
+/-30mV
Equalizing Pulse
Serration Pulse
Equalizing Pulse and Serration Pulse
Symbol
G
H
G
I
Pre-equalizing pulse width
Vertical serration pulse width
Post-equalizing pulse width
Sync rise time
Measurement
point
50%
50%
50%
Value
2.35
4.7
2.35
200
Recommended
tolerance
+/- 0.1
+/- 0.2
+/- 0.1
Max 300
units
usec
usec
usec
nsec
* there is a case where tolerance of Sync rise time is added to Pulse width tolerance.
MS0331-E-00
24
2004 / 08
ASAHI KASEI
[AK8815/16]
( 12 ) On-chip Color Bar
The AK8815/16 can output Color Bar signal.
Color Bar signal to be generated has 100 % amplitude and 100 % Saturation levels.
Color Bar signal is output by setting register.
When to output Color Bar signal, there are 2 modes of operation – one is external Sync timing mode for normal
operation, and the other is internal self-operation mode.
In internal self-operating mode, required timing is internally generated automatically. Namely, it is no need to
input synchronization timing from outside of the chip.
Operation mode setting is done by Mode Register.
When BBG-bit is set, BBG-bit is prioritized ( Black Burst is output ).
BLACK
BLUE
RED
MAGENTA
GREEN
CYAN
YELLOW
WHITE
100%White
Blanking Level
Synctip Level
The following values are code for ITU-R. BT601
WHITE
YELLOW
CYAN
Cb
Y
Cr
128
235
128
15/16
210
146
15/166
170
15/16
GREEN
54
145
34
MAGENT
A
202
106
222
RED
BLUE
BLACK
90
81
240
240
41
110
128
15/16
128
( 13 ) Black Burst Signal generation function
The AK8815/16 can output Black Burst signal ( Black level output ).
When to output Black Burst signal, there are 2 modes of operation – one is external Sync timing mode for
normal operation , and the other is internal self-operation mode.
In internal self-operation mode, required timing is internally generated automatically. Namely, it is no need to
input synchronization timing from outside of the chip.
When BBG-bit of [ Mode Register ] is set to “1”, same operation is processed as in the case where fixed-15/16 Y
signal and fixed-128 Pb / Pr signal outputs are input.
Operation mode setting is done by Mode Register setting.
MS0331-E-00
25
2004 / 08
ASAHI KASEI
[AK8815/16]
(14) Video ID
The AK8815/16 supports to encode the Video ID ( EIAJ CPR-1204 ) which distinguishes the aspect ratio etc..
This is also used as CGMS ( Copy Generation Management System ).
Turning “ON/OFF” of this function is made by setting both VMOD-bit = 0 and VBID-bit = 1 of { Mode Register
(0x00) }. And data to be set is written into { VBID / WSS Data1 & 2 Registers ( 0x01,0x02 )}.
Video ID information is the highest order of priority information among VBI information ( when simultaneous
outputs occur with Macrovision signaling, only the VBI information is super-imposed on this line ).
VBID Data Update timing .
VSYNC
S et C ontro l R egister
u-P D a ta
N EW D AT A
DATA
O LD D A T A
N EW D AT A
VBID Code assignment
20 bit data is configured with WORD0 = 2 bit, WORD1 = 4 bit, WORD2 = 8 bit and CRC = 6 bit.
CRC is automatically calculated and added by the AK8815/16.
Default values of CRC polynomial expression X6 + X + 1 are all ones.
-data configuration
bit1
bit20
DATA
WORD0
2bit
WORD1
4bit
WORD2
8bit
CRC
6bit
VBID Waveform
Ref.
•••
bit1 bit2 bit3
bit20
70IRE +/- 10IRE
0IRE + 10 IRE
− 5 IRE
2.235usec +/- 50nsec
11.2usec +/- 0.3usec
49.1usec +/- 0.44usec
1H
525/60 System
70IRE
20/283
Amplitude
Encode Line
MS0331-E-00
26
2004 / 08
ASAHI KASEI
[AK8815/16]
( 15 ) WSS function
The AK8815/16 supports to encode the WSS ( ITU-R. BT.1119 ) which distinguishes the aspect ratio and sets
CGMS-A etc..
Turning “ON/OFF“ of this function is made by setting both VMOD-bit = 1 and WSS-bit = 1 of { Mode Register
( 0x00 ) }. And data to be set is written into { VBID / WSS Data1 & 2 Registers ( 0x01, 0x02 )}.
WSS Data Update timing
VSYNC
S et C ontro l R egister
u-P D a ta
N EW D AT A
DATA
O LD D A T A
N EW D AT A
WSS Waveform
500mV +/- 5%
0H
27.4usec
1.5usec
10.5usec
11.0 +/- 0.25usec
38.4usec
44.5usec
Encode line : former half of Line 23 ( Blank output during latter half )
Coding : Bi-phase modulation coding
Clock : 5 MHz ( Ts = 200 nS )
Encoding details as follows
Run-in
Start code
29 elements
24 elements
0x1F1C71C7
0x1E3C1F
MS0331-E-00
Group 2
Enhanced
Services
24 elements
Bit numbering
4 5 6 7
LSB
MSB
0 : 000111
1 : 111000
Group 1
Aspect ratio
24 elements
Bit numbering
0 1 2 3
LSB
MSB
0 : 000111
1 : 111000
27
Group 3
Subtitles
18 elements
Bit numbering
8 9 10
LSB MSB
0 : 000111
1 : 111000
Group4 Reserved
18 elements
Bit numbering
11 12 13
LSB MSB
0 : 000111
1 : 111000
2004 / 08
ASAHI KASEI
[AK8815/16]
POWER UP SEQUENCE
Power-Up Sequence ( power supply turn-on sequence )
AVDD
DVDD
PVDD1
PVDD2
PDN
RSTN
SCL
Hi-Z ok
Low
XTI
VREF
raise RSTN high after crystal resonator oscillation is stabilized ~ 5 mS
POWER ON
raise RSTN high after VREF is stabilized >= 10 mS (min.)
Power-Down Release sequence
AVDD/DVDD
PVDD1/PVDD2
PDN
RSTN
SCL
Hi-Z ok
Low
XTI
VREF
raise RSTN high after crystal resonator oscillation is stabilized ~ 5 mS
raise RSTN high after VREF is stabilized >= 10 mS (min.)
PDN off
MS0331-E-00
28
2004 / 08
ASAHI KASEI
[AK8815/16]
DEVICE CONTROL SEQUENCE
Device Control Interface
following modes of operations are controlled via 4-wire serial interface.
Hi-Z inputs to CS, SCLK, and SDI pins are inhibited, except at power-down ( PDN pin = low ).
Write Sequence: A5=0
CS
SCLK
SDI
A7
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
0
Read Sequence: A5=1
CS
SCLK
SDI
A7
A6
A5
A4
A3
A2
A1
A0
1
SDO
High
D7
D6
D5
D4
D3
D2
D1
D0
High
A5 bit becomes an identification tab A5 1 : Read
A5 0 : Write
CS must be set to low at every address change.
MS0331-E-00
29
2004 / 08
ASAHI KASEI
[AK8815/16]
REGISTER MAP
Address
0x00
0x01
0x02
0x03
0x04
Register
Mode Register
VBID/WSS Data 1 Register
VBID/WSS Data 2 Register
Device ID and Revision ID Register
Reserved
Default
0x00
0x00
0x00
0x06
0x00
R/W
R/W
R/W
R/W
R
R/W
0x05
Input Control Register
0x00
R/W
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0x0f
0xfc
0x20
0xd0
0x6f
0x0f
0x00
0x00
0x0c
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x10
0x11
0x12
0x13
0x14
0x15
0x15/16
0x17
0x18
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0xe3
0xf3
0x09
0xbd
0x66
0xb5
0x90
0xb2
0x7d
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
MS0331-E-00
30
Function
Mode set Register
VBID data is set, WSS data is set
VBID data is set, WSS data is set
Register for Device ID and Revision ID
input control register for out-of-standard quality input
signal
2004 / 08
ASAHI KASEI
[AK8815/16]
Mode Register (R/W) [Address 0x00]
Default Value 0x00
Sub Address 0x00
bit 7
DAC
bit 6
BBG
bit 5
CBG
0
0
0
bit 4
bit 3
MAS
WSS
Default Value
0
0
bit 2
VBID
bit 1
SCR
bit 0
VMOD
0
0
0
SYS1_REG Definition
BIT
Register Name
bit 0
VMOD
bit 1
R/W
Video Mode bit
R/W
SCR
Sub-Carrier Reset bit
R/W
bit 2
VBID
VBID Set Register
R/W
bit 3
WSS
WSS Set Register
R/W
bit 4
MASMD
Master Mode bit
R/W
bit 5
CBG
Color Bar Generator bit
R/W
bit 6
BBG
Black Burst Generator
bit
R/W
bit 7
DAC
DAC Set bit
R/W
MS0331-E-00
Definition
0: NTSC
1: PAL
0: Sub-Carrier Reset off
1: Sub-Carrier Reset
0: VBID OFF
1: VBID ON
0: WSS OFF
1: WSS ON
Master Mode bit to set Sync mode when Color Bar signal and
Black Burst signal are generated
0 : operation by an external Sync timing
1 : operation by an internal self-operating mode ( master mode )
0: OFF
1: ON
when BBG is set, BBG is prioritized.
0: OFF
1: ON
0: DAC OFF
1: DAC ON
31
2004 / 08
ASAHI KASEI
[AK8815/16]
VBID/WSS 1 Register (R/W) [Address 0x01]
VBID/WSS 2 Register (R/W) [Address 0x02]
Video ID and WSS data setting are made. A common data register is used for both video ID and WSS data.
When VBID bit of mode register is set in NTSC mode, data is for VBID data ,and when WSS bit of mode
register is set in PAL mode, data is for WSS data.
When VBID-bit is “1” and VMOD-bit is “0” in mode register, the following bits are assigned.
default Value 0x00
Sub Address 0x01
bit 7
VBID7
bit 6
VBID8
bit 5
VBID9
0
0
0
bit 7
Reserved
bit 6
Reserved
bit 5
VBID1
0
0
0
bit 4
bit 3
VBID10
VBID11
Default Value
0
0
bit 2
VBID12
bit 1
VBID13
bit 0
VBID14
0
0
0
bit 4
bit 3
VBID2
VBID3
Default Value
0
0
bit 2
VBID4
bit 1
VBID5
bit 0
VBID6
0
0
0
Sub Address 0x02
default Value 0x00
Note ) “0” should be written into reserved bits.
VBID1 ---- VBID14 above correspond to the bit 1 ---- bit 14 which are described at { VBID Data Code Assignment }
in { ( 14 ) Video ID } section.
A 6-bit CRC code from bit 15 ~ bit 20 is automatically added by the AK8815/16.
Data is retained till data is updated to a new one.
Following bits are assigned when WSS-bit is “1” and VMOD-bit is “1” in mode register.
Sub Address 0x01
bit 7
G2-7
bit 6
G2-6
bit 5
G2-5
0
0
0
bit 7
Reserved
bit 6
Reserved
bit 5
G4-13
0
0
0
default Value 0x00
bit 4
bit 3
G2-4
G1-3
Default Value
0
0
bit 2
G1-2
bit 1
G1-1
bit 0
G1-0
0
0
0
bit 4
bit 3
G412
G4-11
Default Value
0
0
bit 2
G3-10
bit 1
G3-9
bit 0
G3-8
0
0
0
Sub Address 0x02
default Value 0x00
Note ) WSS data is written with 0x01 first, then 0x02 in this order.
When the 2nd byte ( 0x02 ) of WSS data is written, the AK8815/16 interprets that data is updated to a new one and
then encodes it to the next video line ( Line 23 ).
Data is retained till data is updated to a new one.
MS0331-E-00
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ASAHI KASEI
[AK8815/16]
Device ID and Revision ID Register (R) [Address 0x03]
Sub Address 0x03
bit 7
REV3
0
default Value 0x06
bit 6
REV2
0
bit 5
REV1
0
bit 4
REV0
0
bit 3
DEV3
0
bit 2
DEV2
1
bit 1
DEV1
1
bit 0
DEV0
0
Device ID and Revision ID Register Definition
BIT
bit 0
~
bit 3
bit 4
~
bit 7
Register Name
DEV0
~
DEV2
REV0
~
REV3
R/W
Definition
Device ID bit
R
Device ID bit to indicate Device ID.
Revision ID bit
R
Revision ID bit to indicate Revision ID. Revision ID is updated
When a possible software modification is made.
It is 0x00.
Reserved Register (R) [Address 0x04]
Sub Address 0x03
bit 7
Reserved
0
default Value 0x00
bit 6
Reserved
0
bit 5
Reserved
0
bit 4
Reserved
0
bit 3
Reserved
0
bit 2
Reserved
0
bit 1
Reserved
0
bit 2
HD2
0
bit 1
HD1
0
bit 0
Reserved
0
Device ID and Revision ID Register Definition
BIT
bit 0
~
bit 7
Register Name
Reserved
Reserved bit
R/W
Definition
R/W
Reserved
Input Control Register (R/W) [Address 0x05]
This is an out-of-standard quality input signal control register.
Sub Address 0x05
bit 7
FLT
0
default Value 0x00
bit 6
CBCR
0
bit 5
VD2
0
bit 4
VD1
0
bit 3
VD0
0
bit 0
HD0
0
Adjustment of Sync input timing is made
BIT
bit 0
~
bit 2
bit 3
~
bit 5
bit 6
Register Name
HD0
~
HD2
VD0
~
VD2
CBCR
bit 7
FLT
MS0331-E-00
R/W
Definition
HSYNC Input Delay
R/W
HSYNC signal input is delayed by the set value.
HD [ 2:0 ] system clock count delay ( + 0 ~ + 7 CLK delay )
VSYNC Input Delay
R/W
VD0 ~ VD2 VSYNC Input Delay
VSYNC signal input is delayed by the set value.
VD [ 2:0 ] system clock count delay ( + 0 ~ + 7 CLK delay )
Exchange CbCr
R/W
Y Flat Data
R/W
Cb, Cr timing data are interchanged at CBCR = 1.
Y input data is linear- interpolated
( averaging most adjacent data ).
33
2004 / 08
ASAHI KASEI
[AK8815/16]
SYSTEM CONNECTION EXAMPLE
AK8816
PVDD1
PVSS1
Amp + LPF
VIDEOOUT
HSYNC
VSYNC
D[7:0]
390Ω
75Ω
CLKOUT
PVDD2
PVSS2
SDI
SCLK
CS
RSTN
PDN
SDO
VREF
0.1uF
DVCC
DVSS
TEST
IREF
ATPG
12kΩ
CLKINV
CLKMD
XTI
XTO
AVSS
AVDD
Analog
18pF
MS0331-E-00
0.1uF
10uF
22pF
34
2004 / 08
ASAHI KASEI
[AK8815/16]
PACKAGE
Package Outline dimension
57 pin FBGA
-package drawing
5.0 ± 0.1
A
57 − Φ0.3 ± 0.05
Φ0.05 M S AB
5 4 3 2 1
1
A
B
C
D
E
B
F
G
H
J
4.0
5.0 ± 0.1
9 8 7 6
0.5
4.0 = 0.5×8
0.5
S
SEATING PLANE
0.89 ± 0.1
0.25 ± 0.05
0.08 S
Package & Lead frame material
Package molding compound: Epoxy
Interposer material: BT resin
MS0331-E-00
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2004 / 08
ASAHI KASEI
[AK8815/16]
MARKING
8816
XXXXX
a. Package type : BGA
b. Pin count : 57 pins ( 1 pin for index )
c. Product number : 8815
d. Factory control code : xxxxx ( 5 digits )
MS0331-E-00
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2004 / 08
ASAHI KASEI
[AK8815/16]
IMPORTANT NOTICE
• These products and their specifications are subject to change without notice. Before considering any use or
application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning
their current status.
• AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use
of any information contained herein.
• Any export of these products, or devices or systems containing them, may require an export license or other official
approval under the law and regulations of the country of export pertaining to customs and tariffs, currency
exchange, or strategic materials.
• AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other
hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the
express written consent of the Representative Director of AKM. As used here:
(a) A hazard related device or system is one designed or intended for life support or maintenance of safety
or for applications in medicine, aerospace, unclear energy, or other fields, in which its failure to function
or perform may reasonably be expected to result in loss of life or in significant injury or damage to
person or property.
(b) A critical component is one whose failure to function or perform may reasonably be expected to result,
whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing
it, and which must therefore meet very high standards of performance and reliability.
• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places
the product with a third party to notify that party in advance of the above content and conditions, and the buyer or
distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all
claims arising from the use of said product in the absence of such notification.
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