AMD D163DB70PI 16 megabit (2 m x 8-bit/1 m x 16-bit) cmos 3.0 volt-only, simultaneous operation flash memory Datasheet

Am29DL16xD
Data Sheet
July 2003
The following document specifies Spansion memory products that are now offered by both Advanced
Micro Devices and Fujitsu. Although the document is marked with the name of the company that originally developed the specification, these products will be offered to customers of both AMD and
Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal datasheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appropriate,
and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order
these products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion
memory solutions.
Publication Number 21533 Revision E
Amendment +4 Issue Date May 26, 2004
THIS PAGE LEFT INTENTIONALLY BLANK.
Am29DL16xD
16 Megabit (2 M x 8-Bit/1 M x 16-Bit)
CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory
DISTINCTIVE CHARACTERISTICS
ARCHITECTURAL ADVANTAGES
— 10 mA active read current at 5 MHz
— 200 nA in standby or automatic sleep mode
■ Simultaneous Read/Write operations
— Data can be continuously read from one bank while
executing erase/program functions in other bank
— Zero latency between read and write operations
■ Minimum 1 million write cycles guaranteed per sector
■ Multiple bank architectures
— Four devices available with different bank sizes (refer
to Table 2)
SOFTWARE FEATURES
■ SecSi™ (Secured Silicon) Sector
— Current version of device has 64 Kbytes; future
versions will have 256 bytes
— Factory locked and identifiable: 16 bytes available for
secure, random factory Electronic Serial Number;
verifiable as factory locked through autoselect
function. ExpressFlash option allows entire sector to
be available for factory-secured data
— Customer lockable: Can be read, programmed, or
erased just like other sectors. Once locked, data
cannot be changed
■ 20 Year data retention at 125°C
— Reliable operation for the life of the system
■ Data Management Software (DMS)
— AMD-supplied software manages data programming
and erasing, enabling EEPROM emulation
— Eases sector erase limitations
■ Supports Common Flash Memory Interface (CFI)
■ Erase Suspend/Erase Resume
— Suspends erase operations to allow programming in
same bank
■ Data# Polling and Toggle Bits
— Provides a software method of detecting the status of
program or erase cycles
■ Zero Power Operation
— Sophisticated power management circuits reduce
power consumed during inactive periods to nearly
zero
■ Unlock Bypass Program command
— Reduces overall programming time when issuing
multiple program command sequences
■ Package options
— 48-ball Very Thin Profile Fine-pitch BGA
— 48-ball Fine-pitch BGA
— 64-ball Fortified BGA
— 48-pin TSOP
■ Any combination of sectors can be erased
■ Top or bottom boot block
■ Manufactured on 0.23 µm process technology
— Compatible with Am29DL16xC devices
■ Compatible with JEDEC standards
— Pinout and software compatible with
single-power-supply flash standard
PERFORMANCE CHARACTERISTICS
■ High performance
— Access time as fast 70 ns
— Program time: 7 µs/word typical utilizing Accelerate function
■ Ultra low power consumption (typical values)
— 2 mA active read current at 1 MHz
HARDWARE FEATURES
■ Ready/Busy# output (RY/BY#)
— Hardware method for detecting program or erase
cycle completion
■ Hardware reset pin (RESET#)
— Hardware method of resetting the internal state
machine to reading array data
■ WP#/ACC input pin
— Write protect (WP#) function allows protection of two
outermost boot sectors, regardless of sector protect status
— Acceleration (ACC) function accelerates program
timing
■ Sector protection
— Hardware method of locking a sector, either
in-system or using programming equipment, to
prevent any program or erase operation within that
sector
— Temporary Sector Unprotect allows changing data in
protected sectors in-system
This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data
Sheet may be revised by subsequent versions or modifications due to changes in technical specifications.
Publication# 21533 Rev: E Amendment/+4
Issue Date: May 26, 2004
Refer to AMD’s Website (www.amd.com) for the latest information.
GENERAL DESCRIPTION
The Am29DL16xD family consists of 16 megabit, 3.0
volt-only flash memory devices, organized as 1,048,576
words of 16 bits each or 2,097,152 bytes of 8 bits each.
Word mode data appears on DQ0–DQ15; byte mode
data appears on DQ0–DQ7. The device is designed to
be programmed in-system with the standard 3.0 volt
VCC supply, and can also be programmed in standard
EPROM programmers.
The device is available with an access time of 70, 90,
or 120 ns. The devices are offered in 48-pin TSOP,
48-ball Fine-pitch BGA, 48-ball Very Thin Profile
Fine-pitch BGA, and 64-ball Fortified BGA packages.
Standard control pins—chip enable (CE#), write enable (WE#), and output enable (OE#)—control normal
read and write operations, and avoid bus contention
issues.
The device requires only a single 3.0 volt power supply for both read and write functions. Internally
generated and regulated voltages are provided for the
program and erase operations.
Simultaneous Read/Write Operations with
Zero Latency
The Simultaneous Read/Write architecture provides
simultaneous operation by dividing the memory
space into two banks. The device can improve overall
system performance by allowing a host system to program or erase in one bank, then immediately and
simultaneously read from the other bank, with zero latency. This releases the system from waiting for the
completion of program or erase operations.
The Am29DL16xD devices uses multiple bank architectures to provide flexibility for different applications.
Four devices are available with these bank sizes:
Device
DL161
DL162
DL163
DL164
Bank 1
0.5 Mb
2 Mb
4 Mb
8 Mb
Bank 2
15.5 Mb
14 Mb
12 Mb
8 Mb
DMS (Data Management Software) allows systems
to easily take advantage of the advanced architecture
of the simultaneous read/write product line by allowing
removal of EEPROM devices. DMS will also allow the
system software to be simplified, as it will perform all
functions necessary to modify data in file structures,
as opposed to single-byte modifications. To write or
update a particular piece of data (a phone number or
configuration data, for example), the user only needs
to state which piece of data is to be updated, and
where the updated data is located in the system. This
i s a n a d va n t a g e c o m p a r e d t o s ys te m s w h e r e
user-written software must keep track of the old data
location, status, logical to physical translation of the
data onto the Flash memory device (or memory devices), and more. Using DMS, user-written software
does not need to interface with the Flash memory directly. Instead, the user's software accesses the Flash
memory by calling one of only six functions. AMD provides this software to simplify system design and
software integration efforts.
The device offers complete compatibility with the
JEDEC single-power-supply Flash command set
standard. Commands are written to the command
register using standard microprocessor write timings.
Reading data out of the device is similar to reading
from other Flash or EPROM devices.
The host system can detect whether a program or
erase operation is complete by using the device status bits: RY/BY# pin, DQ7 (Data# Polling) and
DQ6/DQ2 (toggle bits). After a program or erase cycle
has been completed, the device automatically returns
to reading array data.
The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.
Am29DL16xD Features
The SecSi™ (Secured Silicon) Sector is an extra sector capable of being permanently locked by AMD or
customers. The SecSi Sector Indicator Bit (DQ7) is
permanently set to a 1 if the part is factory locked,
and set to a 0 if customer lockable. This way, customer lockable parts can never be used to replace a
factory locked part. Current version of device has 64
Kbytes; future versions will have only 256 bytes.
This should be considered during system design.
Factory locked parts provide several options. The
SecSi Sector may store a secure, random 16 byte
ESN (Electronic Serial Number), customer code (programmed through AMD’s ExpressFlash service), or
4
both. Customer Lockable parts may utilize the SecSi
Sector as bonus space, reading and writing like any
other flash sector, or may permanently lock their own
code there.
Hardware data protection measures include a low
V CC detector that automatically inhibits write operations during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of the sectors of memo r y. T h i s c a n b e a c h i ev e d i n - s y s t e m o r v i a
programming equipment.
The device offers two power-saving features. When
addresses have been stable for a specified amount of
time, the device enters the automatic sleep mode.
The system can also place the device into the
standby mode. Power consumption is greatly reduced in both modes.
Am29DL16xD
May 26, 2004
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 6
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 7
Sector Erase Command Sequence .............................................. 27
Erase Suspend/Erase Resume Commands ................................ 28
Special Package Handling Instructions .......................................... 9
Command Definitions ................................................................... 29
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Ordering Information . . . . . . . . . . . . . . . . . . . . . . 11
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 12
Table 1. Am29DL16xD Device Bus Operations ....................................12
Word/Byte Configuration .............................................................. 12
Requirements for Reading Array Data .........................................12
Writing Commands/Command Sequences .................................. 13
Accelerated Program Operation ...............................................13
Autoselect Functions .................................................................13
Simultaneous Read/Write Operations with Zero Latency ............13
Standby Mode .............................................................................. 13
Automatic Sleep Mode .................................................................13
RESET#: Hardware Reset Pin .....................................................14
Output Disable Mode ...................................................................14
Table 2. Am29DL16xD Device Bank Divisions .....................................14
Table 3. Sector Addresses for Top Boot Sector Devices ......................15
Table 4. SecSi™ Sector Addresses for Top Boot Devices .................. 15
Table 5. Sector Addresses for Bottom Boot Sector Devices .................16
Table 6. SecSi™ Addresses for Bottom Boot Devices ........................ 16
Autoselect Mode .......................................................................... 17
Table 7. Am29DL16xD Autoselect Codes, (High Voltage Method) ......17
Sector/Sector Block Protection and Unprotection ........................ 18
Figure 4. Erase Operation .................................................................... 28
Table 14. Am29DL16xD Command Definitions .................................... 29
Write Operation Status . . . . . . . . . . . . . . . . . . . . 30
DQ7: Data# Polling ...................................................................... 30
Figure 5. Data# Polling Algorithm ......................................................... 30
RY/BY#: Ready/Busy# ................................................................. 31
DQ6: Toggle Bit I .......................................................................... 31
Figure 6. Toggle Bit Algorithm .............................................................. 31
DQ2: Toggle Bit II ......................................................................... 32
Reading Toggle Bits DQ6/DQ2 .................................................... 32
DQ5: Exceeded Timing Limits ...................................................... 32
DQ3: Sector Erase Timer ............................................................. 32
Table 15. Write Operation Status ......................................................... 33
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 34
Figure 7. Maximum Negative Overshoot Waveform ............................. 34
Figure 8. Maximum Positive Overshoot Waveform ............................. 34
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 34
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 9. ICC1 Current vs. Time (Showing Active and Automatic
Sleep Currents)..................................................................................... 36
Figure 10. Typical ICC1 vs. Frequency................................................... 36
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 11. Test Setup .......................................................................... 37
Table 16. Test Specifications ................................................................ 37
Key To Switching Waveforms ...................................................... 37
Table 8. Top Boot Sector/Sector Block Addresses
for Protection/Unprotection ...................................................................18
Table 9. Bottom Boot Sector/Sector Block Addresses
for Protection/Unprotection ...................................................................18
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 38
Write Protect (WP#) .....................................................................19
Temporary Sector/Sector Block Unprotect ...................................19
Word/Byte Configuration (BYTE#) ............................................... 40
Figure 1. Temporary Sector Unprotect Operation ................................. 19
Figure 2. In-System Sector/Sector Block Protection and
Unprotection Algorithms........................................................................ 20
SecSi™ (Secured Silicon) Sector Flash Memory Region ............21
Factory Locked: SecSi Sector Programmed and Protected At the
Factory ......................................................................................21
Customer Lockable: SecSi Sector NOT Programmed or
Protected At the Factory ...........................................................21
Hardware Data Protection ............................................................ 21
Low VCC Write Inhibit ...............................................................22
Write Pulse “Glitch” Protection .................................................. 22
Logical Inhibit ............................................................................22
Power-Up Write Inhibit .............................................................. 22
Common Flash Memory Interface (CFI) . . . . . . . 22
Table 10. CFI Query Identification String ..............................................
Table 11. System Interface String.........................................................
Table 12. Device Geometry Definition ..................................................
Table 13. Primary Vendor-Specific Extended Query ............................
22
23
23
24
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 25
Figure 12. Input Waveforms and Measurement Levels ........................ 37
Figure 13. Read Operation Timings...................................................... 38
Figure 14. Reset Timings...................................................................... 39
Figure 15. BYTE# Timings for Read Operations .................................. 40
Figure 16. BYTE# Timings for Write Operations .................................. 40
Erase and Program Operations ................................................... 41
Figure 17. Program Operation Timings ................................................
Figure 18. Accelerated Program Timing Diagram ................................
Figure 19. Chip/Sector Erase Operation Timings .................................
Figure 20. Back-to-back Read/Write Cycle Timings .............................
Figure 21. Data# Polling Timings (During Embedded Algorithms) .......
Figure 22. Toggle Bit Timings (During Embedded Algorithms) ............
Figure 23. DQ2 vs. DQ6 .......................................................................
42
42
43
44
44
45
45
Temporary Sector/Sector Block Unprotect ................................... 46
Figure 24. Temporary Sector/Sector Block Unprotect Timing Diagram 46
Figure 25. Sector/Sector Block Protect and Unprotect Timing Diagram 47
Alternate CE# Controlled Erase and Program Operations ........... 48
Figure 26. Alternate CE# Controlled Write (Erase/Program)
Operation Timings ................................................................................ 49
Erase And Programming Performance . . . . . . .
Latchup Characteristics . . . . . . . . . . . . . . . . . . . .
Package and Pin Capacitance . . . . . . . . . . . . . . .
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . .
50
50
50
50
Reading Array Data ...................................................................... 25
Reset Command .......................................................................... 25
Autoselect Command Sequence .................................................. 25
Enter SecSi™ Sector/Exit SecSi Sector Command Sequence ....26
Byte/Word Program Command Sequence ...................................26
Unlock Bypass Command Sequence .......................................26
FBC048—48-Ball Fine-Pitch Ball Grid Array
8 x 9 mm package ........................................................................ 51
LAA064—64-Ball Fortified Ball Grid Array,
13 x 11 mm package .................................................................... 52
TS 048—48-Pin Standard TSOP ................................................. 53
VBF048—48-Ball Very Thin Profile Fine-Pitch Ball Grid Array .... 54
Figure 3. Program Operation ................................................................ 27
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 55
Chip Erase Command Sequence .................................................27
May 26, 2004
Am29DL16xD
5
PRODUCT SELECTOR GUIDE
Part Number
Am29DL16xD
Standard Voltage Range: VCC = 2.7–3.6 V
70
90
120
Max Access Time (ns)
70
90
120
CE# Access (ns)
70
90
120
OE# Access (ns)
30
40
50
Speed Option
BLOCK DIAGRAM
RY/BY#
X-Decoder
A0–A19
WE#
CE#
BYTE#
STATE
CONTROL
&
COMMAND
REGISTER
Status
DQ0–DQ15
Control
WP#/ACC
DQ0–DQ15
Lower Bank Address
Lower Bank
Latches and
Control Logic
A0–A19
Y-Decoder
A0–A19
X-Decoder
DQ0–DQ15
RESET#
Upper Bank
DQ0–DQ15
A0–A19
Y-Decoder
Upper Bank Address
A0–A19
Latches and Control Logic
OE# BYTE#
VCC
VSS
OE# BYTE#
6
Am29DL16xD
May 26, 2004
CONNECTION DIAGRAMS
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
WE#
RESET#
NC
WP#/ACC
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
48-Pin Standard TSOP
A16
BYTE#
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
48-Ball Fine-pitch BGA
Top View, Balls Facing Down
A6
B6
D6
E6
F6
G6
BYTE# DQ15/A-1
H6
VSS
A13
A12
A14
A15
A16
A5
B5
C5
D5
E5
F5
G5
H5
A9
A8
A10
A11
DQ7
DQ14
DQ13
DQ6
A4
B4
C4
D4
E4
F4
G4
H4
WE#
RESET#
NC
A19
DQ5
DQ12
VCC
DQ4
A3
B3
C3
D3
E3
F3
G3
H3
A18
NC
DQ2
DQ10
DQ11
DQ3
RY/BY# WP#/ACC
May 26, 2004
C6
A2
B2
C2
D2
E2
F2
G2
H2
A7
A17
A6
A5
DQ0
DQ8
DQ9
DQ1
A1
B1
C1
D1
E1
F1
G1
A3
A4
A2
A1
A0
CE#
OE#
H1
VSS
Am29DL16xD
7
CONNECTION DIAGRAMS
64-Ball Fortified BGA
Top View, Balls Facing Down
A8
B8
C8
D8
E8
F8
G8
H8
NC
NC
NC
NC
VSS
NC
NC
NC
A7
B7
C7
D7
E7
F7
G7
H7
A13
A12
A14
A15
A16
A6
B6
C6
D6
E6
F6
VSS
G6
H6
A9
A8
A10
A11
DQ7
DQ14
DQ13
DQ6
A5
B5
C5
D5
E5
F5
G5
H5
WE#
RESET#
NC
A19
DQ5
DQ12
VCC
DQ4
A4
B4
C4
D4
E4
F4
G4
H4
A18
NC
DQ2
DQ10
DQ11
DQ3
RY/BY# WP#/ACC
8
BYTE# DQ15/A-1
A3
B3
C3
D3
E3
F3
G3
H3
A7
A17
A6
A5
DQ0
DQ8
DQ9
DQ1
A2
B2
C2
D2
E2
F2
G2
H2
A3
A4
A2
A1
A0
CE#
OE#
VSS
A1
B1
C1
D1
E1
F1
G1
H1
NC
NC
NC
NC
NC
NC
NC
NC
Am29DL16xD
May 26, 2004
48-Ball Very Thin Profile Fine-pitch BGA
Top View, Balls Facing Down
A6
B6
C6
D6
E6
F6
G6
BYTE# DQ15/A-1
H6
VSS
A13
A12
A14
A15
A16
A5
B5
C5
D5
E5
F5
G5
H5
A9
A8
A10
A11
DQ7
DQ14
DQ13
DQ6
A4
B4
C4
D4
E4
F4
G4
H4
WE#
RESET#
NC
A19
DQ5
DQ12
VCC
DQ4
A3
B3
C3
D3
E3
F3
G3
H3
A18
NC
DQ2
DQ10
DQ11
DQ3
RY/BY# WP#/ACC
A2
B2
C2
D2
E2
F2
G2
H2
A7
A17
A6
A5
DQ0
DQ8
DQ9
DQ1
A1
B1
C1
D1
E1
F1
G1
A3
A4
A2
A1
A0
CE#
OE#
H1
VSS
Special Package Handling Instructions
Special handling is required for Flash Memory products in molded packages (BGA, TSOP, SO, PLCC,
PDIP). The package and/or data integrity may be comp r o m i s e d i f t h e p a c k a g e b o d y i s ex p o s e d t o
temperatures above 150°C for prolonged periods of
time.
May 26, 2004
Am29DL16xD
9
PIN DESCRIPTION
A0–A19
LOGIC SYMBOL
= 20 Addresses
20
DQ0–DQ14 = 15 Data Inputs/Outputs
A0–A19
DQ15/A-1
= DQ15 (Data Input/Output, word
mode), A-1 (LSB Address Input, byte
mode)
CE#
= Chip Enable
OE#
= Output Enable
WE#
= Write Enable
WP#/ACC
= Hardware Write Protect/
Acceleration Pin
RESET#
RESET#
= Hardware Reset Pin, Active Low
BYTE#
BYTE#
= Selects 8-bit or 16-bit mode
RY/BY#
= Ready/Busy Output
VCC
= 3.0 volt-only single power supply
(see Product Selector Guide for speed
options and voltage supply tolerances)
VSS
= Device Ground
NC
= Pin Not Connected Internally
10
16 or 8
DQ0–DQ15
(A-1)
CE#
OE#
WE#
WP#/ACC
Am29DL16xD
RY/BY#
May 26, 2004
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid
Combination) is formed by a combination of the following:
Am29DL16xD
T
70
E
I
OPTIONAL PROCESSING
Blank = Standard Processing
N
= 16-byte ESN devices
TEMPERATURE RANGE
F
= Industrial (–40°C to +85°C) with Pb-Free Package
I
= Industrial (–40°C to +85°C)
PACKAGE TYPE
E
= 48-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 048)
PC
= 64-Ball Fortified Ball Grid Array
1.0 mm pitch, 13 x 11 mm package (LAA064)
WC = 48-Ball Fine-Pitch Ball Grid Array
0.80 mm pitch, 8 x 9 mm package (FBC048)
VR
= 48-Ball Very Thin Profile Ball Grid Array
0.80 mm pitch, 8.15 x 6.15 mm package (VBF048)
SPEED OPTION
See Product Selector Guide and Valid Combinations
BOOT CODE SECTOR ARCHITECTURE
T
=
Top sector
B
=
Bottom sector
DEVICE NUMBER/DESCRIPTION
Am29DL16xD
16 Megabit (2 M x 8-Bit/1 M x 16-Bit) CMOS Flash Memory, 3.0 Volt-only Read, Program, and Erase
Valid Combinations for TSOP Packages
Order Number
Valid Combinations for FBGA Packages
Order Number
Package Marking
AM29DL161DT70, AM29DL161DB70
AM29DL161DT70, AM29DL161DB70
D161DT70, D161DB70
AM29DL162DT70, AM29DL162DB70
AM29DL162DT70, AM29DL162DB70
D162DT70, D162DB70
AM29DL163DT70, AM29DL163DB70
AM29DL163DT70, AM29DL163DB70
D163DT70, D163DB70
AM29DL164DT70, AM29DL164DB70
AM29DL164DT70, AM29DL164DB70
AM29DL161DT90, AM29DL161DB90
AM29DL161DT90, AM29DL161DB90
AM29DL162DT90, AM29DL162DB90
AM29DL163DT90, AM29DL163DB90
EI,
EF
AM29DL162DT90, AM29DL162DB90
AM29DL163DT90, AM29DL163DB90
D164DT70, D164DB70
PCI,
WCI,
VRI,
PCF,
WCF,
VRF
D161DT90, D161DB90
D162DT90, D162DB90
D163DT90, D163DB90
AM29DL164DT90, AM29DL164DB90
AM29DL164DT90, AM29DL164DB90
D164DT90, D164DB90
AM29DL161DT120, AM29DL161DB120
AM29DL161DT120, AM29DL161DB120
D161DT12, D161DB12
AM29DL162DT120, AM29DL162DB120
AM29DL162DT120, AM29DL162DB120
D162DT12, D162DB12
AM29DL163DT120, AM29DL163DB120
AM29DL163DT120, AM29DL163DB120
D163DT12, D163DB12
AM29DL164DT120, AM29DL164DB120
AM29DL164DT120, AM29DL164DB120
D164DT12, D164DB12
PI,
VI,
UI,
PF,
VF,
UF
Note: Ordering numbers containing PCI are identified on device packages with PI. The same
applies to WCI and VI, as well as VRI and UI.
Valid Combinations
Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability
of specific valid combinations and to check on newly released combinations.
May 26, 2004
Am29DL16xD
11
DEVICE BUS OPERATIONS
This section describes the requirements and use of
the device bus operations, which are initiated through
the internal command register. The command register
itself does not occupy any addressable memory locati on . T he re gi ster is a la tch u sed to store th e
commands, along with the address and data information needed to execute the command. The contents of
Table 1.
the register serve as inputs to the internal state machine. The state machine outputs dictate the function
of the device. Table 1 lists the device bus operations,
the inputs and control levels they require, and the resulting output. The following subsections describe
each of these operations in further detail.
Am29DL16xD Device Bus Operations
DQ8–DQ15
Operation
Addresses
(Note 2)
CE# OE# WE# RESET# WP#/ACC
DQ0– BYTE#
DQ7
= VIH
BYTE#
= VIL
Read
L
L
H
H
L/H
AIN
DOUT
DOUT
Write
L
H
L
H
(Note 3)
AIN
DIN
DIN
VCC ±
0.3 V
X
X
VCC ±
0.3 V
H
X
High-Z High-Z
High-Z
Output Disable
L
H
H
H
L/H
X
High-Z High-Z
High-Z
Reset
X
X
X
L
L/H
X
High-Z High-Z
High-Z
Sector Protect (Note 2)
L
H
L
VID
L/H
SA, A6 = L,
A1 = H, A0 = L
DIN
X
X
Sector Unprotect (Note 2)
L
H
L
VID
(Note 3)
SA, A6 = H,
A1 = H, A0 = L
DIN
X
X
Temporary Sector Unprotect
X
X
X
VID
(Note 3)
AIN
DIN
DIN
High-Z
Standby
DQ8–DQ14 = High-Z,
DQ15 = A-1
Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 8.5–12.5 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SA = Sector Address,
AIN = Address In, DIN = Data In, DOUT = Data Out
Notes:
1. Addresses are A19:A0 in word mode (BYTE# = VIH), A19:A-1 in byte mode (BYTE# = VIL).
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector
Block Protection and Unprotection” section.
3. If WP#/ACC = VIL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector
protection depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block
Protection and Unprotection”. If WP#/ACC = VHH, all sectors will be unprotected.
Word/Byte Configuration
Requirements for Reading Array Data
The BYTE# pin controls whether the device data I/O
pins operate in the byte or word configuration. If the
BYTE# pin is set at logic ‘1’, the device is in word configuration, DQ0–DQ15 are active and controlled by
CE# and OE#.
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output control and gates array data to the output pins. WE#
should remain at V IH . The BYTE# pin determines
whether the device outputs array data in words or
bytes.
If the BYTE# pin is set at logic ‘0’, the device is in byte
configuration, and only data I/O pins DQ0–DQ7 are
active and controlled by CE# and OE#. The data I/O
pins DQ8–DQ14 are tri-stated, and the DQ15 pin is
used as an input for the LSB (A-1) address function.
12
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No command is necessary in this mode to obtain array data.
Standard microprocessor read cycles that assert valid
Am29DL16xD
May 26, 2004
addresses on the device address inputs produce valid
data on the device data outputs. Each bank remains
enabled for read access until the command register
contents are altered.
See “Requirements for Reading Array Data” for more
information. Refer to the AC Read-Only Operations
table for timing specifications and to Figure 13 for the
timing diagram. ICC1 in the DC Characteristics table
represents the active current specification for reading
array data.
Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to VIL, and OE# to VIH.
For program operations, the BYTE# pin determines
whether the device accepts program data in bytes or
words. Refer to “Word/Byte Configuration” for more
information.
The device features an Unlock Bypass mode to facilitate faster programming. Once a bank enters the
Unlock Bypass mode, only two write cycles are required to program a word or byte, instead of four. The
“Word/Byte Configuration” section has details on programming data to the device using both standard and
Unlock Bypass command sequences.
An erase operation can erase one sector, multiple sectors, or the entire device. Tables 3–6 indicate the
address space that each sector occupies. The device
address space is divided into two banks: Bank 1 contains the boot/parameter sectors, and Bank 2 contains
the larger, code sectors of uniform size. A “bank address” is the address bits required to uniquely select a
bank. Similarly, a “sector address” is the address bits
required to uniquely select a sector.
ICC2 in the DC Characteristics table represents the active current specification for the write mode. The AC
Characteristics section contains timing specification
tables and timing diagrams for write operations.
Accelerated Program Operation
The device offers accelerated program operations
through the ACC function. This is one of two functions
provided by the WP#/ACC pin. This function is primarily intended to allow faster manufacturing throughput
at the factory.
If the system asserts VHH on this pin, the device automatically enters the aforementioned Unlock Bypass
mode, temporarily unprotects any protected sectors,
and uses the higher voltage on the pin to reduce the
time required for program operations. The system
would use a two-cycle program command sequence
as required by the Unlock Bypass mode. Removing
May 26, 2004
VHH from the WP#/ACC pin returns the device to normal operation. Note that the WP#/ACC pin must not be
at VHH for operations other than accelerated programming, or device damage may result. In addition, the
WP#/ACC pin must not be left floating or unconnected;
inconsistent behavior of the device may result.
Autoselect Functions
If the system writes the autoselect command sequence, the device enters the autoselect mode. The
system can then read autoselect codes from the internal register (which is separate from the memory array)
on DQ7–DQ0. Standard read cycle timings apply in
this mode. Refer to the Autoselect Mode and Autosel e c t C o m m a n d S e q u e n c e s e c t i o n s fo r m o r e
information.
Simultaneous Read/Write Operations with
Zero Latency
This device is capable of reading data from one bank
of memory while programming or erasing in the other
bank of memory. An erase operation may also be suspended to read from or program to another location
within the same bank (except the sector being
erased). Figure 20 shows how read and write cycles
may be initiated for simultaneous operation with zero
latency. ICC6 and ICC7 in the DC Characteristics table
represent the current specifications for read-while-program and read-while-erase, respectively.
Standby Mode
When the system is not reading or writing to the device, it can place the device in the standby mode. In
this mode, current consumption is greatly reduced,
and the outputs are placed in the high impedance
state, independent of the OE# input.
The device enters the CMOS standby mode when the
CE# and RESET# pins are both held at VCC ± 0.3 V.
(Note that this is a more restricted voltage range than
VIH.) If CE# and RESET# are held at VIH, but not within
VCC ± 0.3 V, the device will be in the standby mode,
but the standby current will be greater. The device requires standard access time (t CE ) for read access
when the device is in either of these standby modes,
before it is ready to read data.
If the device is deselected during erasure or programming, the device draws active current until the
operation is completed.
I CC3 in the DC Characteristics table represents the
standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables
this mode when addresses remain stable for t ACC +
Am29DL16xD
13
30 ns. The automatic sleep mode is independent of
the CE#, WE#, and OE# control signals. Standard add r e ss a cce s s ti m i n g s p r ovi d e n ew d a ta w h e n
addresses are changed. While in sleep mode, output
data is latched and always available to the system.
I CC4 in the DC Characteristics table represents the
automatic sleep mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading array data. When the
RESET# pin is driven low for at least a period of tRP,
the device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state machine to reading array data. The operation that was
interrupted should be reinitiated once the device is
ready to accept another command sequence, to ensure data integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at VSS±0.3 V, the device
draws CMOS standby current (ICC4). If RESET# is held
at VIL but not within VSS±0.3 V, the standby current will
be greater.
Table 2.
Device
Part Number
The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firmware from the Flash memory.
If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a
time of tREADY (during Embedded Algorithms). The system can thus monitor RY/BY# to determine whether
the reset operation is complete. If RESET# is asserted
when a program or erase operation is not executing
(RY/BY# pin is “1”), the reset operation is completed
within a time of tREADY (not during Embedded Algorithms). The system can read data t R H after the
RESET# pin returns to VIH.
Refer to the AC Characteristics tables for RESET# parameters and to Figure 14 for the timing diagram.
Output Disable Mode
When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in the high
impedance state.
Am29DL16xD Device Bank Divisions
Bank 1
Bank 2
Megabits
Sector Sizes
Megabits
Sector Sizes
Am29DL161D
0.5 Mbit
Eight 8 Kbyte/4 Kword
15.5 Mbit
Thirty-one
64 Kbyte/32 Kword
Am29DL162D
2 Mbit
14 Mbit
Twenty-eight
64 Kbyte/32 Kword
Am29DL163D
4 Mbit
Eight 8 Kbyte/4 Kword,
seven 64 Kbyte/32 Kword
12 Mbit
Twenty-four
64 Kbyte/32 Kword
Am29DL164D
8 Mbit
Eight 8 Kbyte/4 Kword,
fifteen 64 Kbyte/32 Kword
8 Mbit
Sixteen
64 Kbyte/32 Kword
14
Eight 8 Kbyte/4 Kword,
three 64 Kbyte/32 Kword
Am29DL16xD
May 26, 2004
Am29DL161DT
Am29DL162DT
Am29DL163DT
Bank 2
Bank 2
Bank 1
Bank 1
Bank 1
Bank 1
Bank 2
Bank 2
Am29DL164DT
Table 3.
Sector Addresses for Top Boot Sector Devices
Sector
Sector Address
A19–A12
Sector Size
(Kbytes/Kwords)
(x8)
Address Range
(x16)
Address Range
SA0
00000xxx
64/32
000000h-00FFFFh
00000h–07FFFh
SA1
00001xxx
64/32
010000h-01FFFFh
08000h–0FFFFh
SA2
00010xxx
64/32
020000h-02FFFFh
10000h–17FFFh
SA3
00011xxx
64/32
030000h-03FFFFh
18000h–1FFFFh
SA4
00100xxx
64/32
040000h-04FFFFh
20000h–27FFFh
SA5
00101xxx
64/32
050000h-05FFFFh
28000h–2FFFFh
SA6
00110xxx
64/32
060000h-06FFFFh
30000h–37FFFh
SA7
00111xxx
64/32
070000h-07FFFFh
38000h–3FFFFh
SA8
01000xxx
64/32
080000h-08FFFFh
40000h–47FFFh
SA9
01001xxx
64/32
090000h-09FFFFh
48000h–4FFFFh
SA10
01010xxx
64/32
0A0000h-0AFFFFh
50000h–57FFFh
SA11
01011xxx
64/32
0B0000h-0BFFFFh
58000h–5FFFFh
SA12
01100xxx
64/32
0C0000h-0CFFFFh
60000h–67FFFh
SA13
01101xxx
64/32
0D0000h-0DFFFFh
68000h–6FFFFh
SA14
01110xxx
64/32
0E0000h-0EFFFFh
70000h–77FFFh
SA15
01111xxx
64/32
0F0000h-0FFFFFh
78000h–7FFFFh
SA16
10000xxx
64/32
100000h-10FFFFh
80000h–87FFFh
SA17
10001xxx
64/32
110000h-11FFFFh
88000h–8FFFFh
SA18
10010xxx
64/32
120000h-12FFFFh
90000h–97FFFh
SA19
10011xxx
64/32
130000h-13FFFFh
98000h–9FFFFh
SA20
10100xxx
64/32
140000h-14FFFFh
A0000h–A7FFFh
SA21
10101xxx
64/32
150000h-15FFFFh
A8000h–AFFFFh
SA22
10110xxx
64/32
160000h-16FFFFh
B0000h–B7FFFh
SA23
10111xxx
64/32
170000h-17FFFFh
B8000h–BFFFFh
SA24
11000xxx
64/32
180000h-18FFFFh
C0000h–C7FFFh
SA25
11001xxx
64/32
190000h-19FFFFh
C8000h–CFFFFh
SA26
11010xxx
64/32
1A0000h-1AFFFFh
D0000h–D7FFFh
SA27
11011xxx
64/32
1B0000h-1BFFFFh
D8000h–DFFFFh
SA28
11100xxx
64/32
1C0000h-1CFFFFh
E0000h–E7FFFh
SA29
11101xxx
64/32
1D0000h-1DFFFFh
E8000h–EFFFFh
SA30
11110xxx
64/32
1E0000h-1EFFFFh
F0000h–F7FFFh
SA31
11111000
8/4
1F0000h-1F1FFFh
F8000h–F8FFFh
SA32
11111001
8/4
1F2000h-1F3FFFh
F9000h–F9FFFh
SA33
11111010
8/4
1F4000h-1F5FFFh
FA000h–FAFFFh
SA34
11111011
8/4
1F6000h-1F7FFFh
FB000h–FBFFFh
SA35
11111100
8/4
1F8000h-1F9FFFh
FC000h–FCFFFh
SA36
11111101
8/4
1FA000h-1FBFFFh
FD000h–FDFFFh
SA37
11111110
8/4
1FC000h-1FDFFFh
FE000h–FEFFFh
SA38
11111111
8/4
1FE000h-1FFFFFh
FF000h–FFFFFh
Note: The address range is A19:A-1 in byte mode (BYTE#=VIL) or A19:A0 in word mode (BYTE#=VIH). The bank address bits are A19–A15 for
Am29DL161DT, A19–A17 for Am29DL162DT, A19 and A18 for Am29DL163DT, and A19 for Am29DL164DT.
Table 4.
SecSi™ Sector Addresses for Top Boot Devices
Device
Sector Address
A19–A12
Sector
Size
(x8)
Address Range
(x16)
Address Range
Am29DL16xDT
11111xxx
64/32
1F0000h-1FFFFFh
F8000h–FFFFFh
May 26, 2004
Am29DL16xD
15
Am29DL161DB
Bank 2
Bank 2
Sector Addresses for Bottom Boot Sector Devices
Sector
Sector Address
A19–A12
Sector Size
(Kbytes/Kwords)
(x8)
Address Range
(x16)
Address Range
SA0
00000000
8/4
000000h-001FFFh
00000h-00FFFh
SA1
00000001
8/4
002000h-003FFFh
01000h-01FFFh
SA2
00000010
8/4
004000h-005FFFh
02000h-02FFFh
SA3
00000011
8/4
006000h-007FFFh
03000h-03FFFh
SA4
00000100
8/4
008000h-009FFFh
04000h-04FFFh
SA5
00000101
8/4
00A000h-00BFFFh
05000h-05FFFh
SA6
00000110
8/4
00C000h-00DFFFh
06000h-06FFFh
Bank 1
Am29DL162DB
Bank 1
Am29DL163DB
Bank 2
Bank 2
Bank 1
Bank 1
Am29DL164DB
Table 5.
SA7
00000111
8/4
00E000h-00FFFFh
07000h-07FFFh
SA8
00001XXX
64/32
010000h-01FFFFh
08000h-0FFFFh
SA9
00010XXX
64/32
020000h-02FFFFh
10000h-17FFFh
SA10
00011XXX
64/32
030000h-03FFFFh
18000h-1FFFFh
SA11
00100XXX
64/32
040000h-04FFFFh
20000h-27FFFh
SA12
00101XXX
64/32
050000h-05FFFFh
28000h-2FFFFh
SA13
00110XXX
64/32
060000h-06FFFFh
30000h-37FFFh
SA14
00111XXX
64/32
070000h-07FFFFh
38000h-3FFFFh
SA15
01000XXX
64/32
080000h-08FFFFh
40000h-47FFFh
SA16
01001XXX
64/32
090000h-09FFFFh
48000h-4FFFFh
SA17
01010XXX
64/32
0A0000h-0AFFFFh
50000h-57FFFh
SA18
01011XXX
64/32
0B0000h-0BFFFFh
58000h-5FFFFh
SA19
01100XXX
64/32
0C0000h-0CFFFFh
60000h-67FFFh
SA20
01101XXX
64/32
0D0000h-0DFFFFh
68000h-6FFFFh
SA21
01110XXX
64/32
0E0000h-0EFFFFh
70000h-77FFFh
SA22
01111XXX
64/32
0F0000h-0FFFFFh
78000h-7FFFFh
SA23
10000XXX
64/32
100000h-10FFFFh
80000h-87FFFh
SA24
10001XXX
64/32
110000h-11FFFFh
88000h-8FFFFh
SA25
10010XXX
64/32
120000h-12FFFFh
90000h-97FFFh
SA26
10011XXX
64/32
130000h-13FFFFh
98000h-9FFFFh
SA27
10100XXX
64/32
140000h-14FFFFh
A0000h-A7FFFh
SA28
10101XXX
64/32
150000h-15FFFFh
A8000h-AFFFFh
SA29
10110XXX
64/32
160000h-16FFFFh
B0000h-B7FFFh
SA30
10111XXX
64/32
170000h-17FFFFh
B8000h-BFFFFh
SA31
11000XXX
64/32
180000h-18FFFFh
C0000h-C7FFFh
SA32
11001XXX
64/32
190000h-19FFFFh
C8000h-CFFFFh
SA33
11010XXX
64/32
1A0000h-1AFFFFh
D0000h-D7FFFh
SA34
11011XXX
64/32
1B0000h-1BFFFFh
D8000h-DFFFFh
SA35
11100XXX
64/32
1C0000h-1CFFFFh
E0000h-E7FFFh
SA36
11101XXX
64/32
1D0000h-1DFFFFh
E8000h-EFFFFh
SA37
11110XXX
64/32
1E0000h-1EFFFFh
F0000h-F7FFFh
SA38
11111XXX
64/32
1F0000h-1FFFFFh
F8000h-FFFFFh
Note: The address range is A19:A-1 in byte mode (BYTE#=VIL) or A19:A0 in word mode (BYTE#=VIH). The bank address bits are A19–A15 for
Am29DL161DB, A19–A17 for Am29DL162DB, A19 and A18 for Am29DL163DB, and A19 for Am29DL164DB.
Table 6.
16
SecSi™ Addresses for Bottom Boot Devices
Device
Sector Address
A19–A12
Sector
Size
(x8)
Address Range
(x16)
Address Range
Am29DL16xDB
00000XXX
64/32
000000h-00FFFFh
00000h-07FFFh
Am29DL16xD
May 26, 2004
Autoselect Mode
Table 7. In addition, when verifying sector protection,
the sector address must appear on the appropriate
highest order address bits (see Tables 3–6). Table 7
shows the remaining address bits that are don’t care.
When all necessary bits have been set as required,
the programming equipment may then read the corresponding identifier code on DQ7–DQ0.
The autoselect mode provides manufacturer and device identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This
mode is primarily intended for programming equipm e n t t o a u t o m a t i c a l l y m a t c h a d ev i c e t o b e
programmed with its corresponding programming algorithm. However, the autoselect codes can also be
accessed in-system through the command register.
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in Table 14. This method
does not require V ID. Refer to the Autoselect Command Sequence section for more information.
When using programming equipment, the autoselect
mode requires VID (8.5 V to 12.5 V) on address pin A9.
Address pins A6, A1, and A0 must be as shown in
Table 7.
Am29DL16xD Autoselect Codes, (High Voltage Method)
A11
to
A10
A9
A8
to
A7
DQ8 to DQ15
A6
A5
to
A2
A1
A0
DQ7
to
DQ0
CE#
OE#
WE#
A19
to
A12
Manufacturer ID: AMD
L
L
H
BA
X
VID
X
L
X
L
L
X
X
01h
Device ID: Am29DL161D
L
L
H
BA
X
VID
X
L
X
L
H
22h
X
36h (T), 39h (B)
Device ID: Am29DL162D
L
L
H
BA
X
VID
X
L
X
L
H
22h
X
2Dh (T), 2Eh (B)
Device ID: Am29DL163D
L
L
H
BA
X
VID
X
L
X
L
H
22h
X
28h (T), 2Bh (B)
Device ID: Am29DL164D
L
L
H
BA
X
VID
X
L
X
L
H
22h
X
33h (T), 35h (B)
Sector Protection
Verification
L
L
H
SA
X
VID
X
L
X
H
L
X
X
01h (protected),
00h (unprotected)
SecSi™ Indicator Bit
(DQ7)
L
L
H
BA
X
VID
X
L
X
H
H
X
X
81h (factory locked),
01h (not factory
locked)
Description
BYTE# BYTE#
= VIH
= VIL
Legend: T = Top Boot Block, B = Bottom Boot Block, L = Logic Low = VIL, H = Logic High = VIH, BA = Bank Address, SA =
Sector Address, X = Don’t care.
May 26, 2004
Am29DL16xD
17
Sector/Sector Block Protection and
Unprotection
Table 9. Bottom Boot Sector/Sector Block
Addresses for Protection/Unprotection
(Note: For the following discussion, the term “sector”
applies to both sectors and sector blocks. A sector
block consists of two or more adjacent sectors that are
protected or unprotected at the same time (see Tables
8 and 9).
Table 8.
Top Boot Sector/Sector Block Addresses
for Protection/Unprotection
Sector / Sector
Block
SA0
A19–A12
00000XXX
Sector / Sector Block Size
64 Kbytes
SA1-SA3
00001XXX,
00010XXX,
00011XXX
192 (3x64) Kbytes
SA4-SA7
001XXXXX
256 (4x64) Kbytes
SA8-SA11
010XXXXX
256 (4x64) Kbytes
SA12-SA15
011XXXXX
256 (4x64) Kbytes
SA16-SA19
SA20-SA23
SA24-SA27
100XXXXX
101XXXXX
110XXXXX
Sector / Sector
Block
A19–A12
Sector / Sector Block Size
SA38
11111XXX
64 Kbytes
SA37-SA35
11110XXX,
11101XXX,
11100XXX
192 (3x64) Kbytes
SA34-SA31
110XXXXX
256 (4x64) Kbytes
SA30-SA27
101XXXXX
256 (4x64) Kbytes
SA26-SA23
100XXXXX
256 (4x64) Kbytes
SA22-SA19
011XXXXX
256 (4x64) Kbytes
SA18-SA15
010XXXXX
256 (4x64) Kbytes
SA14-SA11
001XXXXX
256 (4x64) Kbytes
SA10-SA8
00001XXX,
00010XXX,
00011XXX
192 (3x64) Kbytes
SA7
00000111
8 Kbytes
SA6
00000110
8 Kbytes
SA5
00000101
8 Kbytes
SA4
00000100
8 Kbytes
SA3
00000011
8 Kbytes
SA2
00000010
8 Kbytes
SA1
00000001
8 Kbytes
SA0
00000000
8 Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
256 (4x64) Kbytes
SA28-SA30
11100XXX,
11101XXX,
11110XXX
192 (3x64) Kbytes
SA31
11111000
8 Kbytes
SA32
11111001
8 Kbytes
SA33
11111010
8 Kbytes
SA34
11111011
8 Kbytes
SA35
11111100
8 Kbytes
SA36
11111101
8 Kbytes
SA37
11111110
8 Kbytes
SA38
11111111
8 Kbytes
The hardware sector protection feature disables both
program and erase operations in any sector. The hardware sector unprotection feature re-enables both
program and erase operations in previously protected
sectors. Sector protection and unprotection can be implemented via two methods.
The primary method requires VID on the RESET# pin
only, and can be implemented either in-system or via
programming equipment. Figure 2 shows the algorithms and Figure 25 shows the timing diagram. This
method uses standard microprocessor bus cycle timing. For sector unprotect, all unprotected sectors must
first be protected prior to the first sector unprotect
write cycle.
The sector unprotect algorithm unprotects all sectors
in parallel. All previously protected sectors must be individually re-protected. To change data in protected
sectors efficiently, the temporary sector unprotect
function is available. See “Temporary Sector/Sector
Block Unprotect”.
The alternate method intended only for programming
equipment requires VID on address pin A9 and OE#.
This method is compatible with programmer routines
written for earlier 3.0 volt-only AMD flash devices.
Publication number 22243 contains further details;
contact an AMD representative to request a copy.
The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device
18
Am29DL16xD
May 26, 2004
through AMD’s ExpressFlash™ Service. Contact an
AMD representative for details.
It is possible to determine whether a sector is protected or unprotected. See the Autoselect Mode
section for details.
Write Protect (WP#)
The Write Protect function provides a hardware
method of protecting certain boot sectors without
using VID. This function is one of two provided by the
WP#/ACC pin.
This feature allows temporary unprotection of previously protected sectors to change data in-system. The
Sector Unprotect mode is activated by setting the RESET# pin to VID (8.5 V – 12.5 V). During this mode,
formerly protected sectors can be programmed or
erased by selecting the sector addresses. Once VID is
removed from the RESET# pin, all the previously protected sectors are protected again. Figure 1 shows the
algorithm, and Figure 24 shows the timing diagrams,
for this feature.
If the system asserts VIL on the WP#/ACC pin, the device disables program and erase functions in the two
“outermost” 8 Kbyte boot sectors independently of
whether those sectors were protected or unprotected
using the method described in “Sector/Sector Block
Protection and Unprotection”. The two outermost 8
Kbyte boot sectors are the two sectors containing the
lowest addresses in a bottom-boot-configured device,
or the two sectors containing the highest addresses in
a top-boot-configured device.
START
RESET# = VID
(Note 1)
Perform Erase or
Program Operations
If the system asserts VIH on the WP#/ACC pin, the device reverts to whether the two outermost 8 Kbyte boot
sectors were last set to be protected or unprotected.
That is, sector protection or unprotection for these two
sectors depends on whether they were last protected
or unprotected using the method described in “Sector/Sector Block Protection and Unprotection”.
RESET# = VIH
Temporary Sector
Unprotect Completed
(Note 2)
Note that the WP#/ACC pin must not be left floating or
unconnected; inconsistent behavior of the device may
result.
Temporary Sector/Sector Block Unprotect
(Note: For the following discussion, the term “sector”
applies to both sectors and sector blocks. A sector
block consists of two or more adjacent sectors that are
protected or unprotected at the same time (see Tables
8 and 9).
Notes:
1. All protected sectors unprotected (If WP#/ACC = VIL,
outermost boot sectors will remain protected).
2. All previously protected sectors are protected once
again.
Figure 1.
May 26, 2004
Am29DL16xD
Temporary Sector Unprotect Operation
19
START
START
Protect all sectors:
The indicated portion
of the sector protect
algorithm must be
performed for all
unprotected sectors
prior to issuing the
first sector
unprotect address
PLSCNT = 1
RESET# = VID
Wait 1 µs
Temporary Sector
Unprotect Mode
No
PLSCNT = 1
RESET# = VID
Wait 1 µs
No
First Write
Cycle = 60h?
First Write
Cycle = 60h?
Yes
Yes
Set up sector
address
No
All sectors
protected?
Sector Protect:
Write 60h to sector
address with
A6 = 0, A1 = 1,
A0 = 0
Yes
Set up first sector
address
Sector Unprotect:
Write 60h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Wait 150 µs
Verify Sector
Protect: Write 40h
to sector address
with A6 = 0,
A1 = 1, A0 = 0
Increment
PLSCNT
Temporary Sector
Unprotect Mode
Reset
PLSCNT = 1
Read from
sector address
with A6 = 0,
A1 = 1, A0 = 0
Wait 15 ms
Verify Sector
Unprotect: Write
40h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Increment
PLSCNT
No
No
PLSCNT
= 25?
Read from
sector address
with A6 = 1,
A1 = 1, A0 = 0
Data = 01h?
Yes
Yes
No
Yes
Device failed
PLSCNT
= 1000?
Protect another
sector?
No
Yes
Remove VID
from RESET#
Device failed
Write reset
command
Sector Protect
Algorithm
Sector Protect
complete
Set up
next sector
address
No
Data = 00h?
Yes
Last sector
verified?
No
Yes
Sector Unprotect
Algorithm
Remove VID
from RESET#
Write reset
command
Sector Unprotect
complete
Note: The term “sector” in the figure applies to both sectors and sector blocks.
Figure 2.
20
In-System Sector/Sector Block Protection and Unprotection Algorithms
Am29DL16xD
May 26, 2004
SecSi™ (Secured Silicon) Sector Flash
Memory Region
The SecSi (Secured Silicon) Sector feature provides a
Flash memory region that enables permanent part
identification through an Electronic Serial Number
(ESN). The SecSi Sector uses an Indicator Bit (DQ7)
to indicate whether or not the sector is locked when
shipped from the factory. This bit is permanently set at
the factory and cannot be changed, which prevents
cloning of a factory locked part. This ensures the security of the ESN once the product is shipped to the field.
Current version of device has 64 Kbytes; future
versions will have only 256 bytes. This should be
considered during system design.
AMD offers the device with the SecSi Sector either
fac t or y l ocke d or c u s t om e r l o ckabl e. T he fac tory-locked version is always protected when shipped
from the factory, and has the SecSi Sector Indicator
Bit permanently set to a “1.” The customer-lockable
version is shipped with the unprotected, allowing customers to utilize the that sector in any manner they
choose. The customer-lockable version has the SecSi
Sector Indicator Bit permanently set to a “0.” Thus, the
SecSi Sector Indicator Bit prevents customer-lockable
devices from being used to replace devices that are
factory locked.
The system accesses the SecSi Sector through a
command sequence (see “Enter SecSi Sector/Exit
SecSi Sector Command Sequence”). After the system
has written the Enter SecSi Sector command sequence, it may read the SecSi Sector by using the
addresses normally occupied by the boot sectors. This
mode of operation continues until the system issues
the Exit SecSi Sector command sequence, or until
power is removed from the device. On power-up, or
following a hardware reset, the device reverts to sending commands to the boot sectors.
Factory Locked: SecSi Sector Programmed and
Protected At the Factory
In a factory locked device, the SecSi Sector is protected when the device is shipped from the factory.
The SecSi Sector cannot be modified in any way. The
device is available preprogrammed with one of the
following:
bottom of the lowest 8 Kbyte boot sector at addresses
F8000h–F8007h in word mode (or 1F0000h–1F000Fh
in byte mode).
Customers may opt to have their code programmed by
AMD through the AMD ExpressFlash service. AMD
programs the customer’s code, with or without the random ESN. The devices are then shipped from AMD’s
factory with the SecSi Sector permanently locked.
Contact an AMD representative for details on using
AMD’s ExpressFlash service.
Customer Lockable: SecSi Sector NOT
Programmed or Protected At the Factory
If the security feature is not required, the SecSi Sector
can be treated as an additional Flash memory space,
expanding the size of the available Flash array. Current
version of device has 64 Kbytes; future versions
will have only 256 bytes. This should be considered during system design. The SecSi Sector can be
read, programmed, and erased as often as required.
( Note that in upcoming versions of this device, the
SecSi Sector erase function will not be available.) Note
that the accelerated programming (ACC) and unlock
bypass functions are not available when programming
the SecSi Sector.
The SecSi Sector area can be protected using one of the
following procedures:
■ Write the three-cycle Enter SecSi Sector Region
command sequence, and then follow the in-system
sector protect algorithm as shown in Figure 2, except that RESET# may be at either VIH or VID. This
allows in-system protection of the without raising
any device pin to a high voltage. Note that this
method is only applicable to the SecSi Sector.
■ Write the three-cycle Enter SecSi Sector Region
command sequence, and then use the alternate
method of sector protection described in the “Sector/Sector Block Protection and Unprotection”.
Once the SecSi Sector is locked and verified, the syste m m us t w r i te th e Exi t S e c Si S ec to r R e gi on
command sequence to return to reading and writing
the remainder of the array.
■ Customer code through the ExpressFlash service
The SecSi Sector protection must be used with caution since, once protected, there is no procedure
available for unprotecting the SecSi Sector area and
none of the bits in the SecSi Sector memory space
can be modified in any way.
■ Both a random, secure ESN and customer code
through the ExpressFlash service.
Hardware Data Protection
In devices that have an ESN, a Bottom Boot device will
have the 16-byte ESN in the lowest addressable memory area at addresses 00000h–00007h in word mode
(or 000000h–00000Fh in byte mode). In the Top Boot
device the starting address of the ESN will be at the
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to Table 14 for command definitions). In addition, the following hardware
data protection measures prevent accidental erasure
or programming, which might otherwise be caused by
■ A random, secure ESN only
May 26, 2004
Am29DL16xD
21
spurious system level signals during V CC power-up
and power-down transitions, or from system noise.
COMMON FLASH MEMORY INTERFACE
(CFI)
Low VCC Write Inhibit
The Common Flash Interface (CFI) specification outlines device and host system software interrogation
handshake, which allows specific vendor-specified
software algorithms to be used for entire families of
devices. Software support can then be device-independent, JEDEC ID-independent, and forward- and
backward-compatible for the specified flash device
families. Flash vendors can standardize their existing
interfaces for long-term compatibility.
When VCC is less than VLKO, the device does not accept any write cycles. This protects data during VCC
power-up and power-down. The command register
and all internal program/erase circuits are disabled,
and the device resets to reading array data. Subsequent writes are ignored until VCC is greater than VLKO.
The system must provide the proper signals to the
control pins to prevent unintentional writes when VCC
is greater than VLKO.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE#
or WE# do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,
CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = VIL and OE# = V IH during power up,
the device does not accept commands on the rising
edge of WE#. The internal state machine is automatically reset to reading array data on power-up.
Table 10.
This device enters the CFI Query mode when the system writes the CFI Query command, 98h, to address
55h in word mode (or address AAh in byte mode), any
time the device is ready to read array data. The system can read CFI information at the addresses given
in Tables 10–13. To terminate reading CFI data, the
system must write the reset command.
The system can also write the CFI query command
when the device is in the autoselect mode. The device
enters the CFI query mode, and the system can read
CFI data at the addresses given in Tables 10–13. The
system must write the reset command to return the
device to the autoselect mode.
For further information, please refer to the CFI Specification and CFI Publication 100, available via the World
Wide Web at http://www.amd.com/products/nvd/overv i e w / c f i . h t m l . A l t e r n a t i ve l y, c o n t a c t a n A M D
representative for copies of these documents.
CFI Query Identification String
Addresses
(Word Mode)
Addresses
(Byte Mode)
Data
10h
11h
12h
20h
22h
24h
0051h
0052h
0059h
Query Unique ASCII string “QRY”
13h
14h
26h
28h
0002h
0000h
Primary OEM Command Set
15h
16h
2Ah
2Ch
0040h
0000h
Address for Primary Extended Table
17h
18h
2Eh
30h
0000h
0000h
Alternate OEM Command Set (00h = none exists)
19h
1Ah
32h
34h
0000h
0000h
Address for Alternate OEM Extended Table (00h = none exists)
22
Description
Am29DL16xD
May 26, 2004
Table 11.
System Interface String
Addresses
(Word Mode)
Addresses
(Byte Mode)
Data
1Bh
36h
0027h
VCC Min. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Ch
38h
0036h
VCC Max. (write/erase)
D7–D4: volt, D3–D0: 100 millivolt
1Dh
3Ah
0000h
VPP Min. voltage (00h = no VPP pin present)
1Eh
3Ch
0000h
VPP Max. voltage (00h = no VPP pin present)
1Fh
3Eh
0004h
Typical timeout per single byte/word write 2N µs
20h
40h
0000h
Typical timeout for Min. size buffer write 2N µs (00h = not supported)
21h
42h
000Ah
Typical timeout per individual block erase 2N ms
22h
44h
0000h
Typical timeout for full chip erase 2N ms (00h = not supported)
23h
46h
0005h
Max. timeout for byte/word write 2N times typical
24h
48h
0000h
Max. timeout for buffer write 2N times typical
25h
4Ah
0004h
Max. timeout per individual block erase 2N times typical
26h
4Ch
0000h
Max. timeout for full chip erase 2N times typical (00h = not supported)
Table 12.
Addresses
(Word Mode)
Addresses
(Byte Mode)
Description
Device Geometry Definition
Data
Description
N
27h
4Eh
0015h
Device Size = 2 byte
28h
29h
50h
52h
0002h
0000h
Flash Device Interface description (refer to CFI publication 100)
2Ah
2Bh
54h
56h
0000h
0000h
Max. number of bytes in multi-byte write = 2N
(00h = not supported)
2Ch
58h
0002h
Number of Erase Block Regions within device
2Dh
2Eh
2Fh
30h
5Ah
5Ch
5Eh
60h
0007h
0000h
0020h
0000h
Erase Block Region 1 Information
(refer to the CFI specification or CFI publication 100)
31h
32h
33h
34h
62h
64h
66h
68h
001Eh
0000h
0000h
0001h
Erase Block Region 2 Information
35h
36h
37h
38h
6Ah
6Ch
6Eh
70h
0000h
0000h
0000h
0000h
Erase Block Region 3 Information
39h
3Ah
3Bh
3Ch
72h
74h
76h
78h
0000h
0000h
0000h
0000h
Erase Block Region 4 Information
May 26, 2004
Am29DL16xD
23
Table 13.
Primary Vendor-Specific Extended Query
Addresses
(Word Mode)
Addresses
(Byte Mode)
Data
40h
41h
42h
80h
82h
84h
0050h
0052h
0049h
Query-unique ASCII string “PRI”
43h
86h
0031h
Major version number, ASCII
44h
88h
0031h
Minor version number, ASCII
45h
8Ah
0000h
Address Sensitive Unlock (Bits 1-0)
0 = Required, 1 = Not Required
Description
Silicon Revision Number (Bits 7-2)
46h
8Ch
0002h
Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
47h
8Eh
0001h
Sector Protect
0 = Not Supported, X = Number of sectors in per group
48h
90h
0001h
Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
49h
92h
0004h
Sector Protect/Unprotect scheme
04 = 29LV800 mode
4Ah
94h
00XXh
(See Note)
4Bh
96h
0000h
Burst Mode Type
00 = Not Supported, 01 = Supported
4Ch
98h
0000h
Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page
4Dh
9Ah
0085h
4Eh
9Ch
0095h
4Fh
9Eh
000Xh
Simultaneous Operation
00 = Not Supported, X= Number of Sectors in Bank 2 (Uniform Bank)
ACC (Acceleration) Supply Minimum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
ACC (Acceleration) Supply Maximum
00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV
Top/Bottom Boot Sector Flag
02h = Bottom Boot Device, 03h = Top Boot Device
Note:
The number of sectors in Bank 2 is device dependent.
Am29DL161 = 1Fh
Am29DL162 = 1Ch
Am29DL163 = 18h
Am29DL164 = 10h
24
Am29DL16xD
May 26, 2004
COMMAND DEFINITIONS
Writing specific address and data commands or sequences into the command register initiates device
operations. Table 14 defines the valid register command sequences. Writing incorrect address and
data values or writing them in the improper sequence may place the device in an unknown state. A
reset command is then required to return the device to
reading array data.
All addresses are latched on the falling edge of WE#
or CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the AC Characteristics section for timing
diagrams.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. Each bank is ready to read array data
after completing an Embedded Program or Embedded
Erase algorithm.
After the device accepts an Erase Suspend command,
the corresponding ban k enters the erase-suspend-read mode, after which the system can read
data from any non-erase-suspended sector within the
same bank. After completing a programming operation
in the Erase Suspend mode, the system may once
again read array data with the same exception. See
the Erase Suspend/Erase Resume Commands section for more information.
The system must issue the reset command to return a
bank to the read (or erase-suspend-read) mode if DQ5
goes high during an active program or erase operation, or if the bank is in the autoselect mode. See the
next section, Reset Command, for more information.
See also Requirements for Reading Array Data in the
Device Bus Operations section for more information.
The Read-Only Operations table provides the read parameters, and Figure 13 shows the timing diagram.
Reset Command
Writing the reset command resets the banks to the
read or erase-suspend-read mode. Address bits are
don’t cares for this command.
The reset command may be written between the sequence cycles in an erase command sequence before
erasing begins. This resets the bank to which the system was writing to reading array data. Once erasure
begins, however, the device ignores reset commands
until the operation is complete.
The reset command may be written between the
sequence cycles in a program command sequence
before programming begins. This resets the bank to
which the system was writing to reading array data. If
May 26, 2004
the program command sequence is written to a bank
that is in the Erase Suspend mode, writing the reset
co m m an d re tur ns th a t ba nk to the e ra s e- s us pend-read mode. Once programming begins, however,
the device ignores reset commands until the operation
is complete.
The reset command may be written between the sequence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command
must be written to return to reading array data. If a
bank entered the autoselect mode while in the Erase
Suspend mode, writing the reset command returns
that bank to the erase-suspend-read mode.
If DQ5 goes high during a program or erase operation,
writing the reset command returns the banks to reading array data (or erase-suspend-read mode if that
bank was in Erase Suspend).
Autoselect Command Sequence
The autoselect command sequence allows the host
system to access the manufacturer and device codes,
and determine whether or not a sector is protected.
Table 14 shows the address and data requirements.
This method is an alternative to that shown in Table 7,
which is intended for PROM programmers and req ui res V I D o n a ddr es s pi n A 9. T h e au tos el ec t
command sequence may be written to an address
within a bank that is either in the read or
erase-suspend-read mode. The autoselect command
may not be written while the device is actively programming or erasing in the other bank.
The autoselect command sequence is initiated by first
writing two unlock cycles. This is followed by a third
write cycle that contains the bank address and the aut o se l e ct co m m a n d. T h e b a n k th e n e n t er s t h e
autoselect mode. The system may read at any address within the same bank any number of times
without initiating another autoselect command
sequence:
■ A read cycle at address (BA)XX00h (where BA is
the bank address) returns the manufacturer code.
■ A read cycle at address (BA)XX01h in word mode
(or (BA)XX02h in byte mode) returns the device
code.
■ A read cycle to an address containing a sector address (SA) within the same bank, and the address
02h on A7–A0 in word mode (or the address 04h on
A6–A-1 in byte mode) returns 01h if the sector is
protected, or 00h if it is unprotected. (Refer to Tables 3–6 for valid sector addresses).
The system must write the reset command to return to
reading array data (or erase-suspend-read mode if the
bank was previously in Erase Suspend).
Am29DL16xD
25
Enter SecSi™ Sector/Exit SecSi Sector
Command Sequence
The system can access the SecSi Sector region by issuing the three-cycle Enter SecSi Sector command
sequence. The device continues to access the SecSi
Sector region until the system issues the four-cycle
Exit SecSi Sector command sequence. The Exit SecSi
Sector command sequence returns the device to normal operation. Table 14 shows the address and data
requirements for both command sequences. See also
“SecSi Sector Flash Memory Region” for further information. Note that a hardware reset (RESET#=VIL) will
reset the device to reading array data.
Byte/Word Program Command Sequence
The system may program the device by word or byte,
depending on the state of the BYTE# pin. Programming is a four-bus-cycle operation. The program
command sequence is initiated by writing two unlock
write cycles, followed by the program set-up command. The program address and data are written next,
which in turn initiate the Embedded Program algorithm. The system is not required to provide further
controls or timings. The device automatically provides
internally generated program pulses and verifies the
programmed cell margin. Table 14 shows the address
and data requirements for the byte program command
sequence.
When the Embedded Program algorithm is complete,
that bank then returns to reading array data and addresses are no longer latched. The system can
determine the status of the program operation by
using DQ7, DQ6, or RY/BY#. Refer to the Write Operation Status section for information on these status
bits.
Any commands written to the device during the Embedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the program
operation. The program command sequence should
be reinitiated once that bank has returned to reading
array data, to ensure data integrity.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from “0” back to a “1.” Attempting to do so may
cause that bank to set DQ5 = 1, or cause the DQ7 and
26
DQ6 status bits to indicate the operation was successful. However, a succeeding read will show that the
data is still “0.” Only erase operations can convert a “0”
to a “1.”
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to program bytes or words to a bank faster than using the
standard program command sequence. The unlock
bypass command sequence is initiated by first writing
two unlock cycles. This is followed by a third write
cycle containing the unlock bypass command, 20h.
The device then enters the unlock bypass mode. A
two-cycle unlock bypass program command sequence
is all that is required to program in this mode. The first
cycle in this sequence contains the unlock bypass program command, A0h; the second cycle contains the
program address and data. Additional data is programmed in the same manner. This mode dispenses
with the initial two unlock cycles required in the standard program command sequence, resulting in faster
total programming time. Table 14 shows the requirements for the command sequence.
During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset commands
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset command sequence. The device then returns to reading
array data.
The device offers accelerated program operations
through the WP#/ACC pin. When the system asserts
VHH on the WP#/ACC pin, the device automatically enters the Unlock Bypass mode. The system may then
write the two-cycle Unlock Bypass program command
sequence. The device uses the higher voltage on the
WP#/ACC pin to accelerate the operation. Note that
the WP#/ACC pin must not be at V HH any operation
other than accelerated programming, or device damage may result. In addition, the WP#/ACC pin must not
be left floating or unconnected; inconsistent behavior
of the device may result.
Figure 3 illustrates the algorithm for the program operation. Refer to the Erase and Program Operations
table in the AC Characteristics section for parameters,
and Figure 17 for timing diagrams.
Am29DL16xD
May 26, 2004
START
mediately terminates the erase operation. If that
occurs, the chip erase command sequence should be
reinitiated once that bank has returned to reading
array data, to ensure data integrity.
Write Program
Command Sequence
Figure 4 illustrates the algorithm for the erase operation. Refer to the Erase and Program Operations
tables in the AC Characteristics section for parameters, and Figure 19 section for timing diagrams.
Sector Erase Command Sequence
Data Poll
from System
Embedded
Program
algorithm
in progress
Verify Data?
No
Yes
Increment Address
No
The device does not require the system to preprogram
prior to erase. The Embedded Erase algorithm automatically programs and verifies the entire memory for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or timings during these operations.
Last Address?
Yes
Programming
Completed
Note: See Table 14 for program command sequence.
Figure 3.
Program Operation
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any controls or timings during these operations. Table 14
shows the address and data requirements for the chip
erase command sequence.
When the Embedded Erase algorithm is complete,
that bank returns to reading array data and addresses
are no longer latched. The system can determine the
status of the erase operation by using DQ7, DQ6,
DQ2, or RY/BY#. Refer to the Write Operation Status
section for information on these status bits.
Any commands written during the chip erase operation
are ignored. However, note that a hardware reset imMay 26, 2004
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two additional unlock cycles are written, and are then
followed by the address of the sector to be erased, and
the sector erase command. Table 14 shows the address and data requirements for the sector erase
command sequence.
After the command sequence is written, a sector erase
time-out of 50 µs occurs. During the time-out period,
additional sector addresses and sector erase commands within the bank may be written. Loading the
sector erase buffer may be done in any sequence, and
the number of sectors may be from one sector to all
sectors. The time between these additional cycles
must be less than 50 µs, otherwise erasure may begin.
Any sector erase address and command following the
exceeded time-out may or may not be accepted. It is
recommended that processor interrupts be disabled
during this time to ensure all commands are accepted.
The interrupts can be re-enabled after the last Sector
Erase command is written. Any command other than
S e ct o r E ra se o r E ra s e S u s p en d d u r i n g th e
time-out period resets that bank to reading array
data. The system must rewrite the command sequence and any additional addresses and commands.
The system can monitor DQ3 to determine if the sector erase timer has timed out (See the section on DQ3:
Sector Erase Timer.). The time-out begins from the rising edge of the final WE# pulse in the command
sequence.
When the Embedded Erase algorithm is complete, the
bank returns to reading array data and addresses are
no longer latched. Note that while the Embedded
Erase operation is in progress, the system can read
data from the non-erasing bank. The system can determine the status of the erase operation by reading
DQ7, DQ6, DQ2, or RY/BY# in the erasing bank. Refer
Am29DL16xD
27
to the Write Operation Status section for information
on these status bits.
Once the sector erase operation has begun, only the
Erase Suspend command is valid. All other commands are ignored. However, note that a hardware
reset immediately terminates the erase operation. If
that occurs, the sector erase command sequence
should be reinitiated once that bank has returned to
reading array data, to ensure data integrity.
Figure 4 illustrates the algorithm for the erase operation. Refer to the Erase and Program Operations
tables in the AC Characteristics section for parameters, and Figure 19 section for timing diagrams.
Erase Suspend/Erase Resume
Commands
program operation using the DQ7 or DQ6 status bits,
just as in the standard Byte Program operation.
Refer to the Write Operation Status section for more
information.
In the erase-suspend-read mode, the system can also
issue the autoselect command sequence. Refer to the
Autoselect Mode and Autoselect Command Sequence
sections for details.
To resume the sector erase operation, the system
must write the Erase Resume command. The bank
address of the erase-suspended bank is required
when writing this command. Further writes of the Resume command are ignored. Another Erase Suspend
command can be written after the chip has resumed
erasing.
The Erase Suspend command, B0h, allows the system to interrupt a sector erase operation and then read
data from, or program data to, any sector not selected
for erasure. The bank address is required when writing
this command. This command is valid only during the
sector erase operation, including the 50 µs time-out
period during the sector erase command sequence.
The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program
algorithm.
START
Write Erase
Command Sequence
(Notes 1, 2)
When the Erase Suspend command is written during
the sector erase operation, the device requires a maximum of 20 µs to suspend the erase operation.
However, when the Erase Suspend command is written during the sector erase time-out, the device
immediately terminates the time-out period and suspends the erase operation.
After the erase operation has been suspended, the
bank enters the erase-suspend-read mode. The system can read data from or program data to any sector
not selected for erasure. (The device “erase suspends” all sectors selected for erasure.) Reading at
any address within erase-suspended sectors produces status information on DQ7–DQ0. The system
can use DQ7, or DQ6 and DQ2 together, to determine
if a sector is actively erasing or is erase-suspended.
Refer to the Write Operation Status section for information on these status bits.
Data Poll to Erasing
Bank from System
No
Data = FFh?
Yes
Erasure Completed
Notes:
1. See Table 14 for erase command sequence.
2. See the section on DQ3 for information on the sector
erase timer.
After an erase-suspended program operation is complete, the bank returns to the erase-suspend-read
mode. The system can determine the status of the
28
Embedded
Erase
algorithm
in progress
Am29DL16xD
Figure 4.
Erase Operation
May 26, 2004
Command Definitions
Table 14.
Read (Note 6)
Autoselect (Note 8)
Reset (Note 7)
Manufacturer ID
Device ID
Word
Byte
Word
Byte
SecSi™ Factory
Protect (Note 9)
Word
Sector Protect Verify
(Note 10)
Word
Enter SecSi Sector Region
Exit SecSi Sector Region
Program
Unlock Bypass
Byte
Byte
Word
Byte
Word
Byte
Word
Byte
Word
Byte
Bus Cycles (Notes 2–5)
Cycles
Command
Sequence
(Note 1)
Am29DL16xD Command Definitions
Addr
Data
1
RA
RD
1
XXX
F0
4
4
4
4
3
4
4
3
First
555
AAA
555
AAA
555
AAA
555
AAA
555
AAA
555
AAA
555
AAA
555
AAA
Second
AA
AA
AA
AA
AA
AA
AA
AA
Addr
Data
2AA
555
2AA
555
2AA
555
2AA
555
2AA
555
2AA
555
2AA
555
2AA
555
55
55
55
55
55
55
55
55
Unlock Bypass Program (Note 11)
2
XXX
A0
PA
PD
Unlock Bypass Reset (Note 12)
2
XXX
90
XXX
00
Chip Erase
Sector Erase
Word
Byte
Word
Byte
6
6
555
AAA
555
AAA
AA
AA
Erase Suspend (Note 13)
1
BA
B0
Erase Resume (Note 14)
1
BA
30
CFI Query (Note 15)
Word
Byte
1
55
AA
2AA
555
2AA
555
55
55
Third
Addr
(BA)555
(BA)AAA
(BA)555
(BA)AAA
(BA)555
(BA)AAA
(BA)555
(BA)AAA
555
AAA
555
AAA
555
AAA
555
AAA
555
AAA
555
AAA
Fourth
Fifth
Data
Addr
Data
90
(BA)X00
01
(BA)X01
(see
Table 7)
90
90
90
(BA)X02
(BA)X03
(BA)X06
(SA)X02
(SA)X04
Addr
Sixth
Data
Addr
Data
81/01
00/01
88
90
XXX
00
A0
PA
PD
20
80
80
555
AAA
555
AAA
AA
AA
2AA
555
2AA
555
55
55
555
AAA
SA
10
30
98
Legend:
X = Don’t care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses
latch on the falling edge of the WE# or CE# pulse, whichever happens
later.
Notes:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except for the read cycle and the fourth cycle of the autoselect
command sequence, all bus cycles are write cycles.
PD = Data to be programmed at location PA. Data latches on the rising
edge of WE# or CE# pulse, whichever happens first.
SA = Address of the sector to be verified (in autoselect mode) or
erased. Address bits A19–A12 uniquely select any sector.
BA = Address of the bank that is being switched to autoselect mode, is
in bypass mode, or is being erased.
8. The fourth cycle of the autoselect command sequence is a read
cycle. The system must provide the bank address to obtain the
manufacturer ID, device ID, or SecSi Sector factory protect
information. Data bits DQ15–DQ8 are don’t care. See the
Autoselect Command Sequence section for more information.
4. Data bits DQ15–DQ8 are don’t care in command sequences,
except for RD and PD.
9. The data is 81h for factory locked and 01h for not factory locked.
5. Unless otherwise noted, address bits A19–A11 are don’t cares.
10. The data is 00h for an unprotected sector/sector block and 01h for
a protected sector/sector block.
6. No unlock or command cycles required when bank is reading
array data.
7. The Reset command is required to return to reading array data
(or to the erase-suspend-read mode if previously in Erase
Suspend) when a bank is in the autoselect mode, or if DQ5 goes
high (while the bank is providing status information).
11. The Unlock Bypass command is required prior to the Unlock
Bypass Program command.
12. The Unlock Bypass Reset command is required to return to
reading array data when the bank is in the unlock bypass mode.
13. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend mode.
The Erase Suspend command is valid only during a sector erase
operation, and requires the bank address.
14. The Erase Resume command is valid only during the Erase
May 26, 2004
Am29DL16xD
29
WRITE OPERATION STATUS
The device provides several bits to determine the status of a program or erase operation: DQ2, DQ3, DQ5,
DQ6, and DQ7. Table 15 and the following subsections describe the function of these bits. DQ7 and DQ6
each offer a method for determining whether a program or erase operation is complete or in progress.
The device also provides a hardware-based output
signal, RY/BY#, to determine whether an Embedded
Program or Erase operation is in progress or has been
completed.
pleted the program or erase operation and DQ7 has
valid data, the data outputs on DQ0–DQ6 may be still
invalid. Valid data on DQ0–DQ7 will appear on successive read cycles.
Table 15 shows the outputs for Data# Polling on DQ7.
Figure 5 shows the Data# Polling algorithm. Figure 21
in the AC Characteristics section shows the Data#
Polling timing diagram.
DQ7: Data# Polling
START
The Data# Polling bit, DQ7, indicates to the host syste m w h eth er a n Em b ed de d Pr ogram o r Era se
algorithm is in progress or completed, or whether a
bank is in Erase Suspend. Data# Polling is valid after
the rising edge of the final WE# pulse in the command
sequence.
Read DQ7–DQ0
Addr = VA
During the Embedded Program algorithm, the device
outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to
programming during Erase Suspend. When the Embedded Program algorithm is complete, the device
outputs the datum programmed to DQ7. The system
must provide the program address to read valid status
information on DQ7. If a program address falls within a
protected sector, Data# Polling on DQ7 is active for
approximately 1 µs, then that bank returns to reading
array data.
DQ7 = Data?
No
No
Just prior to the completion of an Embedded Program
or Erase operation, DQ7 may change asynchronously
with DQ0–DQ6 while Output Enable (OE#) is asserted
low. That is, the device may change from providing
status information to valid data on DQ7. Depending on
when the system samples the DQ7 output, it may read
the status or valid data. Even if the device has com-
30
DQ5 = 1?
Yes
During the Embedded Erase algorithm, Data# Polling
produces a “0” on DQ7. When the Embedded Erase
algorithm is complete, or if the bank enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
The system must provide an address within any of the
sectors selected for erasure to read valid status information on DQ7.
After an erase command sequence is written, if all
sectors selected for erasing are protected, Data# Polling on DQ7 is active for approximately 100 µs, then the
bank returns to reading array data. If not all selected
sectors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the selected sectors that are protected. However, if the
system reads DQ7 at an address within a protected
sector, the status may not be valid.
Yes
Read DQ7–DQ0
Addr = VA
DQ7 = Data?
Yes
No
FAIL
PASS
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is any sector address
within the sector being erased. During chip erase, a
valid address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” because
DQ7 may change simultaneously with DQ5.
Am29DL16xD
Figure 5. Data# Polling Algorithm
May 26, 2004
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin
which indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output, several RY/BY# pins can be tied together in parallel with a
pull-up resistor to VCC.
If the output is low (Busy), the device is actively erasing or programming. (This includes programming in
the Erase Suspend mode.) If the output is high
(Ready), the device is reading array data, the standby
mode, or one of the banks is in the erase-suspend-read mode.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded Program algorithm is complete.
Table 15 shows the outputs for Toggle Bit I on DQ6.
Figure 6 shows the toggle bit algorithm. Figure 22 in
the “AC Characteristics” section shows the toggle bit
timing diagrams. Figure 23 shows the differences between DQ2 and DQ6 in graphical form. See also the
subsection on DQ2: Toggle Bit II.
START
Table 15 shows the outputs for RY/BY#.
Read DQ7–DQ0
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase
Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final
WE# pulse in the command sequence (prior to the
program or erase operation), and during the sector
erase time-out.
During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause
DQ6 to toggle. The system may use either OE# or
CE# to control the read cycles. When the operation is
complete, DQ6 stops toggling.
Read DQ7–DQ0
Toggle Bit
= Toggle?
Yes
No
After an erase command sequence is written, if all
sectors selected for erasing are protected, DQ6 toggles for approximately 100 µs, then returns to reading
array data. If not all selected sectors are protected, the
Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are
protected.
DQ5 = 1?
Yes
Read DQ7–DQ0
Twice
The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is
erase-suspended. When the device is actively erasing
(that is, the Embedded Erase algorithm is in progress),
DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system
must also use DQ2 to determine which sectors are
erasing or erase-suspended. Alternatively, the system
can use DQ7 (see the subsection on DQ7: Data#
Polling).
If a program address falls within a protected sector,
DQ6 toggles for approximately 1 µs after the program
command sequence is written, then returns to reading
array data.
Toggle Bit
= Toggle?
No
Yes
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Note: The system should recheck the toggle bit even if DQ5
= “1” because the toggle bit may stop toggling as DQ5
changes to “1.” See the subsections on DQ6 and DQ2 for
more information.
Figure 6.
May 26, 2004
No
Am29DL16xD
Toggle Bit Algorithm
31
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence.
DQ2 toggles when the system reads at addresses
within those sectors that have been selected for erasure. (The system may use either OE# or CE# to
control the read cycles.) But DQ2 cannot distinguish
whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but
cannot distinguish which sectors are selected for erasure. Thus, both status bits are required for sector and
mode information. Refer to Table 15 to compare outputs for DQ2 and DQ6.
Figure 6 shows the toggle bit algorithm in flowchart
form, and the section “DQ2: Toggle Bit II” explains the
algorithm. See also the DQ6: Toggle Bit I subsection.
Figure 22 shows the toggle bit timing diagram. Figure
23 shows the differences between DQ2 and DQ6 in
graphical form.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 6 for the following discussion. Whenever the system initially begins reading toggle bit
status, it must read DQ7–DQ0 at least twice in a row
to determine whether a toggle bit is toggling. Typically,
the system would note and store the value of the toggle bit after the first read. After the second read, the
system would compare the new value of the toggle bit
with the first. If the toggle bit is not toggling, the device
has completed the program or erase operation. The
system can read array data on DQ7–DQ0 on the following read cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should
then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling
just as DQ5 went high. If the toggle bit is no longer
toggling, the device has successfully completed the
program or erase operation. If it is still toggling, the device did not completed the operation successfully, and
the system must write the reset command to return to
reading array data.
The remaining scenario is that the system initially determines that the toggle bit is toggling and DQ5 has
not gone high. The system may continue to monitor
the toggle bit and DQ5 through successive read cy-
32
cles, determining the status as described in the
previous paragraph. Alternatively, it may choose to
perform other system tasks. In this case, the system
must start at the beginning of the algorithm when it returns to determine the status of the operation (top of
Figure 6).
DQ5: Exceeded Timing Limits
DQ5 indicates whether the program or erase time
has exceeded a specified internal pulse count limit.
Under these conditions DQ5 produces a “1,” indicating
that the program or erase cycle was not successfully
completed.
The device may output a “1” on DQ5 if the system tries
to program a “1” to a location that was previously programmed to “0.” Only an erase operation can
change a “0” back to a “1.” Under this condition, the
device halts the operation, and when the timing limit
has been exceeded, DQ5 produces a “1.”
Under both these conditions, the system must write
the reset command to return to reading array data (or
to the erase-suspend-read mode if a bank was previously in the erase-suspend-program mode).
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not
erasure has begun. (The sector erase timer does not
apply to the chip erase command.) If additional
sectors are selected for erasure, the entire time-out
also applies after each additional sector erase command. When the time-out period is complete, DQ3
switches from a “0” to a “1.” If the time between additional sector erase commands from the system can be
assumed to be less than 50 µs, the system need not
monitor DQ3. See also the Sector Erase Command
Sequence section.
After the sector erase command is written, the system
should read the status of DQ7 (Data# Polling) or DQ6
(Toggle Bit I) to ensure that the device has accepted
the command sequence, and then read DQ3. If DQ3 is
“1,” the Embedded Erase algorithm has begun; all further commands (except Erase Suspend) are ignored
until the erase operation is complete. If DQ3 is “0,” the
device will accept additional sector erase commands.
To ensure the command has been accepted, the system software should check the status of DQ3 prior to
and following each subsequent sector erase command. If DQ3 is high on the second status check, the
last command might not have been accepted.
Table 15 shows the status of DQ3 relative to the other
status bits.
Am29DL16xD
May 26, 2004
Table 15.
Standard
Mode
Erase
Suspend
Mode
Status
Embedded Program Algorithm
Embedded Erase Algorithm
Erase
Erase-Suspend- Suspended Sector
Read
Non-Erase
Suspended Sector
Erase-Suspend-Program
Write Operation Status
DQ7
(Note 2)
DQ7#
0
DQ6
Toggle
Toggle
DQ5
(Note 1)
0
0
DQ3
N/A
1
DQ2
(Note 2)
No toggle
Toggle
RY/BY#
0
0
1
No toggle
0
N/A
Toggle
1
Data
Data
Data
Data
Data
1
DQ7#
Toggle
0
N/A
N/A
0
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
Refer to the section on DQ5 for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further
details.
3. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm
is in progress. The device outputs array data if the system addresses a non-busy bank.
May 26, 2004
Am29DL16xD
33
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C
20 ns
Ambient Temperature
with Power Applied. . . . . . . . . . . . . . –65°C to +125°C
+0.8 V
Voltage with Respect to Ground
–0.5 V
VCC (Note 1) . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V
A9, OE#, and RESET#
(Note 2) . . . . . . . . . . . . . . . . . . . .–0.5 V to +12.5 V
20 ns
–2.0 V
20 ns
WP#/ACC . . . . . . . . . . . . . . . . . . –0.5 V to +10.5 V
Figure 7. Maximum Negative
Overshoot Waveform
All other pins (Note 1) . . . . . . –0.5 V to VCC +0.5 V
Output Short Circuit Current (Note 3) . . . . . . 200 mA
Notes:
1. Minimum DC voltage on input or I/O pins is –0.5 V.
During voltage transitions, input or I/O pins may
overshoot V SS to –2.0 V for periods of up to 20 ns.
Maximum DC voltage on input or I/O pins is VCC +0.5 V.
See Figure 7. During voltage transitions, input or I/O pins
may overshoot to VCC +2.0 V for periods up to 20 ns. See
Figure 8.
2. Minimum DC input voltage on pins A9, OE#, RESET#,
and WP#/ACC is –0.5 V. During voltage transitions, A9,
OE#, WP#/ACC, and RESET# may overshoot VSS to
–2.0 V for periods of up to 20 ns. See Figure 7. Maximum
DC input voltage on pin A9 is +12.5 V which may
overshoot to +14.0 V for periods up to 20 ns. Maximum
DC input voltage on WP#/ACC is +9.5 V which may
overshoot to +12.0 V for periods up to 20 ns.
20 ns
VCC
+2.0 V
VCC
+0.5 V
2.0 V
20 ns
20 ns
Figure 8. Maximum Positive
Overshoot Waveform
3. No more than one output may be shorted to ground at a
time. Duration of the short circuit should not be greater
than one second.
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This
is a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the
operational sections of this data sheet is not implied.
Exposure of the device to absolute maximum rating
conditions for extended periods may affect device reliability.
OPERATING RANGES
Industrial (I) Devices
Ambient Temperature (TA) . . . . . . . . . –40°C to +85°C
VCC Supply Voltages
VCC for standard voltage range . . . . . . . 2.7 V to 3.6 V
Operating ranges define those limits between which the functionality of the device is guaranteed.
34
Am29DL16xD
May 26, 2004
DC CHARACTERISTICS
CMOS Compatible
Parameter
Symbol
Parameter Description
Test Conditions
Min
ILI
Input Load Current
VIN = VSS to VCC,
VCC = VCC max
ILIT
A9 Input Load Current
VCC = VCC max; A9 = 12.5 V
ILO
Output Leakage Current
VOUT = VSS to VCC,
VCC = VCC max
Typ
Max
Unit
±1.0
µA
35
µA
±1.0
µA
CE# = VIL, OE# = VIH,
Byte Mode
5 MHz
10
16
1 MHz
2
4
CE# = VIL, OE# = VIH,
Word Mode
5 MHz
10
16
1 MHz
2
4
ICC2
VCC Active Write Current (Notes 2, 3) CE# = VIL, OE# = VIH, WE# = VIL
15
30
mA
ICC3
VCC Standby Current (Note 2)
CE#, RESET# = VCC ± 0.3 V
0.2
5
µA
ICC4
VCC Reset Current (Note 2)
RESET# = VSS ± 0.3 V
0.2
5
µA
ICC5
Automatic Sleep Mode (Notes 2, 4)
VIH = VCC ± 0.3 V;
VIL = VSS ± 0.3 V
0.2
5
µA
VCC Active Read-While-Program
Current (Notes 1, 2)
Byte
21
45
ICC6
CE# = VIL, OE# = VIH
Word
21
45
VCC Active Read-While-Erase
Current (Notes 1, 2)
Byte
21
45
ICC7
CE# = VIL, OE# = VIH
Word
21
45
ICC8
VCC Active
Program-While-Erase-Suspended
Current (Notes 2, 5)
CE# = VIL, OE# = VIH
17
35
mA
ACC Accelerated Program Current,
Word or Byte
ACC pin
5
10
mA
IACC
CE# = VIL, OE# = VIH
VCC pin
15
30
mA
VIL
Input Low Voltage
–0.5
0.8
V
VIH
Input High Voltage
0.7 x VCC
VCC + 0.3
V
VHH
Voltage for WP#/ACC Sector
Protect/Unprotect and Program
Acceleration
VCC = 3.0 V ± 10%
8.5
9.5
V
VID
Voltage for Autoselect and Temporary
VCC = 3.0 V ± 10%
Sector Unprotect
8.5
12.5
V
VOL
Output Low Voltage
0.45
V
ICC1
VOH1
VCC Active Read Current
(Notes 1, 2)
Output High Voltage
VOH2
VLKO
mA
mA
IOL = 4.0 mA, VCC = VCC min
IOH = –2.0 mA, VCC = VCC min
0.85 VCC
IOH = –100 µA, VCC = VCC min
VCC–0.4
Low VCC Lock-Out Voltage (Note 5)
mA
2.3
V
2.5
V
Notes:
1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH.
2. Maximum ICC specifications are tested with VCC = VCCmax.
3. ICC active while Embedded Erase or Embedded Program is in progress.
4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode current is
200 nA.
5. Not 100% tested.
May 26, 2004
Am29DL16xD
35
DC CHARACTERISTICS
Zero-Power Flash
25
Supply Current in mA
20
15
10
5
0
0
500
1000
1500
2000
2500
3000
3500
4000
Time in ns
Note: Addresses are switching at 1 MHz
Figure 9.
ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)
12
3.6 V
10
2.7 V
Supply Current in mA
8
6
4
2
0
1
2
3
4
5
Frequency in MHz
Note: T = 25 °C
Figure 10.
36
Typical ICC1 vs. Frequency
Am29DL16xD
May 26, 2004
TEST CONDITIONS
Table 16.
3.3 V
Test Condition
2.7 kΩ
Device
Under
Test
Test Specifications
70, 80
Output Load
30
Input Rise and Fall Times
6.2 kΩ
Figure 11.
100
pF
5
ns
0.0–3.0
V
Input timing measurement
reference levels
1.5
V
Output timing measurement
reference levels
1.5
V
Input Pulse Levels
Note: Diodes are IN3064 or equivalent
Unit
1 TTL gate
Output Load Capacitance, CL
(including jig capacitance)
CL
90, 120
Test Setup
Key To Switching Waveforms
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
3.0 V
Input
Don’t Care, Any Change Permitted
Changing, State Unknown
Does Not Apply
Center Line is High Impedance State (High Z)
1.5 V
Measurement Level
1.5 V
Output
0.0 V
Figure 12.
May 26, 2004
Input Waveforms and Measurement Levels
Am29DL16xD
37
AC CHARACTERISTICS
Read-Only Operations
Parameter
JEDEC
Speed Options
Std Description
Test Setup
70
80
90
120
Unit
Min
70
80
90
120
ns
CE#, OE# = VIL
Max
70
80
90
120
ns
OE# = VIL
Max
70
80
90
120
ns
tAVAV
tRC
Read Cycle Time (Note 1)
tAVQV
tACC Address to Output Delay
tELQV
tCE
Chip Enable to Output Delay
tGLQV
tOE
Output Enable to Output Delay
Max
30
30
40
50
ns
tEHQZ
tDF
Chip Enable to Output High Z (Notes 1, 3)
Max
16
16
16
16
ns
tGHQZ
tDF
Output Enable to Output High Z (Notes 1, 3)
Max
16
16
16
16
ns
tAXQX
tOH
Output Hold Time From Addresses, CE# or
OE#, Whichever Occurs First
Min
0
ns
Read
Min
0
ns
tOEH
Output Enable Hold
Time (Note 1)
Toggle and
Data# Polling
Min
10
ns
Notes:
1. Not 100% tested.
2. See Figure 11 and Table 16 for test specifications.
3. Measurements performed by placing a 50-ohm termination on the data pin with a bias of VCC/2. The time from OE# high to
the data bus driven to VCC/2 is taken as tDF.
tRC
Addresses Stable
Addresses
tACC
CE#
tRH
tRH
tDF
tOE
OE#
tOEH
WE#
tCE
tOH
HIGH Z
HIGH Z
Output Valid
Outputs
RESET#
RY/BY#
0V
Figure 13.
38
Read Operation Timings
Am29DL16xD
May 26, 2004
AC CHARACTERISTICS
Hardware Reset (RESET#)
Parameter
JEDEC
Std
Description
All Speed Options
Unit
tReady
RESET# Pin Low (During Embedded Algorithms)
to Read Mode (See Note)
Max
20
µs
tReady
RESET# Pin Low (NOT During Embedded
Algorithms) to Read Mode (See Note)
Max
500
ns
tRP
RESET# Pulse Width
Min
500
ns
tRH
Reset High Time Before Read (See Note)
Min
50
ns
tRPD
RESET# Low to Standby Mode
Min
20
µs
tRB
RY/BY# Recovery Time
Min
0
ns
Note: Not 100% tested.
RY/BY#
CE#, OE#
tRH
RESET#
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
tReady
RY/BY#
tRB
CE#, OE#
RESET#
tRP
Figure 14.
May 26, 2004
Reset Timings
Am29DL16xD
39
AC CHARACTERISTICS
Word/Byte Configuration (BYTE#)
Parameter
JEDEC
Std
Speed Options
Description
70
tELFL/tELFH CE# to BYTE# Switching Low or High
80
90
Max
120
5
Unit
ns
tFLQZ
BYTE# Switching Low to Output HIGH Z
Max
25
25
30
30
ns
tFHQV
BYTE# Switching High to Output Active
Min
70
80
90
120
ns
CE#
OE#
BYTE#
BYTE#
Switching
from word
to byte
mode
tELFL
Data Output
(DQ0–DQ14)
DQ0–DQ14
Address
Input
DQ15
Output
DQ15/A-1
Data Output
(DQ0–DQ7)
tFLQZ
tELFH
BYTE#
BYTE#
Switching
from byte
to word
mode
Data Output
(DQ0–DQ7)
DQ0–DQ14
Address
Input
DQ15/A-1
Data Output
(DQ0–DQ14)
DQ15
Output
tFHQV
Figure 15.
BYTE# Timings for Read Operations
CE#
The falling edge of the last WE# signal
WE#
BYTE#
tSET
(tAS)
tHOLD (tAH)
Note: Refer to the Erase/Program Operations table for tAS and tAH specifications.
Figure 16.
40
BYTE# Timings for Write Operations
Am29DL16xD
May 26, 2004
AC CHARACTERISTICS
Erase and Program Operations
Parameter
Speed Options
JEDEC
Std
Description
tAVAV
tWC
Write Cycle Time (Note 1)
Min
tAVWL
tAS
Address Setup Time
Min
tASO
Address Setup Time to OE# low during toggle bit
polling
Min
15
15
15
15
ns
tAH
Address Hold Time
Min
45
45
45
50
ns
tAHT
Address Hold Time From CE# or OE# high
during toggle bit polling
Min
tDVWH
tDS
Data Setup Time
Min
tWHDX
tDH
Data Hold Time
Min
tOEPH
Output Enable High during toggle bit polling
Min
tGHWL
tGHWL
Read Recovery Time Before Write
(OE# High to WE# Low)
Min
0
ns
tELWL
tCS
CE# Setup Time
Min
0
ns
tWHEH
tCH
CE# Hold Time
Min
0
ns
tWLWH
tWP
Write Pulse Width
Min
30
30
35
50
ns
tWHDL
tWPH
Write Pulse Width High
Min
30
30
30
30
ns
tSR/W
Latency Between Read and Write Operations
Min
0
Byte
Typ
5
Word
Typ
7
tWLAX
70
80
90
120
Unit
70
80
90
120
ns
0
ns
0
35
35
ns
45
50
0
20
20
ns
ns
20
20
ns
ns
tWHWH1
tWHWH1
Programming Operation (Note 2)
tWHWH1
tWHWH1
Accelerated Programming Operation,
Word or Byte (Note 2)
Typ
4
µs
tWHWH2
tWHWH2
Sector Erase Operation (Note 2)
Typ
0.7
sec
tVCS
VCC Setup Time (Note 1)
Min
50
µs
tRB
Write Recovery Time from RY/BY#
Min
0
ns
Program/Erase Valid to RY/BY# Delay
Min
90
ns
tBUSY
µs
Notes:
1. Not 100% tested.
2. See the “Erase And Programming Performance” section for more information.
May 26, 2004
Am29DL16xD
41
AC CHARACTERISTICS
Program Command Sequence (last two cycles)
tAS
tWC
Addresses
Read Status Data (last two cycles)
555h
PA
PA
PA
tAH
CE#
tCH
OE#
tWHWH1
tWP
WE#
tWPH
tCS
tDS
tDH
PD
A0h
Data
Status
tBUSY
DOUT
tRB
RY/BY#
VCC
tVCS
Notes:
1. PA = program address, PD = program data, DOUT is the true data at the program address.
2. Illustration shows device in word mode.
Figure 17.
Program Operation Timings
VHH
WP#/ACC
VIL or VIH
VIL or VIH
tVHH
Figure 18.
42
tVHH
Accelerated Program Timing Diagram
Am29DL16xD
May 26, 2004
AC CHARACTERISTICS
Erase Command Sequence (last two cycles)
tAS
tWC
2AAh
Addresses
Read Status Data
VA
SA
VA
555h for chip erase
tAH
CE#
tCH
OE#
tWP
WE#
tWPH
tCS
tWHWH2
tDS
tDH
Data
55h
In
Progress
30h
Complete
10 for Chip Erase
tBUSY
tRB
RY/BY#
tVCS
VCC
Notes:
1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).
2. These waveforms are for the word mode.
Figure 19.
May 26, 2004
Chip/Sector Erase Operation Timings
Am29DL16xD
43
AC CHARACTERISTICS
Addresses
tWC
tWC
tRC
Valid PA
Valid RA
tWC
Valid PA
Valid PA
tAH
tCPH
tACC
tCE
CE#
tCP
tOE
OE#
tOEH
tGHWL
tWP
WE#
tDF
tWPH
tDS
tOH
tDH
Valid
Out
Valid
In
Data
Valid
In
Valid
In
tSR/W
WE# Controlled Write Cycle
Read Cycle
Figure 20.
CE# Controlled Write Cycles
Back-to-back Read/Write Cycle Timings
tRC
Addresses
VA
VA
VA
tACC
tCE
CE#
tCH
tOE
OE#
tOEH
tDF
WE#
tOH
High Z
DQ7
Complement
Complement
DQ0–DQ6
Status Data
Status Data
True
Valid Data
High Z
True
Valid Data
tBUSY
RY/BY#
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data
read cycle.
Figure 21.
44
Data# Polling Timings (During Embedded Algorithms)
Am29DL16xD
May 26, 2004
AC CHARACTERISTICS
tAHT
tAS
Addresses
tAHT
tASO
CE#
tCEPH
tOEH
WE#
tOEPH
OE#
tDH
DQ6/DQ2
tOE
Valid Data
Valid
Status
Valid
Status
Valid
Status
(first read)
(second read)
(stops toggling)
Valid Data
RY/BY#
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read
cycle, and array data read cycle
Figure 22.
Enter
Embedded
Erasing
WE#
Erase
Suspend
Erase
Toggle Bit Timings (During Embedded Algorithms)
Enter Erase
Suspend Program
Erase
Suspend
Program
Erase Suspend
Read
Erase
Resume
Erase Suspend
Read
Erase
Erase
Complete
DQ6
DQ2
Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE# to toggle
DQ2 and DQ6.
Figure 23.
May 26, 2004
DQ2 vs. DQ6
Am29DL16xD
45
AC CHARACTERISTICS
Temporary Sector/Sector Block Unprotect
Parameter
JEDEC
Std
Description
All Speed Options
Unit
tVIDR
VID Rise and Fall Time (See Note)
Min
500
ns
tVHH
VHH Rise and Fall Time (See Note)
Min
250
ns
tRSP
RESET# Setup Time for Temporary
Sector/Sector Block Unprotect
Min
4
µs
tRRB
RESET# Hold Time from RY/BY# High for
Temporary Sector/Sector Block Unprotect
Min
4
µs
Note: Not 100% tested.
VID
RESET#
VID
VSS, VIL,
or VIH
VSS, VIL,
or VIH
tVIDR
tVIDR
Program or Erase Command Sequence
CE#
WE#
tRRB
tRSP
RY/BY#
Figure 24.
46
Temporary Sector/Sector Block Unprotect Timing Diagram
Am29DL16xD
May 26, 2004
AC CHARACTERISTICS
VID
VIH
RESET#
SA, A6,
A1, A0
Valid*
Valid*
Sector/Sector Block Protect or Unprotect
Data
60h
60h
Valid*
Verify
40h
Status
Sector/Sector Block Protect: 150 µs,
Sector/Sector Block Unprotect: 15 ms
1 µs
CE#
WE#
OE#
* For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.
Figure 25.
May 26, 2004
Sector/Sector Block Protect and Unprotect Timing Diagram
Am29DL16xD
47
AC CHARACTERISTICS
Alternate CE# Controlled Erase and Program Operations
Parameter
Speed Options
JEDEC
Std
Description
70
80
90
120
Unit
tAVAV
tWC
Write Cycle Time (Note 1)
Min
70
80
90
120
ns
tAVWL
tAS
Address Setup Time
Min
tELAX
tAH
Address Hold Time
Min
45
45
45
50
ns
tDVEH
tDS
Data Setup Time
Min
35
35
45
50
ns
tEHDX
tDH
Data Hold Time
Min
0
ns
tGHEL
tGHEL
Read Recovery Time Before Write
(OE# High to WE# Low)
Min
0
ns
tWLEL
tWS
WE# Setup Time
Min
0
ns
tEHWH
tWH
WE# Hold Time
Min
0
ns
tELEH
tCP
CE# Pulse Width
Min
30
30
45
50
ns
tEHEL
tCPH
CE# Pulse Width High
Min
30
30
30
30
ns
tWHWH1
tWHWH1
Programming Operation
(Note 2)
tWHWH1
tWHWH1
tWHWH2
tWHWH2
0
ns
Byte
Typ
5
Word
Typ
7
Accelerated Programming Operation,
Word or Byte (Note 2)
Typ
4
µs
Sector Erase Operation (Note 2)
Typ
0.7
sec
µs
Notes:
1. Not 100% tested.
2. See the “Erase And Programming Performance” section for more information.
48
Am29DL16xD
May 26, 2004
AC CHARACTERISTICS
555 for program
2AA for erase
PA for program
SA for sector erase
555 for chip erase
Data# Polling
Addresses
PA
tWC
tAS
tAH
tWH
WE#
tGHEL
OE#
tWHWH1 or 2
tCP
CE#
tWS
tCPH
tBUSY
tDS
tDH
DQ7#
Data
tRH
A0 for program
55 for erase
DOUT
PD for program
30 for sector erase
10 for chip erase
RESET#
RY/BY#
Notes:
1. Figure indicates last two bus cycles of a program or erase operation.
2. PA = program address, SA = sector address, PD = program data.
3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device.
4. Waveforms are for the word mode.
Figure 26.
May 26, 2004
Alternate CE# Controlled Write (Erase/Program) Operation Timings
Am29DL16xD
49
ERASE AND PROGRAMMING PERFORMANCE
Parameter
Typ (Note 1)
Max (Note 2)
Unit
Comments
Sector Erase Time
0.7
15
sec
Chip Erase Time
27
Excludes 00h programming
prior to erasure (Note 4)
Byte Program Time
5
150
µs
Word Program Time
7
210
µs
Accelerated Byte/Word Program Time
4
120
µs
Chip Program Time
(Note 3)
sec
Byte Mode
9
27
Word Mode
6
18
Excludes system level
overhead (Note 5)
sec
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC, 1,000,000 cycles. Additionally,
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 2.7 V, 1,000,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table
14 for further information on command definitions.
6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles.
LATCHUP CHARACTERISTICS
Description
Min
Max
Input voltage with respect to VSS on all pins except I/O pins
(including A9, OE#, and RESET#)
–1.0 V
12.5 V
Input voltage with respect to VSS on all I/O pins
–1.0 V
VCC + 1.0 V
–100 mA
+100 mA
VCC Current
Note: Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time.
PACKAGE AND PIN CAPACITANCE
Parameter Symbol
Parameter Description
Test Setup
CIN
Input Capacitance
VIN = 0
COUT
Output Capacitance
VOUT = 0
CIN2
Control Pin Capacitance
VIN = 0
Typ
Max
Unit
TSOP/SO
6
7.5
pF
BGA
4.2
5
pF
TSOP/SO
8.5
12
pF
BGA
5.4
6.5
pF
TSOP/SO
7.5
9
pF
BGA
3.9
4.7
pF
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
DATA RETENTION
Parameter Description
Minimum Pattern Data Retention Time
50
Am29DL16xD
Test Conditions
Min
Unit
150°C
10
Years
125°C
20
Years
May 26, 2004
PHYSICAL DIMENSIONS
FBC048—48-Ball Fine-Pitch Ball Grid Array
8 x 9 mm package
Dwg rev AF; 10/99
May 26, 2004
Am29DL16xD
51
PHYSICAL DIMENSIONS
LAA064—64-Ball Fortified Ball Grid Array,
13 x 11 mm package
52
Am29DL16xD
May 26, 2004
PHYSICAL DIMENSIONS
TS 048—48-Pin Standard TSOP
Dwg rev AA; 10/99
May 26, 2004
Am29DL16xD
53
PHYSICAL DIMENSIONS
VBF048—48-Ball Very Thin Profile Fine-Pitch Ball Grid Array
54
Am29DL16xD
May 26, 2004
REVISION SUMMARY
Revision A (September 1998)
Ordering Information
Initial release.
Added 70, 90R, and 120R speed options to the valid
combination table. Reverted FBGA designator back to
WC.
Revision B (October 1998)
Global
Deleted the 90R and 120R speed options. Expanded
the full voltage range to 2.7–3.6 V.
SecSi (Secured Silicon) Sector Flash Memory
Region
Added 125°C to 20-year data retention bullet.
Factory Locked: SecSi Sector Programmed and Protected at the Factory: Corrected the address range of
the ESN and distinguished between word and byte
modes.
Connection Diagrams
Operating Ranges
Changed the FBGA diagram from bottom view to top view.
VCC Supply Voltages: Replaced single voltage range
with voltage ranges for standard and regulated
devices.
Distinctive Characteristics
Ordering Information
Changed the FBGA ordering nomenclature to “YC.”
The package designation is now FBC048. Reverted to
WC in Revision C.
DC Characteristics
Revision C+1 (March 19, 1999)
SecSi (Secured Silicon) Sector Flash Memory
Region
Customer Lockable subsection: In the bullets, text
should refer to “Enter SecSi Sector Region command
sequence.”
Changed maximum ILI current to ±3.0 µA.
Physical Dimensions
Updated the FBGA drawing, table, and notes. The
package designation is now FBC048. Deleted 40-pin
TSOP drawing.
Revision C+2 (June 14, 1999)
Revision B+1 (October 1998)
Revision C+3 (August 9, 1999)
Command Definitions table
Global
Added the term “sector block” to the notes
where appropriate.
Added Am29DL164 specifications to the document.
DC Characteristics
Added the 70R speed option for the DL163, deleted
the SSOP for the DL162.
Changed data sheet status to Preliminary.
Ordering Information
Changed maximum ILI current to ±1.0 µA.
AC Characteristics
Test Specifications table
Temporary Sector Unprotect: Moved the accelerated
program timing diagram to follow the program operations timings. Added the term “sector block” where
appropriate elsewhere on the page.
The 90 ns speed option is tested at 100 pF loading.
Revision C (January 1998)
Temperature Range: Added “C = Commercial (0°C to
+70°C)”.
Revision C+4 (August 23, 1999)
Ordering Information
Global
Operating Ranges
Changed data sheet title.
Added commercial device.
Product Selector Guide
Replaced “Full Voltage Range: VCC = 2.7–3.6 V” with
“Standard Voltage Range: VCC = 2.7–3.3 V.” Each part
number now has a separate set of speed options.
Revision C+5 (October 18, 1999)
Device Bus Operations
Autoselect Mode: Added Am29DL164 device IDs to
the Autoselect Codes table.
May 26, 2004
Am29DL16xD
55
Revision D (February 22, 2000)
Command Definitions
Global
Table 14, Command Definitions: The SecSi Sector Indicator Bit values have changed from 80h and 00h to
81h and 01h, respectively.
The Am29DL16x family has migrated to a new 0.23
µm process technology, which is indicated by a “D” in
the ordering part number. All references in this document have been changed to reflect the new process.
Distinctive Characteristics
Under “Performance Characteristics,” the typical accelerated programming time was changed to match the
AC tables.
AC Characteristics
Figure 17, Program Operations Timing; Figure 19,
Chip/Sector Erase Operations: Deleted t GHWL and
changed OE# waveform to start at high.
Erase and Program Operations table; Alternate CE#
Controlled Erase and Program Operations table:
Changed the typical and maximum specifications for
programming time.
AC Characteristics
Read-only Operations table: Changed parameter tDF to
16 ns for all speed options. Added Note 3.
Revision D+2 (September 4, 2000)
Deleted remaining references to 80 ns speed option,
which was officially removed in Revision D+1. Corrected references to Am29DL16xC, which officially
changed to Am29DL16xD in Revision D.
Revision D+3 (November 22, 2000)
Global
Deleted Preliminary status from document. Added
table of contents.
Revision E (July 2, 2001)
Erase and Programming Performance
In the table, changed the typical and maximum specifications for programming time. The typical and maximum chip programming times in both byte and word
modes are reduced.
Physical Dimensions
Added Am29DL161D device to data sheet. Deleted
extended temperature range devices.
Sector/Sector Block Protection and Unprotection
Noted that sectors are unprotected in parallel.
SecSi‰ (Secured Silicon) Sector Flash
Memory Region
Replaced figures with more detailed illustrations.
Revision D+1 (June 21, 2000)
Global
Data sheet designation has changed from “Advance
Information” to “Preliminary.”
Deleted references to the 56-pin SSOP and the corresponding 70R speed option.
Noted changes for upcoming versions of these devices: reduced SecSi Sector size and deletion of
SecSi Sector erase functionality. Current versions of
these devices remain unaffected.
Revision E+1 (July 29, 2002)
Global
Added 64-ball Fortified BGA package.
Ordering Information
Added valid combinations for the Am29DL164D device
i n T S O P. A d d e d va l i d c o m b i n a t i o n s fo r t h e
Am29DL162D devices in TSOP and FBGA packages.
D e l e t e d v a l i d c o m b i n a t i o n s fo r t h e 8 0 n s
Am29DL164D device in FBGA package.
Command Definitions
Modified caution to state that incorrect command/sequences may place device in unknown state, upon
which device must be reset.
Device Bus Operations
Unlock Bypass Command Sequence; Command
Definitions table
Table 3, Sector Addresses for Top Boot Sector Devices: In note below table, corrected last device part
number to top boot.
Corrected table and description to indicated that bank
address is not required for unlock bypass reset.
Table 7, Autoselect Codes: The SecSi Sector Indicator
Bit values have changed from 80h and 00h to 81h and
01h, respectively.
56
Package Capacitance
Added BGA capacitance specifications.
Am29DL16xD
May 26, 2004
Revision E + 2 (February 14, 2003)
Revision E+3 (February 25, 2004)
Global
AC Characteristics
Added VBF048 package, Very Thin Profile Fine Pitch
Ball Grid Array, to Distinctive Characteristics, General
Description, Ordering Information, Connection Diagrams, and Physical Dimensions sections.
Corrected tSR/W in Figure 20, Back-to-back Read/Write
Cycle Timings.
Revision E+4 (May 26, 2004)
Ordering Information
Added Pb-Free OPNs.
Trademarks
Copyright © 2004 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
May 26, 2004
Am29DL16xD
57