Revised May 2000 DM74S280 9-Bit Parity Generator/Checker General Description Features These universal, nine-bit parity generators/checkers utilize Schottky-clamped TTL high-performance circuitry, and feature odd/even outputs to facilitate operation of either odd or even parity applications. The word-length capability is easily expanded by cascading. ■ Generates either odd or even parity for nine data lines The DM74S280 can be used to upgrade the performance of most systems utilizing the DM74180 parity generator/ checker. Although the DM74S280 is implemented without expander inputs, the corresponding function is provided by the availability of all input at pin 4, and no internal connection at pin 3. This permits the DM74S280 to be substituted for the 180 in existing designs to produce an identical function, even if DM74S280’s are mixed with existing 180’s. ■ Cascadable for N-bits ■ Can be used to upgrade existing systems using MSI parity circuits ■ Typical data-to-output delay—14 ns Input buffers are provided so that each input represents only one normal 74S load, and full fan-out to 10 normal Series 74S loads is available from each of the outputs at low logic levels. A fan-out to 20 normal Series 74S loads is provided at high logic levels, to facilitate connection of unused inputs to used inputs. Ordering Code: Order Number Package Number Package Description DM74S280M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow DM74S280N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Function Table Number of Inputs © 2000 Fairchild Semiconductor Corporation DS006483 Outputs (A Thru I) that are HIGH ∑ Even 0, 2, 4, 6, 8 H ∑ Odd L 1, 3, 5, 7, 9 L H www.fairchildsemi.com DM74S280 9-Bit Parity Generator/Checker August 1986 DM74S280 Logic Diagram Typical Applications Three DM74S280’s can be used to implement a 25-line parity generator/checker. This arrangement will provide parity in typically 25 ns. (See Figure 1.) Longer word lengths can be implemented by cascading DM74S280’s. As shown in Figure 2, parity can be generated for word lengths up to 81 bits in typically 25 ns. FIGURE 1. 25-Line Parity/Generator Checker FIGURE 2. 81-Line Parity/Generator Checker www.fairchildsemi.com 2 Supply Voltage Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. 7V Input Voltage 5.5V 0°C to +70°C Operating Free Air Temperature Range −65°C to +150°C Storage Temperature Range Recommended Operating Conditions Symbol Parameter Min Nom Max 4.75 5 5.25 Units VCC Supply Voltage VIH HIGH Level Input Voltage VIL LOW Level Input Voltage 0.8 V IOH HIGH Level Output Current −1 mA IOL LOW Level Output Current 20 mA TA Free Air Operating Temperature 70 °C V 2 V 0 Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter Conditions VI Input Clamp Voltage VCC = Min, II=−18 mA VOH HIGH Level VCC = Min, IOH = Max Output Voltage VIL = Max, VIH = Min LOW Level VCC = Min, IOL =Max VOL Output Voltage VIH = Min, VIL = Max II Input Current @ Max Input Voltage VCC = Max, VI = 5.5V Min 2.7 Typ (Note 2) Max Units −1.2 V 3.4 V 0.5 V 1 mA IIH HIGH Level Input Current VCC = Max, VI = 2.7V 50 µA IIL LOW Level Input Current VCC = Max, VI = 0.5V −2 mA IOS Short Circuit Output Current VCC = Max (Note 3) −100 mA ICC Supply Current VCC Max (Note 4) 105 mA −40 67 Note 2: All typicals are at VCC = 5V, TA = 25°C. Note 3: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 4: ICC is measured with all inputs grounded and all outputs OPEN. Switching Characteristics at VCC = 5V and TA = 25°C Symbol Parameter From (Input) To (Output) tPLH Propagation Delay Time LOW-to-HIGH Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output tPLH Propagation Delay Time LOW-to-HIGH Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output RL = 280Ω RL = 280Ω CL = 15 pF CL = 50 pF Min Max Min Units Max Data to ∑ Even 21 24 ns Data to ∑ Even 18 21 ns Data to ∑ Odd 21 24 ns Data to ∑ Odd 18 21 ns 3 www.fairchildsemi.com DM74S280 Absolute Maximum Ratings(Note 1) DM74S280 Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow Package Number M14A www.fairchildsemi.com 4 DM74S280 9-Bit Parity Generator/Checker Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N14A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 5 www.fairchildsemi.com