300 MHz, 32 × 16 Buffered Analog Crosspoint Switch ADV3202/ADV3203 FEATURES Large, 32 × 16, nonblocking switch array G = +1 (ADV3202) or G = +2 (ADV3203) operation 32 × 32 pin-compatible version available (ADV3200/ADV3201) Single +5 V, dual ±2.5 V, or dual ±3.3 V supply (G = +2) Serial programming of switch array 2:1 OSD insertion mux per output Input sync-tip clamp High impedance output disable allows connection of multiple devices with minimal output bus load Excellent video performance 60 MHz 0.1 dB gain flatness 0.1% differential gain error (RL = 150 Ω) 0.1° differential phase error (RL = 150 Ω) Excellent ac performance Bandwidth: >300 MHz Slew rate: >400 V/μs Low power: 1 W Low all hostile crosstalk: −48 dB @ 5 MHz Reset pin allows disabling of all outputs Connected through a capacitor to ground, provides power-on reset capability 176-lead exposed pad LQFP package (24 mm × 24 mm) FUNCTIONAL BLOCK DIAGRAM VPOS VNEG DVCC DGND CLK 193-BIT SHIFT REGISTER DATA OUT DATA IN 96 97 UPDATE CS RESET 96 SYNC-TIP CLAMP .. . .. . 16 16 × 5:32 DECODERS ENABLE/ BYPASS 32 INPUTS ADV3202 (ADV3203) PARALLEL LATCH ENABLE/ DISABLE OUTPUT BUFFER G = +1 (G = +2) 512 SWITCH MATRIX .. . OSD MUX 16 .. . 16 OUTPUTS 16 REFERENCE CCTV surveillance Routing of high speed signals, including Composite video (NTSC, PAL, S, SECAM) RGB and component video routing Compressed video (MPEG, wavelet) Video conferencing VCLAMP OSD OSD VREF INPUTS SWITCHES 07526-001 APPLICATIONS Figure 1. GENERAL DESCRIPTION The ADV3202/ADV3203 are 32 × 16 analog crosspoint switch matrices. They feature a selectable sync-tip clamp input for ac-coupled applications and a 2:1 on-screen display (OSD) insertion mux. With −48 dB of crosstalk and −80 dB isolation at 5 MHz, the ADV3202/ADV3203 are useful in many high density routing applications. The 0.1 dB flatness out to 60 MHz makes the ADV3202/ADV3203 ideal for both composite and component video switching. an output bus if building a larger array. The ADV3202 has a gain of +1 while the ADV3203 has a gain of +2 for ease of use in back-terminated load applications. A single +5 V supply, dual ±2.5 V supplies, or dual ±3.3 V supplies (G = +2) can be used while consuming only 195 mA of idle current with all outputs enabled. The channel switching is performed via a double buffered, serial digital control that can accommodate daisy chaining of several devices. The 16 independent output buffers of the ADV3202/ADV3203 can be placed into a high impedance state for paralleling crosspoint outputs so that off-channels present minimal loading to The ADV3202/ADV3203 are packaged in a 176-lead exposed pad LQFP package (24 mm× 24 mm) and are available over the extended industrial temperature range of −40°C to +85°C. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2008 Analog Devices, Inc. All rights reserved. ADV3202/ADV3203 TABLE OF CONTENTS Features .............................................................................................. 1 Power Dissipation..........................................................................6 Applications ....................................................................................... 1 ESD Caution...................................................................................6 Functional Block Diagram .............................................................. 1 Pin Configuration and Function Descriptions..............................7 General Description ......................................................................... 1 Truth Table and Logic Diagram ............................................... 10 Revision History ............................................................................... 2 Typical Performance Characteristics ........................................... 11 Specifications..................................................................................... 3 Theory of Operation ...................................................................... 14 OSD Disabled ................................................................................ 3 Applications Information .............................................................. 16 OSD Enabled ................................................................................. 4 Programming .............................................................................. 16 Timing Characteristics (Serial Mode) ....................................... 5 Outline Dimensions ....................................................................... 17 Absolute Maximum Ratings............................................................ 6 Ordering Guide .......................................................................... 17 Thermal Resistance ...................................................................... 6 REVISION HISTORY 10/08—Revision 0: Initial Version Rev. 0 | Page 2 of 20 ADV3202/ADV3203 SPECIFICATIONS OSD DISABLED VS = ±2.5 V (ADV3202), VS = ±3.3 V (ADV3203) at TA = 25°C, G = +1 (ADV3202), G = +2 (ADV3203), RL = 150 Ω, all configurations, unless otherwise noted. Table 1. Parameter DYNAMIC PERFORMANCE −3 dB Bandwidth Gain Flatness Settling Time Slew Rate NOISE/DISTORTION PERFORMANCE Differential Gain Error Differential Phase Error Crosstalk, All Hostile, RTI Off Isolation, Input-to-Output Input Voltage Noise DC PERFORMANCE Gain Error Gain Matching OUTPUT CHARACTERISTICS Output Impedance Output Capacitance Output Voltage Range INPUT CHARACTERISTICS Input Offset Voltage Input Voltage Range Input Capacitance Input Resistance Input Bias Current SWITCHING CHARACTERISTICS Enable On Time Switching Time, 2 V Step Switching Transient (Glitch) Conditions Min ADV3202/ADV3203 Typ Max Unit 200 mV p-p 2 V p-p 0.1 dB, 200 mV p-p 0.1 dB, 2 V p-p 1% , 2 V step 2 V step, peak 300 120 60 40 6 400 MHz MHz MHz MHz ns V/μs NTSC or PAL NTSC or PAL f = 5 MHz, RL = 150 Ω RL = 1 kΩ f = 100 MHz, RL = 150 Ω RL = 1 kΩ f = 5 MHz, one channel 0.1 MHz to 50 MHz 0.06/0.1 0.06/0.03 −48 −65 −23 −30 −80 25/22 % Degrees dB dB dB dB dB nV/√Hz Broadcast mode, no load Broadcast mode No load, channel-to-channel Channel-to-channel ±0.5 ±0.5 ±0.5/±0.8 ±0.5/±0.8 DC, enabled DC, disabled Disabled ADV3202 ADV3203 ADV3203, no output load −1.1 to +1.1 −1.5 to +1.5 −1.5 to +1.5 ADV3202 ADV3203 ADV3203, no output load −1.1 to +1.1 −0.75 to +0.75 −0.75 to +0.75 Sync-tip clamp enabled, VIN = VCLAMP + 0.1 V Sync-tip clamp enabled, VIN = VCLAMP − 0.1 V Sync-tip clamp disabled 50% update to 1% settling 50% update to 1% settling IN00 to IN31, RTI Rev. 0 | Page 3 of 20 900/3.2 ±1.75/±2.2 ±2.2/±2.7 ±2.8 ±3.4 0.15 1000/4 3.7 −1.2 to +1.2 −1.6 to +2.0 −2.0 to +2.0 % % % % Ω kΩ pF V V V 1 0.1 ±5 −1.2 to +1.2 −0.8 to +1.0 −1.0 to +1.0 3 4 3 ±30 12 mV V V V pF MΩ μA −2.9 −1 −0.25 mA −10 −3 μA 50 40 300 ns ns mV p-p ADV3202/ADV3203 Parameter POWER SUPPLIES Supply Current Supply Voltage Range PSR OPERATING TEMPERATURE RANGE Temperature Range θJA Conditions ADV3202/ADV3203 Typ Max Min Unit 195/200 220/235 mA 155/165 3.5 mA mA V VNEG, VPOS, f = 1 MHz 120/130 2.5 5 ± 10%/ 6.6 ± 10% −50/−45 Operating (still air) Operating (still air) −40 to +85 16 VPOS or VNEG, outputs enabled, no load VPOS or VNEG, outputs disabled DVCC VPOS − VNEG dB °C °C/W OSD ENABLED VS = ±2.5 V (ADV3202), VS = ±3.3 V (ADV3203) at TA = 25°C, G = +1 (ADV3202), G = +2 (ADV3203), RL = 150 Ω, all configurations, unless otherwise noted. Table 2. Parameter OSD DYNAMIC PERFORMANCE −3 dB Bandwidth Gain Flatness Settling Time Slew Rate OSD NOISE/DISTORTION PERFORMANCE Differential Gain Error Differential Phase Error Input Voltage Noise OSD DC PERFORMANCE Gain Error OSD INPUT CHARACTERISTICS Input Bias Current OSD SWITCHING CHARACTERISTICS OSD Switch Delay, 2 V Step OSD Switching Transient (Glitch) Conditions Min ADV3202/ADV3203 Typ Max Unit 200 mV p-p 2 V p-p 0.1 dB, 200 mV p-p 0.1 dB, 2 V p-p 1%, 2 V step 2 V step, peak 170/150 135/130 35 35 6 400 MHz MHz MHz MHz ns V/μs NTSC or PAL NTSC or PAL 0.5 MHz to 50 MHz 0.12/0.35 0.06/0.04 27/25 % Degrees nV/√Hz No load ±0.1 ±0.1 Sync-tip clamp disabled 50% OSD switch to 1% settling Rev. 0 | Page 4 of 20 −10 ±2.3/±2.2 ±2.7 % % −4 μA 20 15/40 ns mV p-p ADV3202/ADV3203 TIMING CHARACTERISTICS (SERIAL MODE) Specifications subject to change without notice. Table 3. Parameter Serial Data Setup Time CLK Pulse Width Serial Data Hold Time CLK Pulse Separation CLK to UPDATE Delay UPDATE Pulse Width CLK to DATA OUT Valid Propagation Delay, UPDATE to Switch On or Off Data Load Time, CLK = 5 MHz, Serial Mode RESET Time Symbol t1 t2 t3 t4 t5 t6 t7 Min 40 50 50 150 Limit Typ Max 50 160 Unit ns ns ns ns ns ns ns ns μs ns 40 130 50 38.6 160 1 CS 0 t2 1 t4 LOAD DATA INTO SERIAL REGISTER ON RISING EDGE CLK 0 t1 t3 1 CLAMP ON/OFF DATA IN OUT15 (D5) OUT00 (D0) 0 t5 1 = LATCHED t6 TRANSFER DATA FROM SERIAL REGISTER TO PARALLEL LATCHES DURING LOW LEVEL UPDATE 0 = TRANSPARENT 07526-002 t7 DATA OUT Figure 2. Timing Diagram, Serial Mode Table 4. Logic Levels, DVCC = 3.3 V VIH RESET, CS, CLK, DATA IN, UPDATE, OSDS VIL RESET, CS, CLK, DATA IN, UPDATE, OSDS VOH DATA OUT VOL DATA OUT IIH RESET, CS, CLK, DATA IN, UPDATE, OSDS IIL RESET, CS, CLK, DATA IN, UPDATE, OSDS IOH DATA OUT IOL DATA OUT 2.5 V min 0.8 V max 2.7 V min 0.5 V max 0.5 μA typ −0.5 μA typ 3 mA typ −3 mA typ Rev. 0 | Page 5 of 20 ADV3202/ADV3203 ABSOLUTE MAXIMUM RATINGS POWER DISSIPATION Table 5. The ADV3202/ADV3203 are operated with ±2.5 V, +5 V, or ±3.3 V supplies and can drive loads down to 150 Ω, resulting in a large range of possible power dissipations. For this reason, extra care must be taken while derating the operating conditions based on ambient temperature. Rating 7.5 V 6V +0.5 V to –4 V 9.4 V <3 V <3 V 6V VPOS – 3.5 V to VNEG + 3.5 V VPOS – 4 V to VNEG + 4 V VNEG to VPOS DVCC (VPOS − 1 V) to (VNEG + 1 V) Packaged in a 176-lead exposed-pad LQFP, the ADV3202/ ADV3203 junction-to-ambient thermal impedance (θJA) is 16°C/W. For long-term reliability, the maximum allowed junction temperature of the die should not exceed 150°C. Temporarily exceeding this limit may cause a shift in parametric performance due to a change in stresses exerted on the die by the package. Exceeding a junction temperature of 175°C for an extended period can result in device failure. Figure 3 shows the range of allowed internal die power dissipations that meet these conditions over the −40°C to +85°C ambient temperature range. When using Figure 3, do not include external load power in the maximum power calculation, but do include load current dropped on the die output transistors. 9 Momentary 45 mA −65°C to +125°C −40°C to +85°C 300°C TJ = 150°C 8 MAXIMUM POWER (W) 150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE 6 5 4 3 15 25 ESD CAUTION Table 6. Thermal Resistance θJA 16 35 45 55 65 AMBIENT TEMPERATURE (°C) 75 85 Figure 3. Maximum Die Power Dissipation vs. Ambient Temperature θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Package Type 176-Lead LQFP_EP 7 07526-003 Parameter Analog Supply Voltage (VPOS − VNEG) Digital Supply Voltage (DVCC − DGND) Ground Potential Difference (VNEG − DGND) Maximum Potential Difference DVCC − VNEG Disabled Outputs ADV3202 (|VOSD − VOUT|) ADV3203 (|VOSD −(VOUT+VREF)/2|) |VCLAMP − VINxx| VREF Input Voltage ADV3202 ADV3203 Analog Input Voltage Digital Input Voltage Output Voltage (Disabled Analog Output) Output Short-Circuit Duration Output Short-Circuit Current Storage Temperature Range Operating Temperature Range Lead Temperature (Soldering, 10 sec) Junction Temperature Unit °C/W Rev. 0 | Page 6 of 20 ADV3202/ADV3203 134 133 135 137 136 138 140 139 141 142 143 144 145 148 147 146 150 149 151 152 153 155 154 156 157 158 159 160 161 162 163 164 165 166 168 167 169 170 171 173 172 174 1 132 PIN 1 2 131 3 130 4 129 5 128 6 127 7 126 8 125 9 124 10 123 11 122 12 121 13 120 14 119 15 118 16 117 17 116 18 115 19 114 20 113 21 112 ADV3202/ADV3203 22 111 TOP VIEW (Not to Scale) 23 24 110 109 25 108 26 107 27 106 28 105 29 104 30 103 31 102 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 VNEG NC NC NC NC NC OSDS00 IN16 OSDS01 IN17 OSDS02 IN18 OSDS03 IN19 OSDS04 IN20 OSDS05 IN21 OSDS06 IN22 OSDS07 IN23 OSDS08 IN24 OSDS09 IN25 OSDS10 IN26 OSDS11 IN27 OSDS12 IN28 OSDS13 IN29 OSDS14 IN30 OSDS15 IN31 VPOS OSD00 OSD01 OSD02 OSD03 VNEG OSD14 OSD13 OSD12 OSD11 OSD10 OSD09 OSD08 VPOS OUT15 VNEG OUT14 VPOS OUT13 VNEG OUT12 VPOS OUT11 VNEG OUT10 VPOS OUT09 VNEG OUT08 VPOS OUT07 VNEG OUT06 VPOS OUT05 VNEG OUT04 VPOS OUT03 VNEG OUT02 VPOS OUT01 VNEG OUT00 VPOS OSD07 OSD06 OSD05 OSD04 60 89 59 90 44 58 91 43 57 92 42 56 93 41 55 94 40 54 95 39 53 96 38 52 97 37 51 98 36 50 99 35 49 34 48 100 47 101 33 46 32 45 DVCC NC RESET CLK DATA IN DATA OUT UPDATE CS DGND IN00 DGND IN01 DGND IN02 DGND IN03 DGND IN04 DGND IN05 DGND IN06 DGND IN07 DGND IN08 DGND IN09 DGND IN10 DGND IN11 DGND IN12 DGND IN13 DGND IN14 DGND IN15 VNEG VREF VCLAMP OSD15 175 176 DGND NC NC NC NC NC NC NC VPOS NC VNEG NC VPOS NC VNEG NC VPOS NC VNEG NC VPOS NC VNEG NC VPOS NC VNEG NC VPOS NC VNEG NC VPOS NC VNEG NC VPOS NC VNEG NC VPOS NC NC NC PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 07526-004 NOTES 1. NC = NO CONNECT 2. OSDS#: OSD SELECT FOR OUTPUT # OSD#: OSD VIDEO INPUT FOR OUTPUT # 3. THE EXPOSED PAD SHOULD BE CONNECTED TO ANALOG GROUND. Figure 4. Pin Configuration Rev. 0 | Page 7 of 20 ADV3202/ADV3203 Table 7. Pin Function Descriptions Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Mnemonic DVCC NC RESET CLK DATA IN DATA OUT UPDATE CS DGND IN00 DGND IN01 DGND IN02 DGND IN03 DGND IN04 DGND IN05 DGND IN06 DGND IN07 DGND IN08 DGND IN09 DGND IN10 DGND IN11 DGND IN12 DGND IN13 DGND IN14 DGND IN15 VNEG VREF 43 VCLAMP 44 45 46 47 48 49 OSD15 OSD14 OSD13 OSD12 OSD11 OSD10 Description Digital Positive Power Supply. No Connect. Control Pin: 1st and 2nd Rank Reset. Control Pin: Serial Data Clock. Control Pin: Serial Data In. Control Pin: Serial Data Out. Control Pin: Second Rank Write Strobe. Control Pin: Chip Select. Digital Negative Power Supply. Input Number 0. Digital Negative Power Supply. Input Number 1. Digital Negative Power Supply. Input Number 2. Digital Negative Power Supply. Input Number 3. Digital Negative Power Supply. Input Number 4. Digital Negative Power Supply. Input Number 5. Digital Negative Power Supply. Input Number 6. Digital Negative Power Supply. Input Number 7. Digital Negative Power Supply. Input Number 8. Digital Negative Power Supply. Input Number 9. Digital Negative Power Supply. Input Number 10. Digital Negative Power Supply. Input Number 11. Digital Negative Power Supply. Input Number 12. Digital Negative Power Supply. Input Number 13. Digital Negative Power Supply. Input Number 14. Digital Negative Power Supply. Input Number 15. Analog Negative Power Supply. Reference Voltage. See the Theory of Operation section for details. Sync-Tip Clamp Voltage. See the Theory of Operation section for details. OSD Input Number 15. OSD Input Number 14. OSD Input Number 13. OSD Input Number 12. OSD Input Number 11. OSD Input Number 10. Pin 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Rev. 0 | Page 8 of 20 Mnemonic OSD09 OSD08 VPOS OUT15 VNEG OUT14 VPOS OUT13 VNEG OUT12 VPOS OUT11 VNEG OUT10 VPOS OUT09 VNEG OUT08 VPOS OUT07 VNEG OUT06 VPOS OUT05 VNEG OUT04 VPOS OUT03 VNEG OUT02 VPOS OUT01 VNEG OUT00 VPOS OSD07 OSD06 OSD05 OSD04 VNEG OSD03 OSD02 OSD01 OSD00 VPOS IN31 OSDS15 IN30 OSDS14 IN29 OSDS13 Description OSD Input Number 9. OSD Input Number 8. Analog Positive Power Supply. Output Number 15. Analog Negative Power Supply. Output Number 14. Analog Positive Power Supply. Output Number 13. Analog Negative Power Supply. Output Number 12. Analog Positive Power Supply. Output Number 11. Analog Negative Power Supply. Output Number 10. Analog Positive Power Supply. Output Number 9. Analog Negative Power Supply. Output Number 8. Analog Positive Power Supply. Output Number 7. Analog Negative Power Supply. Output Number 6. Analog Positive Power Supply. Output Number 5. Analog Negative Power Supply. Output number 4. Analog Positive Power Supply. Output Number 3. Analog Negative Power Supply. Output Number 2. Analog Positive Power Supply. Output Number 1. Analog Negative Power Supply. Output Number 0. Analog Positive Power Supply. OSD Input Number 7. OSD Input Number 6. OSD Input Number 5. OSD Input Number 4. Analog Negative Power Supply. OSD Input Number 3. OSD Input Number 2. OSD Input Number 1. OSD Input Number 0. Analog Positive Power Supply. Input Number 31. Control Pin: OSD Select Number 15. Input Number 30. Control Pin: OSD Select Number 14. Input Number 29. Control Pin: OSD Select Number 13. ADV3202/ADV3203 Pin 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 Mnemonic IN28 OSDS12 IN27 OSDS11 IN26 OSDS10 IN25 OSDS09 IN24 OSDS08 IN23 OSDS07 IN22 OSDS06 IN21 OSDS05 IN20 OSDS04 IN19 OSDS03 IN18 OSDS02 IN17 OSDS01 IN16 OSDS00 NC NC NC NC NC VNEG NC NC NC VPOS NC VNEG NC Description Input Number 28. Control Pin: OSD Select Number 12. Input Number 27. Control Pin: OSD Select Number 11. Input Number 26. Control Pin: OSD Select Number 10. Input Number 25. Control Pin: OSD Select Number 9. Input Number 24. Control Pin: OSD Select Number 8. Input Number 23. Control Pin: OSD Select Number 7. Input Number 22. Control Pin: OSD Select Number 6. Input Number 21. Control Pin: OSD Select Number 5. Input Number 20. Control Pin: OSD Select Number 4. Input Number 19. Control Pin: OSD Select Number 3. Input Number 18. Control Pin: OSD Select Number 2. Input Number 17. Control Pin: OSD Select Number 1. Input Number 16. Control Pin: OSD Select Number 0. No Connect. No Connect. No Connect. No Connect. No Connect. Analog Negative Power Supply. No Connect. No Connect. No Connect. Analog Positive Power Supply. No Connect. Analog Negative Power Supply. No Connect. Pin 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 Rev. 0 | Page 9 of 20 Mnemonic VPOS NC VNEG NC VPOS NC VNEG NC VPOS NC VNEG NC VPOS NC VNEG NC VPOS NC VNEG NC VPOS NC VNEG NC VPOS NC VNEG NC VPOS NC NC NC NC NC NC NC DGND EPAD (exposed pad) Description Analog Positive Power Supply. No Connect. Analog Negative Power Supply. No Connect. Analog Positive Power Supply. No Connect. Analog Negative Power Supply. No Connect. Analog Positive Power Supply. No Connect. Analog Negative Power Supply. No Connect. Analog Positive Power Supply. No Connect. Analog Negative Power Supply. No Connect. Analog Positive Power Supply. No Connect. Analog Negative Power Supply. No Connect. Analog Positive Power Supply. No Connect. Analog Negative Power Supply. No Connect. Analog Positive Power Supply. No Connect. Analog Negative Power Supply. No Connect. Analog Positive Power Supply. No Connect. No Connect. No Connect. No Connect. No Connect. No Connect. No Connect. Digital Negative Power Supply. Connect to analog ground. ADV3202/ADV3203 TRUTH TABLE AND LOGIC DIAGRAM Table 8. Operation Truth Table CS UPDATE X X 0 1 0 0 1 X 1 CLK X RESET DATA INPUT X DATA OUTPUT X 0 Datai 1 Datai-193 1 X X X 1 X X X 1 Operation/Comment Asynchronous reset. All outputs are disabled; the 193-bit shift register is reset to all 0s. The data on the serial DATA IN line is loaded into the serial register. The first bit clocked into the serial register appears at DATA OUT 193 clock cycles later. Switch matrix update. Data in the 193-bit shift register transfers into the parallel latches that control the switch array and synctip clamps. Chip is not selected. No change in logic. Datai: serial data. Rev. 0 | Page 10 of 20 ADV3202/ADV3203 TYPICAL PERFORMANCE CHARACTERISTICS VS = ±2.5 V (ADV3202), VS = ±3.3 V (ADV3203) at TA = 25°C, RL = 150 Ω. 1.2 2 INxx 0 0.8 –2 0.4 –4 VOUT (V) GAIN (dB) OSDxx –6 0 –0.4 –8 INxx 10 100 FREQUENCY (MHz) 1k –1.2 07526-005 1 Figure 5. ADV3202 Small Signal Frequency Response, 200 mV p-p 0 2 4 6 8 10 12 TIME (ns) 18 20 600 0 400 –2 RISING EDGE dV/dT (V/µs) 200 –4 –6 OSDxx –8 0 –200 FALLING EDGE INxx –400 –10 10 100 FREQUENCY (MHz) 1k –600 07526-006 1 0 2 4 Figure 6. ADV3202 Large Signal Frequency Response, 2 V p-p 6 8 10 12 TIME (ns) 14 16 18 20 07526-009 GAIN (dB) 16 Figure 8. ADV3202 Large Signal Pulse Response, 2 V p-p 2 –12 14 07526-008 –10 –12 OSDxx –0.8 Figure 9. ADV3202 Slew Rate 0.05 0.12 0.04 0.08 DIFFERENTIAL GAIN (%) 0.03 0 –0.04 OSDxx 0.01 0 –0.01 –0.02 0 2 4 6 8 10 12 TIME (ns) 14 16 18 Figure 7. ADV3202 Small Signal Pulse Response, 200 mV p-p 20 –0.05 –0.7 –0.5 –0.3 –0.1 0.1 0.3 INPUT DC OFFSET (V) 0.5 0.7 07526-010 –0.04 INxx –0.12 0.02 –0.03 –0.08 07526-007 VOUT (V) 0.04 Figure 10. ADV3202 Differential Gain, Carrier Frequency = 3.58 MHz, Subcarrier Amplitude = 300 mV p-p Rev. 0 | Page 11 of 20 0.010 0.12 0.005 0.08 0 0.04 VOUT (V) DIFFERENTIAL PHASE (Degrees) ADV3202/ADV3203 –0.005 0 –0.010 –0.04 –0.015 –0.08 OSDxx –0.5 –0.3 –0.1 0.1 0.3 INPUT DC OFFSET (V) 0.5 0.7 –0.12 07526-011 –0.020 –0.7 Figure 11. ADV3202 Differential Phase, Carrier Frequency = 3.58 MHz, Subcarrier Amplitude = 300 mV p-p 2 4 6 8 10 12 TIME (ns) 14 16 18 20 Figure 14. ADV3203 Small Signal Pulse Response, 200 mV p-p 8 1.2 6 0.8 4 0.4 INxx 2 VOUT (V) GAIN (dB) 0 07526-014 INxx OSDxx 0 0 –0.4 –2 10 100 FREQUENCY (MHz) 1k –1.2 Figure 12. ADV3203 Small Signal Frequency Response, 200 mV p-p INxx 0 2 4 6 8 10 12 TIME (ns) 14 16 18 20 07526-015 1 07526-012 –6 OSDxx –0.8 –4 Figure 15. ADV3203 Large Signal Pulse Response, 2 V p-p 600 8 6 OSDxx 400 INxx RISING EDGE 4 dV/dT (V/µs) 2 0 0 –200 –2 FALLING EDGE –6 1 10 100 FREQUENCY (MHz) 1k –600 Figure 13. ADV3203 Large Signal Frequency Response, 2 V p-p 0 2 4 6 8 10 12 TIME (ns) 14 Figure 16. ADV3203 Slew Rate Rev. 0 | Page 12 of 20 16 18 20 07526-016 –400 –4 07526-013 GAIN (dB) 200 ADV3202/ADV3203 0.10 DIFFERENTIAL GAIN (%) 0.05 0 –0.05 –0.15 –0.7 –0.5 –0.3 –0.1 0.1 0.3 INPUT DC OFFSET (V) 0.5 0.7 07526-017 –0.10 Figure 17. ADV3203 Differential Gain, Carrier Frequency = 3.58 MHz, Subcarrier Amplitude = 300 mV p-p 0.05 DIFFERENTIAL PHASE (Degrees) 0.04 0.03 0.02 0.01 0 –0.01 –0.02 –0.03 –0.05 –0.7 –0.5 –0.3 –0.1 0.1 0.3 INPUT DC OFFSET (V) 0.5 0.7 07526-018 –0.04 Figure 18. ADV3203 Differential Phase, Carrier Frequency = 3.58 MHz, Subcarrier Amplitude = 300 mV p-p Rev. 0 | Page 13 of 20 ADV3202/ADV3203 THEORY OF OPERATION The ADV3202/ADV3203 are single-ended crosspoint arrays with 16 outputs, each of which can be connected to any one of 32 inputs.The 32 switchable input stages are connected to each output buffer to form 32-to-1 multiplexers. There are 16 of these multiplexers, each with its inputs wired in parallel, for a total array of 512 stages forming a multicast-capable crosspoint switch. In addition to connecting to any of the nominal inputs (INxx), each output can also be connected to an associated OSD input through an additional 2-to-1 multiplexer at each output. This 2-to-1 multiplexer switches between the output of the 32to-1 multiplexer and the OSD input. FROM INPUT STAGES VPOS OSDS00 x1 OUT00 VNEG Each input to the ADV3202/ADV3203 is buffered by a receiver. The purpose of this receiver is to provide overvoltage protection for the input stages by limiting signal swing. In the ADV3202, the output of the receiver is limited to ±1.2 V about VREF, while in the ADV3203, the signal swing is limited to ±1.2 V about midsupply. This receiver is configured as a voltage feedback unity-gain amplifier. Excess loop gain bandwidth product reduces the effect of the closed-loop gain on the bandwidth of the device. In addition to a receiver, each input also has a sync-tip clamp for use in ac-coupled applications. This clamp is either enabled or disabled according to the 193rd serial data bit. When enabled, the clamp forces the lowest video voltage to the voltage on the VCLAMP pin. The VCLAMP pin is common for the entire chip and needs to be driven with a low impedance to avoid crosstalk. VPOS VPOS VPOS OSD00 07526-019 VCLAMP TO INPUT RECEIVER VNEG Figure 19. Conceptual Diagram of Single Output Channel, G = +1 (ADV3202) IN00 Decoding logic for each output selects one (or none) of the input stages to drive the output stage. The enabled input stage drives the output stage, which is configured as a unity-gain amplifier in the ADV3202 (see Figure 19). In the ADV3203, an internal resistive feedback network and reference buffer provide for a total output stage gain of +2 (see Figure 20). The input voltage to the reference buffer is the VREF pin. This voltage is common for the entire chip and needs to be driven with a low impedance to avoid crosstalk. VPOS FROM INPUT STAGES OSDS00 x1 OUT00 VNEG VPOS OSD00 VNEG VPOS 2kΩ 2kΩ VNEG 07526-020 VREF Figure 20. Conceptual Diagram of Single Output Channel, G = +2 (ADV3203) OFF-CHIP CAPACITOR 5µA 07526-021 VNEG Figure 21. Conceptual Diagram of Sync-Tip Clamp in an AC-Coupled Application The output stage of the ADV3202/ADV3203 is designed for low differential gain and phase error when driving composite video signals. It also provides slew current for fast pulse response when driving component video signals. The outputs of the ADV3202/ADV3203 can be disabled to minimize on-chip power dissipation. When disabled, a series of internal amplifiers drive internal nodes such that a wideband high impedance is presented at the disabled output, even while the output bus is under large signal swings. (In the ADV3203, there is 4 kΩ of resistance terminated to the VREF voltage by the reference buffer). This high impedance allows multiple ICs to be bussed together without additional buffering. Care must be taken to reduce output capacitance, which results in more overshoot and frequency domain peaking. In addition, when the outputs are disabled and driven externally, the voltage applied to them should not exceed the valid output swing range for the ADV3202/ADV3203 to keep these internal amplifiers in their linear range of operation. Applying excess voltage to the disabled outputs can cause damage to the ADV3202/ADV3203 and should be avoided (see the Absolute Maximum Ratings section for guidelines). Rev. 0 | Page 14 of 20 ADV3202/ADV3203 The internal connection of the ADV3202/ADV3203 is controlled by a TTL-compatible logic interface. Serial loading into a first rank of latches preprograms each output. A global update signal moves the programming data into the second rank of latches, simultaneously updating all outputs. A serial out pin allows devices to be daisy chained together for single pin programming of multiple ICs. A power-on reset pin is available to prevent bus conflicts by disabling all outputs. The ADV3202 can operate on a single +5 V supply, powering both the signal path (with the VPOS/VNEG supply pins) and the control logic interface (with the VDD/DGND supply pins). However, to easily interface to ground referenced video signals, split supply operation is possible with ±2.5 V. (The ADV3203 is intended to operate on ±3.3 V.) In the case of split supplies, a flexible logic interface allows the control logic supplies (VDD/DGND) to be run off +3.3 V/0 V to +5 V/0 V while the core remains on split supplies. Rev. 0 | Page 15 of 20 ADV3202/ADV3203 APPLICATIONS INFORMATION PROGRAMMING The ADV3202/ADV3203 are programmed serially through a 193-bit serial word that updates the matrix and the state of the sync-tip clamps each time the part is programmed. Serial Programming Description The serial programming mode uses the CLK, DATA IN, UPDATE, and CS device pins. The first step is to assert a low on CS to select the device for programming. The UPDATE signal should be high during the time that data is shifted into the serial port of the device. Although the data still shifts in when UPDATE is low, the transparent, asynchronous latches allow the shifting data to reach the matrix. This causes the matrix to try to update to every intermediate state as defined by the shifting data. The data at DATA IN is clocked in at every rising edge of CLK. A total of 193 bits must be shifted in to complete the programming. For each of the 16 outputs, there are five bits (D0 to D4) that determine the source of its input followed by one bit (D5) that determines the enabled state of the output. If D5 is low (output disabled), the five associated bits (D0 to D4) do not matter because no input is switched to that output. These comprise the first 96 bits of DATA IN. The remaining 96 bits of DATA IN should be set to zero. If a string of 96 zeros is not suffixed to the first 96 bits of DATA IN, a certain test mode is employed that can cause the device to draw up to 30% more current. The last bit, Bit 193, is used to enable or disable the sync-tip clamps. If Bit 193 is low, the sync-tip clamps are disabled; otherwise, they are enabled. The sync-tip clamp bit is shifted in first, followed by the most significant output address data (OUT15). The enable bit (D5) is shifted in first, followed by the input address (D4 to D0) entered sequentially with D4 first and D0 last. Each remaining output is programmed sequentially, until the least significant output address data is shifted in. At this point, UPDATE can be taken low, which causes the programming of the device according to the data that was just shifted in. The UPDATE latches are asynchronous and when UPDATE is low, they are transparent. If more than one ADV3202/ADV3203 device is to be serially programmed in a system, the DATA OUT signal from one device can be connected to the DATA IN of the next device to form a serial chain. All of the CLK and UPDATE pins should be connected in parallel and operated as described previously. The serial data is input to the DATA IN pin of the first device of the chain, and it ripples through to the last. Therefore, the data for the last device in the chain should come at the beginning of the programming sequence. The length of the programming sequence is 193 bits times the number of devices in the chain. Reset When powering up the ADV3200/ADV3201, it is often useful to have the outputs come up in the disabled state. The RESET pin, when taken low, causes all outputs to be disabled. After power-up, the UPDATE pin should be driven high prior to raising RESET. Because the data in the shift register is random after power-up, it should not be used to program the matrix, or the matrix may enter unknown states. To prevent this, do not apply a logic low signal to UPDATE initially after power-up. The shift register should first be loaded with data and UPDATE then taken low to program the device. The RESET pin has a 25 kΩ pull-up resistor to DVCC that can be used to create a simple power-on reset circuit. A capacitor from RESET to ground holds RESET low for some time while the rest of the device stabilizes. The low condition causes all the outputs to be disabled. The capacitor then charges through the pull-up resistor to the high state, thus allowing full programming capability of the device. The CS pin has a 25 kΩ pull-down resistor to ground. Rev. 0 | Page 16 of 20 ADV3202/ADV3203 OUTLINE DIMENSIONS 0.75 0.60 0.45 1.00 REF 26.20 26.00 SQ 25.80 1.60 MAX 24.10 24.00 SQ 23.90 21.50 REF 133 176 132 1 SEATING PLANE 133 1 PIN 1 7.80 REF EXPOSED PAD TOP VIEW (PINS DOWN) 1.45 1.40 1.35 176 132 0.20 0.15 0.09 7° 3.5° 0° BOTTOM VIEW (PINS UP) 44 89 45 88 88 VIEW A VIEW A 44 89 45 0.50 BSC LEAD PITCH ROTATED 90° CCW 0.27 0.22 0.17 COMPLIANT TO JEDEC STANDARDS MS-026-BGA-HD FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. Figure 22. 176-Lead Low Profile Quad Flat Package, Exposed Pad [LQFP_EP] (SW-176-1) Dimensions shown in millimeters ORDERING GUIDE Model ADV3202ASWZ 1 ADV3203ASWZ1 1 Temperature Range −40°C to +85°C −40°C to +85°C Package Description 176-Lead Low Profile Quad Flat Package, Exposed Pad [LQFP_EP] 176-Lead Low Profile Quad Flat Package, Exposed Pad [LQFP_EP] Z = RoHS Compliant Part. Rev. 0 | Page 17 of 20 Package Option SW-176-1 SW-176-1 081808-A 0.15 0.10 0.05 0.08 COPLANARITY ADV3202/ADV3203 NOTES Rev. 0 | Page 18 of 20 ADV3202/ADV3203 NOTES Rev. 0 | Page 19 of 20 ADV3202/ADV3203 NOTES ©2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07526-0-10/08(0) Rev. 0 | Page 20 of 20