AD AD8313ARM-REEL 0.1 ghz to 2.5 ghz 70 db logarithmic detector/controller Datasheet

0.1 GHz to 2.5 GHz 70 dB
Logarithmic Detector/Controller
AD8313
FEATURES
FUNCTIONAL BLOCK DIAGRAM
+
NINE DETECTOR CELLS
+
+
8dB
8dB
8dB
LP
8dB
INLO 3
8
VOUT
V→I
7
VSET
6
COMM
5
PWDN
INTERCEPT
CONTROL
AD8313
VPOS 4
SLOPE
CONTROL
BAND GAP
REFERENCE
GAIN
BIAS
01085-C-001
EIGHT 8dB 3.5GHz AMPLIFIER STAGES
Figure 1.
When used as a log amplifier, scaling is determined by a separate
feedback interface (a transconductance stage) that sets the slope
to approximately 18 mV/dB; used as a controller, this stage
accepts the setpoint input. The logarithmic intercept is positioned
to nearly −100 dBm, and the output runs from about 0.45 V dc
at −73 dBm input to 1.75 V dc at 0 dBm input. The scale and
intercept are supply- and temperature-stable.
The AD8313 is fabricated on Analog Devices’ advanced 25 GHz
silicon bipolar IC process and is available in an 8-lead MSOP
package. The operating temperature range is −40°C to +85°C.
An evaluation board is available.
2.0
5
1.8
4
1.6
3
1.4
2
1.2
1
1.0
0
0.8
–1
0.6
–2
0.4
–3
0.2
–4
0
–80
–70
–60
–50
–40
–30
INPUT AMPLITUDE (dBm)
–20
–10
0
OUTPUT ERROR (dB)
FREQUENCY = 1.9GHz
OUTPUT VOLTAGE (V DC)
The AD8313 uses a cascade of eight amplifier/limiter cells, each
having a nominal gain of 8 dB and a −3 dB bandwidth of
3.5 GHz. This produces a total midband gain of 64 dB. At each
amplifier output, a detector (rectifier) cell is used to convert the
RF signal to baseband form; a ninth detector cell is placed
directly at the input of the AD8313. The current-mode outputs
of these cells are summed to generate a piecewise linear approximation to the logarithmic function. They are converted to a low
impedance voltage-mode output by a transresistance stage, which
also acts as a low-pass filter.
I→V
CINT
INHI 2
RF transmitter power amplifier setpoint control and
level monitoring
Logarithmic amplifier for RSSI measurement cellular
base stations, radio link, radar
The AD8313 is a complete multistage demodulating logarithmic
amplifier that can accurately convert an RF signal at its differential input to an equivalent decibel-scaled value at its dc output.
The AD8313 maintains a high degree of log conformance for
signal frequencies from 0.1 GHz to 2.5 GHz and is useful over
the range of 10 MHz to 3.5 GHz. The nominal input dynamic
range is –65 dBm to 0 dBm (re: 50 Ω), and the sensitivity can be
increased by 6 dB or more with a narrow-band input impedance
matching network or a balun. Application is straightforward,
requiring only a single supply of 2.7 V to 5.5 V and the addition
of a suitable input and supply decoupling. Operating on a 3 V
supply, its 13.7 mA consumption (for TA = 25°C) is only 41 mW.
A power-down feature is provided; the input is taken high to
initiate a low current (20 µA) sleep mode, with a threshold at
half the supply voltage.
+
VPOS 1
APPLICATIONS
GENERAL DESCRIPTION
+
–5
01085-C-002
Wide bandwidth: 0.1 GHz to 2.5 GHz min
High dynamic range: 70 dB to ±3.0 dB
High accuracy: ±1.0 dB over 65 dB range (@ 1.9 GHz)
Fast response: 40 ns full-scale typical
Controller mode with error output
Scaling stable over supply and temperature
Wide supply range: 2.7 V to 5.5 V
Low power: 40 mW at 3 V
Power-down feature: 60 mW at 3 V
Complete and easy to use
Figure 2. Typical Logarithmic Response and Error vs. Input Amplitude
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703
© 2004 Analog Devices, Inc. All rights reserved.
AD8313
TABLE OF CONTENTS
Specifications..................................................................................... 3
Input Coupling ........................................................................... 16
Absolute Maximum Ratings............................................................ 6
Narrow-Band LC Matching Example at 100 MHz ................ 16
ESD Caution.................................................................................. 6
Adjusting the Log Slope............................................................. 18
Pin Configurations and Function Description............................. 7
Increasing Output Current........................................................ 19
Typical Performance Characteristics ............................................. 8
Effect of Waveform Type on Intercept..................................... 19
Circuit Description......................................................................... 11
Evaluation Board ............................................................................ 20
Interfaces.......................................................................................... 13
Schematic and Layout................................................................ 20
Power-Down Interface, PWDN................................................ 13
General Operation ..................................................................... 20
Signal Inputs, INHI, INLO ........................................................ 13
Using the AD8009 Operational Amplifier .............................. 20
Logarithmic/Error Output, VOUT .......................................... 13
Varying the Logarithmic Slope................................................. 20
Setpoint Interface, VSET............................................................ 14
Operating in Controller Mode ................................................. 20
Applications..................................................................................... 15
RF Burst Response ..................................................................... 20
Basic Connections for Log (RSSI) Mode................................. 15
Outline Dimensions ....................................................................... 24
Operating in Controller Mode ................................................. 15
Ordering Guide .......................................................................... 24
REVISION HISTORY
6/04—Data Sheet Changed from Rev. C to Rev. D
Updated Evaluation Board Section .............................................. 21
2/03—Data Sheet changed from Rev. B to Rev. C
TPCs and Figures Renumbered........................................Universal
Edits to SPECIFICATIONS............................................................. 2
Updated ESD CAUTION ................................................................ 4
Updated OUTLINE DIMENSIONS .............................................. 7
8/99—Data Sheet changed from Rev. A to Rev. B
5/99—Data Sheet changed from Rev. 0 to Rev. A
8/98—Revision 0: Initial Version
Rev. D | Page 2 of 24
AD8313
SPECIFICATIONS
TA = 25°C, VS = 5 V1, RL 10 kΩ, unless otherwise noted.
Table 1.
Parameter
SIGNAL INPUT INTERFACE
Specified Frequency Range
DC Common-Mode Voltage
Input Bias Currents
Input Impedance
LOG (RSSI) MODE
100 MHz5
±3 dB Dynamic Range6
Range Center
±1 dB Dynamic Range
Slope
Intercept
Min2
Conditions
Max2
Unit
2.5
VPOS – 0.75
10
900||1.1
GHz
V
µA
Ω||pF4
65
−31.5
56
19
−88
dB
dBm
dB
mV/dB
dBm
Typ
0.1
fRF < 100 MHz3
Sinusoidal, input termination configuration
shown in Figure 29
Nominal conditions
53.5
17
−96
21
−80
2.7 V ≤ VS ≤ 5.5 V, −40°C ≤ T ≤ +85°C
±3 dB Dynamic Range
Range Center
±1 dB Dynamic Range
Slope
Intercept
Temperature Sensitivity
900 MHz5
±3 dB Dynamic Range
Range Center
±1 dB Dynamic Range
Slope
Intercept
51
16
−99
PIN = −10 dBm
Nominal conditions
60
15.5
−105
64
−31
55
19
−89
−0.022
69
−32.5
62
18
−93
22
−75
20.5
−81
dB
dBm
dB
mV/dB
dBm
dB/°C
dB
dBm
dB
mV/dB
dBm
2.7 V ≤ VS ≤ 5.5 V, –40°C ≤ T ≤ +85°C
±3 dB Dynamic Range
Range Center
±1 dB Dynamic Range
Slope
Intercept
Temperature Sensitivity
1.9 GHz7
±3 dB Dynamic Range
Range Center
±1 dB Dynamic Range
Slope
Intercept
55.5
15
–110
PIN = –10 dBm
Nominal conditions
52
15
–115
68.5
–32.75
61
18
–95
–0.019
73
–36.5
62
17.5
–100
21
–80
20.5
–85
dB
dBm
dB
mV/dB
dBm
dB/°C
dB
dBm
dB
mV/dB
dBm
2.7 V ≤ VS ≤ 5.5 V, –40°C ≤ T ≤ +85°C
±3 dB Dynamic Range
Range Center
±1 dB Dynamic Range
Slope
Intercept
Temperature Sensitivity
50
14
–125
PIN = –10 dBm
Rev. D | Page 3 of 24
73
–36.5
60
17.5
–101
–0.019
21.5
–78
dB
dBm
dB
mV/dB
dBm
dB/°C
AD8313
Parameter
2.5 GHz7
±3 dB Dynamic Range
Range Center
±1 dB Dynamic Range
Slope
Intercept
Conditions
Nominal conditions
Min2
Typ
48
66
–34
46
20
–92
16
–111
Max2
Unit
25
–72
dB
dBm
dB
mV/dB
dBm
2.7 V ≤ VS ≤ 5.5 V, –40°C ≤ T ≤ +85°C
±3 dB Dynamic Range
Range Center
±1 dB Dynamic Range
Slope
Intercept
Temperature Sensitivity
3.5 GHz5
±3 dB Dynamic Range
±1 dB Dynamic Range
Slope
Intercept
CONTROL MODE
Controller Sensitivity
Low Frequency Gain
Open-Loop Corner Frequency
Open-Loop Slew Rate
VSET Delay Time
VOUT INTERFACE
Current Drive Capability
Source Current
Sink Current
Minimum Output Voltage
Maximum Output Voltage
Output Noise Spectral Density
Small Signal Response Time
Large Signal Response Time
VSET INTERFACE
Input Voltage Range
Input Impedance
POWER-DOWN INTERFACE
PWDN Threshold
Power-Up Response Time
PWDN Input Bias Current
47
14.5
–128
PIN =–10 dBm
Nominal conditions
f = 900 MHz
VSET to VOUT8
VSET to VOUT8
f = 900 MHz
Open-loop
Open-loop
PIN = –60 dBm, fSPOT = 100 Hz
PIN = –60 dBm, fSPOT = 10 MHz
PIN = –60 dBm to –57 dBm, 10% to 90%
PIN = No signal to 0 dBm; settled to 0.5 dB
Time delay following high to low transition
until device meets full specifications.
PWDN = 0 V
PWDN = VS
dB
dB
mV/dB
dBm
23
84
700
2.5
150
V/dB
dB
Hz
V/µs
ns
400
10
50
VPOS – 0.1
2.0
1.3
40
110
µA
mA
mV
V
µV/√Hz
µV/√Hz
ns
ns
VPOS
V
kΩ||pF
VPOS/2
1.8
V
µs
5
<1
µA
µA
13.7
Rev. D | Page 4 of 24
60
160
18||1
2.7
4.5 V ≤VS ≤ 5.5 V, –40°C ≤ T ≤ +85°C
2.7 V ≤VS ≤ 3.3 V, –40°C ≤ T ≤ +85°C
4.5 V ≤VS ≤ 5.5 V, –40°C ≤ T ≤ +85°C
2.7 V ≤VS ≤ 3.3 V, –40°C ≤ T ≤ +85°C
25
–56
dB
dBm
dB
mV/dB
dBm
dB/°C
43
35
24
–65
0
POWER SUPPLY
Operating Range
Powered-Up Current
Powered-Down Current
68
–34.5
46
20
–92
–0.040
50
20
5.5
15.5
18.5
18.5
150
50
V
mA
mA
mA
µA
µA
4
AD8313
1
Except where otherwise noted; performance at VS = 3 V is equivalent to 5 V operation.
Minimum and maximum specified limits on parameters that are guaranteed but not tested are 6 sigma values.
3
Input impedance shown over frequency range in Figure 26.
4
Double vertical bars (||) denote “in parallel with.”
5
Linear regression calculation for error curve taken from –40 dBm to –10 dBm for all parameters.
6
Dynamic range refers to range over which the linearity error remains within the stated bound.
7
Linear regression calculation for error curve taken from –60 dBm to –5 dBm for 3 dB dynamic range. All other regressions taken from –40 dBm to –10 dBm.
8
AC response shown in Figure 12.
2
Rev. D | Page 5 of 24
AD8313
ABSOLUTE MAXIMUM RATINGS
Table 2.
Supply Voltage VS
VOUT, VSET, PWDN
Input Power Differential (re: 50 Ω, 5.5 V)
Input Power Single-Ended (re: 50 Ω, 5.5 V)
Internal Power Dissipation
θJA
Maximum Junction Temperature
Operating Temperature Range
Storage Temperature Range
5.5 V
0 V, VPOS
25 dBm
19 dBm
200 mW
200°C/W
125°C
–40°C to +85°C
–65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. D | Page 6 of 24
AD8313
VPOS 1
INHI 2
INLO 3
VPOS 4
AD8313
TOP VIEW
(Not to Scale)
8
VOUT
7
VSET
6
COMM
5
PWDN
01085-C-003
PIN CONFIGURATIONS AND FUNCTION DESCRIPTION
Figure 3. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
1, 4
2
3
5
6
7
8
Mnemonic
VPOS
INHI
INLO
PWDN
COMM
VSET
VOUT
Description
Positive Supply Voltage (VPOS), 2.7 V to 5.5 V.
Noninverting Input. This input should be ac-coupled.
Inverting Input. This input should be ac-coupled.
Connect Pin to Ground for Normal Operating Mode. Connect this pin to the supply for power-down mode.
Device Common.
Setpoint Input for Operation in Controller Mode. To operate in RSSI mode, short VSET and VOUT.
Logarithmic/Error Output.
Rev. D | Page 7 of 24
AD8313
TYPICAL PERFORMANCE CHARACTERISTICS
2.0
2.0
5
1.8
1.8
4
1.6
1.6
3
1.4
1.4
2
100MHz
2.5GHz
1.0
–1
+85°C
0.6
0.6
900MHz
0.4
–2
0.4
–3
SLOPE AND INTERCEPT NORMALIZED AT +25°C
AND APPLIED TO –40°C AND +85°C
0.2
0
–70
–60
–50
–40
–30
–20
INPUT AMPLITUDE (dBm)
–10
0
10
01085-C-004
0.2
0
–70
Figure 4. VOUT vs. Input Amplitude
–60
–50
–40
–30
–20
–10
INPUT AMPLITUDE (dBm)
–4
0
4
2.0
5
1.8
4
1.6
3
900MHz
–40°C
1.4
0
VOUT (V)
100MHz
2
900MHz
–2
1.9GHz
–5
10
Figure 7. VOUT and Log Conformance vs. Input Amplitude at 900 MHz for
Multiple Temperatures
6
ERROR (dB)
0
+25°C
0.8
0.8
1
–40°C
2.5GHz
2
1.2
1
+25°C
1.0
0.8
2.5GHz
100MHz
0
–1
+85°C
0.6
ERROR (dB)
1.0
1.2
01-85-C-007
1.9GHz
VOUT (V)
VOUT (V)
1.2
ERROR (dB)
TA = 25°C, VS = 5 V, RL input match shown in Figure 29, unless otherwise noted.
–2
1.9GHz
0.4
–50
–40
–30
–20
INPUT AMPLITUDE (dBm)
0
–10
10
0
–70
Figure 5. Log Conformance vs. Input Amplitude
–50
–40
–30
–20
–10
INPUT AMPLITUDE (dBm)
0
–5
10
Figure 8. VOUT and Log Conformance vs. Input Amplitude at 1.9 GHz for
Multiple Temperatures
2.0
5
2.0
5
1.8
4
1.8
4
1.6
3
1.6
2
1.4
2
1
1.2
1
1.2
+25°C
1.0
0
+85°C
0.8
–1
VOUT (V)
–40°C
1.0
0.6
–2
0.4
–3
0.4
–60
–50
–40
–30
–20
INPUT AMPLITUDE (dBm)
–10
0
–5
10
Figure 6. VOUT and Log Conformance vs. Input Amplitude at 100 MHz for
Multiple Temperatures
0
–70
–1
SLOPE AND INTERCEPT
NORMALIZED AT +25°C AND
APPLIED TO –40°C AND +85°C
–2
–3
+85°C
0.2
–4
01085-C-006
0
–70
SLOPE AND INTERCEPT NORMALIZED AT +25°C
AND APPLIED TO –40°C AND +85°C
0
+25°C
0.8
0.6
0.2
3
–40°C
ERROR (dB)
1.4
VOUT (V)
–60
ERROR (dB)
–60
–4
–60
–50
–4
–40
–30
–20
–10
INPUT AMPLITUDE (dBm)
0
–5
10
01085-C-009
–6
–70
01085-C-005
0.2
–3
SLOPE AND INTERCEPT NORMALIZED AT +25°C
AND APPLIED TO –40°C AND +85°C
01085-C-008
–4
Figure 9. VOUT and Log Conformance vs. Input Amplitude at 2.5 GHz for
Multiple Temperatures
Rev. D | Page 8 of 24
AD8313
22
–70
21
–80
INTERCEPT (dBm)
SLOPE (mV/dB)
+85°C
20
+25°C
19
–40°C
18
+85°C
–90
+25°C
–100
17
500
1000
1500
FREQUENCY (MHz)
2000
2500
–110
Figure 10. VOUT Slope vs. Frequency for Multiple Temperatures
0
1000
1500
FREQUENCY (MHz)
500
2000
2500
01085-C-013
0
01085-C-010
16
–40°C
Figure 13. VOUT Intercept vs. Frequency for Multiple Temperatures
–70
24
23
–75
SPECIFIED OPERATING RANGE
SPECIFIED OPERATING RANGE
22
–80
INTERCEPT (dBm)
SLOPE (mV/dB)
21
2.5GHz
20
100MHz
19
900MHz
18
1.9GHz
17
–85
100MHz
–90
2.5GHz
–95
900MHz
1.9GHz
–100
16
3.0
3.5
4.0
4.5
5.0
SUPPLY VOLTAGE (V)
5.5
6.0
01085-C-011
14
2.5
–110
2.5
Figure 11. VOUT Slope vs. Supply Voltage
3.0
3.5
4.0
4.5
5.0
SUPPLY VOLTAGE (V)
5.5
6.0
01085-C-014
–105
15
Figure 14. VOUT Intercept vs. Supply Voltage
10
REF LEVEL = 92dB
2GHz RF INPUT
SCALE: 10dB/DIV
VSET TO VOUT GAIN (dB)
RF INPUT
–70dBm
µV/ Hz
–60dBm
–55dBm
1
–50dBm
–45dBm
–40dBm
1k
10k
FREQUENCY (Hz)
100k
1M
0.1
100
1k
10k
100k
FREQUENCY (Hz)
1M
Figure 15. VOUT Noise Spectral Density
Figure 12. AC Response from VSET to VOUT
Rev. D | Page 9 of 24
10M
01085-C-015
100
01085-C-012
–35dBm
–30dBm
AD8313
100.00
CH. 1 AND CH. 2: 200mV/DIV
VS = +5.5V
13.7mA
CH. 1
10.00
VS = +2.7V
CH. 2
PULSED RF
100MHz, –45dBm
CH. 1 GND
1.00
VPOS = +3V
VPOS = +5V
CH. 2 GND
0.10
40µA
0.01
0
1
2
3
PWDN VOLTAGE (V)
4
5
HORIZONTAL: 50ns/DIV
01085-C-016
20µA
Figure 18. Response Time, No Signal to –45 dBm
Figure 16. Typical Supply Current vs. PWDN Voltage
CH. 1 AND CH. 2: 1V/DIV
01085-C-019
SUPPLY CURRENT (mA)
AVERAGE: 50 SAMPLES
CH. 1 & CH. 2: 500mV/DIV
CH. 3: 5V/DIV
AVERAGE: 50 SAMPLES
VS = +5.5V
VOUT @
VS = +5.5V
CH. 1
CH. 1 GND
VS = +2.7V
CH. 2
CH. 1 GND
VOUT @
VS = +2.7V
CH. 2 GND
PULSED RF
100MHz, 0dBm
CH. 2 GND
CH. 3 GND
HORIZONTAL: 1µs/DIV
HORIZONTAL: 50ns/DIV
01085-C-020
01085-C-017
PWDN
Figure 19. Response Time, No Signal to 0 dBm
Figure 17. PWDN Response Time
________________________________________________________________________________________________________________________________
1 VPOS
0.1µF
0.01µF
2 INHI
0.01µF
TEK P6205
FET PROBE
HP8648B
SIGNAL
GENERATOR
PULSE
MODULATION
MODE
OUT
TEK
TDS784C
SCOPE TRIG
COMM 6
4 VPOS PWDN 5
0.1µF
PULSE MODE IN
OUT
HP8112A
PULSE
GENERATOR
TRIG
OUT
RF OUT
0603 SIZE SURFACE
MOUNT COMPONENTS ON
A LOW LEAKAGE PC BOARD
10Ω
EXT TRIG
10MHz REF OUTPUT
–6dB
RF
SPLITTER
VSET 7
54.9Ω
3 INLO
+VS
VOUT 8
AD8313
HP8112A
PULSE
GENERATOR
–6dB
10Ω
+VS
01085-C-018
10Ω
+VS
EXT TRIG
0.01µF
0.01µF
Figure 20. Test Setup for PWDN Response Time
+VS
1
VPOS
2
INHI
VSET 7
3
INLO
COMM 6
4
VPOS PWDN 5
0.1µF
VOUT 8
AD8313
54.9Ω
TEK P6205
FET PROBE
TEK
TDS784C
SCOPE TRIG
0603 SIZE SURFACE
MOUNT COMPONENTS ON
A LOW LEAKAGE PC BOARD
10Ω
0.1µF
Figure 21. Test Setup for RSSI Mode Pulse Response
Rev. D | Page 10 of 24
01085-C-021
HP8648B
10MHz REF OUTPUT
SIGNAL
GENERATOR
PIN = 0dBm
RF OUT
AD8313
CIRCUIT DESCRIPTION
separated by 8 dB, the overall dynamic range is about 72 dB
(Figure 23). The upper end of this range is determined by the
capacity of the first detector cell, and occurs at approximately
0 dBm. The practical dynamic range is over 70 dB to the ±3 dB
error points. However, some erosion of this range can occur at
temperature and frequency extremes. Useful operation to over
3 GHz is possible, and the AD8313 remains serviceable at
10 MHz, needing only a small amount of additional ripple
filtering.
The AD8313 is an 8-stage logarithmic amplifier, specifically
designed for use in RF measurement and power amplifier
control applications at frequencies up to 2.5 GHz. A block
diagram is shown in Figure 22. For a detailed description of
log amp theory and design principles, refer to the AD8307
data sheet.
+
NINE DETECTOR CELLS
+
+
+
+
I→V
8
VOUT
VPOS 1
2.0
CINT
INHI 2
8dB
8dB
8dB
LP
8dB
INLO 3
5
SLOPE = 18mV/dB
1.8
V→I
7
4
VSET
1.6
3
1.4
2
1.2
1
1.0
0
0.8
–1
0.6
–2
BAND GAP
REFERENCE
GAIN
BIAS
5
PWDN
Figure 22. Block Diagram
–3
0.4
A fully differential design is used. Inputs INHI and INLO
(Pins 2 and 3) are internally biased to approximately 0.75 V
below the supply voltage, and present a low frequency impedance
of nominally 900 Ω in parallel with 1.1 pF. The noise spectral
density referred to the input is 0.6 nV/√Hz, equivalent to a
voltage of 35 V rms in a 3.5 GHz bandwidth, or a noise power of
−76 dBm re: 50 Ω. This sets the lower limit to the dynamic range;
the Applications section shows how to increase the sensitivity
by using a matching network or input transformer. However, the
low end accuracy of the AD8313 is enhanced by specially shaping
the demodulation transfer characteristic to partially compensate
for errors due to internal noise.
Each of the eight cascaded stages has a nominal voltage gain of
8 dB and a bandwidth of 3.5 GHz. Each stage is supported by
precision biasing cells that determine this gain and stabilize it
against supply and temperature variations. Since these stages are
direct-coupled and the dc gain is high, an offset compensation
loop is included. The first four stages and the biasing system are
powered from Pin 4, while the later stages and the output interfaces are powered from Pin 1. The biasing is controlled by a logic
interface PWDN (Pin 5); this is grounded for normal operation,
but may be taken high (to VS) to disable the chip. The threshold
is at VPOS/2 and the biasing functions are enabled and disabled
within 1.8 µs.
Each amplifier stage has a detector cell associated with its
output. These nonlinear cells perform an absolute value (fullwave rectification) function on the differential voltages along
this backbone in a transconductance fashion; their outputs are
in current-mode form and are thus easily summed. A ninth
detector cell is added at the input of the AD8313. Since the
midrange response of each of these nine detector stages is
INTERCEPT = –100dBm
–4
0.2
0
–90
–80
–70
–60
–50
–40
–30
INPUT AMPLITUDE (dBm)
–20
–10
0
–5
01085-c-023
SLOPE
CONTROL
COMM
VOUT (V)
VPOS 4
6
01085-C-001
INTERCEPT
CONTROL
AD8313
ERROR (dB)
EIGHT 8dB 3.5GHz AMPLIFIER STAGES
Figure 23. Typical RSSI Response and Error vs. Input Power at 1.9 GHz
The fluctuating current output generated by the detector cells,
with a fundamental component at twice the signal frequency, is
filtered first by a low-pass section inside each cell, and then by
the output stage. The output stage converts these currents to a
voltage, VOUT, at VOUT (Pin 8), which can swing rail-to-rail. The
filter exhibits a 2-pole response with a corner at approximately
12 MHz and full-scale rise time (10% to 90%) of 40 ns. The
residual output ripple at an input frequency of 100 MHz has an
amplitude of under 1 mV. The output can drive a small resistive
load; it can source currents of up to 400 µA, and sink up to
10 mA. The output is stable with any capacitive load, though
settling time could be impaired. The low frequency incremental
output impedance is approximately 0.2 Ω.
In addition to its use as an RF power measurement device (that
is, as a logarithmic amplifier), the AD8313 may also be used in
controller applications by breaking the feedback path from
VOUT to VSET (Pin 7), which determines the slope of the
output (nominally 18 mV/dB). This pin becomes the setpoint
input in controller modes. In this mode, the voltage VOUT
remains close to ground (typically under 50 mV) until the
decibel equivalent of the voltage VSET is reached at the input,
when VOUT makes a rapid transition to a voltage close to VPOS
(see the Operating in Controller Mode section). The logarithmic
intercept is nominally positioned at −100 dBm (re: 50 Ω); this is
effective in both the log amp mode and the controller mode.
Rev. D | Page 11 of 24
AD8313
With Pins 7 and 8 connected (log amp mode), the output can be
stated as
With Pins 7 and 8 disconnected (controller mode), the output
can be stated as
VOUT = VSLOPE ( PIN + 100 dBm)
where PIN is the input power stated in dBm when the source is
directly terminated in 50 Ω. However, the input impedance of
the AD8313 is much higher than 50 Ω, and the sensitivity of this
device may be increased by about 12 dB by using some type of
matching network (see below), which adds a voltage gain and
lowers the intercept by the same amount. Dependence on the reference impedance can be avoided by restating the expression as
when V SLOPE log ( PIN / 100) > V SET
VOUT → 0
when V SLOPE log ( PIN / 100) < V SET
when the input is stated in terms of the power of a sinusoidal
signal across a net termination impedance of 50 Ω. The transition
zone between high and low states is very narrow since the output
stage behaves essentially as a fast integrator. The above equations
can be restated as
VOUT = 20 × VSLOPE × log × (VIN / 2.2 µV)
where VIN is the rms value of a sinusoidal input appearing
across Pins 2 and 3; here, 2.2 µV corresponds to the intercept,
expressed in voltage terms. For detailed information on the
effect of signal waveform and metrics on the intercept
positioning for a log amp, refer to the AD8307 data sheet.
VOUT → V S
VOUT → VS
when VSLOPE log (VIN / 2.2 µV) > VSET
VOUT → 0
when VSLOPE log (VIN / 2.2 µV) < VSET
Another use of the separate VOUT and VSET pins is in raising
the load-driving current capability by including an external
NPN emitter follower. More complete information about usage
in these modes is provided in the Applications section.
Rev. D | Page 12 of 24
AD8313
INTERFACES
For high frequency use, Figure 26 shows the input impedance
plotted on a Smith chart. This measured result of a typical
device includes a 191 mil 50 Ω trace and a 680 pF capacitor to
ground from the INLO pin.
POWER-DOWN INTERFACE, PWDN
Frequency
100MHz
900MHz
1.9GHz
2.5GHz
The power-down threshold is accurately centered at the
midpoint of the supply as shown in Figure 24. If Pin 5 is left
unconnected or tied to the supply voltage (recommended), the
bias enable current is shut off, and the current drawn from the
supply is predominately through a nominal 300 kΩ chain
(20 µA at 3 V). When grounded, the bias system is turned on.
The threshold level is accurately at VPOS/2. When operating in
the device ON state, the input bias current at the PWDN pin is
approximately 5 µA for VPOS = 3 V.
j
j
j
j
j
X
400
135
65
43
100MHz
AD8313 MEASURED
900MHz
2.5GHz
1.9GHz
900Ω
1.1pF
Figure 26. Typical Input Impedance
150kΩ
150kΩ
COMM 6
01085-C-024
TO BIAS
ENABLE
75kΩ
PWDN 5
Figure 24. Power-Down Threshold Circuitry
SIGNAL INPUTS, INHI, INLO
The simplest low frequency ac model for this interface consists
of just a 900 Ω resistance, RIN, in shunt with a 1.1 pF input capacitance, CIN, connected across INHI and INLO. Figure 25 shows
these distributed in the context of a more complete schematic.
The input bias voltage shown is for the enabled chip; when
disabled, it rises by a few hundred millivolts. If the input is
coupled via capacitors, this change may cause a low level signal
transient to be introduced, having a time constant formed by
these capacitors and RIN. For this reason, large coupling capacitors
should be well matched. This is not necessary when using the
small capacitors found in many impedance transforming
networks used at high frequencies.
TO STAGES
1 TO 4
VPOS 1
~0.75V
0.5pF
2.5kΩ
125Ω
2.5kΩ
125Ω
1.25kΩ
INHI 2
TO 2ND
STAGE
INLO 3
1.25kΩ
GAIN BIAS
BIAS
FROM
SETPOINT
SUMMED
DETECTOR
OUTPUTS
COMM
CINT
8
VOUT
LP
LM
10mA
MAX
CL
COMM
Figure 27. Output Interface Circuitry
Thus, for midscale RF input of about 3 mV, which is some 40 dB
above the minimum detector output, this current is 160 µA, and
the output changes by 8 V/µs. When VOUT is connected to VSET,
the rise and fall times are approximately 40 ns (for RL ≥ 10 kΩ ).
1.24V
~1.4mA
ISOURCE
400µA
gm STAGE
6
01085-C-025
250Ω
1 VPOS
The nominal slew rate is 2.5 V/µs. The HF compensation technique results in stable operation with a large capacitive load, CL,
though the positive-going slew rate is then limited by ISOURCE/CL
to 1 V/µs for CL = 400 pF.
0.7pF
(1ST DETECTOR)
The rail-to-rail output interface is shown in Figure 27. VOUT can
run from within about 50 mV of ground, to within about 100 mV
of the supply voltage, and is short-circuit safe to either supply.
However, the sourcing load current, ISOURCE, is limited to that
which is provided by the PNP transistor, typically 400 µA.
Larger load currents can be provided by adding an external NPN
transistor (see the Applications section). The dc open-loop gain
of this amplifier is high, and it may be regarded as an integrator
having a capacitance of 2 pF (CINT) driven by the current-mode
signal generated by the summed outputs of the nine detector
stages, which is scaled approximately 4.0 µA/dB.
01085-C-027
50kΩ
VPOS 4
+
–
–
–
–
LOGARITHMIC/ERROR OUTPUT, VOUT
VPOS 4
0.5pF
R
650
55
22
23
01085-C-026
This section describes the signal and control interfaces and
their behavior. On-chip resistances and capacitances exhibit
variations of up to ±20%. These resistances are sometimes
temperature-dependent, and the capacitances may be voltagedependent.
Figure 25. Input Interface Simplified Schematic
Rev. D | Page 13 of 24
AD8313
SETPOINT INTERFACE, VSET
VPOS 1
25µA
FDBK
TO O/P
STAGE
25µA
R1
12kΩ
LP
VSET 8
R2
6kΩ
R3
1.5kΩ
COMM 6
Figure 28. Setpoint Interface Circuitry
Rev. D | Page 14 of 24
01085-C-028
The setpoint interface is shown in Figure 28. The voltage, VSET, is
divided by a factor of 3 in a resistive attenuator of 18 kΩ total
resistance. The signal is converted to a current by the action of
the op amp and the resistor R3 (1.5 kΩ), which balances the
current generated by the summed output of the nine detector
cells at the input to the previous cell. The logarithmic slope is
nominally 3 µs × 4.0 µA/dB × 1.5 kΩ = 18 mV/dB.
AD8313
APPLICATIONS
BASIC CONNECTIONS FOR LOG (RSSI) MODE
OPERATING IN CONTROLLER MODE
Figure 29 shows the AD8313 connected in its basic measurement
mode. A power supply between 2.7 V and 5.5 V is required. The
power supply to each of the VPOS pins should be decoupled
with a 0.1 µF surface-mount ceramic capacitor and a 10 Ω series
resistor.
Figure 30 shows the basic connections for operation in controller
mode. The link between VOUT and VSET is broken and a setpoint is applied to VSET. Any difference between VSET and the
equivalent input power to the AD8313 drives VOUT either to the
supply rail or close to ground. If VSET is greater than the equivalent
input power, VOUT is driven toward ground, and vice versa.
As stated in the Absolute Maximum Ratings table, an externally
applied overvoltage on the VOUT pin, which is outside the
range 0 V to VPOS, is sufficient to cause permanent damage to
the device. If overvoltages are expected on the VOUT pin, a
series resistor, RPROT, should be included as shown. A 500 Ω
resistor is sufficient to protect against overvoltage up to ±5 V;
1000 Ω should be used if an overvoltage of up to ±15 V is
expected. Since the output stage is meant to drive loads of no
more than 400 μA, this resistor does not impact device performance for higher impedance drive applications (higher output
current applications are discussed in the Increasing Output
Current section).
R1
10Ω
680pF
VPOS VOUT 8
2
INHI
VSET 7
3
INLO
COMM 6
4
VPOS PWDN 5
AD8313
1
VPOS VOUT 8
2
INHI
VSET 7
3
INLO
COMM 6
4
VPOS PWDN 5
0.1µF
RPROT
AD8313
R3
10Ω
0.1µF
Figure 30. Basic Connections for Operation in the Controller Mode
This mode of operation is useful in applications where the output
power of an RF power amplifier (PA) is to be controlled by an
analog AGC loop (Figure 31). In this mode, a setpoint voltage,
proportional in dB to the desired output power, is applied to the
VSET pin. A sample of the output power from the PA, via a
directional coupler or other means, is fed to the input of the
AD8313.
ENVELOPE OF
TRANSMITTED
SIGNAL
POWER
AMPLIFIER
RF IN
DIRECTIONAL
COUPLER
AD8313
VOUT
RFIN
VSET
SETPOINT
CONTROL DAC
RPROT
RL = 1MΩ
Figure 31. Setpoint Controller Operation
53.6Ω
680pF
+VS
1
0.1µF
R2
10Ω
0.1µF
Figure 29. Basic Connections for Log (RSSI) Mode
01085-C-029
+VS
+VS
R1
10Ω
01085-C-031
VSET is connected to VOUT to establish a feedback path that
controls the overall scaling of the logarithmic amplifier. The
load resistance, RL, should not be lower than 5 kΩ so that the
full-scale output of 1.75 V can be generated with the limited
available current of 400 µA max.
+VS
01085-C-030
The PWDN pin is shown as grounded. The AD8313 may be
disabled by a logic high at this pin. When disabled, the chip
current is reduced to about 20 µA from its normal value of
13.7 mA. The logic threshold is at VPOS/2, and the enable
function occurs in about 1.8 µs. However, that additional
settling time is generally needed at low input levels. While the
input in this case is terminated with a simple 50 Ω broadband
resistive match, there are many ways in which the input termination can be accomplished. These are discussed in the Input
Coupling section.
VOUT is applied to the gain control terminal of the power
amplifier. The gain control transfer function of the power
amplifier should be an inverse relationship, that is, increasing
voltage decreases gain.
A positive input step on VSET (indicating a demand for increased
power from the PA) drives VOUT toward ground. This should be
arranged to increase the gain of the PA. The loop settles when
VOUT settles to a voltage that sets the input power to the AD8313
to the dB equivalent of VSET.
Rev. D | Page 15 of 24
AD8313
INPUT COUPLING
3
BALANCED
The signal can be coupled to the AD8313 in a variety of ways.
In all cases, there must not be a dc path from the input pins to
ground. Some of the possibilities include dual-input coupling
capacitors, a flux-linked transformer, a printed circuit balun,
direct drive from a directional coupler, or a narrow-band
impedance matching network.
2
MATCHED
TERMINATED
DR = 66dB
0
BALANCED
DR = 71dB
–1
Figure 32 shows a simple broadband resistive match. A
termination resistor of 53.6 Ω combines with the internal input
impedance of the AD8313 to give an overall resistive input
impedance of approximately 50 Ω. It is preferable to place the
termination resistor directly across the input pins, INHI to
INLO, where it lowers the possible deleterious effects of dc
offset voltages on the low end of the dynamic range. At low
frequencies, this may not be quite as beneficial, since it requires
larger coupling capacitors. The two 680 pF input coupling
capacitors set the high-pass corner frequency of the network at
9.4 MHz.
MATCHED
DR = 69dB
–2
–3
–90
–80
–70
–60 –50 –40 –30 –20
INPUT AMPLITUDE (dBm)
–10
0
10
01085-C-033
ERROR (dB)
1
Figure 33. Comparison of Terminated, Matched, and Balanced
Input Drive at 900 MHz
3
TERMINATED
DR = 75dB
2
AD8313
MATCHED
C2
680pF
RMATCH
53.6Ω
CIN
ERROR (dB)
1
RIN
The high-pass corner frequency can be set higher according to
the equation
BALANCED
MATCHED
DR = 73dB
BALANCED
DR = 75dB
–2
–3
–90
1
=
2 × π × C × 50
–80
–70
–60 –50 –40 –30 –20
INPUT AMPLITUDE (dBm)
–10
0
10
Figure 34. Comparison of Terminated, Matched, and Balanced
Input Drive at 1.9 GHz
where:
NARROW-BAND LC MATCHING EXAMPLE
AT 100 MHz
C1 × C2
C=
C1 × C2
In high frequency applications, the use of a transformer, balun,
or matching network is advantageous. The impedance matching
characteristics of these networks provide what is essentially a
gain stage before the AD8313 that increases the device sensitivity.
This gain effect is explored in the following matching example.
Figure 33 and Figure 34 show device performance under these
three input conditions at 900 MHz and 1.9 GHz.
While the 900 MHz case clearly shows the effect of input
matching by realigning the intercept as expected, little
improvement is seen at 1.9 GHz. Clearly, if no improvement
in sensitivity is required, a simple 50 Ω termination may be
the best choice for a given design based on ease of use and
cost of components.
0
–1
Figure 32. A Simple Broadband Resistive Input Termination
f 3 dB
TERMINATED
01085-C-034
C1
680pF
01085-C-032
50Ω SOURCE
50Ω
While numerous software programs provide an easy way to
calculate the values of matching components, a clear understanding of the calculations involved is valuable. A low frequency
(100 MHz) value has been used for this example because of the
deleterious board effects at higher frequencies. RF layout
simulation software is useful when board design at higher
frequencies is required.
A narrow-band LC match can be implemented either as a
series-inductance/shunt-capacitance or as a series-capacitance/
shunt-inductance. However, the concurrent requirement that
the AD8313 inputs, INHI and INLO, be ac-coupled, makes a
series-capacitance/shunt-inductance type match more
appropriate (Figure 35).
Rev. D | Page 16 of 24
AD8313
50Ω SOURCE
50Ω
Solving for L1 gives
AD8313
C1
LMATCH
CIN
L1 =
RIN
01085-C-035
C2
Typically, the AD8313 needs to be matched to 50 Ω. The input
impedance of the AD8313 at 100 MHz can be read from the
Smith chart (Figure 26) and corresponds to a resistive input
impedance of 900 Ω in parallel with a capacitance of 1.1 pF.
To make the matching process simpler, the AD8313 input capacitance, CIN, can be temporarily removed from the calculation
by adding a virtual shunt inductor (L2), which resonates away
CIN (Figure 36). This inductor is factored back into the calculation
later. This allows the main calculation to be based on a simple
resistive-to-resistive match, that is, 50 Ω to 900 Ω.
The resonant frequency is defined by the equation
1
L2 × C IN
1
ω2 C IN
= 2.3 µH
50Ω SOURCE
50Ω
AD8313
C1
L1
L2
(C1 × C2)
(C1 + C2)
(C1 × C2)
LMATCH =
(C1 + C2)
CMATCH =
CIN
L MATCH =
L1 × L2
= 294 nH
L1 + L2
C1 and C2 can be chosen in a number of ways. First, C2 can be
set to a large value, for example, 1000 pF, so that it appears as an
RF short. C1 would then be set equal to the calculated value of
CMATCH. Alternatively, C1 and C2 can each be set to twice CMATCH
so that the total series capacitance is equal to CMATCH. By making
C1 and C2 slightly unequal (that is, select C2 to be about 10%
less than C1) but keeping their series value the same, the amplitude of the signals on INHI and INLO can be equalized so that
the AD8313 is driven in a more balanced manner. Any of the
options detailed above can be used provided that the combined
series value of C1 and C2, that is, C1 × C2/(C1 + C2) is equal to
CMATCH.
Assuming a lossless matching network and noting conservation
of power, the impedance transformation from RS to RIN (50 Ω to
900 Ω) has an associated voltage gain given by
RIN
01085-C-036
C2
= 337.6 nH
In all cases, the values of CMATCH and LMATCH must be chosen
from standard values. At this point, these values need now be
installed on the board and measured for performance at
100 MHz. Because of board and layout parasitics, the component
values from the preceding example had to be tuned to the final
values of CMATCH = 8.9 pF and LMATCH = 270 nH as shown in
Table 4.
therefore,
L2 =
2πf 0
Because L1 and L2 are parallel, they can be combined to give the
final value for LMATCH, that is,
Figure 35. Narrow-Band Reactive Match
ω=
RS RIN
TEMPORARY
INDUCTANCE
Gain dB = 20 × log
RIN
= 12.6 dB
RS
Figure 36. Input Matching Example
With CIN and L2 temporarily out of the picture, the focus is now
on matching a 50 Ω source resistance to a (purely resistive) load
of 900 Ω and calculating values for CMATCH and L1. When
RS RIN =
L1
C MATCH
the input looks purely resistive at a frequency given by
f0 =
1
2π L1 × C MATCH
= 100 MHz
Solving for CMATCH gives
C MATCH =
1
RS R IN
×
1
= 7.5 pF
2πf 0
Because the AD8313 input responds to voltage and not to true
power, the voltage gain of the matching network increases the
effective input low-end power sensitivity by this amount. Thus,
in this case, the dynamic range is shifted downward, that is, the
12.6 dB voltage gain shifts the 0 dBm to −65 dBm input range
downward to −12.6 dBm to −77.6 dBm. However, because of
network losses, this gain is not be fully realized in practice.
Refer to Figure 33 and Figure 34 for an example of practical
attainable voltage gains.
Table 4 shows recommended values for the inductor and capacitors in Figure 35 for some selected RF frequencies in addition
to the associated theoretical voltage gain. These values for a
reactive match are optimal for the board layout detailed as
Figure 45.
Rev. D | Page 17 of 24
AD8313
Table 4. Recommended Values for C1, C2, and
LMATCH in Figure 35
CMATCH
(pF)
8.9
C1
(pF)
22
900
1.5
1900
1.5
2500
Large
3
1.5
3
1.5
390
C2
(pF)
15
1000
3
1000
3
1000
390
LMATCH
(nH)
270
270
8.2
8.2
2.2
2.2
2.2
9.0
6.2
18–30mV/dB
AD8313
2
INHI
VSET 7
3
INLO
COMM 6
4
VPOS PWDN 5
R2
10kΩ
0.1µF
Figure 38. Adjusting the Log Slope
As stated, the unadjusted log slope varies with frequency from
17 mV/dB to 20 mV/dB, as shown in Figure 10. By placing a
resistor between VOUT and VSET, the slope can be adjusted to
a convenient 20 mV/dB as shown in Figure 39.
Table 5 shows the recommended values for this resistor, REXT.
Also shown are values for REXT, which increase the slope to
approximately 50 mV/dB. The corresponding voltage swings
for a −65 dBm to 0 dBm input range are also shown in Table 6.
3.2
Figure 37 shows the voltage response of the 100 MHz matching
network. Note the high attenuation at lower frequencies typical
of a high-pass network.
+VS
R1
10Ω
1
0.1µF
15
+VS
10
VOLTAGE GAIN (dB)
VPOS VOUT 8
R3
10Ω
+VS
Voltage
Gain(dB)
12.6
1
0.1µF
VPOS VOUT 8
AD8313
20mV/dB
REXT
2
INHI
VSET 7
3
INLO
COMM 6
4
VPOS PWDN 5
R3
10Ω
0.1µF
01085-C-039
Freq.
(MHz)
100
R1
10Ω
+VS
01085-C-038
As previously discussed, a modification of the board layout
produces networks that may not perform as specified. At 2.5 GHz,
a shunt inductor is sufficient to achieve proper matching. Consequently, C1 and C2 are set sufficiently high that they appear as
RF shorts.
Figure 39. Adjusting the Log Slope to a Fixed Value
5
Table 5. Values for REXT in Figure 39
–5
50
01085-C-037
0
100
FREQUENCY (MHz)
200
Figure 37. Voltage Response of 100 MHz Narrow-Band Matching Network
ADJUSTING THE LOG SLOPE
Figure 38 shows how the log slope can be adjusted to an exact
value. The idea is simple: the output at the VOUT pin is attenuated by the variable resistor R2 working against the internal 18 kΩ
of input resistance at the VSET pin. When R2 is 0, the attenuation it introduces is 0, and thus the slope is the basic 18 mV/dB.
Note that this value varies with frequency, (Figure 10). When R2
is set to its maximum value of 10 kΩ, the attenuation from
VOUT to VSET is the ratio 18/(18 + 10), and the slope is raised
to (28/18) × 18 mV, or 28 mV/dB. At about the midpoint, the
nominal scale is 23 mV/dB. Thus, a 70 dB input range changes
the output by 70 × 23 mV, or 1.6 V.
Frequency
MHz
100
900
1900
2500
100
900
1900
2500
REXT
kV
0.953
2.00
2.55
0
29.4
32.4
33.2
26.7
Slope
mV/dB
20
20
20
20
50
50.4
49.8
49.7
VOUT Swing for Pin
−65 dBm to 0 dBm – V
0.44 to 1.74
0.58 to 1.88
0.70 to 2.00
0.54 to 1.84
1.10 to 4.35
1.46 to 4.74
1.74 to 4.98
1.34 to 4.57
The value for REXT is calculated by
REXT =
(New Slope − Original Slope) × 18 kΩ
Original Slope
The value for the Original Slope, at a particular frequency, can
be read from Figure 10. The resulting output swing is calculated
by simply inserting the New Slope value and the intercept at that
frequency (Figure 10 and Figure 13) into the general equation
for the AD8313’s output voltage:
VOUT = Slope(PIN − Intercept)
Rev. D | Page 18 of 24
AD8313
INCREASING OUTPUT CURRENT
EFFECT OF WAVEFORM TYPE ON INTERCEPT
To drive a more substantial load, either a pull-up resistor or an
emitter-follower can be used.
Although specified for input levels in dBm (dB relative to
1 mW), the AD8313 responds to voltage and not to power. A
direct consequence of this characteristic is that input signals of
equal rms power but differing crest factors produce different
results at the log amp’s output.
In Figure 40, a 1 kΩ pull-up resistor is added at the output,
which provides the load current necessary to drive a 1 kΩ load
to 1.7 V for VS = 2.7 V. The pull-up resistor slightly lowers the
intercept and the slope. As a result, the transfer function of the
AD8313 is shifted upward (intercept shifts downward).
+VS
1 VPOS
0.1µF
VOUT 8
AD8313
2 INHI
3 INLO
+VS
20mV/dB
RL = 1kΩ
VSET 7
COMM 6
R3
10Ω
01085-C-040
+VS
1kΩ
R1
10Ω
4 VPOS PWDN 5
0.1µF
Figure 40. Increasing AD8313 Output Current Capability
In Figure 41, an emitter-follower provides the current gain,
when a 100 Ω load can readily be driven to full-scale output.
While a high ß transistor such as the BC848BLT1 (min ß = 200)
is recommended, a 2 kΩ pull-up resistor between VOUT and
+VS can provide additional base current to the transistor.
βMIN = 200
1
0.1µF
VPOS VOUT 8
AD8313
2
INHI
VSET 7
3
INLO
COMM 6
4
VPOS PWDN 5
BC848BLT1
13kΩ
OUTPUT
10kΩ
+VS
Table 6 shows the correction factors that should be applied to
measure the rms signal strength of a various signal types. A
continuous wave input is used as a reference. To measure the
rms power of a square wave, for example, the mV equivalent of
the dB value given in the table (18 mV/dB × 3.01 dB) should be
subtracted from the output voltage of the AD8313.
Table 6. Shift in AD8313 Output for Signals with
Differing Crest Factors
+VS
R1
10Ω
RL
100Ω
R3
10Ω
0.1µF
01085-C-041
+VS
Different signal waveforms vary the effective value of the log
amp’s intercept upward or downward. Graphically, this looks
like a vertical shift in the log amp’s transfer function. The
device’s logarithmic slope, however, is in principle not affected.
For example, if the AD8313 is being fed alternately from a
continuous wave and from a single CDMA channel of the same
rms power, the AD8313 output voltage differs by the equivalent
of 3.55 dB (64 mV) over the complete dynamic range of the
device (the output for a CDMA input being lower).
Figure 41. Output Current Drive Boost Connection
Signal Type
CW Sine Wave
Square Wave or DC
Triangular Wave
GSM Channel (All Time Slots On)
CDMA Channel
PDC Channel (All Time Slots On)
Gaussian Noise
In addition to providing current gain, the resistor/potentiometer
combination between VSET and the emitter of the transistor
increases the log slope to as much as 45 mV/dB, at maximum
resistance. This gives an output voltage of 4 V for a 0 dBm input.
If no increase in the log slope is required, VSET can be connected
directly to the emitter of the transistor.
Rev. D | Page 19 of 24
Correction Factor
(Add to Output Reading)
0 dB
−3.01 dB
+0.9 dB
+0.55 dB
+3.55 dB
+0.58 dB
+2.51 dB
AD8313
EVALUATION BOARD
SCHEMATIC AND LAYOUT
Figure 44 shows the schematic of the AD8313 evaluation board.
Note that uninstalled components are indicated as open. This
board contains the AD8313 as well as the AD8009 currentfeedback operational amplifier.
The evaluation board comes with the AD8313 configured to
operate in RSSI/measurement mode. This mode is set by the
0 Ω resistor (R11), which shorts the VOUT and VSET pins to
each other. When using the AD8009, the AD8313 logarithmic
output appears on the SMA connector labeled VOUT. Using
only the AD8313, the log output can be measured at TP1 or the
SMA connector labeled VSET.
This is a 4-layer board (top and bottom signal layers, ground,
and power). The top layer silkscreen and layout are shown in
Figure 42 and Figure 43. A detailed drawing of the recommended
PCB footprint for the MSOP package and the pads for the
matching components are shown in Figure 45.
USING THE AD8009 OPERATIONAL AMPLIFIER
The vacant portions of the signal and power layers are filled out
with ground plane for general noise suppression. To ensure a low
impedance connection between the planes, there are multiple
through-hole connections to the RF ground plane. While the
ground planes on the power and signal planes are used as
general-purpose ground returns, any RF grounds related to the
input matching network (for example, C2) are returned directly
to the RF internal ground plane.
The AD8009 alleviates both of these issues. It is an ultrahigh
speed current feedback amplifier capable of delivering over
175 mA of load current, with a slew rate of 5,500 V/µs, which
results in a rise time of 545 ps, making it ideal as a pulse amplifier.
GENERAL OPERATION
The AD8313 should be powered by a single supply in the range
of 2.7 V to 5.5 V. The power supply to each AD8313 VPOS pin is
decoupled by a 10 Ω resistor and a 0.1 µF capacitor. The AD8009
can run on either single or dual supplies, +5 V to ±6 V. Both the
positive and negative supply traces are decoupled using a 0.1 µF
capacitor. Pads are provided for a series resistor or inductor to
provide additional supply filtering.
The two signal inputs are ac-coupled using 680 pF high quality
RF capacitors (C1, C2). A 53.6 Ω resistor across the differential
signal inputs (INHI, INLO) combines with the internal 900 Ω
input impedance to give a broadband input impedance of 50.6 Ω.
This termination is not optimal from a noise perspective due to
the Johnson noise of the 53.6 Ω resistor. Neither does it account
for the AD8313’s reactive input impedance nor for the decrease
over frequency of the resistive component of the input impedance. However, it does allow evaluation of the AD8313 over its
complete frequency range without having to design multiple
matching networks.
For optimum performance, a narrow-band match can be
implemented by replacing the 53.6 Ω resistor (labeled L/R) with
an RF inductor and replacing the 680 pF capacitors with
appropriate values. The Narrow-Band LC Matching Example
at 100 MHz section includes a table of recommended values for
selected frequencies and explains the method of calculation.
Switch 1 is used to select between power-up and power-down
modes. Connecting the PWDN pin to ground enables normal
operation of the AD8313. In the opposite position, the PWDN
pin can be driven externally (SMA connector labeled ENBL) to
either device state, or it can be allowed to float to a disabled
device state.
The AD8313 can supply only 400 µA at VOUT. It is also sensitive
to capacitive loading, which can cause inaccurate measurements,
especially in applications where the AD8313 is used to measure
the envelope of RF bursts.
The AD8009 is configured as a buffer amplifier with a gain of 1.
Other gain options can be implemented by installing the appropriate resistors at R10 and R12.
Various output filtering and loading options are available using
R5, R6, and C6. Note that some capacitive loads may cause the
AD8009 to become unstable. It is recommended that a 42.2 Ω
resistor be installed at R5 when driving a capacitive load. More
details can be found in the AD8009 data sheet.
VARYING THE LOGARITHMIC SLOPE
The slope of the AD8313 can be increased from its nominal
value of 18 mV/dB to a maximum of 40 mV/dB by removing
R11, the 0 Ω resistor, which shorts VSET to VOUT. VSET and
VOUT are now connected through the 20 kΩ potentiometer.
The AD8009 must be configured for a gain of 1 to accurately
vary the slope of the AD8313.
OPERATING IN CONTROLLER MODE
To put the AD8313 into controller mode, R7 and R11 should
be removed, breaking the link between VOUT and VSET. The
VSET pin can then be driven externally via the SMA connector
labeled VSET.
RF BURST RESPONSE
The VOUT pin of the AD8313 is very sensitive to capacitive
loading, as a result care must be taken when measuring the
device’s response to RF bursts. For best possible response time
measurements it is recommended that the AD8009 be used to
buffer the output from the AD8313. No connection should be
made to TP1, the added load will effect the response time.
Rev. D | Page 20 of 24
01085-C-049
001085-C-048
AD8313
Figure 43. Signal Layer Silkscreen
Figure 42. Layout of Signal Layer
Rev. D | Page 21 of 24
AD8313
VNEG
C7
0.1µF
R4
0Ω
R12
301Ω
Z1
VPS1
Z2
C1
680pF
C3
0.1µF
INHI
1
VOUT 8
R2
10Ω
AD8009
R11
0Ω
AD8313
VSET 7
3
INLO
COMM 6
4
VPOS PWDN 5
C5
0.1µF R3
0Ω
L/R
53.6Ω
INLO
R9
0Ω
VPOS
INHI
2
C2
680pF
C4
0.1µF
R7
0Ω
VOUT
R6
OPEN
C6
OPEN
R8
20kΩ
EXT VSET
VPS2
R2
10Ω
VPS1
R5
0Ω
TP1
EXT ENABLE
SW1
B
01085-C-046
R1
10Ω
R10
OPEN
A
Figure 44. Evaluation Board Schematic
Table 7. Evaluation Board Configuration Options
Component
VPS1, VPS2,
GND, VNEG
Z1
Z1
SW1
R7, R8
L/R, C1, C2, R9
R10, R12
R5, R6, C6
R1, R2, R3, R4,
C3, C4, C5, C7
Function
Supply Pins. VPS1 is the positive supply pin for the AD8313. VPS2 and VNEG are the
positive and negative supply pins for the AD8009. If the AD8009 is being operated
from a single supply, VNEG should be connected to GND. VPS1 and VPS2 are
independent. GND is shared by both devices.
AD8313 Logarithmic Amplifier. If the AD8313 is used in measurement mode, it is not
necessary to power up the AD8009 op amp. The log output can be measured at TP1 or
at the SMA connector labeled VSET.
AD8009 Operational Amplifier.
Device Enable. When in Position A, the PWDN pin is connected to ground and the
AD8313 is in normal operating mode. In Position B, the PWDN pin is connected to an
SMA connector labeled ENBL. A signal can be applied to this connector.
Slope Adjust. The slope of the AD8313 can be increased from its nominal value of
18 mV/dB to a maximum of 40 mV/dB by removing R11, the 0 Ω resistor, which shorts
VSET to VOUT, and installing a 0 Ω resistor at R7. The 20 kΩ potentiometer at R8 can
then be used to change the slope.
Operating in Controller Mode. To put the AD8313 into controller mode, R7 and R11
should be removed, breaking the link between VOUT and VSET. The VSET pin can then
be driven externally via the SMA connector labeled VSET.
Input Interface. The 52.3 Ω resistor in position L/R, along with C1 and C2, create a
wideband 50 Ω input. Alternatively, the 52.3 Ω resistor can be replaced by an inductor
to form an input matching network. See Input Coupling section for more details.
Remove the 0 Ω resistor at R9 for differential drive applications.
Op Amp Gain Adjust. The AD8009 is initially configured as a buffer; gain = 1. To increase
the gain of the op amp, modify the resistor values R10 and R12.
Op Amp Output Loading/Filtering. A variety of loading and filtering options are
available for the AD8009. The robust output of the op amp is capable of driving low
impedances such as 50 Ω or 75 Ω, configure R5 and R6 accordingly. See the AD8009
data sheet for more details.
Supply Decoupling.
Rev. D | Page 22 of 24
Default
Not Applicable
Installed
Installed
SW1 = A
R7 = 0 Ω (Size 0603)
R8 = installed
L/R = 53.6 Ω (Size 0603)
C1 = C2 = 680 pF (Size 0603)
R9 = 0 Ω (Size 0603)
R10 = open (Size 0603)
R12 = 301 Ω (Size 0603)
R5 = 0 Ω (Size 0603)
R6 = open (Size 0603)
C6 = open (Size 0603)
R1 = R2 = 10 Ω (Size 0603)
R3 = R4 = 0 Ω (Size 0603)
C3 = C4 = 0.1 µF (Size 0603)
C5 = C7 = 0.1 µF (Size 0603)
AD8313
NOT CRITICAL DIMENSIONS
35
TRACE WIDTH
15.4
48
54.4
90.6
50
16
28
41
22
75
20
10
19
UNIT = MILS
50
20
27.5
51
91.3
48
126
51.7
01085-C-047
46
Figure 45. Detail of PCB Footprint for Package and Pads for Matching Network
Rev. D | Page 23 of 24
AD8313
OUTLINE DIMENSIONS
3.00
BSC
8
5
4.90
BSC
3.00
BSC
4
PIN 1
0.65 BSC
1.10 MAX
0.15
0.00
0.38
0.22
COPLANARITY
0.10
0.23
0.08
8°
0°
0.80
0.60
0.40
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-187AA
Figure 46 . 8-Lead MicroSOIC Package [MSOP]
(RM-08)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model
AD8313ARM
AD8313ARM-REEL
AD8313ARM-REEL7
AD8313ARMZ1
AD8313ARMZ-REEL71
AD8313-EVAL
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Descriptions
8-Lead MSOP
13" Tape and Reel
7" Tape and Reel
8-Lead MSOP
7" Tape and Reel
Evaluation Board
Z = Pb-free part.
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C01085–0–6/04(D)
Rev. D | Page 24 of 24
Package Option
RM-08
RM-08
RM-08
Branding
J1A
J1A
J1A