APW7101 1.5MHz, 600mA, Synchronous Buck Regulator Features • • • • • General Description The APW7101 is a high efficiency monolithic synchronous buck regulator. APW 7101 operates with a constant 600mA Output Current 2.5V to 5.5V Input Voltage Range 1.5MHz switching frequency and using the inductor current as a controlled quantity in the current mode 1.5MHz Constant Frequency Operation architecture. The device is available in an adjustable version and fixed output voltages of 1.5V and 1.8V. The 2.5V Low Dropout Operation at 100% Duty Cycle Synchronous Topology: to 5.5V input voltage range makes the APW7101 ideally suited for single Li-Ion battery powered applications. No Schottky Diode Required • • • 100% duty cycle provides low dropout operation, extending battery life in portable electrical devices. The internally 0.6V Low Reference Voltage Shutdown Mode Supply Current Under 1µA fixed 1.5MHz operating frequency allows the use of small surface mount inductors and capacitors. The synchro- Current Mode Operation for Excellent Line and nous switches included inside increase the efficiency and eliminate the need for an external Schottky diode. Low Load Transient Response • • • • Over-Temperature Protection output voltages are easily supported with the 0.6V feedback reference voltage. The APW7101 is available in a Over Current Protection low profile SOT package for saving the printed circuit board area. SOT-23-5 Package Lead Free and Green Devices Available (RoHS Compliant) Pin Configuration Applications • • • • • • Cellular Telephones Top View Personal Information Appliances RUN 1 Wireless and DSL Modems GND 2 5 VFB SW 3 MP3 Players Digital Still Cameras 4 VIN APW7101 ADJ Portable Instruments Top View RUN 1 5 VOUT GND 2 SW 3 4 VIN APW7101 1.5V/1.8V ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.4 - Jun., 2008 1 www.anpec.com.tw APW7101 Ordering and Marking Information Package Code B : SOT-23-5 Temperature Range Assembly Material I : -40 to 85 °C Handling Code Handling Code Temperature Range TR : Tape & Reel Voltage Code Package Code 15: 1.5V 18: 1.8V Blank : Adjustable Version Voltage Code Assembly Material L : Lead Free Device G : Halogen and Lead Free Device APW7101 - APW7101-15 : 019X X - Date Code APW7101 : W01X X - Date Code APW7101-18 : 01CX X - Date Code Note : ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD020C for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Absolute Maximum Ratings Symbol Parameter Value Unit -0.3V to 6V V VCC Input Supply Voltage (VCC to GND) VRUN RUN Pin Voltage -0.3V to (VCC+0.3V) V VFB Feedback Voltage -0.3V to (VCC+0.3V) V VSW Switching Voltage -0.3V to (VCC+0.3V) V ISW_PEAK Peak SW Current 1.3 A PD Average Power Dissipation 0.5 W TJ Junction Temperature, TA < 50° 150 °C -65 ~ 150 °C 260 °C TSTG Storage Temperature TSDR Maximum Lead Soldering Temperature, 10 Seconds Thermal Characteristics Symbol θJA Parameter Junction to Ambient Thermal Resistance in Free Air Copyright ANPEC Electronics Corp. Rev. A.4 - Jun., 2008 2 Typical Value Unit 250 °C/W www.anpec.com.tw APW7101 Electrical Characteristics The * denotes the specifications that apply over TA = -40°C ~ 85°C, otherwise specifications are at TA=25°C. APW7101 Symbol Parameter Test conditions Unit Min. Typ. Max. * -30 - 30 nA IVFB Feedback Current VIN Input Voltage Range *Note * 2.5 - 5.5 V VFB Regulated Feedback Voltage -40°C ≤ TA ≤ 85°C * 0.585 0.6 0.615 V ∆VFB Reference Voltage Line Regulation VIN = 2.5V to 5.5V * - 0.04 0.4 %/V APW7101-1.5, IOUT = 100mA * 1.455 1.500 1.545 V VOUT Regulated Output Voltage APW7101-1.8, IOUT=100mA * 1.746 1.800 1.854 V Output Voltage Line Regulation VIN = 2.5V to 5.5V * - 0.04 0.4 %/V Peak Inductor Current VOUT = 90% Duty < 35% 0.75 1 1.25 A - 0.5 - 300 400 µA - 0.1 1 µA 1.2 1.5 1.8 MHz ∆VOUT VIN = 3V, VFB = 0.5V or IPK VLOADR IQ Output Voltage Load Regulation Quiescent Current Duty Cycle = 0; VFB = 1.5V % IQ_SD Quiescent Current in Shutdown fOSC Oscillator Frequency VFB = 0.6V or VOUT = 100% fOSC_FFB Frequency Foldback VFB = 0V or VOUT = 0V - 300 - kHz RDSON_P On Resistance of P MOSFET ISW = 100mA - 0.4 0.5 Ω RDSON_N On Resistance of N MOSFET ISW = -100mA - 0.35 0.45 Ω ILSW SW Leakage Current VRUN = 0V, VSW = 0V or 5V, VIN = 5V - ±0.01 ±1 µA VRUN RUN Threashold * 0.3 1 1.5 V IRUN RUN Leakage Current * - ±0.01 ±1 µA Note: The Maximum output current didn’t reach 600mA when the supply voltage below 2.7V. Pin Descrpition No. PIN FUNCTION 1 RUN Control input pin. Forcing this pin above 1.5V enables APW7101. Forcing this pin below 0.3V shuts down APW7101. In shutdown situation, all functions are disabled to decrease the supply current below 1µA.There is no pull high or pull low ability inside. 2 GND Ground pin. 3 SW Connected this pin to the inductor of the power stage. This pin connected to the drain terminals of the main and synchronous power MOSFET switches inside. 4 VIN Must be closely decoupled to GND with 4.7µF or greater ceramic capacitor. 5 VFB/VOUT In the adjustable version, feedback function is available. The feedback voltage decided by an external resistive divider across the output. In the fixed version, an internal resistive divider divides the output voltage down for comparison to the internal reference voltage. Copyright ANPEC Electronics Corp. Rev. A.4 - Jun., 2008 3 www.anpec.com.tw APW7101 Block Diagram Slop Compensation Σ ICOMP Oscillator VIN Frequency Shift RSENSE VFB EA QSENSE 0.6V R Q SW Control Logic S Q Shutdown RUN QP QN Reverse detect GND Application Circuit VIN 2.5V TO 5.5V 4 1 CIN 4.7µF L 2.2µH APW7101 VDD SW RUN FB 3 VIN 2.5V TO 5.5V VOUT=2.5V 5 GND 2 4 1 RF1 470K CIN 4.7µF COUT 10µF VDD SW RUN FB GND 2 RF2 150K L 2.2µH APW7101/1.5V/1.8V 3 VOUT 5 COUT 10µF CIN: Murata GRM31CR61C475K COUT: Murata GRM31CR61A106K L: Gotrend GTSD53 Copyright ANPEC Electronics Corp. Rev. A.4 - Jun., 2008 4 www.anpec.com.tw APW7101 Typical Operating Characteristics Oscillator Frequency 0.615 1800 0.610 1700 VIN=5.5V 0.605 VIN=2.5V Frequency (kHz) Reference Voltage (V) Reference Voltage 0.600 0.595 VIN=3.6V 1600 1500 1400 1300 0.590 1200 0.585 -50 -25 0 25 50 75 100 -50 125 -25 Temperature (o C) 0 25 50 75 100 125 100 125 Temperature (o C) Oscillator Frequency vs Supply Voltage RDS(ON) vs Temperature 700 1800 VIN=2.7V TA=25o C VIN=3.6V 600 1700 VIN=4.2V 1600 ON Resistance (mΩ) Frequency (kHz) 500 1500 1400 1300 400 300 200 NMOS PMOS 100 0 1200 2 3 4 5 -50 6 0 25 50 75 Temperature (o C) Supply Voltage (V) Copyright ANPEC Electronics Corp. Rev. A.4 - Jun., 2008 -25 5 www.anpec.com.tw APW7101 Typical Operating Characteristics (Cont.) Efficiency vs Output Current RDS(ON) vs Input Voltage 600 100 VOUT=1.2V TA=25o C 90 PMOS VIN=2.7V 80 70 400 Efficiency (%) ON Resistance (mΩ) 500 300 NMOS 200 60 50 40 VIN=3.6V 30 20 100 VIN=4.2V 10 0 0 0 1 2 3 4 5 0.1 6 Input Voltage (V) 10.0 100.0 1000.0 Output Current (mA) Efficiency vs Output Current Efficiency vs Output Current 100 100 VOUT=1.5V TA=25o C 90 VIN=2.7V VOUT=2.5V TA=25o C 90 80 80 70 70 VIN=3.6V Efficiency (%) Efficiency (%) 1.0 60 50 40 30 VIN=4.2V VIN=3.6V 60 50 40 30 20 20 10 10 0 VIN=4.2V VIN=2.7V 0 0.1 1.0 10.0 100.0 1000.0 0.1 Output Current (mA) Copyright ANPEC Electronics Corp. Rev. A.4 - Jun., 2008 1.0 10.0 100.0 1000.0 Output Current (mA) 6 www.anpec.com.tw APW7101 Typical Operating Characteristics (Cont.) Efficiency vs Output Current Output Voltage vs Output Current 100 1.008 V OUT=1V L=2.2uH TA=25°C 90 1.004 70 Output Voltage (mV) Efficiency (%) 80 V IN=3.3V 60 L=2.2uH TA=25°C 1.006 50 V IN=5V 40 30 V IN=5V 1.002 1 0.998 0.996 V IN=3.3V 0.994 20 0.992 10 0.99 0.988 0 0.1 1 10 100 0 1000 100 200 Output Current (mA) 100 95 95 600 IOUT=100mA 90 IOUT=100mA 85 IOUT=600mA Efficiency (%) Efficiency (%) 500 Efficiency vs Input Voltage 100 85 400 Output Current (mA) Efficiency vs Input Voltage 90 300 80 75 IOUT=10mA 70 65 IOUT=600mA 80 75 IOUT=10mA 70 65 60 60 VOUT=1.5V TA=25o C 55 VOUT=1.8V TA=25o C 55 50 50 2 3 4 5 2 6 Input Voltage (V) Copyright ANPEC Electronics Corp. Rev. A.4 - Jun., 2008 3 4 5 6 Input Voltage (V) 7 www.anpec.com.tw APW7101 Typical Operating Characteristics (Cont.) Efficiency vs Input Voltage Dynamic Supply Current vs Supply Voltage 100 400 95 380 IOUT=100mA 90 Efficiency (%) 85 Dynamic Supply Current (µA) 360 IOUT=600mA 80 75 IOUT=10mA 70 65 60 VOUT=2.5V TA=25o C 55 50 340 320 300 280 260 240 220 200 2 3 4 5 6 2 3 P-FET Leakage vs Temperature 6 N-FET Leakage vs Temperature 300 800 250 750 N-FET Leakage(nA) P-FET Leakage(nA) 5 Supply Voltage (V) Input Voltage (V) 200 150 4 VIN=5.5V 100 50 700 650 VIN=5.5V 600 550 0 500 -50 -25 0 25 50 75 100 125 -50 o Temperature ( C) Copyright ANPEC Electronics Corp. Rev. A.4 - Jun., 2008 -25 0 25 50 75 100 125 o Temperature ( C) 8 www.anpec.com.tw APW7101 Function Description Main Control Loop current has to restrict to protect the electrical circuit in the short situation. The APW7101 uses a constant frequency, current mode step-down architecture. Both the main and synchronous switches are internal to reduce the external Dropout Operation As the input supply voltage decreases to a value ap- components. During normal operation, the internal PMOSFET is turned on, but is turned off when the induc- proaching the output voltage, the duty cycle increases toward the maximum on time. Further reduction of the sup- tor current at the input of ICOMP to reset the RS latch. The load current increases, it causes a slight decrease in ply voltage forces the main switch to remain on for more than one cycle until it reaches 100% duty cycle. The out- the feedback voltage, which in turn, causes the EA’s output voltage to increase until the average inductor current put voltage will then be determined by the input voltage minus the voltage drop across the PMOSFET and the matches the new load current. While the internal power PMOSFET is off, the internal power NMOSFET is turned inductor. An important detail to remember is that on resistance of on until the inductor current starts to reverse, as indicated by the current reversal comparator IRCMP, or the beginning PMOSFET switch will increase at low input supply voltage. Therefore, the user should calculate the power dissipa- of next cycle. When the NMOSFET is turned off by IRCMP, it tion when the APW7101 is used at 100% duty cycle with low input voltage. operates in the discontinuous conduction mode. Pulse Skipping Mode Operation Slope Compensation At light load with a relative small inductance, the inductor current may reach zero. The internal power Slope compensation provides stability in constant frequency current mode architecture by preventing sub- NMOSFET is turned off by the current reversal comparator, IRCMP, and the switching voltage will ring. This is discon- harmonic oscillations at high duty cycle. It is accomplished internally by adding a compensating ramp to the tinuous mode operation, and is normal behavior for the switching regulator. At very light load, the APW7101 will inductor current signal at duty cycle in excess of 40%. Normally, this results in a reduction of maximum induc- automatically skip some pulses in the pulse skipping mode to maintain the output regulation. The skipping pro- tor peak current for duty cycles greater than 40%. In the APW7101, the reduction of inductor peak current recov- cess modulates smoothly depend on the load. ered by a special skill at high duty ratio. This allows the maximum inductor peak current maintain a constant level Short Circuit Protection through all duty ratio. In the short circuit situation, the output voltage is almost zero volts. Output current is limited by the ICOMP to prevent the damage of electrical circuit. In the normal operation, the two straight line of the inductor current ripple have the same height, it means the volts-seconds product is the same. When the short circuit operation occurs, the output voltage down to zero leads to the voltage across the inductor maximum in the on period and the voltage across the inductor minimum in the off period. In order to maintain the volts-seconds balance, the offtime must be extended to prevent the inductor current run away. Frequency decay will extend the switching period to provide more times to the off-period, then the inductor Copyright ANPEC Electronics Corp. Rev. A.4 - Jun., 2008 9 www.anpec.com.tw APW7101 Application Information Inductor Selection Figure-1 shows a schematic of a Buck structure. The Due to the high switching frequency as 1.5MHz, the in- waveforms is shown as Figure-2. ductor value of the application field of APW7101 is usually from 1µH to 4.7µH. The criterion to select a suitable in- IL IOUT ductor is dependent on the worst current ripple throughout the inductor. The worst current ripple defines as 40% IIN 0A of the fully load capability. In the APW7101 applications, the worst value of current ripple is 240mA, the 40% of 600mA. Evaluate L by equation (1): L = (VIN − V OUT ) ⋅ V OUT 1 ⋅ VIN ∆ IL ⋅ f S I(CIN) IIN 0A ......( 1) where fS is the switching frequency of APW7101 and ∆IL is the value of the worst current ripple, it can be any value of current ripple that smaller than the worst value you can 0A I(COUT) accept. In order to perform high efficiency, selecting a low DC resistance inductor is a helpful way. Another impor- I(Q1) tant parameter is the DC current rating of the inductor. The minimum value of DC current rating equals the full IOUT load value of 600mA, plus the half of the worst current ripple, 120mA. Choose inductors with suitable DC 0A current rating to ensure the inductors don’t operate in the saturation. D*TS PWM (1-D)*TS Input Capacitor Selection 0A The input capacitor must be able to support the maxi- Figure-2 mum input operating voltage and maximum RMS input current. The Buck converter absorbs current from input in Observe the waveform of I(CIN),the RMS value of I(CIN) is pulses. I(CIN ) = [(I OUT ] ( − IIN ) ⋅ D + IIN ⋅ 1 − D 2 2 ) 2 ......( 2) Replace D and IIN by following relation: D= VOUT ......( 3) VIN IIN = D ⋅ IOUT ......( 4) The RMS value of input capacitor current equal: I(CIN ) = IOUT ⋅ D(1 − D) ......( 5) When D=0.5 the RMS current of input capacitor will be maximum value. Use this value to choose the input Figure-1 capacitor with suitable current rating. Copyright ANPEC Electronics Corp. Rev. A.4 - Jun., 2008 10 www.anpec.com.tw APW7101 Application Information (Cont.) Output Capacitor Selection The output voltage ripple is a significant parameter to estimate the performance of a convertor. There are two discrete components that affect the output voltage ripple bigger or smaller. It is recommended to use the criterion has mentioned above to choose a suitable inductor. Then based on this known inductor current ripple condition, the value and properties of output capacitor will affect the output voltage ripple better or worse. The output voltage ripple consists of two portions, one is the product of ESR and inductor current ripple, the other portion is the function of the inductor current ripple and the output capacitance. Figure-3 shows the waveforms to explain the part decided by the output capacitance. TS ∆ VOUT = ∆ IL ⋅ ESL + ⋅ 8 C OUT ......( 8 ) Thermal Consideration APW7101 is a high efficiency switching converter, it means less power loss transferred into heat. Due to the on resistance difference between internal power PMOSFET and NMOSFET, the power dissipation in the high converting ratio is greater than low converting ratio. The worst case is in the dropout operation, the mainly conduction loss dissipate on the internal power PMOSFET. The power dissipation nearly defined as: [ ] PD = (IOUT ) R DS _ ONP ⋅ D + R DS _ ONN ⋅ (1 − D) ......( 9) 2 APW7101 has internal over temperature protection. When the junction temperature reaches 150 centigrade, APW7101 will turn off both internal power PMOSFET and ∆IL 0A NMOSFET. The estimation of the junction temperature, I(COUT) TJ, defined as: TJ = PD ⋅ θ JA ......(10 ) 0.5TS where the θJA is the thermal resistance of the package ∆VOUT1 VOUT utilized by APW7101. Output Voltage Setting APW7101 has the adjustable version for output voltage setting by the users. A suggestion of maximum value of RF2 is 200kΩ to keep the minimum current that provides Figure-3 Evaluate the ∆VOUT1 by the ideal of energy equalization. enough noise rejection ability through the resistor divider. The output voltage programmed by the equation: According to the definition of Q, Q = R V OUT = 0 . 6 ⋅ 1 + F1 R F2 11 1 ∆ IL ⋅ TS = C OUT ⋅ ∆ V OUT 1 ......( 6 ) 22 2 ......( 11) VOUT where TS is the inverse of switching frequency and the ∆IL is the inductor current ripple. Move the COUT to the left side to estimate the value of ∆VOUT1 as equation (7). ∆ V OUT 1 = ∆ IL ⋅ TS 8 ⋅ C OUT APW7101 FB ......( 7 ) As mentioned above, one part of output voltage ripple is RF2 the product of the inductor current ripple and ESR of output capacitor. The equation (8) explains the output voltage ripple estimation. Copyright ANPEC Electronics Corp. Rev. A.4 - Jun., 2008 RF1 Figure-4 11 www.anpec.com.tw APW7101 Application Description (Cont.) PCB Layout Consideration APW7101 is a high efficiency DC-DC converter which is a noise source in the electrical circuit by its switching operating. Some PCB layout considerations suppress the effect of switching operating by APW7101 itself to improve the better regulation. <1> Keep the power trace wide and short as possible. The power trace shows in the Figure-6 as thick solid lines. <2> Put the CIN to VIN close and COUT near the inductor as possible. <3> Keep the ground terminal of CIN and COUT as close as possible to minimize the AC current loop. <4> Put the voltage divider consist of RF1 and RF2 closely to FB, the connection path between RF1 and VOUT must far away the SW to prevent the switch noise coupling into FB by crosstalk. If necessary, the connection path between RF1 and VOUT must near to SW, put a ground trace between the feedback trace and SW to prevent Figure-6 Suggested layout Top Side the coupling. VIN 2.5V TO 5.5V 4 1 CIN 4.7µF VIN 2.5V TO 5.5V VDD SW RUN FB 3 5 COUT 10µF RF2 2 APW7101/1.5V/1.8V 4 VDD SW RUN FB VOUT RF1 GND 1 CIN 4.7µF L 2.2µH APW7101 3 L 2.2µH VOUT 5 GND 2 COUT 10µF Figure-5 Figure-7 Suggested layout Button Side Copyright ANPEC Electronics Corp. Rev. A.4 - Jun., 2008 12 www.anpec.com.tw APW7101 Package Information SOT-23-5 D e E E1 SEE VIEW A b c 0.25 A L 0 GAUGE PLANE SEATING PLANE A1 A2 e1 VIEW A S Y M B O L SOT-23-5 INCHES MILLIMETERS MIN. MIN. MAX. MAX. A 1.45 A1 0.00 0.15 0.000 0.057 0.006 A2 0.90 1.30 0.035 0.051 0.020 b 0.30 0.50 0.012 c 0.08 0.22 0.003 0.009 D 2.70 3.10 0.106 0.122 0.118 0.071 E 2.60 3.00 0.102 E1 1.40 1.80 0.055 e 0.95 BSC e1 1.90 BSC 0.037 BSC 0.075 BSC L 0.30 0.60 0 0° 8° 0.012 0° 0.024 8° Note : 1. Follow JEDEC TO-178 AA. 2. Dimension D and E1 do not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 10 mil per side. Copyright ANPEC Electronics Corp. Rev. A.4 - Jun., 2008 13 www.anpec.com.tw APW7101 Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application A H 178.0±2.00 50 MIN. SOT-23-5 T1 C d D 8.4+2.00 13.0+0.50 1.5 MIN. -0.00 -0.20 P0 P1 P2 D0 D1 4.0±0.10 4.0±0.10 2.0±0.05 1.5+0.10 -0.00 1.0 MIN. 20.2 MIN. T W E1 8.0±0.30 1.75±0.10 A0 B0 F 3.5±0.05 K0 0.6+0.00 -0.40 3.20±0.20 3.10±0.20 1.50±0.20 (mm) Devices Per Unit Package Type Unit Quantity SOT-23-5 Tape & Reel 3000 Copyright ANPEC Electronics Corp. Rev. A.4 - Jun., 2008 14 www.anpec.com.tw APW7101 Reflow Condition (IR/Convection or VPR Reflow) tp TP Critical Zone TL to TP Temperature Ramp-up TL tL Tsmax Tsmin Ramp-down ts Preheat 25 t 25°C to Peak Time Reliability Test Program Test item SOLDERABILITY HOLT PCT TST ESD Latch-Up Method MIL-STD-883D-2003 MIL-STD-883D-1005.7 JESD-22-B, A102 MIL-STD-883D-1011.9 MIL-STD-883D-3015.7 JESD 78 Description 245°C, 5 sec 1000 Hrs Bias @125°C 168 Hrs, 100%RH, 121°C -65°C~150°C, 200 Cycles VHBM > 2KV, VMM > 200V 10ms, 1tr > 100mA Classification Reflow Profiles Profile Feature Average ramp-up rate (TL to TP) Preheat - Temperature Min (Tsmin) - Temperature Max (Tsmax) - Time (min to max) (ts) Time maintained above: - Temperature (TL) - Time (tL) Peak/Classification Temperature (Tp) Time within 5°C of actual Peak Temperature (tp) Ramp-down Rate Sn-Pb Eutectic Assembly Pb-Free Assembly 3°C/second max. 3°C/second max. 100°C 150°C 60-120 seconds 150°C 200°C 60-180 seconds 183°C 60-150 seconds 217°C 60-150 seconds See table 1 See table 2 10-30 seconds 20-40 seconds 6°C/second max. 6°C/second max. 6 minutes max. 8 minutes max. Time 25°C to Peak Temperature Note: All temperatures refer to topside of the package. Measured on the body surface. Copyright ANPEC Electronics Corp. Rev. A.4 - Jun., 2008 15 www.anpec.com.tw APW7101 Classification Reflow Profiles (Cont.) Table 1. SnPb Eutectic Process – Package Peak Reflow Temperatures 3 Package Thickness Volume mm <350 <2.5 mm 240 +0/-5°C ≥2.5 mm 225 +0/-5°C 3 Volume mm ≥350 225 +0/-5°C 225 +0/-5°C Table 2. Pb-free Process – Package Classification Reflow Temperatures 3 3 3 Package Thickness Volume mm Volume mm Volume mm <350 350-2000 >2000 <1.6 mm 260 +0°C* 260 +0°C* 260 +0°C* 1.6 mm – 2.5 mm 260 +0°C* 250 +0°C* 245 +0°C* ≥2.5 mm 250 +0°C* 245 +0°C* 245 +0°C* *Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the stated classification temperature (this means Peak reflow temperature +0°C. For example 260°C+0°C) at the rated MSL level. Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.4 - Jun., 2008 16 www.anpec.com.tw