Cypress CY7C68001-56LFXC Ez-usb sx2â ¢ high-speed usb interface device Datasheet

CY7C68001
EZ-USB SX2™ High-Speed USB Interface Device
1.0
EZ-USB SX2™ Features
2.0
• USB 2.0-certified compliant
Applications
• DSL modems
— On the USB-IF Integrators List: Test ID Number
40000713
• ATA interface
• Memory card readers
• Operates at high (480 Mbps) or full (12 Mbps) speed
• Legacy conversion devices
• Supports Control Endpoint 0:
• Cameras
— Used for handling USB device requests
• Scanners
• Supports four configurable endpoints that share a 4-KB
FIFO space
• Home PNA
• Wireless LAN
— Endpoints 2, 4, 6, 8 for application-specific control
and data
• MP3 players
• Networking
• Standard 8- or 16-bit external master interface
• Printers
— Glueless interface to most standard microprocessors DSPs, ASICs, and FPGAs
The “Reference Designs” section of the Cypress web site
provides additional tools for typical USB applications. Each
reference design comes complete with firmware source code
and object code, schematics, and documentation. Please see
the Cypress web site at www.cypress.com.
— Synchronous or Asynchronous interface
• Integrated phase-locked loop (PLL)
• 3.3V operation, 5V tolerant I/Os
• 56-pin SSOP and QFN package
• Complies with most device class specifications
SCL
I2C Bus
Controller
(Master Only)
WAKEUP*
Block Diagram
RESET#
2.1
SDA
IFCLK*
24 MHz
XTAL
Read*, Write*, OE*, PKTEND*, CS#
PLL
Interrupt#, Ready
SX2 Internal Logic
Flags (3/4)
Address (3)
Control
VCC
FIFO
Data
Bus
1.5K
DPLUS
DMINUS
CY Smart USB
FS/HS Engine
USB 2.0 XCVR
4 KB
FIFO
8/16-Bit Data
Data
Figure 2-1. Block Diagram
Cypress Semiconductor Corporation
Document #: 38-08013 Rev. *H
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 1, 2005
CY7C68001
2.2
Introduction
3.3
The EZ-USB SX2™ USB interface device is designed to work
with any external master, such as standard microprocessors,
DSPs, ASICs, and FPGAs to enable USB 2.0 support for any
peripheral design. SX2 has a built-in USB transceiver and
Serial Interface Engine (SIE), along with a command decoder
for sending and receiving USB data. The controller has four
endpoints that share a 4-KB FIFO space for maximum flexibility and throughput, as well as Control Endpoint 0. SX2 has
three address pins and a selectable 8- or 16- bit data bus for
command and data input or output.
2.3
System Diagram
Boot Methods
During the power-up sequence, internal logic of the SX2
checks for the presence of an I2C EEPROM.[1,2] If it finds an
EEPROM, it will boot off the EEPROM. When the presence of
an EEPROM is detected, the SX2 checks the value of first
byte. If the first byte is found to be a 0xC4, the SX2 loads the
next two bytes into the IFCONFIG and POLAR registers,
respectively. If the fourth byte is also 0xC4, the SX2
enumerates using the descriptor in the EEPROM, then signals
to the external master when enumeration is complete via an
ENUMOK interrupt (Section 3.4). If no EEPROM is detected,
the SX2 relies on the external master for the descriptors. Once
this descriptor information is received from the external
master, the SX2 will connect to the USB and enumerate.
3.3.1
W ind ow s/U S B C ap ab le H o st
U SB
EEPROM Organization
The valid sequence of bytes in the EEPROM are displayed
below
Table 3-1. Descriptor Length Set to 0x06:
Default Enumeration
C a ble
Byte Index
0
0xC4
1
IFCONFIG
2
POLAR
3
0xC4
4
Descriptor Length (LSB):0x06
5
Descriptor Length (MSB): 0x00
6
VID (LSB)
7
VID (MSB)
8
PID (LSB)
9
PID (MSB)
10
DID (LSB)
11
DID (MSB)
U SB C o nn ectio n
C ypre ss
S X2
EE PR O M
R AM /R O M
D evice C P U
A pp licatio n
Figure 2-2. Example USB System Diagram
3.0
3.1
Functional Overview
USB Signaling Speed
SX2 operates at two of the three rates defined in the Universal
Serial Bus Specification Revision 2.0, dated April 27, 2000:
Description
Table 3-2. Descriptor Length Not Set to 0x06
Byte Index
Description
• Full-speed, with a signaling bit rate of 12 Mbits/s
0
0xC4
• High-speed, with a signaling bit rate of 480 Mbits/s.
1
IFCONFIG
2
POLAR
3
0xC4
4
Descriptor Length (LSB)
5
Descriptor Length (MSB
6
Descriptor[0]
7
Descriptor[1]
8
Descriptor[2]
SX2 does not support the low-speed signaling rate of 1.5
Mbits/s.
3.2
Buses
SX2 features:
• A selectable 8- or 16-bit bidirectional data bus
• An address bus for selecting the FIFO or Command Interface.
Notes:
1. Because there is no direct way to detect which EEPROM type (single or double address) is connected, SX2 uses the EEPROM address pins A2, A1, and A0
to determine whether to send out one or two bytes of address. Single-byte address EEPROMs (24LC01, etc.) should be strapped to address 000 and doublebyte EEPROMs (24LC64, etc.) should be strapped to address 001.
2. The SCL and SDA pins must be pulled up for this detection method to work properly, even if an EEPROM is not connected. Typical pull-up values are 2.2K–10K
Ohms.
Document #: 38-08013 Rev. *H
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CY7C68001
• 0xC4: This initial byte tells the SX2 that this is a valid EEPROM with configuration information.
3.4
Interrupt System
• IFCONFIG: The IFCONFIG byte contains the settings for
the IFCONFIG register. The IFCONFIG register bits are defined in Section 7.1. If the external master requires an interface configuration different from the default, that interface
can be specified by this byte.
3.4.1
Architecture
• POLAR: The Polar byte contains the polarity of the FIFO
flag pin signals. The POLAR register bits are defined in
Section 7.3. If the external master requires signal polarity
different from the default, the polarity can be specified by
this byte.
• Descriptor: The Descriptor byte determines if the SX2
loads the descriptor from the EEPROM. If this byte = 0xC4,
the SX2 will load the descriptor starting with the next byte.
If this byte does not equal 0xC4, the SX2 will wait for descriptor information from the external master.
• Descriptor Length: The Descriptor length is within the next
two bytes and indicate the length of the descriptor contained
within the EEPROM. The length is loaded least significant
byte (LSB) first, then most significant byte (MSB).
• Byte Index 6 Starts Descriptor Information: The descriptor can be a maximum of 500 bytes.
3.3.2
Default Enumeration
An optional default descriptor can be used to simplify enumeration. Only the Vendor ID (VID), Product ID (PID), and Device
ID (DID) need to be loaded by the SX2 for it to enumerate with
this default set-up. This information is either loaded from an
EEPROM in the case when the presence of an EEPROM
(Table 3-1) is detected, or the external master may simply load
a VID, PID, and DID when no EEPROM is present. In this
default enumeration, the SX2 uses the in-built default
descriptor (refer to Section 12.0).
If the descriptor length loaded from the EEPROM is 6, SX2 will
load a VID, PID, and DID from the EEPROM and enumerate.
The VID, PID, and DID are loaded LSB, then MSB. For
example, if the VID, PID, and DID are 0x0547, 0x1002, and
0x0001, respectively, then the bytes should be stored as:
• 0x47, 0x05, 0x02, 0x10, 0x01, 0x00.
If there is no EEPROM, SX2 will wait for the external master
to provide the descriptor information. To use the default
descriptor, the external master must write to the appropriate
register (0x30) with descriptor length equal to 6 followed by the
VID, PID, and DID. Refer to Section 4.2 for further information
on how the external master may load the values.
The default descriptor enumerates four endpoints as listed in
the following page:
• Endpoint 2: Bulk out, 512 bytes in high-speed mode, 64
bytes in full-speed mode
• Endpoint 4: Bulk out, 512 bytes in high-speed mode, 64
bytes in full-speed mode
• Endpoint 6: Bulk in, 512 bytes in high-speed mode, 64 bytes
in full-speed mode
• Endpoint 8: Bulk in, 512 bytes in high-speed mode, 64 bytes
in full-speed mode.
The entire default descriptor is listed in Section 12.0 of this
data sheet.
Document #: 38-08013 Rev. *H
The SX2 provides an output signal that indicates to the
external master that the SX2 has an interrupt condition, or that
the data from a register read request is available. The SX2 has
six interrupt sources: SETUP, EP0BUF, FLAGS, ENUMOK,
BUSACTIVITY, and READY. Each interrupt can be enabled or
disabled by setting or clearing the corresponding bit in the
INTENABLE register.
When an interrupt occurs, the INT# pin will be asserted, and
the corresponding bit will be set in the Interrupt Status Byte.
The external master reads the Interrupt Status Byte by
strobing SLRD/SLOE. This presents the Interrupt Status Byte
on the lower portion of the data bus (FD[7:0]). Reading the
Interrupt Status Byte automatically clears the interrupt. Only
one interrupt request will occur at a time; the SX2 buffers
multiple pending interrupts.
If the external master has initiated a register read request, the
SX2 will buffer interrupts until the external master has read the
data. This insures that after a read sequence has begun, the
next interrupt that is received from the SX2 will indicate that
the corresponding data is available. Following is a description
of this INTENABLE register.
3.4.2
INTENABLE Register Bit Definition
Bit 7: SETUP
If this interrupt is enabled, and the SX2 receives a set-up
packet from the USB host, the SX2 asserts the INT# pin and
sets bit 7 in the Interrupt Status Byte. This interrupt only occurs
if the set-up request is not one that the SX2 automatically
handles. For complete details on how to handle the SETUP
interrupt, refer to Section 5.0 of this data sheet.
Bit 6: EP0BUF
If this interrupt is enabled, and the Endpoint 0 buffer becomes
available to the external master for read or write operations,
the SX2 asserts the INT# pin and sets bit 6 in the Interrupt
Status Byte. This interrupt is used for handling the data phase
of a set-up request. For complete details on how to handle the
EP0BUF interrupt, refer to Section 5.0 of this data sheet.
Bit 5: FLAGS
If this interrupt is enabled, and any OUT endpoint FIFO’s state
changes from empty to not-empty and from not-empty to
empty, the SX2 asserts the INT# pin and sets bit 5 in the
Interrupt Status Byte. This is an alternate way to monitor the
status of OUT endpoint FIFOs instead of using the FLAGAFLAGD pins, and can be used to indicate when an OUT packet
has been received from the host.
Bit 2: ENUMOK
If this interrupt is enabled and the SX2 receives a
SET_CONFIGURATION request from the USB host, the SX2
asserts the INT# pin and sets bit 2 in the Interrupt Status Byte.
This event signals the completion of the SX2 enumeration
process.
Bit 1: BUSACTIVITY
If this interrupt is enabled, and the SX2 detects either an
absence or resumption of activity on the USB bus, the SX2
asserts the INT# pin and sets bit 1 in the Interrupt Status Byte.
This usually indicates that the USB host is either suspending
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CY7C68001
or resuming or that a self-powered device has been plugged
in or unplugged. If the SX2 is bus-powered, the external
master must put the SX2 into a low-power mode after
detecting a USB suspend condition to be USB-compliant.
RESET# signal. The Clock must be in a stable state for at least
200 µs before the RESET is released.
Bit 0: READY
When the SX2 detects a USB Reset condition on the USB bus,
SX2 handles it like any other enumeration sequence. This
means that SX2 will enumerate again and assert the
ENUMOK interrupt to let the external master know that it has
enumerated. The external master will then be responsible for
configuring the SX2 for the application. The external master
should also check whether SX2 enumerated at High or Full
speed in order to adjust the EPxPKTLENH/L register values
accordingly. The last initialization task is for the external
master to flush all of the SX2 FIFOs.
If this interrupt is enabled, bit 0 in the Interrupt Status Byte is
set when the SX2 has powered up and performed a self-test.
The external master should always wait for this interrupt
before trying to read or write to the SX2, unless an external
EEPROM with a valid descriptor is present. If an external
EEPROM with a valid descriptor is present, the ENUMOK
interrupt will occur instead of the READY interrupt after power
up. A READY interrupt will also occur if the SX2 is awakened
from a low-power mode via the WAKEUP pin. This READY
interrupt indicates that the SX2 is ready for commands or data.
3.5.2
3.5.3
3.4.3
Qualify with READY Pin on Register Reads
Although it is true that all interrupts will be buffered once a
command read request has been initiated, in very rare conditions, there might be a situation when there is a pending
interrupt already, when a read request is initiated by the
external master. In this case it is the interrupt status byte that
will be output when the external master asserts the SLRD. So,
a condition exists where the Interrupt Status Data Byte can be
mistaken for the result of a command register read request. In
order to get around this possible race condition, the first thing
that the external master must do on getting an interrupt from
the SX2 is check the status of the READY pin. If the READY
is low at the time the INT# was asserted, the data that will be
output when the external master strobes the SLRD is the
interrupt status byte (not the actual data requested). If the
READY pin is high at the time when the interrupt is asserted,
the data output on strobing the SLRD is the actual data byte
requested by the external master. So it is important that the
state of the READY pin be checked at the time the INT# is
asserted to ascertain the cause of the interrupt.
3.5
Resets and Wakeup
3.5.1
Reset
USB Reset
Wakeup
The SX2 exits its low-power state when one of the following
events occur:
• USB bus signals a resume. The SX2 will assert a BUSACTIVITY interrupt.
• The external master asserts the WAKEUP pin. The SX2 will
assert a READY interrupt[3].
3.6
Endpoint RAM
3.6.1
Size
• Control endpoint: 64 Bytes: 1 × 64 bytes (Endpoint 0).
• FIFO Endpoints: 4096 Bytes: 8 × 512 bytes (Endpoint 2, 4,
6, 8).
3.6.2
Organization
• EP0–Bidirectional Endpoint 0, 64-byte buffer.
• EP2, 4, 6, 8–Eight 512-byte buffers, bulk, interrupt, or isochronous. EP2 and EP6 can be either double-, triple-, or
quad-buffered. EP4 and EP8 can only be double-buffered.
For high-speed endpoint configuration options, see
Figure 3-1.
An input pin (RESET#) resets the chip. The internal PLL stabilizes after V CC has reached 3.3V. Typically, an external RC
network (R = 100 KOhms, C = 0.1 µF) is used to provide the
Note:
3. If the descriptor loaded is set for remote wakeup enabled and the host does a set feature remote wakeup enabled, then the SX2 logic will perform RESUME
signalling after a WAKEUP interrupt.
Document #: 38-08013 Rev. *H
Page 4 of 42
CY7C68001
3.6.3
Endpoint Configurations (High-speed Mode)
E P 0 IN & O U T
64
64
64
64
64
64
1024
1024
1024
1024
G ro u p C
G ro u p A
512
512
512
512
1 024
EP2
EP2
EP2
512
512
512
512
EP4
512
EP2
1 024
512
512
EP2
512
EP2
G ro u p B
512
EP6
512
EP6
512
1024
1 024
512
512
EP6
512
EP6
512
512
EP8
1 024
512
1024
512
EP8
512
512
1024
EP8
512
512
Figure 3-1. Endpoint Configuration
Endpoint 0 is the same for every configuration as it serves as
the CONTROL endpoint. For Endpoints 2, 4, 6, and 8, refer to
Figure 3-1. Endpoints 2, 4, 6, and 8 may be configured by
choosing either:
• One configuration from Group A and one from Group B
• One configuration from Group C.
Some example endpoint configurations are as follows.
• EP2: 1024 bytes double-buffered, EP6: 512 bytes quadbuffered.
• EP2: 512 bytes double-buffered, EP4: 512 bytes doublebuffered, EP6: 512 bytes double-buffered, EP8: 512 bytes
double buffered.
• EP2: 1024 bytes quad-buffered.
3.6.4
Default Endpoint Memory Configuration
At power-on-reset, the endpoint memories are configured as
follows:
are controlled by FIFO control signals (IFCLK, CS#, SLRD,
SLWR, SLOE, PKTEND, and FIFOADR[2:0]).
The SX2 command interface is used to set up the SX2, read
status, load descriptors, and access Endpoint 0. The
command interface has its own READY signal for gating
writes, and an INT# signal to indicate that the SX2 has data to
be read, or that an interrupt event has occurred. The command
interface uses the same control signals (IFCLK, CS#, SLRD,
SLWR, SLOE, and FIFOADR[2:0]) as the FIFO interface,
except for PKTEND.
3.7.2
Control Signals
3.7.2.1 FIFOADDR Lines
The SX2 has three address pins that are used to select either
the FIFOs or the command interface. The addresses correspond to the following table.
Table 3-3. FIFO Address Lines Setting
• EP2: Bulk OUT, 512 bytes/packet, 2x buffered.
Address/Selection
• EP4: Bulk OUT, 512 bytes/packet, 2x buffered.
FIFO2
0
0
0
• EP6: Bulk IN, 512 bytes/packet, 2x buffered.
FIFO4
0
0
1
• EP8: Bulk IN, 512 bytes/packet, 2x buffered.
FIFO6
0
1
0
FIFO8
0
1
1
3.7
External Interface
FIFOADR2 FIFOADR1 FIFOADR0
COMMAND
1
0
0
The SX2 presents two interfaces to the external master.
RESERVED
1
0
1
1. A FIFO interface through which EP2, 4, 6, and 8 data flows.
RESERVED
1
1
0
2. A command interface, which is used to set up the SX2, read
status, load descriptors, and access Endpoint 0.
RESERVED
1
1
1
3.7.1
Architecture
The SX2 slave FIFO architecture has eight 512-byte blocks in
the endpoint RAM that directly serve as FIFO memories and
Document #: 38-08013 Rev. *H
The SX2 accepts either an internally derived clock (30 or 48
MHz) or externally supplied clock (IFCLK, 5–50 MHz), and
SLRD, SLWR, SLOE, PKTEND, CS#, FIFOADR[2:0] signals
from an external master. The interface can be selected for 8-
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CY7C68001
or 16- bit operation by an internal configuration bit, and an
Output Enable signal SLOE enables the data bus driver of the
selected width. The external master must ensure that the
output enable signal is inactive when writing data to the SX2.
The interface can operate either asynchronously where the
SLRD and SLWR signals act directly as strobes, or synchronously where the SLRD and SLWR act as clock qualifiers. The
optional CS# signal will tristate the data bus and ignore SLRD,
SLWR, PKTEND.
The external master reads from OUT endpoints and writes to
IN endpoints, and reads from or writes to the command
interface.
• Asynchronous–SLRD, SLWR, and PKTEND pins are
strobes.
• Synchronous–SLRD, SLWR, and PKTEND pins are enables for the IFCLK clock pin.
An external master accesses the FIFOs through the data bus,
FD [15:0]. This bus can be either 8- or 16-bits wide; the width
is selected via the WORDWIDE bit in the EPxPKTLENH/L
registers. The data bus is bidirectional, with its output drivers
controlled by the SLOE pin. The FIFOADR[2:0] pins select
which of the four FIFOs is connected to the FD [15:0] bus, or
if the command interface is selected.
3.7.2.2 Read: SLOE and SLRD
3.7.5
In synchronous mode, the FIFO pointer is incremented on
each rising edge of IFCLK while SLRD is asserted. In
asynchronous mode, the FIFO pointer is incremented on each
asserted-to-deasserted transition of SLRD.
The FIFO flags are FLAGA, FLAGB, FLAGC, and FLAGD.
These FLAGx pins report the status of the FIFO selected by
the FIFOADR[2:0] pins. At reset, these pins are configured to
report the status of the following:
FIFO Flag Pins Configuration
SLOE is a data bus driver enable. When SLOE is asserted, the
data bus is driven by the SX2.
• FLAGA reports the status of the programmable flag.
3.7.2.3 Write: SLWR
• FLAGC reports the status of the empty flag.
• FLAGB reports the status of the full flag.
• FLAGD defaults to the CS# function.
In synchronous mode, data on the FD bus is written to the
FIFO (and the FIFO pointer is incremented) on each rising
edge of IFCLK while SLWR is asserted. In asynchronous
mode, data on the FD bus is written to the FIFO (and the FIFO
pointer is incremented) on each asserted-to-deasserted
transition of SLWR.
The FIFO flags can either be indexed or fixed. Fixed flags
report the status of a particular FIFO regardless of the value
on the FIFOADR [2:0] pins. Indexed flags report the status of
the FIFO selected by the FIFOADR [2:0]pins.[4]
3.7.2.4 PKTEND
3.7.6
PKTEND commits the current buffer to USB. To send a short
IN packet (one which has not been filled to max packet size
determined by the value of PL[X:0] in EPxPKTLENH/L), the
external master strobes the PKTEND pin.
By default, FLAGA is the Programmable Flag (PF) for the
endpoint being pointed to by the FIFOADR[2:0] pins. For EP2
and EP4, the default endpoint configuration is BULK, OUT,
512, 2x, and the PF pin asserts when the entire FIFO has
greater than/equal to 512 bytes. For EP6 and EP8, the default
endpoint configuration is BULK, IN, 512, 2x, and the PF pin
asserts when the entire FIFO has less than/equal to 512 bytes.
In other words, EP6/8 report a half-empty state, and EP2/4
report a half-full state.
All these interface signals have a default polarity of low. In
order to change the polarity of PKTEND pin, the master may
write to the POLAR register anytime. In order to switch the
polarity of the SLWR/SLRD/SLOE, the master must set the
appropriate bits 2, 3 and 4 respectively in the FIFOPINPOLAR
register located at XDATA space 0xE609. Please note that the
SX2 powers up with the polarities set to low. Section 7.3
provides further information on how to access this register
located at XDATA space.
3.7.3
IFCLK
The IFCLK pin can be configured to be either an input (default)
or an output interface clock. Bits IFCONFIG[7:4] define the
behavior of the interface clock. To use the SX2’s internallyderived 30- or 48-MHz clock, set IFCONFIG.7 to 1 and set
IFCONFIG.6 to 0 (30 MHz) or to 1 (48 MHz). To use an externally supplied clock, set IFCONFIG.7=0 and drive the IFCLK
pin (5 MHz – 50 MHz). The input or output IFCLK signal can
be inverted by setting IFCONFIG.4=1.
3.7.4
FIFO Access
An external master can access the slave FIFOs either
asynchronously or synchronously:
3.7.7
Default FIFO Programmable Flag Set-up
FIFO Programmable Flag (PF) Set-up
Each FIFO’s programmable-level flag (PF) asserts when the
FIFO reaches a user-defined fullness threshold. That
threshold is configured as follows:
1. For OUT packets: The threshold is stored in PFC12:0. The
PF is asserted when the number of bytes in the entire FIFO
is less than/equal to (DECIS = 0) or greater than/equal to
(DECIS = 1) the threshold.
2. For IN packets, with PKTSTAT = 1: The threshold is stored
in PFC9:0. The PF is asserted when the number of bytes
written into the current packet in the FIFO is less than/equal
to (DECIS = 0) or greater than/equal to (DECIS = 1) the
threshold.
3. For IN packets, with PKTSTAT = 0: The threshold is stored
in two parts: PKTS2:0 holds the number of committed packets, and PFC9:0 holds the number of bytes in the current
packet. The PF is asserted when the FIFO is at or less full
than (DECIS = 0), or at or more full than (DECIS = 1), the
threshold.
Note:
4. In indexed mode, the value of the FLAGx pins is indeterminate except when addressing a FIFO (FIFOADR[2:0]={000,001,010,011}).
Document #: 38-08013 Rev. *H
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CY7C68001
3.7.8
• The first bit signifies an address transfer.
Command Protocol
An address of [1 0 0] on FIFOADR [2:0] will select the
command interface. The command interface is used to write
to and read from the SX2 registers and the Endpoint 0 buffer,
as well as the descriptor RAM. Command read and write transactions occur over FD[7:0] only. Each byte written to the SX2
is either an address or a data byte, as determined by bit7. If
bit7 = 1, then the byte is considered an address byte. If bit7 =
0, then the byte is considered a data byte. If bit7 = 1, then bit6
determines whether the address byte is a read request or a
write request. If bit6 = 1, then the byte is considered a read
request. If bit6 = 0 then the byte is considered a write request.
Bits [5:0] hold the register address of the request. The format
of the command address byte is shown in Table 3-4.
• The second bit signifies that this is a write command.
• The next six bits represent the register address (000001
binary = 0x01 hex).
Once the byte has been received the SX2 pulls the READY
pin low to inform the external master not to send any more
information. When the SX2 is ready to receive the next byte,
the SX2 pulls the READY pin high again. This next byte, the
upper nibble of the data byte, is written to the SX2 as follows.
Table 3-8. Command Data Write Byte One
Address/
Data#
Don’t
Care
Don’t
Care
Don’t
Care
D7
D6
D5
D4
0
X
X
X
1
0
1
1
Table 3-4. Command Address Byte
• The first bit signifies that this is a data transfer.
Address/
Data#
Read/
Write#
A5
A4
A3
A2
A1
A0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Each Write request is followed by two or more data bytes. If
another address byte is received before both data bytes are
received, the SX2 ignores the first address and any incomplete
data transfers. The format for the data bytes is shown in
Table 3-5 and Table 3-6. Some registers take a series of bytes.
Each byte is transferred using the same protocol.
Table 3-5. Command Data Byte One
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
X
X
X
D7
D6
D5
D4
• The next three are don’t care bits.
• The next four bits hold the upper nibble of the transferred
byte.
Once the byte has been received the SX2 pulls the READY
pin low to inform the external master not to send any more
information. When the SX2 is ready to receive the next byte,
the SX2 pulls the READY pin high again. This next byte, the
lower nibble of the data byte is written to the SX2.
Table 3-9. Command Data Write Byte Two
Address/
Data#
Don’t
Care
Don’t
Care
Don’t
Care
D3
D2
D1
D0
0
X
X
X
0
0
0
0
Table 3-6. Command Data Byte Two
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
X
X
X
D3
D2
D1
D0
The first command data byte contains the upper nibble of data,
and the second command byte contains the lower nibble of
data.
3.7.8.1 Write Request Example
Prior to writing to a register, two conditions must be met:
FIFOADR[2:0] must hold [1 0 0], and the Ready line must be
HIGH. The external master should not initiate a command if
the READY pin is not in a HIgh state.
Example: to write the byte <10110000> into the IFCONFIG
register (0x01), first send a command address byte as follows.
Table 3-7. Command Address Write Byte
Address/
Data#
Read/
Write#
A5
A4
A3
A2
A1
A0
1
0
0
0
0
0
0
1
At this point the entire byte <10110000> has been transferred
to register 0x01 and the write sequence is complete.
3.7.8.2 Read Request Example
The Read cycle is simpler than the write cycle. The Read cycle
consists of a read request from the external master to the SX2.
For example, to read the contents of register 0x01, a command
address byte is written to the SX2 as follows.
Table 3-10. Command Address Read Byte
Address/ Read/
Data#
Write#
1
1
A5
A4
A3
A2
A1
A0
0
0
0
0
0
1
When the data is ready to be read, the SX2 asserts the INT#
pin to tell the external master that the data it requested is
waiting on FD[7:0].[5]
Note:
5. An important note: Once the SX2 receives a Read request, the SX2 allocates the interrupt line solely for the read request. If one of the six interrupt sources
described in Section 3.4 is asserted, the SX2 will buffer that interrupt until the read request completes.
Document #: 38-08013 Rev. *H
Page 7 of 42
CY7C68001
4.0
Enumeration
The SX2 has two modes of enumeration. The first mode is
automatic through EEPROM boot load, as described in
Section 3.3. The second method is a manual load of the
descriptor or VID, PID, and DID as described below.
4.1
Standard Enumeration
The SX2 has 500 bytes of descriptor RAM into which the
external master may write its descriptor. The descriptor RAM
is accessed through register 0x30. To load a descriptor, the
external master does the following:
• Initiate a Write Request to register 0x30.
• Write two bytes (four command data transfers) that define
the length of the entire descriptor about to be transferred.
The LSB is written first, followed by the MSB.[6]
• Write the descriptor, one byte at a time until complete.[6]
Note: the register address is only written once.
After the entire descriptor has been transferred, the SX2 will
float the pull-up resistor connected to D+, and parse through
the descriptor to locate the individual descriptors. After the
SX2 has parsed the entire descriptor, the SX2 will connect the
pull-up resistor and enumerate automatically. When enumeration is complete, the SX2 will notify the external master with
an ENUMOK interrupt.
The format and order of the descriptor should be as follows
(see Section 12.0 for an example):
• Device.
• Device qualifier.
• High-speed configuration, high-speed interface, highspeed endpoints.
• Full-speed configuration, full-speed interface, full-speed
endpoints.
• String.
The SX2 can be set to run in full speed only mode. To force full
speed only enumeration write a 0x02 to the unindexed register
CT1 at address 0xE6FB before downloading the descriptors.
This disables the chirp mechanism forcing the SX2 to come up
in full speed only mode after the descriptors are loaded. The
CT1 register can be accessed using the unindexed register
mechanism. Examples of writing to unindexed registers are
shown in Section 5.1. Each write consists of a command write
with the target register followed by the write of the upper nibble
of the value followed by the write of the lower nibble of the
value.
4.2
Default Enumeration
The external master may simply load a VID, PID, and DID and
use the default descriptor built into the SX2. To use the default
descriptor, the descriptor length described above must equal
6. After the external master has written the length, the VID,
PID, and DID must be written LSB, then MSB. For example, if
the VID, PID, and DID are 0x04B4, 0x1002, and 0x0001
respectively, then the external master does the following:
• Initiates a Write Request to register 0x30.
• Writes two bytes (four command data transfers) that define
the length of the entire descriptor about to be transferred.
In this case, the length is always six.
• Writes the VID, PID, and DID bytes: 0xB4, 0x04, 0x02, 0x10,
0x01, 0x00 (in nibble format per the command protocol).
The default descriptor is listed in Section 12.0. The default
descriptor can be used as a starting point for a custom
descriptor.
5.0
Endpoint 0
The SX2 will automatically respond to USB chapter 9 requests
without any external master intervention. If the SX2 receives
a request to which it cannot respond automatically, the SX2
will notify the external master. The external master then has
the choice of responding to the request or stalling.
After the SX2 receives a set-up packet to which it cannot
respond automatically, the SX2 will assert a SETUP interrupt.
After the external master reads the Interrupt Status Byte to
determine that the interrupt source was the SETUP interrupt,
it can initiate a read request to the SETUP register, 0x32.
When the SX2 sees a read request for the SETUP register, it
will present the first byte of set-up data to the external master.
Each additional read request will present the next byte of setup data, until all eight bytes have been read.
The external master can stall this request at this or any other
time. To stall a request, the external master initiates a write
request for the SETUP register, 0x32, and writes any non-zero
value to the register.
If this set-up request has a data phase, the SX2 will then
interrupt the external master with an EP0BUF interrupt when
the buffer becomes available. The SX2 determines the
direction of the set-up request and interrupts when either:
• IN: the Endpoint 0 buffer becomes available to write to, or
• OUT: the Endpoint 0 buffer receives a packet from the USB
host.
For an IN set-up transaction, the external master can write up
to 64 bytes at a time for the data phase. The steps to write a
packet are as follows:
1. Wait for an EP0BUF interrupt, indicating that the buffer is
available.
2. Initiate a write request for register 0x31.
3. Write one data byte.
4. Repeat steps 2 and 3 until either all the data or 64 bytes
have been written, whichever is less.
5. Write the number of bytes in this packet to the byte count
register, 0x33.
To send more than 64 bytes, the process is repeated. The SX2
internally stores the length of the data phase that was specified
in the wLength field (bytes 6,7) of the set-up packet. To send
less than the requested amount of data, the external master
writes a packet that is less than 64 bytes, or if a multiple of 64,
the external master follows the data with a zero-length packet.
When the SX2 sees a short or zero-length packet, it will
complete the set-up transfer by automatically completing the
handshake phase. The SX2 will not allow more data than the
wLength field specified in the set-up packet. Note: the
Note:
6. These and all other data bytes must conform to the command protocol.
Document #: 38-08013 Rev. *H
Page 8 of 42
CY7C68001
PKTEND pin does not apply to Endpoint 0. The only way to
send a short or zero length packet is by writing to the byte
count register with the appropriate value.
For an OUT set-up transaction, the external master can read
each packet received from the USB host during the data
phase. The steps to read a packet are as follows:
1. Wait for an EP0BUF interrupt, indicating that a packet was
received from the USB host into the buffer.
2. Initiate a read request for the byte count register, 0x33. This
indicates the amount of data received from the host.
3. Initiate a read request for register 0x31.
5. Repeat steps 3 and 4 until the number of bytes specified in
the byte count register has been read.
To receive more than 64 bytes, the process is repeated. The
SX2 internally stores the length of the data phase that was
specified in the wLength field of the set-up packet (bytes 6,7).
When the SX2 sees that the specified number of bytes have
been received, it will complete the set-up transfer by automatically completing the handshake phase. If the external master
does not wish to receive the entire transfer, it can stall the
transfer.
If the SX2 receives another set-up packet before the current
transfer has completed, it will interrupt the external master with
another SETUP interrupt. If the SX2 receives a set-up packet
with no data phase, the external master can accept the packet
and complete the handshake phase by writing zero to the byte
count register.
The SX2 automatically responds to all USB standard requests
covered in chapter 9 of the USB 2.0 specification except the
Set/Clear Feature Endpoint requests. When the host issues a
Set Feature or a Clear feature request, the SX2 will trigger a
SETUP interrupt to the external master. The USB spec
requires that the device respond to the Set endpoint feature
request by doing the following:
• Set the STALL condition on that endpoint.
The USB spec requires that the device respond to the Clear
endpoint feature request by doing the following:
• Reset the Data Toggle for that endpoint
• Clear the STALL condition of that endpoint.
The register that is used to reset the data toggle TOGCTL
(located at XDATA location 0xE683) is not an index register
that can be addressed by the command protocol presented in
Section 3.7.8. The following section provides further information on this register bits and how to reset the data toggle
accordingly using a different set of command protocol
sequence.
0xE683
TOGCTL
6
5
Bit Name
Q
S
R
Read/Write
R
W
W
Default
0
0
1
1
Document #: 38-08013 Rev. *H
4
After selecting the desired endpoint by writing the endpoint
select bits (IO and EP3:0), set S=1 to set the data toggle to
DATA1. The endpoint selection bits should not be changed
while this bit is written.
Bit 5: R, Set Data Toggle to DATA0
Bit 4: IO, Select IN or OUT Endpoint
Set this bit to select an endpoint direction prior to setting its R
or S bit. IO=0 selects an OUT endpoint, IO = 1 selects an IN
endpoint.
Bit 3-0: EP3:0, Select Endpoint
Set these bits to select an endpoint prior to setting its R or S
bit. Valid values are 0, 1, 2, , 6, and 8.
A two-step process is employed to clear an endpoint data
toggle bit to 0. First, write to the TOGCTL register with an
endpoint address (EP3:EP0) plus a direction bit (IO). Keeping
the endpoint and direction bits the same, write a “1” to the R
(reset) bit. For example, to clear the data toggle for EP6
configured as an “IN” endpoint, write the following values
sequentially to TOGCTL:
00010110b
00110110b
Following is the sequence of events that the master should
perform to set this register to 0x16:
1. Send Low Byte of the Register (0x83)
a. Command address write of address 0x3A
b. Command data write of upper nibble of the Low Byte of
Register Address (0x08)
c. Command data write of lower nibble of the Low Byte of
Register Address (0x03)
2. Send High Byte of the Register (0xE6)
a. Command address write of address 0x3B
b. Command data write of upper nibble of the High Byte of
Register Address (0x0E)
c. Command data write of lower nibble of the High Byte of
Register Address (0x06)
3. Send the actual value to write to the register Register (in
this case 0x16)
b. Command data write of upper nibble of the register value
(0x01)
Following is the bit definition of the TOGCTL register:
7
Bit 6: S, Set Data Toggle to DATA1
a. Command address write of address0x3C
Resetting Data Toggle
Bit #
Q=0 indicates DATA0 and Q=1 indicates DATA1, for the
endpoint selected by the I/O and EP3:0 bits. Write the endpoint
select bits (IO and EP3:0), before reading this value.
Set R=1 to set the data toggle to DATA0. The endpoint
selection bits should not be changed while this bit is written.
4. Read one byte.
5.1
Bit 7: Q, Data Toggle Value
3
2
1
0
I/O
EP3
EP2
EP1
EP0
R/W
R/W
R/W
R/W
R/W
0
0
1
0
c. Command data write of lower nibble of the register value
(0x06)
The same command sequence needs to be followed to set
TOGCTL register to 0x36. The same command protocol
sequence can be used to reset the data toggle for the other
endpoints.
Page 9 of 42
CY7C68001
In order to read the status of this register, the external master
must do the following sequence of events:
1. Send Low Byte of the Register (0x83)
a. Command address write of address 0x3B
a. Command address write of 0x3A
b. Command data write of upper nibble of the High Byte of
Register Address (0x0E)
b. Command data write of upper nibble of the Low Byte of
Register Address (0x08)
c. Command data write of lower nibble of the High Byte of
Register Address (0x06)
c. Command data write of lower nibble of the Low Byte of
Register Address (0x03)
6.0
6.1
2. Send High Byte of the Register (0xE6)
3. Get the actual value from the TOGCTL register (0x16)
a. Command address READ of 0x3C
Pin Assignments
56-pin SSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
FD13
FD12
FD14
FD11
FD15
FD10
GND
FD9
NC
FD8
VCC
*WAKEUP
GND
VCC
*SLRD
RESET#
*SLWR
GND
AVCC
*FLAGD/CS#
XTALOUT
*PKTEND
XTALIN
FIFOADR1
AGND
FIFOADR0
VCC
FIFOADR2
DPLUS
*SLOE
DMINUS
INT#
GND
READY
VCC
VCC
GND
*FLAGC
*IFCLK
*FLAGB
RESERVED
*FLAGA
SCL
GND
CY7C68001
SDA
56-pin SSOP VCC
VCC
GND
FD0
FD7
FD1
FD6
FD2
FD5
FD3
FD4
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
Figure 6-1. CY7C68001 56-pin SSOP Pin Assignment[7]
Note:
7. A * denotes programmable polarity.
Document #: 38-08013 Rev. *H
Page 10 of 42
CY7C68001
6.2
56-pin QFN
*
GND
VCC
NC
GND
FD15
FD14
FD13
FD12
FD11
FD10
FD9
FD8
W A KEUP
VCC
56
55
54
53
52
51
50
49
48
47
46
45
44
43
* S LRD
1
42
RE SE T#
* S LW R
2
41
GND
A VCC
3
40
* FLAGD/CS#
XTALOUT
4
39
* PK TE ND
XTALIN
5
38
FIFOADR1
AGND
6
37
FIFOADR0
VCC
7
36
FIFOADR2
DPLUS
8
35
* SLOE
DMINUS
9
34
INT#
GND
10
33
RE ADY
VCC
11
32
V CC
GND
12
31
* FLAGC
* IFCLK
13
30
* FLAGB
RE SERV ED
14
29
* FLAGA
CY7C68001
56-pin QFN
15
16
17
18
19
20
21
22
23
24
25
26
27
28
S CL
S DA
V CC
FD0
FD1
FD2
FD3
FD4
FD5
FD6
FD7
GND
V CC
GND
Figure 6-2. CY7C68001 56-pin QFN Assignment[7]
Document #: 38-08013 Rev. *H
Page 11 of 42
CY7C68001
6.3
CY7C68001 Pin Definitions
Table 6-1. SX2 Pin Definitions
QFN SSOP
Pin
Pin
Name
Type
Default
AVCC
Power
N/A
Analog VCC. This signal provides power to the analog section of the chip.
13
AGND
Power
N/A
Analog Ground. Connect to ground with as short a path as possible.
16
DMINUS
I/O/Z
Z
USB D– Signal. Connect to the USB D– signal.
USB D+ Signal. Connect to the USB D+ signal.
3
10
6
9
Description
8
15
DPLUS
I/O/Z
Z
42
49
RESET#
Input
N/A
Active LOW Reset. Resets the entire chip. This pin is normally tied to VCC
through a 100K resistor, and to GND through a 0.1-µF capacitor.
5
12
XTALIN
Input
N/A
Crystal Input. Connect this signal to a 24-MHz parallel-resonant, fundamental
mode crystal and 20-pF capacitor to GND. It is also correct to drive XTALIN with
an external 24-MHz square wave derived from another clock source.
4
11
XTALOUT
Output
N/A
Crystal Output. Connect this signal to a 24-MHz parallel-resonant, fundamental
mode crystal and 20-pF capacitor to GND. If an external clock is used to drive
XTALIN, leave this pin open.
54
5
NC
Output
O
No Connect. This pin must be left unconnected.
33
40
READY
Output
L
READY is an output-only ready that gates external command reads and writes.
Active High.
34
41
INT#
Output
H
INT# is an output-only external interrupt signal. Active Low.
35
42
SLOE
Input
I
SLOE is an input-only output enable with programmable polarity (POLAR.4) for
the slave FIFOs connected to FD[7:0] or FD[15:0].
36
43
FIFOADR2
Input
I
FIFOADR2 is an input-only address select for the slave FIFOs connected to
FD[7:0] or FD[15:0].
37
44
FIFOADR0
Input
I
FIFOADR0 is an input-only address select for the slave FIFOs connected to
FD[7:0] or FD[15:0].
38
45
FIFOADR1
Input
I
FIFOADR1 is an input-only address select for the slave FIFOs connected to
FD[7:0] or FD[15:0].
39
46
PKTEND
Input
I
PKTEND is an input-only packet end with programmable polarity (POLAR.5) for
the slave FIFOs connected to FD[7:0] or FD[15:0].
40
47
FLAGD/C
CS#:I
S#
FLAGD:O
I
FLAGD is a programmable slave-FIFO output status flag signal. CS# is a master
chip select (default).
18
25
FD[0]
I/O/Z
I
FD[0] is the bidirectional FIFO/Command data bus.
19
26
FD[1]
I/O/Z
I
FD[1] is the bidirectional FIFO/Command data bus.
20
27
FD[2]
I/O/Z
I
FD[2] is the bidirectional FIFO/Command data bus.
21
28
FD[3]
I/O/Z
I
FD[3] is the bidirectional FIFO/Command data bus.
22
29
FD[4]
I/O/Z
I
FD[4] is the bidirectional FIFO/Command data bus.
23
30
FD[5]
I/O/Z
I
FD[5] is the bidirectional FIFO/Command data bus.
24
31
FD[6]
I/O/Z
I
FD[6] is the bidirectional FIFO/Command data bus.
25
32
FD[7]
I/O/Z
I
FD[7] is the bidirectional FIFO/Command data bus.
45
52
FD[8]
I/O/Z
I
FD[8] is the bidirectional FIFO data bus.
46
53
FD[9]
I/O/Z
I
FD[9] is the bidirectional FIFO data bus.
47
54
FD[10]
I/O/Z
I
FD[10] is the bidirectional FIFO data bus.
48
55
FD[11]
I/O/Z
I
FD[11] is the bidirectional FIFO data bus.
49
56
FD[12]
I/O/Z
I
FD[12] is the bidirectional FIFO data bus.
50
1
FD[13]
I/O/Z
I
FD[13] is the bidirectional FIFO data bus.
51
2
FD[14]
I/O/Z
I
FD[14] is the bidirectional FIFO data bus.
52
3
FD[15]
I/O/Z
I
FD[15] is the bidirectional FIFO data bus.
Document #: 38-08013 Rev. *H
Page 12 of 42
CY7C68001
Table 6-1. SX2 Pin Definitions (continued)
QFN SSOP
Pin
Pin
Name
Type
Default
Description
1
8
SLRD
Input
N/A
SLRD is the input-only read strobe with programmable polarity (POLAR.3) for the
slave FIFOs connected to FD[7:0] or FD[15:0].
2
9
SLWR
Input
N/A
SLWR is the input-only write strobe with programmable polarity (POLAR.2) for
the slave FIFOs connected to FD[7:0] or FD[15:0].
29
36
FLAGA
Output
H
FLAGA is a programmable slave-FIFO output status flag signal.
Defaults to PF for the FIFO selected by the FIFOADR[2:0] pins.
30
37
FLAGB
Output
H
FLAGB is a programmable slave-FIFO output status flag signal.
Defaults to FULL for the FIFO selected by the FIFOADR[2:0] pins.
31
38
FLAGC
Output
H
FLAGC is a programmable slave-FIFO output status flag signal.
Defaults to EMPTY for the FIFO selected by the FIFOADR[2:0] pins.
13
20
IFCLK
I/O/Z
Z
Interface Clock, used for synchronously clocking data into or out of the slave
FIFOs. IFCLK also serves as a timing reference for all slave FIFO control signals.
When using the internal clock reference (IFCONFIG.7=1) the IFCLK pin can be
configured to output 30/48 MHz by setting bits IFCONFIG.5 and IFCONFIG.6.
IFCLK may be inverted by setting the bit IFCONFIG.4=1. Programmable polarity.
14
21
Reserved
Input
N/A
Reserved. Must be connected to ground.
44
51
WAKEUP
Input
N/A
USB Wakeup. If the SX2 is in suspend, asserting this pin starts up the oscillator
and interrupts the SX2 to allow it to exit the suspend mode. During normal
operation, holding WAKEUP asserted inhibits the SX2 chip from suspending. This
pin has programmable polarity (POLAR.7).
15
22
SCL
OD
Z
I2C Clock. Connect to VCC with a 2.2K-10 KOhms resistor, even if no I2C
EEPROM is attached.
16
23
SDA
OD
Z
I2C Data. Connect to VCC with a 2.2K-10 KOhms resistor, even if no I2C EEPROM
is attached.
55
6
VCC
Power
N/A
VCC. Connect to 3.3V power source.
7
14
VCC
Power
N/A
VCC. Connect to 3.3V power source.
11
18
VCC
Power
N/A
VCC. Connect to 3.3V power source.
17
24
VCC
Power
N/A
VCC. Connect to 3.3V power source.
27
34
VCC
Power
N/A
VCC. Connect to 3.3V power source.
32
39
VCC
Power
N/A
VCC. Connect to 3.3V power source.
43
50
VCC
Power
N/A
VCC. Connect to 3.3V power source.
53
4
GND
Ground
N/A
Connect to ground.
56
7
GND
Ground
N/A
Connect to ground.
10
17
GND
Ground
N/A
Connect to ground.
12
19
GND
Ground
N/A
Connect to ground.
26
33
GND
Ground
N/A
Connect to ground.
28
35
GND
Ground
N/A
Connect to ground.
41
48
GND
Ground
N/A
Connect to ground.
Document #: 38-08013 Rev. *H
Page 13 of 42
CY7C68001
7.0
Register Summary
Table 7-1. SX2 Register Summary
Hex Size Name
Description
General Configuration
01
1 IFCONFIG
Interface Configuration
02
1 FLAGSAB
FIFO FLAGA and FLAGB Assignments
03
1 FLAGSCD
FIFO FLAGC and FLAGD Assignments
04
1 POLAR
FIFO polarities
05
1 REVID
Chip Revision
Endpoint Configuration[8]
06
1 EP2CFG
Endpoint 2 Configuration
07
1 EP4CFG
Endpoint 4 Configuration
08
1 EP6CFG
Endpoint 6 Configuration
09
1 EP8CFG
Endpoint 8 Configuration
0A
1 EP2PKTLENH Endpoint 2 Packet Length H
D7
D6
D4
D3
IFCLKPOL
FLAGB0
ASYNC
FLAGA3
D2
D1
STANDBY FLAGD/CS#
FLAGA2
FLAGA1
D0
DISCON
FLAGA0
Default
Access
11001001 bbbbbbbb
00000000 bbbbbbbb
FLAGD3
FLAGD2
FLAGD1
FLAGD0
FLAGC3
FLAGC2
FLAGC1
FLAGC0
WUPOL
Major
0
Major
PKTEND
Major
SLOE
Major
SLRD
minor
SLWR
minor
EF
minor
FF
minor
00000000
xxxxxxxx
VALID
VALID
VALID
VALID
INFM1
dir
dir
dir
dir
OEP1
TYPE1
TYPE1
TYPE1
TYPE1
ZEROLEN
STALL
STALL
STALL
STALL
PL10
BUF1
0
BUF1
0
PL9
BUF0
0
BUF0
0
PL8
10100010 bbbbbbbb
10100000 bbbbrbrr
11100010 bbbbbbbb
11100000 bbbbrbrr
00110010 bbbbbbbb
PL2
0
PL1
PL9
PL0
PL8
00000000 bbbbbbbb
00110010 bbbbbbbb
PL2
PL10
PL1
PL9
PL0
PL8
00000000 bbbbbbbb
00110010 bbbbbbbb
PL2
0
PL1
PL9
PL0
PL8
00000000 bbbbbbbb
00110010 bbbbbbbb
PL2
0
PL1
PFC9
PL0
PFC8
00000000 bbbbbbbb
10001000 bbbbbbbb
PFC2
0
PFC1
0
PFC0
PFC8
00000000 bbbbbbbb
10001000 bbbbbbbb
PFC2
0
PFC1
PFC9
PFC0
PFC8
00000000 bbbbbbbb
00001000 bbbbbbbb
PFC2
0
PFC1
0
PFC0
PFC8
00000000 bbbbbbbb
00001000 bbbbbbbb
PFC2
0
0
0
0
PFC1
INPPF1
INPPF1
INPPF1
INPPF1
PFC0
INPPF0
INPPF0
INPPF0
INPPF0
00000000
00000001
00000001
00000001
00000001
bbbbbbbb
bbbbbbbb
bbbbbbbb
bbbbbbbb
bbbbbbbb
00100010
01100110
rrrrrrrr
rrrrrrrr
0B
0C
1 EP2PKTLENL
1 EP4PKTLENH
Endpoint 2 Packet Length L (IN only)
Endpoint 4 Packet Length H
PL7
INFM1
PL6
OEP1
0D
0E
1 EP4PKTLENL
1 EP6PKTLENH
Endpoint 4 Packet Length L (IN only)
Endpoint 6 Packet Length H
PL7
INFM1
PL6
OEP1
0F
10
1 EP6PKTLENL
1 EP8PKTLENH
Endpoint 6 Packet Length L (IN only)
Endpoint 8 Packet Length H
PL7
INFM1
PL6
OEP1
11
12
1 EP8PKTLENL
1 EP2PFH
Endpoint 8 Packet Length L (IN only)
EP2 Programmable Flag H
PL7
DECIS
PL6
PKTSTAT
13
14
1 EP2PFL
1 EP4PFH
EP2 Programmable Flag L
EP4 Programmable Flag H
PFC7
DECIS
PFC6
PKTSTAT
15
16
1 EP4PFL
1 EP6PFH
EP4 Programmable Flag L
EP6 Programmable Flag H
PFC7
DECIS
PFC6
PKTSTAT
17
18
1 EP6PFL
1 EP8PFH
EP6 Programmable Flag L
EP8 Programmable Flag H
PFC7
DECIS
PFC6
PKTSTAT
19
1A
1B
1C
1D
1
1
1
1
1
1E
1F
1
1
20
1
2A
2B
2C
2D
1
1
1
1
2E
1
30
500
EP8PFL
EP8 Programmable Flag L
PFC7
PFC6
EP2ISOINPKTS EP2 (if ISO) IN Packets per frame (1-3)
0
0
EP4ISOINPKTS EP4 (if ISO) IN Packets per frame (1-3)
0
0
EP6ISOINPKTS EP6 (if ISO) IN Packets per frame (1-3)
0
0
EP8ISOINPKTS EP8 (if ISO) IN Packets per frame (1-3)
0
0
FLAGS
EP24FLAGS
Endpoints 2,4 FIFO Flags
0
EP4PF
EP68FLAGS
Endpoints 6,8 FIFO Flags
0
EP8PF
INPKTEND/FLUSH[9]
INPKForce Packet End / Flush FIFOs
FIFO8
FIFO6
TEND/FLUSH
USB Configuration
USBFRAMEH USB Frame count H
0
0
USBFRAMEL USB Frame count L
FC7
FC6
MICROFRAME Microframe count, 0-7
0
0
FNADDR
USB Function address
HSGRANT
FA6
Interrupts
INTENABLE
Interrupt Enable
SETUP EP0BUF
Descriptor
DESC
Descriptor RAM
d7
d6
Endpoint 0
31 64 EP0BUF
Endpoint 0 Buffer
32 8/1 SETUP
Endpoint 0 Set-up Data / Stall
33
1 EP0BC
Endpoint 0 Byte Count
Un-Indexed Register control
3A
1
Un-Indexed Register Low Byte pointer
3B
1
Un-Indexed Register High Byte pointer
3C 1
Un-Indexed Register Data
Address Un-Indexed Registers in XDATA Space
0xE609 FIFOPINPOLAR FIFO Interface Pins Polarity
0xE683 TOGCTL
Data Toggle Control
D5
IFCLKSRC 3048MHZ IFCLKOE
FLAGB3 FLAGB2 FLAGB1
TYPE0
SIZE
TYPE0
0
TYPE0
SIZE
TYPE0
0
WORD0
WIDE
PL5
PL4
PL3
ZEROLEN
WORD0
WIDE
PL5
PL4
PL3
ZEROLEN
WORD0
WIDE
PL5
PL4
PL3
ZEROLEN
WORD0
WIDE
PL5
PL4
PL3
IN: PKTS[2] IN: PKTS[1] IN: PKTS[0]
OUT:PFC12 OUT:PFC11 OUT:PFC10
PFC5
PFC4
PFC3
0
IN: PKTS[1] IN: PKTS[0]
OUT:PFC10 OUT:PFC9
PFC5
PFC4
PFC3
IN: PKTS[2] IN: PKTS[1] IN: PKTS[0]
OUT:PFC12 OUT:PFC11 OUT:PFC10
PFC5
PFC4
PFC3
0
IN: PKTS[1] IN: PKTS[0]
OUT:PFC10 OUT:PFC9
PFC5
PFC4
PFC3
0
0
0
0
0
0
0
0
0
0
0
0
00000000 bbbbbbbb
bbbrrrbb
rrrrrrrr
EP4EF
EP8EF
EP4FF
EP8FF
0
0
EP2PF
EP6PF
EP2EF
EP6EF
EP2FF
EP6FF
FIFO4
FIFO2
EP3
EP2
EP1
EP0
00000000 wwwwwwww
0
FC5
0
FA5
0
FC4
0
FA4
0
FC3
0
FA3
FC10
FC2
MF2
FA2
FC9
FC1
MF1
FA1
FC8
FC0
MF0
FA0
xxxxxxxx
xxxxxxxx
xxxxxxxx
00000000
rrrrrrrr
rrrrrrrr
rrrrrrrr
rrrrrrrr
FLAGS
1
1
READY
11111111
bbbbbbbb
d5
d4
d3
d2
d1
d0
xxxxxxxx wwwwwwww
xxxxxxxx
xxxxxxxx
xxxxxxxx
bbbbbbbb
bbbbbbbb
bbbbbbbb
00000000
xxxxxxxx
rrbbbbbb
rbbbbbbb
ENUMOK BUSACTIVITY
d7
d7
d7
d6
d6
d6
d5
d5
d5
d4
d4
d4
d3
d3
d3
d2
d2
d2
d1
d1
d1
d0
d0
d0
a7
a7
a6
a6
a5
a5
a4
a4
a3
a3
a2
a2
a1
a1
a0
a0
d7
d6
d5
d4
d3
d2
d1
d0
0
Q
0
S
PKTEND
R
SLOE
IO
SLRD
EP3
SLWR
EP2
EF
EP1
FF
EP0
Notes:
8. Please note that the SX2 was not designed to support dynamic modification of these endpoint configuration registers. If your applications need the ability to
change endpoint configurations after the device has already enumerated with a specific configuration, please expect some delay in being able to access the
FIFOs after changing the configuration. For example, after writing to EP2PKTLENH, you must wait for at least 35 µs measured from the time the READY signal
is asserted before writing to the FIFO. This delay time varies for different registers and is not characterized, because the SX2 was not designed for this dynamic
change of endpoint configuration registers.
9. Please note that the SX2 was not designed to support dynamic modification of the INPKTEND/FLUSH register. If your applications need the ability to change
endpoint configurations or access the INPKTEND register after the device has already enumerated with a specific configuration, please expect some delay in
being able to access the FIFOs after changing this register. After writing to INPKTEND/FLUSH, you must wait for at least 85 µs measured from the time the
READY signal is asserted before writing to the FIFO. This delay time varies for different registers and is not characterized, because the SX2 was not designed
for this dynamic change of endpoint configuration registers
Document #: 38-08013 Rev. *H
Page 14 of 42
CY7C68001
7.1
IFCONFIG Register 0x01
0x01
IFCONFIG
Bit #
Bit Name
Read/Write
Default
7.1.1
7
6
5
4
3
2
1
0
IFCLKSRC
3048MHZ
IFCLKOE
IFCLKPOL
ASYNC
STANDBY
FLAGD/CS#
DISCON
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
1
0
0
1
0
0
1
When ASYNC = 1 (default), the FIFOs operate asynchronously. No clock signal input to IFCLK is required, and the
FIFO control signals function directly as read and write
strobes.
Bit 7: IFCLKSRC
This bit selects the clock source for the FIFOs. If IFCLKSRC =
0, the external clock on the IFCLK pin is selected. If
IFCLKSRC = 1 (default), an internal 30 or 48 MHz clock is
used.
7.1.2
7.1.6
This bit selects the internal FIFO clock frequency. If 3048MHZ
= 0, the internal clock frequency is 30 MHz. If 3048MHZ = 1
(default), the internal clock frequency is 48 MHz.
7.1.3
Bit 5: IFCLKOE
This bit selects if the IFCLK pin is driven. If IFCLKOE = 0
(default), the IFCLK pin is floated. If IFCLKOE = 1, the IFCLK
pin is driven.
7.1.7
7.1.4
Bit 4: IFCLKPOL
Bit 1: FLAGD/CS#
This bit controls the function of the FLAGD/CS# pin. When
FLAGD/CS# = 0 (default), the pin operates as a slave chip
select. If FLAGD/CS# = 1, the pin operates as FLAGD.
This bit controls the polarity of the IFCLK signal.
• When IFCLKPOL=0, the clock has the polarity shown in all
the timing diagrams in this data sheet (rising edge is the
activating edge).
7.1.8
Bit 0: DISCON
This bit controls whether the internal pull-up resistor
connected to D+ is pulled high or floating. When DISCON = 1
(default), the pull-up resistor is floating simulating a USB
unplug. When DISCON=0, the pull-up resistor is pulled high
signaling a USB connection.
• When IFCLKPOL=1, the clock is inverted (in some cases
may help with satisfying data set-up times).
7.1.5
Bit 2: STANDBY
This bit instructs the SX2 to enter a low-power mode. When
STANDBY=1, the SX2 will enter a low-power mode by turning
off its oscillator. The external master should write this bit after
it receives a bus activity interrupt (indicating that the host has
signaled a USB suspend condition). If SX2 is disconnected
from the USB bus, the external master can write this bit at any
time to save power. Once suspended, the SX2 is awakened
either by resumption of USB bus activity or by assertion of its
WAKEUP pin.
Bit 6: 3048MHZ
Bit 3: ASYNC
This bit controls whether the FIFO interface is synchronous or
asynchronous. When ASYNC = 0, the FIFOs operate synchronously. In synchronous mode, a clock is supplied either internally or externally on the IFCLK pin, and the FIFO control
signals function as read and write enable signals for the clock
signal.
7.2
FLAGSAB/FLAGSCD Registers 0x02/0x03
The SX2 has four FIFO flags output pins: FLAGA, FLAGB,
FLAGC, FLAGD.
0x02
FLAGSAB
Bit #
Bit Name
Read/Write
Default
7
6
5
4
3
2
1
0
FLAGB3
FLAGB2
FLAGB1
FLAGB0
FLAGA3
FLAGA2
FLAGA1
FLAGA0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
FLAGD3
FLAGD2
FLAGD1
FLAGD0
FLAGC3
FLAGC2
FLAGC1
FLAGC0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0x03
FLAGSCD
Bit #
Bit Name
Read/Write
Default
Document #: 38-08013 Rev. *H
Page 15 of 42
CY7C68001
These flags can be programmed to represent various FIFO
flags using four select bits for each FIFO. The 4-bit coding for
all four flags is the same, as shown in Table 7-2.
Table 7-2. FIFO Flag 4-bit Coding
.
FLAGx3 FLAGx2 FLAGx1 FLAGx0
0
0
0
0
Pin Function
FLAGA = PF,
FLAGB = FF,
FLAGC = EF,
FLAGD = CS#
(actual FIFO is
selected by
FIFOADR[2:0]
pins)
7.3.1
Bit 7: WUPOL
This flag sets the polarity of the WAKEUP pin. If WUPOL = 0
(default), the polarity is active LOW. If WUPOL=1, the polarity
is active HIGH.
7.3.2
Bit 5: PKTEND
This flag selects the polarity of the PKTEND pin. If PKTEND =
0 (default), the polarity is active LOW. If PKTEND = 1, the
polarity is active HIGH.
7.3.3
Bit 4: SLOE
0
0
0
1
Reserved
0
0
1
0
Reserved
This flag selects the polarity of the SLOE pin. If SLOE = 0
(default), the polarity is active LOW. If SLOE = 1, the polarity
is active HIGH. This bit can only be changed by using the
EEPROM configuration load.
0
0
1
1
Reserved
7.3.4
0
1
0
0
EP2 PF
0
1
0
1
EP4 PF
0
1
1
0
EP6 PF
0
1
1
1
EP8 PF
This flag selects the polarity of the SLRD pin. If SLRD = 0
(default), the polarity is active LOW. If SLRD = 1, the polarity
is active HIGH. This bit can only be changed by using the
EEPROM configuration load.
1
0
0
0
EP2 EF
7.3.5
1
0
0
1
EP4 EF
1
0
1
0
EP6 EF
1
0
1
1
EP8 EF
This flag selects the polarity of the SLWR pin. If SLWR = 0
(default), the polarity is active LOW. If SLWR = 1, the polarity
is active HIGH. This bit can only be changed by using the
EEPROM configuration load.
1
1
0
0
EP2 FF
1
1
0
1
EP4 FF
7.3.6
This flag selects the polarity of the EF pin (FLAGA/B/C/D). If
EF = 0 (default), the EF pin is pulled low when the FIFO is
empty. If EF = 1, the EF pin is pulled HIGH when the FIFO is
empty.
1
1
1
0
EP6 FF
1
1
1
1
EP8 FF
For the default (0000) selection, the four FIFO flags are fixedfunction as shown in the first table entry; the input pins
FIFOADR[2:0] select to which of the four FIFOs the flags
correspond. These pins are decoded as shown in Table 3-3.
The other (non-zero) values of FLAGx[3:0] allow the designer
to independently configure the four flag outputs FLAGAFLAGD to correspond to any flag-Programmable, Full, or
Empty-from any of the four endpoint FIFOs. This allows each
flag to be assigned to any of the four FIFOs, including those
not currently selected by the FIFOADR [2:0] pins. For
example, the external master could be filling the EP2IN FIFO
with data while also checking the empty flag for the EP4OUT
FIFO.
7.3
POLAR Register 0x04
This register controls the polarities of FIFO pin signals and the
WAKEUP pin.
0x04
POLAR
Bit #
7
6
5
4
Bit
Name
WUPOL
0
Read/W
rite
R/W
R/W
R/W
R
R
Default
0
0
0
0
0
PKTEND SLOE
3
2
7.3.7
Bit 3: SLRD
SLWR Bit 2
EF Bit 1
FF Bit 0
This flag selects the polarity of the FF pin (FLAGA/B/C/D). If
FF = 0 (default), the FF pin is pulled low when the FIFO is full.
If FF = 1, the FF pin is pulled HIGH when the FIFO is full.
Note that bits 2(SLWR), 3(SLRD) and 4 (SLOE) are READ
only bits and cannot be set by the external master or the
EEPROM. On power-up, these bits are set to active low
polarity. In order to change the polarity after the device is
powered-up, the external master must access the previously
undocumented (un-indexed) SX2 register located at XDATA
space at 0xE609. This register has exact same bit definition
as the POLAR register except that bits 2, 3 and 4 defined as
SLWR, SLRD and SLOE respectively are Read/Write bits.
Following is the sequence of events that the master should
perform for setting this register to 0x1C (setting bits 4, 3, and
2):
1. Send Low Byte of the Register (0x09)
a. Command address write of address 0x3A
1
0
EF
FF
b. Command data write of upper nibble of the Low Byte of
Register Address (0x00)
R
R/W
R/W
0
0
0
c. Command data write of lower nibble of the Low Byte of
Register Address (0x09)
SLRD SLWR
2. Send High Byte of the Register (0xE6)
a. Command address write of address 0x3B
Document #: 38-08013 Rev. *H
Page 16 of 42
CY7C68001
b. Command data write of upper nibble of the High Byte of
Register Address (0x0E)
c. Command data write of lower nibble of the High Byte of
Register Address (0x06)
3. Send the actual value to write to the register Register (in
this case 0x1C)
7.5.1
Bit 7: VALID
The external master sets VALID = 1 to activate an endpoint,
and VALID = 0 to deactivate it. All SX2 endpoints default to
valid. An endpoint whose VALID bit is 0 does not respond to
any USB traffic. (Note: when setting VALID=0, use default
values for all other bits.)
a. Command address write of address 0x3C
7.5.2
b. Command data write of upper nibble of the register value
(0x01)
0 = OUT, 1 = IN. Defaults for EP2/4 are DIR = 0, OUT, and for
EP6/8 are DIR = 1, IN.
c. Command data write of lower nibble of the register value
(0x0C)
7.5.3
In order to avoid altering any other bits of the FIFOPINPOLAR
register (0xE609) inadvertently, the external master must do a
read (from POLAR register), modify the value to set/clear
appropriate bits and write the modified value to FIFOPINPOLAR register. The external master may read from the
POLAR register using the command read protocol as stated in
Section 3.7.8. Modify the value with the appropriate bit set to
change the polarity as needed and write this modified value to
the FIFOPINPOLAR register.
7.4
Table 7-3. Endpoint Type
TYPE1
TYPE0
Endpoint Type
0
0
Invalid
0
1
Isochronous
1
0
Bulk (Default)
1
1
Interrupt
7.5.4
REVID
Bit [5,4]: TYPE1, TYPE0
These bits define the endpoint type, as shown in Table 7-3.
The TYPE bits apply to all of the endpoint configuration
registers. All SX2 endpoints except EP0 default to BULK.
REVID Register 0x05
These register bits define the silicon revision.
Bit 6: DIR
Bit 3: SIZE
0x05
0 = 512 bytes (default), 1 = 1024 bytes.
Bit #
7
6
5
4
3
2
1
0
Bit
Name
Major
Major
Major
Major
Minor
Minor
Minor
Minor
Endpoints 4 and 8 can only be 512 bytes and is a read only bit.
The size of endpoints 2 and 6 is selectable.
Read/
Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7.5.5
Bit 2: STALL
The upper nibble is the major revision. The lower nibble is the
minor revision. For example: if REVID = 0x11, then the silicon
revision is 1.1.
Each bulk endpoint (IN or OUT) has a STALL bit (bit 2). If the
external master sets this bit, any requests to the endpoint
return a STALL handshake rather than ACK or NAK. The Get
Status-Endpoint Request returns the STALL state for the
endpoint indicated in byte 4 of the request. Note that bit 7 of
the endpoint number EP (byte 4) specifies direction.
7.5
7.5.6
Default
X
X
X
X
X
X
X
X
EPxCFG Register 0x06–0x09
These registers configure the large, data-handling SX2
endpoints, EP2, 4, 6, and 8. Figure 3-1 shows the configuration choices for these endpoints. Shaded blocks group
endpoint buffers for double-, triple-, or quad-buffering. The
endpoint direction is set independently—any shaded block
can have any direction.
Bit #
7
6
Bit
Name
VALID
DIR
Read/
Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
0
1
0
0
0
1
0
Default
For EP2 and EP6 the depth of endpoint buffering is selected
via BUF1:0, as shown in Table 7-4. For EP4 and EP8 the
buffer is internally set to double buffered and are read only bits.
Table 7-4. Endpoint Buffering
0x06, 0x08
EPxCFG
5
4
TYPE1 TYPE0
3
2
1
0
SIZE
STALL
BUF1
BUF0
.
0x07, 0x09
EPxCFG
Bit #
7
6
5
Bit
Name
VALID
DIR
Read/W
rite
R/W
R/W
R/W
Default
1
0
1
4
3
2
1
0
SIZE
STALL
BUF1
BUF0
R/W
R
R/W
R
R
0
0
0
1
0
TYPE1 TYPE0
Document #: 38-08013 Rev. *H
Bit [1,0]: BUF1, BUF0
BUF1
BUF0
Buffering
0
0
Quad
0
1
Invalid[10]
1
0
Double
1
1
Triple
Note:
10. Setting the endpoint buffering to invalid causes improper buffer allocation
7.6
EPxPKTLENH/L Registers 0x0A–0x11
The external master can use these registers to set smaller
packet sizes than the physical buffer size (refer to the previously described EPxCFG registers). The default packet size is
512 bytes for all endpoints. Note that EP2 and EP6 can have
maximum sizes of 1024 bytes, and EP4 and EP8 can have
maximum sizes of 512 bytes, to be consistent with the
endpoint structure.
Page 17 of 42
CY7C68001
In addition, the EPxPKTLENH register has four other endpoint
configuration bits.
0x0B, 0x0D,
0x0F, 0x11
EPxPKTLENL
7
6
5
4
3
2
1
0
Bit Name
PL7
PL6
PL5
PL4
PL3
PL2
PL1
PL0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bit #
Default
0x0A, 0x0E
EP2PKTLENH,
EP6PKTLENH
7
Bit #
6
5
4
INFM1 OEP1 ZERO WORD
LEN WIDE
Bit Name
Read/Write
3
2
1
0
0
PL10
PL9
PL8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
1
1
0
0
1
0
Default
EP4PKTLENH,
EP8PKTLENH
7
Bit #
Read/Write
Default
6
5
4
INFM1 OEP1 ZERO WORD
LEN WIDE
Bit Name
7.7
EPxPFH/L Registers 0x12–0x19
The Programmable Flag registers control when the PF goes
active for each of the four endpoint FIFOs: EP2, EP4, EP6,
and EP8. The EPxPFH/L fields are interpreted differently for
the high speed operation and full speed operation and for OUT
and IN endpoints.
Following is the register bit definition for high speed operation
and for full speed operation (when endpoint is configured as
an isochronous endpoint).
Bit #
Bit Name
Read/Write
Default
6
5
4
1
0
0
PL9
PL8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
1
1
0
0
1
0
Bit Name
Read/Write
2
1
0
PFC1 PFC0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
Bit #
2
0
3
PFC3 PFC2
R/W
Full Speed ISO and High Speed Mode:
EP4PFH, EP8PFH
Default
7.6.1
7
PFC7 PFC6 PFC5 PFC4
0x0C, 0x10
3
0x13, 0x15,
0x17, 0x19
Full Speed ISO and High Speed Mode: EP2PFL,
EP4PFL, EP6PFL, EP8PFL
7
6
0x14, 0x18
5
DECIS PKTSTAT
4
0
3
IN:
IN:
PKTS[1] PKTS[0]
OUT:
OUT:
PFC10 PFC9
R/W
R/W
R/W
R/W
R/W
0
0
0
0
1
2
1
0
0
0
PFC8
R/W R/W R/W
0
0
0
Bit 7: INFM1 EPxPKTLENH.7
0x12, 0x16
When the external master sets INFM = 1 in an endpoint configuration register, the FIFO flags for that endpoint become valid
one sample earlier than when the full condition occurs. These
bits take effect only when the FIFOs are operating synchronously according to an internally or externally supplied clock.
Having the FIFO flag indications one sample early simplifies
some synchronous interfaces. This applies only to IN
endpoints. Default is INFM1 = 0.
Full Speed ISO and High Speed Mode:
EP2PFH, EP6PFH
7.6.2
Following is the bit definition for the same register when the
device is operating at full speed and the endpoint is not
configured as isochronous endpoint.
Bit 6: OEP1 EPxPKTLENH.6
When the external master sets an OEP = 1 in an endpoint
configuration register, the FIFO flags for that endpoint become
valid one sample earlier than when the empty condition
occurs. These bits take effect only when the FIFOs are
operating synchronously according to an internally or externally supplied clock. Having the FIFO flag indications one
sample early simplifies some synchronous interfaces. This
applies only to OUT endpoints. Default is OEP1 = 0.
7.6.3
Bit 5: ZEROLEN EPxPKTLENH.5
When ZEROLEN = 1 (default), a zero length packet will be
sent when the PKTEND pin is asserted and there are no bytes
in the current packet. If ZEROLEN = 0, then a zero length
packet will not be sent under these conditions.
7.6.4
Bit 4: WORDWIDE EPxPKTLENH.4
This bit controls whether the data interface is 8 or 16 bits wide.
If WORDWIDE = 0, the data interface is eight bits wide, and
FD[15:8] have no function. If WORDWIDE = 1 (default), the
data interface is 16 bits wide.
7.6.5
Bit #
Bit Name
Read/Write
Default
7
6
DECIS PKTSTAT
5
4
3
2
IN:
IN:
IN:
0
PKTS[2] PKTS[1] PKTS[0]
OUT:
OUT:
OUT:
PFC12 PFC11 PFC10
R/W
R/W
R/W
R/W
R/W
1
0
0
0
1
1
R/W R/W R/W
0
0
Bit Name
Read/Write
Default
7
6
5
4
3
2
1
Bit Name
Read/Write
Default
0
IN:
IN:
PFC5 PFC4 PFC3 PFC2 PFC1 PFC0
PKTS[1] PKTS[0]
OUT:
OUT:
PFC7 PFC6
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0x12, 0x16
Full Speed Non-ISO Mode:
EP2PFH, EP6PFH
Bit #
0
0x13, 0x15,
0x17, 0x19
Full Speed Non-ISO Mode: EP2PFL,
EP4PFL, EP6PFL, EP8PFL
Bit #
0
PFC9 PFC8
7
6
5
4
3
DECIS PKTSTAT OUT: OUT: OUT:
PFC12 PFC11 PFC10
R/W
R/W
R/W
R/W
R/W
1
0
0
0
1
2
1
0
0
PFC9
IN:
PKTS[2]
OUT:
PFC8
R/W R/W
0
0
R/W
0
Bit [2..0]: PL[X:0] Packet Length Bits
The default packet size is 512 bytes for all endpoints.
Document #: 38-08013 Rev. *H
Page 18 of 42
CY7C68001
0x14, 0x18
7.8
2
1
0
EP2ISOINOKTS, EP4ISOINPKTS,
EP6ISOINPKTS, EP8ISOINPKTS
0
0
PFC8
Full Speed Non-ISO Mode:
EP4PFH, EP8PFH
Bit #
Bit Name
Read/Write
Default
7.7.1
7
6
5
DECIS
PKTSTAT
0
4
3
OUT: OUT:
PFC10 PFC9
R/W
R/W
R/W
R/W
R/W
0
0
0
0
1
R/W R/W
0
0
R/W
0
DECIS: EPxPFH.7
If DECIS = 0, then PF goes high when the byte count i is equal
to or less than what is defined in the PF registers. If DECIS =
1 (default), then PF goes high when the byte count equal to or
greater than what is set in the PF register. For OUT endpoints,
the byte count is the total number of bytes in the FIFO that are
available to the external master. For IN endpoints, the byte
count is determined by the PKSTAT bit.
7.7.2
EPxISOINPKTS Registers 0x1A–0x1D
Bit #
7
6
5
4
3
Bit Name
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
1
Read/Write
Default
PKTSTAT
PF applies to
EPnPFH:L format
0
Number of committed packets PKTS[] and PFC[]
+ current packet bytes
1
Current packet bytes only
7.7.3
PFC[ ]
IN: PKTS(2:0)/OUT: PFC[12:10]: EPxPFH[5:3]
INPPF0
Packets
0
0
Invalid
0
1
1 (default)
1
0
2
1
1
3
7.9
EPxxFLAGS Registers 0x1E–0x1F
The EPxxFLAGS provide an alternate way of checking the
status of the endpoint FIFO flags. If enabled, the SX2 can
interrupt the external master when a flag is asserted, and the
external master can read these two registers to determine the
state of the FIFO flags. If the INFM1 and/or OEP1 bits are set,
then the EPxEF and EPxFF bits are actually empty +1 and full
–1.
Bit #
7
7.7.3.1 IN Endpoints
Bit Name
0
If IN endpoint, the meaning of this EPxPFH[5:3] bits depend
on the PKTSTAT bit setting. When PKTSTAT = 0 (default), the
PF considers when there are PKTS packets plus PFC bytes in
the FIFO. PKTS[2:0] determines how many packets are
considered, according to Table 7-5.
Read/Write
Table 7-5. PKTS Bits
PKTS0
Number of Packets
0
0
0
0
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
When PKTSTAT = 1, the PF considers when there are PFC
bytes in the FIFO, no matter how many packets are in the
FIFO. The PKTS[2:0] bits are ignored.
7.7.3.2 OUT Endpoints
The PF considers when there are PFC bytes in the FIFO
regardless of the PKTSTAT bit setting.
Document #: 38-08013 Rev. *H
0
INPPF1
EP24FLAGS
PKTS1
1
Table 7-6. EPxISOINPKTS
These three bits have a different meaning, depending on
whether this is an IN or OUT endpoint.
PKTS2
2
INPPF2 INPPF1 INPPF0
For ISOCHRONOUS IN endpoints only, these registers
determine the number of packets per frame (only one per
frame for full-speed mode) or microframe (up to three per
microframe for high-speed mode), according to the following
table.
PKSTAT: EPxPFH.6
For IN endpoints, the PF can apply to either the entire FIFO,
comprising multiple packets, or only to the current packet
being filled. If PKTSTAT = 0 (default), the PF refers to the entire
IN endpoint FIFO. If PKTSTAT = 1, the PF refers to the number
of bytes in the current packet.
0x1A, 0x1B,
0x1C, 0x1D
0x1E
6
5
4
EP4PF EP4EF EP4FF
3
0
2
1
0
EP2PF EP2EF EP2FF
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
1
0
0
0
1
0
Bit #
7
6
5
4
3
2
1
Bit Name
0
Default
0x1F
EP68FLAGS
Read/Write
Default
7.9.1
EP8PF EP8EF EP8FF
0
0
EP6PF EP6EF EP6FF
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
1
0
0
0
1
0
EPxPF Bit 6, Bit 2
This bit is the current state of endpoint x’s programmable flag.
7.9.2
EPxEF Bit 5, Bit 1
This bit is the current state of endpoint x’s empty flag. EPxEF
= 1 if the endpoint is empty.
7.9.3
EPxFF Bit 4, Bit 0
This bit is the current state of endpoint x’s full flag. EPxFF = 1
if the endpoint is full.
Page 19 of 42
CY7C68001
7.10
INPKTEND/FLUSH Register 0x20
7.13
This register allows the external master to duplicate the
function of the PKTEND pin. The register also allows the
external master to selectively flush endpoint FIFO buffers.
0x20
INPKTEND/FLUSH
7
Bit #
6
5
4
FIFO8 FIFO6 FIFO4 FIFO2
Bit Name
3
2
1
0
EP3
EP2
EP1
EP0
FNADDR Register 0x2D
During the USB enumeration process, the host sends a device
a unique 7-bit address that the SX2 copies into this register.
There is normally no reason for the external master to know its
USB device address because the SX2 automatically responds
only to its assigned address.
0x2D
FNADDR
7
6
5
4
3
2
1
0
HSGRANT
FA6
FA5
FA4
FA3
FA2
FA1
FA0
Read/Write
R
R
R
R
R
R
R
R
Bit [4..7]: FIFOx
Default
0
0
0
0
0
0
0
0
These bits allows the external master to selectively flush any
or all of the endpoint FIFOs. By writing the desired endpoint
FIFO bit, SX2 logic flushes the selected FIFO. For example
setting bit 7 flushes endpoint 8 FIFO.
Bit 7: HSGRANT, Set to 1 if the SX2 enumerated at high
speed. Set to 0 if the SX2 enumerated at full speed.
Bit [3..0]: EPx
7.14
These bits are is used only for IN transfers. By writing the
desired endpoint number (2,4,6 or 8), SX2 logic automatically
commits an IN buffer to the USB host. For example, for
committing a packet through endpoint 6, set the lower nibble
to 6: set bits 1 and 2 high.
This register is used to enable/disable the various interrupt
sources, and by default all interrupts are enabled.
Read/Write
W
W
W
W
W
W
W
W
Default
0
0
0
0
0
0
0
0
Bit #
Bit Name
Bit[6..0]: Address set by the host.
INTENABLE Register 0x2E
7
Bit #
USBFRAMEH/L Registers 0x2A, 0x2B
Every millisecond, the USB host sends an SOF token
indicating “Start Of Frame,” along with an 11-bit incrementing
frame count. The SX2 copies the frame count into these
registers at every SOF.
0x2A
USBFRAMEH
Bit #
7
6
5
4
3
2
1
0
Bit Name
0
0
0
0
0
FC10
FC9
FC8
Read/Write
R
R
R
R
R
R
R
R
Default
X
X
X
X
X
X
X
x
7
6
5
4
3
2
1
0x2B
USBFRAMEL
Bit #
0
FC7
FC6
FC5
FC4
FC3
FC2
FC1
FC0
Read/Write
R
R
R
R
R
R
R
R
Default
X
X
X
X
X
X
X
X
Bit Name
One use of the frame count is to respond to the USB
SYNC_FRAME Request. If the SX2 detects a missing or
garbled SOF, the SX2 generates an internal SOF and increments USBFRAMEL–USBRAMEH.
7.12
7.14.1
5
R/W
R/W
R/W
1
1
1
4
3
1
1
R/W R/W
1
1
2
1
0
ENUM
BUS
READY
OK ACTIVITY
R/W
R/W
R/W
1
1
1
SETUP Bit 7
Setting this bit to a 1 enables an interrupt when a set-up packet
is received from the USB host.
7.14.2
EP0BUF Bit 6
Setting this bit to a 1 enables an interrupt when the Endpoint
0 buffer becomes available.
7.14.3
FLAGS Bit 5
Setting this bit to a 1 enables an interrupt when an OUT
endpoint FIFO’s state transitions from empty to not-empty.
7.14.4
ENUMOK Bit 2
Setting this bit to a 1 enables an interrupt when SX2 enumeration is complete.
7.14.5
BUSACTIVITY Bit 1
Setting this bit to a 1 enables an interrupt when the SX2
detects an absence or presence of bus activity.
MICROFRAME Registers 0x2C
0x2C
MICROFRAME
Bit #
7
6
5
4
3
2
1
0
Bit Name
0
0
0
0
0
MF2
MF1
MF0
Read/Write
R
R
R
R
R
R
R
R
Default
X
X
X
X
X
X
X
x
MICROFRAME contains a count 0–7 that indicates which of
the 125 microsecond microframes last occurred.
This register is active only when SX2 is operating in highspeed mode (480 Mbits/sec).
Document #: 38-08013 Rev. *H
Read/Write
Default
6
SETUP EP0 FLAGS
BUF
Bit Name
7.11
0x2E
INTENABLE
7.14.6
READY Bit 0
Setting this bit to a 1 enables an interrupt when the SX2 has
powered on and performed an internal self-test.
7.15
DESC Register 0x30
This register address is used to write the 500-byte descriptor
RAM. The external master writes two bytes (four command
data transfers) to this address corresponding to the length of
the descriptor or VID/PID/DID data to be written. The external
master then consecutively writes that number of bytes into the
Page 20 of 42
CY7C68001
descriptor RAM in nibble format. For complete details, refer to
Section 4.0.
8.0
7.16
Ambient Temperature with Power Supplied...... 0°C to +70°C
Absolute Maximum Ratings
Storage Temperature ................................. –65°C to +150°C
EP0BUF Register 0x31
This register address is used to access the 64-byte Endpoint
0 buffer. The external master can read or write to this register
to complete Endpoint 0 data transfers. For complete details,
refer to Section 5.0.
Supply Voltage to Ground Potential................–0.5V to +4.0V
7.17
Power Dissipation.................................................... 936 mW
DC Input Voltage to Any Pin ........................................ 5.25V
DC Voltage Applied to
Outputs in High-Z State ........................ –0.5V to VCC + 0.5V
SETUP Register 0x32
This register address is used to access the 8-byte set-up
packet received from the USB host. If the external master
writes to this register, it can stall Endpoint 0. For complete
details, refer to Section 5.0.
Static Discharge Voltage.......................................... > 2000V
7.18
Supply Voltage................................................+3.0V to +3.6V
9.0
TA (Ambient Temperature Under Bias) ............. 0°C to +70°C
EP0BC Register 0x33
Ground Voltage.................................................................. 0V
This register address is used to access the byte count of
Endpoint 0. For Endpoint 0 OUT transfers, the external master
can read this register to get the number of bytes transferred
from the USB host. For Endpoint 0 IN transfers, the external
master writes the number of bytes in the Endpoint 0 buffer to
transfer the bytes to the USB host. For complete details, refer
to Section 5.0.
10.0
Operating Conditions
FOSC (Oscillator or Crystal Frequency) ..................... 24 MHz
± 100-ppm Parallel Resonant
DC Electrical Characteristics
Table 10-1. DC Characteristics
Parameter
Conditions[11]
Description
Min.
Typ.
Max.
Unit
3.0
3.3
3.6
V
5.25
V
VCC
Supply Voltage
VIH
Input High Voltage
VIL
Input Low Voltage
II
Input Leakage Current
VOH
Output Voltage High
0< VIN < VCC
IOUT = 4 mA
VOL
Output Voltage Low
IOUT = –4 mA
IOH
IOL
CIN
Input Pin Capacitance
15
pF
ISUSP
Suspend Current
Includes 1.5k integrated pull-up
250
400
µA
ISUSP
Suspend Current
Excluding 1.5k integrated pull-up
30
180
µA
ICC
Supply Current
Connected to USB at high speed
200
260
mA
90
150
mA
TRESET
RESET Time after valid power
VCC min = 3.0V
2
–0.5
0.8
V
±10
µA
2.4
V
0.4
V
Output Current High
4
mA
Output Current Low
4
mA
10
pF
Except D+/D–
D+/D–
Connected to USB at full speed
1.91
mS
Note:
11. Specific conditions for ICC measurements: HS typical 3.3V, 25°C, 48 MHz; FS typical 3.3V, 25°C, 48 MHz.
11.0
11.1
AC Electrical Characteristics
USB Transceiver
USB 2.0-certified compliant in full and high speed.
Document #: 38-08013 Rev. *H
Page 21 of 42
CY7C68001
11.2
Command Interface
11.2.1
Command Synchronous Read
tIFCLK
IFCLK
tSRD
tRDH
SLRD
tINT
INT#
DATA
N
tOEon
tOEoff
SLOE
Figure 11-1. Command Synchronous Read Timing Diagram[12]
Table 11-1. Command Synchronous Read Parameters with Internally Sourced IFCLK
Parameter
Description
Min.
Max.
Unit
tIFCLK
IFCLK period
20.83
ns
tSRD
SLRD to Clock Set-up Time
18.7
ns
tRDH
Clock to SLRD Hold Time
0
ns
tOEon
SLOE Turn-on to FIFO Data Valid
10.5
ns
tOEoff
SLOE Turn-off to FIFO Data Hold
10.5
ns
tINT
Clock to INT# Output Propagation Delay
9.5
ns
Min.
Max.
Unit
20
200
ns
Table 11-2. Command Synchronous Read with Externally Sourced IFCLK[13]
Parameter
Description
tIFCLK
IFCLK Period
tSRD
SLRD to Clock Set-up Time
12.7
ns
tRDH
Clock to SLRD Hold Time
3.7
ns
tOEon
SLOE Turn-on to FIFO Data Valid
10.5
ns
tOEoff
SLOE Turn-off to FIFO Data Hold
10.5
ns
13.5
ns
Clock to INT# Output Propagation
tINT
Notes:
12. Dashed lines denote signals with programmable polarity.
13. Externally sourced IFCLK must not exceed 50 MHz.
Document #: 38-08013 Rev. *H
Delay
Page 22 of 42
CY7C68001
11.2.2
Command Synchronous Write
tIFCLK
IFCLK
tSWR
SLWR
tWRH
tSFD
tFDH
N
DATA
tNRDY
tNRDY
READY
Figure 11-2. Command Synchronous Write Timing Diagram[12]
Table 11-3. Command Synchronous Write Parameters with Internally Sourced IFCLK
Parameter
Description
Min.
Max.
Unit
tIFCLK
IFCLK Period
20.83
ns
tSWR
SLWR to Clock Set-up Time
18.1
ns
tWRH
Clock to SLWR Hold Time
0
ns
tSFD
Command Data to Clock Set-up Time
9.2
ns
tFDH
Clock to Command Data Hold Time
tNRDY
Clock to READY Output Propagation Time
0
ns
9.5
ns
Min.
Max.
Unit
20
200
ns
Table 11-4. Command Synchronous Write Parameters with Externally Sourced IFCLK[13]
Parameter
Description
tIFCLK
IFCLK Period
tSWR
SLWR to Clock Set-up Time
12.1
ns
tWRH
Clock to SLWR Hold Time
3.6
ns
tSFD
Command Data to Clock Set-up Time
3.2
ns
tFDH
Clock to Command Data Hold Time
4.5
ns
tNRDY
Clock to READY Output Propagation Time
Document #: 38-08013 Rev. *H
13.5
ns
Page 23 of 42
CY7C68001
11.2.3
Command Asynchronous Read
tRDpwh
SLRD
tRDpwl
tXINT
tIRD
INT#
DATA
N
tOEon
tOEoff
SLOE
Figure 11-3. Command Asynchronous Read Timing Diagram[12]
Table 11-5. Command Read Parameters
Parameter
Description
Min.
Max.
Unit
tRDpwl
SLRD Pulse Width LOW
50
ns
tRDpwh
SLRD Pulse Width HIGH
50
ns
tIRD
INTERRUPT to SLRD
0
tXINT
SLRD to INTERRUPT
tOEon
SLOE Turn-on to FIFO Data Valid
10.5
ns
tOEoff
SLOE Turn-off to FIFO Data Hold
10.5
ns
Max.
Unit
11.2.4
ns
70
ns
Command Asynchronous Write
tWRpwl
tWRpwh
SLWR
tSFD
tFDH
DATA
tRDYWR
tRDY
READY
Figure 11-4. Command Asynchronous Write Timing Diagram[12]
Table 11-6. Command Write Parameters
Parameter
Description
Min.
tWRpwl
SLWR Pulse LOW
50
ns
tWRpwh
SLWR Pulse HIGH
70
ns
tSFD
SLWR to Command DATA Set-up Time
10
ns
tFDH
Command DATA to SLWR Hold Time
10
ns
tRDYWR
READY to SLWR Time
0
tRDY
SLWR to READY
Document #: 38-08013 Rev. *H
ns
70
ns
Page 24 of 42
CY7C68001
11.3
FIFO Interface
11.3.1
Slave FIFO Synchronous Read
tIFCLK
IFCLK
tSRD
tRDH
SLRD
tXFLG
FLAGS
DATA
N
tOEon
N+1
tXFD
tOEoff
SLOE
Figure 11-5. Slave FIFO Synchronous Read Timing Diagram[12]
Table 11-7. Slave FIFO Synchronous Read with Internally Sourced IFCLK[13]
Parameter
Description
Min.
Max.
Unit
tIFCLK
IFCLK Period
20.83
ns
tSRD
SLRD to Clock Set-up Time
18.7
ns
tRDH
Clock to SLRD Hold Time
0
ns
tOEon
SLOE Turn-on to FIFO Data Valid
10.5
ns
tOEoff
SLOE Turn-off to FIFO Data Hold
10.5
ns
tXFLG
Clock to FLAGS Output Propagation Delay
9.5
ns
tXFD
Clock to FIFO Data Output Propagation Delay
11
ns
Min.
Max.
Unit
20
200
Table 11-8. Slave FIFO Synchronous Read with Externally Sourced IFCLK[13]
Parameter
Description
tIFCLK
IFCLK Period
tSRD
SLRD to Clock Set-up Time
12.7
tRDH
Clock to SLRD Hold Time
3.7
tOEon
SLOE Turn-on to FIFO Data Valid
10.5
ns
tOEoff
SLOE Turn-off to FIFO Data Hold
10.5
ns
tXFLG
Clock to FLAGS Output Propagation Delay
13.5
ns
tXFD
Clock to FIFO Data Output Propagation Delay
15
ns
Document #: 38-08013 Rev. *H
ns
ns
ns
Page 25 of 42
CY7C68001
11.3.2
Slave FIFO Synchronous Write
tIFCLK
IFCLK
SLWR
tSWR
DATA
tWRH
N
tSFD
tFDH
FLAGS
tXFLG
Figure 11-6. Slave FIFO Synchronous Write Timing Diagram [12]
Table 11-9. Slave FIFO Synchronous Write Parameters with Internally Sourced IFCLK[13]
Parameter
Description
Min.
Max.
Unit
tIFCLK
IFCLK Period
20.83
ns
tSWR
SLWR to Clock Set-up Time
18.1
ns
tWRH
Clock to SLWR Hold Time
0
ns
tSFD
FIFO Data to Clock Set-up Time
9.2
ns
tFDH
Clock to FIFO Data Hold Time
tXFLG
Clock to FLAGS Output Propagation Time
0
ns
9.5
ns
Max.
Unit
Table 11-10. Slave FIFO Synchronous Write Parameters with Externally Sourced IFCLK[13]
Parameter
Description
Min.
tIFCLK
IFCLK Period
20
ns
tSWR
SLWR to Clock Set-up Time
12.1
ns
tWRH
Clock to SLWR Hold Time
3.6
ns
tSFD
FIFO Data to Clock Set-up Time
3.2
ns
tFDH
Clock to FIFO Data Hold Time
4.5
tXFLG
Clock to FLAGS Output Propagation Time
Document #: 38-08013 Rev. *H
ns
13.5
ns
Page 26 of 42
CY7C68001
11.3.3
Slave FIFO Synchronous Packet End Strobe
IFCLK
tPEH
PKTEND
tSPE
FLAGS
tXFLG
Figure 11-7. Slave FIFO Synchronous Packet End Strobe Timing Diagram[12]
Table 11-11. Slave FIFO Synchronous Packet End Strobe Parameters, Internally Sourced IFCLK[13]
Parameter
Description
Min.
Max.
Unit
tIFCLK
IFCLK Period
20.83
ns
tSPE
PKTEND to Clock Set-up Time
14.6
ns
tPEH
Clock to PKTEND Hold Time
tXFLG
Clock to FLAGS Output Propagation Delay
0
ns
9.5
ns
Table 11-12. Slave FIFO Synchronous Packet End Strobe Parameters, Externally Sourced IFCLK[13]
Parameter
Description
Min.
Max.
200
tIFCLK
IFCLK Period
20
tSPE
PKTEND to Clock Set-up Time
8.6
tPEH
Clock to PKTEND Hold Time
2.5
tXFLG
Clock to FLAGS Output Propagation Delay
There is no specific timing requirement that needs to be met
for asserting PKTEND pin with regards to asserting SLWR.
PKTEND can be asserted with the last data value clocked into
the FIFOs or thereafter. The only consideration is the set-up
time tSPE and the hold time tPEH must be met.
Although there are no specific timing requirement for the
PKTEND assertion, there is a specific corner case condition
that needs attention while using the PKTEND to commit a one
byte/word packet. There is an additional timing requirement
that need to be met when the FIFO is configured to operate in
Unit
ns
ns
ns
13.5
ns
auto mode and it is desired to send two packets back to back:
a full packet (full defined as the number of bytes in the FIFO
meeting the level set in AUTOINLEN register) committed
automatically followed by a short one byte/word packet
committed manually using the PKTEND pin. In this particular
scenario, user must make sure to assert PKTEND at least one
clock cycle after the rising edge that caused the last byte/word
to be clocked into the previous auto committed packet.
Figure 11-8 shows this scenario. X is the value the
AUTOINLEN register is set to when the IN endpoint is
configured to be in auto mode.
tIFCLK
IFCLK
tSFA
tFAH
FIFOADR
>= tWRH
>= tSWR
SLWR
tSFD
X-4
DATA
tFDH
tSFD
X-3
tFDH
tSFD
X-2
tFDH
tSFD
X-1
tFDH
tSFD
X
tFDH
tSFD
tFDH
1
At least one IFCLK cycle
tSPE
tPEH
PKTEND
Figure 11-8. Slave FIFO Synchronous Write Sequence and Timing Diagram
Document #: 38-08013 Rev. *H
Page 27 of 42
CY7C68001
Figure 11-8 shows a scenario where two packets are being
committed. The first packet gets committed automatically
when the number of bytes in the FIFO reaches X (value set in
AUTOINLEN register) and the second one byte/word short
packet being committed manually using PKTEND. Note that
11.3.4
there is at least one IFCLK cycle timing between the assertion
of PKTEND and clocking of the last byte of the previous packet
(causing the packet to be committed automatically). Failing to
adhere to this timing, will result in the FX2 failing to send the
one byte/word short packet.
Slave FIFO Synchronous Address
IFCLK
SLCS#/FIFOADR[2:0]
tSFA
tFAH
Figure 11-9. Slave FIFO Synchronous Address Timing Diagram
Table 11-13. Slave FIFO Synchronous Address Parameters[13]
Parameter
Description
Min.
Max.
Unit
200
ns
tIFCLK
Interface Clock Period
20
tSFA
FIFOADR[2:0] to Clock Set-up Time
25
ns
tFAH
Clock to FIFOADR[2:0] Hold Time
10
ns
11.3.5
Slave FIFO Asynchronous Read
tRDpwh
SLRD
tRDpwl
FLAGS
tXFD
tXFLG
DATA
N
N+1
tOEon
tOEoff
SLOE
Figure 11-10. Slave FIFO Asynchronous Read Timing Diagram [12]
Table 11-14. Slave FIFO Asynchronous Read Parameters[14]
Parameter
Description
Min.
Max.
Unit
tRDpwl
SLRD Pulse Width Low
50
tRDpwh
SLRD Pulse Width HIGH
50
tXFLG
SLRD to FLAGS Output Propagation Delay
tXFD
SLRD to FIFO Data Output Propagation Delay
tOEon
SLOE Turn-on to FIFO Data Valid
tOEoff
SLOE Turn-off to FIFO Data Hold
10.5
ns
Document #: 38-08013 Rev. *H
ns
ns
70
ns
15
ns
10.5
ns
Page 28 of 42
CY7C68001
11.3.6
Slave FIFO Asynchronous Write
tWRpwh
SLWR/SLCS#
tWRpwl
tSFD
tFDH
DATA
tXFD
FLAGS
Figure 11-11. Slave FIFO Asynchronous Write Timing Diagram[12]
Table 11-15. Slave FIFO Asynchronous Write Parameters with Internally Sourced IFCLK[14]
Parameter
Description
Min.
Max.
SLWR Pulse LOW
tWRpwh
SLWR Pulse HIGH
70
ns
tSFD
SLWR to FIFO DATA Set-up Time
10
ns
tFDH
FIFO DATA to SLWR Hold Time
10
tXFD
SLWR to FLAGS Output Propagation Delay
11.3.7
50
Unit
tWRpwl
ns
ns
70
ns
Slave FIFO Asynchronous Packet End Strobe
tPEpwh
PKTEND
tPEpwl
FLAGS
tXFLG
Figure 11-12. Slave FIFO Asynchronous Packet End Strobe Timing Diagram
Table 11-16. Slave FIFO Asynchronous Packet End Strobe Parameters[14]
Parameter
Description
Min.
tPEpwl
PKTEND Pulse Width LOW
50
tPWpwh
PKTEND Pulse Width HIGH
50
tXFLG
PKTEND to FLAGS Output Propagation Delay
Max.
Unit
ns
ns
110
ns
Note:
14. Slave FIFO asynchronous parameter values are using internal IFCLK setting at 48 MHz.
Document #: 38-08013 Rev. *H
Page 29 of 42
CY7C68001
11.3.8
Slave FIFO Asynchronous Address
SLCS/FIFOADR[2:0]
tFAH
tSFA
SLRD/SLWR/PKTEND
Figure 11-13. Slave FIFO Asynchronous Address Timing Diagram[12]
Table 11-17. Slave FIFO Asynchronous Address Parameters[14]
Parameter
Description
Min.
Max.
FIFOADR[2:0] to RD/WR/PKTEND Set-up Time
tFAH
SLRD/PKTEND to FIFOADR[2:0] Hold Time
20
ns
tFAH
SLWR to FIFOADR[2:0] Hold Time
70
ns
11.4
10
Unit
tSFA
ns
Slave FIFO Address to Flags/Data
Following timing is applicable
asynchronous interfaces.
to
synchronous
and
FIFOADR [2.0]
tXFLG
FLAGS
tXFD
DATA
N
N+1
Figure 11-14. Slave FIFO Address to Flags/Data Timing Diagram[11]
Table 11-18. Slave FIFO Address to Flags/Data Parameters
Max.
Unit
tXFLG
Parameter
FIFOADR[2:0] to FLAGS Output Propagation Delay
10.7
ns
tXFD
FIFOADR[2:0] to FIFODATA Output Propagation Delay
14.3
ns
11.5
Description
Min.
Slave FIFO Output Enable
Following timings are applicable to synchronous and
asynchronous interfaces.
SLOE
tOEon
DATA
tOEoff
Figure 11-15. Slave FIFO Output Enable Timing Diagram [11]
Table 11-19. Slave FIFO Output Enable Parameters
Max.
Unit
tOEon
Parameter
SLOE assert to FIFO DATA Output
Description
10.5
ns
tOEoff
SLOE deassert to FIFO DATA Hold
10.5
ns
Document #: 38-08013 Rev. *H
Min.
Page 30 of 42
CY7C68001
11.6
Sequence Diagram
11.6.1
Single and Burst Synchronous Read Example
tIFCLK
IFCLK
tSFA
tSFA
tFAH
tFAH
FIFOADR
t=0
tSRD
T=0
tRDH
>= tSRD
>= tRDH
SLRD
t=3
t=2
T=3
T=2
SLCS
tXFLG
FLAGS
tXFD
tXFD
Data Driven: N
DATA
N+1
N+1
N+2
N+3
tOEon
tOEoff
tOEon
tXFD
tXFD
N+4
tOEoff
SLOE
t=4
t=1
T=4
T=1
Figure 11-16. Slave FIFO Synchronous Read Sequence and Timing Diagram
IFCLK
FIFO POINTER
N
IFCLK
IFCLK
N
N+1
FIFO DATA BUS Not Driven
Driven: N
N+1
IFCLK
N+1
SLOE
SLRD
SLRD
SLOE
IFCLK
N+1
SLOE
Not Driven
IFCLK
N+2
IFCLK
N+3
SLRD
N+1
IFCLK
N+4
IFCLK
SLRD
N+2
N+3
N+4
IFCLK
N+4
N+4
SLOE
N+4
Not Driven
Figure 11-17. Slave FIFO Synchronous Sequence of Events Diagram
Figure 11-16 shows the timing relationship of the SLAVE FIFO
signals during a synchronous FIFO read using IFCLK as the
synchronizing clock. The diagram illustrates a single read
followed by a burst read.
• At t = 0 the FIFO address is stable and the signal SLCS is
asserted (SLCS may be tied low in some applications).
Note: tSFA has a minimum of 25 ns. This means when IFCLK
is running at 48 MHz, the FIFO address set-up time is more
than one IFCLK cycle.
• At = 1, SLOE is asserted. SLOE is an output enable only,
whose sole function is to drive the data bus. The data that
is driven on the bus is the data that the internal FIFO pointer
is currently pointing to. In this example it is the first data
value in the FIFO. Note: the data is pre-fetched and is driven
on the bus when SLOE is asserted.
• At t = 2, SLRD is asserted. SLRD must meet the set-up time
of tSRD (time from asserting the SLRD signal to the rising
edge of the IFCLK) and maintain a minimum hold time of
tRDH (time from the IFCLK edge to the deassertion of the
SLRD signal). If the SLCS signal is used, it must be asserted
Document #: 38-08013 Rev. *H
with SLRD, or before SLRD is asserted (i.e., the SLCS and
SLRD signals must both be asserted to start a valid read
condition).
• The FIFO pointer is updated on the rising edge of the IFCLK,
while SLRD is asserted. This starts the propagation of data
from the newly addressed location to the data bus. After a
propagation delay of tXFD (measured from the rising edge
of IFCLK) the new data value is present. N is the first data
value read from the FIFO. In order to have data on the FIFO
data bus, SLOE MUST also be asserted.
The same sequence of events are shown for a burst read and
are marked with the time indicators of T = 0 through 5. Note:
For the burst mode, the SLRD and SLOE are left asserted
during the entire duration of the read. In the burst read mode,
when SLOE is asserted, data indexed by the FIFO pointer is
on the data bus. During the first read cycle, on the rising edge
of the clock the FIFO pointer is updated and increments to
point to address N+1. For each subsequent rising edge of
IFCLK, while the SLRD is asserted, the FIFO pointer is incremented and the next data value is placed on the data bus.
Page 31 of 42
CY7C68001
11.6.2
Single and Burst Synchronous Write
tIFCLK
IFCLK
tSFA
tSFA
tFAH
tFAH
FIFOADR
t=0
tSWR
tWRH
>= tWRH
>= tSWR
T=0
SLWR
t=2
T=2
t=3
T=5
SLCS
tXFLG
tXFLG
FLAGS
tFDH
tSFD
tSFD
N+1
N
DATA
t=1
tFDH
T=1
tSFD
tFDH
tSFD
N+3
N+2
T=3
tFDH
T=4
tSPE
tPEH
PKTEND
Figure 11-18. Slave FIFO Synchronous Write Sequence and Timing Diagram[12]
Figure 11-18 shows the timing relationship of the SLAVE FIFO
signals during a synchronous write using IFCLK as the
synchronizing clock. The diagram illustrates a single write
followed by burst write of 3 bytes and committing all 4 bytes as
a short packet using the PKTEND pin.
• At t = 0 the FIFO address is stable and the signal SLCS is
asserted. (SLCS may be tied low in some applications)
Note: tSFA has a minimum of 25 ns. This means when IFCLK
is running at 48 MHz, the FIFO address set-up time is more
than one IFCLK cycle.
• At t = 1, the external master/peripheral must output the data
value onto the data bus with a minimum set up time of tSFD
before the rising edge of IFCLK.
• At t = 2, SLWR is asserted. The SLWR must meet the setup
time of tSWR (time from asserting the SLWR signal to the
rising edge of IFCLK) and maintain a minimum hold time of
tWRH (time from the IFCLK edge to the de-assertion of the
SLWR signal). If SLCS signal is used, it must be asserted
with SLWR or before SLWR is asserted. (i.e.,the SLCS and
SLWR signals must both be asserted to start a valid write
condition).
• While the SLWR is asserted, data is written to the FIFO and
on the rising edge of the IFCLK, the FIFO pointer is incremented. The FIFO flag will also be updated after a delay of
tXFLG from the rising edge of the clock.
The same sequence of events are also shown for a burst write
and are marked with the time indicators of T = 0 through 5.
Note: For the burst mode, SLWR and SLCS are left asserted
for the entire duration of writing all the required data values. In
this burst write mode, once the SLWR is asserted, the data on
Document #: 38-08013 Rev. *H
the FIFO data bus is written to the FIFO on every rising edge
of IFCLK. The FIFO pointer is updated on each rising edge of
IFCLK. In Figure 11-18, once the four bytes are written to the
FIFO, SLWR is deasserted. The short 4-byte packet can be
committed to the host by asserting the PKTEND signal.
There is no specific timing requirement that needs to be met
for asserting PKTEND signal with regards to asserting the
SLWR signal. PKTEND can be asserted with the last data
value or thereafter. The only consideration is the set-up time
tSPE and the hold time tPEH must be met. In the scenario of
Figure 11-18, the number of data values committed includes
the last value written to the FIFO. In this example, both the
data value and the PKTEND signal are clocked on the same
rising edge of IFCLK. PKTEND can be asserted in subsequent
clock cycles. The FIFOADDR lines should be held constant
during the PKTEND assertion.
Although there are no specific timing requirement for the
PKTEND assertion, there is a specific corner case condition
that needs attention while using the PKTEND to commit a one
byte/word packet. Additional timing requirements exists when
the FIFO is configured to operate in auto mode and it is desired
to send two packets: a full packet (full defined as the number
of bytes in the FIFO meeting the level set in AUTOINLEN
register) committed automatically followed by a short one
byte/word packet committed manually using the PKTEND pin.
In this case, the external master must make sure to assert the
PKTEND pin at least one clock cycle after the rising edge that
caused the last byte/word to be clocked into the previous auto
committed packet (the packet with the number of bytes equal
to what is set in the AUTOINLEN register).
Page 32 of 42
CY7C68001
11.6.3
Sequence Diagram of a Single and Burst Asynchronous Read
tSFA
tFAH
tSFA
tFAH
FIFOADR
t=0
tRDpwl
tRDpwh
tRDpwl
T=0
tRDpwl
tRDpwh
tRDpwl
tRDpwh
tRDpwh
SLRD
t=2
t=3
T=2
T=3
T=5
T=4
T=6
SLCS
tXFLG
tXFLG
FLAGS
tXFD
Data (X)
Driven
DATA
tXFD
tXFD
N
N
N+3
N+2
tOEon
tOEoff
tOEon
tXFD
N+1
tOEoff
SLOE
t=4
t=1
T=1
T=7
Figure 11-19. Slave FIFO Asynchronous Read Sequence and Timing Diagram
SLOE
FIFO POINTER
SLRD
N
FIFO DATA BUS Not Driven
SLRD
SLOE
SLOE
SLRD
SLRD
SLRD
SLRD
SLOE
N
N
N+1
N+1
N+1
N+1
N+2
N+2
N+3
N+3
Driven: X
N
N
Not Driven
N
N+1
N+1
N+2
N+2
Not Driven
Figure 11-20. Slave FIFO Asynchronous Read Sequence of Events Diagram
Figure 11-19 diagrams the timing relationship of the SLAVE
FIFO signals during an asynchronous FIFO read. It shows a
single read followed by a burst read.
• At t = 0 the FIFO address is stable and the SLCS signal is
asserted.
• At t = 1, SLOE is asserted. This results in the data bus being
driven. The data that is driven on to the bus is previous data,
it data that was in the FIFO from a prior read cycle.
• At t = 2, SLRD is asserted. The SLRD must meet the
minimum active pulse of tRDpwl and minimum de-active
pulse width of tRDpwh. If SLCS is used then, SLCS must be
asserted with SLRD or before SLRD is asserted (i.e., the
SLCS and SLRD signals must both be asserted to start a
valid read condition).
Document #: 38-08013 Rev. *H
• The data that will be driven, after asserting SLRD, is the
updated data from the FIFO. This data is valid after a propagation delay of tXFD from the activating edge of SLRD. In
Figure 11-19, data N is the first valid data read from the
FIFO. For data to appear on the data bus during the read
cycle (i.e. SLRD is asserted), SLOE MUST be in an asserted
state. SLRD and SLOE can also be tied together.
The same sequence of events is also shown for a burst read
marked with T = 0 through 5. Note: In burst read mode, during
SLOE is assertion, the data bus is in a driven state and outputs
the previous data. Once SLRD is asserted, the data from the
FIFO is driven on the data bus (SLOE must also be asserted)
and then the FIFO pointer is incremented.
Page 33 of 42
CY7C68001
11.6.4
Sequence Diagram of a Single and Burst Asynchronous Write
tSFA
tFAH
tSFA
tFAH
FIFOADR
t=0
tWRpwl
tWRpwh
T=0
tWRpwl
tWRpwl
tWRpwh
tWRpwl
tWRpwh
tWRpwh
SLWR
t =1
t=3
T=1
T=3
T=4
T=6
T=7
T=9
SLCS
tXFLG
tXFLG
FLAGS
tSFD tFDH
tSFD tFDH
tSFD tFDH
tSFD tFDH
N+1
N+2
N+3
N
DATA
t=2
T=2
T=5
T=8
tPEpwl
tPEpwh
PKTEND
Figure 11-21. Slave FIFO Asynchronous Write Sequence and Timing Diagram [12]
Figure 11-21 diagrams the timing relationship of the SLAVE
FIFO write in an asynchronous mode. The diagram shows a
single write followed by a burst write of 3 bytes and committing
the 4-byte-short packet using PKTEND.
• At t = 0 the FIFO address is applied, insuring that it meets
the set-up time of tSFA. If SLCS is used, it must also be
asserted (SLCS may be tied low in some applications).
• At t = 1 SLWR is asserted. SLWR must meet the minimum
active pulse of tWRpwl and minimum de-active pulse width
of tWRpwh. If the SLCS is used, it must be asserted with
SLWR or before SLWR is asserted.
• At t = 2, data must be present on the bus tSFD before the
deasserting edge of SLWR.
• At t = 3, deasserting SLWR will cause the data to be written
from the data bus to the FIFO and then increments the FIFO
12.0
pointer. The FIFO flag is also updated after tXFLG from the
deasserting edge of SLWR.
The same sequence of events are shown for a burst write and
is indicated by the timing marks of T = 0 through 5. Note: In
the burst write mode, once SLWR is deasserted, the data is
written to the FIFO and then the FIFO pointer is incremented
to the next byte in the FIFO. The FIFO pointer is post incremented.
In Figure 11-21 once the four bytes are written to the FIFO and
SLWR is deasserted, the short 4-byte packet can be
committed to the host using the PKTEND. The external device
should be designed to not assert SLWR and the PKTEND
signal at the same time. It should be designed to assert the
PKTEND after SLWR is deasserted and met the minimum deasserted pulse width. The FIFOADDR lines are to be held
constant during the PKTEND assertion.
Default Descriptor
//Device Descriptor
18,
//Descriptor length
1,
//Descriptor type
00,02,
//Specification Version (BCD)
00,
//Device class
00,
//Device sub-class
00,
//Device sub-sub-class
64,
//Maximum packet size
LSB(VID),MSB(VID),//Vendor ID
LSB(PID),MSB(PID),//Product ID
LSB(DID),MSB(DID),//Device ID
1,
//Manufacturer string index
2,
//Product string index
0,
//Serial number string index
1,
//Number of configurations
//DeviceQualDscr
Document #: 38-08013 Rev. *H
Page 34 of 42
CY7C68001
10,
6,
0x00,0x02,
00,
00,
00,
64,
1,
0,
//Descriptor length
//Descriptor type
//Specification Version (BCD)
//Device class
//Device sub-class
//Device sub-sub-class
//Maximum packet size
//Number of configurations
//Reserved
//HighSpeedConfigDscr
9,
//Descriptor length
2,
//Descriptor type
46,
//Total Length (LSB)
0,
//Total Length (MSB)
1,
//Number of interfaces
1,
//Configuration number
0,
//Configuration string
0xA0,
//Attributes (b7 - buspwr, b6 - selfpwr, b5 - rwu)
50,
//Power requirement (div 2 ma)
//Interface Descriptor
9,
//Descriptor length
4,
//Descriptor type
0,
//Zero-based index of this interface
0,
//Alternate setting
4,
//Number of end points
0xFF,
//Interface class
0x00,
//Interface sub class
0x00,
//Interface sub sub class
0,
//Interface descriptor string index
//Endpoint Descriptor
7,
//Descriptor length
5,
//Descriptor type
0x02,
//Endpoint number, and direction
2,
//Endpoint type
0x00,
//Maximum packet size (LSB)
0x02,
//Max packet size (MSB)
0x00,
//Polling interval
//Endpoint Descriptor
7,
//Descriptor length
5,
//Descriptor type
0x04,
//Endpoint number, and direction
2,
//Endpoint type
0x00,
//Maximum packet size (LSB)
0x02,
//Max packet size (MSB)
0x00,
//Polling interval
//Endpoint Descriptor
7,
//Descriptor length
5,
//Descriptor type
0x86,
//Endpoint number, and direction
2,
//Endpoint type
0x00,
//Maximum packet size (LSB)
0x02,
//Max packet size (MSB)
0x00,
//Polling interval
Document #: 38-08013 Rev. *H
Page 35 of 42
CY7C68001
//Endpoint Descriptor
7,
//Descriptor length
5,
//Descriptor type
0x88,
//Endpoint number, and direction
2,
//Endpoint type
0x00,
//Maximum packet size (LSB)
0x02,
//Max packet size (MSB)
0x00,
//Polling interval
//FullSpeedConfigDscr
9,
//Descriptor length
2,
//Descriptor type
46,
//Total Length (LSB)
0,
//Total Length (MSB)
1,
//Number of interfaces
1,
//Configuration number
0,
//Configuration string
0xA0,
//Attributes (b7 - buspwr, b6 - selfpwr, b5 - rwu)
50,
//Power requirement (div 2 ma)
//Interface Descriptor
9,
//Descriptor length
4,
//Descriptor type
0,
//Zero-based index of this interface
0,
//Alternate setting
4,
//Number of end points
0xFF,
//Interface class
0x00,
//Interface sub class
0x00,
//Interface sub sub class
0,
//Interface descriptor string index
//Endpoint Descriptor
7,
//Descriptor length
5,
//Descriptor type
0x02,
//Endpoint number, and direction
2,
//Endpoint type
0x40,
//Maximum packet size (LSB)
0x00,
//Max packet size (MSB)
0x00,
//Polling interval
//Endpoint Descriptor
7,
//Descriptor length
5,
//Descriptor type
0x04,
//Endpoint number, and direction
2,
//Endpoint type
0x40,
//Maximum packet size (LSB)
0x00,
//Max packet size (MSB)
0x00,
//Polling interval
//Endpoint Descriptor
7,
//Descriptor length
5,
//Descriptor type
0x86,
//Endpoint number, and direction
2,
//Endpoint type
0x40,
//Maximum packet size (LSB)
0x00,
//Max packet size (MSB)
0x00,
//Polling interval
//Endpoint Descriptor
Document #: 38-08013 Rev. *H
Page 36 of 42
CY7C68001
7,
5,
0x88,
2,
0x40,
0x00,
0x00,
//Descriptor length
//Descriptor type
//Endpoint number, and direction
//Endpoint type
//Maximum packet size (LSB)
//Max packet size (MSB)
//Polling interval
//StringDscr
//StringDscr0
4,
3,
0x09,0x04,
//StringDscr1
16,
3,
'C',00,
'y',00,
'p',00,
'r',00,
'e',00,
's',00,
's',00,
//StringDscr2
20,
3,
'C',00,
'Y',00,
'7',00,
'C',00,
'6',00,
'8',00,
'0',00,
'0',00,
'1',00,
13.0
//String descriptor length
//String Descriptor
//US LANGID Code
//String descriptor length
//String Descriptor
//String descriptor length
//String Descriptor
General PCB Layout Guidelines[15]
The following recommendations should be followed to ensure
reliable high-performance operation.
• At least a four-layer impedance controlled boards are required to maintain signal quality.
• Specify impedance targets (ask your board vendor what
they can achieve).
• To control impedance, maintain trace widths and trace spacing.
• Minimize stubs to minimize reflected signals.
• Connections between the USB connector shell and signal
ground must be done near the USB connector.
• Bypass/flyback caps on VBus, near connector, are recommended.
• DPLUS and DMINUS trace lengths should be kept to within
2 mm of each other in length, with preferred length of 20–30
mm.
Document #: 38-08013 Rev. *H
• Maintain a solid ground plane under the DPLUS and DMINUS traces. Do not allow the plane to be split under these
traces.
• It is preferred to have no vias placed on the DPLUS or DMINUS trace routing.
• Isolate the DPLUS and DMINUS traces from all other signal
traces by no less than 10 mm.
14.0
Quad Flat Package No Leads (QFN)
Package Design Notes
Electrical contact of the part to the Printed Circuit Board (PCB)
is made by soldering the leads on the bottom surface of the
package to the PCB. Hence, special attention is required to the
heat transfer area below the package to provide a good
thermal bond to the circuit board. A Copper (Cu) fill is to be
designed into the PCB as a thermal pad under the package.
Heat is transferred from the SX2 through the device’s metal
paddle on the bottom side of the package. Heat from here, is
conducted to the PCB at the thermal pad. It is then conducted
Page 37 of 42
CY7C68001
from the thermal pad to the PCB inner ground plane by a 5 x
5 array of via. A via is a plated through hole in the PCB with a
finished diameter of 13 mil. The QFN’s metal die paddle must
be soldered to the PCB’s thermal pad. Solder mask is placed
on the board top side over each via to resist solder flow into
the via. The mask on the top side also minimizes outgassing
during the solder reflow process.
For further information on this package design please refer to
“Application Notes for Surface Mount Assembly of Amkor’s
MicroLeadFrame® (MLF®) Packages.” This application note
can be downloaded from Amkor’s web site from the following
URL: http://www.amkor.com/products/notes_papers/MLFAppNote.pdf. The application note provides detailed information
on board mounting guidelines, soldering flow, rework process,
etc.
Figure 14-1 below displays a cross-sectional area underneath
the package. The cross section is of only one via. The solder
paste template needs to be designed to allow at least 50%
solder coverage. The thickness of the solder paste template
should be 5 mil. It is recommended that “No Clean” type 3
solder paste is used for mounting the part. Nitrogen purge is
recommended during reflow.
Figure 14-2a is a plot of the solder mask pattern and
Figure 14-2b displays an X-Ray image of the assembly
(darker areas indicate solder.
0.017” dia
Solder Mask
Cu Fill
Cu Fill
PCB Material
0.013” dia
Via hole for thermally connecting the
QFN to the circuit board ground plane.
PCB Material
This figure only shows the top three layers of the
circuit board: Top Solder, PCB Dielectric, and the Ground Plane.
Figure 14-1. Cross section of the Area Underneath the QFN Package
Figure 14-2. (a) Plot of the Solder Mask (White Area)
Figure 0-2. (b) X-ray Image of the Assembly
Note:
15. Source for recommendations: High-Speed USB Platform Design Guidelines, http://www.usb.org/developers/data/hs_usb_pdg_r1_0.pdf.
Document #: 38-08013 Rev. *H
Page 38 of 42
CY7C68001
15.0
Ordering Information
Table 15-1. Ordering Information
Ordering Code
Package Type
CY7C68001-56PVC
56 SSOP
CY7C68001-56LFC
56 QFN
CY7C68001-56PVXC
56 SSOP, Lead-free
CY7C68001-56LFXC
56 QFN, Lead-free
CY3682
EZ-USB SX2 Development Kit
16.0
Package Diagrams
16.1
56-pin SSOP Package
56-pin Shrunk Small Outline Package 056
51-85062-*C
Figure 16-1. 56-lead Shrunk Small Outline Package
Document #: 38-08013 Rev. *H
Page 39 of 42
CY7C68001
16.2
56-pin QFN Package
56-Lead QFN 8 x 8 MM LF56A
TOP VIEW
BOTTOM VIEW
SIDE VIEW
0.08[0.003]
C
1.00[0.039] MAX.
7.90[0.311]
8.10[0.319]
A
0.05[0.002] MAX.
0.80[0.031] MAX.
7.70[0.303]
7.80[0.307]
0.18[0.007]
0.28[0.011]
0.20[0.008] REF.
0.80[0.031]
DIA.
PIN1 ID
0.20[0.008] R.
N
N
1
1
2
2
0.45[0.018]
6.45[0.254]
6.55[0.258]
7.90[0.311]
8.10[0.319]
7.70[0.303]
7.80[0.307]
E-PAD
(PAD SIZE VARY
BY DEVICE TYPE)
0.30[0.012]
0.50[0.020]
0°-12°
0.50[0.020]
C
Dimensions in millimeters
SEATING
PLANE
0.24[0.009]
0.60[0.024]
(4X)
6.45[0.254]
6.55[0.258]
51-85144-*D
Figure 16-2. LF56A 56-pin QFN Package
Purchase of I2C components from Cypress, or one of its sublicensed Associated Companies, conveys a license under the Philips
I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification
as defined by Philips. EZ-USB SX2 is a trademark of Cypress Semiconductor. All product and company names mentioned in this
document are the trademarks of their respective holders.
Document #: 38-08013 Rev. *H
Page 40 of 42
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY7C68001
Document History Page
Description Title: CY7C68001 EZ-USB SX2™ High-Speed USB Interface Device
Document Number: 38-08013
REV.
ECN No. Issue Date
Origin of
Change
Description of Change
**
111807
06/07/02
BHA
New Data Sheet
*A
123155
02/07/03
BHA
Minor clean-up and clarification
Removed references to IRQ Register and replaced them with references to
Interrupt Status Byte
Modified pin-out description for XTALIN and XTALOUT
Added CS# timing to Figure 11-11, Figure 11-9, and Figure 11-13
Changed Command Protocol example to IFCONFIG (0x01)
Edited PCB Layout Recommendations
Added AR#10691
Added USB high-speed logo
*B
126324
07/02/03
MON
Default state of registers specified in section where the register bits are defined
Reorganized timing diagram presentation: First all timing related to synchronous
interface, followed by timing related to asynchronous interface, followed by timing
diagrams common to both interfaces
Provided further information in section 3.3 regarding boot methods
Provided timing diagram that encapsulates ALL relevant signals for a synchronous
and asynchronous slave read and write interface
Added section on (QFN) Package Design Notes
FIFOADR[2:0] Hold Time (tFAH) for Asynchronous FIFO Interface has been updated
as follows: SLRD/PKTEND to FIFOADR[2:0] Hold Time: 20 ns; SLWR to
FIFOADR[2:0] Hold Time:70 ns (recommended)
Added information on the polarity of the programmable flag
Fixed the Command Synchronous Write Timing Diagram
Fixed the Command Asynchronous Write Timing Diagram
Added information on the delay required when endpoint configuration registers are
changed after SX2 has already enumerated
*C
129463
10/07/03
MON
Added Test ID for the USB Compliance Test
Added information on the fact that the SX2 does not automatically respond to
Set/Clear Feature Endpoint (Stall) request, external master intervention required
Added information on accessing undocumented register which are not indexed (for
resetting data toggle)
Added information on requirement of clock stability before releasing reset
Added information on configuration of PF register for full speed
Updated confirmed timing on FIFOADR[2:0] Hold Time (tFAH)for Asynchronous
FIFO Interface has been updated
Corrected the default bit settings of EPxxFLAGS register
Added information on how to change SLWR/SLRD/SLOE polarities
Added further information on buffering interrupt on initiation of a command read
request
Change the default state of the FNADDR to 0x00
Added further labels on the sequence diagram for synchronous and asynchronous
read and write in single and burst mode
Added information on the maximum delay allowed between each descriptor byte
write once a command write request to register 0x30 has been initiated by the
external master
Document #: 38-08013 Rev. *H
Page 41 of 42
CY7C68001
Description Title: CY7C68001 EZ-USB SX2™ High-Speed USB Interface Device
Document Number: 38-08013
*D
130447
12/17/03
KKU
Replaced package diagram in Figure 16-2 spec number 51-85144 with clear image
Fixed last history entry for rev *C
Change reference in section 2.7.2.4 from XXXXXXX to 7.3
Removed the word “compatible” in section 3.3
Change the text in section 5.0, last paragraph from 0xE6FB to 0xE683
Changed label “Reset” to “Default” in sections 5.1 and 7.2 through 7.14
Reformatted Figure 6-2
Added entries 3A, 3B, 3C, 0xE609, and 0xE683 to Figure 7-1
Change access on hex values 07 and 09 from bbbbbbbb to bbbbrbrr
Removed tXFD from Figure 11-1 and Figure 11-3 and tables 11-1,2, and 5
Corrected timing diagrams, figures 11-1,11-2, 11-6
Changed Figure 11-16 through Figure 11-21 for clarity, text which followed had
reference to t3 which should be t2, added reference of t3 for deasserting SLWR and
reworded section 11.6
Updated ICC typical and maximum values
*E
243316
See ECN
KKU
Reformatted data sheet to latest format
Added Lead-free parts numbers
Updated default value for address 0x07 and 0x09
Added Footnote 3.
Removed requirement of less then 360 nsec period between nibble writes in
command
Changed PKTEND to FLAGS output propagation delay in table 11-16 from a max
value of 70 ns to 110 ns
*F
329238
See ECN
KEV
Provided additional timing restrictions and requirement regarding the use of
PKTEND pin to commit a short one byte/word packet subsequent to committing
a packet automatically (when in auto mode)
Miscellaneous grammar corrections.
Added 3.4.3 section header.
Fixed command sequence step 3 to say register value instead of High Byte of
Register Address (upper and lower nibble in two places).
Removed statement that programmable flag polarity is set to active low and cannot
be altered. Programmable flag relies on DECIS bit settings.
Updated Amkor application note URL.
Changed T XINT in Figure 11-3 to be from deassertion edge of SLRD.
Changed T RDY in Figure 11-4 to be from deassertion edge of SLWR.
Changed FLAGS Interrupt from empty to not-empty to both empty to not-empty and
from not-empty to empty conditions for triggering this interrupt.
*G
392570
See ECN
KEV
Modified Figure 3-1 to fit across columns. It was getting cropped in half.
Changed corporate address to 198 Champion Court.
*H
411515
See ECN
BHA
Added information in section 4.1 on Full Speed only enumeration.
Document #: 38-08013 Rev. *H
Page 42 of 42