Revised February 2000 DM74ALS161B • DM74ALS162B • DM74ALS163B Synchronous Four-Bit Counter General Description These synchronous presettable counters feature an internal carry look ahead for application in high speed counting designs. The DM74ALS162B is a four-bit decade counter, while the DM74ALS161B and DM74ALS163B are four-bit binary counters. The DM74ALS161B clears asynchronously, while the DM74ALS162B and DM74ALS163B clear synchronously. The carry output is decoded to prevent spikes during normal counting mode of operation. Synchronous operation is provided by having all flip-flops clocked simultaneously so that outputs change coincident with each other when so instructed by count enable inputs and internal gating. This mode of operation eliminates the output counting spikes which are normally associated with asynchronous (ripple clock) counters. A buffered clock input triggers the four flip-flops on the rising (positivegoing) edge of the clock input waveform. These counters are fully programmable, that is, the outputs may be preset to either level. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with set up data after the next clock pulse regardless of the levels of enable input. LOW-to-HIGH transitions at the load input are perfectly acceptable regardless of the logic levels on the clock or enable inputs. The DM74ALS161B clear function is asynchronous. A low level at the clear input sets all four of the flip-flop outputs LOW regardless of the levels of clock, load or enable inputs. These two counters are provided with a clear on power-up feature. The DM74ALS162B and DM74ALS163B clear function is synchronous; and a low level at the clear input sets all four of the flip-flop outputs LOW after the next clock pulse, regardless of the levels of enable inputs. This synchronous clear allows the count length to be modified easily, as decoding the maximum count desired can be accomplished with one external NAND gate. The gate output is connected to the clear input to synchronously clear the counter to all low outputs. LOW-to-HIGH transitions at the clear input of the DM74ALS162B and DM74ALS163B are also permissible regardless of the levels of logic on the clock, enable or load inputs. The carry look ahead circuitry provides for cascading counters for n bit synchronous application without additional gating. Instrumental in accomplishing this function are two count enable inputs (P and T) and a ripple carry output. Both count enable inputs must be HIGH to count. The T input is fed forward to enable the ripple carry output. The ripple carry output thus enabled will produce a high level output pulse with a duration approximately equal to the high level portion of QA output. This high level overflow ripple carry pulse can be used to enable successive cascaded stages. HIGH-to-LOW level transitions at the enable P or T inputs of the DM74ALS161B through DM74ALS163B may occur regardless of the logic level on the clock. The DM74ALS161B through DM74ALS163B feature a fully independent clock circuit. changes made to control inputs (enable P or T, or load) that will modify the operating mode will have no effect until clocking occurs. The function of the counter (whether enabled, disabled, loading or counting) will be dictated solely by the conditions meeting the stable set-up and hold times. Features ■ Switching specifications at 50 pF ■ Switching specifications guaranteed over full temperature and VCC range ■ Advanced oxide-isolated, ion-implanted Schottky TTL process ■ Functionally and pin-for-pin compatible with Schottky and low power Schottky TTL counterpart ■ Improved AC performance over Schottky and low power Schottky counterparts ■ Synchronously programmable ■ Internal look ahead for fast counting ■ Carry output for n-bit cascading ■ Synchronous counting ■ Load control line ■ ESD inputs Ordering Code: Order Number Package Number DM74ALS161BM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Description DM74ALS161BN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide DM74ALS162BM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow DM74ALS162BN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide DM74ALS163BM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow DM74ALS163BN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. © 2000 Fairchild Semiconductor Corporation DS006206 www.fairchildsemi.com DM74ALS161B • DM74ALS162B • DM74ALS163B Synchronous Four-Bit Counter April 1984 DM74ALS161B • DM74ALS162B • DM74ALS163B Connection Diagram Mode Select Table Clear L Load Enable T Enable P X Clock Edge ( Reset (Clear) L X X Load (Pn → Qn) H H H H Count (Increment) H H L X No Change (Hold) H H X L No Change (Hold) Logic Diagrams DM74ALS161B 2 X H H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial www.fairchildsemi.com X Action on the Rising ) DM74ALS161B • DM74ALS162B • DM74ALS163B Logic Diagrams (Continued) DM74ALS162B DM74ALS163B 3 www.fairchildsemi.com DM74ALS161B • DM74ALS162B • DM74ALS163B Timing Diagrams DM74ALS162B www.fairchildsemi.com 4 DM74ALS161B • DM74ALS162B • DM74ALS163B Timing Diagrams (continued) DM74ALS161B, DM74ALS163B 5 www.fairchildsemi.com DM74ALS161B • DM74ALS162B • DM74ALS163B Absolute Maximum Ratings(Note 1) Supply Voltage 7V Input Voltage 7V Operating Free Air Temperature Range 0°C to +70°C Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. −65°C to +150°C Storage Temperature Range Typical θJA N Package 78.1°C/W M Package 106.8°C/W Recommended Operating Conditions Symbol Parameter Min Nom Max 4.5 5 5.5 Units VCC Supply Voltage VIH HIGH Level Input Voltage VIL LOW Level Input Voltage 0.8 V IOH HIGH Level Output Current −0.4 mA IOL LOW Level Output Current fCLK Clock Frequency tSETUP Setup Time 2 0 Data; A, B, C, D En P, En T ns ns tHOLD tW TA Hold Time 15↑ (Note 2) ns 15↑ (Note 2) ns LOW 15↑ (Note 2) ns HIGH 12↑ (Note 2) Load Clear Inactive ns 10 4 ns Data; A, B, C, D 0↑ (Note 2) −3 ns En P, En T 0↑ (Note 2) −3 ns Load 0↑ (Note 2) −4 ns Clear (Only for DM74ALS162B and DM74ALS163B 0↑ (Note 2) −7 ns 0 −4 ns Hold 0 (Only for 161B) Clear Width of Clock CLK HIGH or LOW or Clear Pulse DM74ALS161B CLR LOW 12.5 ns 15 ns Width of Load Pulse 15 Operating Free Air Temperature 0 Note 2: The symbol (↑) indicates that the rising edge of the clock is used as a reference. www.fairchildsemi.com mA MHz 15↑ (Note 2) DM74ALS163B Setup 1 (Only for 161B) 8 40 DM74ALS161B 15↑ (Note 2) DM74ALS162B Clear (Only for DM74ALS162B and DM74ALS163B) V V 6 ns 70 °C over recommended operating free air temperature range. All typical values are measured at VCC = 5V, TA = 25°C. Symbol Parameter Conditions VIK Input Clamp Voltage VCC = 4.5V, II = −18 mA VOH HIGH Level IOH = −0.4 mA Output Voltage VCC = 4.5V to 5.5V LOW Level VCC = 4.5V VOL Input Current at Max Input Voltage Typ Max Units −1.5 V VCC − 2 Output Voltage II Min V IOL = 4 mA 0.25 0.4 V IOL = 8 mA 0.35 0.5 V 0.1 mA VCC = 5.5V, VIH = 7V IIH HIGH Level Input Current VCC = 5.5V, VIH = 2.7V 20 µA IIL LOW Level Input Current VCC = 5.5V, VIL = 0.4V −0.2 mA IO Output Drive Current VCC = 5.5V, VO = 2.25V ICC Supply Current VCC = 5.5V −30 −112 mA 12 21 mA Min Max Units Switching Characteristics DM74ALS161B over recommended operating free air temperature range. Symbol Parameter Conditions fMAX Maximum Clock Frequency VCC = 4.5V to 5.5V tPLH Propagation Delay Time RL = 500Ω LOW-to-HIGH Level Output CL = 50 pF tPHL From 40 Clock Propagation Delay Time Clock Propagation Delay Time Propagation Delay Time HIGH-to-LOW Level Output tPLH Propagation Delay Time 20 ns 5 20 ns 4 15 ns Clock Any Q 6 20 ns En T Ripple 3 13 ns 3 13 ns En T HIGH-to-LOW Level Output tPHL 5 Any Q Carry Propagation Delay Time MHz Clock LOW-to-HIGH Level Output tPHL Ripple Carry LOW-to-HIGH Level Output tPHL Ripple Carry HIGH-to-LOW Level Output tPLH To Ripple Carry Propagation Delay Time Clear Any Q HIGH-to-LOW Level Output Clear Ripple Carry 8 24 ns 11 23 ns Min Max Units Switching Characteristics DM74ALS162B, DM74ALS163B over recommended operating free air temperature range. Symbol Parameter Conditions fMAX Maximum Clock Frequency VCC = 4.5V to 5.5V tPLH Propagation Delay Time RL = 500Ω LOW-to-HIGH Level Output CL = 50 pF Propagation Delay Time TA = Min to Max tPHL From 40 Clock Clock Propagation Delay Time Propagation Delay Time HIGH-to-LOW Level Output tPLH Propagation Delay Time ns 5 20 ns 15 ns Clock Any Q 6 20 ns En T Ripple 3 13 ns 3 13 ns Ripple Carry 7 20 4 En T HIGH-to-LOW Level Output 5 Any Q Carry Propagation Delay Time MHz Clock LOW-to-HIGH Level Output tPHL Ripple Carry LOW-to-HIGH Level Output tPHL Ripple Carry HIGH-to-LOW Level Output tPLH To www.fairchildsemi.com DM74ALS161B • DM74ALS162B • DM74ALS163B Electrical Characteristics DM74ALS161B • DM74ALS162B • DM74ALS163B Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A www.fairchildsemi.com 8 DM74ALS161B • DM74ALS162B • DM74ALS163B Synchronous Four-Bit Counter Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 9 www.fairchildsemi.com