ON CAT28LV64H13I25T 64 kb cmos parallel eeprom Datasheet

CAT28LV64
64 kb CMOS Parallel
EEPROM
Description
The CAT28LV64 is a low voltage, low power, CMOS Parallel
EEPROM organized as 8K x 8−bits. It requires a simple interface for
in−system programming. On−chip address and data latches,
self−timed write cycle with auto−clear and VCC power up/down write
protection eliminate additional timing and protection hardware. DATA
Polling and Toggle status bit signal the start and end of the self−timed
write cycle. Additionally, the CAT28LV64 features hardware and
software write protection.
The CAT28LV64 is manufactured using ON Semiconductor’s
advanced CMOS floating gate technology. It is designed to endure
100,000 program/erase cycles and has a data retention of 100 years.
The device is available in JEDEC approved 28−pin DIP, 28−pin TSOP,
28−pin SOIC or 32−pin PLCC packages.
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PDIP−28
P, L SUFFIX
CASE 646AE
SOIC−28
J, K, W, X SUFFIX
CASE 751BM
Features
• 3.0 V to 3.6 V Supply
• Read Access Times:
•
•
•
•
•
•
•
•
•
•
•
– 150/200/250 ns
Low Power CMOS Dissipation:
– Active: 8 mA Max.
– Standby: 100 mA Max.
Simple Write Operation:
– On−chip Address and Data Latches
– Self−timed Write Cycle with Auto−clear
Fast Write Cycle Time:
– 5 ms Max.
Commercial, Industrial and Automotive Temperature Ranges
CMOS and TTL Compatible I/O
Automatic Page Write Operation:
– 1 to 32 bytes in 5 ms
– Page Load Timer
End of Write Detection:
– Toggle bit
– DATA Polling
Hardware and Software Write Protection
100,000 Program/Erase Cycles
100 Year Data Retention
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
© Semiconductor Components Industries, LLC, 2009
October, 2009 − Rev. 7
1
TSOP−28
H13 SUFFIX
CASE 318AE
PLCC−32
N, G SUFFIX
CASE 776AK
PIN FUNCTION
Pin Name
A0−A12
I/O0−I/O7
Function
Address Inputs
Data Inputs/Outputs
CE
Chip Enable
OE
Output Enable
WE
Write Enable
VCC
3.0 V to 3.6 V Supply
VSS
Ground
NC
No Connect
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 15 of this data sheet.
Publication Order Number:
CAT28LV64/D
CAT28LV64
PIN CONFIGURATIONS
DIP Package (P, L)
SOIC Package (J, K, W, X)
NC
A12
1
2
28
27
VCC
WE
NC
A12
1
2
28
27
VCC
WE
A7
3
26
25
NC
A7
3
A6
4
26
25
NC
A8
5
6
24
24
22
21
A5
A4
A3
5
6
7
A9
A11
OE
A10
A2
7
8
22
21
A9
A11
OE
A1
A0
9
19
CE
I/O7
CE
I/O7
18
I/O6
I/O0
10
11
20
19
18
I/O6
17
16
15
I/O5
I/O1
12
I/O5
I/O2
VSS
13
14
17
16
15
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
VSS
4
8
9
10
11
12
13
14
23
20
I/O4
I/O3
PLCC Package (N, G)
23
A8
A10
I/O4
I/O3
A7
A12
NC
NC
VCC
WE
NC
TSOP Package (8 mm x 13.4 mm) (H13)
A8
A9
A11
NC
OE
A10
CE
I/O7
I/O6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
OE
A11
A9
A8
NC
WE
VCC
NC
A12
A7
A6
A5
A4
A3
I/O1
I/O2
VSS
NC
I/O3
I/O4
I/O5
A6
A5
A4
A3
A2
A1
A0
NC
I/O0
4 3 2 1 32 31 30
5
29
6
28
7
27
8
26
9
25
10
24
11
23
12
22
13
21
14 15 16 17 18 19 20
(Top Views)
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2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
CAT28LV64
A5−A12
ADDR. BUFFER
& LATCHES
ROW
DECODER
VCC
INADVERTENT
WRITE
PROTECTION
HIGH VOLTAGE
GENERATOR
CE
OE
WE
CONTROL
LOGIC
8,192 x 8
E2PROM
ARRAY
32 BYTE PAGE
REGISTER
I/O BUFFERS
DATA POLLING
AND
TOGGLE BIT
TIMER
ADDR. BUFFER
& LATCHES
A0−A4
I/O0−I/O7
COLUMN
DECODER
Figure 1. Block Diagram
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters
Ratings
Units
Temperature Under Bias
−55 to +125
°C
Storage Temperature
−65 to +150
°C
−2.0 V to +VCC + 2.0 V
V
−2.0 to +7.0
V
Voltage on Any Pin with Respect to Ground (Note 1)
VCC with Respect to Ground
Package Power Dissipation Capability (TA = 25°C)
1.0
W
Lead Soldering Temperature (10 secs)
300
°C
Output Short Circuit Current (Note 2)
100
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The minimum DC input voltage is −0.5 V. During transitions, inputs may undershoot to −2.0 V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC + 0.5 V, which may overshoot to VCC + 2.0 V for periods of less than 20 ns.
2. Output shorted for no more than one second. No more than one output shorted at a time.
Table 2. RELIABILITY CHARACTERISTICS (Note 3)
Symbol
Parameter
Test Method
Min
Max
Units
Endurance
MIL−STD−883, Test Method 1033
105
Cycles/Byte
TDR
Data Retention
MIL−STD−883, Test Method 1008
100
Years
VZAP
ESD Susceptibility
MIL−STD−883, Test Method 3015
2,000
V
Latch−Up
JEDEC Standard 17
100
mA
NEND
ILTH (Note 4)
3. These parameters are tested initially and after a design or process change that affects the parameters.
4. Latch−up protection is provided for stresses up to 100 mA on address and data pins from −1 V to VCC + 1 V.
Table 3. MODE SELECTION
Mode
CE
WE
OE
I/O
Power
Read
L
H
L
DOUT
ACTIVE
Byte Write (WE Controlled)
L
H
DIN
ACTIVE
L
H
DIN
ACTIVE
Byte Write (CE Controlled)
Standby and Write Inhibit
H
X
X
High−Z
STANDBY
Read and Write Inhibit
X
H
H
High−Z
ACTIVE
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3
CAT28LV64
Table 4. CAPACITANCE (TA = 25°C, f = 1.0 MHz)
Symbol
Test
Max
Conditions
Units
CI/O (Note 5)
Input/Output Capacitance
10
VI/O = 0 V
pF
CIN (Note 5)
Input Capacitance
6
VIN = 0 V
pF
5. This parameter is tested initially and after a design or process change that affects the parameter.
Table 5. D.C. OPERATING CHARACTERISTICS (VCC = 3.0 V to 3.6 V, unless otherwise specified.)
Limits
Symbol
Parameter
Min
Test Conditions
Typ
Max
Units
8
mA
100
mA
ICC
VCC Current (Operating, TTL)
CE = OE = VIL,
f = 1/tRC min, All I/O’s Open
ISBC (Note 6)
VCC Current (Standby, CMOS)
CE = VIHC, All I/O’s Open
ILI
Input Leakage Current
VIN = GND to VCC
−1
1
mA
ILO
Output Leakage Current
VOUT = GND to VCC,
CE = VIH
−5
5
mA
VIH (Note 6)
High Level Input Voltage
2
VCC + 0.3
V
VIL
Low Level Input Voltage
−0.3
0.6
V
VOH
High Level Output Voltage
IOH = −100 mA
VOL
Low Level Output Voltage
IOL = 1.0 mA
VWI
Write Inhibit Voltage
2
V
0.3
2
V
V
6. VIHC = VCC − 0.3 V to VCC + 0.3 V.
Table 6. A.C. CHARACTERISTICS, READ CYCLE (VCC = 3.0 V to 3.6 V, unless otherwise specified.)
28LV64−15
Symbol
Parameter
Min
Max
150
28LV64−20
Min
Max
200
28LV64−25
Min
Max
250
Units
tRC
Read Cycle Time
ns
tCE
CE Access Time
150
200
250
ns
tAA
Address Access Time
150
200
250
ns
tOE
OE Access Time
70
80
100
ns
tLZ (Note 7)
CE Low to Active Output
0
0
0
ns
tOLZ (Note 7)
OE Low to Active Output
0
0
0
ns
tHZ (Notes 7, 8)
CE High to High−Z Output
50
50
55
ns
tOHZ (Notes 7, 8)
OE High to High−Z Output
50
50
55
ns
tOH (Note 7)
Output Hold from Address Change
0
0
0
7. This parameter is tested initially and after a design or process change that affects the parameter.
8. Output floating (High−Z) is defined as the state when the external data line is no longer driven by the output buffer.
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4
ns
CAT28LV64
VCC − 0.3 V
2.0 V
INPUT PULSE LEVELS
REFERENCE POINTS
0.6 V
0.0 V
Figure 2. A.C. Testing Input/Output Waveform (Note 9)
9. Input rise and fall times (10% and 90%) < 10 ns.
VCC
1.8 K
DEVICE
OUTPUT
UNDER
TEST
1. 3 K
CL = 100 pF
CL INCLUDES JIG CAPACITANCE
Figure 3. A.C. Testing Load Circuit (example)
Table 7. A.C. CHARACTERISTICS, WRITE CYCLE (VCC = 3.0 V to 3.6 V, unless otherwise specified.)
28LV64−15
Symbol
Parameter
Min
Max
28LV64−20
Min
5
Max
28LV64−25
Min
5
Max
Units
5
ms
tWC
Write Cycle Time
tAS
Address Setup Time
0
0
0
ns
tAH
Address Hold Time
100
100
100
ns
tCS
CE Setup Time
0
0
0
ns
tCH
CE Hold Time
0
0
0
ns
tCW (Note 10)
CE Pulse Time
110
150
150
ns
tOES
OE Setup Time
0
10
10
ns
tOEH
OE Hold Time
0
10
10
ns
tWP (Note 10)
WE Pulse Width
110
150
150
ns
tDS
Data Setup Time
60
100
100
ns
tDH
Data Hold Time
0
0
0
ns
tINIT (Note 11)
Write Inhibit Period After
Power−up
5
10
5
10
5
10
ms
tBLC
(Notes 11, 12)
Byte Load Cycle Time
0.05
100
0.1
100
0.1
100
ms
10. A write pulse of less than 20 ns duration will not initiate a write cycle.
11. This parameter is tested initially and after a design or process change that affects the parameter.
12. A timer of duration tBLC max. begins with every LOW to HIGH transition of WE. If allowed to time out, a page or byte write will begin; however
a transition from HIGH to LOW within tBLC max. stops the timer.
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CAT28LV64
DEVICE OPERATION
Byte Write
A write cycle is executed when both CE and WE are low,
and OE is high. Write cycles can be initiated using either WE
or CE, with the address input being latched on the falling
edge of WE or CE, whichever occurs last. Data, conversely,
is latched on the rising edge of WE or CE, whichever occurs
first. Once initiated, a byte write cycle automatically erases
the addressed byte and the new data is written within 5 ms.
Read
Data stored in the CAT28LV64 is transferred to the data
bus when WE is held high, and both OE and CE are held low.
The data bus is set to a high impedance state when either CE
or OE goes high. This 2−line control architecture can be used
to eliminate bus contention in a system environment.
tRC
ADDRESS
tCE
CE
tOE
OE
tOLZ
VIH
WE
tLZ
tHZ
tOH
HIGH−Z
DATA OUT
tOHZ
tAA
DATA VALID
DATA VALID
Figure 4. Read Cycle
tWC
ADDRESS
tAS
tAH
tCH
tCS
CE
OE
tOES
tWP
tOEH
WE
DATA OUT
DATA IN
HIGH−Z
tBLC
DATA VALID
tDS
tDH
Figure 5. Byte Write Cycle [WE Controlled]
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6
CAT28LV64
Page Write
in any order) during the first and subsequent write cycles.
Each successive byte load cycle must begin within tBLC MAX
of the rising edge of the preceding WE pulse. There is no
page write window limitation as long as WE is pulsed low
within tBLC MAX.
Upon completion of the page write sequence, WE must
stay high a minimum of tBLC MAX for the internal automatic
program cycle to commence. This programming cycle
consists of an erase cycle, which erases any data that existed
in each addressed cell, and a write cycle, which writes new
data back into the cell. A page write will only write data to
the locations that were addressed and will not rewrite the
entire page.
The page write mode of the CAT28LV64 (essentially an
extended BYTE WRITE mode) allows from 1 to 32 bytes of
data to be programmed within a single EEPROM write
cycle. This effectively reduces the byte−write time by a
factor of 32.
Following an initial WRITE operation (WE pulsed low,
for tWP, and then high) the page write mode can begin by
issuing sequential WE pulses, which load the address and
data bytes into a 32 byte temporary buffer. The page address
where data is to be written, specified by bits A5 to A12, is
latched on the last falling edge of WE. Each byte within the
page is defined by address bits A0 to A4 (which can be loaded
tWC
ADDRESS
tAS
tBLC
tAH
tCW
CE
tOEH
OE
tCS
tOES
tCH
WE
HIGH−Z
DATA OUT
DATA IN
DATA VALID
tDS
tDH
Figure 6. Byte Write Cycle [CE Controlled]
OE
CE
tWP
tBLC
WE
ADDRESS
tWC
I/O
LAST BYTE
BYTE 0
BYTE 1
BYTE 2
BYTE n
Figure 7. Page Mode Write Cycle
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7
BYTE n+1
BYTE n+2
CAT28LV64
DATA Polling
Toggle Bit
DATA polling is provided to indicate the completion of
write cycle. Once a byte write or page write cycle is initiated,
attempting to read the last byte written will output the
complement of that data on I/O7 (I/O0–I/O 6 are
indeterminate) until the programming cycle is complete.
Upon completion of the self−timed write cycle, all I/O’s will
output true data during a read cycle.
In addition to the DATA Polling feature, the device offers
an additional method for determining the completion of a
write cycle. While a write cycle is in progress, reading data
from the device will result in I/O6 toggling between one and
zero. However, once the write is complete, I/O6 stops
toggling and valid data can be read from the device.
ADDRESS
CE
WE
tOEH
tOES
tOE
OE
tWC
I/O7
DOUT = X
DIN = X
DOUT = X
Figure 8. DATA Polling
WE
CE
tOEH
tOES
tOE
OE
I/O6
(Note 13)
(Note 13)
tWC
Figure 9. Toggle Bit
13. Beginning and ending state of I/O6 is indeterminate.
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CAT28LV64
Hardware Data Protection
4. Noise pulses of less than 20 ns on the WE or CE
inputs will not result in a write cycle.
The following is a list of hardware data protection features
that are incorporated into the CAT28LV64.
1. VCC sense provides for write protection when VCC
falls below 2.0 V min.
2. A power on delay mechanism, tINIT (see AC
characteristics), provides a 5 to 10 ms delay before
a write sequence, after VCC has reached 2.40 V
min.
3. Write inhibit is activated by holding any one of
OE low, CE high or WE high.
WRITE DATA:
ADDRESS:
WRITE DATA:
ADDRESS:
WRITE DATA:
ADDRESS:
Software Data Protection
The CAT28LV64 features a software controlled data
protection scheme which, once enabled, requires a data
algorithm to be issued to the device before a write can be
performed. The device is shipped from ON Semiconductor
with the software protection NOT ENABLED (the
CAT28LV64 is in the standard operating mode).
WRITE DATA:
AA
ADDRESS:
1555
WRITE DATA:
55
ADDRESS:
0AAA
WRITE DATA:
A0
ADDRESS:
1555
WRITE DATA:
SOFTWARE DATA
PROTECTION ACTIVATED (Note 14)
ADDRESS:
XX
WRITE DATA:
TO ANY ADDRESS
ADDRESS:
WRITE LAST BYTE
TO
LAST ADDRESS
WRITE DATA:
WRITE DATA:
ADDRESS:
Figure 10. Write Sequence for Activating Software
Data Protection
AA
1555
55
0AAA
80
1555
AA
1555
55
0AAA
20
1555
Figure 11. Write Sequence for Deactivating
Software Data Protection
14. Write protection is activated at this point whether or not any more writes are completed. Writing to addresses must occur within tBLC Max.,
after SDP activation.
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CAT28LV64
To activate the software data protection, the device must
be sent three write commands to specific addresses with
specific data (Figure 10). This sequence of commands
(along with subsequent writes) must adhere to the page write
timing specifications (Figure 12). Once this is done, all
subsequent byte or page writes to the device must be
preceded by this same set of write commands. The data
protection mechanism is activated until a deactivate
sequence is issued regardless of power on/off transitions.
This gives the user added inadvertent write protection on
power−up in addition to the hardware protection provided.
DATA
ADDRESS
AA
1555
To allow the user the ability to program the device with an
EEPROM programmer (or for testing purposes) there is a
software command sequence for deactivating the data
protection. The six step algorithm (Figure 11) will reset the
internal protection circuitry, and the device will return to
standard operating mode (Figure 13 provides reset timing).
After the sixth byte of this reset sequence has been issued,
standard byte or page writing can commence.
55
0AAA
tWC
A0
1555
BYTE OR
PAGE
CE
tWP
WRITES
ENABLED
tBLC
WE
Figure 12. Software Data Protection Timing
DATA
ADDRESS
AA
1555
55
0AAA
80
1555
AA
1555
55
0AAA
20
1555
tWC
SDP
RESET
CE
DEVICE
UNPROTECTED
WE
Figure 13. Resetting Software Data Protection Timing
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CAT28LV64
PACKAGE DIMENSIONS
PLCC 32
CASE 776AK−01
ISSUE O
PIN#1 IDENTIFICATION
E1
E
E2
D1
A2
D
A3
TOP VIEW
END VIEW
b1
b
e
D2
SIDE VIEW
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MS-016.
SYMBOL
MIN
A2
0.38
A3
2.54
2.80
11
MAX
b
0.33
0.54
b1
0.66
0.82
D
12.32
12.57
D1
11.36
11.50
D2
9.56
11.32
E
14.86
15.11
E1
13.90
14.04
E2
12.10
13.86
e
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NOM
1.27 BSC
CAT28LV64
PACKAGE DIMENSIONS
SOIC−28, 300 mils
CASE 751BM−01
ISSUE O
SYMBOL
E
MIN
NOM
A
2.35
2.65
A1
0.10
0.30
A2
2.05
2.55
b
0.31
0.51
c
0.20
0.33
D
17.78
18.03
E
10.11
10.51
E1
7.34
7.60
e
b
e
PIN #1
IDENTIFICATION
MAX
1.27 BSC
h
0.25
0.75
L
0.40
1.27
θ
0º
8º
θ1
5º
15º
TOP VIEW
h
D
A2 A
A1
h
q1
q
q1 c
L
E1
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-013.
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CAT28LV64
PACKAGE DIMENSIONS
PDIP−28, 600 mils
CASE 646AE−01
ISSUE A
SYMBOL
MIN
NOM
A
E1 E
D
6.35
A1
0.39
A2
3.18
4.95
b
0.36
0.55
b1
0.77
1.77
c
0.21
0.38
D
35.10
39.70
E
15.24
15.87
E1
12.32
14.73
e
TOP VIEW
A2
2.54 BSC
eB
15.24
17.78
L
2.93
5.08
A
c
A1
b1
e
L
b
eB
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MS-011.
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13
MAX
CAT28LV64
PACKAGE DIMENSIONS
TSOP 28, 8x13.4
CASE 318AE−01
ISSUE O
D1
A
PIN 1
b
E1
e
A1
A2
D
TOP VIEW
END VIEW
q1
c
q
L2
L
L1
SIDE VIEW
SYMBOL
MIN
NOM
MAX
A
1.00
1.10
1.20
A1
0.05
A2
0.90
1.00
1.05
b
0.17
0.22
0.27
c
0.10
0.15
0.20
D
13.20
13.40
13.60
D1
11.70
11.80
11.90
E
7.90
8.00
8.10
e
0.55 BSC
L
0.30
L1
0.675
L2
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-183.
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14
0.15
0.50
0.70
0.25 BSC
θ
0°
3°
5°
θ1
10°
12°
16°
CAT28LV64
Example of Ordering Information (Note 15)
Prefix
Device #
Suffix
CAT
28LV64
N
Company ID
(Optional)
Product Number
28LV64
I
− 25
Tape & Reel (Note 18)
T: Tape & Reel
Temperature Range
Blank = Commercial (0°C to +70°C)
I = Industrial (−40°C to +85°C)
A = Automotive (−40°C to +105°C) (Note 17)
Package
P: PDIP
J: SOIC (JEDEC)
K: SOIC (EIAJ)
N: PLCC
L: PDIP (Lead Free, Halogen Free)
W: SOIC (JEDEC) (Lead Free, Halogen Free)
X: SOIC (EIAJ) (Lead Free, Halogen Free)
G: PLCC (Lead Free, Halogen Free)
H13: TSOP (8 mm x 13.4 mm) (Lead Free, Halogen Free) (Note 16)
T
Speed
15: 150 ns
20: 200 ns
25: 250 ns
ORDERING INFORMATION
Orderable Part Numbers (for Pb−Free Devices)
CAT28LV64GI−15T
CAT28LV64H13A15T
CAT28LV64WI−15T
CAT28LV64XA−15T
CAT28LV64GI−20T
CAT28LV64H13A20T
CAT28LV64WI−20T
CAT28LV64XA−20T
CAT28LV64GI−25T
CAT28LV64H13A25T
CAT28LV64WI−25T
CAT28LV64XA−25T
CAT28LV64GA−15T
CAT28LV64LI15
CAT28LV64WA−15T
CAT28LV64GA−20T
CAT28LV64LI20
CAT28LV64WA−20T
CAT28LV64GA−25T
CAT28LV64LI25
CAT28LV64WA−25T
CAT28LV64H13I15T
CAT28LV64LA15
CAT28LV64XI−15T
CAT28LV64H13I20T
CAT28LV64LA20
CAT28LV64XI−20T
CAT28LV64H13I25T
CAT28LV64LA25
CAT28LV64XI−25T
15. The device used in the above example is a CAT28LV64NI−25T (PLCC, Industrial temperature, 250 ns Access Time, Tape & Reel).
16. For the TSOP package (H13), the orderable part number does not contain a hyphen, example: CAT28LV64H13I20T.
17. −40°C to +125°C is available upon request.
18. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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15
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CAT28LV64/D