Fairchild BSS84 P-channel enhancement mode field-effect transistor Datasheet

BSS84
P-Channel Enhancement Mode Field-Effect Transistor
Features
Description


-0.13 A, -50 V, RDS(ON) = 10 Ω at VGS = -5 V


High-Density Cell Design for Low RDS(ON)
This P-channel enhancement-mode field-effect
transistor is produced using Fairchild’s proprietary,
high cell density, DMOS technology. This very high
density process minimizes on-state resistance and to
provide rugged and reliable performance and fast
switching. The BSS84 can be used, with a minimum
of effort, in most applications requiring up to 0.13 A
DC and can deliver current up to 0.52 A. This product
is particularly suited to low-voltage applications
requiring
a
low-current
high-side
switch.
Voltage-Controlled P-Channel Small-Signal
Switch
High Saturation Current
D
D
S
G
G
SOT-23
S
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only. Values are at TA = 25°C unless otherwise noted.
Symbol
VDSS
VGSS
ID
PD
TJ, TSTG
TL
Parameter
Drain-Source Voltage
Gate-Source Voltage
Continuous
Pulsed
Drain Current(1)
Maximum Power Dissipation(1)
Derate Above 25°C
Operating and Storage Junction Temperature Range
Maximum Lead Temperature for Soldering
Purposes, 1/16” from Case for 10 Seconds
Ratings
Unit
−50
±20
−0.13
−0.52
0.36
2.9
−55 to +150
V
V
A
A
W
mW / °C
°C
300
°C
Thermal Characteristics
RθJA
Thermal Resistance, Junction-to-Ambient(1)
350
°C/W
Note:
1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference
is defined as the solder mounting surface of the drain pins. RθJA is guaranteed by design, while RθJA is
determined by the user's board design.
a) 350°C/W when mounted on a minimum pad
Scale 1: 1 on letter-size paper.
Package Marking and Ordering Information
Device Marking
Device
Reel Size
Tape width
Quantity
SP
BSS84
7’’
8mm
3000
© 2002 Fairchild Semiconductor Corporation
BSS84 • Rev. 1.1.0
www.fairchildsemi.com
BSS84 — P-Channel Enhancement Mode Field-Effect Transistor
February 2013
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Unit
Off Characteristics
BVDSS
Drain–Source Breakdown Voltage
ΔBVDSS
ΔTJ
Breakdown Voltage Temperature
Coefficient
IDSS
Zero Gate Voltage Drain Current
IGSS
BVDSS
Gate–Body Leakage.
Drain–Source Breakdown Voltage
VGS = 0 V, ID = –250 μA
ID = –250 μA,
Referenced to 25℃
VDS = –50 V, VGS = 0 V
VDS = –50 V, VGS = 0 V,
TJ = 125°C
VGS = ±20 V, VDS = 0 V
VGS = 0 V,
ID = –250 μA
–50
V
mV / ℃
–48
–15
μA
–60
μA
±10
nA
V
–2
V
–50
On Characteristics(2)
VGS(th)
VGS(TH)
TJ
Gate Threshold Voltage
Gate Threshold Voltage
Temperature Coefficient
RDS(on)
Static Drain–Source
On–Resistance
ID(on)
gFS
On–State Drain Current
Forward Transconductance
VDS = VGS, ID = –1 mA
ID = –1 mA,
–0.8
mV / ℃
3
Referenced to 25℃
VGS = –5 V, ID = –0.10 A
VGS = –5 V, ID = –0.10 A,
TJ = 125°C
VGS = –5 V, VDS = – 10 V
VDS = –25 V, ID = – 0.10 A
–1.7
–0.6
0.05
1.2
10.0
Ω
1.9
17.0
Ω
0.60
A
S
73
10
pF
pF
5
pF
9
Ω
Dynamic Characteristics
CISS
COSS
Input Capacitance
Output Capacitance
CRSS
Reverse Transfer Capacitance
RG
Gate Resistance
VDS = –25 V,
VGS = 0 V,
f = 1.0 MHz
VGS = –15 mV, f = 1.0 MHz
Switching Characteristics(2)
td(on)
tr
td(off)
tf
Qg
Qgs
Qgd
Turn–On Delay
Turn–On Rise Time
Turn–Off Delay
Turn–Off Fall Time
Total Gate Charge
Gate–Source Charge
Gate–Drain Charge
VDD = –30 V, ID = – 0.27 A,
VGS = –10 V, RGEN = 6 
VDS = –25 V, ID = –0.10 A,
VGS = –5 V
2.5
6.3
10
4.8
0.9
0.2
0.3
5.0
13.0
20
9.6
1.3
ns
ns
ns
ns
nC
nC
nC
-0.13
A
-1.2
V
BSS84 — P-Channel Enhancement Mode Field-Effect Transistor
Electrical Characteristics(2)
Drain-Source Diode Characteristics and Maximum Ratings
IS
Maximum Continuous Drain-Source Diode Forward Current
VSD
Drain-Source Diode Forward
Voltage
VGS = 0 V, IS = - 0.26 A(2)
-0.8
tRR
Diode Reverse-Recovery Time
10
ns
QRR
Diode Reverse-Recovery Charge
IF = -0.1 A,
(2)
diF / dt = 100 A / µs
3
nC
Note:
2.
Pulse Test: Pulse Width ≤ 300 μs, Duty Cycle ≤ 2.0%.
© 2002 Fairchild Semiconductor Corporation
BSS84 • Rev. 1.1.0
www.fairchildsemi.com
2
1
2
-4.5V
-3.5V
RDS(ON), NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
-ID, DRAIN CURRENT (A)
VGS = -5V
0.8
0.6
-3.0V
0.4
-2.5V
0.2
0
1.8
VGS=-3.0V
1.6
1.4
-3.5V
1.2
1
2
3
4
5
-5.0V
0
0.2
0.4
0.6
0.8
1
-VDS, DRAIN TO SOURCE VOLTAGE (V)
-ID, DRAIN CURRENT (A)
Figure 1. On-Region Characteristics
Figure 2. On-Resistance Variation with Drain
Current and Gate Voltage
1.8
5
ID = -0.10A
VGS = -5V
ID = -0.05A
RDS(ON), ON-RESISTANCE (OHM)
1.6
1.4
1.2
1
0.8
0.6
0.4
-50
-25
0
25
50
75
100
125
4
3
TA = 125oC
2
TA = 25oC
1
150
2
2.5
o
TJ, JUNCTION TEMPERATURE ( C)
3
3.5
4
4.5
5
-VGS, GATE TO SOURCE VOLTAGE (V)
Figure 3. On-Resistance Variation with
Temperature
Figure 4. On-Resistance Variation with Gate-toSource Voltage
1
VDS = -5V
-IS, REVERSE DRAIN CURRENT (A)
1
-ID, DRAIN CURRENT (A)
-4.5V
1
0.8
0
RDS(ON), NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
-4.0V
BSS84 — P-Channel Enhancement Mode Field-Effect Transistor
Typical Characteristics
25oC
o
TA = -55 C
0.8
125oC
0.6
0.4
0.2
VGS = 0V
0.1
TA = 125oC
25oC
0.01
-55oC
0.001
0.0001
0
1
1.5
2
2.5
3
3.5
0.0
4
0.2
0.4
0.6
0.8
1.0
1.2
-VGS, GATE TO SOURCE VOLTAGE (V)
-VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 5. Transfer Characteristics
Figure 6. Body Diode Forward Voltage Variation with
Source Current and Temperature
© 2002 Fairchild Semiconductor Corporation
BSS84 • Rev. 1.1.0
www.fairchildsemi.com
3
100
VDS = -8V
ID = -0.10A
f = 1 MHz
VGS = 0 V
-25V
4
80
-30V
CAPACITANCE (pF)
-VGS, GATE-SOURCE VOLTAGE (V)
5
3
2
1
CISS
60
40
20
COSS
CRSS
0
0
0
0.2
0.4
0.6
0.8
1
0
10
Qg, GATE CHARGE (nC)
20
30
40
50
-VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure 7. Gate Charge Characteristics
Figure 8. Capacitance Characteristics
P(pk), PEAK TRANSIENT POWER (W)
5
SINGLE PULSE
RθJA = 350캜 /W
TA = 25캜
4
3
2
1
0
0.01
0.1
1
10
100
t1, TIME (sec)
r(t), NORMALIZED EFFECTIVE TRANSIENT
THERMAL RESISTANCE
Figure 9. Maximum Safe Operating Area
BSS84 — P-Channel Enhancement Mode Field-Effect Transistor
Typical Characteristics (Continued)
Figure 10. Single-Pulse Maximum Power
Dissipation
1
D = 0.5
RθJA(t) = r(t) * RθJA
o
0.2
0.1
RθJA = 350 C/W
0.1
P(pk)
0.05
0.02
0.01
t1
t2
0.01
TJ - TA = P * RθJA(t)
Duty Cycle, D = t1 / t2
SINGLE PULSE
0.001
0.0001
0.001
0.01
0.1
1
10
100
1000
t1, TIME (sec)
Figure 11. Transient Thermal Response Curve
Thermal characterization performed using the conditions described on page 1.
Transient thermal response will change depending on the circuit board design.
© 2002 Fairchild Semiconductor Corporation
BSS84 • Rev. 1.1.0
www.fairchildsemi.com
4
BSS84 — P-Channel Enhancement Mode Field-Effect Transistor
Physical Dimension
SOT-23 3L
Figure 12. 3-LEAD, SOT23, JEDEC TO-236, LOW PROFILE
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
For current tape and reel specifications, visit Fairchild Semiconductor’s online packaging area:
http://www.fairchildsemi.com/packaging/tr/SOT23-3L_tr.pdf.
© 2002 Fairchild Semiconductor Corporation
BSS84 • Rev. 1.1.0
www.fairchildsemi.com
5
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BSS84 — P-Channel Enhancement Mode Field-Effect Transistor
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Datasheet contains the design specifications for product development. Specifications may change
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Rev. I64
© 2002 Fairchild Semiconductor Corporation
BSS84 • Rev. 1.1.0
www.fairchildsemi.com
6
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