Features ARM7TDMI™ ARM® Thumb® Processor Core Two 16-bit Fixed-point OakDSPCore® Cores 256 x 32-bit Boot ROM 88K Bytes of Integrated Fast RAM for Each DSP Flexible External Bus Interface with Programmable Chip Selects Dual Codec Interface Multi-level Priority, Individually Maskable, Vectored Interrupt Controller Three 16-bit Timer/Counters Additional Watchdog Timer Two USARTs with FIFO and Modem Control Lines Industry Standard Serial Peripheral Interface (SPI) Up to 23 General-purpose I/O Pins On-chip DRAM Controller JTAG Debug Interface Software Development Suites Available for ARM7TDMI and OakDSPCore Supported by a Wide Range of Ready-to-use Application Software, including Multitasking Operating System, Networking, Modems, and Voice-processing Functions • Available in 160-lead PQFP Package • 3.3V Power Supply • • • • • • • • • • • • • • • • Description The Atmel AT75C310 Smart Internet Appliance Processor (SIAP) is a high-performance processor specially designed for Internet appliance applications, such as Internet telephony (Voice over Internet Protocol – VoIP). The AT75C310 is built around an ARM7TDMI microcontroller core running at 20 MIPS with two DSP co-processors running at 40 MIPS each – all three processors delivering unmatched performance for low power consumption. Smart Internet Appliance Processor – Electrical and Mechanical Characteristics AT75C310 In a typical standalone VoIP phone, one DSP handles the voice-processing functions (voice compression, acoustic echo cancellation, etc.), while the other one deals with the telephony functions (dialing, line echo cancellation, callerID detection, high-speed modem, etc.). In such an application, the power of the ARM7TDMI allows it to run the VoIP protocol stack as well as all the system control tasks. Atmel provides the AT75C310 with three levels of software modules: • a special port of the Linux kernel as the proposed operating system • a comprehensive set of tunable DSP algorithms for modems and voice processing, specially tailored to be run by the DSP subsystems • a broad range of application-level software modules such as H323 telephony or POP-3/SMTP e-mail services Rev. 1370A–07/00 1 Absolute Maximum Ratings* Operating Temperature (Commercial).............0°C to +70°C *NOTICE: Voltage on Any Input Pin with Respect to Ground-..................................0.5V to +4.0V Maximum Operating Voltage..........................................4.6V Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC Characteristics Symbol Parameter Condition Min Typ Max Units VDD DC Supply 3.0 3.3 3.6 V TA Ambient Temperature 0 70 °C VIL Input Low Voltage VDD = 3.0V to 3.6V -0.5 0.3 x VDD V VIH Input High Voltage VDD = 3.0V to 3.6V 0.7 x VDD 3.6 V VOL Output Low Voltage IOL = 0.8 mA, VDD = 3.3V 0.1 V VOH Output High Voltage IOH = 0.8 mA, VDD = 3.3V VDD - 0.1 AC Characteristics Conditions The values are for full temperature range and worst-case process. Environment Constraints The output delays are valid for a capacitive load of 10 pF, as shown in Figure 1. Figure 1. Output/Bidir Pad Capacitive Load CL = 10 pF PAD 2 AT75C310 V AT75C310 Memory Timing Waveforms Figure 2. DRAM Read Cycle (Single Read) tRC tRAS tRP NRASx tCSH tCRP tRCD tRSH tCAS NCASx tASR tRAH tASC tCAH A NDOE tCAC tOEA tAA tOHO tRAC D Table 1. DRAM Read Cycle (Single Read) Timings Symbol Parameter Min (ns) Max (ns) tRC Read or Write Cycle Time 125.0 – tRAS RAS Pulse Width 82.0 – tRP RAS Precharge Time 42.0 – tCSH CAS Hold Time 61.0 – tCRP CAS to RAS Precharge Time 49.0 – tRCD RAS to CAS Delay Time 41.0 – tRSH RAS Hold Time 29.0 – tCAS CAS Pulse Width 20.0 – tASR Row Address Setup Time 1.0 tRAH Row Address Hold Time 22.0 tASC Column Address Setup Time 15.0 tCAH Column Address Hold Time 21.0 tCAC Access Time from CAS – 22.0 tOEA Access Time from NDOE – 34.0 tAA Access Time from Column Address – 38.0 tRAC Access Time from RAS – 63.0 tOHO Data Hold from NDOE 0 – 3 Figure 3. DRAM Read Cycle (Burst Read) NRASx tCPRH tCSH tRCD tCAS tCP tCAS NCASx tASR tRAH tASC tCAH tASC tCAH A NDOE tCAC tCAC tOEA tAA tAA tCPA tRAC tDOH D tOHO Table 2. DRAM Read Cycle (Burst Read) Timings Symbol Parameter Min (ns) Max (ns) tCPRH RAS Hold Time from CAS Precharge 48.0 – tCSH CAS Hold Time 61.0 – tRCD RAS to CAS Delay Time 41.0 – tCAS CAS Pulse Width 20.0 – tCP CAS Precharge Time 19.0 – tASR Row Address Setup Time 1.5 tRAH Row Address Hold Time 22.0 tASC Column Address Setup Time 15.0 tCAH Column Address Hold Time 21.0 tCAC Access Time from CAS – 22.0 tOEA Access Time from NDOE – 34.0 tAA Access Time from Column Address – 38.0 tRAC Access Time from RAS – 63.0 tCPA Access Time from CAS Precharge – 43.0 tOHO Data Hold from NDOE 0 – tDOH Data Hold from CAS Low 0 – 4 AT75C310 AT75C310 Figure 4. DRAM Write Cycle (Single Write) tRC tRAS tRP NRASx tCSH tCRP tRCD tRSH tCAS NCASx tASR tRAH tASC tCAH A tWCS tWCH NDWE tDS tDH D Table 3. DRAM Write Cycle (Single Write) Timings Symbol Parameter Min (ns) Max (ns) tRC Read or Write Cycle Time 125.0 – tRAS RAS Pulse Width 82.0 – tRP RAS Precharge Time 42.0 – tCSH CAS Hold Time 61.0 – tCRP CAS to RAS Precharge Time 49.0 – tRCD RAS to CAS Delay Time 41.0 – tRSH RAS Hold Time 29.0 – tCAS CAS Pulse Width 20.0 – tASR Row Address Setup Time 1.5 – tRAH Row Address Hold Time 22.0 – tASC Column Address Setup Time 15.0 – tCAH Column Address Hold Time 21.0 – tWCS Write Command Setup Time 18.0 – tWCH Write Command Hold Time 21.0 – tDS Data Setup Time 8.0 – tDH Data Hold Time 21.0 – 5 Figure 5. DRAM Refresh Cycle tRC tRP tRAS tRP NRASx tRPC tCP tCSR tCHR tCRP NCASx tWRP tWRH NDWE Table 4. DRAM Refresh Cycle Timings Symbol Parameter Min (ns) Max (ns) tRC Cycle Time 125.0 – tRAS RAS Pulse Width 82.0 – tRP RAS Precharge Time 42.0 – tCP CAS Precharge Time 19.0 – tRPC RAS Precharge before CAS 33.0 – tCSR CAS Setup before RAS 48.0 – tCHR CAS Hold after RAS 32.0 – tCRP CAS to RAS Precharge Time 49.0 – tWRP Write Enable Setup Time (Refresh Cycle) 91.0 – tWRH Write Enable Hold Time (Refresh Cycle) 32.0 – 6 AT75C310 AT75C310 Figure 6. Static Memory Read Cycle (Zero Wait State) tCSLCSH NCEx A tRLRH NSOE (Standard Read Mode) NSOE (Early Read Mode) NWEx (Byte Select Mode) tRLDV1 tCSLDV tRLDV 2 tRHCSH tAVDV tRHBSH tRHAH tRHDH tBSLDV D Table 5. Static Memory Read Cycle (Zero Wait State) Timings Symbol Parameter Min (ns) Max (ns) tCSLCSH Chip Select Low to Chip Select High Time 40.0 – tRLRH Read Strobe Low to Read Strobe High Time 19.0 – tRLDV1 Read Strobe Low to Data Valid Time – Standard Read Mode – 6.0 tRLDV2 Read Strobe Low to Data Valid Time – Early Read Mode – 27.0 tCSLDV Chip Select Low to Data Valid – 25.0 tAVDV Address Valid to Data Valid – 24.0 tBSLDV Byte Select Low to Data Valid – 26.0 tRHCSH Read Strobe High to Chip Select High 0 – tRHAH Address Hold after Read Strobe High 0 – tRHBSH Read Strobe High to Byte Select High 0 – tRHDH Data Hold after Read Strobe High 0 – 7 Figure 7. Static Memory Write Cycle (Zero Wait State) tCSLCSH NCEx A NWEx (Byte Select Mode) tCSLWL tWHCSH tAVWL tWHAH tBSLWL NWR/NWEx (Byte Write Mode) tWHBSH tWLWH tDSUWH tWHDH D Table 6. Static Memory Write Cycle (Zero Wait State) Timings Symbol Parameter Min (ns) Max (ns) tCSLCSH Chip Select Low to Chip Select High Time 40.0 – tCSLWL Chip Select Low to Write Stobe Low Time 18.0 – tAVWL Address Valid to Write Strobe Low Time 17.0 – tBSLWL Byte Select Low to Write Strobe Low Time 19.0 – tWHCSH Write Strobe High to Chip Select High Time 3.0 – tWHAH Address Hold Time after Write Strobe High 4.0 – tWHBSH Write Strobe High to Byte Strobe High Time 0 – tWLWH Write Strobe Low to Write Strobe High Time 17.0 – tDSUWH Data Setup Time before Write Strobe High 13.0 – tWHDH Data Hold Time after Write Strobe High 3.0 – 8 AT75C310 AT75C310 Figure 8. Static Memory Write Cycle (One Wait State) tCSLCSH NCEx A NWEx (Byte Select Mode) tCSLWL tWHCSH tAVWL tWHAH tBSLWL NWR/NWEx (Byte Write Mode) tWHBSH tWLWH tDSUWH tWHDH D Table 7. Static Memory Write Cycle (One Wait State) Timings Symbol Parameter Min (ns) Max (ns) tCSLCSH Chip Select Low to Chip Select High Time 82.0 – tCSLWL Chip Select Low to Write Stobe Low Time 20.0 – tAVWL Address Valid to Write Strobe Low Time 19.0 – tBSLWL Byte Select Low to Write Strobe Low Time 20.0 – tWHCSH Write Strobe High to Chip Select High Time 19.0 – tWHAH Address Hold Time after Write Strobe High 20.0 – tWHBSH Write Strobe High to Byte Strobe High Time 19.0 – tWLWH Write Strobe Low to Write Strobe High Time 40.0 – tDSUWH Data Setup Time before Write Strobe High 38.0 – tWHDH Data Hold Time after Write Strobe High 20.0 Note: Additional wait states will extend the tWLWH and tDSUWH values by one clock period per wait state. – 9 Figure 9. Static Memory Write Cycle (LCD Mode, Two Wait States) tCSLCSH NCE3 tAVCSL tCSHAH tAVWL tWHAH A tWLWH NWR/NWEx tDVCSH tCSHDH tDVWH tWHDH D Table 8. Static Memory Write Cycle (LCD Mode, Two Wait States Timings Symbol Parameter Min (ns) Max (ns) tCSLCSH Chip Select Low to Chip Select High Time 82.0 – tAVCSL Address Valid to Chip Select Low Time 18.0 – tAVWL Address Valid to Write Strobe Low Time 19.0 – tCSHAH Address Hold Time after Chip Select High 21.0 – tWHAH Address Hold Time after Write Strobe High 20.0 – tWLWH Write Strobe Low to Write Strobe High Time 81.0 – tDVCSH Data Setup Time before Chip Select High 79.0 – tDVWH Data Setup Time before Write Strobe High 79.0 – tCSHDH Data Hold Time after Write Chip Select High 21.0 – tWHDH Data Hold Time after Write Strobe High 20.0 – 10 AT75C310 AT75C310 Figure 10. Static Memory Read Cycle (LCD Mode, Two Wait States) tCSLCSH NCE3 tAVCSL tCSHAH A tRLRH NSOE (Standard Read Mode) NSOE (Early Read Mode) tRLDV1 tRHAH tCSLDV tRHDH tAVDV tRLDV2 tCSHDH D Table 9. Static Memory Read Cycle (LCD Mode, Two Wait States) Timings Symbol Parameter Min (ns) Max (ns) tCSLCSH Chip Select Low to Chip Select High Time 82.0 – tAVCSL Address Valid to Chip Select Low 18.0 – tCSHAH Address Hold after Chip Select High 21.0 – tRLRH Read Strobe Low to Read Strobe High Time 102.0 tRLDV1 Read Strobe Low to Data Valid Time – Standard Read Mode – 89.0 tRLDV2 Read Strobe Low to Data Valid Time – Early Read Mode – 110.0 tCSLDV Chip Select Low to Data Valid – 88.0 tAVDV Address Valid to Data Valid – 107.0 tRHAH Address Hold after Read Strobe High 1.0 – tRHDH Data Hold after Read Strobe High 0 – tCSHDH Data Hold after Chip Select High 18.0 – 11 External Bus Master Timing Figure 11. External Bus Master NREQ NGNT tGHADC tGLADCZ Address, Data & Control Table 10. External Bus Master Timings Symbol Parameter tGLADCZ NGNT Low to Address, Data & Control Float tGHADC NGNT High to Address, Data & Control Driven 12 AT75C310 Min (ns) Max (ns) 2.0 – 0 – AT75C310 Codec Timing Waveforms Figure 12. FS and SCLK as Outputs tSCLK SSCLK FS tFSV tFSH STX tSTXV SRX tSRXS tRSXH Table 11. FS and SCLK as Outputs Timings Symbol Parameter Min (ns) Max (ns) tFSV FS Valid after TX Edge of SSCLK (Long PCM Type) – 75.0 FS Valid after TX Edge of SSCLK (All Other Types) – 50.0 FS Output Hold after Last RX Edge of SSCLK (Long PCM) 49.0 – FS Output Hold after Last RX Edge of SSCLK (All Other Types) 25.0 – tSTXV STX Valid after TX Edge of SSCLK 22.0 25.0 tSRXS SRX Setup before RX Edge of SSCLK 50.0 – tRSXH SRX Hold after RX Edge of SSCLK 0 – tFSH tSCLK Note: SSCLK Generated Period 100.0 All timings based on worst-case conditions of Codec A or B interface and so apply to both. 6375.0 13 Figure 13. FS and SCLK as Inputs tFSH tSCLK SSCLK FS tFSS STX tSTXV SRX tSRXS tRSXH Table 12. FS and SCLK as Inputs Timings Symbol Parameter Min (ns) Max (ns) tFSS FS Setup before RX Edge of SSCLK 75.0 – tFSH FS Hold after First RX Edge of SSCLK 0 – tSTXV STX Valid after TX Edge of SSCLK 50.0 80.0 tSRXS SRX Setup before RX Edge of SSCLK 25.0 – tRSXH SRX Hold after RX Edge of SSCLK 25.0 – tSCLK SSCLK Input Period 200.0 – 14 AT75C310 AT75C310 Packaging Information Figure 14. SQFP Package Drawing 1 C C 1 Table 13. Package Dimensions for 160-lead SQFP Package (mm) Symbol Min c 0.11 c1 0.11 L 0.65 L1 Nom Max Symbol Min 0.23 A 4.10 0.15 0.19 A1 0.25 0.88 1.03 A2 3.20 b 0.29 b1 0.29 1.60 REF 0.3 Nom 0.50 3.40 0.13 R1 0.13 D 31.20 S 0.4 D1 28.00 E 31.20 E1 28.00 e 0.65 ddd 0.12 aaa ccc 0.25 0.1 3.60 0.45 R2 Tolerances of Form and Position Max 0.35 0.41 Thermal Resistance Thermal Resistance = 33C°/W 15 Ordering Information 16 Speed (MHz) Power Supply Ordering Code 20 3.3V AT75C310-Q160 AT75C310 Package PQFP160 Operation Range Commercial (0° to 70°C) Atmel Headquarters Atmel Operations Corporate Headquarters Atmel Colorado Springs 2325 Orchard Parkway San Jose, CA 95131 TEL (408) 441-0311 FAX (408) 487-2600 Europe Atmel U.K., Ltd. Coliseum Business Centre Riverside Way Camberley, Surrey GU15 3YL England TEL (44) 1276-686-677 FAX (44) 1276-686-697 1150 E. Cheyenne Mtn. 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The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life suppor t devices or systems. Marks bearing ® and/or ™ are registered trademarks and trademarks of Atmel Corporation. ARM, Thumb and ARM Powered are registered trademarks of ARM Limited. ARM7TDMI is a trademark of ARM Ltd. Printed on recycled paper. 1370A–07/00/0M OakDSPCore is a registered trademark of DSP Group, Inc. Terms and product names in this document may be trademarks of others.