AD AD8138ARMZ-REEL7 Low distortion differential adc driver Datasheet

Low Distortion
Differential ADC Driver
AD8138
PIN CONFIGURATION
–IN 1
8
+IN
VOCM 2
7
NC
V+ 3
6
V–
5
–OUT
+OUT 4
AD8138
NC = NO CONNECT
Figure 1.
TYPICAL APPLICATION CIRCUIT
5V
5V
499Ω
VIN
499Ω
VOCM
499Ω
+
AIN
AD8138
DVDD
DIGITAL
OUTPUTS
ADC
AIN
–
AVDD
AVSS
VREF
01073-002
Easy to use, single-ended-to-differential conversion
Adjustable output common-mode voltage
Externally adjustable gain
Low harmonic distortion
−94 dBc SFDR @ 5 MHz
−85 dBc SFDR @ 20 MHz
−3 dB bandwidth of 320 MHz, G = +1
Fast settling to 0.01% of 16 ns
Slew rate 1150 V/μs
Fast overdrive recovery of 4 ns
Low input voltage noise of 5 nV/√Hz
1 mV typical offset voltage
Wide supply range +3 V to ±5 V
Low power 90 mW on 5 V
0.1 dB gain flatness to 40 MHz
Available in 8-Lead SOIC and MSOP packages
01073-001
FEATURES
499Ω
Figure 2.
APPLICATIONS
ADC drivers
Single-ended-to-differential converters
IF and baseband gain blocks
Differential buffers
Line drivers
GENERAL DESCRIPTION
The AD8138 is a major advancement over op amps for
differential signal processing. The AD8138 can be used as a
single-ended-to-differential amplifier or as a differential-todifferential amplifier. The AD8138 is as easy to use as an op
amp and greatly simplifies differential signal amplification and
driving. Manufactured on ADI’s proprietary XFCB bipolar
process, the AD8138 has a −3 dB bandwidth of 320 MHz and
delivers a differential signal with the lowest harmonic distortion
available in a differential amplifier. The AD8138 has a unique
internal feedback feature that provides balanced output gain
and phase matching, suppressing even order harmonics. The
internal feed-back circuit also minimizes any gain error that
would be associated with the mismatches in the external gain
setting resistors.
The AD8138’s differential output helps balance the input to
differential ADCs, maximizing the performance of the ADC.
The AD8138 eliminates the need for a transformer with high
performance ADCs, preserving the low frequency and dc information. The common-mode level of the differential output is
adjustable by a voltage on the VOCM pin, easily level-shifting the
input signals for driving single-supply ADCs. Fast overload
recovery preserves sampling accuracy.
The AD8138 distortion performance makes it an ideal ADC
driver for communication systems, with distortion performance
good enough to drive state-of-the-art 10-bit to 16-bit converters
at high frequencies. The AD8138’s high bandwidth and IP3 also
make it appropriate for use as a gain block in IF and baseband
signal chains. The AD8138 offset and dynamic performance
makes it well suited for a wide variety of signal processing and
data acquisition applications.
The AD8138 is available in both SOIC and MSOP packages for
operation over −40°C to +85°C temperatures.
Rev. F
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
AD8138
TABLE OF CONTENTS
Features .............................................................................................. 1
Theory of Operation ...................................................................... 17
Applications....................................................................................... 1
Analyzing an Application Circuit ............................................ 17
Pin Configuration............................................................................. 1
Setting the Closed-Loop Gain .................................................. 17
Typical Application Circuit ............................................................. 1
Estimating the Output Noise Voltage ...................................... 17
General Description ......................................................................... 1
The Impact of Mismatches in the Feedback Networks ......... 18
Revision History ............................................................................... 2
Calculating an Application Circuit’s Input Impedance......... 18
Specifications..................................................................................... 3
Input Common-Mode Voltage Range in Single-Supply
Applications ................................................................................ 18
±DIN to ±OUT Specifications...................................................... 3
VOCM to ±OUT Specifications ..................................................... 4
±DIN to ±OUT Specifications...................................................... 5
VOCM to ±OUT Specifications ..................................................... 6
Absolute Maximum Ratings............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Typical Performance Characteristics ............................................. 9
Setting the Output Common-Mode Voltage .......................... 18
Driving a Capacitive Load......................................................... 18
Layout, Grounding, and Bypassing.............................................. 19
Balanced Transformer Driver ....................................................... 20
High Performance ADC Driving ................................................. 21
3 V Operation ................................................................................. 22
Outline Dimensions ....................................................................... 23
Ordering Guide .......................................................................... 23
Test Circuits..................................................................................... 15
Operational Description................................................................ 16
Definition of Terms.................................................................... 16
REVISION HISTORY
1/06—Rev. E to Rev. F
Changes to Features.......................................................................... 1
Added Thermal Resistance Section and Maximum Power
Dissipation Section........................................................................... 7
Changes to Balanced Transformer Driver Section..................... 20
Changes to Ordering Guide .......................................................... 23
7/02—Rev. C to Rev. D
Addition of TPC 35 and TPC 36 .....................................................8
6/01—Rev. B to Rev. C
Edits to Specifications ......................................................................2
Edits to Ordering Guide ...................................................................4
12/00—Rev. A to Rev. B
9/99—Rev. 0 to Rev. A
3/03—Rev. D to Rev. E
Changes to Specifications ................................................................ 2
Changes to Ordering Guide ............................................................ 4
Changes to TPC 16........................................................................... 6
Changes to Table I ............................................................................ 9
Added New Paragraph after Table I ............................................. 10
Updated Outline Dimensions ....................................................... 14
3/99—Rev. 0: Initial Version
Rev. F | Page 2 of 24
AD8138
SPECIFICATIONS
±DIN to ±OUT SPECIFICATIONS
At 25°C, VS = ±5 V, VOCM = 0, G = +1, RL, dm = 500 Ω, unless otherwise noted. Refer to Figure 39 for test setup and label descriptions. All
specifications refer to single-ended input and differential outputs, unless otherwise noted.
Table 1.
Parameter
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth
Bandwidth for 0.1 dB Flatness
Large Signal Bandwidth
Slew Rate
Settling Time
Overdrive Recovery Time
NOISE/HARMONIC PERFORMANCE 1
Second Harmonic
Third Harmonic
IMD
IP3
Voltage Noise (RTI)
Input Current Noise
INPUT CHARACTERISTICS
Offset Voltage
Conditions
Min
Typ
VOUT = 0.5 V p-p, CF = 0 pF
VOUT = 0.5 V p-p, CF = 1 pF
VOUT = 0.5 V p-p, CF = 0 pF
VOUT = 2 V p-p, CF = 0 pF
VOUT = 2 V p-p, CF = 0 pF
0.01%, VOUT = 2 V p-p, CF = 1 pF
VIN = 5 V to 0 V step, G = +2
290
320
225
30
265
1150
16
4
MHz
MHz
MHz
MHz
V/μs
ns
ns
−94
−87
−62
−114
−85
−57
−77
37
5
2
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBm
nV/√Hz
pA/√Hz
VOUT = 2 V p-p, 5 MHz, RL, dm = 800 Ω
VOUT = 2 V p-p, 20 MHz, RL, dm = 800 Ω
VOUT = 2 V p-p, 70 MHz, RL, dm = 800 Ω
VOUT = 2 V p-p, 5 MHz, RL, dm = 800 Ω
VOUT = 2 V p-p, 20 MHz, RL, dm = 800 Ω
VOUT = 2 V p-p, 70 MHz, RL, dm = 800 Ω
20 MHz
20 MHz
f = 100 kHz to 40 MHz
f = 100 kHz to 40 MHz
VOS, dm = VOUT, dm/2; VDIN+ = VDIN− = VOCM = 0 V
TMIN to TMAX variation
Input Bias Current
Input Resistance
Input Capacitance
Input Common-Mode Voltage
CMRR
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Current
Output Balance Error
1
TMIN to TMAX variation
Differential
Common mode
∆VOUT, dm/∆VIN, cm; ∆VIN, cm = ±1 V
Maximum ∆VOUT; single-ended output
∆VOUT, cm/∆VOUT, dm; ∆VOUT, dm = 1 V
−2.5
±1
±4
3.5
−0.01
6
3
1
−4.7 to +3.4
−77
7.75
95
−66
Harmonic distortion performance is equal or slightly worse with higher values of RL, dm. See Figure 17 and Figure 18 for more information.
Rev. F | Page 3 of 24
Max
+2.5
7
−70
Unit
mV
μV/°C
μA
μA/°C
MΩ
MΩ
pF
V
dB
V p-p
mA
dB
AD8138
VOCM to ±OUT SPECIFICATIONS
At 25°C, VS = ±5 V, VOCM = 0, G = +1, RL, dm = 500 Ω, unless otherwise noted. Refer to Figure 39 for test setup and label descriptions. All
specifications refer to single-ended input and differential outputs, unless otherwise noted.
Table 2.
Parameter
DYNAMIC PERFORMANCE
−3 dB Bandwidth
Slew Rate
INPUT VOLTAGE NOISE (RTI)
DC PERFORMANCE
Input Voltage Range
Input Resistance
Input Offset Voltage
Input Bias Current
VOCM CMRR
Gain
POWER SUPPLY
Operating Range
Quiescent Current
Power Supply Rejection Ratio
OPERATING TEMPERATURE RANGE
Conditions
Min
f = 0.1 MHz to 100 MHz
VOS, cm = VOUT, cm; VDIN+ = VDIN– = VOCM = 0 V
–3.5
∆VOUT, dm/∆VOCM; ∆VOCM = ±1 V
∆VOUT, cm/∆VOCM; ∆VOCM = ±1 V
0.9955
±1.4
18
TMIN to TMAX variation
∆VOUT, dm/∆VS; ∆VS = ±1 V
−40
Rev. F | Page 4 of 24
Typ
Max
Unit
250
330
17
MHz
V/μs
nV/√Hz
±3.8
200
±1
0.5
−75
1
V
kΩ
mV
μA
dB
V/V
20
40
−90
+3.5
1.0045
±5.5
23
−70
+85
V
mA
μA/°C
dB
°C
AD8138
±DIN to ±OUT SPECIFICATIONS
At 25°C, VS = 5 V, VOCM = 2.5 V, G = +1, RL, dm = 500 Ω, unless otherwise noted. Refer to Figure 39 for test setup and label descriptions. All
specifications refer to single-ended input and differential output, unless otherwise noted.
Table 3.
Parameter
DYNAMIC PERFORMANCE
−3 dB Small Signal Bandwidth
Bandwidth for 0.1 dB Flatness
Large Signal Bandwidth
Slew Rate
Settling Time
Overdrive Recovery Time
NOISE/HARMONIC PERFORMANCE 1
Second Harmonic
Third Harmonic
IMD
IP3
Voltage Noise (RTI)
Input Current Noise
INPUT CHARACTERISTICS
Offset Voltage
Conditions
Min
Typ
VOUT = 0.5 V p-p, CF = 0 pF
VOUT = 0.5 V p-p, CF = 1 pF
VOUT = 0.5 V p-p, CF = 0 pF
VOUT = 2 V p-p, CF = 0 pF
VOUT = 2 V p-p, CF = 0 pF
0.01%, VOUT = 2 V p-p, CF = 1 pF
VIN = 2.5 V to 0 V step, G = +2
280
310
225
29
265
950
16
4
MHz
MHz
MHz
MHz
V/μs
ns
ns
−90
−79
−60
−100
−82
−53
−74
35
5
2
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBm
nV/√Hz
pA/√Hz
VOUT = 2 V p-p, 5 MHz, RL, dm = 800 Ω
VOUT = 2 V p-p, 20 MHz, RL, dm = 800 Ω
VOUT = 2 V p-p, 70 MHz, RL, dm = 800 Ω
VOUT = 2 V p-p, 5 MHz, RL, dm = 800 Ω
VOUT = 2 V p-p, 20 MHz, RL, dm = 800 Ω
VOUT = 2 V p-p, 70 MHz, RL, dm = 800 Ω
20 MHz
20 MHz
f = 100 kHz to 40 MHz
f = 100 kHz to 40 MHz
VOS, dm = VOUT, dm/2; VDIN+ = VDIN– = VOCM = 0 V
TMIN to TMAX variation
Input Bias Current
Input Resistance
Input Capacitance
Input Common-Mode Voltage
CMRR
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Current
Output Balance Error
1
TMIN to TMAX variation
Differential
Common mode
∆VOUT, dm/∆VIN, cm; ∆VIN, cm = 1 V
Maximum ∆VOUT; single-ended output
∆VOUT, cm/∆VOUT, dm; ∆VOUT, dm = 1 V
−2.5
±1
±4
3.5
−0.01
6
3
1
−0.3 to +3.2
−77
2.9
95
−65
Harmonic distortion performance is equal or slightly worse with higher values of RL, dm. See Figure 17 and Figure 18 for more information.
Rev. F | Page 5 of 24
Max
+2.5
7
−70
Unit
mV
μV/°C
μA
μA/°C
MΩ
MΩ
pF
V
dB
V p-p
mA
dB
AD8138
VOCM TO ±OUT SPECIFICATIONS
At 25°C, VS = 5 V, VOCM = 2.5 V, G = +1, RL, dm = 500 Ω, unless otherwise noted. Refer to Figure 39 for test setup and label descriptions. All
specifications refer to single-ended input and differential output, unless otherwise noted.
Table 4.
Parameter
DYNAMIC PERFORMANCE
−3 dB Bandwidth
Slew Rate
INPUT VOLTAGE NOISE (RTI)
DC PERFORMANCE
Input Voltage Range
Input Resistance
Input Offset Voltage
Input Bias Current
VOCM CMRR
Gain
POWER SUPPLY
Operating Range
Quiescent Current
Power Supply Rejection Ratio
OPERATING TEMPERATURE RANGE
Conditions
Min
f = 0.1 MHz to 100 MHz
VOS, cm = VOUT, cm; VDIN+ = VDIN– = VOCM = 0 V
−5
∆VOUT, dm/∆VOCM; ∆VOCM = 2.5 V ±1 V
∆VOUT, cm/∆VOCM; ∆VOCM = 2.5 V ±1 V
0.9968
2.7
15
TMIN to TMAX variation
∆VOUT, dm/∆VS; ∆VS = ± 1 V
−40
Rev. F | Page 6 of 24
Typ
Max
Unit
220
250
17
MHz
V/μs
nV/√Hz
1.0 to 3.8
100
±1
0.5
−70
1
V
kΩ
mV
μA
dB
V/V
20
40
−90
+5
1.0032
11
21
−70
+85
V
mA
μA/°C
dB
°C
AD8138
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter
Supply Voltage
VOCM
Internal Power Dissipation
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering 10 sec)
Junction Temperature
Ratings
±5.5 V
±VS
550 mW
−40°C to +85°C
−65°C to +150°C
300°C
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, θJA is
specified for the device soldered in a circuit board in still air.
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the
package due to the load drive for all outputs. The quiescent
power is the voltage between the supply pins (VS) times the
quiescent current (IS). The load current consists of the differential
and common-mode currents flowing to the load, as well as
currents flowing through the external feedback networks and
internal common-mode feedback loop. The internal resistor tap
used in the common-mode feedback loop places a negligible
differential load on the output. RMS voltages and currents
should be considered when dealing with ac signals.
Airflow reduces θJA. In addition, more metal directly in contact
with the package leads from metal traces through holes, ground,
and power planes reduces the θJA.
Figure 3 shows the maximum safe power dissipation in the
package vs. the ambient temperature for the 8-lead SOIC
(121°C/W) and 8-lead MSOP (θJA = 145°C/W) packages on a
JEDEC standard 4-layer board. θJA values are approximations.
1.75
θJA
121
145
Unit
°C/W
°C/W
Maximum Power Dissipation
The maximum safe power dissipation in the AD8138 packages
is limited by the associated rise in junction temperature (TJ) on
the die. At approximately 150°C, which is the glass transition
temperature, the plastic changes its properties. Even temporarily
exceeding this temperature limit can change the stresses that the
package exerts on the die, permanently shifting the parametric
performance of the AD8138. Exceeding a junction temperature
of 150°C for an extended period can result in changes in the
silicon devices, potentially causing failure.
1.50
1.25
1.00
SOIC
0.75
MSOP
0.50
0.25
0
–40 –30 –20 –10
0
10
20
30
40
50
70
80
90 100 110 120
Figure 3. Maximum Power Dissipation vs. Temperature
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. F | Page 7 of 24
60
AMBIENT TEMPERATURE (°C)
01073-049
Package Type
8-Lead SOIC/4-Layer
8-Lead MSOP/4-Layer
MAXIMUM POWER DISSIPATION (W)
Table 6.
AD8138
–IN 1
8
+IN
VOCM 2
7
NC
V+ 3
6
V–
5
–OUT
+OUT 4
AD8138
NC = NO CONNECT
01073-004
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 4. Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
1
2
Mnemonic
−IN
VOCM
3
4
5
6
7
8
V+
+OUT
−OUT
V−
NC
+IN
Description
Negative Input Summing Node.
Voltage applied to this pin sets the common-mode output voltage with a ratio of 1:1. For example,
1 V dc on VOCM sets the dc bias level on +OUT and −OUT to 1 V.
Positive Supply Voltage.
Positive Output. Note that the voltage at −DIN is inverted at +OUT (see Figure 42).
Negative Output. Note that the voltage at +DIN is inverted at −OUT (see Figure 42).
Negative Supply Voltage.
No Connect.
Positive Input Summing Node.
Rev. F | Page 8 of 24
AD8138
TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise noted, Gain = 1, RG = RF = RL, dm = 499 V, TA = 25°C; refer to Figure 39 for test setup.
6
6
VIN = 0.2V p-p
CF = 0pF
3
VIN = 2V p-p
CF = 0pF
3
VS = +5V
0
GAIN (dB)
VS = ±5V
–3
–6
0
VS = ±5V
–3
1
10
100
FREQUENCY (MHz)
1000
–9
01073-005
–9
1
Figure 5. Small Signal Frequency Response
10
100
FREQUENCY (MHz)
Figure 8. Large Signal Frequency Response
6
6
VS = ±5V
VIN = 0.2V p-p
VIN = 2V p-p
VS = ±5V
3
3
CF = 0pF
0
GAIN (dB)
CF = 1pF
–3
0
CF = 1pF
–3
–6
–6
1
10
100
FREQUENCY (MHz)
1000
–9
01073-006
–9
1
Figure 6. Small Signal Frequency Response
10
100
FREQUENCY (MHz)
Figure 9. Large Signal Frequency Response
0.5
30
VS = ±5V
VIN = 0.2V p-p
CF = 0pF
G = 10, RF = 4.99kΩ
20
VS = ±5V
CF = 0pF
VOUT, dm = 0.2V p-p
RG = 499Ω
G = 5, RF = 2.49kΩ
GAIN (dB)
0.1
–0.1
10
G = 2, RF = 1kΩ
CF = 1pF
G = 1, RF = 499Ω
0
–0.3
1
10
FREQUENCY (MHz)
100
01073-007
GAIN (dB)
0.3
1000
01073-009
GAIN (dB)
CF = 0pF
–0.5
1000
01073-008
–6
Figure 7. 0.1 dB Flatness vs. Frequency
–10
1
10
100
FREQUENCY (MHz)
1000
Figure 10. Small Signal Frequency Response for Various Gains
Rev. F | Page 9 of 24
01073-010
GAIN (dB)
VS = +5V
AD8138
–50
–60
VOUT, dm = 2V p-p
RL = 800Ω
–60
VS = ±5V
RL = 800Ω
HD2 (F = 20MHz)
DISTORTION (dBc)
–70
DISTORTION (dBc)
HD3 (F = 20MHz)
–70
HD2 (VS = +5V)
–80
HD2 (V S = ±5V)
–90
–100
–80
–90
HD2 (F = 5MHz)
–100
HD3 (VS = +5V)
HD3 (F = 5MHz)
–110
–110
10
20
30
40
50
FUNDAMENTAL FREQUENCY (MHz)
60
70
–120
01073-011
0
Figure 11. Harmonic Distortion vs. Frequency
–40
6
–60
VS = 5V
RL = 800Ω
–70
HD2 (F = 20MHz)
DISTORTION (dBc)
HD3 (V S = +5V)
–60
DISTORTION (dBc)
1
2
3
4
5
DIFFERENTIAL OUTPUT VOLTAGE (V p-p)
Figure 14. Harmonic Distortion vs. Differential Output Voltage
VOUT, dm = 4V p-p
RL = 800Ω
–50
0
01073-014
HD3 (VS = ±5V)
–120
–70
HD2 (VS = +5V)
–80
HD2 (V S = ±5V)
–80
HD3 (F = 20MHz)
–90
HD2 (F = 5MHz)
–100
–90
HD3 (F = 5MHz)
0
10
20
30
40
50
FUNDAMENTAL FREQUENCY (MHz)
60
70
–120
01073-012
–110
0
–60
VOUT, dm = 2V p-p
RL = 800Ω
FO = 20MHz
–40
VS = 3V
RL = 800Ω
DISTORTION (dBc)
HD2 (VS = +5V)
–60
HD3 (VS = +5V)
–70
–80
HD3 (VS = ±5V)
–90
HD2 (VS = ±5V)
–100
–4
–3
–2
–1
0
1
VOCM DC OUTPUT (V)
2
3
4
HD3 (F = 20MHz)
HD2 (F = 20MHz)
–80
–90
HD2 (F = 5MHz)
–100
01073-013
DISTORTION (dBc)
–70
–50
4
Figure 15. Harmonic Distortion vs. Differential Output Voltage
Figure 12. Harmonic Distortion vs. Frequency
–30
1
2
3
DIFFERENTIAL OUTPUT VOLTAGE (V p-p)
01073-015
–110
HD3 (VS = ±5V)
–110
0.25
HD3 (F = 5MHz)
0.50
0.75
1.00
1.25
1.50
DIFFERENTIAL OUTPUT VOLTAGE (V p-p)
1.75
Figure 16. Harmonic Distortion vs. Differential Output Voltage
Figure 13. Harmonic Distortion vs. VOCM
Rev. F | Page 10 of 24
01073-016
–100
AD8138
45
–60
RL = 800Ω
VS = 5V
VOUT, dm = 2V p-p
–70
INTERCEPT (dBm)
DISTORTION (dBc)
40
HD2 (F = 20MHz)
–80
HD3 (F = 20MHz)
–90
HD2 (F = 5MHz)
VS = ±5V
35
VS = +5V
30
–100
600
1000
RLOAD (Ω)
1400
25
01073-017
–110
200
1800
0
Figure 17. Harmonic Distortion vs. RLOAD
20
40
FREQUENCY (MHz)
Figure 20. Third-Order Intercept vs. Frequency
–60
VS = ±5V
VS = ±5V
VOUT, dm = 2V p-p
–70
VOUT, dm
HD3 (F = 20MHz)
VOUT–
–90
VOUT+
HD2 (F = 5MHz)
–100
V+DIN
HD3 (F = 5MHz)
–110
600
1000
RLOAD (Ω)
1400
5ns
01073-018
1V
–120
200
01073-021
DISTORTION (dBc)
HD2 (F = 20MHz)
–80
80
60
1800
Figure 21. Large Signal Transient Response
Figure 18. Harmonic Distortion vs. RLOAD
10
FC = 50MHz
VS = ±5V
CF = 0pF
VOUT, dm = 0.2V p-p
VS = ±5V
–10
CF = 1pF
–50
–90
40mV
–110
49.5
49.7
49.9
50.1
FREQUENCY (MHz)
50.3
50.5
5ns
Figure 22. Small Signal Transient Response
Figure 19. Intermodulation Distortion
Rev. F | Page 11 of 24
01073-022
–70
01073-019
POUT (dBm)
–30
01073-020
HD3 (F = 5MHz)
AD8138
VOUT, dm = 2V p-p
CF = 0pF
VS = ±5V
VOUT, dm
VS = +5V
VS = ±5V
F = 20MHz
V+DIN = 8V p-p
G = 3 (RF = 1500)
5ns
4V
Figure 23. Large Signal Transient Response
Figure 26. Output Overdrive
VOUT, dm = 2V p-p
VS = ±5V
CF = 0pF
30ns
01073-026
400mV
01073-023
V+DIN
VS = ±5V
CF = 0pF
CL = 10pF
CL = 5pF
CF = 1pF
5ns
Figure 24. Large Signal Transient Response
400mV
2.5ns
01073-028
400mV
01073-024
CL = 20pF
Figure 27. Large Signal Transient Response for Various Cap Loads (See Figure 40)
–20
VS = ±5V
ΔVOUT, dm/ΔVIN, cm
VS = ±5V
CF = 1pF
200µV
–30
VOUT, dm
CMRR (dB)
–40
–50
–60
4ns
01073-025
1V
–80
1
10
100
FREQUENCY (MHz)
Figure 28. CMRR vs. Frequency
Figure 25. Settling Time
Rev. F | Page 12 of 24
1k
01073-029
–70
V+DIN
AD8138
–20
5.0
–40
VS = ±5V
–50
–60
–70
VS = +5V
1
10
100
FREQUENCY (MHz)
1k
Figure 29. Output Balance Error vs. Frequency (See Figure 41)
2.5
VS = ±5V
VS = +5V
0
VS = +3V
–2.5
–5.0
–40
01073-031
BALANCE ERROR (dB)
–30
–20
0
20
40
TEMPERATURE (°C)
60
80
100
01073-034
DIFFERENTIAL OUTPUT OFFSET (mV)
VIN = 2V p-p
Figure 32. Output Referred Differential Offset Voltage vs. Temperature
–10
5
ΔVOUT, dm/ΔVS
–20
4
–PSRR
(VS = ±5V)
–40
BIAS CURRENT (µA)
PSRR (dB)
–30
–50
–60
+PSRR
(VS = +5V, 0V AND ±5V)
–70
VS = ±5V, +5V
3
VS = +3V
2
1
10
100
FREQUENCY (MHz)
1k
1
–40
01073-032
–90
Figure 30. PSRR vs. Frequency
–20
0
20
40
60
TEMPERATURE (°C)
80
100
01073-035
–80
Figure 33. Input Bias Current vs. Temperature
100
30
SINGLE-ENDED OUTPUT
SUPPLY CURRENT (mA)
10
VS = +5V
1
1
10
FREQUENCY (MHz)
VS = +5V
15
VS = +3V
100
5
–40
–20
0
20
40
60
TEMPERATURE (°C)
80
Figure 34. Supply Current vs. Temperature
Figure 31. Output Impedance vs. Frequency
Rev. F | Page 13 of 24
100
01073-036
0.1
VS = ±5V
20
10
VS = ±5V
01073-033
IMPEDANCE (Ω)
25
AD8138
100
6
VS = +5V
–3
–9
1
10
100
FREQUENCY (MHz)
1k
1.1pA/ Hz
1
01073-037
–6
10
10
Figure 35. VOCM Frequency Response
100
1k
10k
FREQUENCY (Hz)
100k
1M
01073-039
0
Figure 37. Current Noise (RTI)
1000
VOUT, cm
400mV
5ns
100
10
5.7nV/ Hz
1
10
Figure 36. VOCM Transient Response
100
1k
10k
FREQUENCY (Hz)
Figure 38. Voltage Noise (RTI)
Rev. F | Page 14 of 24
100k
1M
01073-040
INPUT VOLTAGE NOISE (nV/ Hz)
VS = ±5V
VOCM = –1V TO +1V
01073-038
GAIN (dB)
INPUT CURRENT NOISE (pA/ Hz)
VS = ±5V
3
AD8138
TEST CIRCUITS
499Ω
RG = 499Ω
49.9Ω
RG = 499Ω
24.9Ω
01073-003
24.9Ω
RF = 499Ω
499Ω
24.9Ω
24.9Ω
AD8138
24.9Ω
CL
453Ω
499Ω
01073-027
499Ω
AD8138
249Ω
499Ω
Figure 41. Test Circuit for Output Balance
Figure 39. Basic Test Circuit
49.9Ω
499Ω
249Ω
499Ω
49.9Ω
499Ω
RL, dm = 499Ω
AD8138
Figure 40. Test Circuit for Cap Load Drive
Rev. F | Page 15 of 24
01073-030
RF = 499Ω
AD8138
OPERATIONAL DESCRIPTION
DEFINITION OF TERMS
Common-mode voltage refers to the average of two node
voltages. The output common-mode voltage is defined as
CF
VOUT, cm = (V+OUT + V−OUT)/2
RF
RG
+IN
VOCM
–DIN
–OUT
AD8138
RG
RL, dm
VOUT, dm
+OUT
–IN
RF
CF
01073-041
+DIN
Figure 42. Circuit Definitions
Differential voltage refers to the difference between two node
voltages. For example, the output differential voltage (or
equivalently output differential-mode voltage) is defined as
Balance is a measure of how well differential signals are
matched in amplitude and exactly 180° apart in phase. Balance
is most easily determined by placing a well-matched resistor
divider between the differential voltage nodes and comparing
the magnitude of the signal at the divider’s midpoint with the
magnitude of the differential signal (see Figure 41). By this
definition, output balance is the magnitude of the output
common-mode voltage divided by the magnitude of the output
differential mode voltage:
VOUT, dm = (V+OUT − V−OUT)
where V+OUT and V−OUT refer to the voltages at the +OUT and
−OUT terminals with respect to a common reference.
Rev. F | Page 16 of 24
Output Balance Error =
VOUT , cm
VOUT , dm
AD8138
THEORY OF OPERATION
The AD8138 differs from conventional op amps in that it has
two outputs whose voltages move in opposite directions. Like
an op amp, it relies on high open-loop gain and negative
feedback to force these outputs to the desired voltages. The
AD8138 behaves much like a standard voltage feedback op
amp and makes it easy to perform single-ended-to-differential
conversion, common-mode level-shifting, and amplification of
differential signals. Also like an op amp, the AD8138 has high
input impedance and low output impedance.
Previous differential drivers, both discrete and integrated
designs, have been based on using two independent amplifiers
and two independent feedback loops, one to control each of the
outputs. When these circuits are driven from a single-ended
source, the resulting outputs are typically not well balanced.
Achieving a balanced output has typically required exceptional
matching of the amplifiers and feedback networks.
DC common-mode level-shifting has also been difficult with
previous differential drivers. Level-shifting has required the use
of a third amplifier and feedback loop to control the output
common-mode level. Sometimes the third amplifier has also
been used to attempt to correct an inherently unbalanced
circuit. Excellent performance over a wide frequency range
has proven difficult with this approach.
The AD8138 uses two feedback loops to separately control the
differential and common-mode output voltages. The differential
feedback, set with external resistors, controls only the differential
output voltage. The common-mode feedback controls only the
common-mode output voltage. This architecture makes it easy
to arbitrarily set the output common-mode level. It is forced, by
internal common-mode feedback, to be equal to the voltage
applied to the VOCM input, without affecting the differential
output voltage.
The AD8138 architecture results in outputs that are very highly
balanced over a wide frequency range without requiring tightly
matched external components. The common-mode feedback
loop forces the signal component of the output common-mode
voltage to be zeroed. The result is nearly perfectly balanced
differential outputs of identical amplitude and exactly
180° apart in phase.
ANALYZING AN APPLICATION CIRCUIT
The AD8138 uses high open-loop gain and negative feedback to
force its differential and common-mode output voltages in such
a way as to minimize the differential and common-mode error
voltages. The differential error voltage is defined as the voltage
between the differential inputs labeled +IN and −IN in Figure 42.
For most purposes, this voltage can be assumed to be zero.
Similarly, the difference between the actual output commonmode voltage and the voltage applied to VOCM can also be
assumed to be zero. Starting from these two assumptions, any
application circuit can be analyzed.
SETTING THE CLOSED-LOOP GAIN
Neglecting the capacitors CF, the differential-mode gain of the
circuit in Figure 42 can be determined to be described by
VOUT , dm
VOUT , dm
=
RF S
RG S
This assumes the input resistors, RGS, and feedback resistors, RFS,
on each side are equal.
ESTIMATING THE OUTPUT NOISE VOLTAGE
Similar to the case of a conventional op amp, the differential
output errors (noise and offset voltages) can be estimated by
multiplying the input referred terms, at +IN and −IN, by the
circuit noise gain. The noise gain is defined as
⎛R
GN = 1 + ⎜⎜ F
⎝ RG
⎞
⎟
⎟
⎠
To compute the total output referred noise for the circuit of
Figure 42, consideration must also be given to the contribution
of the Resistors RF and RG. Refer to Table 8 for the estimated
output noise voltage densities at various closed-loop gains.
Table 8.
Gain
1
2
5
10
Rev. F | Page 17 of 24
RG
(Ω)
499
499
499
499
RF
(Ω)
499
1.0 k
2.49 k
4.99 k
Bandwidth
−3 dB
320 MHz
180 MHz
70 MHz
30 MHz
Output
Noise
AD8138
Only
10 nV/√Hz
15 nV/√Hz
30 nV/√Hz
55 nV/√Hz
Output
Noise
AD8138 +
RG , RF
11.6 nV/√Hz
18.2 nV/√Hz
37.9 nV/√Hz
70.8 nV/√Hz
AD8138
CALCULATING AN APPLICATION CIRCUIT’S INPUT
IMPEDANCE
When using the AD8138 in gain configurations where
RF
RG
The effective input impedance of a circuit such as the one in
Figure 42, at +DIN and –DIN, depends on whether the amplifier is
being driven by a single-ended or differential signal source. For
balanced differential input signals, the input impedance (RIN, dm)
between the inputs (+DIN and −DIN) is simply
of one feedback network is unequal to
RF
RG
RIN, dm =2 × RG
of the other network, there is a differential output noise due to
input-referred voltage in the VOCM circuitry. The output noise is
defined in terms of the following feedback terms (refer to
Figure 42):
β1 =
In the case of a single-ended input signal (for example if −DIN is
grounded and the input signal is applied to +DIN), the input
impedance becomes
RG
RF + RG
RIN , dm
for −OUT to +IN loop, and
β2 =
RG
RF + RG
⎛
⎞
⎜
⎟
RG
⎜
⎟
=
RF
⎜1−
⎟
⎜
2 × (RG + RF ) ⎟⎠
⎝
The circuit’s input impedance is effectively higher than it would
be for a conventional op amp connected as an inverter because
a fraction of the differential output voltage appears at the inputs
as a common-mode signal, partially bootstrapping the voltage
across the input resistor RG.
for +OUT to −IN loop. With these defined,
⎡ β − β2 ⎤
VnOUT , dm = 2VnIN ,VOCM ⎢ 1
⎥
⎣⎢ β1 + β2 ⎦⎥
INPUT COMMON-MODE VOLTAGE RANGE IN
SINGLE-SUPPLY APPLICATIONS
where VnOUT, dm is the output differential noise, and VnIN ,VCOM is
the input-referred voltage noise in VOCM.
THE IMPACT OF MISMATCHES IN THE FEEDBACK
NETWORKS
As previously mentioned, even if the external feedback
networks (RF/RG) are mismatched, the internal common-mode
feedback loop still forces the outputs to remain balanced. The
amplitudes of the signals at each output remains equal and 180°
out of phase. The input-to-output differential-mode gain varies
proportionately to the feedback mismatch, but the output
balance is unaffected.
Ratio matching errors in the external resistors result in a
degradation of the circuit’s ability to reject input commonmode signals, much the same as for a four-resistor difference
amplifier made from a conventional op amp.
In addition, if the dc levels of the input and output commonmode voltages are different, matching errors result in a small
differential-mode output offset voltage. For the G = 1 case, with
a ground referenced input signal and the output common-mode
level set for 2.5 V, an output offset of as much as 25 mV (1% of
the difference in common-mode levels) can result if 1% tolerance
resistors are used. Resistors of 1% tolerance result in a worstcase input CMRR of about 40 dB, worst-case differential mode
output offset of 25 mV due to 2.5 V level-shift, and no significant
degradation in output balance error.
The AD8138 is optimized for level-shifting, ground-referenced
input signals. For a single-ended input, this would imply, for
example, that the voltage at −DIN in Figure 42 would be 0 V
when the amplifier’s negative power supply voltage (at V−) is
also set to 0 V.
SETTING THE OUTPUT COMMON-MODE VOLTAGE
The AD8138’s VOCM pin is internally biased at a voltage
approximately equal to the midsupply point (average value of
the voltages on V+ and V−). Relying on this internal bias results
in an output common-mode voltage that is within about
100 mV of the expected value.
In cases where more accurate control of the output commonmode level is required, it is recommended that an external
source, or resistor divider (made up of 10 kΩ resistors), be used.
The output common-mode offset listed in the Specifications
section assumes the VOCM input is driven by a low impedance
voltage source.
DRIVING A CAPACITIVE LOAD
A purely capacitive load can react with the pin and bondwire
inductance of the AD8138, resulting in high frequency ringing
in the pulse response. One way to minimize this effect is to
place a small capacitor across each of the feedback resistors. The
added capacitance should be small to avoid destabilizing the
amplifier. An alternative technique is to place a small resistor in
series with the amplifier’s outputs, as shown in Figure 40.
Rev. F | Page 18 of 24
AD8138
LAYOUT, GROUNDING, AND BYPASSING
As a high speed part, the AD8138 is sensitive to the PCB
environment in which it has to operate. Realizing its superior
specifications requires attention to various details of good high
speed PCB design.
The first requirement is for a good solid ground plane that
covers as much of the board area around the AD8138 as
possible. The only exception to this is that the two input pins
(Pin 1 and Pin 8) should be kept a few millimeters from the
ground plane, and ground should be removed from inner layers
and the opposite side of the board under the input pins. This
minimizes the stray capacitance on these nodes and helps
preserve the gain flatness vs. frequency.
The power supply pins should be bypassed as close as possible
to the device to the nearby ground plane. Good high frequency
ceramic chip capacitors should be used. This bypassing should
be done with a capacitance value of 0.01 μF to 0.1 μF for each
supply. Further away, low frequency bypassing should be provided
with 10 μF tantalum capacitors from each supply to ground.
The signal routing should be short and direct to avoid parasitic
effects. Wherever there are complementary signals, a symmetrical
layout should be provided to the extent possible to maximize
the balance performance. When running differential signals
over a long distance, the traces on the PCB should be close
together or any differential wiring should be twisted together to
minimize the area of the loop that is formed. This reduces the
radiated energy and makes the circuit less susceptible to
interference.
Rev. F | Page 19 of 24
AD8138
BALANCED TRANSFORMER DRIVER
CSTRAY
VUNBAL
52.3Ω PRIMARY
500Ω
0.005%
NO SIGNAL IS COUPLED
ON THIS SIDE
Figure 43. Transformer Single-Ended-to-Differential Converter Is Inherently
Imbalanced
499Ω
The balance of a differential circuit can be measured by
connecting an equal-valued resistive voltage divider across the
differential outputs and then measuring the center point of the
circuit with respect to ground. Since the two differential outputs
are supposed to be of equal amplitude, but 180° opposite phase,
there should be no signal present for perfectly balanced outputs.
499Ω
+IN
CSTRAY
OUT–
VUNBAL
AD8138
499Ω
49.9Ω
500Ω
0.005%
VDIFF
500Ω
0.005%
OUT+
–IN
CSTRAY
499Ω
Figure 44. AD8138 Forms a Balanced Transformer Driver
0
OUTPUT BALANCE ERROR (dB)
Figure 45 compares the transformer being driven singleendedly by a signal generator and being driven differentially
using an AD8138. The top signal trace of Figure 45 shows the
balance of the single-ended configuration, while the bottom
shows the differentially driven balance response. The 100 MHz
balance is 35 dB better when using the AD8138.
SECONDARY V DIFF
CSTRAY
49.9Ω
The circuit in Figure 43 shows a Mini-Circuits® T1-6T
transformer connected with its primary driven single-endedly
and the secondary connected with a precision voltage divider
across its terminals. The voltage divider is made up of two
500 Ω, 0.005% precision resistors. The voltage VUNBAL, which is
also equal to the ac common-mode voltage, is a measure of how
closely the outputs are balanced.
500Ω
0.005%
01073-042
If the interwinding capacitance (CSTRAY) is assumed to be
uniformly distributed, a signal from the driving source couples
to the secondary output terminal that is closest to the primary’s
driven side. On the other hand, no signal is coupled to the
opposite terminal of the secondary because its nearest primary
terminal is not driven (see Figure 43). The exact amount of this
imbalance depends on the particular parasitics of the transformer, but is mostly a problem at higher frequencies.
SIGNAL IS COUPLED
ON THIS SIDE VIA CSTRAY
01073-043
However, when driving the transformer in a single-ended
manner, there is an imbalance at the output due to the parasitics
inherent in the transformer. The primary (or driven) side of the
transformer has one side at dc potential (usually ground), while
the other side is driven. This can cause problems in systems that
require good balance of the transformer’s differential output
signals.
The well-balanced outputs of the AD8138 provide a drive signal
to each of the transformer’s primary inputs that are of equal
amplitude and 180° out of phase. Therefore, depending on how
the polarity of the secondary is connected, the signals that
conduct across the interwinding capacitance either both assist
the transformer’s secondary signal equally, or both buck the
secondary signals. In either case, the parasitic effect is
symmetrical and provides a well-balanced transformer output
(see Figure 45).
–20
–40
VUNBAL , FOR TRANSFORMER
WITH SINGLE-ENDED DRIVE
–60
–80
VUNBAL , DIFFERENTIAL DRIVE
–100
0.3
1
10
FREQUENCY (MHz)
100
500
01073-044
Transformers are among the oldest devices used to perform a
single-ended-to-differential conversion (and vice versa). Transformers can also perform the additional functions of galvanic
isolation, step-up or step-down of voltages, and impedance
transformation. For these reasons, transformers always find
uses in certain applications.
Figure 45. Output Balance Error for Circuits of Figure 43 and Figure 44
Rev. F | Page 20 of 24
AD8138
HIGH PERFORMANCE ADC DRIVING
The circuit in Figure 46 shows a simplified front-end
connection for an AD8138 driving an AD9224, a 12-bit,
40 MSPS ADC. The ADC works best when driven differentially,
which minimizes its distortion. The AD8138 eliminates the
need for a transformer to drive the ADC and performs singleended-to-differential conversion, common-mode level-shifting,
and buffering of the driving signal.
The signal generator has a ground-referenced, bipolar output,
that is, it drives symmetrically above and below ground.
Connecting VOCM to the CML pin of the AD9224 sets the output
common-mode of the AD8138 at 2.5 V, which is the midsupply
level for the AD9224. This voltage is bypassed by a 0.1 μF
capacitor.
The full-scale analog input range of the AD9224 is set to
4 V p-p, by shorting the SENSE terminal to AVSS. This has
been determined to be the scaling to provide minimum
harmonic distortion.
The positive and negative outputs of the AD8138 are connected
to the respective differential inputs of the AD9224 via a pair of
49.9 Ω resistors to minimize the effects of the switched-capacitor
front end of the AD9224. For best distortion performance, it
runs from supplies of ±5 V.
For the AD8138 to swing at 4 V p-p, each output swings 2 V p-p
while providing signals that are 180° out of phase. With a
common-mode voltage at the output of 2.5 V, each AD8138
output swings between 1.5 V and 3.5 V.
The AD8138 is configured with unity gain for a single-ended,
input-to-differential output. The additional 23 Ω, 523 Ω total, at
the input to −IN is to balance the parallel impedance of the
50 Ω source and its 50 Ω termination that drives the
noninverting input.
A ground-referenced 4 V p-p, 5 MHz signal at DIN+ was used to
test the circuit in Figure 46. When the combined-device circuit
was run with a sampling rate of 20 MSPS, the spurious-free
dynamic range (SFDR) was measured at −85 dBc.
+5V
+5V
0.1pF
499Ω
3
499Ω
49.9Ω
0.1pF
2
523Ω
+
5
49.9Ω
24
VINB
15 26
28
AVDD
DRVDD
VOCM
AD8138
1
4
DIGITAL
OUTPUTS
AD9224
49.9Ω
23
6
VINA AVSS
16 25
SENSE CML
17
22
DRVSS
27
499Ω
01073-045
50Ω
SOURCE
8
0.1pF
–5V
Figure 46. AD8138 Driving an AD9224, a 12-Bit, 40 MSPS ADC
Rev. F | Page 21 of 24
AD8138
3 V OPERATION
The circuit in Figure 47 shows a simplified front-end
connection for an AD8138 driving an AD9203, a 10-bit,
40 MSPS ADC that is specified to work on a single 3 V supply.
The ADC works best when driven differentially to make the
best use of the signal swing available within the 3 V supply.
The appropriate outputs of the AD8138 are connected to the
appropriate differential inputs of the AD9203 via a low-pass filter.
The circuit was tested with a −0.5 dBFS signal at various
frequencies. Figure 48 shows a plot of the total harmonic
distortion (THD) vs. frequency at signal amplitudes of 1 V and
2 V differential drive levels.
–40
–45
–50
–55
THD (dBc)
The AD8138 is configured for unity gain for a single-ended
input to differential output. The additional 23 Ω at the input to
−IN is to balance the impedance of the 50 Ω source and its 50 Ω
termination that drives the noninverting input.
AD8138–2V
–60
–65
The signal generator has ground-referenced, bipolar output,
that is, it can drive symmetrically above and below ground.
Even though the AD8138 has ground as its negative supply, it
can still function as a level-shifter with such an input signal.
AD8138–1V
–70
–80
0
The output common mode is raised up to midsupply by the
voltage divider that biases VOCM. In this way, the AD8138
provides dc coupling and level-shifting of a bipolar signal,
without inverting the input signal.
0.1µF
499Ω
Figure 49 shows the signal-to-noise-plus distortion (SINAD)
under the same conditions as above. For the smaller signal
swing, the AD8138 performance is quite good, but its
performance degrades when trying to swing too close to the
supply rails.
63
0.1µF
61
2
+
5
AD8138
4
1
6
49.9Ω
20pF
49.9Ω
20pF
25
2
AVDD
AINN
AINP
26
59
DRVDD
AD9203
AVSS
DRVSS
27
1
DIGITAL
OUTPUTS
499Ω
01073-046
10kΩ
Figure 47. AD8138 Driving an AD9203, a 10-Bit, 40 MSPS A/D Converter
57
AD8138–1V
55
AD8138–2V
53
51
49
47
45
0
5
10
15
FREQUENCY (MHz)
20
Figure 49. AD9203 SINAD @ −0.5 dBFS AD8138
Rev. F | Page 22 of 24
25
01073-048
8
28
SINAD (dBc)
3
523Ω
0.1µF
25
3V
10kΩ
49.9Ω
20
65
3V
499Ω
10
15
FREQUENCY (MHz)
Figure 48. AD9203 THD @ −0.5 dBFS AD8138
The low-pass filter between the AD8138 and the AD9203
provides filtering that helps to improve the signal-to-noise ratio
(SNR). Lower noise can be realized by lowering the pole
frequency, but the bandwidth of the circuit is lowered.
0.1µF
5
01073-047
–75
AD8138
OUTLINE DIMENSIONS
3.20
3.00
2.80
5.00 (0.1968)
4.80 (0.1890)
8
4.00 (0.1574)
3.80 (0.1497) 1
5
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
6.20 (0.2440)
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
COPLANARITY
SEATING 0.31 (0.0122)
0.10
PLANE
8
3.20
3.00
2.80
4 5.80 (0.2284)
0.50 (0.0196)
× 45°
0.25 (0.0099)
1
4
0.65 BSC
1.10 MAX
0.15
0.00
COMPLIANT TO JEDEC STANDARDS MS-012-AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
5.15
4.90
4.65
PIN 1
0.95
0.85
0.75
8°
0.25 (0.0098) 0° 1.27 (0.0500)
0.40 (0.0157)
0.17 (0.0067)
5
0.38
0.22
COPLANARITY
0.10
0.23
0.08
0.80
0.60
0.40
8°
0°
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 51. 8-Lead Mini Small Outline Package [MSOP]
(RM-8)
Dimensions shown in millimeters
Figure 50. 8-Lead Standard Small Outline Package [SOIC]
(R-8)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model
AD8138AR
AD8138AR-REEL
AD8138AR-REEL7
AD8138ARZ 1
AD8138ARZ-RL1
AD8138ARZ-R71
AD8138ARM
AD8138ARM-REEL
AD8138ARM-REEL7
AD8138ARMZ1
AD8138ARMZ-REEL1
AD8138ARMZ-REEL71
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
8-Lead SOIC
8-Lead SOIC, 13" Tape and Reel
8-Lead SOIC, 7" Tape and Reel
8-Lead SOIC
8-Lead SOIC, 13" Tape and Reel
8-Lead SOIC, 7" Tape and Reel
8-Lead MSOP
8-Lead MSOP, 13" Tape and Reel
8-Lead MSOP, 7" Tape and Reel
8-Lead MSOP
8-Lead MSOP, 13" Tape and Reel
8-Lead MSOP, 7" Tape and Reel
Z = Pb-free part, # denotes lead-free product may be top or bottom marked.
Rev. F | Page 23 of 24
Package Option
R-8
R-8
R-8
R-8
R-8
R-8
RM-8
RM-8
RM-8
RM-8
RM-8
RM-8
Branding
HBA
HBA
HBA
HBA#
HBA#
HBA#
AD8138
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C01073-0-1/06(F)
Rev. F | Page 24 of 24