Maxim DS1856E-M50+T Dual, temperature-controlled resistors with calibrated monitors and password protection Datasheet

19-6395; Rev 0; 7/12
TION KIT
EVALUA
LE
AVAILAB
Dual, Temperature-Controlled Resistors with
Calibrated Monitors and Password Protection
Features
The DS1856M dual, temperature-controlled, nonvolatile
(NV) variable resistors with three monitors consists of
two 256-position, linear, variable resistors; three analog
monitor inputs (MON1, MON2, MON3); and a direct-todigital temperature sensor. The device provides an
ideal method for setting and temperature-compensating
bias voltages and currents in control applications using
minimal circuitry. The variable resistor settings are
stored in EEPROM memory and can be accessed over
the 2-wire serial bus.
♦ SFF-8472 Compatible
The DS1856M includes 128 bytes of EEPROM memory
at A2h slave address, Table 00/01. The DS1856M also
includes three-levels of password protection. The
DS1856-01 includes 256 bytes of A0h EEPROM memory. The DS1856B-M50+ and DS1856E-M50+ are dropin replacements for the DS1856B-050+ and
DS1866E-050+, respectively. The enhancements
include 256 bytes of EEPROM at A0h; selectable
MON2, MON3 references; and a 13-bit ADC. These are
backward compatible by default with the
DS1856B-050+/DS1856E-050+.
♦ 2-Wire Serial Interface
♦ 13-Bit ADC
♦ Two Linear, 256-Position, Nonvolatile
Temperature-Controlled Variable Resistors with
2°C Resolution
♦ Three Levels of Security
♦ Access to Monitoring and ID Information
Configurable with Separate Device Addresses
♦ Two Buffers with TTL/CMOS-Compatible Inputs
and Open-Drain Outputs
♦ Operates from a 3.3V or 5V Supply
♦ -40°C to +95°C Operating Temperature Range
Typical Operating Circuit
VCC
Applications
VCC = 3.3V
Optical Transceivers
Optical Transponders
Instrumentation and Industrial Controls
RF Power Amps
Diagnostic Monitoring
4.7kΩ
4.7kΩ
1
2-WIRE
INTERFACE
2
3
Tx-FAULT
4
SDA
LOS
Ordering Information appears at end of data sheet.
H1
SCL
L1
OUT1
IN1
5
0.1μF
VCC
H0
DS1856M
L0
8
15
14
13
12
DECOUPLING
CAPACITOR
TO LASER BIAS
CONTROL
TO LASER
MODULATION
CONTROL
OUT2
6
7
16
IN2
MON3
N.C.
MON2
GND
MON1
11 Rx POWER*
10 Tx POWER*
9 Tx BIAS*
DIAGNOSTIC
INPUTS
*SATISFIES SFF-8472 COMPATIBILITY
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
DS1856M
General Description
DS1856M
Dual, Temperature-Controlled Resistors with
Calibrated Monitors and Password Protection
ABSOLUTE MAXIMUM RATINGS
(All voltages relative to ground.)
Voltage Range on VCC ..........................................-0.5V to +6.0V
Voltage Range on Inputs ..........................-0.5V to (VCC + 0.5V)*
Voltage Range on Resistor Inputs ............-0.5V to (VCC + 0.5V)*
Current into Resistors............................................................5mA
Continuous Power Dissipation (TA = +70°C)
CSBGA (derate 16.1°C/W above +70°C) ..................887.1mW
TSSOP (derate 11.1°C/W above +70°C) ...................888.9mW
Operating Temperature Range ...........................-40°C to +95°C
Programming Temperature Range .........................0°C to +70°C
Storage Temperature Range .............................-55°C to +125°C
Lead Temperature (TSSOP only; soldering, 10s) ............+300°C
Soldering Temperature (reflow) .......................................+260°C
*Not to exceed 6.0V.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(TA = -40°C to +95°C, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
Supply Voltage
VCC
(Note 1)
Input Logic 1 (SDA, SCL)
VIH
(Note 2)
Input Logic 0 (SDA, SCL)
VIL
(Note 2)
MIN
TYP
2.85
0.7 x VCC
-0.3
Resistor Inputs (L0, L1, H0, H1)
-0.3
Resistor Current
IRES
High-Impedance Resistor
Current
IROFF
UNITS
5.50
V
VCC + 0.3
V
+0.3 x VCC
VCC + 0.3
V
-3
0.001
Input logic 1
Input Logic Levels (IN1, IN2)
MAX
mA
0.1
μA
2
Input logic 0
V
+3
0.8
V
DC ELECTRICAL CHARACTERISTICS
(VCC = 2.85V to 5.5V, TA = -40°C to +95°C, unless otherwise noted.) (Note 3)
PARAMETER
SYMBOL
TYP
MAX
UNITS
1
2
mA
-200
+200
nA
3mA sink current
0
0.4
V
Full-Scale Input (MON1, MON2,
MON3)
At factory setting
(Note 5)
2.4875
2.5
2.5125
V
Full-Scale VCC Monitor
At factory setting (Note 6)
6.5208
6.5536
6.5864
V
Supply Current
ICC
Input Leakage
I IL
Low-Level Output Voltage
(SDA, OUT1, OUT2)
VOL1
I/O Capacitance
CI/O
Digital Power-On Reset
POD
Analog Power-On Reset
POA
2
CONDITIONS
MIN
(Note 4)
POD < POA (Note 7)
10
pF
1.0
2.5
V
1.875
2.65
V
Dual, Temperature-Controlled Resistors with
Calibrated Monitors and Password Protection
DS1856M
ANALOG RESISTOR CHARACTERISTICS
(VCC = 2.85V to 5.5V, TA = -40°C to +95°C, unless otherwise noted.) (Note 3)
PARAMETER
MIN
TYP
MAX
UNITS
TA = +25°C
CONDITIONS
0.72
0.9
1.08
k
Position FFh Resistance (50k)
TA = +25°C
40
50
60
k
INL
(Note 8)
-2
+2
LSB
DNL
(Note 9)
-1
+1
LSB
Temperature Coefficient
(Note 10)
Position 00h Resistance (50k)
±50
ppm/°C
ANALOG VOLTAGE MONITORING
(VCC = 2.85V to 5.5V, TA = -40°C to +95°C, unless otherwise noted.) (Note 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
ADC Resolution
TA = +25°C
DNL
UNITS
Bits
-3
+3
LSB
-1
+1
LSB
VMON
610
VCC
1.6
mV
0.25
0.5
% FS
(full scale)
32
40
ms
0
1
LSB
Supply Resolution
Input/Supply Accuracy
(MON1, MON2, MON3, VCC)
Update Rate for MON1, MON2,
MON3, Temp, or VCC
MAX
13
INL
Input Resolution
TYP
ACC
At factory setting
tFRAME
Input/Supply Offset
(MON1, MON2, MON3, VCC)
VOS
(Note 6)
MON1, MON2, MON3 (Note 5)
Factory Setting Full Scale
μV
2.5
VCC (Note 5)
V
6.5536
Temperature LSB Weighting
1/256
°C
DIGITAL THERMOMETER
(VCC = 2.85V to 5.5V, TA = -40°C to +95°C, unless otherwise noted.) (Note 3)
PARAMETER
Thermometer Error
SYMBOL
T ERR
CONDITIONS
MIN
TYP
-40°C to +95°C
MAX
UNITS
±3.0
°C
NONVOLATILE MEMORY CHARACTERISTICS
(VCC = 2.85V to 5.5V, unless otherwise noted.) (Note 3)
PARAMETER
EEPROM Writes
SYMBOL
CONDITIONS
+70°C (Note 7)
MIN
50,000
TYP
MAX
UNITS
Writes
3
DS1856M
Dual, Temperature-Controlled Resistors with
Calibrated Monitors and Password Protection
AC ELECTRICAL CHARACTERISTICS
(VCC = 2.85V to 5.5V, TA = -40°C to +95°C, unless otherwise noted. See Figure 5.) (Note 3)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
400
kHz
SCL Clock Frequency
f SCL
0
Bus Free Time Between STOP
and START Condition
tBUF
1.3
μs
0.6
μs
Hold Time (Repeated)
START Condition
tHD:STA
(Note 11)
LOW Period of SCL Clock
tLOW
1.3
μs
HIGH Period of SCL Clock
tHIGH
0.6
μs
Data Hold Time
tHD:DAT
(Notes 12, 13)
0
0.9
μs
Data Setup Time
t SU:DAT
100
ns
START Setup Time
t SU:STA
0.6
μs
Rise Time of Both SDA and SCL
Signals
tR
(Note 14)
20 + 0.1CB
300
ns
Fall Time of Both SDA and SCL
Signals
tF
(Note 14)
20 + 0.1CB
300
ns
Setup Time for STOP Condition
t SU:STO
Capacitive Load for Each Bus
CB
EEPROM Write Time
tW
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
Note 14:
4
0.6
μs
(Note 14)
10
400
pF
20
ms
All voltages are referenced to ground.
I/O pins of fast-mode devices must not obstruct the SDA and SCL lines if VCC is switched off.
Limits are 100% production tested at TA = +25°C and/or TA = +95°C. Limits over the operating temperature range and
relevant supply voltage range are guaranteed by design and characterization. Typical values are not guaranteed.
SDA and SCL are connected to VCC and all other input signals are connected to well-defined logic levels.
Full scale is user programmable. The maximum voltage that the MON inputs read is approximately full scale, even if the
voltage on the inputs is greater than full scale.
This voltage defines the maximum range of the analog-to-digital converter voltage, not the maximum VCC voltage.
Guaranteed by design.
INL is the difference of measured value from expected value at DAC position. The expected value is a straight line from
measured minimum position to measured maximum position.
DNL is the deviation of an LSB DAC setting change vs. the expected LSB change. The expected LSB change is the slope
of the straight line from measured minimum position to measured maximum position.
See the Typical Operating Characteristics.
After this period, the first clock pulse is generated.
The maximum tHD:DAT only has to be met if the device does not stretch the low period (tLOW) of the SCL signal.
A device must internally provide a hold time of at least 300ns for the SDA signal (see the VIH_MIN of the SCL signal) to
bridge the undefined region of the falling edge of SCL.
CB—total capacitance of one bus line, timing referenced to 0.9 x VCC and 0.1 x VCC.
Dual, Temperature-Controlled Resistors with
Calibrated Monitors and Password Protection
(VCC = 5.0V, TA = +25°C, unless otherwise noted.)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
0.7
VCC = 2.85V
0.5
0.4
SDA = SCL = VCC
-40
-15
10
35
60
0.6
0.5
0.4
0.3
25
20
15
10
5
2.85
3.35
3.85
4.35
4.85
0
5.35
0.8
740
0.4
0.2
0
-0.2
-0.4
0.6
0.2
0
-0.2
-0.4
-0.6
-0.8
-0.8
700
-1.0
-1.0
0
25 50 75 100 125 150 175 200 225 250
25 50 75 100 125 150 175 200 225 250
SETTING (DEC)
SETTING (DEC)
RESISTOR 1 INL (LSB) vs. SETTING
RESISTOR 1 DNL (LSB) vs. SETTING
RESISTANCE
vs. POWER-UP VOLTAGE
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-0.8
-1.0
-1.0
25 50 75 100 125 150 175 200 225 250
SETTING (DEC)
>1MΩ
110
100
RESISTANCE (kΩ)
RESISTOR 1 DNL (LSB)
0.6
120
DS1856M toc08
1.0
DS1856M toc07
0.8
0
0
SCL FREQUENCY (kHz)
1.0
250
0.4
720
400
200
0.8
-0.6
300
150
RESISTOR 0 DNL (LSB) vs. SETTING
RESISTOR 0 DNL (LSB)
0.6
RESISTOR 0 INL (LSB)
760
200
100
1.0
DS1856M toc05
1.0
DS1856M toc04
SDA = VCC
780
100
50
SETTING (DEC)
RESISTOR 0 INL (LSB) vs. SETTING
800
0
0
VCC (V)
ACTIVE SUPPLY CURRENT
vs. SCL FREQUENCY
ACTIVE SUPPLY CURRENT (μA)
30
0.1
TEMPERATURE (°C)
RESISTOR 1 INL (LSB)
35
0.2
0
85
-40°C
+25°C
40
DS1856M toc09
0.3
+95°C
0.7
50kI VERSION
45
DS1856M toc06
0.6
0.8
RESISTANCE (kI)
0.8
SDA = SCL = VCC
0.9
RESISTANCE vs. SETTING
50
DS1856M toc02
DS1856M toc01
VCC = 5.5V
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
0.9
1.0
DS1856M toc03
SUPPLY CURRENT vs. TEMPERATURE
1.0
90
80
PROGRAMMED
RESISTANCE
(80h)
70
60
50
40
30
20
10
0
0
25 50 75 100 125 150 175 200 225 250
SETTING (DEC)
0
1
2
3
4
5
POWER-UP VOLTAGE (V)
5
DS1856M
Typical Operating Characteristics
Typical Operating Characteristics (continued)
(VCC = 5.0V, TA = +25°C, unless otherwise noted.)
POSITION FFh RESISTANCE
vs. TEMPERATURE
940
920
900
880
860
840
47.75
47.50
47.25
47.00
46.75
46.50
820
46.25
800
46.00
-40 -25 -10
5
20
35
50
65
80
95
-40 -25 -10
TEMPERATURE (°C)
5
20
35
50
65
80
250
200
+25°C TO +95°C
150
100
50
0
95
+25°C TO -40°C
0
50
100
150
0.8
0.6
MONITOR DNL (LSB)
1
0
-1
DS1856M toc14
1.0
DS1856M toc13
2
0.4
0.2
0
-0.2
-0.4
-0.6
-2
-0.8
-3
-1.0
0
0.5
1.0
1.5
INPUT VOLTAGE (V)
2.0
2.5
200
RESISTOR SETTING (DEC)
MONITOR DNL (LSB)
vs. INPUT VOLTAGE
3
MONITOR INL (LSB)
300
TEMPERATURE (°C)
MONITOR INL (LSB)
vs. INPUT VOLTAGE
6
350
DS1856M toc12
960
48.00
DS1856M toc11
980
POSITION FFh RESISTANCE (kI)
DS1856M toc10
1000
TEMPERATURE COEFFICIENT
vs. RESISITOR SETTING
TEMPERATURE COEFFICIENT (ppm)
POSITION 00h RESISTANCE
vs. TEMPERATURE
POSITION 00h RESISTANCE (I)
DS1856M
Dual, Temperature-Controlled Resistors with
Calibrated Monitors and Password Protection
0
0.5
1.0
1.5
INPUT VOLTAGE (V)
2.0
2.5
250
Dual, Temperature-Controlled Resistors with
Calibrated Monitors and Password Protection
TOP VIEW
A
B
C
D
SDA 1
IN1
SCL
VCC
H1
OUT2
SDA
H0
L1
N.C.
IN2
GND
1
L0
OUT1
MON1
2
+
OUT1 3
MON3
MON2
3
16 VCC
SCL 2
15 H1
DS1856M
14 L1
IN1 4
13 H0
OUT2 5
12 L0
IN2 6
11 MON3
N.C. 7
10 MON2
GND 8
9
MON1
4
TSSOP
Pin/Bump Descriptions
PIN
BALL
NAME
1
B2
SDA
2
A2
SCL
3
C3
OUT1
FUNCTION
2-Wire Serial Data I/O Pin. Transfers serial data to and from the device.
2-Wire Serial Clock Input. Clocks data into and out of the device.
Open-Drain Buffer Output
4
A1
IN1
5
B1
OUT2
TTL/CMOS-Compatible Input to Buffer
6
C2
IN2
7
C1
N.C.
No Connection
8
D1
GND
Ground
9
D3
MON1
External Analog Input
10
D4
MON2
External Analog Input
11
C4
MON3
Open-Drain Buffer Output
TTL/CMOS-Compatible Input to Buffer
External Analog Input
12
D2
L0
Low-End Resistor 0 Terminal. It is not required that the low-end terminals be connected to a
potential less than the high-end terminals of the corresponding resistor. Voltage applied to any of
the resistor terminals cannot exceed the power-supply voltage, VCC, or go below ground.
13
B3
H0
High-End Resistor 0 Terminal. It is not required that the high-end terminals be connected to a
potential greater than the low-end terminals of the corresponding resistor. Voltage applied to any of
the resistor terminals cannot exceed the power-supply voltage, VCC, or go below ground.
14
B4
L1
Low-End Resistor 1 Terminal
15
A4
H1
High-End Resistor 1 Terminal
16
A3
VCC
Supply Voltage
7
DS1856M
Pin/Bump Configurations
DS1856M
Dual, Temperature-Controlled Resistors with
Calibrated Monitors and Password Protection
Detailed Description
The user can read the registers that monitor the VCC,
MON1, MON2, MON3, and temperature analog signals.
After each signal conversion, a corresponding bit is set
that can be monitored to verify that a conversion has
occurred. The signals also have alarm and warning flags
that notify the user when the signals go above or below
the user-defined value. Interrupts can also be set for
each signal.
The position values of each resistor can be independently programmed. The user can assign a unique
value to each resistor for every 2°C increment over the
-40°C to +102°C range.
Two buffers are provided to convert logic-level inputs
into open-drain outputs. Typically, these buffers are
used to implement transmit (Tx) fault and loss-of-signal
(LOS) functionality. Additionally, OUT1 can be asserted
in the event that one or more of the monitored values
go beyond user-defined limits.
Monitored Signals
The comparison of all five signals with the high and low
user-defined values are done automatically. The corresponding flags are set to 1 within a specified time of
the occurrence of an out-of-limit condition.
Calculating Signal Values
The LSB = 100µV for VCC, and the LSB = 38.147µV for
the MON signals when using factory default settings.
To calculate VCC, convert the unsigned 16-bit value to
decimal and multiply by 100µV.
To calculate MON1, MON2, or MON3, convert the
unsigned 16-bit value to decimal and multiply by
38.147µV.
To calculate the temperature, treat the two’s complement value binary number as an unsigned binary number, then convert to decimal and divide by 256. If the
result is greater than or equal to 128, subtract 256 from
the result.
Temperature: high byte: -128°C to +127°C signed; low
byte: 1/256°C.
Each signal (VCC, MON1, MON2, MON3, and temperature) is available as a 16-bit value with 13-bit accuracy
(left-justified) over the serial bus. See Table 1 for signal
full scales and Table 2 for signal format. The three
LSBs are internally masked with 0s.
Monitor/VCC Bit Weights
The signals are updated every frame rate (tFRAME) in a
round-robin fashion.
VCC Conversion Examples
MSB
215
214
213
212
211
210
29
28
LSB
27
26
25
24
23
22
21
20
MSB (BIN)
LSB (BIN)
VOLTAGE (V)
10000000
10000000
3.29
11000000
11111000
4.94
Table 1. Scales for Monitor Channels at
Factory Setting
SIGNAL
+FS SIGNAL
+FS
(hex)
-FS
SIGNAL
-FS
(hex)
Temperature
+127.984°C
7FFC
-128°C
8000
VCC
6.5528V
FFF8
0V
0000
MON1
2.4997V
FFF8
0V
0000
MON2
2.4997V
FFF8
0V
0000
MON3
2.4997V
FFF8
0V
0000
Table 2. Signal Comparison
MSB (BIN)
LSB (BIN)
VOLTAGE (V)
11000000
00000000
1.875
10000000
10000000
1.255
Temperature Bit Weights
S
26
25
24
23
22
21
20
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
Temperature Conversion Examples
SIGNAL
FORMAT
VCC
Unsigned
MSB (BIN)
LSB (BIN)
Unsigned
01000000
00000000
+64
MON2
Unsigned
01000000
00001111
+64.059
MON3
Unsigned
01011111
00000000
+95
Two’s complement
11110110
00000000
-10
11011000
00000000
-40
MON1
Temperature
8
Monitor Conversion Example
TEMPERATURE (°C)
Dual, Temperature-Controlled Resistors with
Calibrated Monitors and Password Protection
TABLE
SELECT
EEPROM
128 x 8 BIT
STANDARDS
ADDRESS
ADDRESS
R/W
ADDRESS
TABLE 04
RESISTOR 0
LOOKUP
TABLE
R/W
WRPROT_AUX
SDA
TABLE
SELECT
EEPROM
72 x 8 BIT
80h-C7h
R/W
DS1856M
TABLE
SELECT
A0h
EEPROM
256 x 8
EEPROM
72 x 8 BIT
80h-C7h
TABLE 05
RESISTOR 1
LOOKUP
TABLE
ADDRESS
2-WIRE
INTERFACE
DATA BUS
SCL
TEMP INDEX
TEMP INDEX
R/W
TxF
Tx FAULT
OUT1
R/W
EEPROM
96 x 8 BIT
00h-5Fh
LIMITS
TxF
SRAM
32 x 8 BIT
60h-7Fh
REGISTER
MINT
H0
MONITORS LIMIT
HIGH
ADDRESS
MONITORS LIMIT
LOW
RESISTOR 0
256 POSITIONS
L0
TEMP INDEX
INV1
RxL
LOS
OUT2
MINT (BIT)
RESISTOR 1
256 POSITIONS
L1
TABLE SELECT
MEASUREMENT
INV2
IN2
VCC
H1
REGISTER
IN1
WARNING FLAGS
R/W
ALARM FLAGS
INV1 (BIT)
RIGHT
SHIFTING
INTERNAL
TEMP
TABLE SELECT
ADDRESS
DEVICE ADDRESS
VENDOR
VCC
INTERNAL
CALIBRATION
MON2
MUX
13-BIT
ADC
MONITORS LIMIT HIGH
MON2 REF
MUX
CTRL
MINT
MEASUREMENT
INTERRUPT
COMP CTRL
MON3
MASKING (TEMP, VCC, MON1, MON2, MON3)
MONITORS LIMIT LOW
A/D
CTRL
VCC
INV2 (BIT)
TABLE 03
EEPROM
80h-B7h
MON1
WARNING FLAGS
COMPARATOR
ALARM FLAGS
MON3 REF
VCC
VCC
DS1856M
GND
Figure 1. Block Diagram
9
DS1856M
Dual, Temperature-Controlled Resistors with
Calibrated Monitors and Password Protection
Variable Resistors
The value of each variable resistor is determined by
a temperature-addressed lookup table, which can
assign a unique value (00h to FFh) to each resistor for
every 2°C increment over the -40°C to +102°C range
(see Table 3). See the Temperature Conversion section
for more information.
The variable resistors can also be used in manual
mode. If the TEN bit equals 0, the resistors are in manual mode and the temperature indexing is disabled. The
user sets the resistors in manual mode by writing to
addresses 82h and 83h in Table 03 to control resistors
0 and 1, respectively.
Memory Description
The DS1856M 2-wire interface uses 8-bit addressing,
which allows up to 256 bytes to be addressed traditionally on a given 2-wire slave address. However,
since the A2h Memory contains more than 256 bytes, a
table scheme is used. The lower 128 bytes of the A2h
Memory, memory locations 00h to 7Fh, function as
expected and are independent of the currently selected table. Byte 7Fh is the Table Select byte. This byte
determines which memory table is accessed by the 2wire interface when address locations 80h–FFh are
accessed. Memory locations 80h–FFh are accessible
only through the A2h Memory address. Valid values for
the Table Select byte are shown in Table 4.
Before attempting to read and write any of the bits or
bytes mentioned in this section, it is important to look at
the memory map provided in a subsequent section to
verify what level of password is required.
Password Protection
The DS1856M uses two 4-byte passwords to achieve
three levels of access to various memory locations. The
three levels of access are:
User Access: This is the default state after power-up.
It allows read access to standard monitoring and status functions.
Level 1 Access: This allows access to customer
data table (Tables 00 and 01) in addition to everything granted by User access. This level is granted
by entering Password 1 (PW1).
Level 2 Access: This allows access to all memory,
settings, and features, in addition to everything
granted by Level 1 and User access. This level is
granted by entering Password 2 (PW2).
10
Table 3. Lookup Table Address for
Corresponding Temperature Values
TEMPERATURE
(°C)
CORRESPONDING LOOKUP TABLE
ADDRESS
<-40
80h
-40
80h
-38
81h
-36
82h
-34
83h
—
—
+98
C5h
+100
C6h
+102
C7h
>+102
C7h
Table 4. Table Select Byte
TABLE SELECT
BYTE
00
01
TABLE NAME
EEPROM Memory
02
Does Not Exist
03
Configuration
04
Resistor 0 Lookup Table
05
Resistor 1 Lookup Table
To obtain a particular level of access, the corresponding password must be entered in the Password Entry
(PWE) bytes located in the A2h Memory at 7Bh to 7Eh.
The value entered is compared to both the PW1 and
PW2 settings located in Table 03, bytes B0h to B3h and
Table 03, bytes B4h to B7h, respectively, to determine
if access should be granted. Access is granted until
the password is changed or until power is cycled.
Writing PWE can be done with any level of access,
although PWE can never be read.
Writing PW1 and PW2 requires PW2 access. However,
PW1 and PW2 can never be read, even with PW2
access.
On power-up, PWE is set to all 1s (FFFFh). As long as
neither of the passwords are ever changed to FFFFh,
then User access is the power-up default. Likewise,
password protection can be intentionally disabled by
setting the PW2 password to FFFFh.
Dual, Temperature-Controlled Resistors with
Calibrated Monitors and Password Protection
DS1856M
DEC HEX 2-WIRE ADDRRESS A2h (DEFAULT)
0
0
00h
0
NOTE 1: A2h MEMORY IS ADDRESSED USING THE 2-WIRE SLAVE ADDRESS, A2h.
NOTE 2: TABLES 00h AND 01h ACCESS THE SAME PHYSICAL MEMORY.
NOTE 3: TABLE 02h DOES NOT EXIST.
NOTE 4: A0h MEMORY IS ADDRESSED USING THE 2-WIRE SLAVE ADDRESS, A0h.
LOWER MEMORY
A2h MEMORY
A0h
A0h MEMORY
PASSWORD ENTRY
(PWE) (4 BYTES)
127
7F
128
80 80h
TABLE SELECT BYTE 7Fh
80h
TABLE 00h/01h
183
B7
199
200
C7
C8
EEPROM
MEMORY
(128 BYTES)
80h
80h
TABLE 03h
TABLE 04h
TABLE 05h
CONFIGURATION
TABLE
RESISTOR 0
LOOKUP TABLE
(72 BYTES)
RESISTOR 1
LOOKUP TABLE
(72 BYTES)
B7h
C7h
F0h
F0h
RESERVED AND
CALIBRATION
CONSTANTS
255
255
FFh
FF
C7h
RESERVED AND
CALIBRATION
CONSTANTS
FFh
FFh
Figure 2. Memory Organization
Memory Map
Table 5. Password Permission
PERMISSION
<0>
READ
WRITE
At least one byte in the row is different than
the rest of the row, so look at each byte
separately for permissions.
<1>
all
PW2
<2>
all
NA
<3>
all
all (The part also writes
to this byte.)
<4>
PW2
PW2 + mode_bit
<5>
all
all
<6>
NA
all
<7>
PW1
PW1
<8>
PW2
PW2
PW2
<9>
NA
<10>
PW2
NA
<11>
all
PW1
Table 5 is the legend used in the memory map to indicate the access level required for read and write
access.
Each table in the memory map begins with a higher
level view of a particular portion of the memory showing
information such as row (8 bytes) and byte names. The
tables are then followed, where applicable, by an
Expanded Bytes table, which shows bit names and values. Furthermore, both tables use the permission legend to indicate the access required on a row, byte, and
bit level.
The memory map is followed by a Register Description
section, which describes bytes and bits in further detail.
11
DS1856M
Dual, Temperature-Controlled Resistors with
Calibrated Monitors and Password Protection
Memory Map
A0h MEMORY (AT 2-WIRE ADDRESS A0h)
Row
(hex)
Row
Name
<1>
00–FF
Word 0
Word 1
Word 2
Word 3
Byte 0/8
Byte 1/9
Byte 2/A
Byte 3/B
Byte 4/C
Byte 5/D
Byte 6/E
Byte 7/F
EE
EE
EE
EE
EE
EE
EE
EE
EE
A2h LOWER MEMORY
Row
(hex)
Row
Name
Word 0
Byte 0/8
Word 1
Byte 1/9
Byte 2/A
Word 2
Byte 3/B
Byte 4/C
Word 3
Byte 5/D
Byte 6/E
Byte 7/F
00
<1>
Threshold0
Temp Alarm Hi
Temp Alarm Lo
Temp Warn Hi
Temp Warn Lo
08
<1>
Threshold1
VCC Alarm Hi
VCC Alarm Lo
VCC Warn Hi
VCC Warn Lo
10
<1>
Threshold2
Mon1 Alarm Hi
Mon1 Alarm Lo
Mon1 Warn Hi
Mon1 Warn Lo
18
<1>
Threshold3
Mon2 Alarm Hi
Mon2 Alarm Lo
Mon2 Warn Hi
Mon2 Warn Lo
20
<1>
Threshold4
Mon3 Alarm Hi
Mon3 Alarm Lo
Mon3 Warn Hi
Mon3 Warn Lo
28
<1>
user ROM
EE
EE
EE
EE
EE
EE
EE
EE
30
<1>
user ROM
EE
EE
EE
EE
EE
EE
EE
EE
38
<1>
user ROM
EE
EE
EE
EE
EE
EE
EE
EE
40
<1>
user ROM
EE
EE
EE
EE
EE
EE
EE
EE
48
<1>
user ROM
EE
EE
EE
EE
EE
EE
EE
EE
50
<1>
user ROM
EE
EE
EE
EE
EE
EE
EE
EE
58
<1>
user ROM
EE
EE
EE
EE
EE
EE
EE
EE
60
<2>
Values0
68
<0>
Values1
70
<2>
Temp Value
<2>
Alrm Wrn
78
Alarm1
Alarm0
<6>
<6>
<2>
Mon3 Value
<0>
Table
Select
Vcc Value
Reserved
<6>
<2>
Reserved
Reserved
Reserve
d
Mon1 Value
Reserved
Reserve
d
<6>
Mon2 Value
<0>
Reserved
Warn1
Warn0
Reserved
<6>
PWE msb
Status
<3>
Update
Reserved
<5>
PWE lsb
Tbl Sel
EXPANDED BYTES
Byte
(hex)
Byte
Name
Bit7
bit15
User EE
Bit5
bit13 bit12
bit11 bit10
EE
EE
Bit4
bit9
EE
Bit3
bit8
bit7
EE
Bit2
bit6
bit5
EE
Bit1
bit4
bit3
EE
Bit0
bit2
bit1
EE
bit0
EE
S
26
25
24
23
22
21
20
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
Temp Warn
S
6
2
5
2
4
2
3
2
2
2
1
2
0
2
-1
2
-2
-3
-4
-5
-6
-7
2-8
Volt Alarm
215
214
213
212
211
210
29
28
27
26
25
24
23
22
21
20
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
20
Temp Alarm
Volt Warn
12
bit14
Bit6
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
28
User ROM
EE
EE
EE
EE
EE
EE
EE
EE
30
User ROM
EE
EE
EE
EE
EE
EE
EE
EE
38
User ROM
EE
EE
EE
EE
EE
EE
EE
EE
40
User ROM
EE
EE
EE
EE
EE
EE
EE
EE
48
User ROM
EE
EE
EE
EE
EE
EE
EE
EE
50
User ROM
EE
EE
EE
EE
EE
EE
EE
EE
58
User ROM
EE
EE
EE
EE
EE
EE
EE
EE
Dual, Temperature-Controlled Resistors with
Calibrated Monitors and Password Protection
EXPANDED BYTES
Byte
(hex)
60
62
Byte
Name
Temp Value
VCC Value
Bit7
bit15
bit14
Bit6
Bit5
bit13 bit12
bit11 bit10
6
S
5
2
15
2
14
2
2
13
2
12
2
14
2
2
2
11
10
2
2
2
2
9
8
2
2
2
-3
2
7
2
6
2
2
5
2
4
2
2
2
3
2
2
2
20
1
2
2
2
2
2
20
66
Mon2 Value
215
214
213
212
211
210
29
28
27
26
25
24
23
22
21
20
Mon3 Value
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
20
2
<2>
2
2
<2>
<2>
6F
Update
Temp Rdy
VCC Rdy
Mon1 Rdy
Mon2 Rdy
Mon3 Rdy
Reserved
Reserved
Reserved
70
Alarm1
Temp Hi
Temp Lo
VCC Hi
VCC Lo
Mon1 Hi
Mon1 Lo
Mon2 Hi
Mon2 Lo
71
Alarm0
Mon3 Hi
Mon3 Lo
Reserved
Reserved
Reserved
Reserved
Reserved
Mint
74
Warn1
Temp Hi
Temp Lo
VCC Hi
VCC Lo
Mon1 Hi
Mon1 Lo
Mon2 Hi
Mon2 Lo
75
Warn0
Mon3 Hi
Mon3 Lo
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
7B
PWE msb
231
230
229
228
227
226
225
223
221
219
217
15
14
13
12
11
10
7F
Tbl Sel
2
2
2
7
2
6
2
2
2
2
224
9
8
2
5
2
4
2
2
222
7
6
2
TxF
2
Status
PWE lsb
SoftHiz
2
6E
7D
Rhiz
2
2
Reserve
2
2
2
<2>
3
2-8
1
2
2
2
2
Reserve
4
2
bit0
-7
2
<2>
5
-6
2
2
2
Reserve
6
-5
bit1
2
<2>
7
-4
Bit0
bit2
2
2
8
-2
bit3
2
2
9
-1
Bit1
bit4
2
<11>
10
0
bit5
2
2
11
1
Bit2
bit6
2
<2>
12
2
bit7
Mon1 Value
2
13
3
Bit3
bit8
64
68
15
4
Bit4
bit9
220
5
2
4
2
3
2
2
2
2
RxL
218
3
2
2
2
Rdyb
216
1
20
2
1
0
2
2
A2h TABLE 00/01
Row
(hex)
80–FF
Row
Name
<7>
EE
Word 0
Word 1
Word 2
Word 3
Byte 0/8
Byte 1/9
Byte 2/A
Byte 3/B
Byte 4/C
Byte 5/D
Byte 6/E
Byte 7/F
EE
EE
EE
EE
EE
EE
EE
EE
13
DS1856M
Memory Map (continued)
DS1856M
Dual, Temperature-Controlled Resistors with
Calibrated Monitors and Password Protection
Memory Map (continued)
A2h TABLE 03 (CONFIGURATION)
Row
(hex)
Row
Name
80
<0>
Config0
88
<8>
Config1
Word 0
Byte 0/8
<8>
Mode
Word 1
Byte 1/9
<4>
Int Enable
Tindex
Config
Byte 2/A
<4>
Res0
Reserved
Word 2
Byte 3/B
<4>
Res1
Reserved
Byte 4/C
<8>
Reserve
chip addr
Word 3
Byte 5/D
<8>
Reserve
Byte 6/E
<8>
Reserved
Reserve
Byte 7/F
<8>
Rshift1
Reserve
Rshift0
<8>
Scale0
Reserved
98
<8>
Scale1
Mon3 Scale
Reserved
Reserved
Reserved
A0
<8>
Offset0
Reserved
Vcc Offset
MON1 Offset
MON2 Offset
A8
<8>
Offset1
MON3 Offset
Reserved
Reserved
Internal Temp Offset*
Pwd Value
PW1 msb
PW1 lsb
PW2 msb
PW2 lsb
90
B0
<9>
Vcc Scale
Mon1 Scale
Mon2 Scale
EXPANDED BYTES
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Byte
(hex)
Byte
Name
80
Mode
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
TEN
AEN
81
Tindex
27
26
25
24
23
22
21
20
82
Res0
27
26
25
24
23
22
21
20
83
Res1
7
2
6
2
5
2
4
2
3
2
2
2
1
2
20
88
Int Enable
Temp
Vcc
Mon1
Mon2
Mon3
Reserved
Reserved
Reserved
89
Config
WRPROT_
AUX
Reserved
Reserved
Reserved
MON3 REF
MON2 REF
Inv 1
Inv 2
8C
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
8E
Rshift1
bit15
bit14
bit13
bit12
2
Reserved
bit9
1
Mon1
Mon1
2
bit6
bit5
bit4
Reserved
Mon2
0
Reserved
2
bit2
bit1
1
bit0
Mon2
Mon20
Rshift0
Reserved
Reserved
Reserved
215
214
213
212
211
210
29
28
27
26
25
24
23
22
21
20
94
Mon1 Scale
215
214
213
212
211
210
29
28
27
26
25
24
23
22
21
20
Mon2 Scale
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
20
1
Mon3 Scale
A2
VCC Offset
A4
Mon1 Offset
15
2
14
2
13
12
11
2
S
28
27
26
25
S
8
7
6
5
2
2
2
2
2
2
20
24
23
22
21
20
2-1
2-2
2-3
2-4
2-5
2-6
4
3
2
1
0
-1
-2
-3
-4
-5
2-6
-5
2
2
2
2
2
2
2
2
2
2
2-6
A8
Mon3 Offset
S
28
27
26
25
24
23
22
21
20
2-1
2-2
2-3
2-4
2-5
2-6
AE
Temp
Offset*
S
28
27
26
25
24
23
22
21
20
2-1
2-2
2-3
2-4
2-5
2-6
B0
PW1 msb
231
230
229
228
227
226
225
224
223
222
221
220
219
218
217
216
15
14
13
12
11
10
6
5
3
2
1
20
17
30
2
29
2
2
27
2
26
2
25
2
24
2
23
2
22
2
21
2
20
2
19
2
18
2
B4
PW2 msb
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
216
B6
PW2 lsb
215
214
213
212
211
210
29
28
27
26
25
24
23
22
21
20
*The final result must be XORed with BB40h.
28
-4
2
2
4
-3
2
2
2
-2
2
2
7
-1
2
2
8
0
2
2
9
1
2
2
2
2
3
2
2
2
4
2
2
3
5
2
2
2
6
2
2
4
7
2
2
2
8
2
2
2
9
2
31
5
2
S
2
6
10
Mon2 Offset
PW1 lsb
7
2
2
A6
B2
8
2
2
2
2
2
2
Mon3
bit3
VCC Scale
2
Mon3
bit7
0
Mon1
1
Mon3
bit8
92
98
Reserved
bit10
8F
96
14
bit11
Dual, Temperature-Controlled Resistors with
Calibrated Monitors and Password Protection
A2h TABLE 04 (LOOKUP TABLE FOR RESISTOR 0)
Row
(hex)
Row
Name
Word 0
Word 1
Word 2
Word 3
Byte 0/8
Byte 1/9
Byte 2/A
Byte 3/B
Byte 4/C
Byte 5/D
Byte 6/E
Byte 7/F
C8
Empty
Empty
Empty
Empty
Empty
Empty
Empty
Empty
D0
Empty
Empty
Empty
Empty
Empty
Empty
Empty
Empty
D8
Empty
Empty
Empty
Empty
Empty
Empty
Empty
Empty
E0
Empty
Empty
Empty
Empty
Empty
Empty
Empty
Empty
E8
Empty
Empty
Empty
Empty
Empty
Empty
Empty
Empty
F0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
80
<8>
LUT
88
<8>
LUT
90
<8>
LUT
98
<8>
LUT
A0
<8>
LUT
A8
<8>
LUT
B0
<8>
LUT
B8
<8>
LUT
C0
<8>
LUT
F8
<10>
Res0 data
Resistor 0 Calibration Constants (see data sheet Table 6)
EXPANDED BYTES
Byte
(hex)
Byte
Name
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
80–
C7
Res0
27
26
25
24
23
22
21
20
F8–FF
Res0 data
Resistor 0 Calibration Constants (see data sheet Table 6 for weighting)
15
DS1856M
Memory Map (continued)
DS1856M
Dual, Temperature-Controlled Resistors with
Calibrated Monitors and Password Protection
Memory Map (continued)
A2h TABLE 05 (LOOKUP TABLE FOR RESISTOR 1)
Row
(hex)
Row
Name
Word 0
Word 1
Word 2
Word 3
Byte 0/8
Byte 1/9
Byte 2/A
Byte 3/B
Byte 4/C
Byte 5/D
Byte 6/E
Byte 7/F
C8
Empty
Empty
Empty
Empty
Empty
Empty
Empty
Empty
D0
Empty
Empty
Empty
Empty
Empty
Empty
Empty
Empty
D8
Empty
Empty
Empty
Empty
Empty
Empty
Empty
Empty
E0
Empty
Empty
Empty
Empty
Empty
Empty
Empty
Empty
E8
Empty
Empty
Empty
Empty
Empty
Empty
Empty
Empty
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
80
<8>
LUT
88
<8>
LUT
90
<8>
LUT
98
<8>
LUT
A0
<8>
LUT
A8
<8>
LUT
B0
<8>
LUT
B8
<8>
LUT
C0
<8>
LUT
F0
F8
<10>
Res1 data
Resistor 1 Calibration Constants (see data sheet Table 6)
EXPANDED BYTES
Byte
(hex)
Byte
Name
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
80–
C7
Res1
27
26
25
24
23
22
21
20
F8–FF
Res1 data
16
Resistor 1 Calibration Constants (see data sheet Table 6 for weighting)
Dual, Temperature-Controlled Resistors with
Calibrated Monitors and Password Protection
Name of Row
•
•
Name of Byte............. <Read/Write><Volatile><Power-On-Value>
Name of Byte............. <Read/Write><Nonvolitile><Factory-Default-Setting>
Threshold0
•
•
•
•
Temp High Alarm ..... <R-all/W-pw2><NV><7FFFh> Temperature measurements above this
two's complement threshold set its corresponding alarm bit.
Measurements below this threshold clear the alarm bit.
Temp Low Alarm....... <R-all/W-pw2><NV><8000h> Temperature measurements below this
two's complement threshold set its corresponding alarm bit.
Measurements above this threshold clear the alarm bit.
Temp High Warning . <R-all/W-pw2><NV><7FFFh> Temperature measurements above this
two's complement threshold set its corresponding warning bit.
Measurements below this threshold clear the warning bit.
Temp Low Warning .. <R-all/W-pw2><NV><8000h> Temperature measurements below this
two's complement threshold set its corresponding warning bit.
Measurements above this threshold clear the warning bit.
Threshold1
•
•
•
•
VCC High Alarm........ <R-all/W-pw2><NV><FFFFh> Voltage measurements of the VCC
input above this unsigned threshold set its corresponding alarm bit.
Measurements below this threshold clear the alarm bit.
VCC Low Alarm.......... <R-all/W-pw2><<NV><0000h> Voltage measurements of the VCC
input below this unsigned threshold set its corresponding alarm bit.
Measurements above this threshold clear the alarm bit.
VCC High Warning.... <R-all/W-pw2><NV><FFFFh> Voltage measurements of the VCC
input above this unsigned threshold set its corresponding warning
bit. Measurements below this threshold clear the warning bit.
VCC Low Warning..... <R-all/W-pw2><<NV><0000h> Voltage measurements of the VCC
input below this unsigned threshold set its corresponding warning
bit. Measurements above this threshold clear the warning bit.
Threshold2
•
•
•
•
Mon1 High Alarm ..... <R-all/W-pw2><NV><FFFFh> Voltage measurements of the Mon1
input above this unsigned threshold set its corresponding alarm bit.
Measurements below this threshold clear the alarm bit.
Mon1 Low Alarm ...... <R-all/W-pw2><NV><0000h> Voltage measurements of the Mon1
input below this unsigned threshold set its corresponding alarm bit.
Measurements above this threshold clear the alarm bit.
Mon1 High Warning. <R-all/W-pw2><NV><FFFFh> Voltage measurements of the Mon1
input above this unsigned threshold set its corresponding warning
bit. Measurements below this threshold clear the warning bit.
Mon1 Low Warning .. <R-all/W-pw2><NV><0000h> Voltage measurements of the Mon1
input below this unsigned threshold set its corresponding warning
bit. Measurements above this threshold clear the warning bit.
17
DS1856M
Register Descriptions
DS1856M
Dual, Temperature-Controlled Resistors with
Calibrated Monitors and Password Protection
Register Descriptions (continued)
Threshold3
•
•
•
•
Mon2 High Alarm ..... <R-all/W-pw2><NV><FFFFh> Voltage measurements of the Mon2
input above this unsigned threshold set its corresponding alarm bit.
Measurements below this threshold clear the alarm bit.
Mon2 Low Alarm ...... <R-all/W-pw2><NV><0000h> Voltage measurements of the Mon2
input below this unsigned threshold set its corresponding alarm bit.
Measurements above this threshold clear the alarm bit.
Mon2 High Warning. <R-all/W-pw2><NV><FFFFh> Voltage measurements of the Mon2
input above this unsigned threshold set its corresponding warning
bit. Measurements below this threshold clear the warning bit.
Mon2 Low Warning .. <R-all/W-pw2><NV><0000h> Voltage measurements of the Mon2
input below this unsigned threshold set its corresponding warning
bit. Measurements above this threshold clear the warning bit.
Threshold4
•
•
•
•
Mon3 High Alarm ..... <R-all/W-pw2><NV><FFFFh> Voltage measurements of the Mon3
input above this unsigned threshold set its corresponding alarm bit.
Measurements below this threshold clear the alarm bit.
Mon3 Low Alarm ...... <R-all/W-pw2><NV><0000h> Voltage measurements of the Mon3
input below this unsigned threshold set its corresponding alarm bit.
Measurements above this threshold clear the alarm bit.
Mon3 High Warning. <R-all/W-pw2><NV><FFFFh> Voltage measurements of the Mon3
input above this unsigned threshold set its corresponding warning
bit. Measurements below this threshold clear the warning bit.
Mon3 Low Warning .. <R-all/W-pw2><NV><0000h> Voltage measurements of the Mon3
input below this unsigned threshold set its corresponding warning
bit. Measurements above this threshold clear the warning bit.
User ROM
•
User ROM ................. <R-all/W-pw2><NV><00h> Nonvolatile EEPROM memory.
A2D Value0
•
•
•
•
18
Temp Meas ................ <R-all/W-NA><Volatile><0000h> The signed two's complement
Direct-to-Temperature measurement.
VCC Meas................... <R-all/W-NA><Volatile><0000h> Unsigned voltage measurement.
Mon1 Meas................ <R-all/W-NA><Volatile><0000h> Unsigned voltage measurement.
Mon2 Meas................ <R-all/W-NA><Volatile><0000h> Unsigned voltage measurement.
Dual, Temperature-Controlled Resistors with
Calibrated Monitors and Password Protection
A2D Value1
•
•
•
Mon3 Meas..........
Reserved ..............
Status ...................
a) Rhiz..............
b) Soft Hiz........
c) Reserved ......
d) TxF .............
e) RxL .............
f) Rdyb.............
•
Update .................
a)
b)
c)
d)
Temp Rdy ....
VCC Rdy.......
Mon1 Rdy....
Mon2 Rdy....
e) Mon3 Rdy....
Status
•
•
•
•
Alarm0 .................
a) Temp Hi.......
b) Temp Lo ......
c) VCC Hi ........
d) VCC Lo ........
e) MON1 Hi.....
f) MON1 Lo ....
g) MON2 Hi.....
h) MON2 Lo ....
Alarm1 .................
a) MON3 HI.....
b) MON3 Lo ....
c) Mint .............
Reserved ..............
Warning0 .............
a) Temp Hi.......
b) Temp Lo ......
c) VCC Hi .......
<R-all/W-NA><Volatile><0000h> Unsigned voltage measurement.
<R-all/W-NA><Volatile><0000h>
<R-all/W-see bits><Volatile><conditional>
<R-all/W-NA><Volatile><1b> High when resistor outputs are high impedance.
<R-all/W-all><Volatile><0b> Setting this bit will make resistor outputs high
impedance.
<R-all/W-NA><Volatile><0b>
<R-all/W-NA><Volatile><conditional> Reflects the logic level to be output on pin Out1.
<R-all/W-NA><Volatile><conditional> Reflects the logic level to be output on pin Out2.
<R-all/W-NA><Volatile>< VCC dependent > Ready Bar. When the supply is
above the Power-On-Analog (POA) trip point, this bit is active LOW.
Thus, this bit reads a logic One if the supply is below POA or too low
to communicate over the 2-wire bus.
<R-all/W-all><00h> Status of completed conversions. At Power-On,
these bits are cleared and will be set as each conversion is completed.
These bits can be cleared so that a completion of a new conversion
may be verified.
Temperature conversion is ready.
VCC conversion is ready.
Mon1 conversion is ready.
Mon2 conversion is ready.
Mon3 conversion is ready.
<R-all/W-NA><Volatile><10h> High Alarm Status bits.
High Alarm Status for Temperature measurement.
Low Alarm Status for Temperature measurement.
High Alarm Status for VCC measurement.
Low Alarm Status for VCC measurement. This bit is set when theVCC
supply is below the POA trip point value. It clears itself when a VCC
measurement is completed and the value is above the low threshold.
High Alarm Status for MON1 measurement.
Low Alarm Status for MON1 measurement.
High Alarm Status for MON2 measurement.
Low Alarm Status for MON2 measurement.
<R-all/W-NA><Volatile><00h> Low Alarm Status bits.
High Alarm Status for MON3 measurement.
Low Alarm Status for MON3 measurement.
Maskable Interrupt. If an alarm is present and the alarm is enabled then
this bit is high. Otherwise this bit is a zero.
<R-all/W-NA><Volatile><00h>.
<R-all/W-NA><Volatile><00h> High Warning Status bits.
High Warning Status for Temperature measurement.
Low Warning Status for Temperature measurement.
High Warning Status for VCC measurement.
19
DS1856M
Register Descriptions (continued)
Dual, Temperature-Controlled Resistors with
Calibrated Monitors and Password Protection
DS1856M
Register Descriptions (continued)
d) VCC Lo .............. Low Warning Status for VCC measurement. This bit is set when the VCC
supply is below the POA trip point value. It clears itself when a VCC
measurement is completed and the value is above the low threshold.
e) MON1 Hi........... High Warning Status for MON1 measurement.
f) MON1 Lo .......... Low Warning Status for MON1 measurement.
g) MON2 Hi........... High Warning Status for MON2 measurement.
h) MON2 Lo .......... Low Warning Status for MON2 measurement.
•
Warning1 ................... <R-all/W-NA><Volatile><00h> Low warning Status bits.
a) MON3 HI........... High Warning Status for MON3 measurement.
b) MON3 Lo........... Low Warning Status for MON3 measurement.
Table Select
•
•
•
Config0
•
•
20
Reserved .................... <R-NA><W-all><00h>
PWE........................... <R-NA><W-all><FFFFFFFFh> Password Entry. There are two
passwords for the DS1856M. The lower level password (PW1) has
all the access of a normal user plus those made available with PW1.
The higher level password (PW2) has all of the access of PW1
plus those made available with PW2. The value of the password reside
in EE inside of PW2 memory.
TBL Sel...................... <R-all/W-all><00h> Table Select. The upper memory tables of the
DS1856M are accessible by writing the correct table value in this register.
If the device is configured to have a Table 01h then writing a 00h ora
01h in this byte will access that table.
Mode.......................... <R-pw2/W-pw2><Volatile><03h>
a) TEN.................... At Power-On this bit is HIGH, which enables autocontrol of the LUT.
If this bit is written to a ZERO then the resistor values are writeable by
the user and the LUT recalls are disabled. This allows the user to
interactively test their modules by manually writing resistor values. The
resistors will update with the new value at the end of the write cycle.
Thus both registers (Res0 and Res1) should be written in the same
write cycle. The 2-wire Stop condition is the end of the write cycle.
b) AEN ................... At Power-On this bit is HIGH, which enables autocontrol of the LUT.
If this bit is cleared to a ZERO then the temperature calculated index
value ( T index ) is writable by the user and the updates of calculated
indexes are disabled. This allows the user to interactively test their
modules by controlling the indexing for the lookup tables. The recalled
values from the LUTs will appear in the resistor registers after the next
completion of a temperature conversion (just like it would happen in
auto mode). Both pots will update at the same time (just like it would
happen in auto mode).
.
T Index....................... <R-pw2><W-pw2+AENb><00h> Holds the calculated index based on
the Temperature Measurement. This index is used for the address
during Lookup of Tables 4 and 5.
Dual, Temperature-Controlled Resistors with
Calibrated Monitors and Password Protection
•
•
•
Config
.
Res0 ........................... <R-pw2><W-pw2+TENb><FFh> The base value used for Resistor 0
and recalled from Table 4 at the memory address found in T Index.
This register is updated at the end of the Temperature conversion.
Res1 ........................... <R-pw2><W-pw2+TENb><FFh> The base value used for Resistor 1
and recalled from Table 5 at the memory address found in T Index.
This register is updated at the end of the Temperature conversion.
Reserved .................... <R-pw2><W-pw2><00h> SRAM.
1
•
•
•
•
Int Enable.................. <R-pw2/W-pw2><NV><F8h> Configures the maskable interrupt for
the Out1 pin.
a) Temp Enable...... Temperature measurements, outside of the threshold limits, are enabled
to create an active interrupt on the Out1 pin.
b) VCC Enable......... VCC measurements, outside of the threshold limits, are enabled to create
an active interrupt on the Out1 pin.
c) MON1 Enable.... MON1 measurements, outside of the threshold limits, are enabled to
create an active interrupt on the Out1 pin.
d) MON2 Enable.... MON2 measurements, outside of the threshold limits, are enabled to
create an active interrupt on the Out1 pin.
e) MON3 Enable.... MON3 measurements, outside of the threshold limits, are enabled to
create an active interrupt on the Out1 pin.
f) Reserved ............ EE.
Config........................ <R-pw2/W-pw2><NV><00h> Configure the memory location and the
polarity of the digital outputs.
a) WRPROT_AUX When this bit is 1, the A0h Memory is write protected.
b) Reserved ............
c) Reserved ............
d) MON3 REF........ When 0, MON3 is referenced to GND. When 1, MON3 is referenced to VCC.
e) MON2 REF........ When 0, MON2 is referenced to GND. When 1, MON2 is referenced to VCC.
f) Inv1 .................... Enable the inversion of the relationship between IN1 and OUT1.
g) Inv2 .................... Enable the inversion of the relationship between IN2 and OUT2.
Right Shift1 ................ Allows for right-shifting the final answer of some voltage
measurements. This allows for scaling the measurements to the smallest
full-scale voltage and then right-shifting the final result so the reading is
weighted to the correct lsb.
Right Shift0 ................ Allows for right-shifting the final answer of some voltage
measurements. This allows for scaling the measurements to the smallest
full-scale voltage and then right-shifting the final result so the reading is
weighted to the correct lsb.
21
DS1856M
Register Descriptions (continued)
DS1856M
Dual, Temperature-Controlled Resistors with
Calibrated Monitors and Password Protection
Register Descriptions (continued)
Scale0
•
•
•
Scale1
VCC Scale................... <R-pw2/W-pw2><NV><Set so that FS value is 6.5535V> Controls the Scaling
or Gain of the VCC measurements.
MON1 Scale .............. <R-pw2/W-pw2><NV><Set so that FS value is 2.500V> Controls the Scaling
or Gain of the MON1 measurements.
MON2 Scale .............. <R-pw2/W-pw2><Set so that FS value is 2.500V> Controls the Scaling or Gain
of the MON2 measurements.
•
MON3 Scale .............. <R-pw2/W-pw2><NV><Set so that FS value is 2.500V> Controls the Scaling or
Gain of the MON3 measurements.
•
VCC Offset.................. <R-pw2/W-pw2><NV><0000h> Allows for offset control of VCC
measurement if desired.
MON1 Offset ............. <R-pw2/W-pw2><NV><0000h> Allows for offset control of MON1
measurement if desired.
MON2 Offset ............. <R-pw2/W-pw2><NV><0000h> Allows for offset control of MON2
measurement if desired.
Offset0
•
•
Offset1
•
•
MON3 Offset ............. <R-pw2/W-pw2><NV><0000h> Allows for offset control of MON3
measurement if desired.
Temp Offset ............... <R-pw2/W-pw2><NV><0000h> Allows for offset control of Temp
measurement if desired.
PWD Value
•
•
LUT
22
•
•
Password 1................ <R-NA/W-pw2><NV><FFFFFFFFh> The PWE value is compared
against the value written to this location to enable PW1 access. At
power-on, the PWE value is set to all ones. Thus writing these bytes to
all ones grants PW1 access on power-up without writing the password entry.
Password 2................ <R-NA/W-pw2><NV><FFFFFFFFh> The PWE value is compared
against the value written to this location to enable PW2 access. At
power-on, the PWE value is set to all ones. Thus writing these bytes to
all ones grants PW2 access on power-up without writing the password entry.
Res0 ........................... The unsigned value for Resistor 0.
Res1 ........................... The unsigned value for Resistor 1.
Dual, Temperature-Controlled Resistors with
Calibrated Monitors and Password Protection
R = the resistance desired at the output terminal
C = temperature in degrees Celsius
u, v, w, x1, x0, y, z, and α are calculated values found in
the corresponding lookup tables. The variable x from the
equation above is separated into x1 (the MSB of x) and x0
(the LSB of x). Their addresses and LSB values are given
below. The variable y is a signed value. All other variables
are unsigned. Resistor 0 variables are found in Table 04,
and Resistor 1 variables are found in Table 05.
When shipped from the factory, all other memory locations in the LUTs are programmed to FFh.
Table 6. Calibration Constants
ADDRESS
VARIABLE
F8h
u
LSB
20
F9h
v
20E-6
FAh
w
100E-9
FBh
x1
21
FCh
x0
2-7
FDh
y
2E-6 (signed)
FEh
z
10E-9
FFh
2-2
Internal Calibration
For monitoring weak receive signals, the DS1856M provides the ability to calibrate the ADC full scale to provide optional SNR for the range of the receive signals.
Calibration of the ADC is discussed in detail in the
Application Note 3408: DS1856 Internal Calibration and
Right Shifting (Scalable Dynamic Ranging).
Temperature Conversion
The direct-to-digital temperature sensor measures
temperature through the use of an on-chip temperature
measurement technique with a -40°C to +102°C operating range. Temperature conversions are initiated
upon power-up, and the most recent conversion is
stored in memory locations 60h and 61h of the A2h
M6
M5
MEMORY LOCATION
2
R − u x ⎡⎢1 + v x (C − 25) + w x (C − 25) ⎤⎥
⎦ −α
⎣
pos(α, R, C) =
2⎤
⎡
(x) x ⎢⎣1 + y x (C − 25) + z x (C − 25) ⎥⎦
DS1856M
Programming the Lookup Table (LUT)
The following equation can be used to determine which
resistor position setting, 00h to FFh, should be written in
the LUT to achieve a given resistance at a specific temperature.
DECREASING
TEMPERATURE
M4
M3
INCREASING
TEMPERATURE
M2
M1
2
4
6
8
10
12
TEMPERATURE (°C)
Figure 3. Lookup Table Hysteresis
Memory, which are updated every tframe. Temperature
conversions do not occur during an active read or
write to memory.
The value of each resistor is determined by the temperature-addressed lookup table. The lookup table assigns a
unique value to each resistor for every 2°C increment with
a 1°C hysteresis at a temperature transition over the operating temperature range (see Figure 3).
Power-Up and Low-Voltage Operation
During power-up, the device is inactive until V CC
exceeds the digital power-on-reset voltage (POD). At this
voltage, the digital circuitry, which includes the 2-wire
interface, becomes functional. However, EEPROMbacked registers/settings cannot be internally read
(recalled into shadow SRAM) until VCC exceeds the analog power-on-reset voltage (POA), at which time the
remainder of the device becomes fully functional. Once
VCC exceeds POA, the RDYB bit in byte 6Eh of the A2h
Memory is timed to go from a 1 to a 0 and indicates when
analog-to-digital conversions begin. If VCC ever dips
below POA, the RDYB bit reads as a 1 again. Once a
device exceeds POA and the EEPROM is recalled, the
values remain active (recalled) until VCC falls below POD.
For 2-wire device addresses sourced from EEPROM, the
device address is A2h until VCC exceeds POA and the
EEPROM values are recalled. The A0h Memory is always
available within this voltage window (between POD and
the EEPROM recall).
23
DS1856M
Dual, Temperature-Controlled Resistors with
Calibrated Monitors and Password Protection
Furthermore, as the device powers up, the VCClo alarm
flag (bit 4 of 70h in A2h Memory) defaults to a 1 until the
first VCC analog-to-digital conversion occurs and sets or
clears the flag accordingly.
2-Wire Operation
Clock and Data Transitions: The SDA pin is normally pulled high with an external resistor or device.
Data on the SDA pin may only change during SCLlow time periods. Data changes during SCL-high
periods will indicate a START or STOP condition
depending on the conditions discussed below. See
the timing diagrams in Figures 4 and 5 for further
details.
START Condition: A high-to-low transition of SDA
with SCL high is a START condition that must precede any other command. See the timing diagrams
in Figures 4 and 5 for further details.
STOP Condition: A low-to-high transition of SDA
with SCL high is a STOP condition. After a read or
write sequence, the stop command places the
DS1856M into a low-power mode. See the timing diagrams in Figures 4 and 5 for further details.
Acknowledge: All address and data bytes are transmitted through a serial protocol. The DS1856M pulls
the SDA line low during the ninth clock pulse to
acknowledge that it has received each word.
Standby Mode: The DS1856M features a low-power
mode that is automatically enabled after power-on,
after a STOP command, and after the completion of
all internal operations.
Device Addressing: The DS1856M must receive an
8-bit device address, the slave address byte, following a START condition to enable a specific device for
a read or write operation. The address is clocked
into this part MSB to LSB. The address byte consists
of either A2h or the value in Table 03, 8Ch for the
A2h Memory or A0h for the A0h Memory, then the
R/W bit. This byte must match the address programmed into Table 03, 8Ch or A0h (for the A0h
Memory). If a device address match occurs, this part
will output a zero for one clock cycle as an acknowledge and the corresponding block of memory is
enabled (see the Memory Organization section). If
the R/W bit is high, a read operation is initiated. If the
R/W is low, a write operation is initiated (see the
Memory Organization section). If the address does
not match, this part returns to a low-power mode.
into the write mode of operation (see the Memory
Organization section). The master must transmit an 8bit EEPROM memory address to the device to define
the address where the data is to be written. After the
byte has been received, the DS1856M transmits a zero
for one clock cycle to acknowledge the address has
been received. The master must then transmit an 8-bit
data word to be written into this address. The DS1856M
again transmits a zero for one clock cycle to acknowledge the receipt of the data. At this point, the master
must terminate the write operation with a STOP condition. The DS1856M then enters an internally timed write
process tw to the EEPROM memory. All inputs are disabled during this byte write cycle.
Page Write
The DS1856M is capable of an 8-byte page write. A
page is any 8-byte block of memory starting with an
address evenly divisible by eight and ending with the
starting address plus seven. For example, addresses
00h through 07h constitute one page. Other pages
would be addresses 08h through 0Fh, 10h through 17h,
18h through 1Fh, etc.
A page write is initiated the same way as a byte write,
but the master does not send a STOP condition after the
first byte. Instead, after the slave acknowledges the
data byte has been received, the master can send up to
seven more bytes using the same nine-clock sequence.
The master must terminate the write cycle with a STOP
condition or the data clocked into the DS1856M will not
be latched into permanent memory.
The address counter rolls on a page during a write. The
counter does not count through the entire address
space as during a read. For example, if the starting
address is 06h and 4 bytes are written, the first byte
goes into address 06h. The second goes into address
07h. The third goes into address 00h (not 08h). The
fourth goes into address 01h. If 9 bytes or more are
written before a STOP condition is sent, the first bytes
sent are overwritten. Only the last 8 bytes of data are
written to the page.
Acknowledge Polling: Once the internally timed write
has started and the DS1856M inputs are disabled,
acknowledge polling can be initiated. The process
involves transmitting a START condition followed by the
device address. The R/W bit signifies the type of operation that is desired. The read or write sequence will only
be allowed to proceed if the internal write cycle has
completed and the DS1856M responds with a zero.
Write Operations
Read Operations
After receiving a matching address byte with the R/W
bit set low, if there is no write protect, the device goes
After receiving a matching address byte with the R/W
bit set high, the device goes into the read mode of
24
Dual, Temperature-Controlled Resistors with
Calibrated Monitors and Password Protection
master receives the first data byte, the master
responds with an acknowledge. As long as the
DS1856M receives this acknowledge after a byte is
read, the master can clock out additional data words
from the DS1856M. After reaching address FFh, it
resets to address 00h.
The sequential read operation is terminated when the
master initiates a STOP condition. The master does not
respond with a zero.
The following section provides a detailed description of
the 2-wire theory of operation.
Current Address Read
The DS1856M has an internal address register that
maintains the address used during the last read or
write operation, incremented by one. This data is maintained as long as V CC is valid. If the most recent
address was the last byte in memory, then the register
resets to the first address.
Once the device address is clocked in and acknowledged by the DS1856M with the R/W bit set to high, the
current address data word is clocked out. The master
does not respond with a zero, but does generate a
STOP condition afterwards.
2-Wire Serial-Port Operation
The 2-wire serial-port interface supports a bidirectional
data transmission protocol with device addressing. A
device that sends data on the bus is defined as a transmitter, and a device that receives data as a receiver.
The device that controls the message is called a master. The devices that are controlled by the master are
slaves. The bus must be controlled by a master device
that generates the serial clock (SCL), controls the bus
access, and generates the START and STOP conditions. The DS1856M operates as a slave on the 2-wire
bus. Connections to the bus are made through the
open-drain I/O lines SDA and SCL. The following I/O
terminals control the 2-wire serial port: SDA, SCL.
Timing diagrams for the 2-wire serial port can be found
in Figures 4 and 5. Timing information for the 2-wire
serial port is provided in the AC Electrical
Characteristics table for 2-wire serial communications.
Single Read
A random read requires a dummy byte write sequence
to load in the data byte address. Once the device and
data address bytes are clocked in by the master and
acknowledged by the DS1856M, the master must generate another START condition. The master now initiates a current address read by sending the device
address with the R/W bit set high. The DS1856M
acknowledges the device address and serially clocks
out the data byte.
Sequential Address Read
Sequential reads are initiated by either a current
address read or a random address read. After the
SDA
MSB
SLAVE ADDRESS
R/W
DIRECTION
BIT
ACKNOWLEDGEMENT
SIGNAL FROM RECEIVER
ACKNOWLEDGEMENT
SIGNAL FROM RECEIVER
SCL
1
2
START
CONDITION
6
7
8
9
1
2
3–7
8
ACK
9
ACK
REPEATED IF MORE BYTES
ARE TRANSFERRED
STOP
CONDITION
OR REPEATED
START
CONDITION
Figure 4. 2-Wire Data Transfer Protocol
25
DS1856M
operation. There are three read operations: current
address read, random read, and sequential address
read.
DS1856M
Dual, Temperature-Controlled Resistors with
Calibrated Monitors and Password Protection
SDA
tBUF
tHD:STA
tLOW
tR
tSP
tF
SCL
tHD:STA
STOP
tSU:STA
tHIGH
tSU:DAT
START
REPEATED
START
tSU:STO
tHD:DAT
Figure 5. 2-Wire AC Characteristics
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus is
not busy.
Within the bus specifications, a standard mode
(100kHz clock rate) and a fast mode (400kHz clock
rate) are defined. The DS1856M works in both modes.
• During data transfer, the data line must remain stable whenever the clock line is high. Changes in the
data line while the clock line is high will be interpreted as control signals.
Accordingly, the following bus conditions have been
defined:
Acknowledge: Each receiving device, when addressed,
is obliged to generate an acknowledge after the byte has
been received. The master device must generate an
extra clock pulse, which is associated with this acknowledge bit.
A device that acknowledges must pull down the SDA line
during the acknowledge clock pulse in such a way that
the SDA line is a stable low during the high period of the
acknowledge-related clock pulse. Setup and hold times
must be taken into account. A master must signal an end
of data to the slave by not generating an acknowledge bit
on the last byte that has been clocked out of the slave. In
this case, the slave must leave the data line high to
enable the master to generate the STOP condition.
1) Data transfer from a master transmitter to a
slave receiver. The first byte transmitted by the
master is the command/control byte. Next follows
a number of data bytes. The slave returns an
acknowledge bit after each received byte.
2) Data transfer from a slave transmitter to a master receiver. The master transmits the first byte
(the command/control byte) to the slave. The slave
then returns an acknowledge bit. Next follows a
number of data bytes transmitted by the slave to
the master. The master returns an acknowledge bit
after all received bytes other than the last byte. At
the end of the last received byte, a not acknowledge can be returned.
Bus not busy: Both data and clock lines remain high.
START data transfer: A change in the state of the data
line from high to low while the clock is high defines a
START condition.
STOP data transfer: A change in the state of the data
line from low to high while the clock line is high defines
the STOP condition.
Data valid: The state of the data line represents valid
data when, after a START condition, the data line is stable for the duration of the high period of the clock signal.
The data on the line can be changed during the low period of the clock signal. There is one clock pulse per bit of
data. Figures 4 and 5 detail how data transfer is accomplished on the 2-wire bus. Depending on the state of the
R/W bit, two types of data transfer are possible.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
data bytes transferred between START and STOP conditions is not limited and is determined by the master
device. The information is transferred byte-wise and
each receiver acknowledges with a ninth bit.
26
Dual, Temperature-Controlled Resistors with
Calibrated Monitors and Password Protection
Ordering Information
RES0/RES1
RESISTANCE
(k)
PART
PIN-PACKAGE
DS1856B-M50+
50/50
16 CSBGA
DS1856B-M50+T&R
50/50
16 CSBGA
DS1856E-M50+
50/50
16 TSSOP
DS1856E-M50+T&R
50/50
16 TSSOP
+Denotes a lead(Pb)-free/RoHS-compliant package.
T&R = Tape and reel.
Note: All devices are specified over the -40°C to +95°C temperature range.
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maxim-ic.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
CSBGA
X16+1
21-0355
90-0334
TSSOP
U16+1
21-0066
90-0117
27
DS1856M
The master device generates all serial clock pulses and
the START and STOP conditions. A transfer is ended with
a STOP condition or with a repeated START condition.
Since a repeated START condition is also the beginning
of the next serial transfer, the bus is not released.
The DS1856M can operate in the following two modes:
1) Slave Receiver Mode: Serial data and clock are
received through SDA and SCL, respectively. After
each byte is received, an acknowledge bit is transmitted. START and STOP conditions are recognized as the beginning and end of a serial transfer.
Address recognition is performed by hardware
after the slave (device) address and direction bit
have been received.
2) Slave Transmitter Mode: The first byte is
received and handled as in the slave receiver
mode. However, in this mode the direction bit
indicates that the transfer direction is reversed.
Serial data is transmitted on SDA by the
DS1856M, while the serial clock is input on SCL.
START and STOP conditions are recognized as
the beginning and end of a serial transfer.
DS1856M
Dual, Temperature-Controlled Resistors with
Calibrated Monitors and Password Protection
Revision History
REVISION
NUMBER
REVISION
DATE
0
7/12
DESCRIPTION
Initial release
PAGES
CHANGED
—
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in
the Electrical. Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
28 ____________________Maxim Integrated Products, 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000
© 2012 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.