Austin AS5C1008 128k x 8 sram ruggedized plastic high speed sram Datasheet

SRAM
AS5C1008
Austin Semiconductor, Inc.
128K x 8 SRAM
PIN ASSIGNMENT
RUGGEDIZED PLASTIC
HIGH SPEED SRAM
(Top View)
32-Pin Plastic SOJ (DJ)
FEATURES
•
•
•
•
•
•
•
•
Access times of 15, 20 and 25 ns
Fast output enable (t ) for cache applications
AOE
Low active power
Low standby power
Fully static operation, no clock or refresh required
TTL Compatible Inputs and Outputs
Single +5V power supply
Package in Industry-standard 32-pin SOJ
OPTIONS
NC
A6
A5
A4
A3
A2
A1
A0
A16
A15
A14
A13
I/O0
I/O1
I/02
Vss
MARKING
• Timing
15ns access
20ns access
25ns access
-15
-20
-25
• Package
Plastic SOJ*
DJ
• Operating Temperature Ranges
-Military (-55oC to +125oC)
-Industrial (-40oC to +85oC)
XT
IT
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Vcc
A7
CE2
WE\
A8
A9
A10
A11
OE\
A12
CE\1
I/O7
I/O6
I/O5
I/O4
I/O3
No. 905
PIN FUNCTIONS
GENERAL DESCRIPTION
The ASI AS5C1008 is a high speed, low power, 128K by
8-bit ruggedized plastic (COTS) CMOS Static RAM. It is fabricated using high performance, CMOS technology. This highly
reliable process coupled with innovative circuit design techniques, yields access times as fast as 15ns (Max) over the
military and industrial temperature ranges.
When Chip Enable (CE\) is HIGH, the device assumes a
standby mode at which the power dissipation can be reduced
down to 125mW (max) at CMOS input levels.
Easy memory expansion is provided by using asserted LOW
CE\ and asserted HIGH CE2, and asserted LOW write enable
(WE\) controls both writing and reading of the memory.
TheAS5C1008 is pin-compatible with other 128K x 8
SRAM's in the SOJ package.
A0 - A16
Address Inputs
WE\
Write Enable
CE\1, CE2
Chip Enable
OE\
Output Enable
I/O0 - I/O7
Data Inputs/Outputs
VCC
Power
VSS
Ground
NC
No Connection
For more products and information
please visit our web site at
www.austinsemiconductor.com
*For ceramic versions of this product, please see the
MT5C1008 datasheet.
AS5C1008
Rev. 3.6 6/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
SRAM
Austin Semiconductor, Inc.
ABSOLUTE MAXIMUM RATINGS*
Vcc Supply Relative to GND...................................-0.5V to +7.0V
Voltage on any pin Relative to GND.........-0.5V to Vcc +7.0V
Storage Temperature ............................................-65°C to +150°C
Ambient Temperature with Power Applied........-55oC to +125oC
Short Circuit Output Current.................................................260oC
Power Dissipation...................................................................1.0W
AS5C1008
*Stresses greater than those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the
operation section of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods
may affect reliability.
FUNCTIONAL BLOCK DIAGRAM
A0
Address
Decoder
Memory Matrix
Input Data
Control
Column I/O
A16
I/O0
Data
I/O7
CE\1
CE2
WE\
OE\
AS5C1008
Rev. 3.6 6/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
2
SRAM
AS5C1008
Austin Semiconductor, Inc.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(-55oC<TA<+125oC or -40oC to +85oC; Vcc = 5V+10%)
PARAMETER
-15
-20
-25
SYMBOL MIN MAX MIN MAX MIN MAX UNITS
CONDITIONS
Dynamic Operating
Current
Vcc=MAX, IOUT = 0mA,
TTL Standby Current TTL Inputs
Vcc=MAX, VIN = VIH or VIL,
CE1 = VIL and CE2 = VIH, f = fmax
CE\1> VIH and CE2 > VIL, f = fmax
Vcc=MAX, CE\1 > Vcc -0.2V, or CE2
CMOS Standby Current < 0.2V, VIN > Vcc -0.2V and
CMOS Inputs
VIN < 0.2V, f = 0
ICC1
180
150
140
mA
ISB1
90
75
70
mA
ISB2
10
10
10
mA
Input Leakage Current
GND < VIN < Vcc
ILI
-10
10
-10
10
-10
10
µA
Output Leakage Current
GND < VOUT < Vcc
Output Disabled
ILO
-10
10
-10
10
-10
10
µA
Output High Voltage
Vcc = MIN, IOH = -4.0 mA
VOH
2.4
Output Low Voltage
Vcc = MIN, IOL = 8.0 mA
VOL
Input High Voltage
VIH
2.2
Input Low Voltage
VIL
-0.5
2.4
2.4
V
0.4
0.4
0.4
Vcc
+0.5
0.8
Vcc
2.2
+0.5
-0.5 0.8
Vcc
+0.5
0.8
2.2
-0.5
V
V
V
PIN DESCRIPTIONS
A0 - A16: Address Inputs
These 17 address inputs select one of the 131,072 8-bit words in
the RAM.
OE\: Output Enable Input
The Output Enable Input is asserted LOW. If asserted LOW
while CE\1 is asserted (LOW) and CE2 is asserted (HIGH) and
WE\ is deasserted (HIGH), data from the SRAM will be present
on the I/O pins. The I/O pins will be in the high-impedance
state when OE\ is deasserted.
CE\1: Chip Enable 1 Input
CE\1 is asserted LOW to read from or write to the device. If Chip
Enable 1 is deasserted, the device is deselected and is in standby
power mode. The I/O pins will be in the high-impedance state
when the device is deselected.
WE\: Write Enable Input
The Write Enable input is asserted LOW and controls read and
write operations. When CE\1 and WE\ are both asserted (LOW)
and CE2 is asserted (HIGH) input data present on the I/O pins
will be written into the selected memory location.
CE2: Chip Enable 2 Input
CE2 is asserted HIGH to read from or write to the device. If Chip
Enable 2 is deasserted, the device is deselected and is in standby
power mode. The I/O pins will be in the high-impedance state
when the device is deselected.
AS5C1008
Rev. 3.6 6/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
3
SRAM
AS5C1008
Austin Semiconductor, Inc.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(-55oC<TA<+125oC or -40oC to +85oC; Vcc = 5V+10%)
-15
DESCRIPTION
READ CYCLE
Read Cycle Time
SYMBOL
1
MIN
-20
MAX
15
tRC
MIN
-25
MAX
20
MIN
MAX
25
UNIT
ns
Address Access Time
tAA
15
20
25
ns
Chip Enable Access Time
tACE
15
20
25
ns
Output Hold from Address Change
tOH
3
3
3
ns
Chip Enable to Output in Low-Z
tLZCE
3
3
3
ns
Chip Disable to Output in High-Z
tHZCE
7
8
10
ns
Output Enable Access Time
tAOE
7
7
10
ns
Output Enable to Output in Low-Z
tLZOE
Output Disable to Output in High-Z
WRITE CYCLE
Write Cycle Time
tHZOE
0
0
7
0
8
ns
10
ns
tWC
15
20
25
ns
Chip Enable to End of Write
tCW
12
15
20
ns
Address Valid to End of Write
tAW
12
15
20
ns
Address Set-up Time
tAS
0
0
0
ns
Address Hold from End of Write
tAH
0
0
0
ns
Write Pulse Width (OE\ > VIH)
tWP
12
15
20
ns
Data Set-up Time
tDS
8
10
15
ns
Data Hold Time
tDH
0
0
0
ns
Write Disable to Output in Low-Z
tLZWE
5
5
5
ns
Write Enable to Output in High-Z
tHZWE
7
9
10
ns
NOTE: 1. tLZCE, tLZWE, tHZCE, tLZOE, and tHZOEare simulated values.
AS5C1008
Rev. 3.6 6/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
4
SRAM
AS5C1008
Austin Semiconductor, Inc.
CAPACITANCE (TA = +25oC, f = 1.0 MHz)
PARAMETER
Input Capacitance
Output Capacitance
CONDITION
SYMBOL
MAX
UNIT
VIN = 0V
CIN
6
pF
VOUT = 0V
COUT
8
pF
AC TEST CONDITIONS
Input Pulse Levels.......................................................GND to 3.0V
Input Rise and Fall Times..........................................................3ns
Input Timing Reference Levels................................................1.5V
Output Reference Levels..........................................................1.5V
Output Load..................................................................See Figure 1
+5V
+5V
480Ω
480Ω
Q
Q
255Ω
30 pF
255Ω
5 pF
for tLZCE, tHZCE, tLZWE, tHZWE, tLZOE, and tHZOE
Fig. 1 OUTPUT LOAD EQUIVALENT
AS5C1008
Rev. 3.6 6/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
SRAM
AS5C1008
Austin Semiconductor, Inc.
READ CYCLE TIMING 1(1)
tRC
ADDR
t AA
t OH
DOUT
DATA VALID
PREVIOUS DATA VALID
NOTE: 1. CE\ is HIGH for READ cycle.
READ CYCLE TIMING 2 (1)
CE\1
tRC
CE2
tACE
t AOE
OE\
tHZCE(2)
DOUT
High-Z
tLZOE
tLZCE
tHZCE
DATA VALID
NOTES: 1. CE\ is HIGH for READ cycle.
2. At any given temperature and voltage condition, tHZCE is less than tLZCE.
WRITE CYCLE TIMING (WE\ CONTROLLED, OE\ = LOW)
tWC
ADDR
tAW
123456789012345678901
12345678901234567890
12345678
12345678901234567890
123456789012345678901
12345678
123456789012345678901
12345678
CE\112345678901234567890
12345678901234567890
123456789012345678901
12345678
t
AH
123456789
123456789012345678901
12345678901234567890
123456789
123456789012345678901
12345678901234567890
123456789
123456789012345678901
12345678901234567890
123456789
123456789012345678901
12345678901234567890
tCW
123456789012345678901
12345678901234567890
12345678
12345678901234567890
123456789012345678901
12345678
12345678901234567890
123456789012345678901
12345678
CE212345678901234567890
123456789012345678901
12345678
WE\
tAS
123456789
123456789012345678901
12345678901234567890
123456789
123456789012345678901
12345678901234567890
123456789
123456789012345678901
12345678901234567890
123456789
123456789012345678901
12345678901234567890
12345
12345
12345
12345
t WP2
tDS
DIN
tLZWE
t DH
DATA VALID
tHZWE
High-Z
DOUT
1234
1234
UNDEFINED 1234
1234 DON’T CARE
AS5C1008
Rev. 3.6 6/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
6
SRAM
AS5C1008
Austin Semiconductor, Inc.
WRITE CYCLE TIMING (CE\1 CONTROLLED, OE\ = LOW)
tWC
ADDR
tAW
12345678901234567890
1234567890123456789
12345678
1234567890123456789
12345678901234567890
12345678
1234567890123456789
12345678901234567890
12345678
CE\1 1234567890123456789
12345678901234567890
12345678
1234567890123456789
12345678901234567890
12345678
t
AH
12345678
123456789012345678901
12345678901234567890
12345678
123456789012345678901
12345678901234567890
123456789012345678901
12345678901234567890
12345678
123456789012345678901
12345678901234567890
12345678
123456789012345678901
12345678901234567890
12345678
tCW
12345678901234567890
1234567890123456789
12345678
1234567890123456789
12345678901234567890
12345678
12345678
123456789012345678901
12345678901234567890
12345678
123456789012345678901
12345678901234567890
123456789012345678901
12345678901234567890
12345678
12345678
123456789012345678901
12345678901234567890
12345678901234567890
12345678
CE2 1234567890123456789
1234567890123456789
12345678901234567890
12345678
WE\
tAS 123456
t WP1
123456
123456
123456
tDS
DIN
t DH
DATA VALID
High-Z
DOUT
WRITE CYCLE TIMING (CE2 CONTROLLED, OE\ = LOW)
tWC
ADDR
CE\1
tAS
tAW
t AH
tCW
CE2
t WP1
1234567890123456789012345678
123456789012345678901234567
12345678
123456789012345678901234567
1234567890123456789012345678
12345678
WE\ 123456789012345678901234567
1234567890123456789012345678
12345678
123456789012345678901234567
1234567890123456789012345678
12345678
123456789012345678901234567
1234567890123456789012345678
12345678
tDS
t DH
DATA VALID
DIN
DOUT
12345678
123456789012345678901
12345678901234567890
12345678
123456789012345678901
12345678901234567890
123456789012345678901
12345678901234567890
12345678
12345678
123456789012345678901
12345678901234567890
12345678
123456789012345678901
12345678901234567890
High-Z
UNDEFINED
AS5C1008
Rev. 3.6 6/05
1234
1234
1234
1234DON’T CARE
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
7
SRAM
AS5C1008
Austin Semiconductor, Inc.
MECHANICAL DEFINITION*
ASI Case #905 (Package Designator DJ)
A A1
A2
e1
e
b
e2
D
C
B
E2
E1
E
ASI SPECIFICATIONS
SYMBOL
A
A1
A2
Β
b
C
D
E
E1
E2
e
e1
e2
MIN
MAX
0.140 BSC
0.105
0.115
0.027 TYP
0.082
--0.018 TYP
0.010 TYP
0.820
0.430
0.395
0.360
0.025
0.880
0.445
0.405
0.380
0.032
0.050 TYP
---
0.045
* All measurements are in inches.
AS5C1008
Rev. 3.6 6/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
8
SRAM
AS5C1008
Austin Semiconductor, Inc.
ORDERING INFORMATION
EXAMPLE: AS5C1008DJ-25/XT
Device Number
Package
Type
Speed
ns
Process
AS5C1008
DJ
-15
/*
AS5C1008
AS5C1008
DJ
DJ
-20
-25
/*
/*
*AVAILABLE PROCESSES
IT = Industrial Temperature Range
XT = Extended Temperature Range
AS5C1008
Rev. 3.6 6/05
-40oC to +85oC
-55oC to +125oC
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
9
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