Freescale DSPA56371 The dsp56371 is a high density cmos device with 5.0-volt compatible inputs and outputs. Datasheet

Freescale Semiconductor
Technical Data
DSP56371
Rev. 3, 1/2005
Table of Contents
1
Section
Introduction
Page
1 Introduction ................................... 1
The DSP56371 is a high density CMOS device with 5.0-volt compatible inputs and outputs.
2 DSP56371 Overview..................... 1
3 Signal/Connection Descriptions .... 8
NOTE
This document contains information on a new product.
Specifications and information herein are subject to
change without notice.
4 Maximum Ratings ....................... 30
5 Power Requirements................... 32
6 Thermal Characteristics.............. 32
7 DC Electrical Characteristics ...... 33
Finalized specifications may be published after further characterization and device
qualifications are completed.
8 AC Electrical Characteristics....... 34
9 Internal Clocks ............................ 34
10 External Clock Operation .......... 35
2
DSP56371 Overview
2.1
Introduction
11 Reset, Stop, Mode Select, and
Interrupt Timing ........................... 36
12 Serial Host Interface SPI Protocol
Timing.......................................... 39
This manual describes the DSP56371 24-bit digital signal processor (DSP), its memory,
operating modes and peripheral modules. The DSP56371 is a member of the DSP56300
family of programmable CMOS DSPs. The DSP56371 is targeted to applications that
require digital audio compression/decompression, sound field processing, acoustic
equalization and other digital audio algorithms. Changes in core functionality specific to the
DSP56371 are also described in this manual. See Figure 1. for the block diagram of the
DSP56371.
13 Serial Host Interface (SHI) I2C
Protocol Timing ........................... 44
14 Enhanced Serial Audio Interface
Timing.......................................... 46
15 Digital Audio Transmitter Timing51
16 Timer Timing ............................. 51
17 GPIO Timing ............................. 52
18 JTAG Timing ............................. 53
19 Package Information ................. 55
20 Design Considerations.............. 61
21 Power Consumption Benchmark63
22 IBIS Model ................................ 66
This document contains certain information on a new pr oduct.
Specifications and information herein ar e subject to change without notice.
© Freescale Semiconductor, Inc., 2005. All rights reserved.
DSP56371 Technical Data
DSP56371 Overview
2
5
12
12
11
Memory Expansion Area
GPIO
EFCOP
2
PIO_EB
DAX
Peripheral
Expansion Area
Address
Generation
Unit
Six Channel
DMA Unit
Program
RAM
4K × 24
X Data
RAM
36K × 24
Y Data
RAM
48K × 24
ROM
64K × 24
ROM
32K × 24
ROM
32K × 24
YAB
XAB
PAB
DAB
YM_EB
ESAI_1
Interface
XM_EB
ESAI
Interface
PM_EB
Triple
Timer
SHI
Interface
24-Bit
Bootstrap
ROM
DSP56300
Core
DDB
YDB
XDB
PDB
GDB
Internal
Data
Bus
Switch
Clock
Generator
EXTAL
RESET
PINIT/NMI
Power
Mngmnt.
PLL
Program
Interrupt
Controller
Program
Decode
Controller
Program
Address
Generator
Data ALU
24 × 24+56→56-bit MAC
Two 56-bit Accumulators
56-bit Barrel Shifter
4
JTAG
OnCE™
MODA/IRQA
MODB/IRQB
MODC/IRQC
MODD/IRQD
Figure 1. DSP56371 Block Diagram
2.2
DSP56300 Core Description
The DSP56371 uses the DSP56300 core, a high-performance, single clock cycle per instruction engine that provides up to twice
the performance of Motorola's popular DSP56000 core family while retaining code compatibility with it.
The DSP56300 core family offers a new level of performance in speed and power, provided by its rich instruction set and low
power dissipation, thus enabling a new generation of wireless, telecommunications and multimedia products. For a description
of the DSP56300 core, see Section 2.4 DSP56300 Core Functional Blocks. Significant architectural enhancements to the
DSP56300 core family include a barrel shifter, 24-bit addressing, an instruction patch module and direct memory access (DMA).
The DSP56300 core family members contain the DSP56300 core and additional modules. The modules are chosen from a library
of standard predesigned elements such as memories and peripherals. New modules may be added to the library to meet
customer specifications. A standard interface between the DSP56300 core and the on-chip memory and peripherals supports a
wide variety of memory and peripheral configurations. Refer to DSP56371 User Manual, Section 3, Memory Configuration.
Core features are described fully in the DSP56300 Family Manual. Pinout, memory and peripheral features are described in this
manual.
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Freescale Semiconductor
DSP56371 Overview
•
•
•
2.3
DSP56300 modular chassis
— 181 Million Instructions Per Second (MIPS) with a 181 MHz clock at an internal logic supply (QVDDL) of 1.25V.
— Object Code Compatible with the 56K core.
— Data ALU with a 24 x 24 bit multiplier-accumulator and a 56-bit barrel shifter. 16-bit arithmetic support.
— Program Control with position independent code support and instruction patch support.
— EFCOP running concurrently with the core, capable of executing 181 million filter taps per second at peak
performance.
— Six-channel DMA controller.
— Low jitter, PLL based clocking with a wide range of frequency multiplications (1 to 255), predivider factors (1 to 31)
and power saving clock divider (2i: i=0 to 7). Reduces clock noise.
— Internal address tracing support and OnCE for Hardware/Software debugging.
— JTAG port.
— Very low-power CMOS design, fully static design with operating frequencies down to DC.
— STOP and WAIT low-power standby modes.
On-chip Memory Configuration
— 48Kx24 Bit Y-Data RAM and 32Kx24 Bit Y-Data ROM.
— 36Kx24 Bit X-Data RAM and 32Kx24 Bit X-Data ROM.
— 64Kx24 Bit Program and Bootstrap ROM.
— 4Kx24 Bit Program RAM.
— PROM patching mechanism.
— Up to 32Kx24 Bit from Y Data RAM and 8Kx24 Bit from X Data RAM can be switched to Program RAM resulting in
up to 44Kx24 Bit of Program RAM.
Peripheral modules
— Enhanced Serial Audio Interface (ESAI): up to 4 receivers and up to 6 transmitters, master or slave. I2S, Left
justified, Right justified, Sony, AC97, network and other programmable protocols.
— Enhanced Serial Audio Interface I (ESAI_1): up to 4 receivers and up to 6 transmitters, master or slave. I2S, Left
justified, Right justified, Sony, AC97, network and other programmable protocols.
— Serial Host Interface (SHI): SPI and I2C protocols, multi master capability in I2C mode, 10-word receive FIFO,
support for 8, 16 and 24-bit words.
— Triple Timer module (TEC).
— 11 dedicated GPIO pins
— Digital Audio Transmitter (DAX): 1 serial transmitter capable of supporting the SPDIF, IEC958, CP-340 and
AES/EBU digital audio formats.
— Pins of unused peripherals (except SHI) may be programmed as GPIO lines.
DSP56371 Audio Processor Architecture
This section defines the DSP56371 audio processor architecture. The audio processor is composed of the following units:
•
The DSP56300 core is composed of the Data ALU, Address Generation Unit, Program Controller, DMA Controller,
Memory Module Interface, Peripheral Module Interface and the On-Chip Emulator (OnCE). The DSP56300 core is
described in the document DSP56300 24-Bit Digital Signal Processor Family Manual, Motorola publication
DSP56300FM/AD.
•
Phased Lock Loop and Clock Generator
•
Memory modules.
•
Peripheral modules. The peripheral modules are defined in the following sections.
Memory sizes in the block diagram are defaults. Memory may be differently partitioned, according to the memory mode of the
chip. See Section 2.4.7 On-Chip Memory for more details about memory size.
2.4
DSP56300 Core Functional Blocks
The DSP56300 core provides the following functional blocks:
•
•
Data arithmetic logic unit (Data ALU)
Address generation unit (AGU)
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DSP56371 Technical Data
3
DSP56371 Overview
•
Program control unit (PCU)
•
DMA controller (with six channels)
•
Instruction patch controller
•
PLL-based clock oscillator
•
OnCE module
•
Memory
In addition, the DSP56371 provides a set of on-chip peripherals, described in Section 2.5 Peripheral Overview.
2.4.1
Data ALU
The Data ALU performs all the arithmetic and logical operations on data operands in the DSP56300 core. The components of
the Data ALU are as follows:
•
•
•
•
•
•
•
2.4.1.1
Fully pipelined 24-bit × 24-bit parallel multiplier-accumulator (MAC)
Bit field unit, comprising a 56-bit parallel barrel shifter (fast shift and normalization; bit stream generation and parsing)
Conditional ALU instructions
24-bit or 16-bit arithmetic support under software control
Four 24-bit input general purpose registers: X1, X0, Y1 and Y0
Six Data ALU registers (A2, A1, A0, B2, B1 and B0) that are concatenated into two general purpose, 56-bit accumulators
(A and B), accumulator shifters
Two data bus shifter/limiter circuits
Data ALU Registers
The Data ALU registers can be read or written over the X memory data bus (XDB) and the Y memory data bus (YDB) as 24- or
48-bit operands (or as 16- or 32-bit operands in 16-bit arithmetic mode). The source operands for the Data ALU, which can be
24, 48, or 56 bits (16, 32, or 40 bits in 16-bit arithmetic mode), always originate from Data ALU registers. The results of all Data
ALU operations are stored in an accumulator.
All the Data ALU operations are performed in two clock cycles in pipeline fashion so that a new instruction can be initiated in
every clock, yielding an effective execution rate of one instruction per clock cycle. The destination of every arithmetic operation
can be used as a source operand for the immediately following arithmetic operation without a time penalty (i.e., without a pipeline
stall).
2.4.1.2
Multiplier-Accumulator (MAC)
The MAC unit comprises the main arithmetic processing unit of the DSP56300 core and performs all of the calculations on data
operands. In the case of arithmetic instructions, the unit accepts as many as three input operands and outputs one 56-bit result
of the following form- Extension:Most Significant Product:Least Significant Product (EXT:MSP:LSP).
The multiplier executes 24-bit × 24-bit, parallel, fractional multiplies, between two’s-complement signed, unsigned, or mixed
operands. The 48-bit product is right-justified and added to the 56-bit contents of either the A or B accumulator. A 56-bit result
can be stored as a 24-bit operand. The LSP can either be truncated or rounded into the MSP. Rounding is performed if specified.
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Freescale Semiconductor
DSP56371 Overview
2.4.2
Address Generation Unit (AGU)
The AGU performs the effective address calculations using integer arithmetic necessary to address data operands in memory
and contains the registers used to generate the addresses. It implements four types of arithmetic: linear, modulo, multiple wraparound modulo and reverse-carry. The AGU operates in parallel with other chip resources to minimize address-generation
overhead.
The AGU is divided into two halves, each with its own Address ALU. Each Address ALU has four sets of register triplets, and
each register triplet is composed of an address register, an offset register and a modifier register. The two Address ALUs are
identical. Each contains a 24-bit full adder (called an offset adder).
A second full adder (called a modulo adder) adds the summed result of the first full adder to a modulo value that is stored in its
respective modifier register. A third full adder (called a reverse-carry adder) is also provided.
The offset adder and the reverse-carry adder are in parallel and share common inputs. The only difference between them is that
the carry propagates in opposite directions. Test logic determines which of the three summed results of the full adders is output.
Each Address ALU can update one address register from its respective address register file during one instruction cycle. The
contents of the associated modifier register specifies the type of arithmetic to be used in the address register update calculation.
The modifier value is decoded in the Address ALU.
2.4.3
Program Control Unit (PCU)
The PCU performs instruction prefetch, instruction decoding, hardware DO loop control and exception processing. The PCU
implements a seven-stage pipeline and controls the different processing states of the DSP56300 core. The PCU consists of the
following three hardware blocks:
•
Program decode controller (PDC)
•
Program address generator (PAG)
•
Program interrupt controller
The PDC decodes the 24-bit instruction loaded into the instruction latch and generates all signals necessary for pipeline control.
The PAG contains all the hardware needed for program address generation, system stack and loop control. The Program
interrupt controller arbitrates among all interrupt requests (internal interrupts, as well as the five external requests: IRQA, IRQB,
IRQC, IRQD and NMI) and generates the appropriate interrupt vector address.
PCU features include the following:
•
Position independent code support
•
Addressing modes optimized for DSP applications (including immediate offsets)
•
On-chip instruction cache controller
•
On-chip memory-expandable hardware stack
•
Nested hardware DO loops
•
Fast auto-return interrupts
The PCU implements its functions using the following registers:
•
PC—program counter register
•
SR—Status register
•
LA—loop address register
•
LC—loop counter register
•
VBA—vector base address register
•
SZ—stack size register
•
SP—stack pointer
•
OMR—operating mode register
•
SC—stack counter register
The PCU also includes a hardware system stack (SS).
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DSP56371 Technical Data
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DSP56371 Overview
2.4.4
Internal Buses
To provide data exchange between blocks, the following buses are implemented:
•
•
•
•
•
Peripheral input/output expansion bus (PIO_EB) to peripherals
Program memory expansion bus (PM_EB) to program memory
X memory expansion bus (XM_EB) to X memory
Y memory expansion bus (YM_EB) to Y memory
Global data bus (GDB) between registers in the DMA, AGU, OnCE, PLL, BIU and PCU, as well as the memory-mapped
registers in the peripherals
•
DMA data bus (DDB) for carrying DMA data between memories and/or peripherals
•
DMA address bus (DAB) for carrying DMA addresses to memories and peripherals
•
Program Data Bus (PDB) for carrying program data throughout the core
•
X memory Data Bus (XDB) for carrying X data throughout the core
•
Y memory Data Bus (YDB) for carrying Y data throughout the core
•
Program address bus (PAB) for carrying program memory addresses throughout the core
•
X memory address bus (XAB) for carrying X memory addresses throughout the core
•
Y memory address bus (YAB) for carrying Y memory addresses throughout the core
All internal buses on the DSP56300 family members are 24-bit buses. See Figure 1.
2.4.5
Direct Memory Access (DMA)
The DMA block has the following features:
•
•
•
•
2.4.6
Six DMA channels supporting internal and external accesses
One-, two- and three-dimensional transfers (including circular buffering)
End-of-block-transfer interrupts
Triggering from interrupt lines and all peripherals
PLL-based Clock Oscillator
The clock generator in the DSP56300 core is composed of two main blocks: the PLL, which performs clock input division,
frequency multiplication, skew elimination and the clock generator (CLKGEN), which performs low-power division and clock pulse
generation. PLL-based clocking:
•
•
•
Allows change of low-power divide factor (DF) without loss of lock
Provides output clock with skew elimination
Provides a wide range of frequency multiplications (1 to 255), predivider factors (1 to 31), PLL feedback multiplier (2 or
4), Output divide factor (1, 2 or 4) and a power-saving clock divider (2i: i = 0 to 7) to reduce clock noise
The PLL allows the processor to operate at a high internal clock frequency using a low frequency clock input. This feature offers
two immediate benefits:
•
•
A lower frequency clock input reduces the overall electromagnetic interference generated by a system.
The ability to oscillate at different frequencies reduces costs by eliminating the need to add additional oscillators to a
system.
NOTE
The PLL will momentarily overshoot the target frequency when the PLL is first enabled or
when the VCO frequency is modified. It is important that when modifying the PLL frequency
or enabling the PLL that the two step procedure defined in Section 3, DSP56371 Overview
be followed.
2.4.7
On-Chip Memory
The memory space of the DSP56300 core is partitioned into program memory space, X data memory space and Y data memory
space. The data memory space is divided into X and Y data memory in order to work with the two Address ALUs and to feed two
operands simultaneously to the Data ALU. Memory space includes internal RAM and ROM and can not be expanded off-chip.
There is an instruction patch module. The patch module is used to patch program ROM. The memory switch mode is used to
increase the size of program RAM as needed (switch from X data RAM and/or Y data RAM).
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DSP56371 Technical Data
Freescale Semiconductor
DSP56371 Overview
There are on-chip ROMs for program and bootstrap memory (64K x 24-bit), X ROM (32K x 24-bit) and Y ROM(32K x 24-bit).
More information on the internal memory is provided in DSP56371 User Manual, Section 3, MemorySection 3, .
2.4.8
Off-Chip Memory Expansion
Memory cannot be expanded off-chip. There is no external memory bus.
2.5
Peripheral Overview
The DSP56371 is designed to perform a wide variety of fixed-point digital signal processing functions. In addition to the core
features previously discussed, the DSP56371 provides the following peripherals:
•
•
•
•
•
•
•
•
2.5.1
As many as 39 dedicate or user-configurable general purpose input/output (GPIO) signals
Timer/event counter (TEC) module, containing three independent timers
Memory switch mode in on-chip memory
Four external interrupt/mode control lines and one external non-maskable interrupt line
Enhanced serial audio interface (ESAI) with up to four receivers and up to six transmitters, master or slave, using the
I2S, Sony, AC97, network and other programmable protocols
A second enhanced serial audio interface (ESAI_1) with up to four receivers and up to six transmitters, master or slave,
using the I2S, Sony, AC97, network and other programmable protocols.
Serial host interface (SHI) using SPI and I2C protocols, with multi-master capability, 10-word receive FIFO and support
for 8-, 16- and 24-bit words
A Digital audio transmitter (DAX): a serial transmitter capable of supporting the SPDIF, IEC958, CP-340 and AES/EBU
digital audio formats
General Purpose Input/Output (GPIO)
The DSP56371 provides 11 dedicated GPIO and 28 programmable signals that can operate either as GPIO pins or peripheral
pins (ESAI, ESAI_1, DAX, and TEC). The signals are configured as GPIO after hardware reset. Register programming
techniques for all GPIO functionality among these interfaces are very similar and are described in the following sections.
2.5.2
Triple Timer (TEC)
This section describes a peripheral module composed of a common 21-bit prescaler and three independent and identical general
purpose 24-bit timer/event counters, each one having its own register set.
Each timer can use internal or external clocking and can interrupt the DSP after a specified number of events (clocks). Two of
the three timers can signal an external device after counting internal events. Each timer can also be used to trigger DMA transfers
after a specified number of events (clocks) occurred. Two of the three timers connect to the external world through bidirectional
pins (TIO0, TIO1). When a TIO pin is configured as input, the timer functions as an external event counter or can measure
external pulse width/signal period. When a TIO pin is used as output the timer is functioning as either a timer, a watchdog or a
Pulse Width Modulator. When a TIO pin is not used by the timer it can be used as a General Purpose Input/Output Pin. Refer to
DSP56371 User Manual, Section 11, Triple Timer Module.
2.5.3
Enhanced Serial Audio Interface (ESAI)
The ESAI provides a full-duplex serial port for serial communication with a variety of serial devices including one or more industrystandard codecs, other DSPs, microprocessors and peripherals that implement the Motorola SPI serial protocol. The ESAI
consists of independent transmitter and receiver sections, each with its own clock generator. It is a superset of the DSP56300
family ESSI peripheral and of the DSP56000 family SAI peripheral. For more information on the ESAI, refer to DSP56371 User
Manual, Section 8, Enhanced Serial Audio Interface (ESAI).
2.5.4
Enhanced Serial Audio Interface 1 (ESAI_1)
The ESAI_1 is a second ESAI interface. The ESAI_1 is functionally identical to ESAI. For more information on the ESAI_1, refer
to DSP56371 User Manual, Section 9, Enhanced Serial Audio Interface (ESAI_1).
2.5.5
Serial Host Interface (SHI)
The SHI is a serial input/output interface providing a path for communication and program/coefficient data transfers between the
DSP and an external host processor. The SHI can also communicate with other serial peripheral devices. The SHI can interface
directly to either of two well-known and widely used synchronous serial buses: the Motorola serial peripheral interface (SPI) bus
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DSP56371 Technical Data
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Signal/Connection Descriptions
and the Philips inter-integrated-circuit control (I2C) bus. The SHI supports either the SPI or I2C bus protocol, as required, from a
slave or a single-master device. To minimize DSP overhead, the SHI supports single-, double- and triple-byte data transfers. The
SHI has a 10-word receive FIFO that permits receiving up to 30 bytes before generating a receive interrupt, reducing the overhead
for data reception. For more information on the SHI, refer to DSP56371 User Manual, Section 7, Serial Host Interface.
2.5.6
Digital Audio Transmitter (DAX)
The DAX is a serial audio interface module that outputs digital audio data in the AES/EBU, CP-340 and IEC958 formats. For
more information on the DAX, refer to DSP56371 User Manual, Section 10, Digital Audio.
3
Signal/Connection Descriptions
3.1
Signal Groupings
The input and output signals of the DSP56374 are organized into functional groups, which are listed in Table 1. and illustrated in
Figure 2.
The DSP56374 is operated from a 1.25 V and 3.3 V supply; however, some of the inputs can tolerate 5.0 V. A special notice for
this feature is added to the signal descriptions of those inputs.
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DSP56371 Technical Data
Freescale Semiconductor
Signal/Connection Descriptions
Table 1. DSP56374 Functional Signal Groupings
Number of
Signals
Detailed
Description
Power (VDD)
12
Table 2.
Ground (GND)
12
Table 3.
Scan Pins
1
Table 4.
Clock and PLL
2
Table 5.
Interrupt and mode control
5
Table 6.
SHI
5
Table 7.
Functional Group
ESAI
Port C1
12
Table 8.
ESAI_1
Port E2
12
Table 9.
SPDIF Transmitter (DAX)
Port D3
2
Table 10.
Dedicated GPIO
Port F4
11
Table 11.
Timer
2
Table 12.
JTAG/OnCE Port
4
Table 13.
Notes:
1.
2.
3.
4.
Port C signals are the GPIO port signals which are multiplexed with the ESAI signals.
Port E signals are the GPIO port signals which are multiplexed with the ESAI_1 signals.
Port D signals are the GPIO port signals which are multiplexed with the DAX signals.
Port F signals are the dedicated GPIO port signals.
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DSP56371 Technical Data
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Signal/Connection Descriptions
Pinout (80 pin package)
GPIO
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
Port F
SPDIF TRANSMITTER (DAX)
Port D
MOSI/HA0
SS/HA2
MISO/HDA
SCK/SCL
SHI
HREQ
Port C
TIO0
TIO1
TIMER
SCKT
FST
HCKT
SCKR
ESAI
FSR
HCKR
SDO0
SDO1
SDO2/SDI3
ADO [PD1]
ACI [PD0]
INTERRUPTS
IRQA/MODA
IRGB/MODB
IRQC/MODC
IRQD/MODD
RESET
SDO3/SDI2
SDO4/SDI1
SDO5/SDI0
SCKT_1
FST_1
HCKT_1
SCKR_1
Port E
PLL AND CLOCK
EXTAL
NMI/PINIT
PLL_VDD(3)
PLL_GND(3)
ESAI_1
FSR_1
HCKR_1
SDO0_1
SDO1_1
SDO2_1/SDI3_1
CORE POWER
CORE_VDD (4)
CORE_GND (4)
SDO3_1/SDI2_1
SDO4_1/SDI1_1
SDO5_1/SDI0_1
OnCE/JTAG
TDI
TCLK
TDO
TMS
PERIPHERAL I/O POWER
IO_VDD (5)
IO_GNDS (5)
SCAN
SCAN
Figure 2. Signals Identified by Functional Group
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Freescale Semiconductor
Signal/Connection Descriptions
3.2
Power
Table 2. Power Inputs
Power Name
Description
PLLA_VDD (1)
PLL Power— The voltage (3.3 V) should be well-regulated and the input should be provided with
an extremely low impedance path to the 3.3 VDD power rail. The user must provide adequate
external decoupling capacitors.
PLLP_VDD(1)
PLLD_VDD (1)
PLL Power— The voltage (1.25 V) should be well-regulated and the input should be provided with
an extremely low impedance path to the 1.25 VDD power rail. The user must provide adequate
external decoupling capacitors.
CORE_VDD (4) Core Power—The voltage (1.25 V) should be well-regulated and the input should be provided with
an extremely low impedance path to the 1.25 VDD power rail. The user must provide adequate
decoupling capacitors.
SHI, ESAI, ESAI_1, DAX and Timer I/O Power —The voltage (3.3 V) should be well-regulated
and the input should be provided with an extremely low impedance path to the 3.3 VDD power rail.
This is an isolated power for the SHI, ESAI, ESAI_1, DAX and Timer I/O. The user must provide
adequate external decoupling capacitors.
ESAI
61
62
63
64
65
66
67
68
DAX
ESAI_1
60
1
59
2
58
3
57
4
56
5
55
6
54
7
53
8
52
9
51
10
50
11
49
Int/Mod
12
13
GPIO
48
47
14
46
15
45
16
44
17
43
PLL
18
42
40
39
38
41
37
36
35
34
SHI
33
32
31
30
28
27
26
25
23
22
OnCE
FST_PE4
SDO5_SDI0_PE6
SDO4_SDI1_PE7
SDO3_SDI2_PE8
SDO2_SDI3_PE9
SDO1_PE10
SDO0_PE11
CORE_GND
CORE_VDD
MODB_IRQA
MODB_IRQB
MODC_IRQC
MODD_IRQD
RESET_B
PINIT_NMI
EXTAL
PLLD_VDD
PLLD_GND
PLLP_GND
PLLP_VDD
PF9
SCAN
PF10
IO_GND
IO_VDD
TIO0_PB0
TIO1_PB1
CORE_GND
CORE_VDD
TDO
TDI
TCK
TMS
MOSI_HA0
MISO_SDA
SCK_SCL
SS_HA2
HREQ
PLLA_VDD
PLLA_GND
24
Timer
20
29
19
21
SDO5_SDI0_PC7
IO_GND
IO_VDD
SDO3_SDI2_PC8
SDO2_SDI3_PC9
SDO1_PC10
SDO0_PC11
CORE_VDD
PF8
PF6
PF7
CORE_GND
PF2
PF3
PF4
PF5
IO_VDD
PF1
PF0
IO_GND
69
70
71
72
73
74
75
76
77
78
79
0
8
SDO5_SDI0_PC6
FST_PC4
FSR_PC1
SCKT_PC3
SCKR_PC0
IO_VDD
IO_GND
HCKT_PC5
HCKR_PC2
CORE_VDD
ACI_PD0
ADO_PD1
CORE_GND
HCKR_PE2
HCKT_PE5
IO_GND
IO_VDD
SCKR_PE0
SCKT_PE3
FSR_PE1
IO_VDD (5)
1.25V
3.3V
Figure 3. VDD Connections
Freescale Semiconductor
DSP56371 Technical Data
11
Signal/Connection Descriptions
3.3
Ground
Table 3. Grounds
Ground Name
PLLA_GND(1)
PLLP_GND(1)
PLLD_GND(1)
Description
PLL Ground—The PLL ground should be provided with an extremely low-impedance path to
ground. The user must provide adequate external decoupling capacitors.
PLL Ground—The PLL ground should be provided with an extremely low-impedance path to
ground. The user must provide adequate external decoupling capacitors.
CORE_GND (4) Core Ground—The Core ground should be provided with an extremely low-impedance path to
ground. This connection must be tied externally to all other chip ground connections. The user
must provide adequate external decoupling capacitors.
IO_GND (5)
3.4
SHI, ESAI, ESAI_1, DAX and Timer I/O Ground—IO_GND is an isolated ground for the SHI,
ESAI, ESAI_1, DAX and Timer I/O. This connection must be tied externally to all other chip ground
connections. The user must provide adequate external decoupling capacitors.
SCAN
Table 4. SCAN signals
Signal
Name
Type
State
during
Reset
SCAN
Input
Input
Signal Description
SCAN—Manufacturing test pin. This pin should be pulled low.
Internal Pull down resistor.
3.5
Clock and PLL
Table 5. Clock and PLL Signals
Signal
Name
Type
State
during
Reset
EXTAL
Input
Input
Signal Description
External Clock Input—An external clock source must be connected to EXTAL
in order to supply the clock to the internal clock generator and PLL.
This input cannot tolerate 5 V.
PINIT/NMI
Input
Input
PLL Initial/Nonmaskable Interrupt—During assertion of RESET, the value of
PINIT/NMI is written into the PLL Enable (PEN) bit of the PLL control register,
determining whether the PLL is enabled or disabled. After RESET de assertion
and during normal instruction processing, the PINIT/NMI Schmitt-trigger input is
a negative-edge-triggered nonmaskable interrupt (NMI) request internally
synchronized to internal system clock.
Internal Pull up resistor.
This input is 5 V tolerant.
3.6
Interrupt and Mode Control
The interrupt and mode control signals select the chip’s operating mode as it comes out of hardware reset. After RESET is
deasserted, these inputs are hardware interrupt request lines.
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DSP56371 Technical Data
Freescale Semiconductor
Signal/Connection Descriptions
Table 6. Interrupt and Mode Control
Signal Name
Type
State
During
Reset
MODA/IRQA
Input
Input
Signal Description
Mode Select A/External Interrupt Request A—MODA/IRQA is an active-low
Schmitt-trigger input, internally synchronized to the DSP clock. MODA/IRQA
selects the initial chip operating mode during hardware reset and becomes a
level-sensitive or negative-edge-triggered, maskable interrupt request input
during normal instruction processing. MODA, MODB, MODC and MODD
select one of 16 initial chip operating modes, latched into the OMR when the
RESET signal is deasserted. If the processor is in the stop standby state and
the MODA/IRQA pin is pulled to GND, the processor will exit the stop state.
Internal Pull up resistor.
This input is 5 V tolerant.
MODB/IRQB
Input
Input
Mode Select B/External Interrupt Request B—MODB/IRQB is an active-low
Schmitt-trigger input, internally synchronized to the DSP clock. MODB/IRQB
selects the initial chip operating mode during hardware reset and becomes a
level-sensitive or negative-edge-triggered, maskable interrupt request input
during normal instruction processing. MODA, MODB, MODC and MODD
select one of 16 initial chip operating modes, latched into OMR when the
RESET signal is deasserted.
Internal Pull up resistor.
This input is 5 V tolerant.
MODC/IRQC
Input
Input
Mode Select C/External Interrupt Request C—MODC/IRQC is an active-low
Schmitt-trigger input, internally synchronized to the DSP clock. MODC/IRQC
selects the initial chip operating mode during hardware reset and becomes a
level-sensitive or negative-edge-triggered, maskable interrupt request input
during normal instruction processing. MODA, MODB, MODC and MODD
select one of 16 initial chip operating modes, latched into OMR when the
RESET signal is deasserted.
Internal Pull up resistor.
This input is 5 V tolerant.
MODD/IRQD
Input
Input
Mode Select D/External Interrupt Request D—MODD/IRQD is an active-low
Schmitt-trigger input, internally synchronized to the DSP clock. MODD/IRQD
selects the initial chip operating mode during hardware reset and becomes a
level-sensitive or negative-edge-triggered, maskable interrupt request input
during normal instruction processing. MODA, MODB, MODC and MODD
select one of 16 initial chip operating modes, latched into OMR when the
RESET signal is deasserted.
Internal Pull up resistor.
This input is 5 V tolerant.
Freescale Semiconductor
DSP56371 Technical Data
13
Signal/Connection Descriptions
Table 6. Interrupt and Mode Control (Continued)
Signal Name
Type
State
During
Reset
RESET
Input
Input
Signal Description
Reset—RESET is an active-low, Schmitt-trigger input. When asserted, the
chip is placed in the Reset state and the internal phase generator is reset. The
Schmitt-trigger input allows a slowly rising input (such as a capacitor charging)
to reset the chip reliably. When the RESET signal is deasserted, the initial chip
operating mode is latched from the MODA, MODB, MODC and MODD inputs.
The RESET signal must be asserted during power up. A stable EXTAL signal
must be supplied while RESET is being asserted.
Internal Pull up resistor.
This input is 5 V tolerant.
3.7
Serial Host Interface
The SHI has five I/O signals that can be configured to allow the SHI to operate in either SPI or I2C mode.
Table 7. Serial Host Interface Signals
Signal
Name
Signal
Type
State
during
Reset
SCK
Input or
output
Tri-stated
SCL
Input or
output
Signal Description
SPI Serial Clock—The SCK signal is an output when the SPI is configured as a
master and a Schmitt-trigger input when the SPI is configured as a slave. When
the SPI is configured as a master, the SCK signal is derived from the internal
SHI clock generator. When the SPI is configured as a slave, the SCK signal is
an input, and the clock signal from the external master synchronizes the data
transfer. The SCK signal is ignored by the SPI if it is defined as a slave and the
slave select (SS) signal is not asserted. In both the master and slave SPI
devices, data is shifted on one edge of the SCK signal and is sampled on the
opposite edge where data is stable. Edge polarity is determined by the SPI
transfer protocol.
I2C Serial Clock—SCL carries the clock for I2C bus transactions in the I2C
mode. SCL is a Schmitt-trigger input when configured as a slave and an opendrain output when configured as a master. SCL should be connected to VDD
through a pull-up resistor.
This signal is tri-stated during hardware, software and individual reset. Thus,
there is no need for an external pull-up in this state.
Internal Pull up resistor.
This input is 5 V tolerant.
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DSP56371 Technical Data
Freescale Semiconductor
Signal/Connection Descriptions
Table 7. Serial Host Interface Signals (Continued)
Signal
Name
Signal
Type
State
during
Reset
Input or
output
Tri-stated
MISO
SDA
Signal Description
SPI Master-In-Slave-Out—When the SPI is configured as a master, MISO is
the master data input line. The MISO signal is used in conjunction with the
MOSI signal for transmitting and receiving serial data. This signal is a Schmitttrigger input when configured for the SPI Master mode, an output when
configured for the SPI Slave mode, and tri-stated if configured for the SPI Slave
mode when SS is deasserted. An external pull-up resistor is not required for
SPI operation.
I2C Data and Acknowledge—In I2C mode, SDA is a Schmitt-trigger input when
receiving and an open-drain output when transmitting. SDA should be
connected to VDD through a pull-up resistor. SDA carries the data for I2C
transactions. The data in SDA must be stable during the high period of SCL.
The data in SDA is only allowed to change when SCL is low. When the bus is
free, SDA is high. The SDA line is only allowed to change during the time SCL is
high in the case of start and stop events. A high-to-low transition of the SDA line
while SCL is high is a unique situation, and it is defined as the start event. A
low-to-high transition of SDA while SCL is high is a unique situation defined as
the stop event.
Input or
open-drain
output
This signal is tri-stated during hardware, software and individual reset. Thus,
there is no need for an external pull-up in this state.
Internal Pull up resistor.
This input is 5 V tolerant.
MOSI
Input or
output
HA0
Input
Tri-stated
SPI Master-Out-Slave-In—When the SPI is configured as a master, MOSI is
the master data output line. The MOSI signal is used in conjunction with the
MISO signal for transmitting and receiving serial data. MOSI is the slave data
input line when the SPI is configured as a slave. This signal is a Schmitt-trigger
input when configured for the SPI Slave mode.
I2C Slave Address 0—This signal uses a Schmitt-trigger input when
configured for the I2C mode. When configured for I2C slave mode, the HA0
signal is used to form the slave device address. HA0 is ignored when
configured for the I2C master mode.
This signal is tri-stated during hardware, software and individual reset. Thus,
there is no need for an external pull-up in this state.
Internal Pull up resistor.
This input is 5 V tolerant.
Freescale Semiconductor
DSP56371 Technical Data
15
Signal/Connection Descriptions
Table 7. Serial Host Interface Signals (Continued)
Signal
Name
Signal
Type
State
during
Reset
Input
Tri-stated
SS
HA2
Signal Description
SPI Slave Select—This signal is an active low Schmitt-trigger input when
configured for the SPI mode. When configured for the SPI Slave mode, this
signal is used to enable the SPI slave for transfer. When configured for the SPI
master mode, this signal should be kept deasserted (pulled high). If it is
asserted while configured as SPI master, a bus error condition is flagged. If SS
is deasserted, the SHI ignores SCK clocks and keeps the MISO output signal in
the high-impedance state.
I2C Slave Address 2—This signal uses a Schmitt-trigger input when
configured for the I2C mode. When configured for the I2C Slave mode, the HA2
signal is used to form the slave device address. HA2 is ignored in the I2C
master mode.
Input
This signal is tri-stated during hardware, software and individual reset. Thus,
there is no need for an external pull-up in this state.
Internal Pull up resistor.
This input is 5 V tolerant.
HREQ
Input or
Output
Tri-stated
Host Request—This signal is an active low Schmitt-trigger input when
configured for the master mode but an active low output when configured for the
slave mode.
When configured for the slave mode, HREQ is asserted to indicate that the SHI
is ready for the next data word transfer and deasserted at the first clock pulse of
the new data word transfer. When configured for the master mode, HREQ is an
input. When asserted by the external slave device, it will trigger the start of the
data word transfer by the master. After finishing the data word transfer, the
master will await the next assertion of HREQ to proceed to the next transfer.
This signal is tri-stated during hardware, software, personal reset, or when the
HREQ1–HREQ0 bits in the HCSR are cleared. There is no need for an external
pull-up in this state.
Internal Pull up resistor.
This input is 5 V tolerant.
16
DSP56371 Technical Data
Freescale Semiconductor
Signal/Connection Descriptions
3.8
Enhanced Serial Audio Interface
Table 8. Enhanced Serial Audio Interface Signals
Signal
Name
Signal Type
State during
Reset
Signal Description
HCKR
Input or output
GPIO
disconnected
High Frequency Clock for Receiver—When programmed as an
input, this signal provides a high frequency clock source for the
ESAI receiver as an alternate to the DSP core clock. When
programmed as an output, this signal can serve as a highfrequency sample clock (e.g., for external digital to analog
converters [DACs]) or as an additional system clock.
PC2
Input, output, or
disconnected
Port C2—When the ESAI is configured as GPIO, this signal is
individually programmable as input, output, or internally
disconnected.
The default state after reset is GPIO disconnected.
Internal Pull down resistor.
This input is 5 V tolerant.
HCKT
Input or output
PC5
Input, output, or
disconnected
GPIO
disconnected
High Frequency Clock for Transmitter—When programmed as
an input, this signal provides a high frequency clock source for the
ESAI transmitter as an alternate to the DSP core clock. When
programmed as an output, this signal can serve as a high
frequency sample clock (e.g., for external DACs) or as an
additional system clock.
Port C5—When the ESAI is configured as GPIO, this signal is
individually programmable as input, output, or internally
disconnected.
The default state after reset is GPIO disconnected.
Internal Pull down resistor.
This input is 5 V tolerant.
Freescale Semiconductor
DSP56371 Technical Data
17
Signal/Connection Descriptions
Table 8. Enhanced Serial Audio Interface Signals (Continued)
Signal
Name
Signal Type
State during
Reset
Signal Description
FSR
Input or output
GPIO
disconnected
Frame Sync for Receiver—This is the receiver frame sync
input/output signal. In the asynchronous mode (SYN=0), the FSR
pin operates as the frame sync input or output used by all the
enabled receivers. In the synchronous mode (SYN=1), it operates
as either the serial flag 1 pin (TEBE=0), or as the transmitter
external buffer enable control (TEBE=1, RFSD=1).
When this pin is configured as serial flag pin, its direction is
determined by the RFSD bit in the RCCR register. When
configured as the output flag OF1, this pin will reflect the value of
the OF1 bit in the SAICR register, and the data in the OF1 bit will
show up at the pin synchronized to the frame sync in normal
mode or the slot in network mode. When configured as the input
flag IF1, the data value at the pin will be stored in the IF1 bit in the
SAISR register, synchronized by the frame sync in normal mode
or the slot in network mode.
PC1
Input, output, or
disconnected
Port C1—When the ESAI is configured as GPIO, this signal is
individually programmable as input, output, or internally
disconnected.
The default state after reset is GPIO disconnected.
Internal Pull down resistor.
This input is 5 V tolerant.
FST
Input or output
PC4
Input, output, or
disconnected
GPIO
disconnected
Frame Sync for Transmitter—This is the transmitter frame sync
input/output signal. For synchronous mode, this signal is the
frame sync for both transmitters and receivers. For asynchronous
mode, FST is the frame sync for the transmitters only. The
direction is determined by the transmitter frame sync direction
(TFSD) bit in the ESAI transmit clock control register (TCCR).
Port C4—When the ESAI is configured as GPIO, this signal is
individually programmable as input, output, or internally
disconnected.
The default state after reset is GPIO disconnected.
Internal Pull down resistor.
This input is 5 V tolerant.
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DSP56371 Technical Data
Freescale Semiconductor
Signal/Connection Descriptions
Table 8. Enhanced Serial Audio Interface Signals (Continued)
Signal
Name
Signal Type
State during
Reset
Signal Description
SCKR
Input or output
GPIO
disconnected
Receiver Serial Clock—SCKR provides the receiver serial bit
clock for the ESAI. The SCKR operates as a clock input or output
used by all the enabled receivers in the asynchronous mode
(SYN=0), or as serial flag 0 pin in the synchronous mode
(SYN=1).
When this pin is configured as serial flag pin, its direction is
determined by the RCKD bit in the RCCR register. When
configured as the output flag OF0, this pin will reflect the value of
the OF0 bit in the SAICR register, and the data in the OF0 bit will
show up at the pin synchronized to the frame sync in normal
mode or the slot in network mode. When configured as the input
flag IF0, the data value at the pin will be stored in the IF0 bit in the
SAISR register, synchronized by the frame sync in normal mode
or the slot in network mode.
PC0
Input, output, or
disconnected
Port C0—When the ESAI is configured as GPIO, this signal is
individually programmable as input, output, or internally
disconnected.
The default state after reset is GPIO disconnected.
Internal Pull down resistor.
This input is 5 V tolerant.
SCKT
Input or output
PC3
Input, output, or
disconnected
GPIO
disconnected
Transmitter Serial Clock—This signal provides the serial bit rate
clock for the ESAI. SCKT is a clock input or output used by all
enabled transmitters and receivers in synchronous mode, or by all
enabled transmitters in asynchronous mode.
Port C3—When the ESAI is configured as GPIO, this signal is
individually programmable as input, output, or internally
disconnected.
The default state after reset is GPIO disconnected.
Internal Pull down resistor.
This input is 5 V tolerant.
SDO5
Output
GPIO
disconnected
Serial Data Output 5—When programmed as a transmitter,
SDO5 is used to transmit data from the TX5 serial transmit shift
register.
SDI0
Input
Serial Data Input 0—When programmed as a receiver, SDI0 is
used to receive serial data into the RX0 serial receive shift
register.
PC6
Input, output, or
disconnected
Port C6—When the ESAI is configured as GPIO, this signal is
individually programmable as input, output, or internally
disconnected.
The default state after reset is GPIO disconnected.
Internal Pull down resistor.
This input is 5 V tolerant.
Freescale Semiconductor
DSP56371 Technical Data
19
Signal/Connection Descriptions
Table 8. Enhanced Serial Audio Interface Signals (Continued)
Signal
Name
Signal Type
State during
Reset
SDO4
Output
GPIO
disconnected
SDI1
Input
Serial Data Input 1—When programmed as a receiver, SDI1 is
used to receive serial data into the RX1 serial receive shift
register.
PC7
Input, output, or
disconnected
Port C7—When the ESAI is configured as GPIO, this signal is
individually programmable as input, output, or internally
disconnected.
Signal Description
Serial Data Output 4—When programmed as a transmitter,
SDO4 is used to transmit data from the TX4 serial transmit shift
register.
The default state after reset is GPIO disconnected.
Internal Pull down resistor.
This input is 5 V tolerant.
SDO3
Output
GPIO
disconnected
Serial Data Output 3—When programmed as a transmitter,
SDO3 is used to transmit data from the TX3 serial transmit shift
register.
SDI2
Input
Serial Data Input 2—When programmed as a receiver, SDI2 is
used to receive serial data into the RX2 serial receive shift
register.
PC8
Input, output, or
disconnected
Port C8—When the ESAI is configured as GPIO, this signal is
individually programmable as input, output, or internally
disconnected.
The default state after reset is GPIO disconnected.
Internal Pull down resistor.
This input is 5 V tolerant.
20
DSP56371 Technical Data
Freescale Semiconductor
Signal/Connection Descriptions
Table 8. Enhanced Serial Audio Interface Signals (Continued)
Signal
Name
Signal Type
State during
Reset
SDO2
Output
GPIO
disconnected
SDI3
Input
Serial Data Input 3—When programmed as a receiver, SDI3 is
used to receive serial data into the RX3 serial receive shift
register.
PC9
Input, output, or
disconnected
Port C9—When the ESAI is configured as GPIO, this signal is
individually programmable as input, output, or internally
disconnected.
Signal Description
Serial Data Output 2—When programmed as a transmitter,
SDO2 is used to transmit data from the TX2 serial transmit shift
register
The default state after reset is GPIO disconnected.
Internal Pull down resistor.
This input is 5 V tolerant.
SDO1
Output
PC10
Input, output, or
disconnected
GPIO
disconnected
Serial Data Output 1—SDO1 is used to transmit data from the
TX1 serial transmit shift register.
Port C10—When the ESAI is configured as GPIO, this signal is
individually programmable as input, output, or internally
disconnected.
The default state after reset is GPIO disconnected.
Internal Pull down resistor.
This input is 5 V tolerant.
SDO0
Output
PC11
Input, output, or
disconnected
GPIO
disconnected
Serial Data Output 0—SDO0 is used to transmit data from the
TX0 serial transmit shift register.
Port C11—When the ESAI is configured as GPIO, this signal is
individually programmable as input, output, or internally
disconnected.
The default state after reset is GPIO disconnected.
Internal Pull down resistor.
This input is 5 V tolerant.
Freescale Semiconductor
DSP56371 Technical Data
21
Signal/Connection Descriptions
3.9
Enhanced Serial Audio Interface_1
Table 9. Enhanced Serial Audio Interface_1 Signals
Signal Name
Signal Type
State during
Reset
Signal Description
HCKR_1
Input or output
GPIO
disconnected
High Frequency Clock for Receiver—When programmed as
an input, this signal provides a high frequency clock source for
the ESAI_1 receiver as an alternate to the DSP core clock.
When programmed as an output, this signal can serve as a
high-frequency sample clock (e.g., for external digital to analog
converters [DACs]) or as an additional system clock.
PE2
Input, output, or
disconnected
Port E2—When the ESAI_1 is configured as GPIO, this signal
is individually programmable as input, output, or internally
disconnected.
The default state after reset is GPIO disconnected.
Internal Pull down resistor.
This input is 5 V tolerant.
HCKT_1
Input or output
PE5
Input, output, or
disconnected
GPIO
disconnected
High Frequency Clock for Transmitter—When programmed
as an input, this signal provides a high frequency clock source
for the ESAI_1 transmitter as an alternate to the DSP core
clock. When programmed as an output, this signal can serve as
a high frequency sample clock (e.g., for external DACs) or as an
additional system clock.
Port E5—When the ESAI_1 is configured as GPIO, this signal
is individually programmable as input, output, or internally
disconnected.
The default state after reset is GPIO disconnected.
Internal Pull down resistor.
This input is 5 V tolerant.
22
DSP56371 Technical Data
Freescale Semiconductor
Signal/Connection Descriptions
Table 9. Enhanced Serial Audio Interface_1 Signals
Signal Name
Signal Type
State during
Reset
Signal Description
FSR_1
Input or output
GPIO
disconnected
Frame Sync for Receiver_1—This is the receiver frame sync
input/output signal. In the asynchronous mode (SYN=0), the
FSR_1 pin operates as the frame sync input or output used by
all the enabled receivers. In the synchronous mode (SYN=1), it
operates as either the serial flag 1 pin (TEBE=0), or as the
transmitter external buffer enable control (TEBE=1, RFSD=1).
When this pin is configured as serial flag pin, its direction is
determined by the RFSD bit in the RCCR_1 register. When
configured as the output flag OF1, this pin will reflect the value
of the OF1 bit in the SAICR_1 register, and the data in the OF1
bit will show up at the pin synchronized to the frame sync in
normal mode or the slot in network mode. When configured as
the input flag IF1, the data value at the pin will be stored in the
IF1 bit in the SAISR register, synchronized by the frame sync in
normal mode or the slot in network mode.
PE1
Input, output, or
disconnected
Port E1—When the ESAI_1 is configured as GPIO, this signal
is individually programmable as input, output, or internally
disconnected.
The default state after reset is GPIO disconnected.
Internal Pull down resistor.
This input is 5 V tolerant.
FST_1
Input or output
PE4
Input, output, or
disconnected
GPIO
disconnected
Frame Sync for Transmitter_1—This is the transmitter frame
sync input/output signal. For synchronous mode, this signal is
the frame sync for both transmitters and receivers. For
asynchronous mode, FST_1 is the frame sync for the
transmitters only. The direction is determined by the transmitter
frame sync direction (TFSD) bit in the ESAI_1 transmit clock
control register (TCCR_1).
Port E4—When the ESAI_1 is configured as GPIO, this signal
is individually programmable as input, output, or internally
disconnected.
The default state after reset is GPIO disconnected.
Internal Pull down resistor.
This input is 5 V tolerant.
Freescale Semiconductor
DSP56371 Technical Data
23
Signal/Connection Descriptions
Table 9. Enhanced Serial Audio Interface_1 Signals
Signal Name
Signal Type
State during
Reset
Signal Description
SCKR_1
Input or output
GPIO
disconnected
Receiver Serial Clock_1—SCKR_1 provides the receiver
serial bit clock for the ESAI_1. The SCKR_1 operates as a clock
input or output used by all the enabled receivers in the
asynchronous mode (SYN=0), or as serial flag 0 pin in the
synchronous mode (SYN=1).
When this pin is configured as serial flag pin, its direction is
determined by the RCKD bit in the RCCR_1 register. When
configured as the output flag OF0, this pin will reflect the value
of the OF0 bit in the SAICR_1 register, and the data in the OF0
bit will show up at the pin synchronized to the frame sync in
normal mode or the slot in network mode. When configured as
the input flag IF0, the data value at the pin will be stored in the
IF0 bit in the SAISR_1 register, synchronized by the frame sync
in normal mode or the slot in network mode.
PE0
Input, output, or
disconnected
Port E0—When the ESAI_1 is configured as GPIO, this signal
is individually programmable as input, output, or internally
disconnected.
The default state after reset is GPIO disconnected.
Internal Pull down resistor.
This input is 5 V tolerant.
SCKT_1
Input or output
PE3
Input, output, or
disconnected
GPIO
disconnected
Transmitter Serial Clock_1—This signal provides the serial bit
rate clock for the ESAI_1. SCKT_1 is a clock input or output
used by all enabled transmitters and receivers in synchronous
mode, or by all enabled transmitters in asynchronous mode.
Port E3—When the ESAI_1 is configured as GPIO, this signal
is individually programmable as input, output, or internally
disconnected.
The default state after reset is GPIO disconnected.
Internal Pull down resistor.
This input is 5 V tolerant.
SDO5_1
Output
GPIO
disconnected
Serial Data Output 5_1—When programmed as a transmitter,
SDO5_1 is used to transmit data from the TX5 serial transmit
shift register.
SDI0_1
Input
Serial Data Input 0_1—When programmed as a receiver,
SDI0_1 is used to receive serial data into the RX0 serial receive
shift register.
PE6
Input, output, or
disconnected
Port E6—When the ESAI_1 is configured as GPIO, this signal
is individually programmable as input, output, or internally
disconnected.
The default state after reset is GPIO disconnected.
Internal Pull down resistor.
This input is 5 V tolerant.
24
DSP56371 Technical Data
Freescale Semiconductor
Signal/Connection Descriptions
Table 9. Enhanced Serial Audio Interface_1 Signals
Signal Name
Signal Type
State during
Reset
Signal Description
SDO4_1
Output
GPIO
disconnected
Serial Data Output 4_1—When programmed as a transmitter,
SDO4_1 is used to transmit data from the TX4 serial transmit
shift register.
SDI1_1
Input
Serial Data Input 1_1—When programmed as a receiver,
SDI1_1 is used to receive serial data into the RX1 serial receive
shift register.
PE7
Input, output, or
disconnected
Port E7—When the ESAI_1 is configured as GPIO, this signal
is individually programmable as input, output, or internally
disconnected.
The default state after reset is GPIO disconnected.
Internal Pull down resistor.
This input is 5 V tolerant.
SDO3_1
Output
GPIO
disconnected
Serial Data Output 3—When programmed as a transmitter,
SDO3_1 is used to transmit data from the TX3 serial transmit
shift register.
SDI2_1
Input
Serial Data Input 2—When programmed as a receiver, SDI2_1
is used to receive serial data into the RX2 serial receive shift
register.
PE8
Input, output, or
disconnected
Port E8—When the ESAI_1 is configured as GPIO, this signal
is individually programmable as input, output, or internally
disconnected.
The default state after reset is GPIO disconnected.
Internal Pull down resistor.
This input is 5 V tolerant.
SDO2_1
Output
GPIO
disconnected
Serial Data Output 2—When programmed as a transmitter,
SDO2_1 is used to transmit data from the TX2 serial transmit
shift register.
SDI3_1
Input
Serial Data Input 3—When programmed as a receiver, SDI3_1
is used to receive serial data into the RX3 serial receive shift
register.
PE9
Input, output, or
disconnected
Port E9—When the ESAI_1 is configured as GPIO, this signal
is individually programmable as input, output, or internally
disconnected.
The default state after reset is GPIO disconnected.
Internal Pull down resistor.
This input is 5 V tolerant.
Freescale Semiconductor
DSP56371 Technical Data
25
Signal/Connection Descriptions
Table 9. Enhanced Serial Audio Interface_1 Signals
Signal Name
Signal Type
State during
Reset
SDO1_1
Output
GPIO
disconnected
PE10
Input, output, or
disconnected
Signal Description
Serial Data Output 1—SDO1_1 is used to transmit data from
the TX1 serial transmit shift register.
Port E10—When the ESAI_1 is configured as GPIO, this signal
is individually programmable as input, output, or internally
disconnected.
The default state after reset is GPIO disconnected.
Internal Pull down resistor.
This input is 5 V tolerant.
SDO0_1
Output
GPIO
disconnected
PE11
Input, output, or
disconnected
Serial Data Output 0—SDO0_1 is used to transmit data from
the TX0 serial transmit shift register.
Port E11—When the ESAI_1 is configured as GPIO, this signal
is individually programmable as input, output, or internally
disconnected.
The default state after reset is GPIO disconnected.
Internal Pull down resistor.
This input is 5 V tolerant.
3.10
SPDIF Transmitter Digital Audio Interface
Table 10. Digital Audio Interface (DAX) Signals
Signal
Name
Type
State During
Reset
Signal Description
ACI
Input
GPIO
Disconnected
Audio Clock Input—This is the DAX clock input. When
programmed to use an external clock, this input supplies the DAX
clock. The external clock frequency must be 256, 384, or 512
times the audio sampling frequency (256 × Fs, 384 × Fs or 512 ×
Fs, respectively).
PD0
Input,
output, or
disconnected
Port D0—When the DAX is configured as GPIO, this signal is
individually programmable as input, output, or internally
disconnected.
The default state after reset is GPIO disconnected.
Internal Pull down resistor.
This input is 5 V tolerant.
26
DSP56371 Technical Data
Freescale Semiconductor
Signal/Connection Descriptions
Table 10. Digital Audio Interface (DAX) Signals (Continued)
Signal
Name
Type
State During
Reset
Signal Description
ADO
Output
GPIO
Disconnected
Digital Audio Data Output—This signal is an audio and nonaudio output in the form of AES/SPDIF, CP340 and IEC958 data
in a biphase mark format.
PD1
Input,
output, or
disconnected
Port D1—When the DAX is configured as GPIO, this signal is
individually programmable as input, output, or internally
disconnected.
The default state after reset is GPIO disconnected.
Internal Pull down resistor.
This input is 5 V tolerant.
3.11
Dedicated GPIO Interface
Table 11. Dedicated GPIO Signals
Signal
Name
Type
State During
Reset
Signal Description
PF0
Input,
GPIO
disconnected
Port F0—this signal is individually programmable as input, output,
or internally disconnected. The default state after reset is GPIO
disconnected.
output, or
disconnected
Internal Pull down resistor.
This input is 5 V tolerant.
PF1
Input,
output, or
disconnected
GPIO
disconnected
Port F1— this signal is individually programmable as input,
output, or internally disconnected. The default state after reset is
GPIO disconnected.
Internal Pull down resistor.
This input is 5 V tolerant.
PF2
Input,
output, or
disconnected
GPIO
disconnected
Port F2— this signal is individually programmable as input,
output, or internally disconnected. The default state after reset is
GPIO disconnected.
Internal Pull down resistor.
This input is 5 V tolerant.
PF3
Input,
output, or
disconnected
GPIO
disconnected
Port F3—this signal is individually programmable as input, output,
or internally disconnected. The default state after reset is GPIO
disconnected.
Internal Pull down resistor.
This input is 5 V tolerant.
Freescale Semiconductor
DSP56371 Technical Data
27
Signal/Connection Descriptions
Table 11. Dedicated GPIO Signals (Continued)
Signal
Name
PF4
Type
State During
Reset
Signal Description
Input,
GPIO
disconnected
Port F4— this signal is individually programmable as input,
output, or internally disconnected. The default state after reset is
GPIO disconnected.
output, or
disconnected
Internal Pull down resistor.
This input is 5 V tolerant.
PF5
Input,
output, or
disconnected
GPIO
disconnected
Port F5—this signal is individually programmable as input, output,
or internally disconnected. The default state after reset is GPIO
disconnected.
Internal Pull down resistor.
This input is 5 V tolerant.
PF6
Input,
output, or
disconnected
GPIO
disconnected
Port F6—this signal is individually programmable as input, output,
or internally disconnected. The default state after reset is GPIO
disconnected.
Internal Pull down resistor.
This input is 5 V tolerant.
PF7
Input,
output, or
disconnected
GPIO
disconnected
Port F7— this signal is individually programmable as input,
output, or internally disconnected. The default state after reset is
GPIO disconnected.
Internal Pull down resistor.
This input is 5 V tolerant.
PF8
Input,
output, or
disconnected
GPIO
disconnected
Port F8— this signal is individually programmable as input,
output, or internally disconnected. The default state after reset is
GPIO disconnected.
Internal Pull down resistor.
This input is 5 V tolerant.
PF9
Input,
output, or
disconnected
GPIO
disconnected
Port F9— this signal is individually programmable as input,
output, or internally disconnected. The default state after reset is
GPIO disconnected.
Internal Pull down resistor.
This input is 5 V tolerant.
PF10
Input,
output, or
disconnected
GPIO
disconnected
Port F10— this signal is individually programmable as input,
output, or internally disconnected. The default state after reset is
GPIO disconnected.
Internal Pull down resistor.
This input is 5 V tolerant.
28
DSP56371 Technical Data
Freescale Semiconductor
Signal/Connection Descriptions
3.12
Timer
Table 12. Timer Signal
Signal
Name
Type
TIO0
Input or
Output
State
during
Reset
Signal Description
GPIO Input Timer 0 Schmitt-Trigger Input/Output—When timer 0 functions as an
external event counter or in measurement mode, TIO0 is used as input.
When timer 0 functions in watchdog, timer, or pulse modulation mode,
TIO0 is used as output.
The default mode after reset is GPIO input. This can be changed to
output or configured as a timer input/output through the timer 0
control/status register (TCSR0). If TIO0 is not being used, it is
recommended to either define it as GPIO output immediately at the
beginning of operation or leave it defined as GPIO input but connected
to VDD through a pull-up resistor in order to ensure a stable logic level
at this input.
Internal Pull down resistor.
This input is 5 V tolerant.
TIO1
Input or
Output
GPIO Input Timer 1 Schmitt-Trigger Input/Output—When timer 1 functions as an
external event counter or in measurement mode, TIO1 is used as input.
When timer 1 functions in watchdog, timer, or pulse modulation mode,
TIO1 is used as output.
The default mode after reset is GPIO input. This can be changed to
output or configured as a timer input/output through the timer 1
control/status register (TCSR1). If TIO1 is not being used, it is
recommended to either define it as GPIO output immediately at the
beginning of operation or leave it defined as GPIO input but connected
to Vdd through a pull-up resistor in order to ensure a stable logic level
at this input.
Internal Pull down resistor.
This input is 5 V tolerant.
3.13
JTAG/OnCE Interface
Table 13. JTAG/OnCE Interface
Signal
Name
Signal
Type
State
during
Reset
TCK
Input
Input
Signal Description
Test Clock—TCK is a test clock input signal used to synchronize the JTAG
test logic. It has an internal pull-up resistor.
Internal Pull up resistor.
This input is 5 V tolerant..
Freescale Semiconductor
DSP56371 Technical Data
29
Maximum Ratings
Table 13. JTAG/OnCE Interface (Continued)
Signal
Name
Signal
Type
State
during
Reset
TDI
Input
Input
Signal Description
Test Data Input—TDI is a test data serial input signal used for test
instructions and data. TDI is sampled on the rising edge of TCK and has an
internal pull-up resistor.
Internal Pull up resistor.
This input is 5 V tolerant.
TDO
Output
Tri-state
TMS
Input
Input
Test Data Output—TDO is a test data serial output signal used for test
instructions and data. TDO is tri-statable and is actively driven in the shift-IR
and shift-DR controller states. TDO changes on the falling edge of TCK.
Test Mode Select—TMS is an input signal used to sequence the test
controller’s state machine. TMS is sampled on the rising edge of TCK and
has an internal pull-up resistor.
Internal Pull up resistor.
This input is 5 V tolerant.
4
Maximum Ratings
CAUTION
This device contains circuitry protecting against damage due to
high static voltage or electrical fields. However, normal
precautions should be taken to avoid exceeding maximum
voltage ratings. Reliability of operation is enhanced if unused
inputs are pulled to an appropriate logic voltage level (e.g.,
either GND or VDD). The suggested value for a pullup or
pulldown resistor is 10 kΩ.
NOTE
In the calculation of timing requirements, adding a maximum value of one specification to a
minimum value of another specification does not yield a reasonable sum. A maximum
specification is calculated using a worst case variation of process parameter values in one
direction. The minimum specification is calculated using the worst case for the same
parameters in the opposite direction. Therefore, a “maximum” value for a specification will
never occur in the same device that has a “minimum” value for another specification; adding
a maximum to a minimum represents a condition that can never exist.
Table 14. Maximum Ratings
Rating1
Supply Voltage
Symbol
VCORE_VDD,
VPLLD_VDD
VPLLP_VDD,
VIO_VDD,
VPLLA_VDD,
30
DSP56371 Technical Data
Value1, 2
Unit
−0.3 to + 1.6
V
−0.3 to + 4.0
V
Freescale Semiconductor
Maximum Ratings
Table 14. Maximum Ratings (Continued)
Rating1
Symbol
Value1, 2
Unit
VIN
GND − 0.3 to 5.5V
V
I
12
mA
SCK_SCL
ISCK
16
mA
ACI_PD0,ADO_PD1
IDAX
24
mA
TDO
Ijtag
24
mA
TJ
-40 to +115
TSTG
−55 to +125
°C
°C
All “5.0V tolerant” input voltages
Current drain per pin excluding VDD and GND
(Except for pads listed below)
Operating temperature range3
Storage temperature
Notes:
1. GND = 0 V; TJ = –40°C to 115°C for 150 MHz; TJ = 0°C to 100°C for 181 MHz; CL = 50PF
2. Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress
beyond the maximum rating may affect device reliability or cause permanent damage to the device.
3. Operating temperature qualified for automotive applications.
Freescale Semiconductor
DSP56371 Technical Data
31
Power Requirements
5
Power Requirements
To prevent high current conditions due to possible improper sequencing of the power supplies, the connection shown below is
recommended to be made between the DSP56371 IO_VDD and CORE_VDD power pins.
IO VDD
CORE VDD
External
Schottky
Diode
To prevent a high current condition upon power up, the IOVDD must be applied ahead of the CORE VDD as shown below if the
external Schottcky is not used.
CORE VDD
IO VDD
6
Thermal Characteristics
Table 15. Thermal Characteristics
Characteristic
Symbol
TQFP Value
Unit
Natural Convection, Junction-to-ambient thermal
resistance1,2
RθJA or θJA
39
°C/W
Junction-to-case thermal resistance3
RθJC or θJC
18.25
°C/W
Notes:
32
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board
thermal resistance.
2. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.
3. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC883 Method 1012.1).
DSP56371 Technical Data
Freescale Semiconductor
DC Electrical Characteristics
7
DC Electrical Characteristics
Table 16. DC ELECTRICAL CHARACTERISTICS4
Characteristics
Supply voltages
Symbol
Min
Typ
Max
1
Unit
VDD
1.2
1.25
1.3
V
VDDIO
3.14
3.3
3.461
V
• Core (core_vdd)
• PLL (plld_vdd)
Supply voltages
• Vio_vdd
• PLL (pllp_vdd)
• PLL (plla_vdd)
Input high voltage
• All pins
V
VIH
2.0
—
VIO_VDD+2V
Note: All 3.3 volt supplies must rise prior to the rise of the 1.25 volt supplies to avoid a high current condition and possible system
damage.
Input low voltage
• All pins
VIL
–0.3
—
0.8
V
Input leakage current (All pins)
IIN
—
—
84
µA
Clock pin Input Capacitance (EXTAL)
CIN
High impedance (off-state) input current
(@ 3.46 V)
ITSI
–84
—
84
µA
Output high voltage
VOH
2.4
—
—
V
VOL
—
—
0.4
V
• In Normal mode
ICCI
—
99
200
mA
• In Wait mode
ICCW
—
48
150
mA
• In Stop mode3
ICCS
—
2.5
82
mA
—
115
150
mA
—
—
10
pF
3.749
pF
IOH = -5 mA
Output low voltage
IOL = 5 mA
Internal supply current1 at internal clock of
181MHz
IO supply current
Input capacitance4
Notes:
CIN
1. The Section 3, Power Consumption Considerations section provides a formula to compute the estimated current
requirements in Normal mode. In order to obtain these results, all inputs must be terminated (i.e., not allowed to float).
Measurements are based on synthetic intensive DSP benchmarks. The power consumption numbers in this
specification are 90% of the measured results of this benchmark. This reflects typical DSP applications. Typical internal
supply current is measured with VCORE_VDD = 1.25V, VDD_IO = 3.3V at TJ = 25°C. Maximum internal supply current is
measured with VCORE_VDD = 1.30V, VIO_VDD) = 3.46V at TJ = 115°C.
2. In order to obtain these results, all inputs, which are not disconnected at Stop mode, must be terminated (i.e., not
allowed to float).
3. Periodically sampled and not 100% tested
4. TJ = –40°C to 115°C for 150 MHz; TJ = 0°C to 100°C for 181 MHz; CL=50pF
Freescale Semiconductor
DSP56371 Technical Data
33
AC Electrical Characteristics
8
AC Electrical Characteristics
The timing waveforms shown in the AC electrical characteristics section are tested with a VIL maximum of 0.8V and a VIH
minimum of 2.0V for all pins. AC timing specifications, which are referenced to a device input signal, are measured in production
with respect to the 50% point of the respective input signal’s transition. DSP56371 output levels are measured with the production
test machine VOL and VOH reference levels set at 1.0V and 1.8V, respectively.
NOTE
Although the minimum value for the frequency of EXTAL is 0 MHz (PLL bypassed), the
device AC test conditions are 5 MHz and rated speed.
9
Internal Clocks
Table 17. INTERNAL CLOCKS
No.
Symbol
Min
Typ
Max
UNIT
Condition
5
--
20
MHZ
Fref = FN/NR
1
Comparison Frequency
Fref1
2
Input Clock Frequency
FIN
3
Output clock Frequency (with
PLL enabled2,3
FOUT
75
(1000/Etc × MF x
FM)/
(PDF × DF x OD)
--
MHZ
FOUT=FVCO/NO
where NO is output
divider value
4
Output clock Frequency (with
PLL disabled2,3
FOUT
--
1000/Etc
--
MHZ
---
5
Duty Cycle
--
40
50
60
%
FVCO=300MHZ~60
0MHZ
Notes:
34
Characteristics
Fref*NR
NR is input divider
value
1. See users manual for definition.
2. DF = Division Factor
Ef = External frequency
MF = Multiplication Factor
PDF = Predivision Factor
FM= Feedback Multiplier
OD = Output Divider
3. Maximum frequency will vary depending on the ordered part number.
DSP56371 Technical Data
Freescale Semiconductor
External Clock Operation
10
External Clock Operation
The DSP56371 system clock is an externally supplied square wave voltage source connected to EXTAL (see Figure 4).
.
VIH
Midpoint
EXTAL
ETH
VIL
ETL
6
7
8
Note:
ETC
The midpoint is 0.5 (VIH + VIL).
Figure 4. External Clock Timing
Table 18. Clock Operation 150 and 181 MHz Values
150 MHz
No.
6
Characteristics
EXTAL input high
1,2
181 MHz
Symbol
Min
Max
Min
Max
Eth
3.33ns
100ns
2.75ns
100ns
Etl
3.33ns
100ns
2.75ns
100ns
6.66ns
inf
5.52ns
inf
6.66ns
200ns
5.52ns
200ns
6.66ns
inf
5.52ns
inf
6.66ns
13.0ns
5.52ns
13.0ns
(40% to 60% duty cycle)
7
EXTAL input low1,2
(40% to 60% duty cycle)
8
EXTAL cycle time2
Etc
• With PLL disabled
• With PLL enabled
9
Instruction cycle time= ICYC = TC3
Icyc
• With PLL disabled
• With PLL enabled
Notes:
1.
2.
3.
4.
Measured at 50% of the input transition
The maximum value for PLL enabled is given for minimum VCO and maximum MF.
The maximum value for PLL enabled is given for minimum VCO and maximum DF.
The indicated duty cycle is for the specified maximum frequency for which a part is rated. The minimum clock high or low
time required for correct operation, however, remains the same at lower operating frequencies; therefore, when a lower
clock frequency is used, the signal symmetry may vary from the specified duty cycle as long as the minimum high time
and low time requirements are met.
Freescale Semiconductor
DSP56371 Technical Data
35
Reset, Stop, Mode Select, and Interrupt Timing
11
Reset, Stop, Mode Select, and Interrupt Timing
Table 19. Reset, Stop, Mode Select, and Interrupt Timing
No.
Characteristics
Expression
Min
Max
Unit
10
Delay from RESET assertion to all output pins at
reset value3
—
—
11
ns
11
Required RESET duration4
• Power on, external clock generator, PLL
disabled
2 x TC
11.1
—
ns
• Power on, external clock generator, PLL
enabled
2 x TC
11.1
--
ns
TC
—
5.5
ns
2× TC
11.1
—
(2xTC)+TLOCK
5.0
12
Syn reset setup time from RESET
• Maximum
13
Syn reset de assert delay time
• Minimum
• Maximum(PLL enabled)
14
Mode select setup time
10.0
—
ns
15
Mode select hold time
10.0
—
ns
16
Minimum edge-triggered interrupt request
assertion width
2 xTC
11.1
—
ns
17
Minimum edge-triggered interrupt request
deassertion width
2 xTC
11.1
—
ns
18
Delay from interrupt trigger to interrupt code
execution.
10 xTC + 5
60.0
19
Duration of level sensitive IRQA assertion to
ensure interrupt service (when exiting Stop)2, 3
9+(128K× TC)
704
—
us
• PLL is active during Stop and Stop delay is
not enabled
(OMR Bit 6 = 1)
25× TC
138
—
ns
• PLL is not active during Stop and Stop delay
is enabled (OMR Bit 6 = 0)
9+(128KxTC)+Tlock
5.7
ms
• PLL is not active during Stop and Stop delay
is not enabled (OMR Bit 6 = 1)
(25 x TC)+Tlock
5
ms
• Delay from IRQA, IRQB, IRQC, IRQD, NMI
assertion to general-purpose transfer
output valid caused by first interrupt
instruction execution
10 x TC + 3.0
• PLL is active during Stop and Stop delay is
enabled
(OMR Bit 6 = 0)
20
36
ns
ms
DSP56371 Technical Data
ns
59.0
ns
Freescale Semiconductor
Reset, Stop, Mode Select, and Interrupt Timing
Table 19. Reset, Stop, Mode Select, and Interrupt Timing (Continued)
No.
21
22
Notes:
Characteristics
Expression
Min
Max
Unit
• ESAI, ESAI_1, SHI, DAX, Timer
12 x TC
—
—
ns
• DMA
8 x TC
—
—
ns
• IRQ, NMI (edge trigger)
8 x TC
—
—
ns
• IRQ (level trigger)
12 c TC
—
—
ns
• Data read from ESAI, ESAI_1, SHI, DAX
6 x TC
—
—
ns
• Data write to ESAI, ESAI_1, SHI, DAX
7 x TC
—
—
ns
• Timer
2 x TC
—
—
ns
• IRQ, NMI (edge trigger)
3 x TC
—
—
ns
Interrupt Requests Rate
DMA Requests Rate
1. When using fast interrupts and IRQA, IRQB, IRQC, and IRQD are defined as level-sensitive, timings 19 through 21 apply
to prevent multiple interrupt service. To avoid these timing restrictions, the deasserted Edge-triggered mode is
recommended when using fast interrupts. Long interrupts are recommended when using Level-sensitive mode.
2. For PLL disable, using external clock (PCTL Bit 13 = 0), no stabilization delay is required and recovery time will be
defined by the OMR Bit 6 settings.
For PLL enable, (if bit 12 of the PCTL register is 0), the PLL is shutdown during Stop. Recovering from Stop requires the
PLL to get locked. The PLL lock procedure duration, PLL Lock Cycles (PLC), may be in the range of 0.5 ms.
3. Periodically sampled and not 100% tested
4. RESET duration is measured during the time in which RESET is asserted, VDD is valid, and the EXTAL input is active
and valid. When the VDD is valid, but the other “required RESET duration” conditions (as specified above) have not been
yet met, the device circuitry will be in an uninitialized state that can result in significant power consumption and heat-up.
Designs should minimize this state to the shortest possible duration.
VIH
RESET
11
13
10
All Pins
Reset Value
Figure 5. Reset Timing
Freescale Semiconductor
DSP56371 Technical Data
37
Reset, Stop, Mode Select, and Interrupt Timing
VIH
RESET
14
15
MODA, MODB,
MODC, MODD,
PINIT
VIH
VIH
VIL
VIL
IRQA, IRQB,
IRQD, NMI
Figure 6. Recovery from Stop State Using IRQA Interrupt Service
IRQA, IRQB,
IRQC, IRQD,
NMI
16
IRQA, IRQB,
IRQC, IRQD,
NMI
17
Figure 7. External Interrupt Timing (Negative Edge-Triggered)
IRQA, IRQB,
IRQC, IRQD,
NMI
19
18
a) First Interrupt Instruction Execution
General
Purpose
I/O
20
IRQA, IRQB,
IRQC, IRQD,
NMI
b) General Purpose I/O
Figure 8. External Fast Interrupt Timing
38
DSP56371 Technical Data
Freescale Semiconductor
Serial Host Interface SPI Protocol Timing
12
Serial Host Interface SPI Protocol Timing
Table 20. Serial Host Interface SPI Protocol Timing
Characteristics1
No.
Mode
Min
Max
Unit
23
Minimum serial clock cycle = tSPICC(min)
Master
79.0
—
ns
24
Serial clock high period
Master
29.5
—
ns
Slave
25.8
—
ns
Master
29.5
—
ns
Slave
25.8
—
ns
Master
—
10
ns
Slave
—
10
ns
CPHA = 0
Slave
34.4
—
ns
CPHA = 1
Slave
10
—
ns
28
Last SCK edge to SS not asserted
Slave
12
—
ns
29
Data input valid to SCK edge (data input set-up time)
Master/Slave
0
—
ns
30
SCK last sampling edge to data input not valid
Master/Slave
22.4
—
ns
31
SS assertion to data out active
Slave
5
—
ns
Slave
—
9
ns
25
26
27
Serial clock low period
Serial clock rise/fall time
SS assertion to first SCK edge
impedance2
32
SS deassertion to data high
33
SCK edge to data out valid
(data out delay time)
Master/Slave
—
100
ns
34
SCK edge to data out not valid
(data out hold time)
Master/Slave
21.4
—
ns
35
SS assertion to data out valid
(CPHA = 0)
Slave
—
15.0
ns
36
First SCK sampling edge to HREQ output deassertion
Slave
50
—
ns
37
Last SCK sampling edge to HREQ output not deasserted
(CPHA = 1)
Slave
52.2
—
ns
38
SS deassertion to HREQ output not deasserted (CPHA = 0)
Slave
46.6
—
ns
39
SS deassertion pulse width (CPHA = 0)
Slave
12.7
—
ns
40
HREQ in assertion to first SCK edge
Master
—
—
ns
41
HREQ in deassertion to last SCK sampling edge (HREQ in
set-up time) (CPHA = 1)
Master
0
—
ns
First SCK edge to HREQ in not asserted
Master
0
—
ns
42
(HREQ in hold time)
43
Notes:
HREQ assertion width
Master
ns
1. VCORE_VDD = 1.2 5 ± 0.05 V; TJ = –40°C to 115°C for 150 MHz; TJ = 0°C to 100°C for 181 MHz; CL = 50 pF
2. Periodically sampled, not 100% tested
Freescale Semiconductor
DSP56371 Technical Data
39
Serial Host Interface SPI Protocol Timing
SS
(Input)
25
23
24
26
26
SCK (CPOL = 0)
(Output)
24
23
26
25
26
SCK (CPOL = 1)
(Output)
29
30
MISO
(Input)
MSB
Valid
LSB
Valid
34
33
MOSI
(Output)
MSB
40
30
29
LSB
42
HREQ
(Input)
71
Figure 9. SPI Master Timing (CPHA = 0)
40
DSP56371 Technical Data
Freescale Semiconductor
Serial Host Interface SPI Protocol Timing
SS
(Input)
25
23
24
26
26
SCK (CPOL = 0)
(Output)
24
23
26
25
SCK (CPOL = 1)
(Output)
26
29
29
30
MISO
(Input)
30
MSB
Valid
LSB
Valid
33
MOSI
(Output)
34
MSB
LSB
40
41
42
HREQ
(Input)
2
Figure 10. SPI Master Timing (CPHA = 1)
Freescale Semiconductor
DSP56371 Technical Data
41
Serial Host Interface SPI Protocol Timing
SS
(Input)
25
23
24
26
28
26
39
SCK (CPOL = 0)
(Input)
27
24
23
26
25
26
SCK (CPOL = 1)
(Input)
35
33
34
31
MISO
(Output)
34
32
MSB
LSB
29
29
30
MOSI
(Input)
MSB
Valid
30
LSB
Valid
36
38
HREQ
(Output)
73
Figure 11. SPI Slave Timing (CPHA = 0)
42
DSP56371 Technical Data
Freescale Semiconductor
Serial Host Interface SPI Protocol Timing
SS
(Input)
25
23
24
26
28
26
SCK (CPOL = 0)
(Input)
27
24
26
25
27
SCK (CPOL = 1)
(Input)
33
33
34
31
MISO
(Output)
32
MSB
LSB
29
29
30
MOSI
(Input)
MSB
Valid
30
LSB
Valid
36
37
HREQ
(Output)
74
Figure 12. SPI Slave Timing (CPHA = 1)
Freescale Semiconductor
DSP56371 Technical Data
43
Serial Host Interface (SHI) I2C Protocol Timing
Serial Host Interface (SHI) I2C Protocol Timing
13
Table 21. SHI I2C Protocol Timing
Standard I2C*
Characteristics1
No.
Standard
Fast-Mode
Symbol/
Expression
Min
Max
Min
Max
Unit
44
SCL clock frequency
FSCL
—
100
—
400
kHz
44
SCL clock cycle
TSCL
10
—
2.5
—
µs
45
Bus free time
TBUF
4.7
—
1.3
—
µs
46
Start condition set-up time
TSUSTA
4.7
—
0.6
—
µs
47
Start condition hold time
THD;STA
4.0
—
0.6
—
µs
48
SCL low period
TLOW
4.7
—
1.3
—
µs
49
SCL high period
THIGH
4.0
—
1.3
—
µs
50
SCL and SDA rise time
TR
—
5
—
5
ns
51
SCL and SDA fall time
TF
—
5
—
5
ns
52
Data set-up time
TSU;DAT
250
—
100
—
ns
53
Data hold time
THD;DAT
0.0
—
0.0
0.9
µs
54
DSP clock frequency
FOSC
10.6
—
28.5
—
MHz
55
SCL low to data out valid
TVD;DAT
—
3.4
—
0.9
µs
56
Stop condition setup time
TSU;STO
4.0
—
0.6
—
µs
57
HREQ in deassertion to last SCL edge (HREQ
in set-up time)
tSU;RQI
0.0
—
0.0
—
ns
58
First SCL sampling edge to HREQ output
deassertion
—
—
—
—
ns
50
—
50
—
ns
0.5 × TI2CCP
4327
—
927
—
ns
tHO;RQI
0.0
—
0.0
—
ns
TNG;RQO
4 × TC + 30
59
Last SCL edge to HREQ output not deasserted
TAS;RQO
2 × TC + 30
60
HREQ in assertion to first SCL edge
TAS;RQI
-0.5 × TC - 21
61
Note:
44
First SCL edge to HREQ in not asserted
(HREQ in hold time.)
1. VCORE_VDD = 1.2 5 ± 0.05 V; TJ = –40°C to 115°C for 150 MHz; TJ = 0°C to 100°C for 181 MHz; CL = 50 pF
DSP56371 Technical Data
Freescale Semiconductor
Serial Host Interface (SHI) I2C Protocol Timing
13.1
Programming the Serial Clock
The programmed serial clock cycle, T I2CCP , is specified by the value of the HDM[7:0] and HRS bits of the HCKR (SHI clock control
register).
The expression for T I2CCP is
T I2CCP = [TC × 2 × (HDM[7:0] + 1) × (7 × (1 – HRS) + 1)]
where
—
HRS is the pre-scaler rate select bit. When HRS is cleared, the fixed
divide-by-eight pre-scaler is operational. When HRS is set, the pre-scaler is bypassed.
— HDM[7:0] are the divider modulus select bits. A divide ratio from 1 to 256 (HDM[7:0] = $00 to $FF) may be selected.
In I2C mode, the user may select a value for the programmed serial clock cycle from
6 × TC
(if HDM[7:0] = $02 and HRS = 1)
4096 × TC
(if HDM[7:0] = $FF and HRS = 0)
to
The programmed serial clock cycle (TI2CCP ), SCL rise time (TR), should be chosen in order to achieve the desired SCL serial
clock cycle (TSCL), as shown in Table 22.
44
46
49
48
SCL
50
SDA
53
51
45
52
Stop
Start
MSB
47
60
LSB
58
61
55
ACK
Stop
56
57
59
HREQ
Figure 13. I2C Timing
Freescale Semiconductor
DSP56371 Technical Data
45
Enhanced Serial Audio Interface Timing
14
Enhanced Serial Audio Interface Timing
Table 22. Enhanced Serial Audio Interface Timing
Characteristics1, 2, 3
No.
62
63
5
Clock cycle
Symbol
Expression3
Min
Max
Condition4
Unit
tSSICC
4 × Tc
22.3
—
i ck
ns
4 × Tc
22.3
—
x ck
SCKT:max[(3*TC) or t87]
26.5
—
x ck
2 × Tc − 10.0
3.4
—
2 × Tc
10.0
—
2 × Tc − 10.0
3.4
—
2 × Tc
10.0
—
Clock high period
• For internal clock
—
• For external clock
64
Clock low period
• For internal clock
—
• For external clock
65
66
67
68
69
70
71
72
73
74
75
76
77
46
ns
SCKR rising edge to FSR out (bl) high
—
SCKR rising edge to FSR out (bl) low
—
SCKR rising edge to FSR out (wr) high6
—
SCKR rising edge to FSR out (wr) low6
—
SCKR rising edge to FSR out (wl) high
—
SCKR rising edge to FSR out (wl) low
—
Data in setup time before SCKR (SCK in
synchronous mode) falling edge
—
Data in hold time after SCKR falling edge
—
FSR input (bl, wr) high before SCKR falling
edge 6
—
FSR input (wl) high before SCKR falling edge
—
FSR input hold time after SCKR falling edge
Flags input setup before SCKR falling edge
Flags input hold time after SCKR falling edge
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DSP56371 Technical Data
ns
—
37.0
x ck
—
22.0
i ck a
—
37.0
x ck
—
22.0
i ck a
—
39.0
x ck
—
24.0
i ck a
—
39.0
x ck
—
24.0
i ck a
—
36.0
x ck
—
21.0
i ck a
—
37.0
x ck
—
22.0
i ck a
0.0
—
x ck
19.0
—
i ck
5.0
—
x ck
3.0
—
i ck
1.0
—
x ck
23.0
—
i ck a
1.0
—
x ck
23.0
—
i ck a
3.0
—
x ck
0.0
—
i ck a
0.0
—
x ck
19.0
—
i ck s
6.0
—
x ck
0.0
—
i ck s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Freescale Semiconductor
Enhanced Serial Audio Interface Timing
Table 22. Enhanced Serial Audio Interface Timing (Continued)
No.
78
79
80
82
83
84
85
86
87
88
Characteristics1, 2, 3
SCKT rising edge to FST out (bl) high
SCKT rising edge to FST out (bl) low
SCKT rising edge to FST out (wr)
Expression3
Min
Max
Condition4
Unit
—
—
—
29.0
x ck
ns
—
15.0
i ck
—
31.0
x ck
—
17.0
i ck
—
31.0
x ck
—
17.0
i ck
—
33.0
x ck
—
19.0
i ck
—
30.0
x ck
—
16.0
i ck
—
31.0
x ck
—
17.0
i ck
—
31.0
x ck
—
17.0
i ck
—
34.0
x ck
—
20.0
i ck
—
26.5
x ck
—
21.0
i ck
—
31.0
x ck
—
16.0
i ck
—
34.0
x ck
—
20.0
i ck
2.0
—
x ck
21.0
—
i ck
—
high6
SCKT rising edge to FST out (wr) low
Symbol
—
6
—
SCKT rising edge to FST out (wl) high
—
SCKT rising edge to FST out (wl) low
—
SCKT rising edge to data out enable from
high impedance
—
SCKT rising edge to transmitter #0 drive
enable assertion
—
SCKT rising edge to data out valid
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
SCKT rising edge to data out high
impedance7
—
SCKT rising edge to transmitter #0 drive
enable deassertion7
—
FST input (bl, wr) setup time before SCKT
falling edge6
—
91
FST input (wl) to data out enable from high
impedance
—
—
—
27.0
—
ns
92
FST input (wl) to transmitter #0 drive enable
assertion
—
—
—
31.0
—
ns
93
FST input (wl) setup time before SCKT falling
edge
—
—
ns
FST input hold time after SCKT falling edge
—
89
90
94
95
Flag output valid after SCKT rising edge
—
—
—
—
—
—
2.0
—
x ck
21.0
—
i ck
4.0
—
x ck
0.0
—
i ck
—
32.0
x ck
—
18.0
i ck
ns
ns
ns
ns
ns
96
HCKR/HCKT clock cycle
—
2 x TC
40.0
—
ns
97
HCKT input rising edge to SCKT output
—
—
—
18.0
ns
98
HCKR input rising edge to SCKR output
—
—
—
18.0
ns
Freescale Semiconductor
DSP56371 Technical Data
47
Enhanced Serial Audio Interface Timing
Table 22. Enhanced Serial Audio Interface Timing (Continued)
No.
Notes:
48
Characteristics1, 2, 3
Symbol
Expression3
Min
Max
Condition4
Unit
1. VCORE_VDD = 1.25 ± 0.05 V; TJ = –40°C to 115°C for 150 MHz; TJ = 0°C to 100°C for 181 MHz; CL = 50 pF
2. i ck = internal clock
x ck = external clock
i ck a = internal clock, asynchronous mode
(asynchronous implies that SCKT and SCKR are two different clocks)
i ck s = internal clock, synchronous mode
(synchronous implies that SCKT and SCKR are the same clock)
3. bl = bit length
wl = word length
wr = word length relative
4. SCKT(SCKT pin) = transmit clock
SCKR(SCKR pin) = receive clock
FST(FST pin) = transmit frame sync
FSR(FSR pin) = receive frame sync
HCKT(HCKT pin) = transmit high frequency clock
HCKR(HCKR pin) = receive high frequency clock
5. For the internal clock, the external clock cycle is defined by Icyc and the ESAI control register.
6. The word-relative frame sync signal waveform relative to the clock operates in the same manner as the bit-length frame sync signal
waveform, but spreads from one serial clock before first bit clock (same as bit length frame sync signal), until the one before last bit
clock of the first word in frame.
7. Periodically sampled and not 100% tested
8. ESAI_1 specs match those of ESAI_0
DSP56371 Technical Data
Freescale Semiconductor
Enhanced Serial Audio Interface Timing
62
SCKT
(Input/Output
)
63
64
78
FST (Bit)
Out
79
83
FST (Word)
Out
84
87
87
85
88
First Bit
Data Out
Transmitter
#0 Drive
Enable
Last Bit
92
90
86
89
94
FST (Bit) In
91
94
93
FST (Word)
In
95
See Note
Flags Out
Note:
In network mode, output flag transitions can occur at the start of each time slot within the frame. In
normal mode, the output flag state is asserted for the entire frame period.
Figure 14. ESAI Transmitter Timing
Freescale Semiconductor
DSP56371 Technical Data
49
Enhanced Serial Audio Interface Timing
62
63
64
SCKR
(Input/Output)
65
66
FSR (Bit)
Out
69
70
FSR (Word)
Out
72
71
Data In
First Bit
Last Bit
75
73
FSR (Bit)
In
74
75
FSR (Word)
In
76
77
Flags In
Figure 15. ESAI Receiver Timing
HCKT
SCKT(output)
96
97
Figure 16. ESAI HCKT Timing
HCKR
SCKR (output)
96
98
Figure 17. ESAI HCKR Timing
50
DSP56371 Technical Data
Freescale Semiconductor
Digital Audio Transmitter Timing
15
Digital Audio Transmitter Timing
Table 23. Digital Audio Transmitter Timing
181 MHz
No.
Characteristic
Expression
Unit
Min
Max
1 / (2 x TC)
—
90
MHz
2 × TC
11.1
—
ns
99
ACI frequency (see note)
100
ACI period
101
ACI high duration
0.5 × TC
2.8
—
ns
102
ACI low duration
0.5 × TC
2.8
—
ns
103
ACI rising edge to ADO valid
1.5 × TC
—
8.3
ns
Note:
1. In order to assure proper operation of the DAX, the ACI frequency should be less than 1/2 of theDSP56371
internal clock frequency. For example, if the DSP56371 is running at 181 MHz internally, the ACI frequency
should be less than 90MHz.
ACI
100
101
102
103
ADO
Figure 18. Digital Audio Transmitter Timing
16
Timer Timing
Table 24. Timer Timing
181 MHz
No.
Characteristics
Expression
Unit
Min
Max
104
TIO Low
2 × TC + 2.0
13
—
ns
105
TIO High
2 × TC + 2.0
13
—
ns
Note:
1. VCORE_VDD = 1.25
V ± 0.05 V; TJ = –40°C to 115°C for 150 MHz; TJ = 0°C to 100°C for 181 MHz; CL = 50 pF
TIO
104
105
Figure 19. TIO Timer Event Input Restrictions
Freescale Semiconductor
DSP56371 Technical Data
51
GPIO Timing
17
GPIO Timing
Table 25. GPIO Timing
Characteristics1
No.
Expression
Min
Max
Unit
106
FOSC edge to GPIO out valid (GPIO out delay time)
—
7
ns
107
FOSC edge to GPIO out not valid (GPIO out hold time)
----
7
ns
108
FOSC In valid to EXTAL edge (GPIO in set-up time)
2
---
ns
109
FOSC edge to GPIO in not valid (GPIO in hold time)
0
---
ns
110
Minimum GPIO pulse high width (except Port F)
2 x TC
11.1
—
ns
111
Minimum GPIO pulse low width (except Port F)
2 x TC
11.1
ns
112
Minimum GPIO pulse low width (Port F)
6 x TC
33.3
ns
113
Minimum GPIO pulse high width (Port F)
6 x TC
33.3
ns
114
GPIO out rise time
—
—
13
ns
115
GPIO out fall time
—
—
13
ns
Note:
1. VCORE_VDD = 1.25 V ± 0.05 V; TJ = –40°C to 115°C for 150 MHz; TJ = 0°C to 100°C for 181 MHz; CL = 50 pF
FOSC
106
107
GPIO
(Output)
108
GPIO
(Input)
109
Valid
GPIO
(Output)
110
111
112
113
Figure 20. GPIO Timing
52
DSP56371 Technical Data
Freescale Semiconductor
JTAG Timing
18
JTAG Timing
Table 26. JTAG Timing
All frequencies
No.
Characteristics
Unit
Min
Max
116
TCK frequency of operation (1/(TC × 6); maximum 22 MHz)
0.0
22.0
MHz
117
TCK cycle time
45.0
—
ns
118
TCK clock pulse width
20.0
—
ns
119
TCK rise and fall times
0.0
10.0
ns
120
TCK low to output data valid
0.0
40.0
ns
121
TCK low to output high impedance
0.0
40.0
ns
122
TMS, TDI data setup time
5.0
—
ns
123
TMS, TDI data hold time
25.0
—
ns
124
TCK low to TDO data valid
0.0
44.0
ns
125
TCK low to TDO high impedance
0.0
44.0
ns
Note:
1. VCORE_VDD = 1.25 V ± 0.05 V; TJ = –40°C to 115°C for 150 MHz; TJ = 0°C to 100°C for 181 MHz; CL = 50 pF
All timings apply to OnCE module data transfers because it uses the JTAG port as an interface.
117
TCK
(Input)
VIH
118
118
VM
VM
VIL
119
119
Figure 21. Test Clock Input Timing Diagram
Freescale Semiconductor
DSP56371 Technical Data
53
JTAG Timing
TCK
(Input)
VIH
VIL
122
Data
Inputs
123
Input Data Valid
120
Data
Outputs
Output Data Valid
121
Data
Outputs
120
Data
Outputs
Output Data Valid
Figure 22. Debugger Port Timing Diagram
TCK
(Input)
VIH
VIL
122
TDI
TMS
(Input)
123
Input Data Valid
124
TDO
(Output)
Output Data Valid
125
TDO
(Output)
124
TDO
(Output)
Output Data Valid
Figure 23. Test Access Port Timing Diagram
54
DSP56371 Technical Data
Freescale Semiconductor
Package Information
19
Package Information
IO_VDD
SCKR_PE0
SCKT_PE3
FSR_PE1
62
61
IO_GND
65
63
HCKT_PE5
66
DAX
64
HCKR_PE2
67
CORE_VDD
71
CORE_GND
HCKR_PC2
72
ADO_PD1
HCKT_PC5
73
68
IO_GND
74
ACI_PD0
IO_VDD
69
SCKR_PC0
75
ESAI
70
SCKT_PC3
FSR_PC1
78
76
FST_PC4
79
77
SDO5_SDI0_PC6
80
.
ESAI_1
SDO4_SDI1_PC7
1
60
FST_PE4
IO_GND
2
59
SDO5_SDI0_PE6
IO_VDD
3
58
SDO4_SDI1_PE7
SDO3_SDI2_PC8
4
57
SDO3_SDI2_PE8
SDO2_SDI3_PC9
5
56
SDO2_SDI3_PE9
SDO1_PC10
6
55
SDO1_PE10
SDO0_PC11
7
54
SDO0_PE11
CORE_VDD
8
53
CORE_GND
PF8
9
52
CORE_VDD
PF6
10
51
MODA_IRQA
PF7
11
50
MODB_IRQB
CORE_GND
12
49
MODC_IRQC
PF2
13
48
MODD_IRQD
PF3
14
47
RESET_B
PF4
15
46
PINIT_NMI
PF5
16
45
EXTAL
IO_VDD
17
44
PLLD_VDD
PF1
18
43
PLLD_GND
PF0
19
42
PLLP_GND
GND
20
41
PLLP_VDD
Int/Mod
GPIO
PLL
28
29
30
31
32
33
34
35
36
37
38
39
40
CORE_GND
CORE_VDD
TDO
TDI
TCK
TMS
MOSI_HA0
MISO_SDA
SCK_SCL
SS_HA2
HREQ
PLLA_VDD
PLLA_GND
25
IO_VDD
27
24
IO_GND
TIO1_PB1
23
PF10
SHI
26
22
SCAN
OnCE
TIO0_PB0
21
PF9
Timer
Figure 24. DSP56371 Pinout
Freescale Semiconductor
DSP56371 Technical Data
55
Package Information
Table 27. Signal Identification by Pin Number
Pin
No.
56
Signal Name
Pin
No
Signal Name
Pin
No
Signal Name
Pin
No
Signal Name
1
SDO4_SDI1_PC7
21
PF9
41
PLLP_VDD
61
FSR_PE1
2
IO_GND
22
SCAN
42
PLLP_GND
62
SCKT_PE3
3
IO_VDD
23
PF10
43
PLLD_GND
63
SCKR_PE0
4
SDO3_SDI2_PC8
24
IO_GND
44
PLLD_VDD
64
IO_VDD
5
SDO2_SDI3_PC9
25
IO_VDD
45
EXTAL
65
IO_GND
6
SDO1_PC10
26
TI0_PB0
46
PINIT_NMI
66
HCKT_PE5
7
SDO0_PC11
27
TI0_PB1
47
RESET_B
67
HCKR_PE2
8
CORE_VDD
28
CORE_GND
48
MODD_IRQD
68
CORE_GND
9
PF8
29
CORE_VDD
49
MODC_IRQC
69
ADO_PD1
10
PF6
30
TDO
50
MODB_IRQB
70
ADI_PD0
11
PF7
31
TDI
51
MODA_IRQA
71
CORE_VDD
12
CORE_GND
32
TCK
52
CORE_VDD
72
HCKR_PC2
13
PF2
33
TMS
53
CORE_GND
73
HCKT2_PC5
14
PF3
34
MOSI_HA0
54
SDO0_PE11
74
IO_GND
15
PF4
35
MISO_SDA
55
SDO1_PE10
75
IO_VDD
16
PF5
36
SCK_SCL
56
SDO2_SDI3_PE9
76
SCKR_PC0
17
IO_VDD
37
SS_HA2
57
SDO3_SDI2_PE8
77
SCKT_PC3
18
PF1
38
HREQ
58
SDO4_SDI1_PE7
78
FSR_PC1
19
PF0
39
PLLA_VDD
59
SDO5_SD10_PE6
79
FST_PC4
20
GND
40
PLLA_GND
60
FST_PE4
80
SDO5_SDI10_PC6
DSP56371 Technical Data
Freescale Semiconductor
Package Information
Freescale Semiconductor
DSP56371 Technical Data
57
Package Information
58
DSP56371 Technical Data
Freescale Semiconductor
Package Information
Freescale Semiconductor
DSP56371 Technical Data
59
Package Information
60
DSP56371 Technical Data
Freescale Semiconductor
Design Considerations
20
Design Considerations
20.1
Thermal Design Considerations
An estimation of the chip junction temperature, TJ, in °C can be obtained from the following equation:
T J = T A + ( P D × R θJA )
Where: TA
=
RqJA =
PD =
ambient temperature °C
package junction-to-ambient thermal resistance °C/W
power dissipation in package W
Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient
thermal resistance.
R θJA = R θJC + R θCA
Where: RθJA =
RθJC =
RθCA =
package junction-to-ambient thermal resistance °C/W
package junction-to-case thermal resistance °C/W
package case-to-ambient thermal resistance °C/W
RθJC is device-related and cannot be influenced by the user. The user controls the thermal environment to change the case-toambient thermal resistance, RθCA. For example, the user can change the air flow around the device, add a heat sink, change the
mounting arrangement on the printed circuit board (PCB), or otherwise change the thermal dissipation capability of the area
surrounding the device on a PCB. This model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is
dissipated through the case to the heat sink and out to the ambient environment. For ceramic packages, in situations where the
heat flow is split between a path to the case and an alternate path through the PCB, analysis of the device thermal performance
may need the additional modeling capability of a system level thermal simulation tool.
The thermal performance of plastic packages is more dependent on the temperature of the PCB to which the package is
mounted. Again, if the estimations obtained from RθJA do not satisfactorily answer whether the thermal performance is adequate,
a system level model may be appropriate.
A complicating factor is the existence of three common ways for determining the junction-to-case thermal resistance in plastic
packages.
•
To minimize temperature variation across the surface, the thermal resistance is measured from the junction to the
outside surface of the package (case) closest to the chip mounting area when that surface has a proper heat sink.
•
To define a value approximately equal to a junction-to-board thermal resistance, the thermal resistance is measured
from the junction to where the leads are attached to the case.
•
If the temperature of the package case (TT) is determined by a thermocouple, the thermal resistance is computed using
the value obtained by the equation
(TJ – TT)/PD.
As noted above, the junction-to-case thermal resistances quoted in this data sheet are determined using the first definition. From
a practical standpoint, that value is also suitable for determining the junction temperature from a case thermocouple reading in
forced convection environments. In natural convection, using the junction-to-case thermal resistance to estimate junction
temperature from a thermocouple reading on the case of the package will estimate a junction temperature slightly hotter than
actual temperature. Hence, the new thermal metric, thermal characterization parameter or ΨJT, has been defined to be (TJ –
TT)/PD. This value gives a better estimate of the junction temperature in natural convection when using the surface temperature
of the package. Remember that surface temperature readings of packages are subject to significant errors caused by inadequate
attachment of the sensor to the surface and to errors caused by heat loss to the sensor. The recommended technique is to attach
a 40-gauge thermocouple wire and bead to the top center of the package with thermally conductive epoxy.
Freescale Semiconductor
DSP56371 Technical Data
61
Design Considerations
20.2
Electrical Design Considerations
CAUTION
This device contains circuitry protecting against damage due to
high static voltage or electrical fields. However, normal
precautions should be taken to avoid exceeding maximum
voltage ratings. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (e.g., either
GND or VCC). The suggested value for a pullup or pulldown
resistor is 10 k ohm.
Use the following list of recommendations to assure correct DSP operation:
•
•
•
•
•
•
•
•
•
•
•
20.3
Provide a low-impedance path from the board power supply to each VCC pin on the DSP and from the board ground to
each GND pin.
Use at least six 0.01–0.1 µF bypass capacitors positioned as close as possible to the four sides of the package to
connect the VCC power source to GND.
Ensure that capacitor leads and associated printed circuit traces that connect to the chip VCC and GND pins are less
than 1.2 cm (0.5 inch) per capacitor lead.
Route the DVDD pin carefully to minimize noise.
Use at least a four-layer PCB with two inner layers for VCC and GND.
Because the DSP output signals have fast rise and fall times, PCB trace lengths should be minimal. This
recommendation particularly applies to the IRQA, IRQB, IRQC, and IRQD pins. Maximum PCB trace lengths on the
order of 15 cm (6 inches) are recommended.
Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance. This is
especially critical in systems with higher capacitive loads that could create higher transient currents in the VCC and GND
circuits.
Take special care to minimize noise levels on the VCCP and GNDP pins.
If multiple DSP56371 devices are on the same board, check for cross-talk or excessive spikes on the supplies due to
synchronous operation of the devices.
RESET must be asserted when the chip is powered up. A stable EXTAL signal must be supplied before deassertion of
RESET.
At power-up, ensure that the voltage difference between the 3.3 V tolerant pins and the chip VCC never exceeds a 3.00 V.
Power Consumption Considerations
Power dissipation is a key issue in portable DSP applications. Some of the factors which affect current consumption are
described in this section. Most of the current consumed by CMOS devices is alternating current (ac), which is charging and
discharging the capacitances of the pins and internal nodes.
Current consumption is described by the following formula:
I = C×V×f
where C
V
f
62
=
=
=
node/pin capacitance
voltage swing
frequency of node/pin toggle
DSP56371 Technical Data
Freescale Semiconductor
Power Consumption Benchmark
Power Consumption Example
For a GPIO address pin loaded with 50 pF capacitance, operating at 3.3 V, and with a 150 MHz clock, toggling at
its maximum possible rate (75 MHz), the current consumption is
I = 50 x 10 – 12 x 3.3 x 75 x 10 6 = 12.375mA
The maximum internal current (ICCImax) value reflects the typical possible switching of the internal buses on best-case operation
conditions, which is not necessarily a real application case. The typical internal current (ICCItyp) value reflects the average
switching of the internal buses on typical operating conditions.
For applications that require very low current consumption, do the following:
•
Minimize the number of pins that are switching.
•
Minimize the capacitive load on the pins.
One way to evaluate power consumption is to use a current per MIPS measurement methodology to minimize specific board
effects (i.e., to compensate for measured board current not caused by the DSP). Use the test algorithm, specific test current
measurements, and the following equation to derive the current per MIPS value.
I/MIPS = I/MHz = (ItypF2 - ItypF1)/(F2 - F1)
where :ItypF2
ItypF1
F2
F1
=
=
=
=
current at F2
current at F1
high frequency (any specified operating frequency)
low frequency (any specified operating frequency lower than F2)
NOTE
F1 should be significantly less than F2. For example, F2 could be 66 MHz and F1 could be
33 MHz. The degree of difference between F1 and F2 determines the amount of precision
with which the current rating can be determined for an application.
21
Power Consumption Benchmark
The following benchmark program permits evaluation of DSP power usage in a test situation.
;***********************************;********************************
;* ;* CHECKS Typical Power Consumption
;********************************************************************
ORG P:$000800
move #$000000,r1
move #$000000,r0
do #1024,ldmem
move r1,p:(r0)
move r1,y:(r0)+
ldmem nop
move #0,b1
;jmp $FF2AE0
;org P:$FF2AE0
move b1,y:>$100
Freescale Semiconductor
DSP56371 Technical Data
63
Power Consumption Benchmark
move
move
move
move
#$FF,B
#>$AF080,X0
#>$FF2AD6,r0
#$0,r1
dor #6,loop1
move p:(r0)+,x1
move x0,p:(r1)+
move x1,p:(r1)+
nop
loop1
move #$0,vba
move #$0,sp
move #$0,sc
reset
move #$FFFFFF,m0
move m0,m1
move m0,m2
move m0,m3
move m0,m4
move m0,m5
move m0,m6
move m0,m7
move #>$102,ep
move #>$18,sz
move #>$110000,omr
move #$300,sr
movep #>$F02000,X:$FFFFFF
movep #$187,X:$FFFFFE
;then sets up BCR and AAR registers
;then sets up PORTB and HDI08 PORT
andi #$FC,mr
;start running ROM intialisation stage
;jsr $FF1C7E
; Set green HLX zone table
jsr $FF1D64
; Run GPIONil function
jsr $FF2F82
; Initialise Green HLX
jsr $FF1FA1
; Disable DAX
move #>$15F,x1
move x1,P:$FF0D7F
; Run Green HLX
jmp $FF1FDB
nop
nop
nop
nop
nop
nop
64
DSP56371 Technical Data
Freescale Semiconductor
Power Consumption Benchmark
dor forever,endprog
nop
nop
endprog nop
Freescale Semiconductor
DSP56371 Technical Data
65
IBIS Model
22
IBIS Model
[IBIS ver]
2.1
[File name]
[File Rev]
[Date]
tpz013g3.ibs
1.0
07/30/2002
[Source]
Made By 0.13uu HSPICE model.
[Disclaimer]
This information is for modeling purposes only and is not guaranteed.
[Copyright]
Copyright 2002, Design Service, tsmc, All Rights Reserved.
|
|************************************************************************
|
Component tpz013g3
|************************************************************************
(Pin) signal_name
model_name
1
SDO4_SDI1_PC7
PRD12DGZ
2
IO_GND
PVSS3DGZ
3
IO_VDD
PVDD2DGZ
4
SDO3_SDI2_PC8
PRD12DGZ
5
SDO2_SDI3_PC9
PRD12DGZ
6
SDO1_PC10
PRD12DGZ
7
SDO0_PC11
PRD12DGZ
8
CORE_VDD
PVDD1DGZ
9
PF8
PRD12DGZ
10
PF6
PRD12DGZ
11
PF7
PRD12DGZ
12
CORE_GND
PVSS3DGZ
13
PF2
PRD12DGZ
14
PF3
PRD12DGZ
15
PF4
PRD12DGZ
16
PF5
PRD12DGZ
17
IO_VDD
PVDD2DGZ
18
PF1
PRD12DGZ
19
PF0
PRD12DGZ
66
DSP56371 Technical Data
Freescale Semiconductor
IBIS Model
20
GND
PVSS2DGZ
21
PF9
PRD12DGZ
22
SCAN
PDDDGZ
23
PF10
PRD12DGZ
24
IO_GND
PVSS3DGZ
25
IO_VDD
PVDD2DGZ
26
TI0_PB0
PVDD2DGZ
27
TI1_PB1
PVDD2DGZ
28
CORE_GND
PVSS3DGZ
29
CORE_VDD
PVDD1DGZ
30
TDO
PRT24DGZ
31
TDI
PDUDGZ
32
TCK
PDUDGZ
33
TMS
PDUDGZ
34
MOSI_HA0
PRD12DGZ
35
MISO_SDA
PRD12DGZ
36
SCK_SCL
PRD16DGZ
37
SS_HA2
PDUSDGZ
38
HREQ
PRD12DGZ
39
PLLA_VDD
PVDD1P
40
PLLA_GND
PVSS1P
41
PLLP_VDD
PVDD2DGZ
42
PLLP_GND
PVSS2P
43
PLLD_GND
PVSS1P
44a PLLD_VDD
PVDD1PC
44b
PLLD_VDD
PVDD1DGZ
45
EXTAL
PDIDGZ
46
PINIT_NMI
PDUSDGZ
47
RESET_B
PDUSDGZ
48
MODD_IRQD
PDUSDGZ
49
MODC_IRQC
PDUSDGZ
50
MODB_IRQB
PDUSDGZ
51
MODA_IRQA
PDUSDGZ
Freescale Semiconductor
DSP56371 Technical Data
67
IBIS Model
52
CORE_VDD
PVDD1DGZ
53
CORE_GND
PVSS3DGZ
54
SDO0_PE11
PRD12DGZ
55
SDO1_PE10
PRD12DGZ
56
SDO2_SDI3_PE9
PRD12DGZ
57
SDO3_SDI2_PE8
PRD12DGZ
58
SDO4_SDI1_PE7
PRD12DGZ
59
SDO5_SDI0_PE6
PRD12DGZ
60
FST_PE4
PRD12DGZ
61
FSR_PE1
PRD12DGZ
62
SCKT_PE4
PRD12DGZ
63
SCKR_PE0
PRD12DGZ
64
IO_VDD
PVDD2DGZ
65
IO_GND
PVSS3DGZ
66
HCKT_PE5
PRD12DGZ
67
HCKR_PE2
PRD12DGZ
68
CORE_GND
PVSS3DGZ
69
ADO_PD1
PRD24DGZ
70
ADI_PD2
PRD24DGZ
71
CORE_VDD
PVDD1DGZ
72
HCKR_PC2
PRD12DGZ
73
HCKT_PC5
PRD12DGZ
74
IO_GND
PVSS3DGZ
75
IO_VDD
PVDD2DGZ
76
SCKR_PC0
PRD12DGZ
77
SCKT_PC4
PRD12DGZ
78
FSR_PC1
PRD12DGZ
79
FST_PC4
PRD12DGZ
80
SDO5_SDI0_PC6
PRD12DGZ
|************************************************************************
|
Model prd12dgz
|************************************************************************
|
68
DSP56371 Technical Data
Freescale Semiconductor
IBIS Model
[Model]
prd12dgz
Model_type
I/O
Polarity
Non-Inverting
Enable
Active-Low
Vinl = 0.80V
Vinh = 2.00V
Vmeas = 1.50V
Cref = 50.00pF
Rref = 1.00M
Vref = 0.000V
C_comp
4.17pF
|
|
[Temperature Range]
25.00
[Pullup Reference]
3.30V
[Pulldown Reference]
0.000V
[POWER Clamp Reference] 5.00V
[GND Clamp Reference]
0.000V
[Pulldown]
| voltage
I(typ)
I(min)
|
-3.30
0.000A
0.000A
-3.10
0.000A
0.000A
-2.90
0.000A
0.000A
-2.70
0.000A
0.000A
-2.50
0.000A
-10.00mA
-2.30
-10.00mA
0.000A
-2.10
0.000A
-10.00mA
-1.90
0.000A
0.000A
-1.70
0.000A
0.000A
-1.50
-10.00mA
0.000A
-1.00
-11.00mA
-5.00mA
-0.90
-12.00mA
-5.00mA
-0.80
-24.00mA
-7.00mA
-0.70
-29.14mA
-8.00mA
-0.60
-26.47mA
-13.80mA
-0.50
-22.61mA
-14.54mA
-0.40
-18.32mA
-12.17mA
-0.30
-13.87mA
-9.16mA
-0.20
-9.33mA
-6.10mA
-0.10
-4.70mA
-3.05mA
-0.00
2.86nA
7.25nA
0.10
4.61mA
2.94mA
0.20
8.96mA
5.69mA
0.30
13.07mA
8.26mA
0.40
16.92mA
10.65mA
0.50
20.53mA
12.86mA
0.60
23.91mA
14.90mA
Freescale Semiconductor
3.75pF
4.58pF
0.12k
3.00V
0.000V
4.50V
0.000V
0.000
3.60V
0.000V
5.50V
0.000V
I(max)
0.000A
-10.00mA
0.000A
0.000A
0.000A
-10.00mA
0.000A
-10.00mA
-10.00mA
-10.00mA
-13.00mA
-15.00mA
-32.51mA
-32.35mA
-29.35mA
-25.54mA
-20.93mA
-15.91mA
-10.74mA
-5.43mA
11.72nA
5.36mA
10.49mA
15.36mA
20.00mA
24.40mA
28.55mA
DSP56371 Technical Data
69
IBIS Model
0.70
0.80
0.90
1.00
1.10
1.20
1.30
1.40
1.50
1.60
1.70
1.80
1.90
2.00
2.10
2.20
2.30
2.40
2.50
2.60
2.70
2.80
2.90
3.00
3.10
3.20
3.30
3.40
3.50
3.60
3.70
3.80
3.90
4.00
4.10
4.20
4.30
4.50
4.70
4.90
5.10
5.30
5.50
5.70
5.90
6.10
6.60
|
[Pullup]
| voltage
|
70
27.04mA
29.95mA
32.61mA
35.06mA
37.27mA
39.27mA
41.04mA
42.60mA
43.95mA
45.08mA
46.00mA
46.70mA
47.20mA
47.55mA
47.81mA
48.01mA
48.17mA
48.31mA
48.42mA
48.53mA
48.62mA
48.70mA
48.78mA
48.85mA
48.92mA
48.99mA
49.05mA
49.12mA
49.20mA
49.24mA
49.31mA
49.40mA
49.61mA
50.41mA
51.65mA
52.87mA
50.78mA
50.67mA
51.17mA
51.85mA
52.75mA
53.86mA
55.21mA
56.82mA
58.68mA
60.78mA
66.91mA
16.76mA
18.46mA
19.99mA
21.37mA
22.58mA
23.64mA
24.55mA
25.32mA
25.95mA
26.44mA
26.80mA
27.07mA
27.26mA
27.41mA
27.53mA
27.63mA
27.71mA
27.78mA
27.85mA
27.90mA
27.96mA
28.01mA
28.05mA
28.09mA
28.14mA
28.18mA
28.23mA
28.42mA
28.97mA
29.74mA
30.57mA
31.13mA
28.60mA
28.66mA
28.72mA
28.80mA
28.89mA
29.12mA
29.42mA
29.83mA
30.37mA
31.02mA
31.82mA
32.77mA
33.86mA
35.10mA
38.73mA
32.48mA
36.18mA
39.64mA
42.87mA
45.87mA
48.64mA
51.19mA
53.50mA
55.60mA
57.46mA
59.11mA
60.53mA
61.71mA
62.63mA
63.31mA
63.79mA
64.15mA
64.43mA
64.65mA
64.84mA
65.00mA
65.14mA
65.27mA
65.38mA
65.49mA
65.59mA
65.68mA
65.77mA
65.86mA
65.95mA
66.04mA
66.12mA
66.22mA
66.33mA
66.49mA
66.72mA
67.28mA
70.40mA
73.03mA
69.12mA
70.18mA
71.45mA
73.05mA
74.98mA
77.25mA
79.83mA
87.50mA
I(typ)
I(min)
I(max)
DSP56371 Technical Data
Freescale Semiconductor
IBIS Model
-3.30
-3.10
-2.90
-2.70
-2.50
-2.30
-2.10
-1.90
-1.70
-1.50
-1.00
-0.90
-0.80
-0.70
-0.60
-0.50
-0.40
-0.30
-0.20
-0.10
0.00
0.10
0.20
0.30
0.40
0.50
0.60
0.70
0.80
0.90
1.00
1.10
1.20
1.30
1.40
1.50
1.60
1.70
1.80
1.90
2.00
2.10
2.20
2.30
2.40
2.50
2.60
2.70
2.80
2.90
3.00
0.11A
0.11A
0.10A
97.60mA
92.41mA
87.04mA
81.44mA
75.56mA
69.36mA
62.83mA
48.46mA
43.82mA
38.59mA
33.28mA
28.26mA
23.64mA
19.01mA
14.32mA
9.58mA
4.80mA
34.08uA
-4.58mA
-8.94mA
-13.04mA
-16.89mA
-20.50mA
-23.86mA
-26.98mA
-29.87mA
-32.53mA
-34.96mA
-37.16mA
-39.15mA
-40.92mA
-42.48mA
-43.83mA
-44.98mA
-45.94mA
-46.72mA
-47.35mA
-47.86mA
-48.29mA
-48.65mA
-48.97mA
-49.25mA
-49.50mA
-49.72mA
-49.92mA
-50.11mA
-50.28mA
-50.44mA
Freescale Semiconductor
82.01mA
79.25mA
76.07mA
72.55mA
68.70mA
64.55mA
60.13mA
55.45mA
50.52mA
45.36mA
31.37mA
28.63mA
28.69mA
24.97mA
21.04mA
17.11mA
13.34mA
9.87mA
6.53mA
3.23mA
11.20uA
-3.08mA
-5.98mA
-8.72mA
-11.27mA
-13.66mA
-15.87mA
-17.92mA
-19.80mA
-21.51mA
-23.06mA
-24.45mA
-25.68mA
-26.75mA
-27.66mA
-28.43mA
-29.05mA
-29.53mA
-29.90mA
-30.20mA
-30.45mA
-30.66mA
-30.85mA
-31.02mA
-31.17mA
-31.31mA
-31.44mA
-31.56mA
-31.67mA
-31.78mA
-31.88mA
0.13A
0.13A
0.12A
0.11A
0.11A
0.10A
94.69mA
87.72mA
80.48mA
73.03mA
56.75mA
50.74mA
44.61mA
38.60mA
33.20mA
27.91mA
22.52mA
17.03mA
11.45mA
5.78mA
71.92uA
-5.50mA
-10.80mA
-15.82mA
-20.56mA
-25.04mA
-29.25mA
-33.21mA
-36.91mA
-40.36mA
-43.56mA
-46.52mA
-49.24mA
-51.73mA
-53.98mA
-56.01mA
-57.81mA
-59.40mA
-60.77mA
-61.93mA
-62.90mA
-63.70mA
-64.37mA
-64.93mA
-65.40mA
-65.82mA
-66.18mA
-66.50mA
-66.79mA
-67.05mA
-67.29mA
DSP56371 Technical Data
71
IBIS Model
3.10
3.20
3.30
3.40
3.50
3.60
3.70
3.80
3.90
4.00
4.10
4.20
4.30
4.50
4.70
4.90
5.10
5.30
5.50
5.70
5.90
6.10
6.60
|
[GND_clamp]
| voltage
|
-5.00
-4.80
-4.60
-4.40
-4.20
-4.00
-3.80
-3.60
-3.40
-3.20
-3.00
-2.80
-2.60
-2.40
-2.20
-2.00
-1.80
-1.60
-1.40
-1.20
-1.00
-0.80
-0.60
-0.40
72
-50.59mA
-50.74mA
-50.88mA
-51.01mA
-51.14mA
-51.27mA
-51.42mA
-51.84mA
-53.78mA
-64.80mA
-0.29A
-1.85A
-3.90A
-8.00A
-12.10A
-16.20A
-20.30A
-24.40A
-28.50A
-32.60A
-36.70A
-40.80A
-51.05A
-31.98mA
-32.08mA
-32.20mA
-32.75mA
-40.35mA
-0.14A
-0.94A
-2.69A
-4.48A
-6.27A
-8.06A
-9.85A
-11.63A
-15.21A
-18.79A
-22.36A
-25.94A
-29.51A
-33.09A
-36.67A
-40.24A
-43.82A
-52.76A
-67.51mA
-67.72mA
-67.92mA
-68.11mA
-68.29mA
-68.47mA
-68.64mA
-68.80mA
-68.97mA
-69.30mA
-70.82mA
-75.29mA
-83.12mA
-1.14A
-5.39A
-9.64A
-13.89A
-18.15A
-22.41A
-26.66A
-30.92A
-35.17A
-45.81A
I(typ)
I(min)
I(max)
-85.83A
-81.73A
-77.63A
-73.53A
-69.43A
-65.33A
-61.23A
-57.13A
-53.03A
-48.93A
-44.84A
-40.74A
-36.64A
-32.54A
-28.45A
-24.35A
-20.25A
-16.15A
-12.05A
-7.95A
-3.85A
-0.23A
-2.25mA
-89.81uA
-77.78A
-74.20A
-70.62A
-67.04A
-63.46A
-59.88A
-56.30A
-52.72A
-49.14A
-45.56A
-41.99A
-38.42A
-34.84A
-31.27A
-27.69A
-24.12A
-20.54A
-16.97A
-13.39A
-9.82A
-6.24A
-2.66A
-0.10A
-0.52mA
-88.32A
-84.06A
-79.80A
-75.54A
-71.28A
-67.02A
-62.76A
-58.50A
-54.24A
-49.98A
-45.73A
-41.48A
-37.22A
-32.97A
-28.72A
-24.46A
-20.21A
-15.95A
-11.70A
-7.44A
-3.19A
-70.99mA
-5.98mA
-0.26mA
DSP56371 Technical Data
Freescale Semiconductor
IBIS Model
-0.20
-0.00
0.20
0.40
0.60
0.80
1.00
1.20
1.40
1.60
1.80
2.00
2.20
2.40
2.60
2.80
3.00
3.20
3.40
3.60
3.80
4.00
4.20
4.40
4.60
4.80
5.00
-27.92uA
-87.63nA
18.71uA
29.19uA
32.49uA
33.07uA
33.30uA
33.45uA
33.57uA
33.68uA
33.77uA
33.87uA
33.96uA
34.01uA
34.03uA
34.05uA
34.06uA
34.07uA
34.07uA
34.07uA
34.07uA
34.07uA
34.07uA
34.07uA
34.07uA
34.07uA
34.07uA
|
[POWER_clamp]
| voltage
I(typ)
|
-5.00
48.57uA
-4.90
48.24uA
-4.80
47.91uA
-4.70
47.58uA
-4.60
47.25uA
-4.50
46.92uA
-4.40
46.59uA
-4.30
46.26uA
-4.20
45.93uA
-4.10
45.60uA
-4.00
45.27uA
-3.90
44.94uA
-3.80
4.61uA
-3.70
44.28uA
-3.60
43.95uA
-3.50
43.62uA
-3.40
43.29uA
-3.30
42.96uA
-3.20
42.63uA
-3.10
42.30uA
Freescale Semiconductor
-14.70uA
-89.05nA
7.31uA
10.25uA
10.67uA
10.78uA
10.86uA
10.92uA
10.97uA
11.02uA
11.07uA
11.11uA
11.14uA
11.15uA
11.16uA
11.17uA
11.19uA
11.51uA
10.95uA
10.39uA
9.83uA
9.27uA
8.71uA
8.15uA
7.59uA
7.03uA
6.47uA
-42.92uA
-0.10uA
32.27uA
54.12uA
65.78uA
69.33uA
70.17uA
70.55uA
70.80uA
70.99uA
71.16uA
71.32uA
71.46uA
71.61uA
71.76uA
71.84uA
71.86uA
71.88uA
71.90uA
71.92uA
71.94uA
71.96uA
71.98uA
72.00uA
72.02uA
72.04uA
72.06uA
I(min)
I(max)
16.33uA
16.21uA
16.09uA
15.97uA
15.85uA
15.73uA
15.61uA
15.49uA
15.37uA
15.25uA
15.13uA
15.01uA
14.89uA
14.77uA
14.65uA
14.53uA
14.41uA
14.29uA
14.17uA
14.05uA
95.57uA
95.07uA
94.57uA
94.07uA
93.57uA
93.07uA
92.57uA
92.07uA
91.57uA
91.07uA
90.57uA
90.07uA
89.57uA
89.07uA
88.57uA
88.07uA
87.57uA
87.07uA
86.57uA
86.07uA
DSP56371 Technical Data
73
IBIS Model
-3.00
-2.90
-2.80
-2.70
-2.60
-2.50
-2.40
-2.30
-2.20
-2.10
-2.00
-1.90
-1.80
-1.70
-1.60
-1.50
-1.40
-1.30
-1.20
-1.10
-1.00
-0.90
-0.80
-0.70
-0.60
-0.50
0.40
-0.30
-0.20
-0.10
41.97uA
41.64uA
41.31uA
40.98uA
40.65uA
40.32uA
39.99uA
39.66uA
39.33uA
39.00uA
38.67uA
38.34uA
38.01uA
37.68uA
37.35uA
37.02uA
36.71uA
36.42uA
36.15uA
35.89uA
35.66uA
35.45uA
35.26uA
35.09uA
34.93uA
34.80uA
34.68uA
34.59uA
34.50uA
34.43uA
13.93uA
13.81uA
13.69uA
13.57uA
13.45uA
13.33uA
13.21uA
13.09uA
12.97uA
12.85uA
12.73uA
12.61uA
12.49uA
12.37uA
12.25uA
12.15uA
12.05uA
11.95uA
11.87uA
11.79uA
11.72uA
11.66uA
11.60uA
11.55uA
11.51uA
11.47uA
11.43uA
11.41uA
11.38uA
11.36uA
0.00
34.37uA
11.34uA
|
[Ramp]
| variable
typ
dV/dt_r
1.21/2.06n
dV/dt_f
1.22/2.51n
R_load = 50.00
|
[Rising Waveform]
R_fixture = 50.00
V_fixture = 0.000
V_fixture_min = 0.000
V_fixture_max = 0.000
L_fixture = 0.000H
C_fixture = 0.000F
| time
V(typ)
|
0.000S
1.26uV
0.20nS
1.04uV
0.40nS
-5.64uV
74
85.57uA
85.07uA
84.57uA
84.07uA
83.57uA
83.07uA
82.57uA
82.07uA
81.57uA
81.07uA
80.57uA
80.07uA
79.57uA
79.07uA
78.57uA
78.07uA
77.57uA
77.07uA
76.57uA
76.07uA
75.57uA
75.10uA
74.67uA
74.28uA
73.93uA
73.61uA
73.34uA
73.10uA
72.89uA
72.72uA
72.57uA
min
0.85/2.62n
0.78/3.11n
max
1.45/1.82n
1.45/2.14n
V(min)
V(max)
1.62uV
1.45uV
-1.36uV
1.22uV
0.74uV
11.59uV
DSP56371 Technical Data
Freescale Semiconductor
IBIS Model
0.60nS
0.80nS
1.00nS
1.20nS
1.40nS
1.60nS
1.80nS
2.00nS
2.20nS
2.40nS
2.60nS
2.80nS
3.00nS
3.20nS
3.40nS
3.60nS
3.80nS
4.00nS
4.20nS
4.40nS
4.60nS
4.80nS
5.00nS
5.20nS
5.40nS
5.60nS
5.80nS
6.00nS
6.20nS
6.40nS
6.60nS
6.80nS
7.00nS
7.20nS
7.40nS
7.60nS
7.80nS
8.00nS
8.20nS
8.40nS
8.60nS
8.80nS
9.00nS
9.20nS
9.40nS
9.60nS
9.80nS
10.00nS
-0.29mV
-3.54mV
-3.50mV
33.86mV
79.34mV
0.14V
0.20V
0.28V
0.36V
0.47V
0.60V
0.77V
0.92V
1.03V
1.16V
1.29V
1.39V
1.49V
1.58V
1.65V
1.69V
1.72V
1.76V
1.80V
1.83V
1.86V
1.88V
1.89V
1.91V
1.92V
1.93V
1.94V
1.95V
1.96V
1.97V
1.98V
1.98V
1.98V
1.99V
1.99V
1.99V
2.00V
2.00V
2.00V
2.01V
2.01V
2.01V
2.01V
-5.13uV
25.94uV
-4.79uV
-0.86mV
-3.75mV
-8.09mV
3.52mV
38.97mV
82.84mV
0.13V
0.18V
0.27V
0.34V
0.40V
0.50V
0.59V
0.67V
0.75V
0.84V
0.91V
0.95V
0.99V
1.03V
1.07V
1.12V
1.16V
1.18V
1.20V
1.23V
1.25V
1.27V
1.28V
1.30V
1.31V
1.33V
1.34V
1.35V
1.36V
1.37V
1.37V
1.38V
1.39V
1.39V
1.40V
1.40V
1.41V
1.41V
1.41V
-3.27mV
-9.17mV
56.24mV
0.13V
0.19V
0.27V
0.36V
0.47V
0.59V
0.74V
0.90V
1.12V
1.32V
1.46V
1.63V
1.78V
1.91V
2.01V
2.11V
2.18V
2.21V
2.23V
2.27V
2.29V
2.31V
2.33V
2.34V
2.34V
2.35V
2.36V
2.37V
2.38V
2.38V
2.39V
2.39V
2.39V
2.40V
2.40V
2.40V
2.40V
2.41V
2.41V
2.41V
2.41V
2.41V
2.42V
2.42V
2.42V
|
[Rising Waveform]
R_fixture = 50.00
Freescale Semiconductor
DSP56371 Technical Data
75
IBIS Model
V_fixture = 3.30
V_fixture_min = 3.00
V_fixture_max = 3.60
L_fixture = 0.000H
C_fixture = 0.000F
| time
V(typ)
|
0.000S
1.27V
0.20nS
1.27V
0.40nS
1.27V
0.60nS
1.27V
0.80nS
1.28V
1.00nS
1.40V
1.20nS
1.60V
1.40nS
1.77V
1.60nS
1.99V
1.80nS
2.24V
2.00nS
2.50V
2.20nS
2.74V
2.40nS
2.94V
2.60nS
3.09V
2.80nS
3.18V
3.00nS
3.24V
3.20nS
3.26V
3.40nS
3.27V
3.60nS
3.29V
3.80nS
3.29V
4.00nS
3.30V
4.20nS
3.30V
4.40nS
3.30V
4.60nS
3.30V
4.80nS
3.30V
5.00nS
3.30V
5.20nS
3.30V
5.40nS
3.30V
5.60nS
3.30V
5.80nS
3.30V
6.00nS
3.30V
6.20nS
3.30V
6.40nS
3.30V
6.60nS
3.30V
6.80nS
3.30V
7.00nS
3.30V
7.20nS
3.30V
7.40nS
3.30V
7.60nS
3.30V
7.80nS
3.30V
8.00nS
3.30V
8.20nS
3.30V
8.40nS
3.30V
8.60nS
3.30V
76
V(min)
V(max)
1.66V
1.66V
1.66V
1.66V
1.66V
1.66V
1.67V
1.69V
1.80V
1.95V
2.13V
2.32V
2.49V
2.63V
2.79V
2.87V
2.91V
2.96V
2.98V
2.99V
2.99V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
1.18V
1.18V
1.18V
1.19V
1.24V
1.47V
1.71V
1.88V
2.12V
2.41V
2.70V
2.99V
3.21V
3.34V
3.44V
3.49V
3.52V
3.55V
3.57V
3.59V
3.59V
3.60V
3.60V
3.60V
3.60V
3.60V
3.60V
3.60V
3.60V
3.60V
3.60V
3.60V
3.60V
3.60V
3.60V
3.60V
3.60V
3.60V
3.60V
3.60V
3.60V
3.60V
3.60V
3.60V
DSP56371 Technical Data
Freescale Semiconductor
IBIS Model
8.80nS
9.00nS
9.20nS
9.40nS
9.60nS
9.80nS
10.00nS
3.30V
3.30V
3.30V
3.30V
3.30V
3.30V
3.30V
|
[Falling Waveform]
R_fixture = 50.00
V_fixture = 0.000
V_fixture_min = 0.000
V_fixture_max = 0.000
L_fixture = 0.000H
C_fixture = 0.000F
|time
V(typ)
|
0.000S
2.02V
0.20nS
2.02V
0.40nS
2.02V
0.60nS
2.02V
0.80nS
1.97V
1.00nS
1.73V
1.20nS
1.45V
1.40nS
1.24V
1.60nS
0.96V
1.80nS
0.70V
2.00nS
0.50V
2.20nS
0.36V
2.40nS
0.27V
2.60nS
0.20V
2.80nS
0.14V
3.00nS
99.16mV
3.20nS
79.41mV
3.40nS
53.08mV
3.60nS
36.21mV
3.80nS
23.36mV
4.00nS
12.42mV
4.20nS
6.73mV
4.40nS
2.10mV
4.60nS
1.57mV
4.80nS
1.14mV
5.00nS
0.68mV
5.20nS
0.62mV
5.40nS
0.54mV
5.60nS
0.46mV
5.80nS
0.41mV
6.00nS
0.37mV
6.20nS
0.34mV
6.40nS
0.32mV
6.60nS
0.27mV
Freescale Semiconductor
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.60V
3.60V
3.60V
3.60V
3.60V
3.60V
3.60V
V(min)
V(max)
1.44V
1.44V
1.44V
1.44V
1.44V
1.44V
1.42V
1.38V
1.29V
1.12V
0.92V
0.73V
0.55V
0.40V
0.27V
0.20V
0.16V
0.11V
75.26mV
51.00mV
31.87mV
18.57mV
8.15mV
5.93mV
3.71mV
1.71mV
1.31mV
0.89mV
0.73mV
0.65mV
0.59mV
0.53mV
0.48mV
0.43mV
2.43V
2.43V
2.43V
2.38V
2.13V
1.82V
1.49V
1.24V
0.92V
0.67V
0.50V
0.38V
0.30V
0.24V
0.17V
0.13V
0.11V
78.74mV
59.16mV
39.59mV
27.31mV
15.01mV
7.54mV
4.99mV
2.45mV
1.29mV
0.88mV
0.54mV
0.46mV
0.42mV
0.38mV
0.34mV
0.29mV
0.26mV
DSP56371 Technical Data
77
IBIS Model
6.80nS
7.00nS
7.20nS
7.40nS
7.60nS
7.80nS
8.00nS
8.20nS
8.40nS
8.60nS
8.80nS
9.00nS
9.20nS
9.40nS
9.60nS
9.80nS
10.00nS
0.22mV
0.18mV
0.18mV
0.18mV
0.15mV
0.12mV
0.11mV
0.11mV
0.12mV
97.87uV
59.73uV
36.18uV
61.23uV
87.87uV
67.13uV
29.42uV
71.42uV
|
[Falling Waveform]
R_fixture = 50.00
V_fixture = 3.30
V_fixture_min = 3.00
V_fixture_max = 3.60
L_fixture = 0.000H
C_fixture = 0.000F
| time
V(typ)
|
0.000S
3.30V
0.20nS
3.30V
0.40nS
3.30V
0.60nS
3.30V
0.80nS
3.30V
1.00nS
3.22V
1.20nS
3.12V
1.40nS
3.06V
1.60nS
2.96V
1.80nS
2.86V
2.00nS
2.75V
2.20nS
2.64V
2.40nS
2.52V
2.60nS
2.40V
2.80nS
2.26V
3.00nS
2.16V
3.20nS
2.10V
3.40nS
2.01V
3.60nS
1.93V
3.80nS
1.86V
4.00nS
1.78V
4.20nS
1.68V
4.40nS
1.58V
4.60nS
1.53V
78
0.38mV
0.34mV
0.30mV
0.26mV
0.23mV
0.22mV
0.20mV
0.18mV
0.17mV
0.16mV
0.15mV
0.14mV
0.12mV
0.10mV
0.10mV
0.10mV
84.83uV
0.22mV
0.20mV
0.18mV
0.15mV
0.13mV
0.12mV
0.11mV
0.10mV
92.36uV
78.53uV
64.71uV
61.02uV
60.74uV
58.12uV
46.02uV
39.81uV
50.29uV
V(min)
V(max)
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
2.95V
2.89V
2.83V
2.77V
2.70V
2.61V
2.54V
2.48V
2.41V
2.35V
2.30V
2.25V
2.19V
2.13V
2.10V
3.60V
3.60V
3.60V
3.59V
3.48V
3.36V
3.25V
3.16V
3.04V
2.90V
2.76V
2.61V
2.48V
2.34V
2.18V
2.04V
1.93V
1.79V
1.68V
1.57V
1.49V
1.41V
1.34V
1.31V
DSP56371 Technical Data
Freescale Semiconductor
IBIS Model
4.80nS
5.00nS
5.20nS
5.40nS
5.60nS
5.80nS
6.00nS
6.20nS
6.40nS
6.60nS
6.80nS
7.00nS
7.20nS
7.40nS
7.60nS
7.80nS
8.00nS
8.20nS
8.40nS
8.60nS
8.80nS
9.00nS
9.20nS
9.40nS
9.60nS
9.80nS
10.00nS
1.49V
1.43V
1.39V
1.35V
1.32V
1.31V
1.30V
1.29V
1.29V
1.29V
1.28V
1.28V
1.28V
1.28V
1.28V
1.28V
1.28V
1.28V
1.27V
1.27V
1.27V
1.27V
1.27V
1.27V
1.27V
1.27V
1.27V
2.08V
2.04V
2.01V
1.98V
1.95V
1.94V
1.93V
1.91V
1.90V
1.88V
1.87V
1.85V
1.84V
1.83V
1.82V
1.81V
1.81V
1.80V
1.79V
1.79V
1.78V
1.77V
1.76V
1.75V
1.73V
1.72V
1.71V
1.29V
1.26V
1.24V
1.22V
1.21V
1.20V
1.20V
1.19V
1.19V
1.19V
1.19V
1.19V
1.19V
1.19V
1.19V
1.19V
1.19V
1.19V
1.19V
1.19V
1.19V
1.19V
1.19V
1.19V
1.18V
1.18V
1.18V
|
| End [Model] prd12dgz
|
|************************************************************************
|
Model prd16dgz
|************************************************************************
|
[Model]
prd16dgz
Model_type
I/O
Polarity
Non-Inverting
Enable
Active-Low
Vinl = 0.80V
Vinh = 2.00V
Vmeas = 1.50V
Cref = 50.00pF
Rref = 1.00M
Vref = 0.000V
C_comp
3.86pF
3.48pF
4.25pF
|
|
[Temperature Range]
25.00
0.12k
0.000
[Pullup Reference]
3.30V
3.00V
3.60V
[Pulldown Reference]
0.000V
0.000V
0.000V
[POWER Clamp Reference] 5.00V
4.50V
5.50V
Freescale Semiconductor
DSP56371 Technical Data
79
IBIS Model
[GND Clamp Reference]
[Pulldown]
| voltage
I(typ)
|
-3.30
-10.00mA
-3.10
0.000A
-2.90
0.000A
-2.70
0.000A
-2.50
0.000A
-2.30
0.000A
-2.10
-10.00mA
-1.90
0.000A
-1.70
-10.00mA
-1.50
-10.00mA
-1.00
-16.00mA
-0.90
-16.00mA
-0.80
-32.00mA
-0.70
-38.86mA
-0.60
-35.29mA
-0.50
-30.14mA
-0.40
-24.42mA
-0.30
-18.49mA
-0.20
-12.44mA
-0.10
-6.27mA
-0.00
4.09nA
0.10
6.14mA
0.20
11.95mA
0.30
17.42mA
0.40
22.56mA
0.50
27.38mA
0.60
31.88mA
0.70
36.06mA
0.80
39.93mA
0.90
43.49mA
1.00
46.74mA
1.10
49.69mA
1.20
52.35mA
1.30
54.72mA
1.40
56.80mA
1.50
58.59mA
1.60
60.11mA
1.70
61.33mA
1.80
62.26mA
1.90
62.93mA
2.00
63.40mA
2.10
63.75mA
2.20
64.01mA
2.30
64.23mA
2.40
64.41mA
2.50
64.56mA
2.60
64.70mA
80
0.000V
0.000V
I(min)
I(max)
0.000A
0.000A
0.000A
0.000A
0.000A
0.000A
0.000A
0.000A
0.000A
0.000A
-6.00mA
-8.00mA
-8.00mA
-10.60mA
-18.40mA
-19.39mA
-16.22mA
-12.22mA
-8.14mA
-4.06mA
6.98nA
3.92mA
7.59mA
11.01mA
14.20mA
17.14mA
19.86mA
22.35mA
24.61mA
26.66mA
28.49mA
30.11mA
31.52mA
32.74mA
33.76mA
34.59mA
35.25mA
35.74mA
36.09mA
36.35mA
36.55mA
36.71mA
36.84mA
36.95mA
37.04mA
37.13mA
37.21mA
0.000A
0.000A
0.000A
0.000A
0.000A
0.000A
0.000A
-10.00mA
-10.00mA
-20.00mA
-18.00mA
-21.00mA
-43.34mA
-43.13mA
-39.13mA
-34.05mA
-27.89mA
-21.21mA
-14.32mA
-7.24mA
10.67nA
7.15mA
13.98mA
20.48mA
26.67mA
32.53mA
38.07mA
43.31mA
48.24mA
52.85mA
57.16mA
61.16mA
64.86mA
68.25mA
71.34mA
74.13mA
76.62mA
78.81mA
80.70mA
82.27mA
83.51mA
84.41mA
85.06mA
85.54mA
85.91mA
86.20mA
86.45mA
0.000V
DSP56371 Technical Data
Freescale Semiconductor
IBIS Model
2.70
2.80
2.90
3.00
3.10
3.20
3.30
3.40
3.50
3.60
3.70
3.80
3.90
4.00
4.10
4.20
4.30
4.50
4.70
4.90
5.10
5.30
5.50
5.70
5.90
6.10
6.60
|
[Pullup]
| voltage
|
-3.30
-3.10
-2.90
-2.70
-2.50
-2.30
-2.10
-1.90
-1.70
-1.50
-1.00
-0.90
-0.80
-0.70
-0.60
-0.50
-0.40
-0.30
-0.20
-0.10
64.82mA
64.94mA
65.04mA
65.14mA
65.23mA
65.32mA
65.40mA
65.49mA
65.59mA
65.66mA
65.75mA
65.86mA
66.08mA
66.86mA
68.11mA
69.36mA
67.34mA
67.43mA
68.10mA
69.00mA
70.20mA
71.67mA
73.47mA
75.61mA
78.09mA
80.89mA
89.06mA
37.28mA
37.34mA
37.40mA
37.46mA
37.51mA
37.57mA
37.63mA
37.81mA
38.34mA
39.10mA
39.94mA
40.42mA
38.09mA
38.16mA
38.25mA
38.35mA
38.47mA
38.78mA
39.19mA
39.73mA
40.44mA
41.32mA
42.38mA
43.64mA
45.10mA
46.75mA
51.59mA
86.66mA
86.85mA
87.02mA
87.17mA
87.32mA
87.45mA
87.58mA
87.70mA
87.82mA
87.93mA
88.05mA
88.16mA
88.29mA
88.44mA
88.63mA
88.90mA
89.46mA
92.67mA
95.47mA
91.91mA
93.29mA
95.00mA
97.12mA
99.69mA
0.10A
0.11A
0.12A
I(typ)
I(min)
I(max)
0.16A
0.16A
0.15A
0.14A
0.14A
0.13A
0.12A
0.11A
0.10A
93.76mA
70.54mA
63.97mA
56.74mA
49.39mA
42.27mA
35.43mA
28.50mA
21.47mA
14.35mA
7.19mA
0.12A
0.12A
0.11A
0.11A
0.10A
96.26mA
89.72mA
82.79mA
75.47mA
67.80mA
46.98mA
42.83mA
41.47mA
36.27mA
30.78mA
25.27mA
19.90mA
14.79mA
9.79mA
4.85mA
0.19A
0.18A
0.17A
0.16A
0.16A
0.15A
0.14A
0.13A
0.12A
0.11A
82.43mA
74.23mA
65.83mA
57.50mA
49.67mA
41.79mA
33.74mA
25.52mA
17.14mA
8.64mA
Freescale Semiconductor
DSP56371 Technical Data
81
IBIS Model
0.00
0.10
0.20
0.30
0.40
0.50
0.60
0.70
0.80
0.90
1.00
1.10
1.20
1.30
1.40
1.50
1.60
1.70
1.80
1.90
2.00
2.10
2.20
2.30
2.40
2.50
2.60
2.70
2.80
2.90
3.00
3.10
3.20
3.30
3.40
3.50
3.60
3.70
3.80
3.90
4.00
4.10
4.20
4.30
4.50
4.70
4.90
5.10
5.30
5.50
5.70
82
34.08uA
-6.89mA
-13.43mA
-19.58mA
-25.36mA
-30.77mA
-35.81mA
-40.49mA
-44.83mA
-48.81mA
-52.46mA
-55.77mA
-58.75mA
-61.41mA
-63.75mA
-65.77mA
-67.50mA
-68.93mA
-70.10mA
-71.04mA
-71.82mA
-72.46mA
-73.01mA
-73.48mA
-73.90mA
-74.27mA
-74.60mA
-74.91mA
-75.18mA
-75.44mA
-75.68mA
-75.90mA
-76.12mA
-76.32mA
-76.52mA
-76.71mA
-76.89mA
-77.09mA
-77.56mA
-79.54mA
-90.56mA
-0.31A
-1.88A
-3.93A
-8.04A
-12.14A
-16.25A
-20.36A
-24.46A
-28.57A
-32.68A
11.19uA
-4.62mA
-8.98mA
-13.08mA
-16.92mA
-20.50mA
-23.82mA
-26.89mA
-29.70mA
-32.27mA
-34.60mA
-36.68mA
-38.52mA
-40.13mA
-41.50mA
-42.65mA
-43.58mA
-44.31mA
-44.87mA
-45.31mA
-45.68mA
-46.00mA
-46.28mA
-46.53mA
-46.76mA
-46.97mA
-47.17mA
-47.35mA
-47.52mA
-47.68mA
-47.83mA
-47.97mA
-48.11mA
-48.27mA
-48.87mA
-56.48mA
-0.15A
-0.95A
-2.71A
-4.50A
-6.29A
-8.09A
-9.88A
-11.66A
-15.24A
-18.83A
-22.41A
-25.99A
-29.57A
-33.15A
-36.73A
71.92uA
-8.29mA
-16.24mA
-23.77mA
-30.88mA
-37.60mA
-43.93mA
-49.86mA
-55.41mA
-60.59mA
-65.39mA
-69.83mA
-73.91mA
-77.64mA
-81.02mA
-84.06mA
-86.77mA
-89.14mA
-91.20mA
-92.94mA
-94.40mA
-95.60mA
-96.60mA
-97.44mA
-98.15mA
-98.77mA
-99.31mA
-99.80mA
-0.10A
-0.10A
-0.10A
-0.10A
-0.10A
-0.10A
-0.10A
-0.10A
-0.10A
-0.10A
-0.10A
-0.10A
-0.10A
-0.11A
-0.11A
-0.12A
-1.17A
-5.43A
-9.69A
-13.95A
-18.21A
-22.48A
-26.74A
DSP56371 Technical Data
Freescale Semiconductor
IBIS Model
5.90
6.10
6.60
|
[GND_clamp]
| voltage
|
-5.00
-4.80
-4.60
-4.40
-4.20
-4.00
-3.80
-3.60
-3.40
-3.20
-3.00
-2.80
-2.60
-2.40
-2.20
-2.00
-1.80
-1.60
-1.40
-1.20
-1.00
-0.80
-0.60
-0.40
0.20
-0.00
0.20
0.40
0.60
0.80
1.00
1.20
1.40
1.60
1.80
2.00
2.20
2.40
2.60
2.80
3.00
3.20
3.40
3.60
-36.78A
-40.89A
-51.16A
-40.31A
-43.89A
-52.84A
-31.00A
-35.27A
-45.93A
I(typ)
I(min)
I(max)
-85.90A
-81.80A
-77.70A
-73.60A
-69.50A
-65.40A
-61.30A
-57.20A
-53.10A
-49.00A
-44.90A
-40.80A
-36.69A
-32.59A
-28.49A
-24.38A
-20.28A
-16.17A
-12.06A
-7.96A
-3.86A
-0.23A
-2.22mA
-89.20uA
-27.89uA
-62.88nA
18.73uA
29.21uA
32.51uA
33.09uA
33.31uA
33.46uA
33.58uA
33.69uA
33.78uA
33.87uA
33.96uA
34.01uA
34.03uA
34.04uA
34.05uA
34.06uA
34.08uA
34.10uA
-77.84A
-74.26A
-70.68A
-67.10A
-63.52A
-59.94A
-56.36A
-52.78A
-49.20A
-45.62A
-42.04A
-38.46A
-34.89A
-31.31A
-27.73A
-24.15A
-20.57A
-16.99A
-13.40A
-9.83A
-6.25A
-2.66A
-0.10A
-0.52mA
-14.67uA
-63.80nA
7.33uA
10.27uA
10.69uA
10.80uA
10.87uA
10.93uA
10.98uA
11.03uA
11.08uA
11.12uA
11.14uA
11.15uA
11.16uA
11.17uA
11.18uA
11.57uA
10.87uA
10.17uA
-88.40A
-84.14A
-79.88A
-75.62A
-71.36A
-67.10A
-62.84A
-58.58A
-54.32A
-50.06A
-45.80A
-41.54A
-37.28A
-33.02A
-28.76A
-24.50A
-20.24A
-15.97A
-11.71A
-7.45A
-3.19A
-70.76mA
-5.90mA
-0.26mA
-42.88uA
-74.38nA
32.30uA
54.14uA
65.81uA
69.35uA
70.19uA
70.56uA
70.81uA
71.00uA
71.17uA
71.33uA
71.47uA
71.62uA
71.76uA
71.84uA
71.86uA
71.88uA
71.90uA
71.92uA
Freescale Semiconductor
DSP56371 Technical Data
83
IBIS Model
3.80
4.00
4.20
4.40
4.60
4.80
5.00
34.12uA
34.14uA
34.16uA
34.18uA
34.20uA
34.22uA
34.24uA
|
[POWER_clamp]
| voltage
I(typ)
|
-5.00
48.54uA
-4.90
48.21uA
-4.80
47.88uA
-4.70
47.55uA
-4.60
47.22uA
-4.50
46.89uA
-4.40
46.56uA
-4.30
46.23uA
-4.20
45.90uA
-4.10
45.57uA
-4.00
45.24uA
-3.90
44.91uA
-3.80
44.58uA
-3.70
44.25uA
-3.60
43.92uA
-3.50
43.59uA
-3.40
43.26uA
-3.30
42.93uA
-3.20
42.60uA
-3.10
42.27uA
-3.00
41.94uA
-2.90
41.61uA
-2.80
41.28uA
-2.70
40.95uA
-2.60
40.62uA
2.50
40.29uA
-2.40
39.96uA
-2.30
39.63uA
-2.20
39.30uA
-2.10
38.97uA
-2.00
38.64uA
-1.90
38.31uA
-1.80
37.98uA
-1.70
37.65uA
-1.60
37.32uA
-1.50
36.99uA
-1.40
36.68uA
-1.30
36.39uA
-1.20
36.12uA
-1.10
35.87uA
84
9.47uA
8.77uA
8.07uA
7.37uA
6.67uA
5.97uA
5.27uA
71.94uA
71.96uA
71.98uA
72.00uA
72.02uA
72.04uA
72.06uA
I(min)
I(max)
16.29uA
16.17uA
16.05uA
15.93uA
15.81uA
15.69uA
15.57uA
15.45uA
15.33uA
15.21uA
15.09uA
14.97uA
14.85uA
14.73uA
14.61uA
14.49uA
14.37uA
14.25uA
14.13uA
14.01uA
13.89uA
13.77uA
13.65uA
13.53uA
13.41uA
13.29uA
13.17uA
13.05uA
12.93uA
12.81uA
12.69uA
12.57uA
12.45uA
12.33uA
12.22uA
12.11uA
12.02uA
11.92uA
11.84uA
11.76uA
95.93uA
95.42uA
94.91uA
94.40uA
93.89uA
93.38uA
92.87uA
92.36uA
91.85uA
91.34uA
90.83uA
90.32uA
89.81uA
89.30uA
88.79uA
88.28uA
87.77uA
87.26uA
86.75uA
86.24uA
85.73uA
85.22uA
84.71uA
84.20uA
83.69uA
83.18uA
82.67uA
82.16uA
81.65uA
81.14uA
80.63uA
80.12uA
79.61uA
79.10uA
78.59uA
78.08uA
77.57uA
77.06uA
76.55uA
76.04uA
DSP56371 Technical Data
Freescale Semiconductor
IBIS Model
-1.00
-0.90
-0.80
-0.70
-0.60
-0.50
-0.40
-0.30
-0.20
-0.10
0.00
35.63uA
35.42uA
35.23uA
35.06uA
34.91uA
34.78uA
34.66uA
34.56uA
34.48uA
34.41uA
34.35uA
|
[Ramp]
| variable
typ
dV/dt_r
1.43/2.06n
dV/dt_f
1.39/2.80n
R_load = 50.00
|
[Rising Waveform]
R_fixture = 50.00
V_fixture = 0.000
V_fixture_min = 0.000
V_fixture_max = 0.000
L_fixture = 0.000H
C_fixture = 0.000F
| time
V(typ)
0.000S
0.20nS
0.40nS
0.60nS
0.80nS
1.00nS
1.20nS
1.40nS
1.60nS
1.80nS
2.00nS
2.20nS
2.40nS
2.60nS
2.80nS
3.00nS
3.20nS
3.40nS
3.60nS
3.80nS
4.00nS
4.20nS
4.40nS
4.60nS
0.71uV
0.48uV
-6.07uV
-0.29mV
-3.39mV
-4.34mV
25.79mV
62.40mV
0.11V
0.16V
0.22V
0.28V
0.37V
0.48V
0.63V
0.79V
0.90V
1.07V
1.24V
1.39V
1.55V
1.71V
1.84V
1.90V
Freescale Semiconductor
11.69uA
11.63uA
11.58uA
11.53uA
11.48uA
11.44uA
11.41uA
11.38uA
11.36uA
11.34uA
11.32uA
75.53uA
75.06uA
74.64uA
4.25uA
73.90uA
73.58uA
73.31uA
73.07uA
72.87uA
72.69uA
72.55uA
min
1.08/2.82n
0.98/4.41n
max
1.66/1.86n
1.61/2.52n
V(min)
V(max)
0.94uV
0.81uV
-1.89uV
-5.66uV
26.90uV
-5.17uV
-0.87mV
-3.65mV
-7.89mV
0.71mV
29.71mV
65.63mV
0.10V
0.15V
0.22V
0.28V
0.34V
0.43V
0.53V
0.63V
0.74V
0.86V
0.97V
1.03V
0.68uV
0.000V
12.38uV
-3.13mV
-6.39mV
43.34mV
0.11V
0.15V
0.21V
0.28V
0.37V
0.46V
0.59V
0.71V
0.92V
1.12V
1.28V
1.49V
1.70V
1.89V
2.07V
2.24V
2.37V
2.44V
DSP56371 Technical Data
85
IBIS Model
4.80nS
5.00nS
5.20nS
5.40nS
5.60nS
5.80nS
6.00nS
6.20nS
6.40nS
6.60nS
6.80nS
7.00nS
7.20nS
7.40nS
7.60nS
7.80nS
8.00nS
8.20nS
8.40nS
8.60nS
8.80nS
9.00nS
9.20nS
9.40nS
9.60nS
9.80nS
10.00nS
1.96V
2.03V
2.08V
2.13V
2.18V
2.20V
2.22V
2.24V
2.26V
2.27V
2.29V
2.30V
2.31V
2.32V
2.33V
2.34V
2.34V
2.35V
2.35V
2.36V
2.36V
2.36V
2.37V
2.37V
2.38V
2.38V
2.38V
|
[Rising Waveform]
R_fixture = 50.00
V_fixture = 3.30
V_fixture_min = 3.00
V_fixture_max = 3.60
L_fixture = 0.000H
C_fixture = 0.000F
| time
V(typ)
|
0.000S
0.98V
0.20nS
0.98V
0.40nS
0.98V
0.60nS
0.98V
0.80nS
0.99V
1.00nS
1.05V
1.20nS
1.18V
1.40nS
1.31V
1.60nS
1.49V
1.80nS
1.69V
2.00nS
1.92V
2.20nS
2.18V
2.40nS
2.46V
2.60nS
2.73V
86
1.09V
1.16V
1.22V
1.29V
1.36V
1.39V
1.43V
1.47V
1.51V
1.54V
1.57V
1.60V
1.63V
1.66V
1.68V
1.69V
1.70V
1.72V
1.73V
1.74V
1.75V
1.76V
1.77V
1.78V
1.79V
1.80V
1.80V
2.50V
2.54V
2.59V
2.62V
2.65V
2.66V
2.67V
2.68V
2.69V
2.70V
2.71V
2.72V
2.72V
2.73V
2.74V
2.74V
2.74V
2.75V
2.75V
2.75V
2.76V
2.76V
2.76V
2.76V
2.77V
2.77V
2.77V
V(min)
V(max)
1.34V
1.34V
1.34V
1.34V
1.34V
1.34V
1.34V
1.36V
1.44V
1.57V
1.73V
1.92V
2.11V
2.32V
0.92V
0.92V
0.92V
0.92V
0.94V
1.07V
1.24V
1.37V
1.55V
1.76V
2.02V
2.33V
2.62V
2.91V
DSP56371 Technical Data
Freescale Semiconductor
IBIS Model
2.80nS
3.00nS
3.20nS
3.40nS
3.60nS
3.80nS
4.00nS
4.20nS
4.40nS
4.60nS
4.80nS
5.00nS
5.20nS
5.40nS
5.60nS
5.80nS
6.00nS
6.20nS
6.40nS
6.60nS
6.80nS
7.00nS
7.20nS
7.40nS
7.60nS
7.80nS
8.00nS
8.20nS
8.40nS
8.60nS
8.80nS
9.00nS
9.20nS
9.40nS
9.60nS
9.80nS
10.00nS
2.97V
3.09V
3.15V
3.20V
3.24V
3.26V
3.28V
3.29V
3.29V
3.30V
3.30V
3.30V
3.30V
3.30V
3.30V
3.30V
3.30V
3.30V
3.30V
3.30V
3.30V
3.30V
3.30V
3.30V
3.30V
3.30V
3.30V
3.30V
3.30V
3.30V
3.30V
3.30V
3.30V
3.30V
3.30V
3.30V
3.30V
|
[Falling Waveform]
R_fixture = 50.00
V_fixture = 0.000
V_fixture_min = 0.000
V_fixture_max = 0.000
L_fixture = 0.000H
C_fixture = 0.000F
| time
V(typ)
|
0.000S
2.41V
0.20nS
2.41V
0.40nS
2.41V
0.60nS
2.41V
Freescale Semiconductor
2.55V
2.69V
2.76V
2.86V
2.92V
2.95V
2.98V
2.99V
2.99V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.20V
3.33V
3.39V
3.44V
3.50V
3.53V
3.55V
3.57V
3.59V
3.59V
3.59V
3.60V
3.60V
3.60V
3.60V
3.60V
3.60V
3.60V
3.60V
3.60V
3.60V
3.60V
3.60V
3.60V
3.60V
3.60V
3.60V
3.60V
3.60V
3.60V
3.60V
3.60V
3.60V
3.60V
3.60V
3.60V
3.60V
V(min)
V(max)
1.87V
1.87V
1.87V
1.87V
2.79V
2.79V
2.79V
2.76V
DSP56371 Technical Data
87
IBIS Model
0.80nS
1.00nS
1.20nS
1.40nS
1.60nS
1.80nS
2.00nS
2.20nS
2.40nS
2.60nS
2.80nS
3.00nS
3.20nS
3.40nS
3.60nS
3.80nS
4.00nS
4.20nS
4.40nS
4.60nS
4.80nS
5.00nS
5.20nS
5.40nS
5.60nS
5.80nS
6.00nS
6.20nS
6.40nS
6.60nS
6.80nS
7.00nS
7.20nS
7.40nS
7.60nS
7.80nS
8.00nS
8.20nS
8.40nS
8.60nS
8.80nS
9.00nS
9.20nS
9.40nS
9.60nS
9.80nS
10.00nS
2.37V
2.24V
2.07V
1.94V
1.76V
1.54V
1.28V
1.01V
0.78V
0.61V
0.46V
0.37V
0.33V
0.26V
0.21V
0.17V
0.14V
0.10V
73.29mV
60.19mV
48.89mV
34.23mV
24.65mV
14.47mV
8.10mV
5.49mV
3.06mV
1.82mV
1.09mV
0.61mV
0.54mV
0.47mV
0.42mV
0.35mV
0.31mV
0.29mV
0.27mV
0.24mV
0.20mV
0.18mV
0.18mV
0.17mV
0.15mV
0.12mV
0.10mV
0.11mV
0.11mV
1.87V
1.86V
1.85V
1.82V
1.75V
1.65V
1.51V
1.36V
1.18V
0.99V
0.76V
0.59V
0.49V
0.39V
0.31V
0.25V
0.19V
0.15V
0.10V
87.46mV
70.67mV
50.83mV
38.23mV
23.57mV
14.65mV
9.93mV
6.30mV
4.27mV
2.24mV
1.46mV
1.08mV
0.78mV
0.69mV
0.59mV
0.52mV
0.48mV
0.45mV
0.40mV
0.35mV
0.32mV
0.31mV
0.28mV
0.24mV
0.20mV
0.19mV
0.20mV
0.17mV
2.62V
2.44V
2.25V
2.10V
1.85V
1.55V
1.23V
0.96V
0.77V
0.63V
0.51V
0.43V
0.37V
0.32V
0.27V
0.22V
0.19V
0.14V
0.11V
93.57mV
8.29mV
61.98mV
46.06mV
32.51mV
20.47mV
15.65mV
11.70mV
6.64mV
4.15mV
2.31mV
1.05mV
0.76mV
0.48mV
0.37mV
0.31mV
0.29mV
0.26mV
0.24mV
0.21mV
0.18mV
0.16mV
0.16mV
0.15mV
0.12mV
93.74uV
90.71uV
97.83uV
|
[Falling Waveform]
R_fixture = 50.00
V_fixture = 3.30
88
DSP56371 Technical Data
Freescale Semiconductor
IBIS Model
V_fixture_min = 3.00
V_fixture_max = 3.60
L_fixture = 0.000H
C_fixture = 0.000F
| time
V(typ)
|
0.000S
3.30V
0.20nS
3.30V
0.40nS
3.30V
0.60nS
3.30V
0.80nS
3.30V
1.00nS
3.25V
1.20nS
3.17V
1.40nS
3.12V
1.60nS
3.05V
1.80nS
2.97V
2.00nS
2.87V
2.20nS
2.78V
2.40nS
2.68V
2.60nS
2.58V
2.80nS
2.45V
3.00nS
2.34V
3.20nS
2.26V
3.40nS
2.17V
3.60nS
2.07V
3.80nS
1.98V
4.00nS
1.89V
4.20nS
1.76V
4.40nS
1.63V
4.60nS
1.55V
4.80nS
1.48V
5.00nS
1.40V
5.20nS
1.32V
5.40nS
1.25V
5.60nS
1.19V
5.80nS
1.15V
6.00nS
1.13V
6.20nS
1.10V
6.40nS
1.07V
6.60nS
1.05V
6.80nS
1.03V
7.00nS
1.02V
7.20nS
1.01V
7.40nS
1.00V
7.60nS
1.00V
7.80nS
1.00V
8.00nS
1.00V
8.20nS
0.99V
8.40nS
0.99V
8.60nS
0.99V
8.80nS
0.99V
Freescale Semiconductor
V(min)
V(max)
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
2.97V
2.92V
2.87V
2.82V
2.76V
2.69V
2.62V
2.57V
2.50V
2.44V
2.38V
2.32V
2.25V
2.18V
2.15V
2.11V
2.06V
2.01V
1.96V
1.92V
1.89V
1.87V
1.84V
1.81V
1.78V
1.75V
1.72V
1.70V
1.67V
1.64V
1.62V
1.60V
1.57V
1.53V
1.50V
1.47V
3.60V
3.60V
3.60V
3.59V
3.52V
3.43V
3.34V
3.27V
3.17V
3.06V
2.95V
2.83V
2.70V
2.58V
2.43V
2.30V
2.21V
2.07V
1.91V
1.76V
1.62V
1.49V
1.37V
1.32V
1.27V
1.21V
1.16V
1.10V
1.06V
1.04V
1.02V
1.00V
0.98V
0.96V
0.95V
0.94V
0.93V
0.93V
0.92V
0.92V
0.92V
0.92V
0.92V
0.92V
0.92V
DSP56371 Technical Data
89
IBIS Model
9.00nS
9.20nS
9.40nS
9.60nS
9.80nS
10.00nS
0.99V
0.99V
0.99V
0.99V
0.99V
0.99V
1.44V
1.42V
1.40V
1.38V
1.37V
1.36V
0.92V
0.92V
0.92V
0.92V
0.92V
0.92V
|
| End [Model] prd16dgz
|
|************************************************************************
|
Model prd24dgz
|************************************************************************
|
[Model]
prd24dgz
Model_type
I/O
Polarity
Non-Inverting
Enable
Active-Low
Vinl = 0.80V
Vinh = 2.00V
Vmeas = 1.50V
Cref = 50.00pF
Rref = 1.00M
Vref = 0.000V
C_comp
4.15pF
3.73pF
4.56pF
|
|
[Temperature Range]
25.00
0.12k
0.000
[Pullup Reference]
3.30V
3.00V
3.60V
[Pulldown Reference]
0.000V
0.000V
0.000V
[POWER Clamp Reference] 5.00V
4.50V
5.50V
[GND Clamp Reference]
0.000V
0.000V
0.000V
[Pulldown]
| voltage
I(typ)
I(min)
I(max)
|
-3.30
-10.00mA
0.000A
0.000A
-3.10
0.000A
0.000A
-10.00mA
-2.90
0.000A
0.000A
0.000A
-2.70
0.000A
0.000A
0.000A
-2.50
0.000A
0.000A
0.000A
-2.30
0.000A
0.000A
-10.00mA
-2.10
-10.00mA
0.000A
-10.00mA
-1.90
-10.00mA
0.000A
-10.00mA
-1.70
-10.00mA
-10.00mA
-10.00mA
-1.50
-10.00mA
-10.00mA
-20.00mA
-1.00
-19.00mA
-10.00mA
-23.00mA
-0.90
-21.00mA
-10.00mA
-26.00mA
-0.80
-41.70mA
-11.00mA
-55.33mA
-0.70
-50.61mA
-14.60mA
-55.12mA
-0.60
-46.07mA
-25.10mA
-50.21mA
-0.50
-39.45mA
-26.37mA
-43.90mA
-0.40
-32.03mA
-22.06mA
-36.08mA
90
DSP56371 Technical Data
Freescale Semiconductor
IBIS Model
-0.30
-0.20
-0.10
-0.00
0.10
0.20
0.30
0.40
0.50
0.60
0.70
0.80
0.90
1.00
1.10
1.20
1.30
1.40
1.50
1.60
1.70
1.80
1.90
2.00
2.10
2.20
2.30
2.40
2.50
2.60
2.70
2.80
2.90
3.00
3.10
3.20
3.30
3.40
3.50
3.60
3.70
3.80
3.90
4.00
4.10
4.20
4.30
4.50
4.70
4.90
5.10
-24.29mA
-16.36mA
-8.26mA
3.80nA
8.11mA
15.76mA
22.98mA
29.76mA
36.11mA
42.04mA
47.55mA
52.66mA
57.35mA
61.65mA
65.55mA
69.06mA
72.19mA
74.94mA
77.32mA
79.33mA
80.95mA
82.19mA
83.09mA
83.74mA
84.23mA
84.62mA
84.93mA
85.20mA
85.44mA
85.65mA
85.84mA
86.01mA
86.18mA
86.33mA
86.48mA
86.62mA
86.75mA
86.89mA
87.06mA
87.16mA
87.30mA
87.47mA
87.77mA
88.66mA
90.00mA
91.34mA
89.39mA
89.66mA
90.64mA
91.94mA
93.66mA
Freescale Semiconductor
-16.63mA
-11.11mA
-5.55mA
7.33nA
5.36mA
10.37mA
15.05mA
19.40mA
23.42mA
27.12mA
30.50mA
33.58mA
36.36mA
38.84mA
41.04mA
42.96mA
44.61mA
45.99mA
47.12mA
48.01mA
48.68mA
49.17mA
49.54mA
49.83mA
50.06mA
50.25mA
50.42mA
50.57mA
50.70mA
50.82mA
50.93mA
51.03mA
51.13mA
51.22mA
51.31mA
51.40mA
51.50mA
51.73mA
52.32mA
53.14mA
54.02mA
54.48mA
52.16mA
52.28mA
52.42mA
52.58mA
52.77mA
53.24mA
53.86mA
54.68mA
55.73mA
-27.48mA
-18.57mA
-9.40mA
12.06nA
9.30mA
18.18mA
26.64mA
34.69mA
42.32mA
49.54mA
56.36mA
62.78mA
68.80mA
74.42mA
79.65mA
84.48mA
88.92mA
92.97mA
96.63mA
99.91mA
0.10A
0.11A
0.11A
0.11A
0.11A
0.11A
0.11A
0.11A
0.11A
0.11A
0.11A
0.11A
0.11A
0.11A
0.11A
0.11A
0.11A
0.12A
0.12A
0.12A
0.12A
0.12A
0.12A
0.12A
0.12A
0.12A
0.12A
0.12A
0.12A
0.12A
0.12A
DSP56371 Technical Data
91
IBIS Model
5.30
5.50
5.70
5.90
6.10
6.60
|
[Pullup]
| voltage
|
-3.30
-3.10
-2.90
-2.70
-2.50
-2.30
-2.10
-1.90
-1.70
-1.50
-1.00
-0.90
-0.80
-0.70
-0.60
-0.50
-0.40
-0.30
-0.20
-0.10
0.00
0.10
0.20
0.30
0.40
0.50
0.60
0.70
0.80
0.90
1.00
1.10
1.20
1.30
1.40
1.50
1.60
1.70
1.80
1.90
2.00
92
95.77mA
98.33mA
0.10A
0.10A
0.11A
0.12A
57.03mA
58.59mA
60.44mA
62.55mA
64.93mA
71.83mA
0.13A
0.13A
0.13A
0.14A
0.14A
0.15A
I(typ)
I(min)
I(max)
0.22A
0.21A
0.20A
0.19A
0.18A
0.17A
0.16A
0.15A
0.14A
0.12A
92.80mA
84.30mA
75.06mA
65.63mA
56.31mA
47.22mA
38.00mA
28.62mA
19.12mA
9.57mA
34.08uA
-9.20mA
-17.92mA
-26.12mA
-33.83mA
-41.04mA
-47.76mA
-54.01mA
-59.78mA
-65.10mA
-69.96mA
-74.37mA
-78.35mA
-81.89mA
-85.01mA
-87.72mA
-90.01mA
-91.93mA
-93.48mA
-94.74mA
-95.77mA
0.16A
0.16A
0.15A
0.14A
0.14A
0.13A
0.12A
0.11A
0.10A
90.15mA
62.50mA
57.02mA
54.41mA
47.70mA
40.65mA
33.53mA
26.51mA
19.71mA
13.04mA
6.46mA
11.19uA
-6.16mA
-11.98mA
-17.45mA
-22.56mA
-27.33mA
-31.76mA
-35.85mA
-39.61mA
-43.04mA
-46.14mA
-48.91mA
-51.37mA
-53.51mA
-55.34mA
-56.87mA
-58.11mA
-59.08mA
-59.83mA
-60.42mA
-60.91mA
0.25A
0.24A
0.23A
0.22A
0.21A
0.20A
0.19A
0.17A
0.16A
0.14A
0.11A
97.94mA
87.24mA
76.50mA
66.14mA
55.68mA
44.96mA
34.00mA
22.83mA
11.50mA
71.92uA
-11.08mA
-21.68mA
-31.71mA
-41.21mA
-50.17mA
-58.60mA
-66.51mA
-73.91mA
-80.81mA
-87.22mA
-93.14mA
-98.58mA
-0.10A
-0.11A
-0.11A
-0.12A
-0.12A
-0.12A
-0.12A
-0.13A
DSP56371 Technical Data
Freescale Semiconductor
IBIS Model
2.10
2.20
2.30
2.40
2.50
2.60
2.70
2.80
2.90
3.00
3.10
3.20
3.30
3.40
3.50
3.60
3.70
3.80
3.90
4.00
4.10
4.20
4.30
4.50
4.70
4.90
5.10
5.30
5.50
5.70
5.90
6.10
6.60
|
[GND_clamp]
| voltage
|
-5.00
-4.80
-4.60
-4.40
-4.20
-4.00
-3.80
-3.60
-3.40
-3.20
-3.00
-2.80
-2.60
-2.40
-96.63mA
-97.36mA
-97.99mA
-98.55mA
-99.04mA
-99.49mA
-99.89mA
-0.10A
-0.10A
-0.10A
-0.10A
-0.10A
-0.10A
-0.10A
-0.10A
-0.10A
-0.10A
-0.10A
-0.11A
-0.12A
-0.34A
-1.90A
-3.94A
-8.02A
-12.10A
-16.18A
-20.27A
-24.35A
-28.43A
-32.51A
-36.60A
-40.68A
-50.89A
-61.34mA
-61.71mA
-62.05mA
-62.36mA
-62.64mA
-62.90mA
-63.14mA
-63.36mA
-63.57mA
-63.78mA
-63.97mA
-64.15mA
-64.35mA
-64.99mA
-72.69mA
-0.17A
-0.97A
-2.72A
-4.50A
-6.28A
-8.06A
-9.85A
-11.62A
-15.19A
-18.75A
-22.31A
-25.88A
-29.44A
-33.00A
-36.56A
-40.13A
-43.69A
-52.59A
-0.13A
-0.13A
-0.13A
-0.13A
-0.13A
-0.13A
-0.13A
-0.13A
-0.13A
-0.13A
-0.14A
-0.14A
-0.14A
-0.14A
-0.14A
-0.14A
-0.14A
-0.14A
-0.14A
-0.14A
-0.14A
-0.14A
-0.15A
-1.21A
-5.43A
-9.67A
-13.90A
-18.14A
-22.38A
-26.62A
-30.86A
-35.09A
-45.69A
I(typ)
I(min)
I(max)
-85.26A
-81.20A
-77.14A
-73.08A
-69.02A
-64.96A
-60.90A
-56.84A
-52.78A
-48.72A
-44.64A
-40.56A
-36.48A
-32.40A
-77.43A
-73.87A
-70.31A
-66.75A
-63.19A
-59.63A
-56.07A
-52.51A
-48.95A
-45.39A
-41.83A
-38.27A
-34.71A
-31.15A
-87.91A
-83.67A
-79.43A
-75.19A
-70.95A
-66.71A
-62.47A
-58.23A
-53.99A
-49.75A
-45.52A
-41.29A
-37.05A
-32.82A
Freescale Semiconductor
DSP56371 Technical Data
93
IBIS Model
-2.20
-2.00
-1.80
-1.60
-1.40
-1.20
-1.00
-0.80
-0.60
-0.40
-0.20
-0.00
0.20
0.40
0.60
0.80
1.00
1.20
1.40
1.60
1.80
2.00
2.20
2.40
2.60
2.80
3.00
3.20
3.40
3.60
3.80
4.00
4.20
4.40
4.60
4.80
5.00
-28.32A
-24.24A
-20.16A
-16.08A
-12.00A
-7.92A
-3.84A
-0.23A
-2.33mA
-91.55uA
-27.91uA
-75.80nA
18.72uA
29.20uA
32.50uA
33.08uA
33.30uA
33.45uA
33.57uA
33.68uA
33.78uA
33.87uA
33.96uA
34.01uA
34.03uA
34.04uA
34.05uA
34.06uA
34.08uA
34.10uA
34.12uA
34.14uA
34.16uA
34.18uA
34.20uA
34.22uA
34.24uA
|
[POWER_clamp]
| voltage
I(typ)
|
-5.00
48.55uA
-4.90
48.22uA
-4.80
47.89uA
-4.70
47.56uA
-4.60
47.23uA
-4.50
46.90uA
-4.40
46.57uA
-4.30
46.24uA
-4.20
45.91uA
-4.10
45.58uA
94
-27.59A
-24.03A
-20.47A
-16.90A
-13.34A
-9.78A
-6.22A
-2.66A
-0.10A
-0.52mA
-14.70uA
-77.03nA
7.32uA
10.26uA
10.68uA
10.79uA
10.86uA
10.92uA
10.98uA
11.03uA
11.07uA
11.11uA
11.14uA
11.15uA
11.16uA
11.17uA
11.18uA
11.75uA
10.69uA
9.63uA
8.57uA
7.51uA
6.45uA
5.39uA
4.33uA
3.27uA
2.21uA
-28.58A
-24.35A
-20.11A
-15.88A
-11.64A
-7.41A
-3.18A
-71.67mA
-6.23mA
-0.28mA
-42.94uA
-90.19nA
32.29uA
54.13uA
65.79uA
69.34uA
70.18uA
70.55uA
70.80uA
71.00uA
71.16uA
71.32uA
71.47uA
71.61uA
71.76uA
71.84uA
71.86uA
71.88uA
71.90uA
71.92uA
71.94uA
71.96uA
71.98uA
72.00uA
72.02uA
72.04uA
72.06uA
I(min)
I(max)
16.31uA
16.19uA
16.07uA
15.95uA
15.83uA
15.71uA
15.59uA
15.47uA
15.35uA
15.23uA
95.55uA
95.05uA
94.55uA
94.05uA
93.55uA
93.05uA
92.55uA
92.05uA
91.55uA
91.05uA
DSP56371 Technical Data
Freescale Semiconductor
IBIS Model
-4.00
-3.90
-3.80
-3.70
-3.60
-3.50
-3.40
-3.30
-3.20
-3.10
-3.00
-2.90
-2.80
-2.70
-2.60
-2.50
-2.40
-2.30
-2.20
-2.10
-2.00
-1.90
-1.80
-1.70
-1.60
-1.50
-1.40
-1.30
-1.20
-1.10
-1.00
-0.90
-0.80
-0.70
-0.60
-0.50
-0.40
-0.30
-0.20
-0.10
0.00
45.25uA
44.92uA
44.59uA
44.26uA
43.93uA
43.60uA
43.27uA
42.94uA
42.61uA
42.28uA
41.95uA
41.62uA
41.29uA
40.96uA
40.63uA
40.30uA
39.97uA
39.64uA
39.31uA
38.98uA
38.65uA
38.32uA
37.99uA
37.66uA
37.33uA
37.00uA
36.69uA
36.40uA
36.13uA
35.88uA
35.64uA
35.43uA
35.24uA
35.07uA
34.92uA
34.79uA
34.67uA
34.57uA
34.49uA
34.42uA
34.36uA
|
[Ramp]
| variable
typ
dV/dt_r
1.54/2.22n
dV/dt_f
1.52/3.16n
R_load = 50.00
|
[Rising Waveform]
R_fixture = 50.00
V_fixture = 0.000
Freescale Semiconductor
15.11uA
14.99uA
14.87uA
14.75uA
14.63uA
14.51uA
14.39uA
14.27uA
14.15uA
14.03uA
13.91uA
13.79uA
13.67uA
13.55uA
13.43uA
13.31uA
13.19uA
13.07uA
12.95uA
12.83uA
12.71uA
12.59uA
12.47uA
12.35uA
12.23uA
12.13uA
12.03uA
11.94uA
11.85uA
11.78uA
11.71uA
11.64uA
11.59uA
11.54uA
11.49uA
11.45uA
11.42uA
11.39uA
11.37uA
11.35uA
11.33uA
90.55uA
90.05uA
89.55uA
89.05uA
88.55uA
88.05uA
87.55uA
87.05uA
86.55uA
86.05uA
85.55uA
85.05uA
84.55uA
84.05uA
83.55uA
83.05uA
82.55uA
82.05uA
81.55uA
81.05uA
80.55uA
80.05uA
79.55uA
79.05uA
78.55uA
78.05uA
77.55uA
77.05uA
76.55uA
76.05uA
75.55uA
75.08uA
74.65uA
74.26uA
73.91uA
73.60uA
73.32uA
73.08uA
72.88uA
72.70uA
72.56uA
min
1.20/2.88n
1.15/4.46n
max
1.77/2.15n
1.73/3.00n
DSP56371 Technical Data
95
IBIS Model
V_fixture_min = 0.000
V_fixture_max = 0.000
L_fixture = 0.000H
C_fixture = 0.000F
| time
V(typ)
|
0.000S
0.70uV
0.20nS
0.45uV
0.40nS
-5.49uV
0.60nS
-0.25mV
0.80nS
-2.88mV
1.00nS
-3.85mV
1.20nS
18.80mV
1.40nS
45.63mV
1.60nS
80.05mV
1.80nS
0.11V
2.00nS
0.16V
2.20nS
0.20V
2.40nS
0.26V
2.60nS
0.32V
2.80nS
0.41V
3.00nS
0.51V
3.20nS
0.58V
3.40nS
0.71V
3.60nS
0.85V
3.80nS
1.00V
4.00nS
1.17V
4.20nS
1.38V
4.40nS
1.57V
4.60nS
1.68V
4.80nS
1.78V
5.00nS
1.91V
5.20nS
2.01V
5.40nS
2.13V
5.60nS
2.22V
5.80nS
2.27V
6.00nS
2.31V
6.20nS
2.35V
6.40nS
2.38V
6.60nS
2.41V
6.80nS
2.43V
7.00nS
2.45V
7.20nS
2.46V
7.40nS
2.48V
7.60nS
2.49V
7.80nS
2.50V
8.00nS
2.51V
8.20nS
2.52V
8.40nS
2.52V
8.60nS
2.53V
8.80nS
2.54V
96
V(min)
V(max)
0.92uV
0.77uV
-1.76uV
-4.97uV
24.27uV
-5.54uV
-0.76mV
-3.09mV
-6.58mV
-0.18mV
21.52mV
48.21mV
76.15mV
0.11V
0.16V
0.19V
0.24V
0.30V
0.36V
0.45V
0.54V
0.67V
0.80V
0.88V
0.96V
1.06V
1.15V
1.25V
1.34V
1.40V
1.44V
1.50V
1.56V
1.61V
1.66V
1.70V
1.74V
1.78V
1.82V
1.84V
1.86V
1.88V
1.90V
1.92V
1.93V
0.68uV
0.000V
16.07uV
-2.66mV
-5.55mV
32.40mV
80.52mV
0.11V
0.16V
0.21V
0.27V
0.33V
0.41V
0.48V
0.61V
0.73V
0.82V
0.97V
1.16V
1.35V
1.55V
1.80V
2.03V
2.15V
2.26V
2.39V
2.51V
2.61V
2.70V
2.74V
2.77V
2.80V
2.82V
2.84V
2.86V
2.87V
2.88V
2.89V
2.90V
2.91V
2.91V
2.92V
2.92V
2.92V
2.93V
DSP56371 Technical Data
Freescale Semiconductor
IBIS Model
9.00nS
9.20nS
9.40nS
9.60nS
9.80nS
10.00nS
2.54V
2.55V
2.55V
2.56V
2.56V
2.57V
|
[Rising Waveform]
R_fixture = 50.00
V_fixture = 3.30
V_fixture_min = 3.00
V_fixture_max = 3.60
L_fixture = 0.000H
C_fixture = 0.000F
| time
V(typ)
|
0.000S
0.76V
0.20nS
0.76V
0.40nS
0.76V
0.60nS
0.76V
0.80nS
0.77V
1.00nS
0.81V
1.20nS
0.90V
1.40nS
0.98V
1.60nS
1.09V
1.80nS
1.22V
2.00nS
1.35V
2.20nS
1.51V
2.40nS
1.69V
2.60nS
1.91V
2.80nS
2.22V
3.00nS
2.47V
3.20nS
2.65V
3.40nS
2.85V
3.60nS
2.97V
3.80nS
3.08V
4.00nS
3.14V
4.20nS
3.19V
4.40nS
3.23V
4.60nS
3.25V
4.80nS
3.27V
5.00nS
3.28V
5.20nS
3.29V
5.40nS
3.29V
5.60nS
3.30V
5.80nS
3.30V
6.00nS
3.30V
6.20nS
3.30V
6.40nS
3.30V
6.60nS
3.30V
6.80nS
3.30V
Freescale Semiconductor
1.95V
1.96V
1.97V
1.98V
2.00V
2.00V
2.93V
2.94V
2.94V
2.94V
2.95V
2.95V
V(min)
V(max)
1.03V
1.03V
1.03V
1.03V
1.03V
1.03V
1.03V
1.04V
1.11V
1.20V
1.32V
1.45V
1.59V
1.74V
1.96V
2.16V
2.31V
2.49V
2.62V
2.73V
2.83V
2.89V
2.94V
2.95V
2.97V
2.98V
2.99V
2.99V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
0.72V
0.72V
0.72V
0.72V
0.73V
0.82V
0.93V
1.01V
1.13V
1.26V
1.42V
1.58V
1.78V
2.02V
2.36V
2.63V
2.82V
3.03V
3.17V
3.30V
3.36V
3.42V
3.47V
3.50V
3.52V
3.54V
3.56V
3.57V
3.58V
3.59V
3.59V
3.59V
3.60V
3.60V
3.60V
DSP56371 Technical Data
97
IBIS Model
7.00nS
7.20nS
7.40nS
7.60nS
7.80nS
8.00nS
8.20nS
8.40nS
8.60nS
8.80nS
9.00nS
9.20nS
9.40nS
9.60nS
9.80nS
10.00nS
3.30V
3.30V
3.30V
3.30V
3.30V
3.30V
3.30V
3.30V
3.30V
3.30V
3.30V
3.30V
3.30V
3.30V
3.30V
3.30V
|
[Falling Waveform]
R_fixture = 50.00
V_fixture = 0.000
V_fixture_min = 0.000
V_fixture_max = 0.000
L_fixture = 0.000H
C_fixture = 0.000F
| time
V(typ)
|
0.000S
2.62V
0.20nS
2.62V
0.40nS
2.62V
0.60nS
2.62V
0.80nS
2.60V
1.00nS
2.50V
1.20nS
2.38V
1.40nS
2.29V
1.60nS
2.17V
1.80nS
2.04V
2.00nS
1.89V
2.20nS
1.71V
2.40nS
1.51V
2.60nS
1.27V
2.80nS
0.99V
3.00nS
0.81V
3.20nS
0.71V
3.40nS
0.59V
3.60nS
0.51V
3.80nS
0.44V
4.00nS
0.37V
4.20nS
0.31V
4.40nS
0.26V
4.60nS
0.23V
4.80nS
0.20V
98
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.60V
3.60V
3.60V
3.60V
3.60V
3.60V
3.60V
3.60V
3.60V
3.60V
3.60V
3.60V
3.60V
3.60V
3.60V
3.60V
V(min)
V(max)
2.12V
2.12V
2.12V
2.12V
2.12V
2.12V
2.11V
2.09V
2.04V
1.96V
1.85V
1.74V
1.63V
1.50V
1.33V
1.17V
1.04V
0.87V
0.72V
0.59V
0.49V
0.40V
0.33V
0.28V
0.25V
2.99V
2.99V
2.99V
2.96V
2.85V
2.72V
2.59V
2.50V
2.36V
2.20V
2.00V
1.76V
1.49V
1.23V
0.98V
0.83V
0.75V
0.66V
0.57V
0.50V
0.45V
0.38V
0.32V
0.29V
0.26V
DSP56371 Technical Data
Freescale Semiconductor
IBIS Model
5.00nS
5.20nS
5.40nS
5.60nS
5.80nS
6.00nS
6.20nS
6.40nS
6.60nS
6.80nS
7.00nS
7.20nS
7.40nS
7.60nS
7.80nS
8.00nS
8.20nS
8.40nS
8.60nS
8.80nS
9.00nS
9.20nS
9.40nS
9.60nS
9.80nS
10.00nS
0.17V
0.15V
0.12V
92.71mV
79.46mV
67.17mV
54.74mV
42.77mV
33.26mV
25.46mV
18.21mV
13.43mV
8.06mV
4.81mV
3.27mV
1.98mV
1.32mV
0.78mV
0.50mV
0.42mV
0.34mV
0.30mV
0.27mV
0.24mV
0.21mV
0.22mV
|
[Falling Waveform]
R_fixture = 50.00
V_fixture = 3.30
V_fixture_min = 3.00
V_fixture_max = 3.60
L_fixture = 0.000H
C_fixture = 0.000F
| time
V(typ)
|
0.000S
3.30V
0.20nS
3.30V
0.40nS
3.30V
0.60nS
3.30V
0.80nS
3.30V
1.00nS
3.25V
1.20nS
3.18V
1.40nS
3.14V
1.60nS
3.09V
1.80nS
3.03V
2.00nS
2.96V
2.20nS
2.88V
2.40nS
2.80V
2.60nS
2.72V
2.80nS
2.61V
Freescale Semiconductor
0.21V
0.18V
0.14V
0.11V
96.17mV
83.01mV
65.86mV
53.06mV
41.31mV
31.29mV
23.99mV
16.92mV
11.32mV
6.46mV
4.82mV
3.62mV
2.10mV
1.45mV
1.01mV
0.70mV
0.61mV
0.51mV
0.45mV
0.40mV
0.35mV
0.32mV
0.23V
0.20V
0.17V
0.14V
0.12V
0.11V
89.82mV
75.55mV
61.63mV
50.25mV
40.51mV
31.37mV
23.11mV
15.54mV
12.49mV
9.63mV
6.17mV
4.24mV
2.46mV
1.45mV
0.94mV
0.50mV
0.38mV
0.28mV
0.23mV
0.21mV
V(min)
V(max)
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
2.97V
2.92V
2.88V
2.84V
2.80V
2.74V
3.60V
3.60V
3.60V
3.59V
3.52V
3.44V
3.37V
3.32V
3.24V
3.16V
3.07V
2.98V
2.88V
2.78V
2.65V
DSP56371 Technical Data
99
IBIS Model
3.00nS
3.20nS
3.40nS
3.60nS
3.80nS
4.00nS
4.20nS
4.40nS
4.60nS
4.80nS
5.00nS
5.20nS
5.40nS
5.60nS
5.80nS
6.00nS
6.20nS
6.40nS
6.60nS
6.80nS
7.00nS
7.20nS
7.40nS
7.60nS
7.80nS
8.00nS
8.20nS
8.40nS
8.60nS
8.80nS
9.00nS
9.20nS
9.40nS
9.60nS
9.80nS
10.00nS
2.51V
2.44V
2.34V
2.25V
2.15V
2.06V
1.93V
1.81V
1.73V
1.65V
1.54V
1.44V
1.32V
1.23V
1.18V
1.13V
1.08V
1.04V
1.00V
0.96V
0.93V
0.90V
0.87V
0.85V
0.83V
0.82V
0.81V
0.80V
0.79V
0.78V
0.78V
0.78V
0.77V
0.77V
0.77V
0.77V
2.68V
2.64V
2.58V
2.52V
2.46V
2.39V
2.32V
2.24V
2.20V
2.15V
2.09V
2.04V
1.97V
1.91V
1.87V
1.84V
1.79V
1.75V
1.71V
1.67V
1.63V
1.59V
1.54V
1.48V
1.44V
1.40V
1.35V
1.31V
1.27V
1.23V
1.20V
1.17V
1.15V
1.12V
1.10V
1.09V
2.55V
2.47V
2.35V
2.23V
2.09V
1.93V
1.75V
1.58V
1.50V
1.43V
1.34V
1.26V
1.18V
1.11V
1.07V
1.04V
1.00V
0.96V
0.92V
0.89V
0.87V
0.84V
0.82V
0.80V
0.78V
0.78V
0.76V
0.75V
0.75V
0.74V
0.73V
0.73V
0.73V
0.72V
0.72V
0.72V
|
| End [Model] prd24dgz
|
|************************************************************************
|
Model prt24dgz
|************************************************************************
|
[Model]
prt24dgz
Model_type
3-state
Polarity
Non-Inverting
Enable
Active-Low
Vmeas = 1.50V
Cref = 50.00pF
Rref = 1.00M
Vref = 0.000V
100
DSP56371 Technical Data
Freescale Semiconductor
IBIS Model
C_comp
4.09pF
|
|
[Temperature Range]
25.00
[Pullup Reference]
3.30V
[Pulldown Reference]
0.000V
[POWER Clamp Reference] 5.00V
[GND Clamp Reference]
0.000V
[Pulldown]
| voltage
I(typ)
I(min)
|
-3.30
-10.00mA
0.000A
-3.10
0.000A
0.000A
-2.90
0.000A
0.000A
-2.70
0.000A
0.000A
-2.50
0.000A
0.000A
-2.30
0.000A
0.000A
-2.10
-10.00mA
0.000A
-1.90
-10.00mA
0.000A
-1.70
-10.00mA
-10.00mA
-1.50
-10.00mA
-10.00mA
-1.00
-20.00mA
-10.00mA
-0.90
-21.00mA
-10.00mA
-0.80
-41.70mA
-12.00mA
-0.70
-50.60mA
-14.60mA
-0.60
-46.07mA
-25.10mA
-0.50
-39.45mA
-26.38mA
-0.40
-32.03mA
-22.06mA
-0.30
-24.30mA
-16.63mA
-0.20
-16.36mA
-11.10mA
-0.10
-8.26mA
-5.55mA
-0.00
3.97nA
7.41nA
0.10
8.11mA
5.36mA
0.20
15.76mA
10.38mA
0.30
22.98mA
15.05mA
0.40
29.76mA
19.40mA
0.50
36.11mA
23.42mA
0.60
42.04mA
27.11mA
0.70
47.55mA
30.50mA
0.80
52.65mA
33.58mA
0.90
57.35mA
36.36mA
1.00
61.64mA
38.84mA
1.10
65.54mA
41.04mA
1.20
69.06mA
42.96mA
1.30
72.18mA
44.61mA
1.40
74.93mA
45.99mA
1.50
77.31mA
47.12mA
1.60
79.32mA
48.01mA
1.70
80.95mA
48.68mA
1.80
82.19mA
49.17mA
1.90
83.08mA
49.54mA
Freescale Semiconductor
3.68pF
4.50pF
0.12k
3.00V
0.000V
4.50V
0.000V
0.000
3.60V
0.000V
5.50V
0.000V
I(max)
0.000A
-10.00mA
0.000A
0.000A
0.000A
-10.00mA
-10.00mA
-10.00mA
-10.00mA
-20.00mA
-23.00mA
-26.00mA
-55.37mA
-55.11mA
-50.21mA
-43.90mA
-36.09mA
-27.49mA
-18.57mA
-9.40mA
12.45nA
9.30mA
18.18mA
26.64mA
34.68mA
42.32mA
49.54mA
56.36mA
62.78mA
68.80mA
74.42mA
79.65mA
84.48mA
88.92mA
92.97mA
96.63mA
99.91mA
0.10A
0.11A
0.11A
DSP56371 Technical Data
101
IBIS Model
2.00
2.10
2.20
2.30
2.40
2.50
2.60
2.70
2.80
2.90
3.00
3.10
3.20
3.30
3.40
3.50
3.60
3.70
3.80
3.90
4.00
4.10
4.20
4.30
4.50
4.70
4.90
5.10
5.30
5.50
5.70
5.90
6.10
6.60
|
[Pullup]
| voltage
|
-3.30
-3.10
-2.90
-2.70
-2.50
-2.30
-2.10
-1.90
-1.70
-1.50
-1.00
-0.90
-0.80
102
83.74mA
84.23mA
84.61mA
84.93mA
85.20mA
85.43mA
85.64mA
85.83mA
86.01mA
86.17mA
86.32mA
86.47mA
86.61mA
86.75mA
86.88mA
87.01mA
87.15mA
87.30mA
87.47mA
87.77mA
88.66mA
90.00mA
91.29mA
89.03mA
89.65mA
90.63mA
91.94mA
93.62mA
95.73mA
98.29mA
0.10A
0.10A
0.11A
0.12A
49.82mA
50.06mA
50.25mA
50.42mA
50.57mA
50.70mA
50.82mA
50.93mA
51.03mA
51.13mA
51.22mA
51.31mA
51.40mA
51.50mA
51.73mA
52.32mA
53.14mA
54.01mA
54.42mA
52.16mA
52.28mA
52.42mA
52.58mA
52.77mA
53.24mA
53.86mA
54.68mA
55.72mA
57.02mA
58.58mA
60.42mA
62.54mA
64.92mA
71.81mA
0.11A
0.11A
0.11A
0.11A
0.11A
0.11A
0.11A
0.11A
0.11A
0.11A
0.11A
0.11A
0.11A
0.11A
0.12A
0.12A
0.12A
0.12A
0.12A
0.12A
0.12A
0.12A
0.12A
0.12A
0.12A
0.12A
0.12A
0.12A
0.13A
0.13A
0.13A
0.14A
0.14A
0.15A
I(typ)
I(min)
I(max)
0.22A
0.21A
0.20A
0.19A
0.18A
0.17A
0.16A
0.15A
0.14A
0.12A
92.59mA
84.26mA
75.03mA
0.16A
0.16A
0.15A
0.14A
0.14A
0.13A
0.12A
0.11A
0.10A
90.13mA
62.48mA
56.95mA
54.36mA
0.25A
0.24A
0.23A
0.22A
0.21A
0.20A
0.18A
0.17A
0.16A
0.14A
0.11A
97.88mA
87.19mA
DSP56371 Technical Data
Freescale Semiconductor
IBIS Model
-0.70
-0.60
-0.50
-0.40
-0.30
-0.20
-0.10
0.00
0.10
0.20
0.30
0.40
0.50
0.60
0.70
0.80
0.90
1.00
1.10
1.20
1.30
1.40
1.50
1.60
1.70
1.80
1.90
2.00
2.10
2.20
2.30
2.40
2.50
2.60
2.70
2.80
2.90
3.00
3.10
3.20
3.30
3.40
3.50
3.60
3.70
3.80
3.90
4.00
4.10
4.20
4.30
65.60mA
56.28mA
47.19mA
37.96mA
28.58mA
19.09mA
9.54mA
0.17uA
-9.23mA
-17.95mA
-26.16mA
-33.86mA
-41.07mA
-47.79mA
-54.04mA
-59.82mA
-65.13mA
-69.99mA
-74.41mA
-78.38mA
-81.93mA
-85.05mA
-87.75mA
-90.05mA
-91.96mA
-93.52mA
-94.78mA
-95.80mA
-96.66mA
-97.39mA
-98.03mA
-98.58mA
-99.08mA
-99.52mA
-99.92mA
-0.10A
-0.10A
-0.10A
-0.10A
-0.10A
-0.10A
-0.10A
-0.10A
-0.10A
-0.10A
-0.10A
-0.11A
-0.12A
-0.34A
-1.90A
-3.94A
Freescale Semiconductor
47.69mA
40.63mA
33.52mA
26.49mA
19.70mA
13.03mA
6.45mA
0.16uA
-6.17mA
-11.99mA
-17.46mA
-22.57mA
-27.35mA
-31.77mA
-35.86mA
-39.62mA
-43.05mA
-46.15mA
-48.92mA
-51.38mA
-53.52mA
-55.36mA
-56.88mA
-58.12mA
-59.09mA
-59.84mA
-60.43mA
-60.92mA
-61.35mA
-61.72mA
-62.06mA
-62.37mA
-62.65mA
-62.91mA
-63.15mA
-63.37mA
-63.58mA
-63.78mA
-63.96mA
-64.14mA
-64.33mA
-64.95mA
-72.61mA
-0.17A
-0.97A
-2.72A
-4.50A
-6.28A
-8.06A
-9.85A
-11.62A
76.45mA
66.08mA
55.62mA
44.89mA
33.93mA
22.76mA
11.43mA
0.19uA
-11.15mA
-21.75mA
-31.79mA
-41.28mA
-50.24mA
-58.67mA
-66.58mA
-73.98mA
-80.88mA
-87.29mA
-93.21mA
-98.65mA
-0.10A
-0.11A
-0.11A
-0.12A
-0.12A
-0.12A
-0.12A
-0.13A
-0.13A
-0.13A
-0.13A
-0.13A
-0.13A
-0.13A
-0.13A
-0.13A
-0.13A
-0.13A
-0.14A
-0.14A
-0.14A
-0.14A
-0.14A
-0.14A
-0.14A
-0.14A
-0.14A
-0.14A
-0.14A
-0.14A
-0.15A
DSP56371 Technical Data
103
IBIS Model
4.50
4.70
4.90
5.10
5.30
5.50
5.70
5.90
6.10
6.60
|
[GND_clamp]
| voltage
|
-3.30
-3.20
-3.10
-3.00
-2.90
-2.80
-2.70
-2.60
-2.50
-2.40
-2.30
-2.20
-2.10
-2.00
-1.90
-1.80
-1.70
-1.60
-1.50
-1.40
-1.30
-1.20
-1.10
-1.00
-0.90
-0.80
-0.70
-0.60
-0.50
-0.40
-0.30
-0.20
-0.10
-0.00
0.10
0.20
0.30
104
-8.02A
-12.10A
-16.18A
-20.27A
-24.35A
-28.43A
-32.51A
-36.60A
-40.68A
-50.89A
-15.19A
-18.75A
-22.31A
-25.88A
-29.44A
-33.00A
-36.56A
-40.13A
-43.69A
-52.59A
-1.20A
-5.43A
-9.67A
-13.90A
-18.14A
-22.38A
-26.62A
-30.86A
-35.09A
-45.69A
I(typ)
I(min)
I(max)
-50.75A
-48.72A
-46.68A
-44.64A
-42.60A
-40.56A
-38.52A
-36.48A
-34.44A
-32.40A
-30.36A
-28.32A
-26.28A
-24.24A
-22.20A
-20.16A
-18.12A
-16.08A
-14.04A
-12.00A
-9.96A
-7.92A
-5.88A
-3.84A
-1.80A
-0.23A
-13.26mA
-2.23mA
-0.34mA
-28.68uA
-1.65uA
-0.15uA
-86.50nA
-76.61nA
-68.52nA
-60.47nA
-52.43nA
-47.17A
-45.39A
-43.61A
-41.83A
-40.05A
-38.27A
-36.49A
-34.71A
-32.93A
-31.15A
-29.37A
-27.59A
-25.81A
-24.03A
-22.25A
-20.47A
-18.68A
-16.90A
-15.12A
-13.34A
-11.56A
-9.78A
-8.00A
-6.22A
-4.44A
-2.65A
-0.90A
-0.10A
-7.99mA
-0.48mA
-27.22uA
-1.61uA
-0.17uA
-77.36nA
-64.82nA
-56.49nA
-48.39nA
-51.87A
-49.75A
-47.63A
-45.52A
-43.40A
-41.29A
-39.17A
-37.05A
-34.94A
-32.82A
-30.70A
-28.58A
-26.47A
-24.35A
-22.23A
-20.11A
-18.00A
-15.88A
-13.76A
-11.64A
-9.53A
-7.41A
-5.29A
-3.18A
-1.07A
-71.53mA
-13.93mA
-6.08mA
-1.62mA
-0.18mA
-10.18uA
-0.42uA
-0.11uA
-91.73nA
-83.30nA
-75.01nA
-66.73nA
DSP56371 Technical Data
Freescale Semiconductor
IBIS Model
0.40
0.50
0.60
0.70
0.80
0.90
1.00
1.10
1.20
1.30
1.40
1.50
1.60
1.70
1.80
1.90
2.00
2.10
2.20
2.30
2.40
2.50
2.60
2.70
2.80
2.90
3.00
3.10
3.20
3.30
-44.39nA
-36.35nA
-28.31nA
-20.27nA
-12.24nA
-4.20nA
3.83nA
11.86nA
19.89nA
27.92nA
35.95nA
43.98nA
52.00nA
60.02nA
68.04nA
76.05nA
84.05nA
92.04nA
100.00nA
0.11uA
0.12uA
0.12uA
0.13uA
0.13uA
0.14uA
0.14uA
0.15uA
0.15uA
0.15uA
0.16uA
|
[POWER_clamp]
| voltage
I(typ)
|
-3.30
0.37uA
-3.20
0.37uA
-3.10
0.36uA
-3.00
0.35uA
-2.90
0.35uA
-2.80
0.34uA
-2.70
0.33uA
-2.60
0.33uA
-2.50
0.32uA
-2.40
0.32uA
-2.30
0.31uA
-2.20
0.30uA
-2.10
0.30uA
-2.00
0.29uA
-1.90
0.28uA
-1.80
0.28uA
-1.70
0.27uA
Freescale Semiconductor
-40.30nA
-32.21nA
-24.12nA
-16.03nA
-7.94nA
0.15nA
8.23nA
16.32nA
24.41nA
32.50nA
40.59nA
48.68nA
56.77nA
64.85nA
72.94nA
81.03nA
89.12nA
97.20nA
0.11uA
0.11uA
0.12uA
0.12uA
0.13uA
0.13uA
0.13uA
0.14uA
0.15uA
0.17uA
0.56uA
0.19uA
-58.46nA
-50.19nA
-41.93nA
-33.68nA
-25.42nA
-17.17nA
-8.92nA
-0.67nA
7.58nA
15.84nA
24.10nA
32.36nA
40.64nA
48.92nA
57.21nA
65.52nA
73.85nA
82.20nA
90.59nA
99.01nA
0.11uA
0.12uA
0.12uA
0.13uA
0.14uA
0.15uA
0.15uA
0.16uA
0.16uA
0.17uA
I(min)
I(max)
0.37uA
0.36uA
0.36uA
0.35uA
0.34uA
0.34uA
0.33uA
0.33uA
0.32uA
0.31uA
0.31uA
0.30uA
0.29uA
0.29uA
0.28uA
0.28uA
0.27uA
0.40uA
0.39uA
0.39uA
0.38uA
0.37uA
0.37uA
0.36uA
0.36uA
0.35uA
0.34uA
0.34uA
0.33uA
0.32uA
0.32uA
0.31uA
0.30uA
0.30uA
DSP56371 Technical Data
105
IBIS Model
-1.60
-1.50
-1.40
-1.30
-1.20
-1.10
-1.00
-0.90
-0.80
-0.70
-0.60
-0.50
-0.40
-0.30
-0.20
-0.10
0.00
0.27uA
0.26uA
0.25uA
0.25uA
0.24uA
0.24uA
0.23uA
0.22uA
0.22uA
0.21uA
0.21uA
0.20uA
0.20uA
0.19uA
0.48mA
0.16uA
0.16uA
|
[Ramp]
| variable
typ
dV/dt_r
1.54/2.19n
dV/dt_f
1.52/3.15n
R_load = 50.00
|
[Rising Waveform]
R_fixture = 50.00
V_fixture = 0.000
V_fixture_min = 0.000
V_fixture_max = 0.000
L_fixture = 0.000H
C_fixture = 0.000F
time
V(typ)
|
0.000S
0.70uV
0.20nS
0.46uV
0.40nS
-5.77uV
0.60nS
-0.27mV
0.80nS
-2.96mV
1.00nS
-3.62mV
1.20nS
19.35mV
1.40nS
46.31mV
1.60nS
79.98mV
1.80nS
0.12V
2.00nS
0.16V
2.20nS
0.20V
2.40nS
0.26V
2.60nS
0.32V
2.80nS
0.42V
3.00nS
0.51V
3.20nS
0.58V
106
0.26uA
0.26uA
0.25uA
0.25uA
0.24uA
0.23uA
0.23uA
0.22uA
0.22uA
0.21uA
0.20uA
0.20uA
0.19uA
0.19uA
0.56uA
0.17uA
0.15uA
0.29uA
0.29uA
0.28uA
0.27uA
0.27uA
0.26uA
0.25uA
0.25uA
0.24uA
0.24uA
0.23uA
0.22uA
0.22uA
0.21uA
0.72uA
0.18uA
0.18uA
min
1.20/2.87n
1.15/4.45n
max
1.77/2.14n
1.73/3.01n
V(min)
V(max)
0.93uV
0.77uV
-1.75uV
-5.10uV
26.03uV
-5.61uV
-0.80mV
-3.19mV
-6.88mV
-0.22mV
21.89mV
48.68mV
76.62mV
0.11V
0.16V
0.20V
0.24V
0.69uV
0.000V
11.67uV
-2.79mV
-6.12mV
32.64mV
81.12mV
0.11V
0.16V
0.21V
0.27V
0.33V
0.41V
0.49V
0.61V
0.73V
0.82V
DSP56371 Technical Data
Freescale Semiconductor
IBIS Model
3.40nS
3.60nS
3.80nS
4.00nS
4.20nS
4.40nS
4.60nS
4.80nS
5.00nS
5.20nS
5.40nS
5.60nS
5.80nS
6.00nS
6.20nS
6.40nS
6.60nS
6.80nS
7.00nS
7.20nS
7.40nS
7.60nS
7.80nS
8.00nS
8.20nS
8.40nS
8.60nS
8.80nS
9.00nS
9.20nS
9.40nS
9.60nS
9.80nS
10.00nS
0.71V
0.85V
1.01V
1.18V
1.38V
1.57V
1.69V
1.79V
1.91V
2.03V
2.14V
2.24V
2.28V
2.31V
2.36V
2.39V
2.41V
2.43V
2.45V
2.46V
2.48V
2.49V
2.50V
2.51V
2.52V
2.52V
2.53V
2.54V
.54V
2.55V
2.55V
2.56V
2.56V
2.57V
|
[Rising Waveform]
R_fixture = 50.00
V_fixture = 3.30
V_fixture_min = 3.00
V_fixture_max = 3.60
L_fixture = 0.000H
C_fixture = 0.000F
| time
V(typ)
|
0.000S
0.76V
0.20nS
0.76V
0.40nS
0.76V
0.60nS
0.76V
0.80nS
0.77V
1.00nS
0.81V
1.20nS
0.90V
Freescale Semiconductor
0.30V
0.36V
0.45V
0.54V
0.67V
0.81V
0.89V
0.96V
1.06V
1.15V
1.26V
1.35V
1.40V
1.45V
1.51V
1.56V
1.61V
1.66V
1.70V
1.74V
1.78V
1.82V
1.84V
1.86V
1.88V
1.90V
1.92V
1.93V
1.95V
1.96V
1.97V
1.99V
2.00V
2.00V
0.99V
1.17V
1.36V
1.56V
1.81V
2.03V
2.16V
2.27V
2.40V
2.52V
2.61V
2.70V
2.74V
2.77V
2.80V
2.83V
2.85V
2.86V
2.87V
2.88V
2.89V
2.90V
2.91V
2.91V
2.92V
2.92V
2.93V
2.93V
2.93V
2.94V
2.94V
2.94V
2.95V
2.95V
V(min)
V(max)
1.03V
1.03V
1.03V
1.03V
1.03V
1.03V
1.03V
0.72V
0.72V
0.72V
0.72V
0.73V
0.82V
0.93V
DSP56371 Technical Data
107
IBIS Model
1.40nS
1.60nS
1.80nS
2.00nS
2.20nS
2.40nS
2.60nS
2.80nS
3.00nS
3.20nS
3.40nS
3.60nS
3.80nS
4.00nS
4.20nS
4.40nS
4.60nS
4.80nS
5.00nS
5.20nS
5.40nS
5.60nS
5.80nS
6.00nS
6.20nS
6.40nS
6.60nS
6.80nS
7.00nS
7.20nS
7.40nS
7.60nS
7.80nS
8.00nS
8.20nS
8.40nS
8.60nS
8.80nS
9.00nS
9.20nS
9.40nS
9.60nS
9.80nS
10.00nS
0.98V
1.10V
1.22V
1.36V
1.53V
1.72V
1.93V
2.23V
2.48V
2.66V
2.85V
2.97V
3.09V
3.14V
3.19V
3.23V
3.25V
3.27V
3.28V
.29V
3.29V
3.30V
3.30V
3.30V
3.30V
3.30V
3.30V
3.30V
3.30V
3.30V
3.30V
3.30V
3.30V
3.30V
3.30V
3.30V
3.30V
3.30V
3.30V
3.30V
3.30V
3.30V
3.30V
3.30V
1.04V
1.11V
1.21V
1.33V
1.46V
1.60V
1.75V
1.97V
2.16V
2.30V
2.49V
2.63V
2.73V
2.83V
2.89V
2.94V
2.96V
2.97V
2.98V
2.99V
2.99V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
1.02V
1.13V
1.26V
1.42V
1.58V
1.80V
2.04V
2.36V
2.62V
2.82V
3.04V
3.19V
3.29V
3.36V
3.42V
3.47V
3.50V
3.52V
3.54V
3.56V
3.57V
3.58V
3.59V
3.59V
3.60V
3.60V
3.60V
3.60V
3.60V
3.60V
3.60V
3.60V
3.60V
3.60V
3.60V
3.60V
3.60V
3.60V
3.60V
3.60V
3.60V
3.60V
3.60V
3.60V
|
[Falling Waveform]
R_fixture = 50.00
V_fixture = 0.000
V_fixture_min = 0.000
V_fixture_max = 0.000
L_fixture = 0.000H
108
DSP56371 Technical Data
Freescale Semiconductor
IBIS Model
C_fixture = 0.000F
| time
V(typ)
|
0.000S
2.62V
0.20nS
2.62V
0.40nS
2.62V
0.60nS
2.62V
0.80nS
2.60V
1.00nS
2.50V
1.20nS
2.37V
1.40nS
2.29V
1.60nS
2.17V
1.80nS
2.04V
2.00nS
1.89V
2.20nS
1.71V
2.40nS
1.50V
2.60nS
1.28V
2.80nS
1.01V
3.00nS
0.82V
3.20nS
0.72V
3.40nS
0.61V
3.60nS
0.51V
3.80nS
0.44V
4.00nS
0.38V
4.20nS
0.32V
4.40nS
0.26V
4.60nS
0.23V
4.80nS
0.21V
5.00nS
0.17V
5.20nS
0.15V
5.40nS
0.12V
5.60nS
93.14mV
5.80nS
80.86mV
6.00nS
68.57mV
6.20nS
55.24mV
6.40nS
43.92mV
6.60nS
33.33mV
6.80nS
25.91mV
7.00nS
18.81mV
7.20nS
13.52mV
7.40nS
8.40mV
7.60nS
4.73mV
7.80nS
3.46mV
8.00nS
2.19mV
8.20nS
1.26mV
8.40nS
0.84mV
8.60nS
0.49mV
8.80nS
0.41mV
9.00nS
0.35mV
9.20nS
0.31mV
9.40nS
0.28mV
Freescale Semiconductor
V(min)
V(max)
2.12V
2.12V
2.12V
2.12V
2.12V
2.12V
2.11V
2.09V
2.04V
1.96V
1.85V
1.74V
1.63V
1.50V
1.33V
1.17V
1.04V
0.87V
0.72V
0.60V
0.49V
0.40V
0.32V
0.28V
0.25V
0.21V
0.18V
0.14V
0.11V
94.78mV
80.67mV
65.96mV
51.39mV
40.71mV
31.19mV
22.83mV
17.13mV
10.61mV
6.73mV
4.67mV
3.16mV
2.23mV
1.32mV
0.95mV
0.74mV
0.58mV
0.51mV
0.45mV
2.99V
2.99V
2.99V
2.96V
2.85V
2.72V
2.59V
2.50V
2.36V
2.20V
2.00V
1.75V
1.48V
1.24V
1.01V
0.82V
0.75V
0.65V
0.57V
0.50V
0.44V
0.38V
0.32V
0.29V
0.26V
0.23V
0.20V
0.17V
0.14V
0.12V
0.11V
90.13mV
74.96mV
61.03mV
50.31mV
39.65mV
31.61mV
22.62mV
15.75mV
12.43mV
9.14mV
6.37mV
4.12mV
2.29mV
1.55mV
0.81mV
0.53mV
0.39mV
DSP56371 Technical Data
109
IBIS Model
9.60nS
9.80nS
10.00nS
0.24mV
0.22mV
0.20mV
|
[Falling Waveform]
R_fixture = 50.00
V_fixture = 3.30
V_fixture_min = 3.00
V_fixture_max = 3.60
L_fixture = 0.000H
C_fixture = 0.000F
| time
V(typ)
|
0.000S
3.30V
0.20nS
3.30V
0.40nS
3.30V
0.60nS
3.30V
0.80nS
3.30V
1.00nS
3.25V
1.20nS
3.18V
1.40nS
3.14V
1.60nS
3.09V
1.80nS
3.03V
2.00nS
2.96V
2.20nS
2.88V
2.40nS
2.80V
2.60nS
2.72V
2.80nS
2.60V
3.00nS
2.51V
3.20nS
2.44V
3.40nS
2.34V
3.60nS
2.25V
3.80nS
2.15V
4.00nS
2.05V
4.20nS
1.93V
4.40nS
1.81V
4.60nS
1.73V
4.80nS
1.65V
5.00nS
1.53V
5.20nS
1.43V
5.40nS
1.32V
5.60nS
1.22V
5.80nS
1.18V
6.00nS
1.13V
6.20nS
1.08V
6.40nS
1.03V
6.60nS
0.99V
6.80nS
0.96V
7.00nS
0.93V
7.20nS
0.90V
7.40nS
0.87V
110
0.40mV
0.36mV
0.32mV
0.27mV
0.24mV
0.21mV
V(min)
V(max)
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
3.00V
2.97V
2.92V
2.88V
2.84V
2.80V
2.74V
2.68V
2.64V
2.58V
2.52V
2.46V
2.39V
2.32V
2.24V
2.19V
2.15V
2.09V
2.04V
1.97V
1.91V
1.87V
1.84V
1.79V
1.75V
1.70V
1.66V
1.63V
1.59V
1.53V
3.60V
3.60V
3.60V
3.59V
3.52V
3.44V
3.37V
3.32V
3.24V
3.16V
3.07V
2.98V
2.88V
2.77V
2.64V
2.54V
2.46V
2.34V
2.22V
2.08V
1.92V
1.74V
1.58V
1.50V
1.42V
1.34V
1.26V
1.18V
1.11V
1.07V
1.03V
0.99V
0.95V
0.92V
0.89V
0.87V
0.84V
0.82V
DSP56371 Technical Data
Freescale Semiconductor
IBIS Model
7.60nS
7.80nS
8.00nS
8.20nS
8.40nS
8.60nS
8.80nS
9.00nS
9.20nS
9.40nS
9.60nS
9.80nS
10.00nS
0.84V
0.83V
0.82V
0.81V
0.80V
0.79V
0.78V
0.78V
0.78V
0.77V
0.77V
0.77V
0.77V
1.47V
1.44V
1.40V
1.35V
1.30V
1.26V
1.23V
1.19V
1.17V
1.14V
1.12V
1.10V
1.08V
0.80V
0.78V
0.78V
0.76V
0.75V
0.75V
0.74V
0.73V
0.73V
0.73V
0.72V
0.72V
0.72V
|
| End [Model] prt24dgz
|
|************************************************************************
|
Model pdusdgz
|************************************************************************
|
[Model]
pdusdgz
Model_type
Input
Polarity
Non-Inverting
Vinl = 0.000V
Vinh = 3.30V
C_comp
5.00pF
5.00pF
5.00pF
|
|
[Temperature Range]
25.00
0.12k
0.000
[Pullup Reference]
3.30V
3.00V
3.60V
[Pulldown Reference]
0.000V
0.000V
0.000V
[POWER Clamp Reference] 5.00V
4.50V
5.50V
[GND Clamp Reference]
0.000V
0.000V
0.000V
[GND_clamp]
| voltage
I(typ)
I(min)
I(max)
|
-5.00
-64.63A
-59.13A
-66.41A
-4.80
-61.55A
-56.41A
-63.21A
-4.60
-58.47A
-53.69A
-60.01A
-4.40
-55.39A
-50.97A
-56.81A
-4.20
-52.31A
-48.25A
-53.61A
-4.00
-49.23A
-45.53A
-50.41A
-3.80
-46.15A
-42.81A
-47.21A
-3.60
-43.07A
-40.09A
-44.01A
-3.40
-39.99A
-37.37A
-40.81A
-3.20
-36.91A
-34.65A
-37.61A
-3.00
-33.82A
-31.94A
-34.41A
-2.80
-30.73A
-29.22A
-31.22A
-2.60
-27.64A
-26.51A
-28.02A
-2.40
-24.56A
-23.79A
-24.82A
-2.20
-21.47A
-21.08A
-21.62A
Freescale Semiconductor
DSP56371 Technical Data
111
IBIS Model
-2.00
-1.80
-1.60
-1.40
-1.20
-1.00
-0.80
-0.60
-0.40
-0.20
-0.00
0.20
0.40
0.60
0.80
1.00
1.20
1.40
1.60
1.80
2.00
2.20
2.40
2.60
2.80
3.00
3.20
3.40
3.60
3.80
4.00
4.20
4.40
4.60
4.80
5.00
-18.38A
-15.29A
-12.20A
-9.12A
-6.03A
-2.94A
-0.20A
-1.85mA
-83.24uA
-60.52uA
-60.40uA
-60.32uA
-60.23uA
-60.11uA
-59.96uA
-59.74uA
-59.32uA
-58.35uA
-56.47uA
-53.57uA
-49.55uA
-43.70uA
-3.73uA
0.10uA
0.12uA
0.13uA
0.14uA
0.15uA
0.16uA
0.17uA
0.18uA
0.18uA
0.19uA
0.20uA
0.21uA
0.22uA
|
[POWER_clamp]
| voltage
I(typ)
|
-5.00
0.61uA
-4.90
0.60uA
-4.80
0.59uA
-4.70
0.59uA
-4.60
0.58uA
-4.50
0.57uA
-4.40
0.56uA
-4.30
0.56uA
-4.20
0.55uA
-4.10
0.54uA
-4.00
0.54uA
112
-18.36A
-15.64A
-12.93A
-10.21A
-7.50A
-4.78A
-2.07A
-96.40mA
-0.50mA
-36.82uA
-35.33uA
-35.27uA
-35.20uA
-35.13uA
-35.03uA
-34.91uA
-34.50uA
-33.59uA
-31.92uA
-29.25uA
-7.60uA
-16.78nA
0.10uA
0.11uA
0.12uA
0.13uA
0.20uA
0.15uA
96.30nA
43.50nA
-9.30nA
62.10nA
-0.11uA
-0.17uA
-0.22uA
-0.27uA
-18.42A
-15.22A
-12.03A
-8.83A
-5.63A
-2.43A
-64.17mA
-4.85mA
-0.23mA
-86.29uA
-85.95uA
-85.85uA
-85.73uA
-85.57uA
-85.37uA
-85.08uA
-84.56uA
-83.44uA
-81.36uA
-78.20uA
-73.89uA
-68.43uA
-61.70uA
-51.99uA
-2.43uA
0.13uA
0.14uA
0.15uA
0.16uA
0.17uA
0.18uA
0.19uA
0.20uA
0.21uA
0.22uA
0.23uA
I(min)
I(max)
0.59uA
0.58uA
0.58uA
0.57uA
0.56uA
0.56uA
0.55uA
0.54uA
0.54uA
0.53uA
0.52uA
0.65uA
0.65uA
0.64uA
0.63uA
0.63uA
0.62uA
0.61uA
0.60uA
0.60uA
0.59uA
0.58uA
DSP56371 Technical Data
Freescale Semiconductor
IBIS Model
-3.90
-3.80
-3.70
-3.60
-3.50
-3.40
-3.30
-3.20
-3.10
-3.00
-2.90
-2.80
-2.70
-2.60
-2.50
-2.40
-2.30
-2.20
-2.10
-2.00
-1.90
-1.80
-1.70
-1.60
-1.50
-1.40
-1.30
-1.20
-1.10
-1.00
-0.90
-0.80
-0.70
-0.60
-0.50
-0.40
-0.30
-0.20
-0.10
0.00
0.53uA
0.52uA
0.52uA
0.51uA
0.50uA
0.50uA
0.49uA
0.48uA
0.48uA
0.47uA
0.46uA
0.46uA
0.45uA
0.44uA
0.44uA
0.43uA
0.42uA
0.42uA
0.41uA
0.40uA
0.39uA
0.39uA
0.38uA
0.37uA
0.37uA
0.36uA
0.35uA
0.35uA
0.34uA
0.33uA
0.33uA
0.32uA
0.31uA
0.31uA
0.30uA
0.29uA
0.29uA
0.28uA
0.27uA
0.27uA
0.52uA
0.51uA
0.50uA
0.50uA
0.49uA
0.48uA
0.48uA
0.47uA
0.46uA
0.46uA
0.45uA
0.44uA
0.44uA
0.43uA
0.42uA
0.41uA
0.41uA
0.40uA
0.39uA
0.39uA
0.38uA
0.37uA
0.37uA
0.36uA
0.35uA
0.35uA
0.34uA
0.33uA
0.33uA
0.32uA
0.31uA
0.31uA
0.30uA
0.29uA
0.29uA
0.28uA
0.27uA
0.27uA
0.26uA
0.25uA
0.58uA
0.57uA
0.56uA
0.56uA
0.55uA
0.54uA
0.53uA
0.53uA
0.52uA
0.51uA
0.51uA
0.50uA
0.49uA
0.49uA
0.48uA
0.47uA
0.46uA
0.46uA
0.45uA
0.44uA
0.44uA
0.43uA
0.42uA
0.42uA
0.41uA
0.40uA
0.39uA
0.39uA
0.38uA
0.37uA
0.37uA
0.36uA
0.35uA
0.35uA
0.34uA
0.33uA
0.32uA
0.32uA
0.31uA
0.30uA
|
| End [Model] pdusdgz
|
|************************************************************************
|
Model pdddgz
|************************************************************************
|
[Model]
pdddgz
Model_type
Input
Polarity
Non-Inverting
Vinl = 0.000V
Freescale Semiconductor
DSP56371 Technical Data
113
IBIS Model
Vinh = 3.30V
C_comp
5.00pF
|
|
[Temperature Range]
25.00
[Pullup Reference]
3.30V
[Pulldown Reference]
0.000V
[POWER Clamp Reference] 5.00V
[GND Clamp Reference] \ 0.000V
[GND_clamp]
| voltage
I(typ)
I(min)
|
-5.00
-64.63A
-59.13A
-4.80
-61.55A
-56.41A
-4.60
-58.47A
-53.69A
-4.40
-55.39A
-50.97A
-4.20
-52.31A
-48.25A
-4.00
-49.23A
-45.53A
-3.80
-46.15A
-42.81A
-3.60
-43.07A
-40.09A
-3.40
-39.99A
-37.37A
-3.20
-36.91A
-34.65A
-3.00
-33.82A
-31.94A
-2.80
-30.73A
-29.22A
-2.60
-27.64A
-26.51A
-2.40
-24.56A
-23.79A
-2.20
-21.47A
-21.08A
-2.00
-18.38A
-18.36A
-1.80
-15.29A
-15.64A
-1.60
-12.20A
-12.93A
-1.40
-9.12A
-10.21A
-1.20
-6.03A
-7.50A
-1.00
-2.94A
-4.78A
-0.80
-0.20A
-2.07A
-0.60
-1.89mA
-96.41mA
-0.40
-85.69uA
-0.50mA
-0.20
-27.91uA
-14.61uA
-0.00
-87.50nA
-88.83nA
0.20
18.71uA
7.31uA
0.40
29.18uA
10.24uA
0.60
32.49uA
10.66uA
0.80
33.06uA
10.78uA
1.00
33.29uA
10.85uA
1.20
33.44uA
10.91uA
1.40
33.56uA
10.96uA
1.60
33.66uA
11.01uA
1.80
33.76uA
11.06uA
2.00
33.85uA
11.10uA
2.20
33.94uA
11.12uA
2.40
33.99uA
11.13uA
2.60
34.01uA
11.14uA
114
5.00pF
5.00pF
0.12k
3.00V
0.000V
4.50V
0.000V
0.000
3.60V
0.000V
5.50V
0.000V
I(max)
-66.41A
-63.21A
-60.01A
-56.81A
-53.61A
-50.41A
-47.21A
-44.01A
-40.81A
-37.61A
-34.41A
-31.22A
-28.02A
-24.82A
-21.62A
-18.42A
-15.22A
-12.03A
-8.83A
-5.63A
-2.43A
-64.21mA
-4.91mA
-0.24mA
-42.88uA
-0.10uA
32.27uA
54.12uA
65.78uA
69.33uA
70.16uA
70.54uA
70.78uA
70.98uA
71.15uA
71.30uA
71.44uA
71.59uA
71.74uA
DSP56371 Technical Data
Freescale Semiconductor
IBIS Model
2.80
3.00
3.20
3.40
3.60
3.80
4.00
4.20
4.40
4.60
4.80
5.00
34.02uA
34.03uA
34.04uA
34.06uA
34.08uA
34.10uA
34.12uA
34.14uA
34.16uA
34.18uA
34.20uA
34.22uA
|
[POWER_clamp]
| voltage
I(typ)
|
-5.00
48.19uA
-4.90
47.87uA
-4.80
47.55uA
-4.70
47.23uA
-4.60
46.91uA
-4.50
46.59uA
-4.40
46.27uA
-4.30
45.95uA
-4.20
45.63uA
-4.10
45.31uA
-4.00
44.99uA
-3.90
44.67uA
-3.80
44.35uA
-3.70
44.03uA
-3.60
43.71uA
-3.50
43.39uA
-3.40
43.07uA
-3.30
42.75uA
-3.20
42.43uA
-3.10
42.11uA
-3.00
41.79uA
-2.90
41.47uA
-2.80
41.15uA
-2.70
40.83uA
-2.60
40.51uA
-2.50
40.19uA
-2.40
39.87uA
-2.30
39.55uA
-2.20
39.23uA
-2.10
38.91uA
-2.00
38.59uA
-1.90
38.27uA
-1.80
37.95uA
-1.70
37.63uA
-1.60
37.31uA
Freescale Semiconductor
11.15uA
11.16uA
11.25uA
11.17uA
11.09uA
11.01uA
10.93uA
10.85uA
10.77uA
10.69uA
10.61uA
10.53uA
71.82uA
71.84uA
71.85uA
71.87uA
71.89uA
71.91uA
71.93uA
71.95uA
71.97uA
71.99uA
72.01uA
72.03uA
I(min)
I(max)
16.29uA
16.17uA
16.05uA
15.93uA
15.81uA
15.69uA
15.57uA
15.45uA
15.33uA
15.21uA
15.09uA
14.97uA
14.85uA
14.73uA
14.61uA
14.49uA
14.37uA
14.25uA
14.13uA
14.01uA
13.89uA
13.77uA
13.65uA
13.53uA
13.41uA
13.29uA
13.17uA
13.05uA
12.93uA
12.81uA
12.69uA
12.57uA
12.45uA
12.33uA
12.22uA
95.53uA
95.03uA
94.53uA
94.03uA
93.53uA
93.03uA
92.53uA
92.03uA
91.53uA
91.03uA
90.53uA
90.03uA
89.53uA
89.03uA
88.53uA
88.03uA
87.53uA
87.03uA
86.53uA
86.03uA
85.53uA
85.03uA
84.53uA
84.03uA
83.53uA
83.03uA
82.53uA
82.03uA
81.53uA
81.03uA
80.53uA
80.03uA
79.53uA
79.03uA
78.53uA
DSP56371 Technical Data
115
IBIS Model
-1.50
-1.40
-1.30
-1.20
-1.10
-1.00
-0.90
-0.80
-0.70
-0.60
-0.50
-0.40
-0.30
-0.20
-0.10
0.00
36.99uA
36.68uA
36.38uA
36.11uA
35.86uA
35.63uA
35.41uA
35.22uA
35.05uA
34.90uA
34.77uA
34.65uA
34.55uA
34.47uA
34.40uA
34.34uA
12.11uA
12.01uA
11.92uA
11.84uA
11.76uA
11.69uA
11.63uA
11.57uA
11.52uA
11.48uA
11.44uA
11.41uA
11.38uA
11.35uA
11.33uA
11.31uA
78.03uA
77.53uA
77.03uA
76.53uA
76.03uA
75.53uA
75.06uA
74.63uA
74.24uA
73.89uA
73.58uA
73.30uA
73.06uA
72.86uA
72.68uA
72.54uA
|
| End [Model] pdddgz
|
|************************************************************************
|
Model pdudgz
|************************************************************************
|
[Model]
pdudgz
Model_type
Input
Polarity
Non-Inverting
Vinl = 0.000V
Vinh = 3.30V
C_comp
5.00pF
5.00pF
5.00pF
|
|
[Temperature Range]
25.00
0.12k
0.000
[Pullup Reference]
3.30V
3.00V
3.60V
[Pulldown Reference]
0.000V
0.000V
0.000V
[POWER Clamp Reference] 5.00V
4.50V
5.50V
[GND Clamp Reference] 0.000V
0.000V
0.000V
[GND_clamp]
| voltage
I(typ)
I(min)
I(max)
|
-5.00
-64.63A
-59.13A
-66.41A
-4.80
-61.55A
-56.41A
-63.21A
-4.60
-58.47A
-53.69A
-60.01A
-4.40
-55.39A
-50.97A
-56.81A
-4.20
-52.31A
-48.25A
-53.61A
-4.00
-49.23A
-45.53A
-50.41A
-3.80
-46.15A
-42.81A
-47.21A
-3.60
-43.07A
-40.09A
-44.01A
-3.40
-39.99A
-37.37A
-40.81A
-3.20
-36.91A
-34.65A
-37.61A
-3.00
-33.82A
-31.94A
-34.41A
-2.80
-30.73A
-29.22A
-31.22A
116
DSP56371 Technical Data
Freescale Semiconductor
IBIS Model
-2.60
-2.40
-2.20
-2.00
-1.80
-1.60
-1.40
-1.20
-1.00
-0.80
-0.60
-0.40
-0.20
-0.00
0.20
0.40
0.60
0.80
1.00
1.20
1.40
1.60
1.80
2.00
2.20
2.40
2.60
2.80
3.00
3.20
3.40
3.60
3.80
4.00
4.20
4.40
4.60
4.80
5.00
-27.64A
-24.56A
-21.47A
-18.38A
-15.29A
-12.20A
-9.12A
-6.03A
-2.94A
-0.20A
-1.85mA
-83.24uA
-60.52uA
-60.40uA
-60.32uA
-60.23uA
-60.11uA
-59.96uA
-59.74uA
-59.32uA
-58.35uA
-56.47uA
-53.57uA
-49.55uA
-43.70uA
-3.73uA
0.10uA
0.12uA
0.13uA
0.14uA
0.15uA
0.16uA
0.17uA
0.18uA
0.18uA
0.19uA
0.20uA
0.21uA
0.22uA
|
[POWER_clamp]
| voltage I(typ)
|
-5.00
0.61uA
-4.90
0.60uA
-4.80
0.59uA
-4.70
0.59uA
-4.60
0.58uA
-4.50
0.57uA
-4.40
0.56uA
-4.30
0.56uA
Freescale Semiconductor
-26.51A
-23.79A
-21.08A
-18.36A
-15.64A
-12.93A
-10.21A
-7.50A
-4.78A
-2.07A
-96.40mA
-0.50mA
-36.82uA
-35.33uA
-35.27uA
-35.20uA
-35.13uA
-35.03uA
-34.87uA
-34.50uA
-33.59uA
-31.92uA
-29.25uA
-7.60uA
-16.78nA
0.10uA
0.11uA
0.12uA
0.13uA
0.20uA
0.15uA
96.30nA
43.50nA
-9.30nA
62.10nA
-0.11uA
-0.17uA
-0.22uA
-0.27uA
I(min)
0.59uA
0.58uA
0.58uA
0.57uA
0.56uA
0.56uA
0.55uA
0.54uA
-28.02A
-24.82A
-21.62A
-18.42A
-15.22A
-12.03A
-8.83A
-5.63A
-2.43A
-64.17mA
-4.85mA
-0.23mA
-86.29uA
-85.95uA
-85.85uA
-85.73uA
-85.57uA
-85.37uA
-85.08uA
-84.56uA
-83.44uA
-81.36uA
-78.20uA
-73.89uA
-68.43uA
61.70uA
51.99uA
-2.43uA
0.13uA
0.14uA
0.15uA
0.16uA
0.17uA
0.18uA
0.19uA
0.20uA
0.21uA
0.22uA
0.23uA
I(max)
0.65uA
0.65uA
0.64uA
0.63uA
0.63uA
0.62uA
0.61uA
0.60uA
DSP56371 Technical Data
117
IBIS Model
-4.20
-4.10
-4.00
-3.90
-3.80
-3.70
-3.60
-3.50
-3.40
-3.30
-3.20
-3.10
-3.00
-2.90
-2.80
-2.70
-2.60
-2.50
-2.40
-2.30
-2.20
-2.10
-2.00
-1.90
-1.80
-1.70
-1.60
-1.50
-1.40
-1.30
-1.20
-1.10
-1.00
-0.90
-0.80
-0.70
-0.60
-0.50
-0.40
-0.30
-0.20
-0.10
0.00
0.55uA
0.54uA
0.54uA
0.53uA
0.52uA
0.52uA
0.51uA
0.50uA
0.50uA
0.49uA
0.48uA
0.48uA
0.47uA
0.46uA
0.46uA
0.45uA
0.44uA
0.44uA
0.43uA
0.42uA
0.42uA
0.41uA
0.40uA
0.39uA
0.39uA
0.38uA
0.37uA
0.37uA
0.36uA
0.35uA
0.35uA
0.34uA
0.33uA
0.33uA
0.32uA
0.31uA
0.31uA
0.30uA
0.29uA
0.29uA
0.28uA
0.27uA
0.27uA
0.54uA
0.53uA
0.52uA
0.52uA
0.51uA
0.50uA
0.50uA
0.49uA
0.48uA
0.48uA
0.47uA
0.46uA
0.46uA
0.45uA
0.44uA
0.44uA
0.43uA
0.42uA
0.41uA
0.41uA
0.40uA
0.39uA
0.39uA
0.38uA
0.37uA
0.37uA
0.36uA
0.35uA
0.35uA
0.34uA
0.33uA
0.33uA
0.32uA
0.31uA
0.31uA
0.30uA
0.29uA
0.29uA
0.28uA
0.27uA
0.27uA
0.26uA
0.25uA
0.60uA
0.59uA
0.58uA
0.58uA
0.57uA
0.56uA
0.56uA
0.55uA
0.54uA
0.53uA
0.53uA
0.52uA
0.51uA
0.51uA
0.50uA
0.49uA
0.49uA
0.48uA
0.47uA
0.46uA
0.46uA
0.45uA
0.44uA
0.44uA
0.43uA
0.42uA
0.42uA
0.41uA
0.40uA
0.39uA
0.39uA
0.38uA
0.37uA
0.37uA
0.36uA
0.35uA
0.35uA
0.34uA
0.33uA
0.32uA
0.32uA
0.31uA
0.30uA
|
| End [Model] pdudgz
|
|************************************************************************
|
Model pdidgz
|************************************************************************
|
[Model]
pdidgz
118
DSP56371 Technical Data
Freescale Semiconductor
IBIS Model
Model_type
Input
Polarity
Non-Inverting
Vinl = 0.000V
Vinh = 3.30V
C_comp
5.00pF
|
|
[Temperature Range]
25.00
[Pullup Reference]
3.30V
[Pulldown Reference]
0.000V
[POWER Clamp Reference] 5.00V
[GND Clamp Reference]
0.000V
[GND_clamp]
| voltage
I(typ)
I(min)
|
-5.00
-64.63A
-59.13A
-4.80
-61.55A
-56.41A
-4.60
-58.47A
-53.69A
-4.40
-55.39A
-50.97A
-4.20
-52.31A
-48.25A
-4.00
-49.23A
-45.53A
-3.80
-46.15A
-42.81A
-3.60
-43.07A
-40.09A
-3.40
-39.99A
-37.37A
-3.20
-36.91A
-34.65A
-3.00
-33.82A
-31.94A
-2.80
-30.73A
-29.22A
-2.60
-27.64A
-26.51A
-2.40
-24.56A
-23.79A
-2.20
-21.47A
-21.08A
-2.00
-18.38A
-18.36A
-1.80
-15.29A
-15.64A
-1.60
-12.20A
-12.93A
-1.40
-9.12A
-10.21A
-1.20
-6.03A
-7.50A
-1.00
-2.94A
-4.78A
-0.80
-0.20A
-2.07A
-0.60
-1.79mA
-96.39mA
-0.40
-22.83uA
-0.47mA
-0.20
-0.15uA
-1.56uA
-0.00
-88.71nA
-89.34nA
0.20
-72.38nA
-68.50nA
0.40
-56.11nA
-52.12nA
0.60
-39.84nA
-35.76nA
0.80
-23.57nA
-19.40nA
1.00
-7.31nA
-3.04nA
1.20
8.94nA
13.32nA
1.40
25.19nA
29.68nA
1.60
41.42nA
46.03nA
1.80
57.64nA
62.39nA
2.00
73.83nA
78.74nA
Freescale Semiconductor
5.00pF
5.00pF
0.12k
3.00V
0.000V
4.50V
0.000V
0.000
3.60V
0.000V
5.50V
0.000V
I(max)
-66.41A
-63.21A
-60.01A
-56.81A
-53.61A
-50.41A
-47.21A
-44.01A
-40.81A
-37.61A
-34.41A
-31.22A
-28.02A
-24.82A
-21.62A
-18.42A
-15.22A
-12.03A
-8.83A
-5.63A
-2.43A
-64.14mA
-4.77mA
-0.14mA
-0.37uA
-0.11uA
-88.30nA
-71.55nA
-54.82nA
-38.12nA
-21.42nA
-4.73nA
11.97nA
28.68nA
45.42nA
62.20nA
DSP56371 Technical Data
119
IBIS Model
2.20
2.40
2.60
2.80
3.00
3.20
3.40
3.60
3.80
4.00
4.20
4.60
4.80
5.00
89.95nA
0.11uA
0.12uA
0.13uA
0.14uA
0.15uA
0.15uA
0.16uA
0.17uA
0.18uA
0.20uA
0.20uA
0.21uA
0.22uA
|
[POWER_clamp]
| voltage I(typ)
|
-5.00
0.60uA
-4.90
0.60uA
-4.80
0.59uA
-4.70
0.58uA
-4.60
0.58uA
-4.50
0.57uA
-4.40
0.56uA
-4.30
0.56uA
-4.20
0.55uA
-4.10
0.54uA
-4.00
0.54uA
-3.90
0.53uA
-3.80
0.52uA
-3.70
0.52uA
-3.60
0.51uA
-3.50
0.50uA
-3.40
0.49uA
-3.30
0.49uA
-3.20
0.48uA
-3.10
0.47uA
-3.00
0.47uA
-2.90
0.46uA
-2.80
0.45uA
-2.70
0.45uA
-2.60
0.44uA
-2.50
0.43uA
-2.40
0.43uA
-2.30
0.42uA
-2.20
0.41uA
-2.10
0.41uA
-2.00
0.40uA
-1.90
0.39uA
-1.80
0.39uA
120
94.86nA
0.11uA
0.12uA
0.13uA
0.14uA
0.21uA
0.15uA
0.10uA
47.20nA
-5.80nA
-0.11uA
-0.16uA
-0.22uA
-0.27uA
I(min)
0.59uA
0.58uA
0.58uA
0.57uA
0.56uA
0.56uA
0.55uA
0.54uA
0.54uA
0.53uA
0.52uA
0.52uA
0.51uA
0.50uA
0.50uA
0.49uA
0.48uA
0.48uA
0.47uA
0.46uA
0.46uA
0.45uA
0.44uA
0.43uA
0.43uA
0.42uA
0.41uA
0.41uA
0.40uA
0.39uA
0.39uA
0.38uA
0.37uA
79.06nA
96.02nA
0.11uA
0.13uA
0.14uA
0.15uA
0.16uA
0.17uA
0.18uA
0.18uA
0.20uA
0.21uA
0.22uA
0.23uA
I(max)
0.65uA
0.64uA
0.64uA
0.63uA
0.62uA
0.62uA
0.61uA
0.60uA
0.59uA
0.59uA
0.58uA
0.57uA
0.57uA
0.56uA
0.55uA
0.55uA
0.54uA
0.53uA
0.53uA
0.52uA
0.51uA
0.51uA
0.50uA
0.49uA
0.48uA
0.48uA
0.47uA
0.46uA
0.46uA
0.45uA
0.44uA
0.44uA
0.43uA
DSP56371 Technical Data
Freescale Semiconductor
IBIS Model
-1.70
-1.60
-1.50
-1.40
-1.30
-1.20
-1.10
-1.00
-0.90
-0.80
-0.70
-0.60
-0.50
-0.40
-0.30
-0.20
-0.10
0.00
0.38uA
0.37uA
0.37uA
0.36uA
0.35uA
0.35uA
0.34uA
0.33uA
0.33uA
0.32uA
0.31uA
0.31uA
0.30uA
0.29uA
0.29uA
0.28uA
0.28uA
0.27uA
0.37uA
0.36uA
0.35uA
0.35uA
0.34uA
0.33uA
0.33uA
0.32uA
0.31uA
0.31uA
0.30uA
0.29uA
0.29uA
0.28uA
0.27uA
0.27uA
0.26uA
0.26uA
0.42uA
0.42uA
0.41uA
0.40uA
0.39uA
0.39uA
0.38uA
0.37uA
0.37uA
0.36uA
0.35uA
0.35uA
0.34uA
0.33uA
0.33uA
0.32uA
0.31uA
0.31uA
|
| End [Model] pdidgz
Freescale Semiconductor
DSP56371 Technical Data
121
IBIS Model
NOTES
122
DSP56371 Technical Data
Freescale Semiconductor
IBIS Model
NOTES
Freescale Semiconductor
DSP56371 Technical Data
123
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© Freescale Semiconductor, Inc. 2005. All rights reserved.
DSP56371
Rev. 3
1/2005