WEDC EDI2CG272128V85D1 2x128kx72, 3.3v sync/sync burst sram so-dimm Datasheet

White Electronic Designs
EDI2CG272128V
ADVANCED*
2x128Kx72, 3.3V Sync/Sync Burst SRAM SO-DIMM
FEATURES
DESCRIPTION
2x128Kx72 Synchronous, Synchronous Burst
Flow-Through Architecture
Linear and Sequential Burst Support via MODE pin
Access Speed(s): TKHQV = 8.5, 9, 12, 15ns
Clock Controlled Registered Bank Enables (E1#, E2#)
Clock Controlled Registered Address
Clock Controlled Registered Global Write (GW#)
The EDI2CG272128VxxD1 is a Synchronous/Synchronous
Burst SRAM, 72 position DIMM (144 contacts) Module,
small outline. The Module contains four (4) Synchronous
Burst Ram Devices, packaged in the industry standard
JEDEC 14mmx20mm TQFP placed on a Multilayer FR4
Substrate. The module architecture is defined as a Sync/
Sync Burst, Flow-Through, with support for linear burst.
This module provides High Performance, 2-1-1-1 accesses
when used in Burst Mode, and used as a Synchronous
Only Mode, provides a high performance cost advantage
over BiCMOS aysnchronous device architectures.
Aysnchronous Output Enable (G#)
Internally Self-timed Write
Individual Bank Sleep Mode enables (ZZ1, ZZ2)
Gold Lead Finish
3.3V ± 10% Operation
Common Data I/O
High Capacitance (30pf) drive, at rated Access Speed
Single Total Array Clock
Multiple Vcc and Gnd
Synchronous Only operations are performed via strapping
ADSC# Low, and ADSP# / ADV# High, which provides
for Ultra Fast Accesses in Read Mode while providing for
internally self-timed Early Writes.
Synchronous/Synchronous Burst operations are in relation
to an externally supplied clock, Registered Address,
Registered Global Write, Registered Enables as well
as an Asynchronous Output enable. This Module has
been defined for Quad Words in both Read and Write
Operations.
*This product is under development, is not qualified or characterized and is subject to
change or cancellation without notice.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
August 2000
Rev. 0
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
EDI2CG272128V
ADVANCED
PIN CONFIGURATION
PIN NAMES
PIN SYMBOLS
PIN
FUNCTION
PIN
FUNCTION
PIN
FUNCTION
PIN
FUNCTION
1
VSS
37
DQ0
73
VSS
109
DQ41
2
VSS
38
DQ7
74
VSS
110
DQ46
3
A0
39
DQ1
75
ZZ2
111
DQ42
4
RFU
40
DQ6
76
DQP3
112
DQ45
5
A16
41
DQ2
77
6
A1
42
DQ5
78
7
A2
43
DQ3
79
8
A15
44
DQ4
80
VCC
113
DQ43
VCC
114
DQ44
DQ24
115
VSS
DQ31
116
VSS
9
A14
45
VSS
81
DQ25
117
RFU
10
A3
46
VSS
82
DQ30
118
DQP6
11
A4
47
ZZ1
83
DQ26
119
VCC
DQ0-DQ63
DQP0-DQP7
Parity Bits
A0-A16
Address Bus
E1#, E2#
Synchronous Bank Enables
CK
Array Clock
GW#
Synchronous Global
Write Enable
G#
Asynchronous Output
Enable
ZZ1, ZZ2
Blank Sleep Mode Enables
Vcc
3.3V Power Supply
Ground
No Connect
12
A13
48
DQP1
84
DQ29
120
VCC
Vss
13
A12
49
VCC
85
DQ27
121
DQ48
NC
14
A5
50
VCC
86
DQ28
122
DQ55
15
A6
51
DQ8
87
VSS
123
DQ49
16
A11
52
DQ15
88
VSS
124
DQ54
17
A10
53
DQ9
89
RFU
125
DQ50
18
A7
54
DQ14
90
DQP4
126
DQ53
19
A8
55
DQ10
91
VCC
127
DQ51
20
A9
56
DQ13
92
VCC
128
DQ52
21
VCC
57
DQ11
93
DQ32
129
VSS
22
VCC
58
DQ12
94
DQ39
130
VSS
23
G#
59
VSS
95
DQ33
131
RFU
24
RFU
60
VSS
96
DQ38
132
DQP7
25
GW#
61
E2
97
DQ34
133
VCC
26
ADV#
62
DQP2
98
DQ37
134
VCC
27
ADSP#
63
VCC
99
DQ35
135
DQ56
28
ADSC#
64
VCC
100
DQ36
136
DQ63
29
MODE
65
DQ16
101
VSS
137
DQ57
DQ62
30
CK
66
DQ23
102
VSS
138
31
VSS
67
DQ17
103
RFU
139
DQ58
32
VSS
68
DQ22
104
DQP5
140
DQ61
33
E1#
69
DQ18
105
VCC
141
DQ59
34
DQP0
70
DQ21
106
VCC
142
DQ60
35
VCC
71
DQ19
107
DQ40
143
VSS
36
VCC
72
DQ20
108
DQ47
144
VSS
Input/Output Bus
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
August 2000
Rev. 0
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White Electronic Designs
EDI2CG272128V
ADVANCED
FIG. 1
FUNCTIONAL BLOCK DIAGRAM
A0-16
ADSC#
ADSP#
ADV#
CK
G#
GW#
ADSC#
ADSP#
ADV#
CK
G#
GW#
E#
ZZ
E1#
ZZ1
ADSC#
ADSP#
ADV#
CK
G#
GW#
E#
ZZ
E2#
ADSC#
ADSP#
ADV#
CK
G#
GW#
E#
ZZ
ZZ2
ADSC#
ADSP#
ADV#
CK
G#
GW#
E#
ZZ
DQ
DQ0-31
DQP0-3
U1
DQ
DQ0-31
DQP0-3
U2
DQ
DQ32-63
DQP4-7
U3
DQ
DQ32-63
DQP4-7
U4
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
August 2000
Rev. 0
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White Electronic Designs
EDI2CG272128V
ADVANCED
PIN DESCRIPTIONS
DIMM Pins
Symbol
Type
Description
3, 6, 10, 11, 14, 15,
18, 19, 20, 17, 16,
13, 12, 9, 8, 3, 5
A0-16
Input
Synchronous
Addresses: These inputs are registered and must meet the setup and hold times around the
rising edge of CK. The burst counter generates internal addresses associated with A0 and A1,
during burst and wait cycle.
25
GW#
Input
Synchronous
Global Write: This active LOW input allows a full 72-bit WRITE to occur independent of the
BWE# and BWx# lines and must meet the setup and hold times around the rising edge of CK.
30
CK
Input
Synchronous
Clock: This signal registers the addresses, data, chip enables, write control and burst control
inputs on its rising edge. All synchronous inputs must meet setup and hold times around the
clock’s rising edge.
33, 61
E1#, E2#
Input
Synchronous
Bank Enables: These active LOW inputs are used to enable each individual bank and to
gate ADSP#.
23
G#
Input
Synchronous
Output Enable: This active LOW asynchronous input enables the data output drivers.
26
ADV#
Input
Synchronous
Address Status Processor: This active LOW input is used to control the internal burst counter.
A HIGH on this pin generates wait cycle (no address advance)
27
ADSP#
Input
Synchronous
Address Status Processor: This active LOW input, along with EL# and EH# being LOW,
causes a new external address to be registered and a READ cycle is initiated using the new
address.
28
ADSC#
Input
Synchronous
Address Status Controller: This active LOW input causes device to be de-selected or selected
along with new external address to be registered. A READ or WRITE cycle is initiated depending upon write control inputs.
29
MODE
Input Static
47, 75
ZZ1, ZZ2
Input
Asynchronous
Snooze: These active HIGH inputs put the individual banks in low power consumption standby
mode. For normal operation,this input has to be either LOW or NC (no connect).
Various
DQ0-63
Input/Output
Data Inputs/Outputs: First byte is DQ0-7, second byte is DQ8-15, third byte is DQ16-23, fourth
byte is DQ24-31, fifth byte is DQ32-39, sixth byte is DQ40-47, seventh byte is DQ48-55 and
the eight byte is DQ56-64.
Parity Inputs/Outputs: DQP0 is parity bit for DQ0-7. DQP1 is parity bit for DQ8-15. DQP2 is
parity bit for DQ16-23. DQP3 is parity bit for DQ24-31. DQP4# is parity bit for DQ32-39. DQP5
is parity bit for DQ40-47. DQP6# is parity bit for DQ48-55. DQP7 is parity bit for DQ56-64 and
DQP7. In order to use the device configured as a 128K x 64, the parity bits need to be tied to
Vss through a 10K ohm resistor.
Mode: This input selects the burst sequence. A LOW on this pin selects LINEAR BURST.
A NC or HIGH on this pin selects INTERLEAVED BURST.
34, 48, 62, 76,
90, 104, 118, 132
DQP0-7
Input/Output
Various
Vcc
Supply
Core power supply: +3.3V -5%/+10%
Various
Vss
Ground
Ground
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
August 2000
Rev. 0
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White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
EDI2CG272128V
ADVANCED
SYNCHRONOUS BURST - TRUTH TABLE
Operation
E1#
E2#
ADSP#
ADSC#
ADV#
GW#
G#
CK
DQ
Addr. Used
Deselected Cycle, Power Down; Bank 1
H
X
X
L
X
X
X
L-H
High-Z
None
Deselected Cycle, Power Down; Bank 2
X
H
X
L
X
X
X
L-H
High-Z
None
Read Cycle, Begin Burst; Bank 1
L
H
L
X
X
X
L
L-H
Q
External
Read Cycle, Begin Burst; Bank 1
L
H
L
X
X
X
H
L-H
High-Z
External
Read Cycle, Begin Burst; Bank 2
H
L
L
X
X
X
L
L-H
Q
External
Read Cycle, Begin Burst; Bank 2
H
L
L
X
X
X
H
L-H
High-Z
External
Write Cycle, Begin Burst; Bank 1
L
H
H
L
X
L
X
L-H
D
External
Write Cycle, Begin Burst; Bank 2
H
L
H
L
X
L
X
L-H
D
External
Read Cycle, Begin Burst; Bank 1
L
H
H
L
X
H
L
L-H
Q
External
Read Cycle, Begin Burst; Bank 1
L
H
H
L
X
H
H
L-H
High-Z
External
Read Cycle, Begin Burst; Bank 2
H
L
H
L
X
H
L
L-H
Q
External
Read Cycle, Begin Burst; Bank 2
H
L
H
L
X
H
H
L-H
High-Z
External
Read Cycle, Continue Burst; Bank 1
X
H
X
H
L
H
L
L-H
Q
Next
Read Cycle, Continue Burst; Bank 1
X
H
X
H
L
H
H
L-H
High-Z
Next
Read Cycle, Continue Burst; Bank 2
H
X
X
H
L
H
L
L-H
Q
Next
Read Cycle, Continue Burst; Bank 2
H
X
X
H
L
H
H
L-H
High-Z
Next
Read Cycle, Continue Burst; Bank 1
H
H
X
H
L
H
L
L-H
Q
Next
Read Cycle, Continue Burst; Bank 1
H
H
X
H
L
H
H
L-H
High-Z
Next
Read Cycle, Continue Burst; Bank 2
H
H
X
H
L
H
L
L-H
Q
Next
Read Cycle, Continue Burst; Bank 2
H
H
X
H
L
H
H
L-H
High-Z
Next
Write Cycle, Continue Burst; Bank 1
X
H
H
H
L
L
X
L-H
D
Next
Write Cycle, Continue Burst; Bank 1
H
H
X
H
L
L
X
L-H
D
Next
Write Cycle, Continue Burst; Bank 2
H
X
H
H
L
L
X
L-H
D
Next
Write Cycle, Continue Burst; Bank 2
H
H
X
H
L
L
X
L-H
D
Next
Read Cycle, Suspend Burst; Bank 1
X
H
H
H
H
H
L
L-H
Q
Current
Read Cycle, Suspend Burst; Bank 1
X
H
H
H
H
H
H
L-H
High-Z
Current
Read Cycle, Suspend Burst; Bank 2
H
X
H
H
H
H
L
L-H
Q
Current
Read Cycle, Suspend Burst; Bank 2
H
X
H
H
H
H
H
L-H
High-Z
Current
Read Cycle, Suspend Burst; Bank 1
H
H
X
H
H
H
L
L-H
Q
Current
Read Cycle, Suspend Burst; Bank 1
H
H
X
H
H
H
H
L-H
High-Z
Current
Read Cycle, Suspend Burst; Bank 2
H
H
X
H
H
H
L
L-H
Q
Current
Read Cycle, Suspend Burst; Bank 2
H
H
X
H
H
H
H
L-H
High-Z
Current
Write Cycle, Suspend Burst; Bank 1
X
H
H
H
H
L
X
L-H
D
Current
Write Cycle, Suspend Burst; Bank 1
H
H
X
H
H
L
X
L-H
D
Current
Write Cycle, Suspend Burst; Bank 2
H
X
H
H
H
L
X
L-H
D
Current
Write Cycle, Suspend Burst; Bank 2
H
H
X
H
H
L
X
L-H
D
Current
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
August 2000
Rev. 0
5
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
EDI2CG272128V
ADVANCED
SYNCHRONOUS ONLY - TRUTH TABLE
Operation
E1#
E2#
GW#
G#
ZZ
CK
DQ
L
L
H
H
H
L
L
H
L
H
L
H
L
L
L
High-Z
Synchronous Write-Bank 1
Synchronous Read-Bank 1
Synchronous Write-Bank 2
Synchronous Read-Bank 2
H
L
H
L
L
Synchronous Write-Bank 3
Synchronous Read-Bank 3
Synchronous Write-Bank 4
Synchronous Read-Bank 4
Snooze Mode
H
H
H
H
X
H
H
H
H
X
L
H
L
H
X
H
L
H
L
X
L
L
L
L
H
X
ABSOLUTE MAXIMUM RATINGS*
Voltage on VCC Relative to VSS
VIN
Storage Temperature
Operating Temperature (Commercial)
Operating Temperature (Industrial)
Short Circuit Output Current
-0.5V to +4.6V
-0.5V to VCC +0.5V
-55°C to +125°C
0°C to +70°C
-40°C to +85°C
10 mA
*Stress greater than those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions greater
than those indicated in operational sections of this specifications is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
High-Z
High-Z
High-Z
High-Z
RECOMMENDED DC OPERATING CONDITIONS
Parameter
Sym
Min
Typ
Max
Units
Supply Voltage
Supply Voltage
Input High
Input Low
Input Leakage
Output Leakage
VCC
VSS
VIH
VIL
ILI
ILO
3.14
0.0
2.0
-0.3
-2
-2
3.3
0.0
3.0
0.0
1
1
3.6
0.0
VCC+0.3
0.8
2
2
V
V
V
V
µA
µA
DC ELECTRICAL CHARACTERISTICS - READ CYCLE
Max
Description
Power Supply Current
Power Supply Current Device
Selected, No Operation
Snooze Mode
CMOS Standby
Clock Running-Deselect
Symbol
Icc1
Typ
1.55
8.5
2.2
9
2.1
12
2.1
15
2.0
Units
A
Icc
750
1.5
1.5
1.0
1.0
A
Icczz
Icc3
IccK
150
400
600
200
600
1.0
200
600
1.0
200
600
0.75
200
600
0.75
mA
mA
mA
AC TEST CIRCUIT
I/O
AC TEST CONDITIONS
Parameter
Z0
Z0==50Ω
50Ω
Input Pulse Levels
50 Ω
Input and Output Timing Ref.
Output Test equivalencies
I/0
Unit
VSS to 3.0
V
1.25
V
See figure
at left
Vt = 1.25V
FIG. 2
AC Output Load Equivalent
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
August 2000
Rev. 0
6
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
EDI2CG272128V
ADVANCED
BURST ADDRESS TABLE (MODE=VSS)
BURST ADDRESS TABLE (MODE=NC/VCC)
First
Address
(external)
A-A00
A-A01
A-A10
A-A11
Second
Address
(internal)
A-A01
A-A00
A-A11
A-A10
Third
Address
(internal)
A-A10
A-A11
A-A00
A-A01
Fourth
Address
(internal)
A-A11
A-A10
A-A01
A-A00
First
Address
(external)
A-A00
A-A01
A-A10
A-A11
Second
Address
(internal)
A-A01
A-A10
A-A11
A-A00
Third
Address
(internal)
A-A10
A-A11
A-A00
A-A01
Fourth
Address
(internal)
A-A11
A-A00
A-A01
A-A10
READ CYCLE TIMING PARAMETERS
Description
Clock Cycle Time
Clock High Time
Clock Low Time
Clock to Output Valid
Clock to Output Invalid
Clock to Output Low-Z
Output Enable to Output Valid
Output Enable to Output Low-Z
Output Enable to Output High-Z
Address Setup
Bank Enable Setup
Address Hold
Bank Enable Hold
8.5ns
Min
Max
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
Sym
tKHKH
tKHKL
tKLKH
tKHQV
tKHQX1
tKHQX
tGLQV
tGLQX
tGHQZ
tAVKH
tEVKH
tKHAX
tKHEX
9ns
Min
10
4
4
Max
Min
12
5
5
12ns
Max
9
3
2
10
3
2
12
4
0
5
0
4
2.5
2.5
1.0
1.0
15ns
Max
3
2
4
0
Min
15
5
5
4
2.5
2.5
1.0
1.0
5
2.5
2.5
1.0
1.0
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
*TBD
FIG. 3
SYNCHRONOUS ONLY READ CYCLE
tKHKH
tKHKL
tKLKH
CK
tAVKH
EX#
ADDR
G#
Addr 1
Addr 1
tKHAX
tKHQV
tGLQV
tGLQX
GW#
tKHQX
DQ
Addr 2
Q(Addr 1)
Q(Addr 1)
tKHQZ
Q(Addr 2)
tKHQX1
Read Cycle
Back to Back Read
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
August 2000
Rev. 0
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White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
EDI2CG272128V
ADVANCED
FIG. 4
SYNCHRONOUS-BURST READ CYCLE
tKHKH
tKHKL
tKLKH
CK
tSPVKH
tKHSPX
ADSP#
tSCVKH
tKHSCX
ADSC#
tAVKH
tKHAX
ADDR
BWx#,
GW#
tEVKH
tKHEX
Ex#
tAVVKH
tKHAVX
ADV#
tGHQX
tKHQV
G#
tGLQV
tGLQX
tGHQZ
DQ
tKHQX
tKHQX
Burst Read Cycle
Read Cycle
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August 2000
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White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
EDI2CG272128V
ADVANCED
WRITE CYCLE TIMING PARAMETERS
Description
Clock Cycle Time
Clock High Time
Clock Low Time
Address Setup
Address Hold
Bank Enable Setup
Bank Enable Hold
Global Write Enable Setup
Global Write Enable Hold
Data Setup
Data Hold
FIG. 5
Sym
tKHKH
tKHKL
tKLKH
tAVKH
tKHAX
tEVKH
tKHEX
tWVKH
tKHWX
tDVKH
tKHDX
8.5ns
Min
Max
9ns
Min
9
4
4
2.5
1.0
2.5
1.0
2.5
1.0
2.5
1.0
Max
Min
12
5
5
2.5
1.0
2.5
1.0
2.5
1.0
2.5
1.0
12ns
Max
15ns
Min Max
15
5
5
2.5
1.0
2.5
1.0
2.5
1.0
2.5
1.0
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYNCHRONOUS (NON-BURST) WRITE CYCLE
tKHKH
tKHKL
tAVKH
tKHAX
tKLKH
CK
Ex#
ADDR
Addr 1
Addr 1
Addr 2
tKHGWH
tGWLKH
GW#
G#
G#
tKHGH
DQ
tKHDX
tDVKH
tGHKH
Write Cycle
Back to Back Writes
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August 2000
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White Electronic Designs
EDI2CG272128V
ADVANCED
FIG. 6
SYNCHRONOUS-BURST WRITE CYCLE
tKHKH
tKLKH
tKHKL
CK
ADSP#
ADSC#
tAVKH
tKHAX
ADDR
BWx#,
GW#
tEVKH
tKHEX
Ex#
tAVVKH
tKHAVX
ADV#
G#
tDVKH
tKHQX
DQ
tKHQX
Early Write Cycle
Burst - Late Write- Cycle
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August 2000
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White Electronic Designs
EDI2CG272128V
ADVANCED
FIG. 7
SYNCHRONOUS (NON-BURST) READ/WRITE CYCLE
tKHKH
tKHKL
tKLKH
CK
tAVKH
Ex#
ADDR
G#
Addr 1
Addr 2
tKHQV
tKHDX
GW#
tKHQX
DQ
Q (Addr 1)
D (Addr 2)
tDVKH
Read Cycle
tKHDX
Write Cycle
Back to Back Cycles
G# Controlled
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
August 2000
Rev. 0
11
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
White Electronic Designs
EDI2CG272128V
ADVANCED
PACKAGE DESCRIPTION: 144 Lead SMALL OUTLINE DIMM
Package No. 409
0.175
MAX.
R9
R11
R3
R1
2.667 MAX.
0.157
U1
R17
0.788
R15
R7
R13
R5
1.000
MAX.
R18
U3
P1
0.181 TYP
0.913
1.112
1.291
1.490
ALL DIMENSIONS ARE IN INCHES
ORDERING INFORMATION
Part Number
Organization
Voltage
Speed (ns)
Package
EDI2CG272128V85D1*
2x128Kx72
3.3
8.5
144 Small Outline DIMM
EDI2CG272128V9D1*
2x128Kx72
3.3
9
144 Small Outline DIMM
EDI2CG272128V12D1
2x128Kx72
3.3
12
144 Small Outline DIMM
EDI2CG272128V15D1
2x128Kx72
3.3
15
144 Small Outline DIMM
*Consult Factory for Availability
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
August 2000
Rev. 0
12
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
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