Digital Power Monitor
with Convert Pin and ALERTB Output
ADM1191
FEATURES
Powered from 3.15 V to 26 V
Precision current sense amplifier
Precision voltage input
12-bit ADC for current and voltage readback
Convert pin (CONV) for commanding an ADC read
SETV input for setting overcurrent alert threshold
ALERTB output provides an overcurrent interrupt
I2C® fast mode-compliant interface (400 kHz maximum)
Two address pins allow 16 devices on the same bus
10-lead MSOP
FUNCTIONAL BLOCK DIAGRAM
CONV
ADM1191
V
VCC
I
A
SDA
0
I2 C
12-BIT
ADC
SCL
A1
1
SENSE
MUX
CURRENT
SENSE
AMPLIFIER
A0
ALERT
ALERTB
SETV
APPLICATIONS
GENERAL DESCRIPTION
The ADM1191 is an integrated current sense amplifier that
offers digital current and voltage monitoring via an on-chip,
12-bit analog-to-digital converter (ADC), communicated
through an I2C interface.
An internal current sense amplifier senses voltage across the sense
resistor in the power path via the VCC pin and the SENSE pin.
A 12-bit ADC can measure the current seen in the sense
resistor, as well as the supply voltage on the VCC pin.
An industry-standard I2C interface allows a controller to read
current and voltage data from the ADC. Measurements can be
initiated by an I2C command or via the convert (CONV) pin.
The CONV pin is especially useful for synchronizing reads on
multiple ADM1191 devices. Alternatively, the ADC can run
continuously, and the user can read the latest conversion data
whenever it is required. Up to 16 unique I2C addresses can be
created, depending on the way the A0 pin and the A1 pin are
connected.
A SETV pin is also included. A voltage applied to this pin is
internally compared to the output voltage on the current sense
amplifier. The output of the SETV comparator asserts when the
current sense amplifier ouput exceeds the SETV voltage. When
this event occurs, the ALERTB output asserts.
05804-001
GND
Figure 1.
3.15V TO 26V
RSENSE
VCC
SENSE
ALERTB
CONTROLLER
INTERRUPT
ADM1191
P = VI
SDA
SCL
SETV
CONV
GND
SDA
SCL
CONV
A1
A0
05804-002
Power monitoring/power budgeting
Central office equipment
Telecommunication and data communication equipment
PCs/servers
COMPARATOR
Figure 2. Applications Diagram
The ALERTB output can be used as a flag to warn a microcontroller or field programmable gate array (FPGA) of an
overcurrent condition. ALERTB outputs of multiple ADM1191
devices can be tied together and used as a combined alert.
The ADM1191 is packaged in a 10-lead MSOP.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
ADM1191
TABLE OF CONTENTS
Features .............................................................................................. 1
Identifying the ADM1191 on the I2C Bus..................................9
Applications....................................................................................... 1
General I2C Timing.......................................................................9
General Description ......................................................................... 1
Timing Diagrams ....................................................................... 10
Functional Block Diagram .............................................................. 1
Write and Read Operations ...................................................... 11
Revision History ............................................................................... 2
Quick Command........................................................................ 11
Specifications..................................................................................... 3
Write Command Byte ................................................................ 11
Absolute Maximum Ratings............................................................ 5
Write Extended Byte .................................................................. 12
Thermal Characteristics .............................................................. 5
Read Voltage and/or Current Data Bytes ................................ 13
ESD Caution.................................................................................. 5
ALERTB Output......................................................................... 14
Pin Configuration and Function Descriptions............................. 6
SETV Pin ..................................................................................... 14
Typical Performance Characteristics ............................................. 7
Kelvin Sense Resistor Connection ........................................... 14
Voltage and Current Readback ....................................................... 9
Outline Dimensions ....................................................................... 15
Serial Bus Interface....................................................................... 9
Ordering Guide .......................................................................... 15
REVISION HISTORY
9/06—Revision 0: Initial Version
Rev. 0 | Page 2 of 16
ADM1191
SPECIFICATIONS
VCC = 3.15 V to 26 V; TA = −40°C to +85°C; typical values at TA = 25°C, unless otherwise noted.
Table 1.
Parameter
VCC PIN
Operating Voltage Range, VVCC
Supply Current, ICC
Undervoltage Lockout, VUVLO
Undervoltage Lockout Hysteresis, VUVLOHYST
CONV PIN
Input Current, ICONV
Logic Low Threshold, VCONVL
Logic High Threshold, VCONVH
MONITORING ACCURACY 1
Current Sense Absolute Accuracy
Min
Typ
3.15
1.7
2.8
80
−2
26
2
V
mA
V
mV
+2
1.2
Conditions
VCC rising
μA
V
mV
−1.45
+1.45
%
VSENSE = 75 mV
0°C to +70°C
−1.8
+1.8
%
VSENSE = 50 mV
0°C to +70°C
−2.8
+2.8
%
VSENSE = 25 mV
0°C to +70°C
−5.7
+5.7
%
VSENSE = 12.5 mV
0°C to +70°C
−1.5
+1.5
%
VSENSE = 75 mV
0°C to +85°C
−1.8
+1.8
%
VSENSE = 50 mV
0°C to +85°C
−2.95
+2.95
%
VSENSE = 25 mV
0°C to +85°C
−6.1
+6.1
%
VSENSE = 12.5 mV
0°C to +85°C
−1.95
+1.95
%
VSENSE = 75 mV
−40°C to +85°C
−2.45
+2.45
%
VSENSE = 50 mV
−40°C to +85°C
−3.85
+3.85
%
VSENSE = 25 mV
−40°C to +85°C
+6.7
%
VSENSE = 12.5 mV
−40°C to +85°C
mV
This is an absolute value to be used
when converting ADC codes to current
readings; any inaccuracy in this value is
factored into absolute current accuracy
values (see specs for Current Sense
Absolute Accuracy)
0°C to +70°C
VCC = 3.0 V to 5.5 V
(low range)
0°C to +70°C
VCC = 10.8 V to
16.5 V (high range)
0°C to +85°C
VCC = 3.0 V to 5.5 V
(low range)
0°C to +85°C
VCC = 10.8 V to
16.5 V (high range)
VVCC = 3.0 V to 5.5 V −40°C to +85°C
(low range)
−40°C to +85°C
VVCC = 10.8 V to
16.5 V (high range)
These are absolute values to be used
when converting ADC codes to voltage
readings; any inaccuracy in these values
is factored into voltage accuracy values
(see specs for Voltage Accuracy)
−6.7
105.84
−0.85
+0.85
%
−0.9
+0.9
%
−0.85
+0.85
%
−0.9
+0.9
%
−0.9
+0.9
%
−1.15
+1.15
%
VCC for ADC Full Scale,
Low Range (VRANGE = 1)
VCC for ADC Full Scale,
High Range (VRANGE = 0)
SENSE PIN
Input Current, ISENSE
Unit
1.4
VSENSE for ADC Full Scale
Voltage Accuracy
Max
−1
6.65
V
26.52
V
+1
Rev. 0 | Page 3 of 16
μA
VSENSE = VVCC
ADM1191
Parameter
SETV PIN
Overcurrent Trip Threshold
Overcurrent Trip, Gain {VSETV/(VVCC − VSENSE)}
Input Current, ISETVLEAK
ALERTB PIN
Output Low Voltage, VALERTOL
Input Current, IALERT
A0 PIN, A1 PIN
Set Address to 00, VADRLOWV
Set Address to 01, RADRLOWZ
Set Address to 10, IADRHIGHZ
Set Address to 11, VADRHIGHV
Input Current for 00 Decode, IADRLOW
Input Current for 11 Decode, IADRHIGH
I2C TIMING
Low Level Input Voltage, VIL
High Level Input Voltage, VIH
Low Level Output Voltage on SDA, VOL
Output Fall Time on SDA from VIHMIN to VILMAX
Maximum Width of Spikes Suppressed by
Input Filtering on SDA and SCL Pins
Input Current, II, on SDA/SCL When Not
Driving Out a Logic Low
Input Capacitance on SDA/SCL
SCL Clock Frequency, fSCL
Low Period of the SCL Clock
High Period of the SCL Clock
Setup Time for Repeated Start Condition, tSU;STA
SDA Output Data Hold Time, tHD;DAT
Setup Time for a Stop Condition, tSU;STO
Bus Free Time Between a Stop and a Start
Condition, tBUF
Capacitive Load for Each Bus Line
1
Min
Typ
Max
Unit
Conditions
98
49.5
100
50
18
102
50.5
mV
mV
+1
μA
VSETV = 1.8 V
VSETV = 0.9 V
VSETV = 0.9 V to 1.9 V
VSETV = 0.9 V to 1.9 V
−1
0.1
1.5
+1
V
mA
μA
IALERT = −100 μA
IALERT = −2 mA
VALERT = VCC; ALERTB not asserted
0
80
0.8
160
V
kΩ
+0.3
μA
5.5
6
V
μA
μA
Low state
Resistor to ground state, load pin with
specified resistance for 01 decode
Open state, maximum load allowed on
A0 pin or A1 pin for 10 decode
High state
VADR = 2.0 V to 5.5 V
VADR = 0 V to 0.8 V
0.3 VBUS
IOL = 3 mA
CB = bus capacitance from SDA to GND
−1
0.05
1
120
−0.3
2
−40
3
−25
20 +
0.1 CB
50
0.4
250
V
V
V
ns
250
ns
−10
+10
μA
0.7 VBUS
5
400
600
1300
600
100
600
1300
900
400
pF
kHz
ns
ns
ns
ns
ns
ns
pF
Monitoring accuracy is a measure of the error in a code that is read back for a particular voltage/current. This is a combination of amplifier error, reference
error, ADC error, and error in ADC full-scale code conversion factor.
Rev. 0 | Page 4 of 16
ADM1191
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
VCC Pin
SENSE Pin
CONV Pin
SETV Pin
ALERTB Pin
SDA Pin, SCL Pin
A0 Pin, A1 Pin
Storage Temperature Range
Operating Temperature Range
Lead Temperature (Soldering, 10 sec)
Junction Temperature
THERMAL CHARACTERISTICS
Rating
30 V
30 V
−0.3 V to +6 V
30 V
30 V
−0.3 V to +6 V
−0.3 V to +6 V
−65°C to +125°C
−40°C to +85°C
300°C
150°C
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 3. Thermal Resistance
Package Type
10-Lead MSOP
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. 0 | Page 5 of 16
θJA
137.5
Unit
°C/W
ADM1191
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
10
ALERTB
SENSE 2
9
A1
8
A0
GND 4
7
SDA
SETV 5
6
SCL
CONV 3
TOP VIEW
(Not to Scale)
05804-003
ADM1191ARMZ
VCC 1
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1
Mnemonic
VCC
2
SENSE
3
CONV
4
5
GND
SETV
6
7
8
SCL
SDA
A0
9
A1
10
ALERTB
Description
Positive Supply Input Pin. The operating supply voltage range is from 3.15 V to 26 V. An undervoltage lockout
(UVLO) circuit resets the ADM1191 when a low supply voltage is detected.
Current Sense Input Pin. A sense resistor between the VCC pin and the SENSE pin generates a voltage across
a sense resistor. This voltage is proportional to the load current. A current sense amplifier amplifies this
voltage before it is digitized by the ADC.
Convert Start Pin. A high level on this pin enables an ADC conversion. The state of an internal control register,
which is set through the I2C interface, configures the part to convert current only, voltage only, or both
channels when the convert pin is asserted.
Chip Ground Pin.
Input Pin. The voltage driven onto this pin is compared to the output of the internal current sense amplifier.
The lower the voltage on the SETV, the lower the current level that causes the ALERTB output to assert.
I2C Clock Pin. Open-drain input; requires an external resistive pull-up.
I2C Data I/O Pin. Open-drain input/output; requires an external resistive pull-up.
I2C Address Pin. This pin can be tied low, tied high, left floating, or tied low through a resistor. Sixteen different
I2C address options are available, depending on the external configuration of the A0 pin and the A1 pin.
I2C Address Pin. This pin can be tied low, tied high, left floating, or tied low through a resistor. Sixteen different
I2C address options are available, depending on the external configuration of the A0 pin and the A1 pin.
Alert Output Pin. Active-low, open-drain configuration. This pin asserts low when an overcurrent condition is
present. The level at which an overcurrent condition is detected depends on the voltage on the SETV pin.
Rev. 0 | Page 6 of 16
ADM1191
TYPICAL PERFORMANCE CHARACTERISTICS
1000
2.0
900
HITS PER CODE (1000 READS)
1.8
1.6
ICC (mA)
1.4
1.2
1.0
0.8
0.6
800
700
600
500
400
300
200
0.4
100
0
0
4
8
12
16
20
24
28
VCC (V)
2046
05804-021
0
Figure 4. Supply Current vs. Supply Voltage
2047
2048
2049
2050
CODE
05804-060
0.2
Figure 7. ADC Noise, Current Channel, Midcode Input, 1000 Reads
1000
2.0
900
HITS PER CODE (1000 READS)
1.8
1.6
ICC (mA)
1.4
1.2
1.0
0.8
0.6
800
700
600
500
400
300
200
0.4
100
0
–20
0
20
40
60
779
05804-022
0
–40
80
TEMPERATURE (°C)
10 DECODE
782
783
Figure 8. ADC Noise, 14:1 Voltage Channel, 5 V Input, 1000 Reads
1000
01 DECODE 00 DECODE
HITS PER CODE (1000 READS)
900
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
800
700
600
500
400
300
200
0
0
–35
–30
–25
–20
–15
–10
–5
0
5
I (A0/A1) (µA)
10
3078
3079
3080
3081
3082
CODE
Figure 6. Address Pin Voltage vs. Address Pin Current
for Four Addressing Options
Figure 9. ADC Noise, 7:1 Voltage Channel, 5 V Input, 1000 Reads
Rev. 0 | Page 7 of 16
05804-062
100
05804-026
V (A0/A1)
11 DECODE
781
CODE
Figure 5. Supply Current vs. Temperature
3.2
3.0
2.8
780
05804-061
0.2
ADM1191
0.60
4
0.55
3
0.50
0.45
ALERTB LOW (V)
2
INL (LSB)
1
0
–1
0.40
0.35
0.30
0.25
0.20
0.15
–2
0.10
–3
500
1000
1500
2000
2500
3000
3500
4000
CODE
0
–40
05804-023
0
–20
0
20
40
60
05804-047
0.05
–4
80
TEMPERATURE (°C)
Figure 10. INL for ADC
Figure 13. ALERTB Output Low Voltage vs. Temperature @ 1 mA
1.0
4
3
0.8
OUTPUT LOW (V)
DNL (LSB)
2
1
0
–1
0.6
0.4
–2
0.2
0
500
1000
1500
2000
2500
3000
3500
4000
CODE
0
05804-024
4
6
8
10
12
14
16
18
20
22
24
26
28
Figure 14. ALERTB Output Low Voltage vs. Supply @ 1 mA
2.0
100
1.8
90
1.6
80
1.4
OUTPUT LOW (V)
70
60
50
40
1.2
1.0
0.8
30
0.6
20
0.4
10
0.2
0
0.2
0.4
0.6
0.8
1.0
1.2
VSETV (V)
1.4
1.6
1.8
2.0
05804-046
VLIM (mV)
2
VCC (V)
Figure 11. DNL for ADC
0
0
Figure 12. VLIM vs. VSETV
0
0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
LOAD CURRENT (mA)
Figure 15. ALERTB Output Low Voltage vs. Load Current
Rev. 0 | Page 8 of 16
05804-049
–4
05804-048
–3
ADM1191
VOLTAGE AND CURRENT READBACK
The ADM1191 contains the components to allow voltage and
current readback over an Inter-IC (I2C) bus. The voltage output
of the current sense amplifier and the voltage on the VCC pin
are fed into a 12-bit ADC via a multiplexer. The device can be
instructed to convert voltage and/or current at any time during
operation via an I2C command or by driving the CONV pin high.
When all conversions are complete, the voltage and/or current
values can be read out to 12-bit accuracy in two or three bytes.
1.
SERIAL BUS INTERFACE
Control of the ADM1191 is carried out via the serial system
management bus (I2C). This interface is compatible with I2C
fast mode (400 kHz maximum). The ADM1191 is connected to
this bus as a slave device, under the control of a master device.
The peripheral whose address corresponds to the transmitted
address responds by pulling the data line low during the
low period before the ninth clock pulse, known as the
acknowledge bit, and holding it low during the high period
of this clock pulse. All other devices on the bus remain idle
while the selected device waits for data to be read from it
or written to it. If the R/W bit is 0, the master writes to the
slave device. If the R/W bit is 1, the master reads from the
slave device.
IDENTIFYING THE ADM1191 ON THE I2C BUS
The ADM1191 has a 7-bit serial bus slave address. When the
device powers up, it does so with a default serial bus address.
The three MSBs of the address are set to 010; the four LSBs are
determined by the state of the A0 pin and the A1 pin. There are
16 different configurations available on the A0 pin and A1 pin
that correspond to 16 different I2C addresses for the four LSBs
(see Table 5). This scheme allows 16 ADM1191 devices to operate
on a single I2C.
2.
Table 5. Setting I2C Addresses via the A0 Pin and the A1 Pin
A0 Configuration
Low state
Low state
Low state
Low state
Resistor to GND
Resistor to GND
Resistor to GND
Resistor to GND
Floating
Floating
Floating
Floating
High state
High state
High state
High state
A1 Configuration
Low state
Resistor to GND
Floating
High state
Low state
Resistor to GND
Floating
High state
Low state
Resistor to GND
Floating
High state
Low state
Resistor to GND
Floating
High state
Address
0x60
0x68
0x70
0x78
0x62
0x6A
0x72
0x7A
0x64
0x6C
0x74
0x7C
0x66
0x6E
0x76
0x7E
The master initiates data transfer by establishing a start
condition, defined as a high-to-low transition on the serial
data line, SDA, while the serial clock line, SCL, remains
high. This indicates that a data stream follows. All slave
peripherals connected to the serial bus respond to the start
condition and shift in the next eight bits, consisting of a 7bit slave address (MSB first) plus an R/W bit that
determines the direction of the data transfer; that is,
whether data is written to or read from the slave device
(0 = write, 1 = read).
Data is sent over the serial bus in sequences of nine clock
pulses: eight bits of data followed by an acknowledge bit
from the slave device. Data transitions on the data line
must occur during the low period of the clock signal and
remain stable during the high period, because a low-tohigh transition when the clock is high can be interpreted as
a stop signal.
If the operation is a write operation, the first data byte after
the slave address is a command byte. This tells the slave
device what to expect next. It can be an instruction, such
as telling the slave device to expect a block write, or it can
be a register address that tells the slave where subsequent
data is to be written.
Because data can flow in only one direction, as defined by
the R/W bit, it is not possible to send a command to a slave
device during a read operation. Before doing a read
operation, it may first be necessary to do a write operation
to tell the slave what sort of read operation to expect and/or
the address from which data is to be read.
3.
GENERAL I2C TIMING
Figure 16 and Figure 17 show timing diagrams for general read
and write operations using the I2C. The I2C specification defines
conditions for different types of read and write operations, which
are discussed later. The general I2C protocol operates as follows:
Rev. 0 | Page 9 of 16
When all data bytes have been read or written, stop
conditions are established. In write mode, the master pulls
the data line high during the 10th clock pulse to assert a
stop condition. In read mode, the master device releases the
SDA line during the low period before the ninth clock
pulse, but the slave device does not pull it low. This is
known as a no acknowledge. The master then takes the data
line low during the low period before the 10th clock pulse,
then high during the 10th clock pulse to assert a stop
condition.
ADM1191
TIMING DIAGRAMS
9
1
9
1
SCL
0
SDA
0
1
1
A1
1
A0
D7
R/W
D6
D5
ACKNOWLEDGE BY
SLAVE
START BY MASTER
FRAME 1
SLAVE ADDRESS
1
D4
D2
D3
D0
D1
ACKNOWLEDGE BY
SLAVE
FRAME 2
COMMAND CODE
1
9
9
SCL
(CONTINUED)
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
ACKNOWLEDGE BY
SLAVE
FRAME 3
DATA BYTE
D3
D2
D1
D0
ACKNOWLEDGE BY STOP
BY
SLAVE
MASTER
FRAME N
DATA BYTE
05804-004
SDA
(CONTINUED)
Figure 16. General I2C Write Timing Diagram
9
1
9
1
SCL
0
SDA
0
1
1
A1
1
A0
D7
R/W
D6
D5
D4
ACKNOWLEDGE BY
SLAVE
START BY MASTER
FRAME 1
SLAVE ADDRESS
1
D2
D3
D0
D1
ACKNOWLEDGE BY
MASTER
FRAME 2
DATA BYTE
1
9
9
SCL
(CONTINUED)
D7
D6
D5
D4
D3
FRAME 3
DATA BYTE
D2
D1
D0
D7
D6
D5
ACKNOWLEDGE BY
MASTER
D4
D3
FRAME N
DATA BYTE
D2
D1
D0
NO ACKNOWLEDGE STOP
BY
MASTER
2
Figure 17. General I C Read Timing Diagram
tLOW
tR
tHD;STA
tF
SCL
tHD;STA
tSU;STA
tHIGH
tHD;DAT
tSU;DAT
tSU;STO
tBUF
P
S
S
Figure 18. Serial Bus Timing Diagram
Rev. 0 | Page 10 of 16
P
05804-006
SDA
05804-005
SDA
(CONTINUED)
ADM1191
WRITE COMMAND BYTE
WRITE AND READ OPERATIONS
The I C specification defines several protocols for different
types of read and write operations. The operations used in the
ADM1191 are discussed in the sections that follow. Table 6
shows the abbreviations used in the command diagrams.
In the write command byte operation, the master device sends
a command byte to the slave device, as follows:
1.
The master device asserts a start condition on SDA.
Table 6. I2C Abbreviations
2.
The master sends the 7-bit slave address, followed by the
write bit (low).
3.
The addressed slave device asserts an acknowledge on SDA.
4.
The master sends the command byte. The command byte
is identified by an MSB = 0. An MSB =1 indicates an
extended register write (see the Write Extended Byte
section).
QUICK COMMAND
5.
The slave asserts an acknowledge on SDA.
The quick command operation allows the master to check if the
slave is present on the bus, as follows:
6.
The master asserts a stop condition on SDA to end the
transaction.
Abbreviation
S
P
R
W
A
N
1.
Condition
Start
Stop
Read
Write
Acknowledge
No acknowledge
The master device asserts a start condition on SDA.
1
2.
The master sends the 7-bit slave address, followed by the
write bit (low).
3.
The addressed slave device asserts an acknowledge on SDA.
2
3
4
5 6
SLAVE
COMMAND
S ADDRESS W A
A P
BYTE
05804-008
2
Figure 20. Write Command Byte
2
3
SLAVE
S ADDRESS W A
05804-007
1
The seven LSBs of the command byte are used to configure and
control the ADM1191. Table 7 provides details of the function
of each bit.
Figure 19. Quick Command
Table 7. Command Byte Operations
Bit
Default
Name
C0
0
V_CONT
C1
0
V_ONCE
C2
0
I_CONT
C3
0
I_ONCE
C4
0
VRANGE
C5
C6
0
0
N/A
STATUS_RD
Function
Set to convert voltage continuously. If readback is attempted before the first conversion is complete,
the ADM1191 asserts an acknowledge and returns all 0s in the returned data.
Set to convert voltage once. Self-clears. I2C asserts a no acknowledge on attempted reads until the ADC
conversion is complete.
Set to convert voltage continuously. If readback is attempted before the first conversion is complete,
the ADM1191 asserts an acknowledge and returns all 0s in the returned data.
Set to convert current once. Self-clears. I2C asserts a no acknowledge on attempted reads until the ADC
conversion is complete.
Selects different internal attenuation resistor networks for voltage readback. A 0 in C4 selects a 14:1 voltage
divider. A 1 in C4 selects a 7:2 voltage divider. With an ADC full scale of 1.902 V, the voltage at the VCC pin for
an ADC full-scale result is 26.52 V for VRANGE = 0 and 6.65 V for VRANGE = 1.
Unused,
Status Read. When this bit is set, the data byte read back from the ADM1191 is the STATUS byte. It contains
the status of the device alerts. See Table 15 for full details of the STATUS byte.
Rev. 0 | Page 11 of 16
ADM1191
WRITE EXTENDED BYTE
1.
The master device asserts a start condition on SDA.
2.
The master sends the 7-bit slave address, followed by the
write bit (low).
3.
The addressed slave device asserts an acknowledge on SDA.
4.
The master sends the register address byte. The MSB of
this byte is set to 1 to indicate an extended register write.
The two LSBs indicate which of the three extended registers is
to be written to (see Table 8). All other bits should be set to 0.
5.
The slave asserts an acknowledge on SDA.
6.
The master sends the command byte. The command byte
is identified by an MSB = 0. An MSB = 1 indicates an
extended register write.
7.
The slave asserts an acknowledge on SDA.
8.
The master asserts a stop condition on SDA to end the
transaction.
1
2
3
4
5
6
7 8
SLAVE
REGISTER
REGISTER
S ADDRESS W A ADDRESS A
A P
DATA
05804-009
In the write extended byte operation, the master device writes
to one of the three extended registers of the slave device, as follows:
Figure 21. Write Extended Byte
Table 9, Table 10, and Table 11 give details of each extended
register.
Table 8. Extended Register Addresses
A6
0
0
0
A5
0
0
0
A4
0
0
0
A3
0
0
0
A2
0
0
0
A1
0
1
1
A0
1
0
1
Extended Register
ALERT_EN
ALERT_TH
CONTROL
Table 9. ALERT_EN Register Operations
Bit
0
Default
0
Name
EN_ADC_OC1
1
0
EN_ADC_OC4
2
1
EN_OC_ALERT
3
4
0
0
EN_OFF_ALERT
CLEAR
Function
Enabled if a single ADC conversion on the I channel has exceeded the threshold set in the ALERT_TH
register.
Enabled if four consecutive ADC conversions on the I channel have exceeded the threshold set in the
ALERT_TH register.
Enables the OC_ALERT register. If an overcurrent condition is present, the OC_ALERT register captures
and latches this condition.
N/A.
Clears the ON_ALERT, OC_ALERT, and ADC_ALERT status bits in the status register. These can immediately
reset if the source of the alert has not been cleared or disabled with the other bits in this register. This bit
self-clears to 0 after the status register bits have been cleared.
Table 10. ALERT_TH Register Operations
Bit
7:0
Default
FF
Function
The ALERT_TH register sets the current level at which an alert occurs. Defaults to ADC full scale. The ALERT_TH 8-bit
number corresponds to the top eight bits of the current channel data.
Table 11. CONTROL Register Operations
Bit
0
Default
0
Name
SWOFF
Function
Forces the ALERTB pin to deassert. Can be active only if the EN_OFF_ALERT bit is high (see Table 9).
Rev. 0 | Page 12 of 16
ADM1191
READ VOLTAGE AND/OR CURRENT DATA BYTES
For cases where the master is reading voltage only or current
only, only two data bytes are read. Step 7 and Step 8 are not
required.
1
Voltage and Current Readback
2
2
3
6
7
8
9 10
B6
V10
B5
V9
B4
V8
B3
V7
B2
V6
B1
V5
B0
V4
I11
I10
I9
I8
I7
I6
I5
I4
V3
V2
V1
V0
I3
I2
I1
I0
Voltage Readback
The ADM1191 digitizes voltage only. Two bytes are read out of
the device in the format shown in Table 13.
B1
V5
0
B0
V4
0
3
4
5
6
7 8
Figure 23. Two-Byte Read from ADM1191
Converting ADC Codes to Voltage and Current Readings
The following equations can be used to convert ADC codes
representing voltage and current from the ADM1175 12-bit
ADC into actual voltage and current values.
Voltage = (VFULLSCALE/4096) × Code
Table 13. Voltage Only Readback Format
B7 B6 B5 B4 B3 B2
V11 V10 V9 V8 V7 V6
V3 V2 V1 V0 0
0
2
SLAVE
REGISTER
REGISTER
S ADDRESS R A ADDRESS A
N P
DATA
05804-011
1
B7
V11
Byte Contents
1
Voltage MSBs
2
Voltage LSBs
5
Figure 22. Three-Byte Read from ADM1191
Table 12. Voltage and Current Readback
Contents
Voltage
MSBs
Current
MSBs
LSBs
4
SLAVE
S ADDRESS R A DATA 1 A DATA 2 A DATA 3 N P
The ADM1191 digitizes both voltage and current. Three bytes
are read out of the device in the format shown in Table 12.
Byte
1
3
05804-010
The ADM1191 can be set up to provide information in three
different ways (see the Write Command Byte section). Depending
on how the device is configured, the following data can be read
out of the device after a conversion (or conversions).
where:
VFULLSCALE = 6.65 (7:2 range) or 26.52 (14:1 range).
Code is the ADC voltage code read from the device (Bit V0
to Bit V11).
Current Readback
The ADM1191 digitizes current only. Two bytes are read out of
the device in the format shown in Table 14.
Table 14. Current Only Readback Format
Byte Contents
1
Current MSBs
2
Current LSBs
B7
I11
I3
B6
I10
I2
B5 B4 B3 B2
I9 I8 I7 I6
I1 I0 0
0
B1
I5
0
B0
I4
0
Current = ((IFULLSCALE/4096) × Code)/Sense Resistor
where:
IFULLSCALE = 105.84 mV.
Code is the ADC current code read from the device (Bit I0 to
Bit I11).
Read Status Register
The following series of events occurs when the master receives
three bytes (voltage and current data) from the slave device:
A single register of status data can also be read from the
ADM1191.
1.
The master device asserts a start condition on SDA.
1.
The master device asserts a start condition on SDA.
2.
The master sends the 7-bit slave address, followed by the
read bit (high).
2.
The master sends the 7-bit slave address, followed by the
read bit (high).
3.
The addressed slave device asserts an acknowledge on SDA.
3.
The addressed slave device asserts an acknowledge on SDA.
4.
The master receives the first data byte.
4.
The master receives the status byte.
5.
The master asserts an acknowledge on SDA.
5.
The master asserts an acknowledge on SDA.
6.
The master receives the second data byte.
7.
The master asserts an acknowledge on SDA.
8.
The master receives the third data byte.
9.
The master asserts a no acknowledge on SDA.
10. The master asserts a stop condition on SDA, and the
transaction ends.
2
3
4
5
SLAVE
S ADDRESS R A DATA 1 A
05804-012
1
Figure 24. Status Read from ADM1191
Table 15 shows the ADM1191 status registers in detail. Note
that Bit 1, Bit 3, and Bit 5 are cleared by writing to Bit 4 of the
ALERT_EN register (CLEAR).
Rev. 0 | Page 13 of 16
ADM1191
Table 15. Status Byte Operations
Bit
0
1
Name
ADC_OC
ADC_ALERT
2
OC
3
OC_ALERT
4
5
OFF_STATUS
OFF_ALERT
Function
An ADC-based overcurrent comparison has been detected on the last three conversions.
An ADC-based overcurrent trip has occurred, which has caused the alert. Cleared by writing to Bit 4 of the ALERT_EN
register.
An overcurrent condition is present (that is, the output of the current sense amplifier is greater than the voltage on the
SETV input).
An overcurrent condition has caused the ALERT block to latch a fault, and the ALERTB output has asserted. Cleared by
writing to Bit 4 of the ALERT_EN register.
Set to 1 by writing to the SWOFF bit of the CONTROL register.
An alert has been caused by the SWOFF bit. Cleared by writing to Bit 4 of the ALERT_EN register.
ALERTB OUTPUT
The ALERTB output is an open-drain pin with 30 V tolerance.
This output can be used as an overcurrent flag by connecting it
to the general-purpose logic input of a controller. Under normal
operation, this output is pulled high (an external pull-up resistor
should be used because this is an open-drain pin). When an
overcurrent condition occurs, the ADM1191 pulls this output low.
VCC
SENSE
ADM1191
A
CURRENT
SENSE
AMPLIFIER
RSENSE
APPLIED
VOLTAGE
SETV
SENSE
ALERTB
CONTROLLER
SDA
SCL
CLRB
COMPARATOR
ALERTB
ADM1191
SETV
Figure 26. SETV Operation
P = VI
SDA
SCL
KELVIN SENSE RESISTOR CONNECTION
CLRB
ADR
05804-013
TIMER
GND
ALERT
05804-014
VCC
ALERT
Figure 25. Using the ALERTB Output as an Interrupt
SETV PIN
The SETV pin allows the user to adjust the current level that
trips the ALERTB output. The output of the current sense
amplifier is compared with the voltage driven onto the SETV
pin. If the current sense amplifier output is higher than the
SETV voltage, then the output of the comparator asserts. By
driving a different voltage onto the SETV pin, the ADM1191
detects an overcurrent condition at a different current level,
with a gain of 18. See Figure 15 for an illustration of this
relationship.
When using a low value sense resistor for high current
measurement, the problem of parasitic series resistance can
arise. The lead resistance can be a substantial fraction of the
rated resistance, making the total resistance a function of lead
length. This problem can be avoided by using a Kelvin sense
connection. This type of connection separates the current path
through the resistor and the voltage drop across the resistor.
Figure 27 shows the correct way to connect the sense resistor
between the VCC pin and the SENSE pin of the ADM1191.
SENSE RESISTOR
CURRENT
FLOW FROM
SUPPLY
CURRENT
FLOW TO
LOAD
KELVIN SENSE TRACES
VCC
SENSE
ADM1191
Figure 27. Kelvin Sense Connections
Rev. 0 | Page 14 of 16
05804-015
3.15V TO 26V
ILOAD
RSENSE
ADM1191
OUTLINE DIMENSIONS
3.10
3.00
2.90
10
3.10
3.00
2.90
1
6
5.15
4.90
4.65
5
PIN 1
0.50 BSC
0.95
0.85
0.75
1.10 MAX
0.15
0.05
0.33
0.17
SEATING
PLANE
0.23
0.08
0.80
0.60
0.40
8°
0°
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-BA
Figure 28. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADM1191-2ARMZ-R7 1
EVAL-ADM1191EBZ1
1
Temperature Range
−40°C to +85°C
Package Description
10-Lead MSOP
Evaluation Board
Z = Pb-free part.
Rev. 0 | Page 15 of 16
Package Option
RM-10
Branding
M5L
ADM1191
NOTES
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent
Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05804-0-9/06(0)
Rev. 0 | Page 16 of 16