AMCC CS19205CBI 10 gigabit ethernet mac and phy/oc-192c pos framer/mapper Datasheet

KHATANGA
Product Brief
Part Number S19205CBI, Revision 1.4, October 2002
10 Gigabit Ethernet MAC and PHY/OC-192c POS Framer/Mapper
Features
• POS processing includes HDLC framing, payload scrambling (x43 +
1) and transparency processing.
• Single STS-192c/STM-64 framer/mapper device to support 10
Gigabit Ethernet (10GbE) serial WAN, serial LAN and STS-192c/
AU-4-64c POS applications.
• 10GbE MAC transmit processing includes frame assembly, pad
insertion, and CRC generation.
• Supports full duplex mapping of Ethernet frames into a single
SONET/SDH STS-192c/AU-4-64c (WIS functionality) in compliance
with IEEE P802.3ae / D2.0 proposed baseline specification for
10GbE over the WAN.
• Supports 802.3x PAUSE flow control.
• 10GbE MAC receive processing includes Ethernet framing, CRC
checking, and frame size monitoring.
• Provides counters to support implementation of RMON, 802.3
MIBs.
• SONET/SDH section/line/path processing compliant with Telcordia
GR-253, ANSI T1.105 and T1.416, and ITU G.751, G.783 and
G.804. Provides a subset of the full SONET/SDH processing which
implements the P802.3ae / D2.0 defined 10GbE WAN Interface
Sublayer (WIS).
• Provides a 622.08 MHz 16-bit bus interface on the line side in both
the TX and RX directions (SFI-4/XSBI compliant).
• Provides a 644 MHz 16-bit LVDS interface on the line side in both
TX and RX directions for LAN PHY applications (XSBI).
• Performs 10GbE MAC processing, compliant with IEEE P802.3ae /
D2.0.
• Provides a 64-bit, 200 MHz FlexBus-4TM system interface (SPI-4
Phase 1 compliant).
• Performs 64B/66B encoding in the TX direction and 64B/66B
decoding in the RX direction when operating in 10GbE mode.
• Direct Map Mode for mapping of any traffic type in SONET/SDH
STS-192c/AU-4-64c payloads
• A WIS bypass mode is provided, to support 10GbE serial LAN
applications.
• 16-bit synchronous microprocessor interface for configuration, control, and status monitoring.
• Supports external MAC implementations.
• Provides a 622.08 MHz 16-bit line bus to support Automatic Protection Switching (APS) configurations.
• Alternatively, supports full-duplex mapping of packets in a single
SONET/SDH STS-192c/AU-4-64c per IETF 2615 (POS).
• Packaged in a 624-pin CBGA.
• SONET/SDH processing includes termination and generation of
section, line, & path layers, with transport/section and path overhead interfaces in both transmit and receive directions.
• Implemented in .18 micron CMOS, 1.8V and 2.5V technology.
RDYB(DTACKB)
BU S M OD E
AP S_ IN TB
UPCLK
WRB(RWB)
ADDR[12:0]
CSN
RSTB
INTB
D[15:0]
GPIO[15:0]
TX_TOH_DATA_IN
TX_TOH_CLK_OUT
PROT_CLK _OUT
TX_TOH_FRM_OUT
SEL
GEN
64B66B
E
E
nn
cc
oo
dd
ee
rr
10G
MAC
FIFO
Control
STX_DATA_IN[63:0]
SEL
SYS_REFCLK_OUT
SYS_REFCLK_IN
S YS _ AS Y NC _ FR M _ IN
HDLC
Proc
64B66B
Decoder
10G
MAC
JTAG
TDO
TCK
TMS
TDI
TRSTB
TS_EN
PROT_CLK_IN
FRM
PROT_DATA_IN[15:0]
TOHEXTRACT
RX_ALM_OUT
RX_LOSEXT
RX_REFCLK_IN
LOC
DET
PTR
INT
SEL
FRAM
LBK
SEL
POH
MON
FInal Production Release Information - The information contained in this document is about a product in its fully tested and characterized stage. All features
described herein are supported. Contact AMCC for updates to this document and
the latest product status.
Empowering Intelligent Optical Networks
S EL
HDLC
Proc
R X_ TOH _ FR M _ OU T
RX_CLK_IN
MUX
TOH
MON.
FRMR
RX_TOH_CLK_OUT
RX_DATA_IN[15:0]
FRG
E
N
F
R
TX
SYSTEM
INTRFC
MICROPROCESSOR I/F
SPE
RX_TOH_DATA_OUT
TX_CLK_OUT
TX_DATA_OUT[15:0]
TOHINSERT
MUX
SEL
LINE SIDE INTERFACE
PROT_DATA_OUT[15:0]
Figure 1: Block Diagram
SYSTEM
INTRFC
FIFO
SRX_DATA_OUT[63:0]
Control
KHATANGA
Product Brief
Part Number S19205CBI, Revision 1.4, October 2002
10 Gigabit Ethernet MAC and PHY/OC-192c POS Framer/Mapper
Overview and Applications
The S19205 is a dense VLSI device that integrates a 10GbE MAC,
a 64B/66B Physical Coding Sublayer (PCS) and a WAN Interface
Sublayer (WIS) as baselined by the IEEE P802.3ae task force.
Optionally, it can be configured to perform full-duplex mapping of
packets into SONET/SDH payloads at OC-192c rate (POS). When
configured for SONET/SDH operation, the S19205 supports Automatic Protection Switching (APS) as required in carrier-class equipment.
SONET/SDH Processing (WIS)
The S19205 implements SONET/SDH processing functions for a
single STS-192/STM-64 data stream. The S19205 performs full section, line, and path overhead processing of all defined TOH/POH
bytes, including framing, scrambling/descrambling, alarm signal
(AIS) insertion/detection, remote failure insertion/detection (REI/
RDI), section/path trace insertion/capture (J0/J1) and bit interleaved
parity (B1/B2/B3) processing. The S19205 provides programmable
Signal Fail (SF) and Signal Degrade (SD) thresholds for B2 and B3
monitoring.
The S19205 is SONET and SDH standards compliant with Telcordia
GR-253, GR-499 and GR-1377, and ANSI T1. 105-1995, and ITU
G.707 and G.783.
POS HDLC Processing
The S19205 can be configured for HDLC processing for STS-192c/
AU-4-64c POS applications. When configured for POS HDLC processing, the S19205’s transmit HDLC processor will provide the
insertion of HDLC framed packets into the STS SPE. It will perform
packet framing, provide interframe fill and TX FIFO error recovery.
In addition, it optionally performs payload scrambling (x43 + 1), performs transparency processing as required by RFC 2615 and will
optionally generate a 32 bit CRC.
The receive HDLC processor provides for the extraction of HDLC
frames, transparency removal, de-scrambling (if enabled), FCS
error checking and optionally deletes the HDLC address and control
fields. The S19205 also provides a robust set of counters and status/control registers for performance monitoring via the microprocessor.
It is SONET/SDH standards compliant IETF RFC 1662 and RFC
2615.
10 Gigabit Ethernet MAC Processing
The MAC block also integrates an extensive set of counters for network statistics collection in support of RMON and IETF standard
MIBs.
The MAC supports flow control for both serial LAN (10Gbps) or
WAN (9.95Gbps) applications through the 802.3x MAC ‘PAUSE’
functionality.
64B/66B Encoder / Decoder
When configured for Ethernet operation, the PCS sublayer performs
frame scrambling and bit ordering before passing data to the WAN
Interface Sublayer or to the XSBI interface. 64B/66B block coding is
used to guarantee run length, transition density and DC balance of
the serial data stream. Data frames are delineated using “01” sync
header. Control frames are identified with a “10” sync header.
Line-side Interface
In 10GbE WAN PHY and OC-192c POS mode, the line-side interface supports a 16-bit parallel bus operating at 622.08 MHz, compliant with the OIF SFI-4 and the proposed IEEE P802.3ae XSBI
interfaces. In 10GbE LAN PHY mode, the line side interface operates as a XSBI-compliant 16-bit LVDS parallel interface operating at
644.53MHz.
System Interface
A 64-bit, 200MHz FlexBus-4TM interface is used for transferring
packets on the system side. FlexBus-4TM is compliant to the OIF
SPI-4 Phase 1 Specification.
Microprocessor Interface
The user of the S19205 can select between an 8-bit asynchronous
or a 16-bit synchronous microprocessor interface for device control
and monitoring. The interface supports both Intel and Motorola type
microprocessors, and is capable of operating in either an interrupt
driven or polled-mode configurations.
Applications
•
Core switches/routers
•
Multi-service switches
•
MAN switches
•
Direct Mapping of any traffic type in SONET/SDH
STS-192c/AU-4-64c payloads
The 10GbE Medium Access Control block supports full-duplex traffic at 10Gbps rates. In the transmit direction, it performs encapsulation of packets received through the system interface into Ethernet
frames. It provides pad insertion to insure a minimum frame length,
as well as CRC generation. The MAC processing block also provides for preamble, SFD and IFG generation.
In the receive direction, the MAC processing consists of Ethernet
framing and CRC validation, as well as monitoring of the size of the
received frame.
2
Empowering Intelligent Optical Networks
KHATANGA
Product Brief
Part Number S19205CBI, Revision 1.4, October 2002
10 Gigabit Ethernet MAC and PHY/OC-192c POS Framer/Mapper
Figure 2: Typical Application
Microprocessor
Control
Control
Addr
Data
Reference
Clock
PPP or Ethernet data
TX_SONETCLK
SerTxD±
SONET
SDH
Line Side
Interface
Fiber Optic
Transceiver
SerRxD±
TX_DATA_OUT[15:0]
P/S & S/P
SONET XCVR
RX_LOSEXT
with
Clk Recovery
RX_SONETCLK
RX_DATA_IN[15:0]
STS-192/STM-64
8/16
F
L
S19205CBI E
X
B
U
S
4
STX_DATA_OUT[63:0]
System Control Signals
Network
Processor
SRX_DATA_IN[63:0]
AMCC S3091 and S3092
TOH Insertion
and Extraction
AMCC reserves the right to make changes to its products, or to discontinue any product or service without notice, and advises its customers to
obtain the latest version of relevant information to verify, before placing orders, that the information being relied upon is cu rrent.
AMCC is a registered trademark of Applied Micro Circuits Corporation. Copyright © 2002 Applied Micro Circuits Corporation. All Rights Reserved.
200 Minuteman Road • Andover, MA 01810 • Tel: 978-247-8000 • Fax: 978-623-0024 • http://www.amcc.com
Empowering Intelligent Optical Networks
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