Programmable Low Power Gyroscope ADIS16250/ADIS16255 FEATURES APPLICATIONS Yaw rate gyroscope with digital range scaling ±80°/sec, ±160°/sec, and ±320°/sec settings 14-bit digital gyroscope sensor outputs 12-bit digital temperature sensor output Calibrated sensitivity and bias ADIS16250: +25°C ADIS16255: −40°C to +85°C In-system, auto-zero for bias drift calibration Digitally controlled sample rate Digitally controlled frequency response Dual alarm settings with configurable operation Embedded integration for short-term angle estimates Digitally activated self-test Digitally activated low power mode Interrupt-driven wake-up SPI®-compatible serial interface 50 Hz sensor bandwidth Auxiliary 12-bit ADC input and 12-bit DAC output Auxiliary digital input/output Single-supply operation: 4.75 V to 5.25 V 2000 g powered shock survivability Instrumentation control Platform control and stabilization Motion control and analysis Avionics instrumentation Navigation Image stabilization Robotics FUNCTIONAL BLOCK DIAGRAM AUX ADC AUX DAC VREF ADIS16250/ ADIS16255 TEMPERATURE SENSOR RATE GYROSCOPE SENSOR FILT DIGITAL CONTROL SELF-TEST VCC CALIBRATION AND DIGITAL PROCESSING SIGNAL CONDITIONING AND CONVERSION POWER MANAGEMENT ALARM CS SPI PORT SCLK DIN DOUT AUXILIARY I/O RST DIO0 DIO1 06070-001 COM Figure 1. GENERAL DESCRIPTION The ADIS16250/ADIS16255 are complete angular rate measurement systems available in a single compact package enabled by Analog Devices, Inc. iSensor™ integration. By enhancing Analog Devices iMEMS® sensor technology with an embedded signal processing solution, the ADIS16250/ADIS16255 provide factory-calibrated and tunable digital sensor data in a convenient format that can be accessed using a simple SPI serial interface. The ADIS16255 additionally provides an extended temperature calibration. The SPI interface provides access to measurements for the gyroscope, temperature, power supply, and one auxiliary analog input. Easy access to calibrated digital sensor data provides developers with a system-ready device, reducing development time, cost, and program risk. The device range can be digitally selected from three different settings: ±80°/sec, ±160°/sec, and ±320°/sec. Unique characteristics of the end system are accommodated easily through several built-in features, including a single-command auto-zero recalibration function, as well as configurable sample rate and frequency response. Additional features can be used to further reduce system complexity, including: • Configurable alarm function • Auxiliary 12-bit ADC and DAC • Two configurable digital I/O ports • Digital self-test function System power dissipation can be optimized via the ADIS16250/ ADIS16255 power management features, including an interruptdriven wake-up. The ADIS16250/ADIS16255 are available in an 11 mm × 11 mm × 5.5 mm, laminate-based land grid array (LGA) package with a temperature range of −40°C to +85°C. Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006–2009 Analog Devices, Inc. All rights reserved. ADIS16250/ADIS16255 TABLE OF CONTENTS Features .............................................................................................. 1 Factory Calibration .................................................................... 10 Applications ....................................................................................... 1 Auxiliary ADC Function ........................................................... 10 Functional Block Diagram .............................................................. 1 Basic Operation .............................................................................. 11 General Description ......................................................................... 1 Serial Peripheral Interface (SPI) ............................................... 11 Revision History ............................................................................... 2 Data Output Register Access .................................................... 12 Specifications..................................................................................... 3 Programming and Control ............................................................ 13 Timing Specifications .................................................................. 5 Control Register Overview ....................................................... 13 Absolute Maximum Ratings............................................................ 6 Control Register Structure ........................................................ 13 ESD Caution .................................................................................. 6 Calibration................................................................................... 14 Pin Configuration and Function Descriptions ............................. 7 Global Commands ..................................................................... 14 Recommended Layout ................................................................. 7 Operational Control................................................................... 15 Typical Performance Characteristics ............................................. 8 Status and Diagnostics ............................................................... 16 Theory of Operation ...................................................................... 10 Outline Dimensions ....................................................................... 20 Overview...................................................................................... 10 Ordering Guide .......................................................................... 20 Relative Angle Estimate ............................................................. 10 REVISION HISTORY 11/09—Rev. C to Rev. D Changes to Flash Memory, Endurance Parameter, Table 1 ......... 4 Changes to Figure 16 ........................................................................ 9 Changes to Control Register Structure Section .......................... 13 11/08—Rev. B to Rev. C Deleted Temperature Sensor Parameter, Table 1 .......................... 3 Added Logic Inputs Conditions and Digital Outputs Conditions ......................................................................................... 4 3/07—Rev. A to Rev. B Changes to Table 2 and Figure 2 ..................................................... 5 Changes to Table 8 .......................................................................... 13 Changes to Table 9 and Table 11................................................... 14 Changes to Table 24 ........................................................................ 16 Changes to Data-Ready I/O Indicator Section ........................... 17 Changes to Self-Test Section ......................................................... 17 2/07—Rev. 0 to Rev. A Added ADIS16255.............................................................. Universal Changes to Table 1.............................................................................3 Changes to Table 2.............................................................................5 Changes to Figure 2 ...........................................................................5 Changes to Typical Performance Characteristics..........................8 Deleted Temperature Sensor Section ........................................... 11 Added Factory Calibration Section.............................................. 11 Changes to Table 7.......................................................................... 12 Changes to Table 8.......................................................................... 13 Changes to Table 11 ....................................................................... 14 Changes to Table 19 ....................................................................... 16 Changes to Flash Memory Endurance Section .......................... 18 Changes to Ordering Guide .......................................................... 20 10/06—Revision 0: Initial Version Rev. D | Page 2 of 20 ADIS16250/ADIS16255 SPECIFICATIONS TA = −40°C to +85°C, VCC = 5.0 V, angular rate = 0°/sec, ±1 g, ±320°/sec range setting, unless otherwise noted. Table 1. Parameter SENSITIVITY 1 Initial Tolerance Temperature Coefficient Nonlinearity BIAS In Run Bias Stability Turn-On-to-Turn-On Bias Stability Angular Random Walk Temperature Coefficient Linear Acceleration Effect Voltage Sensitivity NOISE PERFORMANCE Output Noise Rate Noise Density FREQUENCY RESPONSE 3 dB Bandwidth Sensor Resonant Frequency SELF-TEST STATE Change for Positive Stimulus Change for Negative Stimulus Internal Self-Test Cycle Time ADC INPUT Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error Input Range Input Capacitance ON-CHIP VOLTAGE REFERENCE Accuracy Temperature Coefficient Output Impedance Conditions Clockwise rotation is positive output 25°C, dynamic range = ±320°/sec 2 25°C, dynamic range = ±160°/sec 25°C, dynamic range = ±80°/sec 25°C, dynamic range = ±320°/sec ADIS16250 (see Figure 8) ADIS16255 (see Figure 11) Best fit straight line Min Typ 0.07326 0.03663 0.01832 ±0.2 225 25 0.1 Max Unit ±1 °/sec/LSB °/sec/LSB °/sec/LSB % ppm/°C ppm/°C % of FS 25°C, 1σ 25°C, 1σ 25°C, 1σ ADIS16250 (see Figure 7) ADIS16255 (see Figure 10) Any axis VCC = 4.75 V to 5.25 V 0.016 0.05 3.6 0.03 0.005 0.2 1.0 °/sec °/sec °/√hour °/sec/°C °/sec/°C °/sec/g °/sec/V At 25°C, ±320°/sec range, no filtering At 25°C, ±160°/sec range, 4-tap filter setting At 25°C, ±80°/sec range, 16-tap filter setting At 25°C, f = 25 Hz, ±320°/sec range, no filtering 0.48 0.28 0.14 0.056 °/sec rms °/sec rms °/sec rms °/sec/√Hz rms See the Analog Bandwidth section for adjustment 50 14 Hz kHz 320°/sec dynamic range setting 320°/sec dynamic range setting 439 −439 721 −721 20 1092 −1092 12 ±2 ±1 ±4 ±2 0 During acquisition 2.5 20 2.5 At 25°C −10 +10 ±40 70 Rev. D | Page 3 of 20 LSB LSB ms Bits LSB LSB LSB LSB V pF V mV ppm/°C Ω ADIS16250/ADIS16255 Parameter DAC OUTPUT Resolution Relative Accuracy Differential Nonlinearity Offset Error Gain Error Output Range Output Impedance Output Settling Time LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Logic 1 Input Current, IINH Logic 0 Input Current, IINL All except RST RST 3 Input Capacitance, CIN DIGITAL OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL SLEEP TIMER Timeout Period 4 START-UP TIME Initial Sleep Mode Recovery FLASH MEMORY Endurance 5 Data Retention 6 CONVERSION RATE Minimum Conversion Time Maximum Conversion Time Maximum Throughput Rate Minimum Throughput Rate POWER SUPPLY Operating Voltage Range, VCC Power Supply Current Conditions 5 kΩ/100 pF to GND Min Typ Max 12 4 1 ±5 ±0.5 0 to 2.5 2 10 For Code 101 to Code 4095 Unit Bits LSB LSB mV % V Ω μs Internal 3.3 V Interface 2.0 For CS signal when used to wake up from sleep mode VIH = 3.3 V VIL = 0 V ±0.2 −40 −1 10 Internal 3.3 V Interface ISOURCE = 1.6 mA ISINK = 1.6 mA 0.8 0.55 ±10 −60 2.4 0.5 V V 128 sec ms ms 10,000 20 Cycles Years 3.906 7.75 256 0.129 4.75 Normal mode at 25°C Fast mode at 25°C Sleep mode at 25°C 1 μA mA pF 0.4 160 2.5 TJ = 55°C V V V μA 5.0 18 44 425 ms sec SPS SPS 5.25 V mA mA μA ADIS16255 characterization data represents ±4σ to fall within the ±1% limit. The sensor is capable of ±600°/sec, but the specifications herein are for ±320°/sec only. 3 The RST pin has an internal pull-up. 4 Guaranteed by design. 5 Endurance is qualified as per JEDEC Standard 22 Method A117 and measured at −40°C, +25°C, +85°C, and +125°C. 6 Retention lifetime equivalent at junction temperature (TJ) 55°C, as per JEDEC Standard 22 Method A117. Retention lifetime decreases with junction temperature. 2 Rev. D | Page 4 of 20 ADIS16250/ADIS16255 TIMING SPECIFICATIONS TA = −40°C to +85°C, VCC = 5.0 V, unless otherwise noted. Table 2. Parameter fSCLK Description Fast mode, SMPL_PRD ≤ 0x07 (fS ≥ 64 Hz) Normal mode, SMPL_PRD ≥ 0x08 (fS ≤ 56.9 Hz) Data rate period, fast mode, SMPL_PRD ≤ 0x07 (fS ≥ 64 Hz) Data rate period, normal mode, SMPL_PRD ≥ 0x08 (fS ≤ 56.9 Hz) Stall period, fast mode, SMPL_PRD ≤ 0x07 (fS ≥ 64 Hz) Stall period, normal mode, SMPL_PRD ≥ 0x08 (fS ≤ 56.9 Hz) Chip select to clock edge Data output valid after SCLK falling edge 2 Data input setup time before SCLK rising edge Data input hold time after SCLK rising edge Data output fall time Data output rise time CS high after SCLK edge 3 Flash update time (power supply must be within range) tDATARATE tSTALL tCS tDAV tDSU tDHD tDF tDR tSFS Min 1 0.01 0.01 32 42 9 12 48.8 Max1 2.5 1.0 Typ Unit MHz MHz μs μs μs μs ns ns ns ns ns ns ns ms 100 24.4 48.8 5 5 12.5 12.5 5 50 1 Guaranteed by design; not production tested. The MSB presents an exception to this parameter. The MSB clocks out on the falling edge of CS. The rest of the DOUT bits are clocked after the falling edge of SCLK and are governed by this specification. 3 This parameter may need to be expanded to allow for proper capture of the LSB. After CS goes high, the DOUT line goes into a high impedance state. 2 tDATARATE 06070-026 CS SCLK tDATASTALL Figure 2. SPI Chip Select Timing CS tCS tSFS 1 SCLK 2 3 4 5 6 15 16 tDAV DOUT * MSB DB14 DB13 tDSU DIN DB11 A4 A3 DB10 DB2 DB1 LSB tDHD A5 A2 D2 D1 LSB 06070-003 W/R DB12 *NOT DEFINED Figure 3. SPI Timing (Using SPI Settings Typically Identified as Phase = 1, Polarity = 1) Rev. D | Page 5 of 20 ADIS16250/ADIS16255 ABSOLUTE MAXIMUM RATINGS Table 3. 1 Rating 2000 g 2000 g −0.3 V to +6.0 V −0.3 V to +5.5 V −0.3 V to +3.5 V −40°C to +125°C −65°C to +150°C Extended exposure to temperatures outside of the specified temperature range of −40°C to +85°C can adversely affect the accuracy of the factory calibration. For best accuracy, store the parts within the specified operating range of −40°C to +85°C. RATEOUT RATE AXIS +8191 LSB LONGITUDINAL AXIS CLOCKWISE ROTATION 10 5 6 1 LATERAL AXIS –8192 LSB RATEIN Figure 4. RATEOUT Level Increase with Clockwise Rotation Increase ESD CAUTION Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. D | Page 6 of 20 06070-011 Parameter Acceleration (Any Axis, Unpowered, 0.5 ms) Acceleration (Any Axis, Powered, 0.5 ms) VCC to COM Digital Input/Output Voltage to COM Analog Inputs to COM Operating Temperature Range1 Storage Temperature Range1 ADIS16250/ADIS16255 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VREF COM COM VCC VCC 20 1 DOUT 2 DIN 3 CS 4 DIO0 5 19 18 17 16 15 FILT 14 RATE 13 AUX ADC 12 AUX DAC DNC = DO NOT CONNECT 11 9 10 7 8 DNC ADIS16250/ ADIS16255 TOP VIEW (Not To Scale) POSITIVE OUTPUT ROTATIONAL DIRECTION 6 DIO1 RST DNC DNC DNC 06070-004 SCLK Figure 5. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 2 3 4 5, 6 7 8, 9, 10, 11 12 13 14 15 Mnemonic SCLK DOUT DIN CS DIO0, DIO1 RST DNC AUX DAC AUX ADC RATE FILT Type 1 I O I I I/O I – O I O I 16, 17 18, 19 20 VCC COM VREF S S O 1 Description SPI, Serial Clock. SPI, Data Output. SPI, Data Input. SPI, Chip Select, Active Low. Multifunction Digital Input/Output Pin. Reset, Active Low. This resets the sensor signal conditioning circuit and initiates a start-up sequence. Do Not Connect. Auxiliary DAC Analog Output Voltage. Auxiliary ADC Analog Input Voltage. Analog Rate Signal Output (Uncalibrated). Analog Amplifier Summing Junction. This is used for setting the analog bandwidth. See the Analog Bandwidth section for more details. 5.0 V Power Supply. Common. Reference point for all circuitry in the ADIS16250/ADIS16255. Precision Reference Output. S = supply; O = output; I = input. RECOMMENDED LAYOUT 5.0865 8× 3.800 8× 0.773 16× 10.173 2× 7.600 4× 1.127 20× 11mm × 11mm STACKED LGA PACKAGE Figure 6. Recommended Pad Layout (Units in Millimeters) Rev. D | Page 7 of 20 06070-010 0.500 20× ADIS16250/ADIS16255 4 4 3 3 2 2 1 1 0 BIAS (°/s) +1σ –1 –3 –20 –5 10 25 40 55 70 85 100 –4 –50 –40 –30 –20 –10 06070-012 –35 TEMPERATURE (°C) 0 10 20 30 40 50 60 70 80 90 TEMPERATURE (°C) Figure 7. Bias vs. Temperature, ADIS16250 Figure 10. Bias vs. Temperature, ADIS16255 2.0 2.0 1.5 1.5 1.0 1.0 SENSITIVITY (%) SENSITIVITY (%) –1σ –2 –1σ –3 –4 –50 0 –1 µ –2 +1σ µ 06070-024 BIAS (°/s) TYPICAL PERFORMANCE CHARACTERISTICS 0.5 +1σ 0 µ –0.5 –1.0 µ +1σ 0.5 0 –0.5 –1σ –1.0 –1σ –20 –5 10 25 40 55 70 85 TEMPERATURE (°C) 100 –2.0 –50 3 1.5 2 1.0 SENSITIVITY (%) 2.0 0 –1 40 55 70 80 –0.5 –3 –1.5 SUPPLY VOLTAGE (4.75V, 5.00V, 5.25V) 25 0 –1.0 MAXIMUM 10 0.5 –2 –2.0 06070-013 BIAS (°/s) 1 TYPICAL –5 Figure 11. Sensitivity vs. Temperature, ADIS16255 4 MINIMUM –20 TEMPERATURE (°C) Figure 8. Sensitivity vs. Temperature, ADIS16250 –4 –35 MINIMUM TYPICAL MAXIMUM SUPPLY VOLTAGE (4.75V, 5.00V, 5.25V) Figure 9. Bias vs. Supply Voltage Figure 12. Sensitivity vs. Supply Voltage Rev. D | Page 8 of 20 06070-017 –35 06070-016 –2.0 –50 –1.5 06070-025 –1.5 ADIS16250/ADIS16255 1 13.75 13.65 SENSITIVITY (LSB/°/s) ROOT ALLAN VARIANCE (°/s) 13.70 0.1 13.60 13.55 13.50 13.45 1 10 100 1000 TAU (Seconds) 13.35 06070-014 0.01 0.1 0 100 200 300 400 500 600 RATE (°/s) 06070-018 13.40 Figure 16. Sensitivity vs. Angular Rate, ±320°/sec Range Figure 13. Root Allan Variance vs. TAU, ±320°/sec Range 44 65 42 40 60 FAST MODE 38 55 34 SELF-TEST (°/s) CURRENT (mA) 36 32 30 28 26 50 45 40 24 22 20 35 NORMAL MODE –35 –20 –5 10 25 40 55 70 85 100 TEMPERATURE (°C) 30 –50 06070-019 16 –50 –35 –20 –5 10 25 40 55 70 85 100 85 100 TEMPERATURE (°C) Figure 14. Current vs. Temperature 06070-020 18 Figure 17. Positive Self-Test vs. Temperature 0.5 –30 0.4 –35 0.3 –40 SELF-TEST (°/s) 0.1 0 –0.1 –45 –50 –55 –0.2 –60 –0.3 –0.5 0 500 1000 1500 2000 TIME (Minutes) 2500 3000 Figure 15. Bias vs. Time –70 –50 –35 –20 –5 10 25 40 55 70 TEMPERATURE (°C) Figure 18. Negative Self-Test vs. Temperature Rev. D | Page 9 of 20 06070-022 –65 –0.4 06070-015 BIAS (°/s) 0.2 ADIS16250/ADIS16255 THEORY OF OPERATION OVERVIEW AUXILIARY ADC FUNCTION The core angular rate sensor integrated inside the ADIS16250/ ADIS16255 is based on the Analog Devices iMEMS technology. This sensor operates on the principle of a resonator gyroscope. Two polysilicon sensing structures each contain a dither frame electrostatically driven to resonance. This provides the necessary velocity element to produce a Coriolis force during rotation. At two of the outer extremes of each frame, orthogonal to the dither motion, are movable fingers placed between fixed fingers to form a capacitive pickoff structure that senses Coriolis motion. The resulting signal is fed to a series of gain and demodulation stages that produce the electrical rate signal output. The auxiliary ADC function integrates a standard 12-bit ADC into the ADIS16250/ADIS16255 to digitize other system-level analog signals. The output of the ADC can be monitored through the AUX_ADC control register, as defined in Table 6. The ADC is a 12-bit successive approximation converter. The output data is presented in straight binary format with the fullscale range extending from 0 V to 2.5 V. The 2.5 V upper limit is derived from the on-chip precision internal reference. The base sensor output signal is sampled using an ADC, and then the digital data is fed into a proprietary digital calibration circuit. This circuit contains calibration coefficients from the factory calibration, along with user-defined calibration registers that can be used to calibrate system-level errors. The calibrated gyroscope data (GYRO_OUT) is made available through output data registers along with temperature, power supply, auxiliary ADC, and relative angle output calculations. RELATIVE ANGLE ESTIMATE Figure 19 shows the equivalent circuit of the analog input structure of the ADC. The input capacitor (C1) is typically 4 pF and can be attributed to parasitic package capacitance. The two diodes provide ESD protection for the analog input. Care must be taken to ensure that the analog input signals never exceed the range of −0.3 V to +3.5 V. This causes the diodes to become forward-biased and to start conducting. The diodes can handle 10 mA without causing irreversible damage. The resistor is a lumped component that represents the on resistance of the switches. The value of this resistance is typically 100 Ω. Capacitor C2 represents the ADC sampling capacitor and is typically 16 pF. VDD FACTORY CALIBRATION The ADIS16250/ADIS16255 provide a factory calibration that includes correction for initial tolerance and power supply variation. In addition, the ADIS16255 provides correction for temperature variation. This calibration includes individual sensor characterization and custom correction coefficient calculation. D C1 D R1 C2 06070-005 The ANGL_OUT register offers the integration of the GYRO_OUT data. In order for this information to be useful, the reference angle must be known. This can be accomplished by reading the register contents at the initial time, before starting the monitoring, or by setting its contents to zero. This number is reset to zero when the NULL command is used, after a RESET command is used, and during power-up. This function can be used to estimate change in angle over a period. The user is cautioned to fully understand the stability requirements and the time period over which to use this estimated relative angle position. Figure 19. Equivalent Analog Input Circuit Conversion Phase: Switch Open Track Phase: Switch Closed For ac applications, it is recommended to remove high frequency components from the analog input signal by using a low-pass filter on the analog input pin. In applications where harmonic distortion and signal-to-noise ratio are critical, the analog input must be driven from a low impedance source. Large source impedances significantly affect the ac performance of the ADC. This can necessitate the use of an input buffer amplifier. When no input amplifier is used to drive the analog input, the source impedance should be limited to values lower than 1 kΩ. Rev. D | Page 10 of 20 ADIS16250/ADIS16255 BASIC OPERATION Writing to Registers The ADIS16250/ADIS16255 are designed for simple integration into industrial system designs, requiring only a 5.0 V power supply and a 4-wire, industry standard serial peripheral interface (SPI). All outputs and user-programmable functions are handled by a simple register structure. Each register is 16 bits in length and has its own unique bit map. The 16 bits in each register consist of an upper (D8 to D15) byte and a lower (D0 to D7) byte, each of which has its own 6-bit address. Figure 20 displays a typical data frame for writing a command to a control register. In this case, the first bit of the DIN sequence is a 1, followed by a 0, the 6-bit address, and the 8-bit data command. Because each write command covers a single byte of data, two data frames are required when writing the entire 16-bit space of a register. Reading from Registers SERIAL PERIPHERAL INTERFACE (SPI) Reading the contents of a register requires a modification to the sequence in Figure 20. In this case, the first two bits in the DIN sequence are 0, followed by the address of the register. Each register has two addresses (upper, lower), but either one can be used to access its entire 16 bits of data. The final eight bits of the DIN sequence are irrelevant and can be counted as don’t cares during a read command. During the next data frame, the DOUT sequence contains the register’s 16-bit data, as shown in Figure 21. Although a single read command requires two separate data frames, the full duplex mode minimizes this overhead, requiring only one extra data frame when continuously sampling. The ADIS16250/ADIS16255 serial peripheral interface (SPI) port includes four signals: chip select (CS), serial clock (SCLK), data input (DIN), and data output (DOUT). The CS line enables the ADIS16250/ADIS16255 SPI port and frames each SPI event, which consists of single or multiple data frames. When this signal is high, the DOUT lines are in a high impedance state and the signals on DIN and SCLK have no impact on operation. A complete data frame contains 16 clock cycles. Because the SPI port operates in full duplex mode, it supports simultaneous, 16-bit receive (DIN) and transmit (DOUT) functions during the same data frame. Refer to Table 2, Figure 2, and Figure 3 for detailed timing and operation of the SPI port. DATA FRAME CS SCLK A5 A4 A3 A2 A1 A0 REGISTER ADDRESS WRITE = 1 READ = 0 DC7 DC6 DC5 DC4 DC3 DC2 DC1 DATA FOR WRITE COMMANDS DON’T CARE FOR READ COMMANDS DC0 06070-006 W/R DIN Figure 20. DIN Bit Sequence CS DATA FRAME DATA FRAME SCLK W/R BIT DOUT ADDRESS DON’T CARE NEXT COMMAND DON’T CARE ZERO BASED ON PREVIOUS COMMAND 16-BIT REGISTER CONTENTS Figure 21. SPI Sequence for Read Commands Rev. D | Page 11 of 20 06070-007 DIN DON’T CARE ADIS16250/ADIS16255 The MSB holds the new data (ND) indicator. When the output registers are updated with new data, the ND bit goes to a 1 state. After the output data is read, it returns to a 0 state. The EA bit is used to indicate a system error or an alarm condition that can result from a number of conditions, such as a power supply that is out of the specified operating range. See the Status and Diagnostics section for more details. The output data is either 12 bits or 14 bits in length. For all of the 12-bit output data, Bit D13 and Bit D12 are assigned don’t care status. DATA OUTPUT REGISTER ACCESS The ADIS16250/ADIS16255 provide access to calibrated rotation measurements, relative angle estimates, power supply measurements, temperature measurements, and an auxiliary 12-bit ADC channel. This output data is continuously updating internally, regardless of user read rates. The following bit map describes the structure of all output data registers, except ENDURANCE, in the ADIS16250/ADIS16255. Table 5. Register Bit Map MSB ND D7 EA D6 D13 D5 D12 D4 D11 D3 D10 D2 D9 D1 The output data register map is located in Table 6 and provides all of the necessary details for accessing each register’s data. Table 7 displays the output coding for the GYRO_OUT register. Figure 22 provides an example SPI read cycle for this register. LSB D8 D0 Table 6. Data Output Register Information Name ENDURANCE SUPPLY_OUT GYRO_OUT AUX_ADC TEMP_OUT ANGL_OUT 1 Function Flash Memory Write Counter Power Supply Data Gyroscope Data Auxiliary Analog Input Data Sensor Temperature Data Angle Output Address 0x01, 0x00 0x03, 0x02 0x05, 0x04 0x0B, 0x0A 0x0D, 0x0C 0x0F, 0x0E Resolution (Bits) 16 12 14 12 12 14 Data Format Binary Binary Twos Complement Binary Twos Complement Binary Scale Factor (per LSB) 1 count 1.8315 mV 0.07326°/sec 1 0.6105 mV 0.1453°C 0.03663° Assumes that the scaling is set to 320°/sec. Table 7. Output Coding Example, GYRO_OUT 1, 2 Rate of Rotation ±160°/sec Range 300°/sec 160°/sec 40°/sec 20°/sec 0.03663°/sec 0°/sec −0.03663°/sec −20°/sec −40°/sec −160°/sec −300°/sec ±320°/sec Range 600°/sec 320°/sec 80°/sec 40°/sec 0.07326°/sec 0°/sec −0.07326°/sec −40°/sec −80°/sec −320°/sec −600°/sec 2 Binary Output 01 1111 1111 1111 01 0001 0001 0000 00 0100 0100 0100 00 0010 0010 0010 00 0000 0000 0001 00 0000 0000 0000 11 1111 1111 1111 11 1101 1101 1110 11 1011 1011 1100 10 1110 1111 0000 10 0000 0000 0000 Hex Output 0x1FFF 0x1110 0x0444 0x0222 0x0001 0x0000 0x3FFF 0x3DDE 0x3BBC 0x2EF0 0x2000 Two MSBs have been masked off and are not considered in the coding. Nominal sensitivity and zero offset null performance are assumed. CS SCLK DIN W/R BIT = 0 ADDRESS = 000101 DOUT DATA = 1011 1101 1101 1110 NEW DATA, NO ALARM, GYRO_OUT = –40°/SECOND Figure 22. Example Read Cycle, ±320°/sec Setting Rev. D | Page 12 of 20 06070-008 1 ±80°/sec Range 150°/sec 80°/sec 20°/sec 10°/sec 0.018315°/sec 0°/sec −0.018315°/sec −10°/sec −20°/sec −80°/sec −150°/sec Decimal 8191 4368 1092 546 1 0 −1 −546 −1092 −4368 −8192 ADIS16250/ADIS16255 PROGRAMMING AND CONTROL CONTROL REGISTER OVERVIEW CONTROL REGISTER STRUCTURE The ADIS16250/ADIS16255 offer many programmable features controlled by writing commands to the appropriate control registers using the SPI. Table 8 provides a summary of these control registers, which controls the operation of the following parameters: The ADIS16250/ADIS16255 uses a temporary, RAM-based memory structure to facilitate the control registers displayed in Table 8. The start-up configuration is stored in a flash memory structure that automatically loads into the control registers during the start-up sequence. Each nonvolatile register has a corresponding flash memory location, for storing the latest configuration contents. Since flash memory has endurance limitations, the contents of each nonvolatile register must be manually stored to flash (note that the contents of the control register contents are only nonvolatile when they are stored to flash). The manual flash update command, made available in the COMMAND register, provides this function. The ENDURANCE register provides a counter that allows for memory reliability management against the write cycle specification. • Calibration • Global commands • Operational control • • Sample rate • Power management • Digital filtering • Dynamic range • DAC output • Digital I/O Operational status and diagnostics • Self-test • Status conditions • Alarms Table 8. Control Register Memory Map Register Name GYRO_OFF GYRO_SCALE Type R/W R/W Volatility Nonvolatile Nonvolatile ALM_MAG1 ALM_MAG2 ALM_SMPL1 ALM_SMPL2 ALM_CTRL R/W R/W R/W R/W R/W Nonvolatile Nonvolatile Nonvolatile Nonvolatile Nonvolatile AUX_DAC GPIO_CTRL MSC_CTRL SMPL_PRD SENS/AVG R/W R/W R/W R/W R/W SLP_CNT STATUS COMMAND 1 Volatile Volatile Nonvolatile 1 Nonvolatile Nonvolatile Address 0x15, 0x14 0x17, 0x16 0x18 to 0x1F 0x21, 0x20 0x23, 0x22 0x25, 0x24 0x27, 0x26 0x29, 0x28 0x2A to 0x2F 0x31, 0x30 0x33, 0x32 0x35, 0x34 0x37, 0x36 0x39, 0x38 Bytes 2 2 8 2 2 2 2 2 6 2 2 2 2 2 R/W Volatile 0x3B, 0x3A 2 R W Volatile N/A 0x3D, 0x3C 0x3F, 0x3E 2 2 Function Gyroscope bias offset factor Gyroscope scale factor Reserved Alarm 1 amplitude threshold and polarity Alarm 2 amplitude threshold and polarity Alarm 1 sample period Alarm 2 sample period Alarm control register Reserved Auxiliary DAC data Auxiliary digital I/O control register Miscellaneous control register ADC sample period control Defines the dynamic range (sensitivity setting) and the number of taps for the digital filter Counter used to determine length of powerdown mode System status register System command register The contents of the upper byte are nonvolatile; the contents of the lower byte are volatile. Rev. D | Page 13 of 20 Reference Table Table 9, Table 10 Table 11, Table 12 Table 31, Table 32 Table 35, Table 36 Table 33, Table 34 Table 37, Table 38 Table 39, Table 40 Table 21, Table 22 Table 23, Table 24 Table 26, Table 27 Table 15, Table 16 Table 19, Table 20 Table 17, Table 18 Table 28, Table 29 Table 13, Table 14 ADIS16250/ADIS16255 CALIBRATION GLOBAL COMMANDS The ADIS16250/ADIS16255 are factory-calibrated for sensitivity and bias. It also provides several user calibration functions for simplifying field-level corrections. The calibration factors are stored in nonvolatile memory and are applied using the following linear calibration equation: The ADIS16250/ADIS16255 provide global commands for common operations such as auto-null, factory calibration restore, manual flash update, auxiliary DAC latch, and software reset. Each of these global commands has a unique control bit assigned to it in the COMMAND register and is initiated by writing a 1 to its assigned bit. y = mx + b The auto-null function does two things: it resets the contents of the ANGL_OUT register to zero, and it adjusts the GYRO_OUT register to zero. This automated adjustment takes two steps: where: y is the calibrated output data. x is the precalibration data. m is the sensitivity scale factor. b is the offset scale factor. 1. Characterize the behavior of the ADIS16250/ADIS16255 at predefined critical operating conditions. 2. Use this characterization data to calculate and load the contents of GYRO_OFF (b) and GYRO_SCALE (m). The GYRO_OFF provides a calibration range of ±37.5°/sec, and its contents are nonvolatile. The GYRO_SCALE register provides a calibration range of 0 to 1.9995, and its contents are also nonvolatile. Table 9. GYRO_OFF Register Definition 1 Scale1 0.018315°/sec Default 0x0000 Format Twos complement Access R/W Table 10. GYRO_OFF Bit Descriptions 1 2 Scale1 0.0487% Write the opposite of this value into the GRYO_OFF register. Sensor noise influences the accuracy of this step. The factory calibration restore command sets the contents of GYRO_OFF to 0x0000 and GYRO_SCALE to 0x0800, erasing any field-level calibration contents. The manual flash update writes the contents of each nonvolatile register into flash memory for storage. This process takes approximately 50 ms and requires the power supply voltage to be within specification for the duration of the event. It is worth noting that this operation also automatically follows the auto-null and factory reset commands. The DAC latch command loads the contents of AUX_DAC into the DAC latches. Since the AUX_DAC contents must be updated one byte at a time, this command ensures a stable DAC output voltage during updates. Finally, the software reset command sends the ADIS16250/ADIS16255 digital processor into a restart sequence, effectively doing the same thing as the RST line. Table 13. COMMAND Register Definition Default2 0x0800 Format Binary Scale is the weight of each LSB. Equates to a scale factor of one. Access R/W Bit 15:8 7 6:4 3 2 1 0 Format N/A Description Not used Software reset command Not used Manual flash update command Auxiliary DAC data latch Factory calibration restore command Auto-null command Table 12. GYRO_SCALE Bit Descriptions Bit 15:12 11:0 Default N/A Table 14. COMMAND Bit Descriptions Description Not used Data bits Table 11. GYRO_SCALE Register Definition Address 0x17, 0x16 2. Address 0x3F, 0x3E Scale is the weight of each LSB. Bit 15:12 11:0 Read GYRO_OUT. For optimal calibration accuracy, set the number of filtering taps to its maximum, wait for the appropriate number of samples to process through the filter, and then exercise this option. There are three options for system-level calibrations of the bias in the ADIS16250/ADIS16255: auto-null, factory calibration restore, and manual calibration updates. The auto-null and factory reset options are described in the Global Commands section. Optional field-level calibrations use the preceding equation and require two steps: Address 0x15, 0x14 1. Description Not used Data bits Rev. D | Page 14 of 20 Access Write only ADIS16250/ADIS16255 OPERATIONAL CONTROL Internal Sample Rate The internal sample rate defines how often data output variables are updated, independent of the rate at which they are read out on the SPI port. The SMPL_PRD register controls the ADIS16250/ADIS16255 internal sample rate and has two parts: a selectable time base and a multiplier. The sample period can be calculated using the following equation: TS = TB × (NS + 1) After completing the sleep period, the ADIS16250/ADIS16255 return to normal operation. If measurements are required before sleep period completion, the ADIS16250/ADIS16255 can be awakened by putting the CS line in a zero logic state. Otherwise, the CS line must be kept high to maintain sleep mode. Table 17. SLP_CNT Register Definition Address 0x3B, 0x3A 1 Scale1 0.5 sec Default 0x0000 Format Binary Access R/W Scale is the weight of each LSB. where: Table 18. SLP_CNT Bit Descriptions TS is the sample period. TB is the time base. NS is the increment setting. Bit 15:8 7:0 The default value is the maximum 256 samples per second, and the contents of this register are nonvolatile. Analog Bandwidth The analog bandwidth of the ADIS16250/ADIS16255 is 50 Hz. This bandwidth can be reduced by placing an external capacitor across the RATE and FILT pins. In this case, the analog bandwidth can be calculated using the following equation: Table 15. SMPL_PRD Register Definition Format N/A Access R/W fOUT = 1/(2 × π × ROUT × (COUT + 0.068 μF)) Table 16. SMPL_PRD Bit Descriptions Bit 15:8 7 6:0 Description Not used Time base, 0 = 1.953 ms, 1 = 60.54 ms Multiplier where: ROUT = 45.22 kΩ. COUT is the external capacitance. The following is an example calculation of the sample period for the ADIS16250/ADIS16255: If SMPL_PRD = 0x0007, B7…B0 = 00000111 B7 = 0 → TB = 1.953 ms B6…B0 = 000000111 → NS = 7 TS = TB × (NS + 1) = 1.953 ms × (7 + 1) = 15.624 ms fS = 1∕TS = 64 SPS The sample rate setting has a direct impact on the SPI data rate capability. For sample rates of 64 SPS and above, the SPI SCLK can run at a rate up to 2.5 MHz. For sample rates below 64 SPS, the SPI SCLK can run at a rate up to 1 MHz. The sample rate setting also affects the power dissipation. When the sample rate is set below 64 SPS, the power dissipation reduces by a factor of 60%. The two different modes of operation offer a system-level trade-off between performance (sample rate, serial transfer rate) and power dissipation. Power Management In addition to offering two different performance modes for power optimization, the ADIS16250/ADIS16255 offer a programmable shutdown period. Writing the appropriate sleep time to the SLP_CNT register shuts the device down for the specified time. The following example provides an illustration of this relationship: Digital Filtering The ADIS16250/ADIS16255 GYRO_OUT signal path has a nominal analog bandwidth of 50 Hz. The ADIS16250 provides a Bartlett Window FIR filter for additional noise reduction on all of the output data registers. The SENS/AVG register stores the number of taps in this filter in seven power-of-two step sizes (that is, 2M = 1, 2, 4, 16, 32, 64, and 128). Filter setup requires one simple step: write the appropriate M factor to the assigned bits in the SENS/AVG register. The bit assignments are listed in Table 20. The following equation offers a frequency response relationship for this filter: HB ( f ) = HA2 ( f ) ⇒ H A ( f ) = sin(π × N × f × t S ) N × sin(π × f × t S ) 0 N=4 N=2 –20 N = 16 –40 –60 N = 128 –80 –100 –120 –140 –160 0.001 B7 … B0 = 00000110 0.01 0.1 FREQUENCY (f/fs) Figure 23. Bartlett Window FIR Frequency Response Sleep period = 3 sec Rev. D | Page 15 of 20 1 06070-009 Default 0x0001 MAGNITUDE (dB) Address 0x37, 0x36 Description Not used Data bits ADIS16250/ADIS16255 Dynamic Range General-Purpose I/O The ADIS16250/ADIS16255 provide three dynamic range settings: ±80°/sec, ±160°/sec, and ±320°/sec. The lower dynamic range settings (80, 160) limit the minimum filter tap sizes in order to maintain the resolution as the maximum rate measurements decrease. The recommended order for programming the SENS/AVG register is (1) dynamic range and then (2) filtering response. The contents of the SENS/AVG register are nonvolatile. The ADIS16250/ADIS16255 provide two general-purpose pins that enable digital I/O control using the SPI. The GPIO_CTRL control register establishes the configuration of these pins and handles the SPI-to-pin controls. Each pin provides the flexibility of both input (read) and output (write) operations. For example, writing a 0x0202 to this register establishes Line 0 as an output and sets its level as a one. Writing 0x0000 to this register establishes both lines as inputs, and their status can be read through Bit 0 and Bit 1 of this register. Table 19. SENS/AVG Register Definition Address 0x39, 0x38 Default 0x0402 Format Binary Access R/W The digital I/O lines are also available for data-ready and alarm/error indications. In the event of conflict, the following priority structure governs the digital I/O configuration: Table 20. SENS/AVG Bit Descriptions 1. MSC_CTRL Bit 15:11 10:8 2. ALM_CTRL 3. GPIO_CTRL Value 100 010 001 7:4 3:0 Description Not used Sensitivity selection bits 320°/sec (default condition) 160°/sec, filter taps ≥ 4 (Bits[3:0] ≥ 0x02) 80°/sec, filter taps ≥16 (Bits[3:0] ≥ 0x04) Not used Filter tap setting, M = binary number (number of taps, N = 2M) Auxiliary DAC The auxiliary DAC provides a 12-bit level adjustment function. The AUX_DAC register controls the operation of this feature. It offers a rail-to-rail buffered output that has a range of 0 V to 2.5 V. The DAC can drive its output to within 5 mV of the ground reference when it is not sinking current. As the output approaches ground, the linearity begins to degrade (100 LSB beginning point). As the sink current increases, the nonlinear range increases. The DAC output latch function, contained in the COMMAND register, provides continuous operation while writing each byte of this register. The contents of this register are volatile, which means that the desired output level must be set after every reset and power cycle event. Table 21. AUX_DAC Register Definition Address 0x31, 0x30 Default 0x0000 Format Binary Access R/W Table 23. GPIO_CTRL Register Definition Address 0x33, 0x32 Default 0x0000 Format N/A Table 24. GPIO_CTRL Bit Descriptions Bit 15:10 9 8 7:2 1 0 Description Not used General-purpose I/O Line 1 polarity 1 = high 0 = low General-purpose I/O Line 0 polarity 1 = high 0 = low Not used General-purpose I/O Line 1, data direction control 1 = output 0 = input General-purpose I/O Line 0, data direction control 1 = output 0 = input STATUS AND DIAGNOSTICS The ADIS16250/ADIS16255 provide a number of status and diagnostic functions. Table 25 provides a summary of these functions, along with their appropriate control registers. Table 22. AUX_DAC Bit Descriptions Table 25. Status and Diagnostic Functions Bit 15:12 11:0 Function Data-ready I/O indicator Self-test, mechanical check for MEMS sensor Status, check for predefined error conditions Flash memory endurance Alarms, configure and check for userspecific conditions Description Not used Data bits Access R/W Rev. D | Page 16 of 20 Register MSC_CTRL MSC_CTRL STATUS ENDURANCE ALM_MAG1/2 ALM_SMPL1/2 ALM_CTRL ADIS16250/ADIS16255 Data-Ready I/O Indicator The data-ready function provides an indication of updated output data. The MSC_CTRL register provides the opportunity to configure either of the general-purpose I/O pins (DIO0 and DIO1) as a data-ready indicator signal. After each output register update, the digital I/O changes states, then returns to its original state, creating a pulsed waveform. The duty cycle of that waveform is in between 15% and 35%. Status Conditions Table 26. MSC_CTRL Register Definition Address 0x35, 0x34 Default 0x0000 Format N/A The STATUS register contains the following error-condition flags: Alarm conditions, self-test status, angular rate over range, SPI communication failure, control register update failure, and power supply out of range. See Table 28 and Table 29 for the appropriate register access and bit assignment for each flag. Access R/W Table 27. MSC_CTRL Bit Descriptions Bit 15:11 10 9 8 7:3 2 1 0 For example, the standard 52 Hz bandwidth reflects an exponential response with a time constant of 3.2 ms. If the bandwidth is reduced externally (capacitor across RATE and FILT) or internally (increasing the number of filter taps, SENS/AVG), this time constant increases. For the internal self-test option, increasing the delay can produce false alarms, since the internal timing for this function is optimized for maximum bandwidth. The appropriate bit definitions for selftest are listed in Table 26 and Table 27. Description Not used Internal self-test enable 1 = enabled 0 = disabled External negative rotation self-test enable 1 = enabled 0 = disabled External positive rotation self-test enable 1 = enabled 0 = disabled Not used Data-ready enable 1 = enabled 0 = disabled Data-ready polarity 1 = active high 0 = active low Data-ready line select 1 = DIO1 0 = DIO0 The bits assigned for checking power supply range and angular rate over range automatically reset to 0 when the error condition no longer exists. The remaining error-flag bits in the STATUS register require a read in order to return them to 0. Note that a STATUS register read clears all of the bits to 0. Table 28. STATUS Register Definition Address 0x3D, 0x3C Default 0x0000 Format N/A Table 29. STATUS Bit Descriptions Bit 15:10 9 8 7:6 5 Self-Test The MSC_CTRL register also provides a self-test function, which verifies the MEMS sensor’s mechanical integrity. There are two different self-test options: (1) internal self-test and (2) external self-test. The internal test provides a simple, two-step process for checking the MEMS sensor: (1) start the process by writing a 1 to Bit 10 in the MSC_CTRL register and (2) check the result by reading Bit 5 of the STATUS register, after 35 ms. The external self-test is a static condition that can be enabled and disabled. In this test, both positive and negative MEMS sensor movements are available. After writing to the appropriate control bit, the GYRO_OUT register reflects the changes after a delay that reflects the sensor signal chain response time. 4 3 2 1 0 Rev. D | Page 17 of 20 Description Not used Alarm 2 status 1 = active 0 = inactive Alarm 1 status 1 = active 0 = inactive Not used Self-test diagnostic error flag 1 = error condition 0 = normal operation Angular rate over range 1 = error condition 0 = normal operation SPI communications failure 1 = error condition 0 = normal operation Control register update failed 1 = error condition 0 = normal operation Power supply above 5.25 V 1 = above 5.25 V 0 = below 5.25 V (normal) Power supply below 4.75 V 1 = below 4.75 V 0 = above 4.75 V (normal) Access Read-only ADIS16250/ADIS16255 Flash Memory Endurance Table 31. ALM_MAG1 Register Definition The ENDURANCE register maintains a running count of writes to the flash memory. It provides up to 32,768 counts. Note that if this count is exceeded, the register wraps around, and goes back to zero, before beginning to increment again. Address 0x21, 0x20 Table 30. ENDURANCE Register Definition Address 0x01, 0x00 Default N/A Format Binary Access Read-only Default 0x0000 Format N/A Access R/W Table 32. ALM_MAG1 Bit Descriptions Bit 15 14 13:0 Description Comparison polarity: 1 = greater than, 0 = less than Not used Data bits: format matches source data format Alarms The ADIS16250/ADIS16255 provide two independent alarm options for event detection. Event detections occur when output register data meets the configured conditions. Configuration options are: • All output data registers are available for monitoring as the source data. • The source data can be filtered or unfiltered. • Comparisons can be static or dynamic (rate of change). • The threshold levels and times are configurable. • Comparison can be greater than or less than. YC = 1 N DS ∑ y(n + 1) − y(n) N DS n = 1 Rate of change alarm ⇒ is YC > or < M C ? Address 0x25, 0x24 Default 0x0000 Format Binary Access R/W Table 34. ALM_SMPL1 Bit Descriptions Bit 15:8 7:0 Description Not used Data bits Table 35. ALM_MAG2 Register Definition Address 0x23, 0x22 The ALM_MAG1 register and the ALM_MAG2 register both establish the threshold level for detecting events. They take on the format of the source data and provide a bit for establishing the greater than/less than comparison direction. When making dynamic comparisons, the ALM_SMPL1 register and the ALM_SMPL2 register establish the number of averages taken for the source data as a reference for comparison. In this configuration, each subsequent source data sample is subtracted from the previous one, establishing an instantaneous delta. The ALM_CTRL register controls the source data selection, static/dynamic selection, filtering selection, and digital I/O usage for the alarms. The rate of change calculation is Table 33. ALM_SMPL1 Register Definition Default 0x0000 Format N/A Access R/W Table 36. ALM_MAG2 Bit Descriptions Bit 15 14 13:0 Description Comparison polarity 1 = greater than 0 = less than Not used Data bits: format matches source data format Table 37. ALM_SMPL2 Register Definition Address 0x27, 0x26 Default 0x0000 Format Binary Access R/W Table 38. ALM_SMPL2 Bit Designations Bit 15:8 7:0 Description Not used Data bits where: NDS is the number of samples in ALM_SMPL1/2. y(n) is the sampled output data. MC is the magnitude for comparison in ALM_MAG1/2. YC is the factor to be compared with MC. > or < is determined by the MSB in ALM_MAG1/2. Table 39. ALM_CTRL Register Definition Address 0x29, 0x28 Rev. D | Page 18 of 20 Default 0x0000 Format N/A Access R/W ADIS16250/ADIS16255 Table 40. ALM_CTRL Bit Descriptions Bit 15 Value 14:12 000 001 010 011 100 101 110 111 11 10:8 000 001 010 011 100 101 110 111 7:5 4 3 2 1 0 Description Rate of change (ROC) enable for Alarm 2 1 = rate of change 0 = static level Alarm 2 source selection Disable Power supply output Gyroscope output Inactive Inactive Auxiliary ADC output Temperature sensor output Inactive Rate of change (ROC) enable for Alarm 1 1 = rate of change 0 = static level Alarm 1 source selection Disable Power supply output Gyroscope output Inactive Inactive Auxiliary ADC output Temperature sensor output Inactive Not used Filtered data comparison 1 = filtered data 0 = unfiltered data Not used Alarm output enable 1 = enabled 0 = disabled Alarm output polarity 1 = active high 0 = active low Alarm output line select 1 = DIO1 0 = DIO0 Rev. D | Page 19 of 20 ADIS16250/ADIS16255 OUTLINE DIMENSIONS 7.600 BSC (4×) 3.800 BSC (8×) 11.15 MAX 16 15 11.00 TYP 20 0.200 MIN (ALL SIDES) 7.00 TYP 1.000 BSC (20×) 1 10.173 BSC (2×) 0.900 BSC (16×) 11 10 TOP VIEW PIN 1 INDICATOR 6 5 BOTTOM VIEW 0.373 BSC (20×) 022007-B 5.50 MAX SIDE VIEW Figure 24. 20-Terminal Stacked Land Grid Array [LGA] (CC-20-1) Dimensions shown in millimeters ORDERING GUIDE Model ADIS16250ACCZ 1 ADIS16255ACCZ1 ADIS16250/PCBZ1 ADIS16255/PCBZ1 1 Temperature Range −40°C to +85°C −40°C to +85°C Package Description 20-Terminal Stacked Land Grid Array [LGA] 20-Terminal Stacked Land Grid Array [LGA] Evaluation Board for the ADIS16250 Evaluation Board for the ADIS16255 Z = RoHS Compliant Part. ©2006–2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06070-0-11/09(D) Rev. D | Page 20 of 20 Package Option CC-20-1 CC-20-1