a Multi-Rate to 2.7Gbps Clock and Data Recovery IC with Limiting Amplifier Preliminary Technical Data FEATURES Meets SONET Requirements for Jitter Transfer / Generation / Tolerance Quantizer Sensitivity: 6 mV typical • Adjustable Slice Level: +/- 100 mV • 1.9GHz minimum Bandwidth Loss of Signal Detect Range: 4mV to 17mV Single Reference Clock Frequency for all rates Including 15/14 (7%) Wrapper Rate • Choice of 19.44, 38.88, 77.76 or 155.52MHz LVPECL / LVDS / LVCMOS / LVTTL compatible inputs (LVPECL / LVDS only at 155.52 MHz) 19.44MHz Crystal Oscillator for Module apps Loss of Lock indicator Loopback mode for High Speed Test Data Output Squelch & Clock Recovery Functions Single Supply Operation: 3.3 Volts (+10%) Low Power: 780 mW Typical Patented Clock Recovery Architecture 7 x 7 mm 48 pin LFCSP APPLICATIONS SONET OC-3/12/48, SDH STM-1/4/16, and all associated FEC rates WDM transponders SONET/SDH regenerators and test equipment Backplane applications ADN2809 PRODUCT DESCRIPTION The ADN2809 provides the receiver functions of Quantization, Signal Level Detect and Clock and Data Recovery at rates of OC-3, OC-12, Gigabit Ethernet, OC-48 and all FEC rates. All SONET jitter requirements are met, including: Jitter Transfer; Jitter Generation; and Jitter Tolerance. All specifications are quoted for -40 to 85C ambient temperature unless otherwise noted. The device is intended for WDM system applications and can be used with either an external reference clock or an on-chip oscillator crystal. Both native rates and 15/14 rate digital ‘wrappers’ rates are supported by the ADN2809, without any change of reference clock required. This device together with a PIN diode and a TIA preamplifier can implement a highly integrated, low cost, low power fiber optic receiver. The receiver front end Signal Detect circuit indicates when the input signal level has fallen below a user adjustable threshold. The ADN2809 is available in a compact 48 pin chip scale package. Loss of lock CF Functional Block Diagr am REV. PrB Sept 2001 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A . Tel: 781/329-4700 Fax: 781/326-8703 www.analog.com ©Analog Devices, Inc., 2001 ADN2809 ADN2809 ELECTRICAL CHARACTERISTICS Par ameter QUANTIZER–DC CHARACTERISTICS Input Voltage Range Input Common Mode Voltage Input Peak-to-Peak Differential Voltage Input Sensitivity, VSENSE (Peak-to-Peak Differential) Input Overdrive, VOD Input Maximum Offset Voltage Input Current Input RMS Noise QUANTIZER-AC CHARACTERISTICS Upper –3 dB Bandwidth Small Signal Gain S11 Maximum @ 2.5GHz, Figure 7 Input Resistance Input Capacitance Pulse Width Distortion QUANTIZER SLICE ADJ USTMENT Gain (Threshold/Vin) Control Voltage Range Control Voltage Range Slice Threshold Offset LEVEL DETECT Level Detect Range (See Figure 4) at TA=TMIN to TMAX, VCC=VMIN to VMAX, VEE=0V, CF=4.7µF, 20 ohm ESR for xo unless otherwise noted Conditions Min Single Ended, DC Coupled @ PIN or NIN “ @ PIN or NIN AC Coupled I/P1 PIN- NIN, Figure 2, BER= <1 x 10-10 Figure 3, BER = <1 X 10-10 SliceP, SliceN = VCC Max Units 1.2 1.2 2.4 6 3 0.5 10 244 V V V mV mV mV µA µVrms 1.9 54 -15 50 0.65 10 GHz dB dB Ω pF ps 0 0.4 10 5 BER = <1 X 10-10 Differential Single-Ended Vin = SliceP-SliceN SliceP-SliceN SliceP or SliceN Full input range Typ 0.131 -0.8 1.3 -1.0 0.134 0.8 VCC 1.0 V/V V V mV RTHRESH = 0Ω RTHRESH = 10kΩ RTHRESH = 200kΩ 2 6 15 3 8.8 17 4 12 21 mV mV mV Response Time DC Coupled 0.1 3 5 µs Hysterises (Electrical), AC Coupled Signal RTHRESH = 0Ω RTHRESH = 10kΩ RTHRESH = 200kΩ 5 5 5 7 7 7 dB dB dB SDOUT output Logic High SDOUT output Logic Low Load = +2mA (ADN2812 Sources I) Load = -2mA (ADN2812 Sinks I) 2.7 3 0.2 0.4 V V VMIN to VMAX VMIN to VMAX 3.0 140 236 3.6 380 V mA 370 185 93 23 2000 1000 500 130 KHz KHz KHz KHz Level Detect Output is a logic “1” LVCMOS Compatible with no signal present. POWER SUPPLY VOLTAGE POWER SUPPLY CURRENT PHASE-LOCKED LOOP CHARACTERISTICS NOTE: SONET SPECS APPEAR IN BOLD JITTER TRANSFER BANDWIDTH (See Figure 5 and Table 1) OC-48 Gigabit Ethernet OC-12 OC-3 JITTER TOLERANCE TRACKING BANDWIDTH (See Figure 5 and Table 1) OC-48 Gigabit Ethernet OC-12 OC-3 JITTER TOLERANCE (OC-48) 4.8 4.8 4.8 4.8 MHz MHz MHz MHz 600 Hz 6 KHz 100 MHz 1 MHz 80 >202 5.5 >0.62 UIp-p UIp-p UIp-p UIp-p JITTER GENERATION (12kHz to 20MHz) OC-48 0.003 0.03 0.01 0.1 UI rms UIp-p (12kHz to 10MHz) Gigabit Ethernet 0.003 0.03 0.01 0.1 UI rms UIp-p (12kHz to 5MHz) OC-12 0.003 0.03 0.01 0.1 UI rms UIp-p (12kHz to 1.3MHz) OC-3 0.003 0.03 0.01 0.1 UI rms UIp-p REV. PrB Oct. .2001 1.0 0.5 0.25 0.065 - 2 - ADN2809 ADN2809 ELECTRICAL CHARACTERISTICS at TA=TMIN to TMAX, VCC=VMIN to VMAX, VEE=0V, CF=4.7µF, 20 ohm ESR for xo unless otherwise noted Par ameter Conditions JITTER PEAKING MAXIMUM OC-48 Gigabit Ethernet OC-12 OC-3 CML OUTPUT FORMAT Single-Ended Output Voltage Swing VSE Differential Output Voltage Swing VDIFF Min Typ Max See Figure 2 and Figure 6 See Figure 2 and Figure 6 300 600 430 860 Units dB dB dB dB 0.1 0.1 0.1 0.1 550 1100 mV mV 150 150 pS pS VCC-0.32 V V Rise Time (tR) Fall Time (tF) 20% - 80% 80% - 20% Output High Voltage VOH Output Low Voltage VOL Figure 6 Figure 6 Data Setup Time TS (Figure 1) OC48 Gigabit Ethernet OC12 OC3 150 350 750 3150 pS pS pS pS Data Hold Time TH (Figure 1) OC48 Gigabit Ethernet OC12 OC3 150 350 750 3150 pS pS pS pS Single-Ended Single-Ended 0.06 2.3 IOH = -100uA (ADN2809 Sources I) IOL = 1.0mA (ADN2809 Sinks I) 2.4 TEST DATA DC CHARACTERISTICS Input Voltage Swing VSE (Figure 2) Input Voltage Range LVTTL DC CHARACTERISTICS VOH Output High Voltage VOL Output Low Voltage VCC VCC-0.55 VIH Input High Voltage VIL Input Low Voltage IIH Input High Current IIL Input Low Current REFCLK DC CHARACTERISTICS Input Voltage Swing VSE (Figure 2) Input Voltage Range 0.8 VCC+0.4 V V 0.5 V V 0.8 V V 2.0 Vin = +2.4 V @ +25C Vin = +0.5 V @ +25C -500 Single-Ended Single-Ended 0.032 0 50 µA µA VCC VCC V V Note: (1) Recommended for Optimum Sensitivity. Note: (2) Equipment Limitation. ABSOLUTE MAXIMUM RATINGS ORDERING GUIDE Supply Voltage....................................... ....................... ...+8 V Input Voltage (pin x or pin xto Vcc).... ........................... .TBD Maximum Junction Temperature............................. .165 deg C Storage Temperature Range...... ........ -65 deg C to +150 deg C Lead Temperature (Soldering 10 sec).. ................ ....300 deg C ESD Rating (human body model)....... ........................... ..TBD TEMP RANGE Package Descript-ion Option ADN2809XCP -40/+85oC LFCSP-16 LFCSP-16 2500 Pieces CP-16 ADN2809XCP-RL Stress above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. REV. PrB Oct. .2001 MODEL - 3 - o -40/+85 C CP-16 ADN2809 Figure 1. Output Timing definitions Figure 2. Signal Level Definition Figure 3. Quantizer Signal Definitions OC-48 2^23 LOS Curve 20.0 18.0 LOS Trip Voltage (mV) 16.0 14.0 12.0 10.0 8.0 6.0 4.0 2.0 0.0 0 20000 40000 60000 80000 100000 120000 140000 160000 RThresh Figure 4. LOS Comparator Trip Point Programming REV. PrB Oct. .2001 - 4 - 180000 200000 ADN2809 Rate J itter Tr ansfer J itter Toler ance SONET Spec ADN2809 Mar gin SONET spec ADN2809 Mar gin OC48 2MHz 370kHz 5.4 1MHz 4.77MHz 4.8 GbE 1MHz 185kHz 5.4 500kHz 4.77MHz 9.6 OC12 500kHz 93kHz 5.4 250kHz 4.77MHz 19.2 OC3 130kHz 23kHz 5.6 65kHz 4.77MHz 73.4 Table I. Typical Jitter Transfer and Jitter Tolerance Performance FIGURE 5: ADN2809 JITTER FILTERING & TRACKING BANDWIDTH OC3_jit_tolerance OC12_jit_tolerance GBE_jit_tolerance OC48_jit_tolerance OC3_jit_transfer OC12_jit_transfer GBE_jit_transfer OC48_jit_transfer 0 -.5 -1 -1.5 -2 -2.5 -3 -3.5 -4 -4.5 dB -5 -5.5 -6 -6.5 -7 -7.5 -8 -8.5 -9 -9.5 -10 1e3 freq, Hertz 1e4 1e5 1e6 1e7 Figure 5. Tracking Bandwidth and Jitter Filtering REV. PrB Oct. .2001 - 5 - 1e8 ADN2809 Figure 6. Recommended AC Output Termination Figure 7. ADN2809 S11 vs. Frequency REV. PrB Oct. .2001 - 6 - ADN2809 optimized to give excellent wide-band jitter accommodation since the jitter transfer function, Z(s)/X(s), provides the narrowband jitter filtering. See Figure 5 for a table of error transfer bandwidths and jitter transfer bandwidths at the various data rates. THEORY OF OPERATION The ADN2809 is a delay- and phase-locked loop circuit for clock recovery and data retiming from an NRZ encoded data stream. The phase of the input data signal is tracked by two separate feedback loops which share a common control voltage. A high speed delay- locked loop path uses a voltage controlled phase shifter to track the high frequency components of input jitter. A separate phase control loop, comprised of the vco, tracks the low frequency components of input jitter. The initial frequency of the vco is set by yet a third loop which compares the vco frequency with the reference frequency and sets the coarse tuning voltage. The jitter tracking phase-locked loop controls the vco by the fine tuning control. The delay- and phase- loops contribute to overall jitter accommodation. At low frequencies of input jitter on the data signal, the integrator in the loop filter provides high gain to track large jitter amplitudes with small phase error. In this case the vco is frequency modulated and jitter is tracked as in an ordinary phase-locked loop. The amount of low frequency jitter that can be tracked is a function of the vco tuning range. A wider tuning range gives larger accommodation of low frequency jitter. The internal loop control voltage remains small for small phase errors, so the phase shifter remains close to the center of its range and thus contributes little to the low frequency jitter accommodation. The delay- and phase- loops together track the phase of the input data signal. For example, when the clock lags input data, the phase detector drives the vco to higher frequency, and also, increases the delay through the phase shifter: these actions both serve to reduce the phase error between the clock and data. The faster clock picks up phase while the delayed data loses phase. Since the loop filter is an integrator, the static phase error will be driven to zero. At medium jitter frequencies, the gain and tuning range of the vco are not large enough to track input jitter. In this case the vco control voltage becomes large and saturates and the vco frequency dwells at one or the other extreme of its tuning range. The size of the vco tuning range, therefore has only a small effect on the jitter accommodation. The delay-locked loop control voltage is now larger, and so the phase shifter takes on the burden of tracking the input jitter. The phase shifter range, in UI, can be seen as a broad plateau on the jitter tolerance curve . The phase shifter has a minimum range of 2UI at all data rates. Another view of the circuit is that the phase shifter implements the zero required for frequency compensation of a second order phase-locked loop, and this zero is placed in the feedback path and thus, does not appear in the closed-loop transfer function. Jitter peaking in a conventional second order phase-locked loop is caused by the presence of this zero in the closed-loop transfer function. Since this circuit has no zero in the closed-loop transfer, jitter peaking is minimized. The gain of the loop integrator is small for high jitter frequencies, so that larger phase differences are needed to make the loop control voltage big enough to tune the range of the phase shifter. Large phase errors at high jitter frequencies cannot be tolerated. In this region the gain of the integrator determines the jitter accommodation. Since the gain of the loop integrator declines linearly with frequency, jitter accommodation is lower with higher jitter frequency. At the highest frequencies, the loop gain is very small, and little tuning of the phase shifter can be expected. In this case, jitter accommodation is determined by the eye opening of the input data, the static phase error, and the residual loop jitter generation. The jitter accommodation is roughly 0.5UI in this region. The corner frequency between the declining slope and the flat region is the closed loop bandwidth of the delay-locked loop, which is roughly 3MHz for all data rates. The delay- and phase- loops together simultaneously provide wide-band jitter accommodation and narrow-band jitter filtering. The linearized block diagram in Figure 8 shows the jitter transfer function , Z(s)/X(s), is a second order low pass providing excellent filtering. Note the jitter transfer has no zero, unlike an ordinary second order phase-locked loop. This means that the main PLL loop has low jitter peaking, see Figure 9. This makes this circuit ideal for signal regenerator applications where jitter peaking in a cascade of regenerators can contribute to hazardous jitter accumulation. The error transfer, e(s)/X(s), has the same high pass form as an ordinary phase-locked loop. This transfer function is free to be REV. PrB Oct. .2001 - 7 - ADN2809 Figure 8. ADN2809 Architecture ADN2809 Figure 9. ADN2809 Jitter Response vs. Conventional PLL REV. PrB Oct. .2001 - 8 - ADN2809 FUNCTIONAL DESCRIPTION Refer ence Clock Limiting Amplifier / Bypass & Loopback The ADN2809 can accept any of the following reference clock frequencies: 19.44 MHz, 38.88MHz, 77.76MHz at LVTTL/LVCMOS/LVPECL/LVDS levels or 155.52MHz at LVPECL/LVDS levels via the REFCLKN/P inputs, independent of data rate (including gigabit ethernet). The input buffer accepts any differential signal with a peak to peak differential amplitude of greater than 64mV (e.g. LVPECL or LVDS) or a standard single ended low voltage TTL input, providing maximum system flexibility. The appropriate division ratio can be selected using the REFSEL0/1 pins, according to Table 3. Phase noise and duty cycle of the Reference Clock are not critical and 100ppm accuracy is sufficient. The limiting amplifier has differential inputs (PIN/NIN), which are normally AC coupled to the internal 50 ohm termination (although DC coupling is possible). Input offset is factory trimmed to achieve better than 6mV typical sensitivity with minimal drift. The Quantizer Slicing level can be offset by +/100mV to mitigate the effect of ASE (amplified spontaneous emission) noise by a differential voltage input of +/-0.8V applied to ‘SLICEP/N’ inputs. If no adjustment of the slice level is needed, SLICEP/N should be tied to VCC. When the ‘Bypass’ input is driven to a TTL high state, the Quantizer output is connected directly to the buffers driving the Data Out pins, thus bypassing the clock recovery circuit (Figure 10). This feature can help the system to deal with non standard bit rates. The loopback mode can be invoked by driving the ‘LOOPEN’ pin to a TTL high state, which facilitates system diagnostic testing. This will connect the Test inputs (TDINP/N) to the clock and data recovery circuit (per Figure 10). The Test inputs can be left floating, when not in use. They accept AC or DC coupled signal levels, or AC coupled LVDS. A crystal oscillator is also provided, as an alternative to using the REFCLKN/P input. Details of the recommended crystal are given in Table 3. REFSEL must be tied to VCC when the REFCLKN/P inputs are active, or tied to VEE when the oscillator is used. No connection between the XO pin and REFCLK input is necessary (see figure 11). Please note that the crystal should operate in series resonant mode, which renders it insensitive to external parasitics. No trimming capacitors are required. Loss of Signal (LOS) Detector Lock Detector Oper ation The receiver front end Signal Detect circuit indicates when the input signal level has fallen below a user adjustable threshold. The threshold is set with a single external resistor, as illustrated in figure 4, which assumes that the slice inputs are inactive. The lock detector monitors the frequency difference between the VCO and the reference clock, and de-asserts the ‘Loss of Lock’ signal when the VCO is within 500ppm of center frequency. This enables the phase loop which then maintains phase lock, unless the frequency error exceeds 0.1%. Should this occur, the ‘Loss of Lock’ signal is re-asserted and control returns to the frequency loop which will re-acquire, and maintain a stable clock signal at the output. The frequency loop requires a single external capacitor between CF1 and CF2. The capacitor specification is given in Table 5. If the LOS detector is used the Quantizer Slice Adjust pins must both be tied to VCC, to avoid interaction with the LOS threshold level. Note that it is not expected to use both LOS and Slice Adjust at the same time: systems with optical amplifiers need the slice adjust to evade ASE, but a loss of signal causes the optical amplifier output to be full scale noise, thus the LOS would not detect the failure. In this case the Loss of Lock signal will indicate the failure. Squelch Mode When the ‘Squelch’ input is driven to a TTL high state, both the clock and data outputs are set to the zero state, to suppress downstream processing. If desired, this pin can be directly driven by the LOS (Loss-Of-Signal) or LOL (Loss-Of-Lock) detector outputs. If the Squelch function is not required, the pin should be tied to VEE. REV. PrB Oct. .2001 - 9 - ADN2809 Figure 10. Test Modes ADN 2809 ADN 2809 Figure 11. Reference Sources Note: The value of Cin required depends on the data rate, # Consecutive Identical Digits (CID) and amount of Patter Dependent Jitter (PDJ) which can be tolerated. e.g. for 1000 CID and <0.01UI pk-pk PDJ, 100nF is needed at OC48 and 1.6uF at OC3. Figure 12. Data Input Terminations REV. PrB Oct. .2001 - 10 - ADN2809 TABLE 2. Data Rate Selection SEL2 0 0 0 0 1 1 1 1 SEL0 0 0 1 1 0 0 1 1 SEL1 0 1 0 1 0 1 0 1 Rate OC48 Gigabit Ethernet OC12 OC3 OC48 * 15/14 Gigabit Ethernet * 15/14 OC12 * 15/14 OC3 * 15/14 Fr equency 2.48832 GHz 1.25 GHz 622.08 MHz 155.52 MHz 2.666 GHz 1.339 GHz 666.51 MHz 166.63 MHz TABLE 3. Refer ence Fr equency Selection REFSEL1 0 0 1 1 Par ameter REFSEL0 0 1 0 1 Applied Refer ence Fr equency 19.44 MHz 38.88 MHz 77.76 MHz 155.52 MHz TABLE 4. Cr ystal Specification - see note (3) Value Mode Frequency / Overall Stability Frequency Accuracy Temp. Stability Ageing ESR Series Resonant 19.44 MHz / +/- 50 ppm +/- 50 ppm / total Temp. Stability 20 ohms max (3) No additional external components are required TABLE 5. Recommended Capacitor Specification Par ameter Capacitance Leakage Rating REV. PrB Oct. .2001 Value (-40C to 85C) >3.0uF (-40C to 85C) <80nA >6.3V - 11 - ADN2809 ADN2809 PIN DESCRIPTION Pin No. 2,26,28, Exposed Pad 3,9,27,29, 42 20,35,36,47 1 4 5 6 7 8 10 11 12 13 14 15 17 18 21 23 24 25 30 31 32 37 38 39 40 41 44 45 48 Name VCC VEE VCC THRADJ VREGF PIN NIN SLICEP SLICEN LOL XO XO REFCLKN REFCLKP REFSEL TDINP TDINN CF1 REFSEL1 REFSEL0 CF2 SEL2 SEL1 SEL0 DATAOUTN DATAOUTP SQUELCH CLKOUTN CLKOUTP BYPASS SDOUT LOOPEN I/O P G P I/O I/O I I I I O O O I I I I I I/O I I I/O I I I O O I O O I O I Level 3.3V 0V 3.3V Analog I/O Analog I/O Analog current Analog current Analog voltage Analog voltage LVTTL / LVCMOS Analog output Analog output Any Any LVTTL / LVCMOS CML CML Analog I/O LVTTL / LVCMOS LVTTL / LVCMOS Analog I/O LVTTL / LVCMOS LVTTL / LVCMOS LVTTL / LVCMOS CML CML LVTTL / LVCMOS CML CML LVTTL / LVCMOS LVTTL / LVCMOS LVTTL / LVCMOS ADN2809 PIN CONFIGURATION REV. PrB Oct. .2001 - 12 - Descr iption Analog Power Analog ground Digital supply LOS threshold setting resistor Reference capacitor Differential data signal input Differential data signal input Slice level Slice level High level indicates loss of lock Crystal oscillator Crystal oscillator Differential reference clock Differential reference clock Reference source select Differential test data input Differential test data input Frequency loop capacitor Reference rate select Reference rate select Frequency loop capacitor Data rate select Data rate select Data rate select Differential recovered data Differential recovered data Disable clock and data outputs Differential retimed clock Differential retimed clock Disable clock and data recovery High level indicates loss of signal Enable high speed test data inputs ADN2809 Mechanical Outline Dimensions Dimensions shown in millimeters and (inches). REV. PrB Oct. .2001 - 13 -