022CY7C10 PRELIMINARY CY7C1022 32K x 16 Static RAM Features • 5.0V operation (± 10%) • High speed — tAA = 12 ns • Low active power — 825 mW (max., 10 ns, “L” version) • Very Low standby power — 500 µW (max., “L” version) • Automatic power-down when deselected • Independent Control of Upper and Lower bytes • Available in 400-mil SOJ Functional Description The CY7C1022 is a high-performance CMOS static RAM organized as 32,768 words by 16 bits. This device has an automatic power-down feature that significantly reduces power consumption when deselected. enable (BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is written into the location specified on the address pins (A0 through A14). If byte high enable (BHE) is LOW, then data from I/O pins (I/O9 through I/O16) is written into the location specified on the address pins (A0 through A14). Reading from the device is accomplished by taking chip enable (CE) HIGH and output enable (OE) LOW while forcing the write enable (WE) HIGH. If byte low enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O1 to I/O8. If byte high enable (BHE) is LOW, then data from memory will appear on I/O9 to I/O16. See the truth table at the back of this data sheet for a complete description of read and write modes. The input/output pins (I/O1 through I/O16) are placed in a high-impedance state when the device is deselected (CE LOW), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE HIGH, and WE LOW). The CY7C1022 is available in standard 400-mil-wide SOJ packages. Writing to the device is accomplished by taking chip enable (CE) input HIGH and write enable (WE) input LOW. If byte low Logic Block Diagram Pin Configuration SOJ Top View SENSE AMPS A6 A5 A4 A3 A2 A1 A0 ROW DECODER DATA IN DRIVERS 32K x 16 RAM Array NC A 14 A 13 A 12 A11 CE I/O1 I/O2 I/O3 I/O4 VCC VSS I/O5 I/O6 I/O7 I/O8 WE A10 A9 A8 A7 NC I/O1 – I/O8 I/O9 – I/O16 COLUMN DECODER A7 A8 A9 A10 A11 A12 A13 A14 BHE WE CE OE BLE 1 44 2 3 43 42 4 41 40 39 38 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A0 A1 A2 OE BHE BLE I/O16 I/O15 I/O14 I/O13 VSS VCC I/O12 I/O11 I/O10 I/O9 NC A3 A4 A5 A6 NC 1022-2 2CY7C1022 Selection Guide 7C1022-12 7C1022-15 Maximum Access Time (ns) 12 15 Maximum Operating Current (mA) 170 160 L 140 130 3 3 L 0.1 0.1 Maximum CMOS Standby Current (mA) Shaded areas contain advance information. Cypress Semiconductor Corporation Document #: 38-05090 Rev. ** • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised September 18, 2001 PRELIMINARY CY7C1022 DC Input Voltage[1] ................................ –0.5V to VCC + 0.5V Maximum Ratings Current into Outputs (LOW) ........................................ 20 mA (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................–65×C to +150×C Operating Range Ambient Temperature with Power Applied............................................–55×C to +125×C Range Commercial Supply Voltage on VCC to Relative GND[1] .... –0.5V to +7.0V Ambient Temperature[2] VCC 0°C to +70°C 4.5V–5.5V DC Voltage Applied to Outputs in High Z State[1] ....................................–0.5V to VCC + 0.5V Electrical Characteristics Over the Operating Range 7C1022-12 Parameter Description Test Conditions VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA VIH Input HIGH Voltage Min. 7C1022-15 Max. Min. 2.4 Unit 2.4 0.4 [1] Max. V 0.4 V 2.2 6.0 2.2 6.0 V –0.5 0.8 –0.5 0.8 V VIL Input LOW Voltage IIX Input Load Current GND < VI < VCC –1 +1 –1 +1 µA IOZ Output Leakage Current GND < VI < VCC, Output Disabled –2 +2 –2 +2 µA ICC VCC Operating Supply Current VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC 170 160 mA 140 130 Automatic CE Power-Down Current —TTL Inputs Max. VCC, CE > VIH VIN > VIH or VIN < VIL, f = fMAX 20 20 10 10 Automatic CE Power-Down Current —CMOS Inputs Max. VCC, CE > VCC – 0.3V, VIN > VCC – 0.3V, or VIN < 0.3V, f=0 3 3 mA 0.1 0.1 mA ISB1 ISB2 L L L mA Shaded area contains advance information. Capacitance[3] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions Max. Unit 8 pF 8 pF TA = 25°C, f = 1 MHz, VCC = 5.0V AC Test Loads and Waveforms R 481 Ω R 481 Ω 5V ALL INPUT PULSES 5V OUTPUT 3.0V 90% OUTPUT 30 pF R2 255Ω INCLUDING JIG AND SCOPE (a) OUTPUT Equivalent to: THÉVENIN EQUIVALENT R2 255Ω 5 pF INCLUDING JIG AND SCOPE 167Ω GND <3ns (b) 10% 90% 10% <3ns 1022-3 1022-4 1.73V 30 pF Notes: 1. VIL (min.) = –2.0V for pulse durations of less than 20 ns. 2. TA is the “instant on” case temperature. 3. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05090 Rev. ** Page 2 of 8 PRELIMINARY CY7C1022 Switching Characteristics[4] Over the Operating Range 7C1022-12 Parameter Description Min. Max. 7C1022-15 Min. Max. Unit READ CYCLE tRC Read Cycle Time 12 tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE HIGH to Data Valid tDOE OE LOW to Data Valid tLZOE OE LOW to Low Z 12 3 [6] 15 6 0 OE HIGH to High Z ns 3 12 [5, 6] tHZOE 15 ns 15 ns 7 ns 0 6 ns 7 3 ns tLZCE CE HIGH to Low Z tHZCE CE LOW to High Z[5, 6] tPU CE HIGH to Power-Up tPD CE LOW to Power-Down 12 15 ns tDBE Byte enable to Data Valid 6 7 ns tLZBE Byte enable to Low Z tHZBE 3 ns 6 0 0 0 Byte disable to High Z ns 7 ns 0 6 ns ns 7 ns [7] WRITE CYCLE tWC Write Cycle Time 12 15 ns tSCE CE HIGH to Write End 9 10 ns tAW Address Set-Up to Write End 8 10 ns tHA Address Hold from Write End 0 0 ns tSA Address Set-Up to Write Start 0 0 ns tPWE WE Pulse Width 8 10 ns tSD Data Set-Up to Write End 6 10 ns tHD Data Hold from Write End 0 0 ns [6] tLZWE WE HIGH to Low Z tHZWE WE LOW to High Z[5, 6] tBW Byte enable to end of write 3 3 6 8 ns 7 9 ns ns Notes: 4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 5. tHZOE, tHZBE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage. 6. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 7. The internal write time of the memory is defined by the overlap of CE HIGH, WE LOW and BHE / BLE LOW. CE HIGH, WE and BHE / BLE must be LOW to initiate a write, and the transition of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. Document #: 38-05090 Rev. ** Page 3 of 8 PRELIMINARY CY7C1022 Switching Waveforms Read Cycle No.1 [8, 9] tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID 1022-5 Read Cycle No.2 (OE Controlled) [9, 10] ADDRESS CE tRC tACE OE tHZOE tDOE BHE, BLE tLZOE tHZCE tDBE tLZBE DATA OUT HIGH IMPEDANCE tLZCE V CC SUPPLY CURRENT tHZBE HIGH IMPEDANCE DATA VALID tPD tPU 50% IICC CC 50% IISB SB 1022-6 Notes: 8. Device is continuously selected. OE, CE, BHE and/or BHE = VIL 9. WE is HIGH for read cycle. 10. Address valid prior to or coincident with CE transition HIGH. Document #: 38-05090 Rev. ** Page 4 of 8 PRELIMINARY CY7C1022 Switching Waveforms (continued) Write Cycle No. 1 (CE Controlled) [11, 12] tWC ADDRESS tSA tSCE CE tAW tHA tPWE WE tBW BHE, BLE tSD tHD DATAI/O 1022-7 Write Cycle No. 2 (BLE or BHE Controlled) tWC ADDRESS BHE, BLE tSA tBW tAW tHA tPWE WE tSCE CE tSD tHD DATAI/O 1022-8 Notes: 11. Data I/O is high impedance if OE or BHE and/or BLE= VIH. 12. If CE goes LOW simultaneously with WE going HIGH, the output remains in a high-impedance state. Document #: 38-05090 Rev. ** Page 5 of 8 PRELIMINARY CY7C1022 Switching Waveforms (continued) Write Cycle No.3 (WE Controlled, OE LOW) tWC ADDRESS tSCE CE tAW tHA tSA tPWE WE tBW BHE, BLE tHZWE tSD tHD DATA I/O tLZWE 1022-10 Truth Table CE OE WE BLE BHE L X X X X High Z High Z Power-Down Standby (ISB) H L H L L Data Out Data Out Read - All bits Active (ICC) L H Data Out High Z Read - Lower bits only Active (ICC) H L High Z Data Out Read - Upper bits only Active (ICC) L L Data In Data In Write - All bits Active (ICC) L H Data In High Z Write - Lower bits only Active (ICC) H L High Z Data In Write - Upper bits only Active (ICC) H X L I/O1 - I/O8 I/O9 - I/O16 Mode Power H H H X X High Z High Z Selected, Outputs Disabled Active (ICC) H X X H H High Z High Z Selected, Outputs Disabled Active (ICC) Ordering Information Speed (ns) 12 Ordering Code CY7C1022-12VC Document #: 38-05090 Rev. ** Package Name V34 Package Type 44-Lead (400-Mil) Molded SOJ Operating Range Commercial Page 6 of 8 PRELIMINARY CY7C1022 Package Diagram 44-Lead (400-Mil) Molded SOJ V34 Document #: 38-05090 Rev. ** Page 7 of 8 © Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. PRELIMINARY CY7C1022 Document Title: CY7C1022 32k x 16 Static RAM Data Sheet Document Number: 38-05090 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 110184 09/29/01 SZV Change from Spec number: 38-00636 to 38-05090 Document #: 38-05090 Rev. ** Page 8 of 8