ATMEL ATtiny48-MMU 8-bit microcontroller with 4/8k bytes in-system programmable flash Datasheet

Features
• High Performance, Low Power AVR® 8-Bit Microcontroller
• Advanced RISC Architecture
•
•
•
•
•
•
•
•
– 123 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
High Endurance Non-volatile Memory Segments
– 4K/8K Bytes of In-System Self-Programmable Flash program memory(ATtiny48/88)
– 64/64 Bytes EEPROM (ATtiny48/88)
– 256/512 Bytes Internal SRAM (ATtiny48/88)
– Write/Erase Cycles: 10,000 Flash/100,000 EEPROM
– Data retention: 20 years at 85°C / 100 years at 25°C
– Programming Lock for Software Security
Peripheral Features
– One 8-bit Timer/Counter with Separate Prescaler and Compare Mode
– One 16-bit Timer/Counter with Prescaler, and Compare and Capture Modes
– 8-channel 10-bit ADC in 32-lead TQFP and 32-pad QFN/MLF package
– 6-channel 10-bit ADC in 28-pin PDIP and 28-pad QFN/MLF package
– Master/Slave SPI Serial Interface
– Byte-oriented 2-wire Serial Interface (Philips I2C Compatible)
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– Interrupt and Wake-up on Pin Change
Special Microcontroller Features
– debugWIRE On-chip Debug System
– In-System Programmable via SPI Port
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated Oscillator
– External and Internal Interrupt Sources
– Three Sleep Modes: Idle, ADC Noise Reduction and Power-down
I/O and Packages
– 28 Programmable I/O Lines in 32-lead TQFP and 32-pad QFN/MLF package
– 24 Programmable I/O Lines in 28-pin PDIP and 28-pad QFN/MLF package
– 28-pin PDIP, 32-lead TQFP, 28-pad QFN/MLF and 32-pad QFN/MLF
Operating Voltage:
– 1.8 – 5.5V
Temperature Range:
– -40°C to +85°C
Speed Grade:
– 0 – 4 MHz @ 1.8 – 5.5V
– 0 – 8 MHz @ 2.7 – 5.5V
– 0 – 12 MHz @ 4.5 – 5.5V
Low Power Consumption
– Active Mode: 1 MHz, 1.8V: 240µA
– Power-down Mode: 0.1µA at 1.8V
8-bit
Microcontroller
with 4/8K Bytes
In-System
Programmable
Flash
ATtiny48/88
Preliminary
Rev. 8008C–AVR–03/09
1. Pin Configurations
Figure 1-1.
Pinout of ATtiny48/88
PD2 (INT0/PCINT18)
PD1 (PCINT17)
PD0 (PCINT16)
PC6 (RESET/PCINT14)
PC5 (ADC5/SCL/PCINT13)
PC4 (ADC4/SDA/PCINT12)
PC3 (ADC3/PCINT11)
PC2 (ADC2/PCINT10)
TQFP Top View
32
31
30
29
28
27
26
25
PDIP
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
PC1 (ADC1/PCINT9)
PC0 (ADC0/PCINT8)
PA1 (ADC7/PCINT25)
GND
PC7 (PCINT15)
PA0 (ADC6/PCINT24)
AVCC
PB5 (SCK/PCINT5)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PC5 (ADC5/SCL/PCINT13)
PC4 (ADC4/SDA/PCINT12)
PC3 (ADC3/PCINT11)
PC2 (ADC2/PCINT10)
PC1 (ADC1/PCINT9)
PC0 (ADC0/PCINT8)
GND
PC7 (PCINT15)
AVCC
PB5 (SCK/PCINT5)
PB4 (MISO/PCINT4)
PB3 (MOSI/PCINT3)
PB2 (SS/OC1B/PCINT2)
PB1 (OC1A/PCINT1)
24
23
22
21
20
19
18
17
PC1 (ADC1/PCINT9)
PC0 (ADC0/PCINT8)
PA1 (ADC7/PCINT25)
GND
PC7 (PCINT15)
PA0 (ADC6/PCINT24)
AVCC
PB5 (SCK/PCINT5)
(PCINT21/T1) PD5
(PCINT22/AIN0) PD6
(PCINT23/AIN1) PD7
(PCINT0/CLKO/ICP1) PB0
(PCINT1/OC1A) PB1
(PCINT2/SS/OC1B) PB2
(PCINT3/MOSI) PB3
(PCINT4/MISO) PB4
9
10
11
12
13
14
15
16
(PCINT19/INT1) PD3
(PCINT20/T0) PD4
(PCINT26) PA2
VCC
GND
(PCINT27) PA3
(PCINT6/CLKI) PB6
(PCINT7) PB7
(PCINT14/RESET) PC6
(PCINT16) PD0
(PCINT17) PD1
(PCINT18/INT0) PD2
(PCINT19/INT1) PD3
(PCINT20/T0) PD4
VCC
GND
(PCINT6/CLKI) PB6
(PCINT7) PB7
(PCINT21/T1) PD5
(PCINT22/AIN0) PD6
(PCINT23/AIN1) PD7
(PCINT0/CLKO/ICP1) PB0
32 MLF Top View
28
27
26
25
24
23
22
32
31
30
29
28
27
26
25
PD2 (INT0/PCINT18)
PD1 (PCINT17)
PD0 (PCINT16)
PC6 (RESET/PCINT14)
PC5 (ADC5/SCL/PCINT13)
PC4 (ADC4/SDA/PCINT12)
PC3 (ADC3/PCINT11)
PD2 (INT0/PCINT18)
PD1 (PCINT17)
PD0 (PCINT16)
PC6 (RESET/PCINT14)
PC5 (ADC5/SCL/PCINT13)
PC4 (ADC4/SDA/PCINT12)
PC3 (ADC3/PCINT11)
PC2 (ADC2/PCINT10)
28 MLF Top View
PC2 (ADC2/PCINT10)
PC1 (ADC1/PCINT9)
PC0 (ADC0/PCINT8)
GND
PC7 (PCI NT15)
AVCC
PB5 (SCK/PCINT5)
(PCINT19/INT1) PD3
(PCINT20/T0) PD4
(PCINT26) PA2
VCC
GND
(PCINT27) PA3
(PCINT6/CLKI) PB6
(PCINT7) PB7
1
2
3
4
5
6
7
8
2
(PCINT22/AIN0) PD6
(PCINT23/AIN1) PD7
(PCINT0/CLKO/ICP1) PB0
(PCINT1/OC1A) PB1
(PCINT2/SS/OC1B) PB2
(PCINT3//MOSI) PB3
(PCINT4/MISO) PB4
NOTE: Bottom pad should be soldered to ground.
9
10
11
12
13
14
15
16
NOTE: Bottom pad should be soldered to ground.
(PCINT21/T1) PD5
(PCINT22/AIN0) PD6
(PCINT23/AIN1) PD7
(PCINT0/CLKO/ICP1) PB0
(PCINT1/OC1A) PB1
(PCINT2/SS/OC1B) PB2
(PCINT3/MOSI) PB3
(PCINT4/MISO) PB4
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
(PCINT19/INT1) PD3
(PCINT20/T0) PD4
VCC
GND
(PCINT6/CLKI) PB6
(PCINT7) PB7
(PCINT21/T1) PD5
ATtiny48/88
8008C–AVR–03/09
ATtiny48/88
1.1
1.1.1
Pin Descriptions
VCC
Digital supply voltage.
1.1.2
GND
Ground.
1.1.3
Port A (PA3:0) (in 32-lead TQFP and 32-pad QFN/MLF packages, only)
Port A is a 4-bit bi-directional I/O port with internal pull-up resistors (selected for each bit) in 32lead TQFP and 32-pad QFN/MLF package. The PA3..0 output buffers have symmetrical drive
characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tristated when a reset condition becomes active, even if the clock is not running.
1.1.4
Port B (PB7:0)
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port B output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Depending on the clock selection fuse settings, PB6 can be used as input to the internal clock
operating circuit.
The various special features of Port B are elaborated in “Alternate Functions of Port B” on page
64 and “System Clock and Clock Options” on page 25.
1.1.5
Port C (PC7, PC5:0)
Port C is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
PC7 and PC5..0 output buffers have symmetrical drive characteristics with both high sink and
source capability. As inputs, Port C pins that are externally pulled low will source current if the
pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes
active, even if the clock is not running.
1.1.6
PC6/RESET
If the RSTDISBL Fuse is programmed, PC6 is used as an I/O pin. Note that the electrical characteristics of PC6 differ from those of the other pins of Port C.
If the RSTDISBL Fuse is unprogrammed, PC6 is used as a reset input. A low level on this pin for
longer than the minimum pulse width will generate a reset, even if the clock is not running. The
minimum pulse length is given in Table 21-3 on page 204. Shorter pulses are not guaranteed to
generate a reset.
The various special features of Port C are elaborated in “Alternate Functions of Port C” on page
67.
1.1.7
Port D (PD7:0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
PD7..4 output buffers have symmetrical drive characteristics with both high sink and source
capabilities, while the PD3..0 output buffers have stronger sink capabilities. As inputs, Port D
3
8008C–AVR–03/09
pins that are externally pulled low will source current if the pull-up resistors are activated. The
Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running.
The various special features of Port D are elaborated in “Alternate Functions of Port D” on page
70.
1.1.8
AVCC
AVCC is the supply voltage pin for the A/D converter and a selection of I/O pins. This pin should
be externally connected to VCC even if the ADC is not used. If the ADC is used, it is recommended this pin is connected to VCC through a low-pass filter, as described in “Analog Noise
Canceling Techniques” on page 166.
The following pins receive their supply voltage from AVCC: PC7, PC5:0 and (in 32-lead packages) PA1:0. All other I/O pins take their supply voltage from VCC.
4
ATtiny48/88
8008C–AVR–03/09
ATtiny48/88
2. Overview
The ATtiny48/88 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC
architecture. By executing powerful instructions in a single clock cycle, the ATtiny48/88 achieves
throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.
Block Diagram
Block Diagram
GND
Figure 2-1.
VCC
2.1
Watchdog
Timer
Watchdog
Oscillator
Power
Supervision
POR / BOD &
RESET
debugWIRE
Flash
SRAM
Oscillator
Circuits /
Clock
Generation
Program
Logic
CPU
EEPROM
8bit T/C 0
16bit T/C 1
A/D Conv.
DATABUS
2
6
Internal
Bandgap
Analog
Comp.
PORT D (8)
SPI
PORT B (8)
TWI
PORT C (8)
PORT A (4)
RESET
CLKI
PD[0..7]
PB[0..7]
PC[0..7]
PA[0..3] (in TQFP and MLF)
The AVR core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
5
8008C–AVR–03/09
The ATtiny48/88 provides the following features: 4/8K bytes of In-System Programmable Flash,
64/64 bytes EEPROM, 256/512 bytes SRAM, 24 general purpose I/O lines (28 I/Os in 32-lead
TQFP and 32-pad QFN/MLF packages), 32 general purpose working registers, two flexible
Timer/Counters with compare modes, internal and external interrupts, a byte-oriented 2-wire
serial interface, an SPI serial port, a 6-channel 10-bit ADC (8 channels in 32-lead TQFP and 32pad QFN/MLF packages), a programmable Watchdog Timer with internal oscillator, and three
software selectable power saving modes. Idle mode stops the CPU while allowing Timer/Counters, 2-wire serial interface, SPI port, and interrupt system to continue functioning. Power-down
mode saves the register contents but freezes the oscillator, disabling all other chip functions until
the next interrupt or hardware reset. ADC Noise Reduction mode stops the CPU and all I/O
modules except ADC, and helps to minimize switching noise during ADC conversions.
The device is manufactured using Atmel’s high density non-volatile memory technology. The
On-chip ISP Flash allows the program memory to be reprogrammed In-System through an SPI
serial interface, by a conventional non-volatile memory programmer, or by an on-chip boot program running on the AVR core. The boot program can use any interface to download the
application program in the Flash memory. By combining an 8-bit RISC CPU with In-System SelfProgrammable Flash on a monolithic chip, the Atmel ATtiny48/88 is a powerful microcontroller
that provides a highly flexible and cost effective solution to many embedded control applications.
The ATtiny48/88 AVR is supported by a full suite of program and system development tools
including: C compilers, macro assemblers, program debugger/simulators and evaluation kits.
2.2
Comparison Between ATtiny48 and ATtiny88
The ATtiny48 and ATtiny88 differ only in memory sizes. Table 2-1 summarizes the different
memory sizes for the two devices.
Table 2-1.
6
Memory Size Summary
Device
Flash
EEPROM
RAM
ATtiny48
4K Bytes
64 Bytes
256 Bytes
ATtiny88
8K Bytes
64 Bytes
512 Bytes
ATtiny48/88
8008C–AVR–03/09
ATtiny48/88
3. Additional Information
3.1
Resources
A comprehensive set of development tools, application notes and datasheets are available for
download at http://www.atmel.com/avr.
3.2
About Code Examples
This documentation contains simple code examples that briefly show how to use various parts of
the device. These code examples assume that the part specific header file is included before
compilation. Be aware that not all C compiler vendors include bit definitions in the header files
and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details.
For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI”
instructions must be replaced with instructions that allow access to extended I/O. Typically
“LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.
3.3
Data Retention
Reliability Qualification results show that the projected data retention failure rate is much less
than 1 PPM over 20 years at 85°C or 100 years at 25°C.
3.4
Disclaimer
Typical values contained in this datasheet are based on simulations and characterization of
other AVR microcontrollers manufactured on the same process technology. Min and Max values
will be available after the device is characterized.
7
8008C–AVR–03/09
4. AVR CPU Core
4.1
Introduction
This section discusses the AVR core architecture in general. The main function of the CPU core
is to ensure correct program execution. The CPU must therefore be able to access memories,
perform calculations, control peripherals, and handle interrupts.
4.2
Architectural Overview
Figure 4-1.
Block Diagram of the AVR Architecture
Data Bus 8-bit
Flash
Program
Memory
Program
Counter
Status
and Control
32 x 8
General
Purpose
Registrers
Control Lines
Direct Addressing
Instruction
Decoder
Indirect Addressing
Instruction
Register
Interrupt
Unit
SPI
Unit
Watchdog
Timer
ALU
Analog
Comparator
I/O Module1
Data
SRAM
I/O Module 2
I/O Module n
EEPROM
I/O Lines
In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with
separate memories and buses for program and data. Instructions in the program memory are
executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed
in every clock cycle. The program memory is In-System Reprogrammable Flash memory.
8
ATtiny48/88
8008C–AVR–03/09
ATtiny48/88
The fast-access Register File contains 32 x 8-bit general purpose working registers with a single
clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed,
and the result is stored back in the Register File – in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data
Space addressing – enabling efficient address calculations. One of the these address pointers
can also be used as an address pointer for look up tables in Flash program memory. These
added function registers are the 16-bit X-, Y-, and Z-register, described later in this section.
The ALU supports arithmetic and logic operations between registers or between a constant and
a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation.
Program flow is provided by conditional and unconditional jump and call instructions, able to
directly address the whole address space. Most AVR instructions have a single 16-bit word format, but there are also 32-bit instructions.
During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the
Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack
size is only limited by the total SRAM size and the usage of the SRAM. All user programs must
initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack
Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed
through the five different addressing modes supported in the AVR architecture.
The memory spaces in the AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional Global
Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the
Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other I/O functions. The I/O Memory can be accessed directly, or as the Data
Space locations following those of the Register File, 0x20 – 0x5F. In addition, the ATtiny48/88
has Extended I/O space from 0x60 – 0xFF in SRAM where only the ST/STS/STD and
LD/LDS/LDD instructions can be used.
4.3
ALU – Arithmetic Logic Unit
The high-performance AVR ALU operates in direct connection with all the 32 general purpose
working registers. Within a single clock cycle, arithmetic operations between general purpose
registers or between a register and an immediate are executed. The ALU operations are divided
into three main categories – arithmetic, logical, and bit-functions. Some implementations of the
architecture also provide a powerful multiplier supporting both signed/unsigned multiplication
and fractional format. See the “Instruction Set” section for a detailed description.
4.4
Status Register
The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform
conditional operations. Note that the Status Register is updated after all ALU operations, as
specified in the Instruction Set Reference. This will in many cases remove the need for using the
dedicated compare instructions, resulting in faster and more compact code.
9
8008C–AVR–03/09
The Status Register is not automatically stored when entering an interrupt routine and restored
when returning from an interrupt. This must be handled by software.
The AVR Status Register – SREG – is defined as:
Bit
7
6
5
4
3
2
1
0
I
T
H
S
V
N
Z
C
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
SREG
• Bit 7 – I: Global Interrupt Enable
The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable
Register is cleared, none of the interrupts are enabled independent of the individual interrupt
enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by
the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by
the application with the SEI and CLI instructions, as described in the instruction set reference.
• Bit 6 – T: Bit Copy Storage
The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the Register File can be copied into T by the
BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the
BLD instruction.
• Bit 5 – H: Half Carry Flag
The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Is useful
in BCD arithmetic. See the “Instruction Set Description” for detailed information.
• Bit 4 – S: Sign Bit, S = N ⊕ V
The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement
Overflow Flag V. See the “Instruction Set Description” for detailed information.
• Bit 3 – V: Two’s Complement Overflow Flag
The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the
“Instruction Set Description” for detailed information.
• Bit 2 – N: Negative Flag
The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the
“Instruction Set Description” for detailed information.
• Bit 1 – Z: Zero Flag
The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction
Set Description” for detailed information.
• Bit 0 – C: Carry Flag
The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set
Description” for detailed information.
10
ATtiny48/88
8008C–AVR–03/09
ATtiny48/88
4.5
General Purpose Register File
The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve
the required performance and flexibility, the following input/output schemes are supported by the
Register File:
• One 8-bit output operand and one 8-bit result input
• Two 8-bit output operands and one 8-bit result input
• Two 8-bit output operands and one 16-bit result input
• One 16-bit output operand and one 16-bit result input
Figure 4-2 shows the structure of the 32 general purpose working registers in the CPU.
Figure 4-2.
AVR CPU General Purpose Working Registers
7
0
Addr.
R0
0x00
R1
0x01
R2
0x02
…
R13
0x0D
General
R14
0x0E
Purpose
R15
0x0F
Working
R16
0x10
Registers
R17
0x11
…
R26
0x1A
X-register Low Byte
R27
0x1B
X-register High Byte
R28
0x1C
Y-register Low Byte
R29
0x1D
Y-register High Byte
R30
0x1E
Z-register Low Byte
R31
0x1F
Z-register High Byte
Most of the instructions operating on the Register File have direct access to all registers, and
most of them are single cycle instructions.
As shown in Figure 4-2, each register is also assigned a data memory address, mapping them
directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the
registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file.
11
8008C–AVR–03/09
4.5.1
The X-register, Y-register, and Z-register
The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect
address registers X, Y, and Z are defined as described in Figure 4-3.
Figure 4-3.
The X-, Y-, and Z-registers
15
X-register
XH
XL
7
0
R27 (0x1B)
15
Y-register
0
R26 (0x1A)
YH
YL
7
0
R29 (0x1D)
Z-register
0
7
0
7
0
R28 (0x1C)
15
ZH
7
0
ZL
7
R31 (0x1F)
0
0
R30 (0x1E)
In the different addressing modes these address registers have functions as fixed displacement,
automatic increment, and automatic decrement (see the instruction set reference for details).
4.6
Stack Pointer
The Stack is mainly used for storing temporary data, for storing local variables and for storing
return addresses after interrupts and subroutine calls. The Stack Pointer Register always points
to the top of the Stack. Note that the Stack is implemented as growing from higher memory locations to lower memory locations. This implies that a Stack PUSH command decreases the Stack
Pointer.
The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt
Stacks are located. This Stack space in the data SRAM must be defined by the program before
any subroutine calls are executed or interrupts are enabled. The Stack Pointer should be set to
point to RAMEND. The Stack Pointer is decremented by one when data is pushed onto the
Stack with the PUSH instruction, and it is decremented by two when the return address is
pushed onto the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one
when data is popped from the Stack with the POP instruction, and it is incremented by two when
data is popped from the Stack with return from subroutine RET or return from interrupt RETI.
The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of
bits actually used is implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register
will not be present.
Bit
Read/Write
Initial Value
12
15
14
13
12
11
10
9
8
SP15
SP14
SP13
SP12
SP11
SP10
SP9
SP8
SPH
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP0
SPL
7
6
5
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RAMEND
RAMEND
RAMEND
RAMEND
RAMEND
RAMEND
RAMEND
RAMEND
RAMEND
RAMEND
RAMEND
RAMEND
RAMEND
RAMEND
RAMEND
RAMEND
ATtiny48/88
8008C–AVR–03/09
ATtiny48/88
4.7
Instruction Execution Timing
This section describes the general access timing concepts for instruction execution. The AVR
CPU is driven by the CPU clock clkCPU, directly generated from the selected clock source for the
chip. No internal clock division is used.
Figure 4-4 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access Register File concept. This is the basic pipelining concept
to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost,
functions per clocks, and functions per power-unit.
Figure 4-4.
The Parallel Instruction Fetches and Instruction Executions
T1
T2
T3
T4
clkCPU
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
Figure 4-5 shows the internal timing concept for the Register File. In a single clock cycle an ALU
operation using two register operands is executed, and the result is stored back to the destination register.
Figure 4-5.
Single Cycle ALU Operation
T1
T2
T3
T4
clkCPU
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
4.8
Reset and Interrupt Handling
The AVR provides several different interrupt sources. These interrupts and the separate Reset
Vector each have a separate program vector in the program memory space. All interrupts are
assigned individual enable bits which must be written logic one together with the Global Interrupt
Enable bit in the Status Register in order to enable the interrupt. Depending on the Program
Counter value, interrupts may be automatically disabled when Lock Bits LB2 or LB1 are programmed. This feature improves software security. See the section “Memory Programming” on
page 184 for details.
The lowest addresses in the program memory space are by default defined as the Reset and
Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 47. The list also
determines the priority levels of the different interrupts. The lower the address the higher is the
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8008C–AVR–03/09
priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request
0. Refer to “Interrupts” on page 47 for more information.
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled
interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a
Return from Interrupt instruction – RETI – is executed.
There are basically two types of interrupts. The first type is triggered by an event that sets the
Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding
Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s)
to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is
cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is
cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt
Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the
Global Interrupt Enable bit is set, and will then be executed by order of priority.
The second type of interrupts will trigger as long as the interrupt condition is present. These
interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the
interrupt is enabled, the interrupt will not be triggered.
When the AVR exits from an interrupt, it will always return to the main program and execute one
more instruction before any pending interrupt is served.
Note that the Status Register is not automatically stored when entering an interrupt routine, nor
restored when returning from an interrupt routine. This must be handled by software.
When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled.
No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the
CLI instruction. The following example shows how this can be used to avoid interrupts during the
timed EEPROM write sequence.
Assembly Code Example
in r16, SREG
cli
; store SREG value
; disable interrupts during timed sequence
sbi EECR, EEMPE
; start EEPROM write
sbi EECR, EEPE
out SREG, r16
; restore SREG value (I-bit)
C Code Example
char cSREG;
cSREG = SREG; /* store SREG value */
/* disable interrupts during timed sequence */
_CLI();
EECR |= (1<<EEMPE); /* start EEPROM write */
EECR |= (1<<EEPE);
SREG = cSREG; /* restore SREG value (I-bit) */
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ATtiny48/88
When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in this example.
Assembly Code Example
sei
; set Global Interrupt Enable
sleep; enter sleep, waiting for interrupt
; note: will enter sleep before any pending interrupt(s)
C Code Example
__enable_interrupt(); /* set Global Interrupt Enable */
__sleep(); /* enter sleep, waiting for interrupt */
/* note: will enter sleep before any pending interrupt(s) */
4.8.1
Interrupt Response Time
The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum. After four clock cycles the program vector address for the actual interrupt handling routine
is executed. During this four clock cycle period, the Program Counter is pushed onto the Stack.
The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If
an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed
before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt
execution response time is increased by four clock cycles. This increase comes in addition to the
start-up time from the selected sleep mode.
A return from an interrupt handling routine takes four clock cycles. During these four clock
cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is
incremented by two, and the I-bit in SREG is set.
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8008C–AVR–03/09
5. Memories
This section describes the different memories in the ATtiny48/88. The AVR architecture has two
main memory spaces, the Data Memory and the Program Memory space. In addition, the
ATtiny48/88 features an EEPROM Memory for data storage. All three memory spaces are linear
and regular.
5.1
In-System Reprogrammable Flash Program Memory
The ATtiny48/88 contains 4/8K bytes On-chip In-System Reprogrammable Flash memory for
program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as
2/4K x 16. ATtiny48/88 does not have separate Boot Loader and Application Program sections,
and the SPM instruction can be executed from the entire Flash. See SELFPRGEN description in
section “SPMCSR – Store Program Memory Control and Status Register” on page 182 for more
details.
The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATtiny48/88
Program Counter (PC) is 11/12 bits wide, thus addressing the 2/4K program memory locations.
“Memory Programming” on page 184 contains a detailed description on Flash Programming in
SPI- or Parallel Programming mode.
Constant tables can be allocated within the entire program memory address space (see instructions LPM – Load Program Memory and SPM – Store Program Memory).
Timing diagrams for instruction fetch and execution are presented in “Instruction Execution Timing” on page 13.
Figure 5-1.
Program Memory Map of ATtiny48/88
Program Memory
0x0000
Application Flash Section
0x07FF/0x0FFF
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ATtiny48/88
5.2
SRAM Data Memory
Figure 5-2 shows how the ATtiny48/88 SRAM Memory is organized.
The ATtiny48/88 is a complex microcontroller with more peripheral units than can be supported
within the 64 locations reserved in the Opcode for the IN and OUT instructions. For the
Extended I/O space from 0x60 – 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD
instructions can be used.
The lower 512/768 data memory locations address both the Register File, the I/O memory,
Extended I/O memory, and the internal data SRAM. The first 32 locations address the Register
File, the next 64 location the standard I/O memory, then 160 locations of Extended I/O memory,
and the next 256/512 locations address the internal data SRAM.
The five different addressing modes for the data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register
File, registers R26 to R31 feature the indirect addressing pointer registers.
The direct addressing reaches the entire data space.
The Indirect with Displacement mode reaches 63 address locations from the base address given
by the Y- or Z-register.
When using register indirect addressing modes with automatic pre-decrement and post-increment, the address registers X, Y, and Z are decremented or incremented.
The 32 general purpose working registers, 64 I/O Registers, 160 Extended I/O Registers, and
the 256/512 bytes of internal data SRAM in the ATtiny48/88 are all accessible through all these
addressing modes. The Register File is described in “General Purpose Register File” on page
11.
Figure 5-2.
Data Memory Map
Data Memory
32 Registers
64 I/O Registers
160 Ext I/O Reg.
0x0000 - 0x001F
0x0020 - 0x005F
0x0060 - 0x00FF
0x0100
Internal SRAM
(256/512 x 8)
0x01FF/0x02FF
5.2.1
Data Memory Access Times
This section describes the general access timing concepts for internal memory access. The
internal data SRAM access is performed in two clkCPU cycles as described in Figure 5-3.
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8008C–AVR–03/09
Figure 5-3.
On-chip Data SRAM Access Cycles
T1
T2
T3
clkCPU
Address
Compute Address
Address valid
Write
Data
WR
Read
Data
RD
Memory Access Instruction
5.3
Next Instruction
EEPROM Data Memory
ATtiny48/88 devices contain 64 bytes of data EEPROM memory, organized as a separate data
space in which single bytes can be read and written. The EEPROM has an endurance of at least
100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the
following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the
EEPROM Control Register.
“Memory Programming” on page 184 contains a detailed description on EEPROM Programming
in SPI or Parallel Programming mode.
5.3.1
EEPROM Read/Write Access
The EEPROM Access Registers are located in I/O space.
The write access time for the EEPROM is given in Table 5-2. A self-timing function, however,
lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken. In heavily filtered power
supplies, VCC is likely to rise or fall slowly on power-up/down. This causes the device for some
period of time to run at a voltage lower than specified as minimum for the clock frequency used.
See “Preventing EEPROM Corruption” on page 21 for details on how to avoid problems in these
situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.
Refer to “Atomic Byte Programming” on page 18 and “Split Byte Programming” on page 19 for
details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is
executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next
instruction is executed.
5.3.2
Atomic Byte Programming
The simplest programming method is called Atomic Byte Programming. When writing a byte to
the EEPROM, the user must write the address into register EEAR and data into register EEDR.
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ATtiny48/88
8008C–AVR–03/09
ATtiny48/88
If the EEPMn bits are zero, writing EEPE (within four cycles after EEMPE is written) will trigger
the erase/write operation. Both the erase and write cycle are done in one operation and the total
programming time is given in Figure 5-1 on page 23. The EEPE bit remains set until the erase
and write operations are completed. While the device is busy with programming, it is not possible to do any other EEPROM operations.
5.3.3
Split Byte Programming
It is possible to split the erase/write cycle in two different operations. This may be useful if the
system requires short access time for some limited period of time (typically if the power supply
voltage falls). In order to take advantage of this method, it is required that the locations to be
written have been erased before the write operation.
5.3.4
Erase
To erase a byte, the address must be written to EEAR. If the EEPMn bits are 0b01, writing the
EEPE (within four cycles after EEMPE is written) will trigger the erase operation only (programming time is given in Figure 5-1 on page 23). The EEPE bit remains set until the erase operation
completes. While the device is busy programming, it is not possible to do any other EEPROM
operations.
5.3.5
Write
To write a location, the user must write the address into EEAR and the data into EEDR. If the
EEPMn bits are 0b10, writing the EEPE (within four cycles after EEMPE is written) will trigger
the write operation only (programming time is given in Figure 5-1 on page 23). The EEPE bit
remains set until the write operation completes. If the location to be written has not been erased
before write, the data that is stored must be considered as lost. While the device is busy with
programming, it is not possible to do any other EEPROM operations.
The calibrated oscillator is used to time the EEPROM accesses. Make sure the oscillator frequency is within the requirements described in “OSCCAL – Oscillator Calibration Register” on
page 31.
The following code examples show one assembly and one C function for erase, write, or atomic
write of the EEPROM. The examples assume that interrupts are controlled (e.g., by disabling
interrupts globally) so that no interrupts will occur during execution of these functions.
Assembly Code Example
EEPROM_write:
; Wait for completion of previous write
sbic EECR,EEPE
rjmp EEPROM_write
; Set up address (r17) in address register
out EEARL, r17
; Write data (r19) to Data Register
out EEDR,r19
; Write logical one to EEMPE
sbi EECR,EEMPE
; Start eeprom write by setting EEPE
sbi EECR,EEPE
ret
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8008C–AVR–03/09
C Code Example
void EEPROM_write(unsigned int uiAddress, unsigned char ucData)
{
/* Wait for completion of previous write */
while(EECR & (1<<EEPE))
;
/* Set up address and Data Registers */
EEAR = uiAddress;
EEDR = ucData;
/* Write logical one to EEMPE */
EECR |= (1<<EEMPE);
/* Start eeprom write by setting EEPE */
EECR |= (1<<EEPE);
}
The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of
these functions.
Assembly Code Example
EEPROM_read:
; Wait for completion of previous write
sbic EECR,EEPE
rjmp EEPROM_read
; Set up address (r17) in address register
out EEARL, r17
; Start eeprom read by writing EERE
sbi EECR,EERE
; Read data from Data Register
in
r16,EEDR
ret
C Code Example
unsigned char EEPROM_read(unsigned int uiAddress)
{
/* Wait for completion of previous write */
while(EECR & (1<<EEPE))
;
/* Set up address register */
EEAR = uiAddress;
/* Start eeprom read by writing EERE */
EECR |= (1<<EERE);
/* Return data from Data Register */
return EEDR;
}
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ATtiny48/88
5.3.6
Preventing EEPROM Corruption
During periods of low VCC the EEPROM data can be corrupted because the supply voltage is too
low for the CPU and the EEPROM to operate properly. These issues are the same as for board
level systems using EEPROM, and the same design solutions should be applied.
An EEPROM data corruption can be caused by two situations when the voltage is too low. First,
a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Secondly, the CPU itself can execute instructions incorrectly, if the supply voltage is too low.
EEPROM data corruption can easily be avoided by keeping the RESET active (low) during periods of insufficient power supply voltage. This can be done by enabling the internal Brown-out
Detector (BOD). If the detection level of the internal BOD does not match the needed detection
level, an external low VCC reset Protection circuit can be used. If a reset occurs while a write
operation is in progress, the write operation will be completed provided that the power supply
voltage is sufficient.
5.4
I/O Memory
The I/O space definition of the ATtiny48/88 is shown in “Register Summary” on page 243.
All ATtiny48/88 I/Os and peripherals are placed in the I/O space. All I/O locations may be
accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32
general purpose working registers and the I/O space. I/O Registers within the address range
0x00 – 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the
value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the
instruction set section for more details. When using the I/O specific commands IN and OUT, the
I/O addresses 0x00 – 0x3F must be used. When addressing I/O Registers as data space using
LD and ST instructions, 0x20 must be added to these addresses. The ATtiny48/88 is a complex
microcontroller with more peripheral units than can be supported within the 64 location reserved
in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 – 0xFF in
SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
For compatibility with future devices, reserved bits should be written to zero if accessed.
Reserved I/O memory addresses should never be written.
Some of the Status Flags are cleared by writing a logical one to them. Note that the CBI and SBI
instructions will only operate on the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only.
The I/O and peripherals control registers are explained in later sections.
5.4.1
General Purpose I/O Registers
ATtiny48/88 contains three General Purpose I/O Registers. These registers can be used for
storing any information, and they are particularly useful for storing global variables and Status
Flags. General Purpose I/O Registers within the address range 0x00 – 0x1F are directly bitaccessible using the SBI, CBI, SBIS, and SBIC instructions.
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8008C–AVR–03/09
5.5
5.5.1
Register Description
EEARH and EEARL – EEPROM Address Register
Bit
Read/Write
Initial Value
15
14
13
12
11
10
9
–
–
–
–
–
–
–
8
-
EEARH
-
-
EEAR5
EEAR4
EEAR3
EEAR2
EEAR1
EEAR0
EEARL
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
X
X
X
X
X
X
• Bits 15..6 – Res: Reserved Bits
These bits are reserved and will always read zero.
• Bits 5..0 – EEAR5..0: EEPROM Address
The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the
64/64 bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and
63/63. The initial value of EEAR is undefined. A proper value must be written before the
EEPROM may be accessed.
5.5.2
EEDR – EEPROM Data Register
Bit
7
6
5
4
3
2
1
MSB
0
LSB
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
EEDR
• Bits 7..0 – EEDR7.0: EEPROM Data
For the EEPROM write operation, the EEDR Register contains the data to be written to the
EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the
EEDR contains the data read out from the EEPROM at the address given by EEAR.
5.5.3
EECR – EEPROM Control Register
Bit
7
6
5
4
3
2
1
0
–
–
EEPM1
EEPM0
EERIE
EEMPE
EEPE
EERE
Read/Write
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
X
X
0
0
X
0
EECR
• Bits 7..6 – Res: Reserved Bits
These bits are reserved and will always read zero.
• Bits 5, 4 – EEPM1 and EEPM0: EEPROM Programming Mode Bits
The EEPROM Programming mode bit setting defines which programming action that will be triggered when writing EEPE. It is possible to program data in one atomic operation (erase the old
value and program the new value) or to split the Erase and Write operations in two different
operations. The Programming times for the different modes are shown in Table 5-1. While EEPE
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ATtiny48/88
8008C–AVR–03/09
ATtiny48/88
is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00
unless the EEPROM is busy programming.
Table 5-1.
EEPROM Mode Bits
EEPM1
EEPM0
Programming
Time
0
0
3.4 ms
Erase and Write in one operation (Atomic Operation)
0
1
1.8 ms
Erase Only
1
0
1.8 ms
Write Only
1
1
–
Operation
Reserved for future use
• Bit 3 – EERIE: EEPROM Ready Interrupt Enable
Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing
EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEPE is cleared. The interrupt will not be generated during EEPROM write or SPM.
• Bit 2 – EEMPE: EEPROM Master Write Enable
The EEMPE bit determines whether setting EEPE to one causes the EEPROM to be written.
When EEMPE is set, setting EEPE within four clock cycles will write data to the EEPROM at the
selected address If EEMPE is zero, setting EEPE will have no effect. When EEMPE has been
written to one by software, hardware clears the bit to zero after four clock cycles. See the
description of the EEPE bit for an EEPROM write procedure.
• Bit 1 – EEPE: EEPROM Write Enable
The EEPROM Write Enable Signal EEPE is the write strobe to the EEPROM. When address
and data are correctly set up, the EEPE bit must be written to one to write the value into the
EEPROM. The EEMPE bit must be written to one before a logical one is written to EEPE, otherwise no EEPROM write takes place. The following procedure should be followed when writing
the EEPROM (the order of steps 3 and 4 is not essential):
1. Wait until EEPE becomes zero.
2. Wait until SELFPRGEN in SPMCSR becomes zero.
3. Write new EEPROM address to EEAR (optional).
4. Write new EEPROM data to EEDR (optional).
5. Write a logical one to the EEMPE bit while writing a zero to EEPE in EECR.
6. Within four clock cycles after setting EEMPE, write a logical one to EEPE.
The EEPROM can not be programmed during a CPU write to the Flash memory. The software
must check that the Flash programming is completed before initiating a new EEPROM write. If
the Flash is never being updated by the CPU, step 2 can be omitted.
Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the
EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is
interrupting another EEPROM access, the EEAR or EEDR Register will be modified, causing the
interrupted EEPROM access to fail. It is recommended to have the Global Interrupt Flag cleared
during all the steps to avoid these problems.
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8008C–AVR–03/09
When the write access time has elapsed, the EEPE bit is cleared by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEPE has been set,
the CPU is halted for two cycles before the next instruction is executed.
• Bit 0 – EERE: EEPROM Read Enable
The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct
address is set up in the EEAR Register, the EERE bit must be written to a logic one to trigger the
EEPROM read. The EEPROM read access takes one instruction, and the requested data is
available immediately. When the EEPROM is read, the CPU is halted for four cycles before the
next instruction is executed.
The user should poll the EEPE bit before starting the read operation. If a write operation is in
progress, it is neither possible to read the EEPROM, nor to change the EEAR Register.
The calibrated oscillator is used to time the EEPROM accesses. Table 5-2 lists the typical programming time for EEPROM access from the CPU.
Table 5-2.
EEPROM Programming Time
Symbol
Number of Calibrated Oscillator Cycles
Typ Programming Time
26,368
3.4 ms
EEPROM write
(from CPU)
5.5.4
GPIOR2 – General Purpose I/O Register 2
Bit
7
6
5
4
3
2
1
MSB
0
LSB
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
2
1
GPIOR2
This register may be used freely for storing any kind of data.
5.5.5
GPIOR1 – General Purpose I/O Register 1
Bit
7
6
5
4
3
MSB
0
LSB
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
2
1
GPIOR1
This register may be used freely for storing any kind of data.
5.5.6
GPIOR0 – General Purpose I/O Register 0
Bit
7
6
5
4
3
MSB
0
LSB
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
GPIOR0
This register may be used freely for storing any kind of data.
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ATtiny48/88
6. System Clock and Clock Options
6.1
Clock Systems and their Distribution
Figure 6-1 presents the principal clock systems in the AVR and their distribution. All of the clocks
need not be active at a given time. In order to reduce power consumption, the clocks to modules
not being used can be halted by using different sleep modes, as described in “Power Management and Sleep Modes” on page 33. The clock systems are detailed below.
Figure 6-1.
Clock Distribution
TWI
GENERAL
I/O MODULES
clk I/O
clk TWIHS
CPU
CORE
ADC
clk ADC
RAM
clk CPU
FLASH AND
EEPROM
clk FLASH
CLOCK CONTROL UNIT
CLOCK
PRESCALER
SOURCE CLOCK
RESET
LOGIC
WATCHDOG
CLOCK
WATCHDOG
TIMER
CLOCK
SWITCH
EXTERNAL
CLOCK
WATCHDOG
OSCILLATOR
CALIBRATED
OSCILLATOR
6.1.1
CPU Clock – clkCPU
The CPU clock is routed to parts of the system concerned with operation of the AVR core.
Examples of such modules are the General Purpose Register File, the Status Register and the
data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing
general operations and calculations.
6.1.2
I/O Clock – clkI/O
The I/O clock is used by the majority of the I/O modules such as Timer/Counters, the Serial
Peripheral Interface and the External Interrupt module. Note, that some external interrupts are
detected by asynchronous logic, meaning they are recognized even if the I/O clock is halted.
Also note that the start condition detection of the Two-Wire Interface module is asynchronous,
meaning TWI address recognition works in all sleep modes (even when clkI/O is halted).
6.1.3
Flash Clock – clkFLASH
The Flash clock controls operation of the Flash interface. The Flash clock is usually active simultaneously with the CPU clock.
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8008C–AVR–03/09
6.1.4
Analog to Digital Converter Clock – clkADC
The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks
in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion
results.
6.1.5
High-Speed Two-Wire Interface Clock – clkTWIHS
The TWI clock controls the operation of the Two-Wire Interface module, when operated in highspeed mode. In practice, this clock is identical to the source clock of the device. See “Bit Rate
Generator Unit” on page 130.
6.2
Clock Sources
The device has the following clock source options, selectable by Flash Fuse bits as shown
below. The clock from the selected source is input to the AVR clock generator, and routed to the
appropriate modules.
Table 6-1.
Device Clocking Options(1)
CKSEL1..0
Note:
Device Clocking Option
00
External Clock
01
Reserved
10
Calibrated Internal Oscillator
11
Internal 128 kHz Oscillator
1. For all fuses “1” means unprogrammed while “0” means programmed.
6.2.1
Default Clock Source
The device is shipped with internal oscillator at 8.0 MHz and with the fuse CKDIV8 programmed,
resulting in 1.0 MHz system clock. The startup time is set to maximum and time-out period
enabled (CKSEL = 0b10, SUT = 0b10, CKDIV8 = 0). The default setting ensures that all users
can make their desired clock source setting using any available programming interface.
6.2.2
Clock Startup Sequence
Any clock source needs a sufficient VCC to start oscillating and a minimum number of oscillating
cycles before it can be considered stable.
To ensure sufficient VCC, the device issues an internal reset with a time-out delay (tTOUT) after
the device reset is released by all other reset sources. “System Control and Reset” on page 39
describes the start conditions for the internal reset. The delay (tTOUT) is timed from the Watchdog
oscillator and the number of cycles in the delay is set by the SUTx and CKSELx fuse bits. The
selectable delays are shown in Table 6-2. The frequency of the Watchdog oscillator is voltage
26
ATtiny48/88
8008C–AVR–03/09
ATtiny48/88
and temperature dependent, as shown in “Watchdog Oscillator Frequency vs. VCC” on page
236 and “Watchdog Oscillator Frequency vs. Temperature” on page 237.
Table 6-2.
Length of Startup Sequence.
CKSEL1:0
00
10
11
01
SUT1:0
Number of WDT Cycles
Typical Time-out
00
0
0 ms
01
4K (4,096)
4 ms
10
8K (8,192)
64 ms
11
Reserved
Reserved
XX
Reserved
Reserved
The main purpose of the delay is to keep the AVR in reset until it is supplied with minimum VCC.
The delay will not monitor the actual voltage and it will be required to select a delay longer than
the VCC rise time. If this is not possible, an internal or external Brown-Out Detection circuit
should be used. A BOD circuit will ensure sufficient VCC before it releases the reset, and the
time-out delay can be disabled. Disabling the time-out delay without utilizing a Brown-Out Detection circuit is not recommended.
The oscillator is required to oscillate for a minimum number of cycles before the clock is considered stable. An internal ripple counter monitors the oscillator output clock, and keeps the internal
reset active for a given number of clock cycles. The reset is then released and the device will
start to execute.
The start-up sequence for the clock includes both the time-out delay and the start-up time when
the device starts up from reset. When starting up from Power-down mode, VCC is assumed to be
at a sufficient level and only the start-up time is included.
6.3
Calibrated Internal Oscillator
By default, the Internal Oscillator provides an approximate 8.0 MHz clock. Though voltage and
temperature dependent, this clock can be very accurately calibrated by the user. See Table 21-1
on page 203 for more details. The device is shipped with the CKDIV8 Fuse programmed. See
“System Clock Prescaler” on page 30 for more details.
This clock may be selected as the system clock by programming the CKSEL Fuses as shown in
Table 6-3. If selected, it will operate with no external components. During reset, hardware loads
the pre-programmed calibration value into the OSCCAL Register and thereby automatically calibrates the oscillator. The accuracy of this calibration is shown as Factory calibration in Table 211 on page 203.
By changing the OSCCAL register from SW, see “OSCCAL – Oscillator Calibration Register” on
page 31, it is possible to get a higher calibration accuracy than by using the factory calibration.
The accuracy of this calibration is shown as User calibration in Table 21-1 on page 203.
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8008C–AVR–03/09
When this oscillator is used as the chip clock, the Watchdog oscillator will still be used for the
Watchdog Timer and for the Reset Time-out. For more information on the pre-programmed calibration value, see the section “Calibration Byte” on page 186.
Selecting Internal Calibrated Oscillator Mode(1)(3)
Table 6-3.
Notes:
CKSEL1..0
Frequency Range(2) (MHz)
10
7.3 – 8.1
1. The device is shipped with this option selected.
2. The frequency ranges are preliminary values. Actual values are TBD.
3. If 8 MHz frequency exceeds the specification of the device (depends on VCC), the CKDIV8
Fuse can be programmed in order to divide the internal frequency by 8.
When this oscillator is selected, start-up times are determined by the SUT Fuses as shown in
the table below.
Table 6-4.
SUT1..0
Start-up Times for the Internal Calibrated Oscillator Clock Selection
Power Conditions
Start-up Time
from Power-down
Additional Delay
from Reset (VCC = 5.0V)
00
BOD enabled
6 CK
14CK(1)
01
Fast rising power
6 CK
14CK + 4 ms
10
Slowly rising power
6 CK
14CK + 64 ms(2)
11
Note:
Reserved
1. If the RSTDISBL fuse is programmed, this start-up time will be increased to 14CK + 4 ms to
ensure programming mode can be entered.
2. The device is shipped with this option selected.
6.4
128 kHz Internal Oscillator
The 128 kHz internal oscillator is a low power oscillator providing a clock of 128 kHz. The frequency is nominal at 3V and 25°C. This clock may be select as the system clock by
programming the CKSEL Fuses to “11” as shown in Table 6-5.
Table 6-5.
CKSEL1..0
Nominal Frequency
11
128 kHz
Note:
28
Selecting 128 kHz Internal Oscillator Modes
1. The frequency is preliminary value. Actual value is TBD.
ATtiny48/88
8008C–AVR–03/09
ATtiny48/88
When this clock source is selected, start-up times are determined by the SUT Fuses as shown in
Table 6-6.
Table 6-6.
Start-up Times for the 128 kHz Internal Oscillator
SUT1..0
Power Conditions
Start-up Time
from Power-down
Additional Delay
from Reset
00
BOD enabled
6 CK
14CK(1)
01
Fast rising power
6 CK
14CK + 4 ms
10
Slowly rising power
6 CK
14CK + 64 ms
11
Note:
6.5
Reserved
1. If the RSTDISBL fuse is programmed, this start-up time will be increased to 14CK + 4 ms to
ensure programming mode can be entered.
External Clock
To drive the device from an external clock source, CLKI should be driven as shown in Figure 6-2
on page 29. To run the device on an external clock, the CKSEL Fuses must be programmed to
“00” (see Table 6-7).
Table 6-7.
Selecting External Clock
CKSEL1..0
Frequency
00
0 – 12 MHz
Figure 6-2.
External Clock Drive Configuration
EXTERNAL
CLOCK
SIGNAL
CLKI
GND
When this clock source is selected, start-up times are determined by the SUT Fuses as shown in
Table 6-8.
Table 6-8.
SUT1..0
00
Start-up Times for the External Clock Selection
Power Conditions
BOD enabled
Start-up Time
from Power-down
Additional Delay
from Reset (VCC = 5.0V)
6 CK
14CK
29
8008C–AVR–03/09
Table 6-8.
SUT1..0
Start-up Times for the External Clock Selection
Power Conditions
Start-up Time
from Power-down
Additional Delay
from Reset (VCC = 5.0V)
01
Fast rising power
6 CK
14CK + 4 ms
10
Slowly rising power
6 CK
14CK + 64 ms
11
Reserved
When applying an external clock, it is required to avoid sudden changes in the applied clock frequency to ensure stable operation of the MCU. A variation in frequency of more than 2% from
one clock cycle to the next can lead to unpredictable behavior. If changes of more than 2% is
required, ensure that the MCU is kept in Reset during the changes.
Note that the System Clock Prescaler can be used to implement run-time changes of the internal
clock frequency while still ensuring stable operation. Refer to “System Clock Prescaler” on page
30 for details.
6.6
Clock Output Buffer
The device can output the system clock on the CLKO pin. To enable the output, the CKOUT
Fuse has to be programmed. This mode is suitable when the chip clock is used to drive other circuits on the system. The clock also will be output during reset, and the normal operation of I/O
pin will be overridden when the fuse is programmed. Any clock source, including the internal
oscillator, can be selected when the clock is output on CLKO. If the System Clock Prescaler is
used, it is the divided system clock that is output.
6.7
System Clock Prescaler
The ATtiny48/88 has a system clock prescaler, and the system clock can be divided by setting
the “CLKPR – Clock Prescale Register” on page 31. This feature can be used to decrease the
system clock frequency and the power consumption when the requirement for processing power
is low. This can be used with all clock source options, and it will affect the clock frequency of the
CPU and all synchronous peripherals. clkI/O, clkADC, clkCPU, and clkFLASH are divided by a factor
as shown in Table 6-9 on page 32.
When switching between prescaler settings, the System Clock Prescaler ensures that no
glitches occur in the clock system. It also ensures that no intermediate frequency is higher than
neither the clock frequency corresponding to the previous setting, nor the clock frequency corresponding to the new setting. The ripple counter that implements the prescaler runs at the
frequency of the undivided clock, which may be faster than the CPU's clock frequency. Hence, it
is not possible to determine the state of the prescaler – even if it were readable, and the exact
time it takes to switch from one clock division to the other cannot be exactly predicted. From the
time the CLKPS values are written, it takes between T1 + T2 and T1 + 2 * T2 before the new
clock frequency is active. In this interval, 2 active clock edges are produced. Here, T1 is the previous clock period, and T2 is the period corresponding to the new prescaler setting.
To avoid unintentional changes of clock frequency, a special write procedure must befollowed to
change the CLKPS bits:
1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bitsin
CLKPR to zero.
2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE.
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ATtiny48/88
Interrupts must be disabled when changing prescaler setting to make sure the write procedure is
not interrupted.
6.8
6.8.1
Register Description
OSCCAL – Oscillator Calibration Register
Bit
Read/Write
7
6
5
4
3
2
1
0
CAL7
CAL6
CAL5
CAL4
CAL3
CAL2
CAL1
CAL0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
OSCCAL
Device Specific Calibration Value
The Oscillator Calibration Register is used to trim the internal oscillator to remove process variations from the oscillator frequency. A pre-programmed calibration value is automatically written
to this register during chip reset, giving the factory calibrated frequency as specified in Table 211 on page 203. The application software can write to the OSCCAL register to change the oscillator frequency. The oscillator can be calibrated to frequencies as specified in Table 21-1 on page
203. Calibration outside the given range is not guaranteed.
Note that this oscillator is used to time EEPROM and Flash write accesses, and the write times
will be affected accordingly. If the EEPROM or Flash are written, do not calibrate to more than
8.8 MHz. Otherwise, the EEPROM or Flash write may fail.
All register bits are in use for frequency . A setting of 0x00 gives the lowest frequency and a setting of 0xFF gives the highest frequency.
6.8.2
CLKPR – Clock Prescale Register
Bit
7
6
5
4
3
2
1
0
CLKPCE
–
–
–
CLKPS3
CLKPS2
CLKPS1
CLKPS0
Read/Write
R/W
R
R
R
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
CLKPR
See Bit Description
• Bit 7 – CLKPCE: Clock Prescaler Change Enable
The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE
bit is only updated when the other bits in CLKPR are simultaneously written to zero. CLKPCE is
cleared by hardware four cycles after it is written or when CLKPS bits are written. Rewriting the
CLKPCE bit within this time-out period does neither extend the time-out period, nor clear the
CLKPCE bit.
• Bits 6..4 – Res: Reserved Bits
These bits are reserved and will always read zero.
• Bits 3..0 – CLKPS3..0: Clock Prescaler Select Bits 3 – 0
These bits define the division factor between the selected clock source and the internal system
clock. These bits can be written run-time to vary the clock frequency to suit the application
requirements. As the divider divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used. The division factors are given in
Table 6-9.
The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed,
the CLKPS bits will be reset to 0b0000. If CKDIV8 is programmed, CLKPS bits are reset to
31
8008C–AVR–03/09
0b0011, giving a division factor of 8 at start up. This feature should be used if the selected clock
source has a higher frequency than the maximum frequency of the device at the present operating conditions. Note that any value can be written to the CLKPS bits regardless of the CKDIV8
Fuse setting. The Application software must ensure that a sufficient division factor is chosen if
the selected clock source has a higher frequency than the maximum frequency of the device at
the present operating conditions. The device is shipped with the CKDIV8 Fuse programmed.
Table 6-9.
32
Clock Prescaler Select
CLKPS3
CLKPS2
CLKPS1
CLKPS0
Clock Division Factor
0
0
0
0
1
0
0
0
1
2
0
0
1
0
4
0
0
1
1
8
0
1
0
0
16
0
1
0
1
32
0
1
1
0
64
0
1
1
1
128
1
0
0
0
256
1
0
0
1
Reserved
1
0
1
0
Reserved
1
0
1
1
Reserved
1
1
0
0
Reserved
1
1
0
1
Reserved
1
1
1
0
Reserved
1
1
1
1
Reserved
ATtiny48/88
8008C–AVR–03/09
ATtiny48/88
7. Power Management and Sleep Modes
Sleep modes enable the application to shut down unused modules in the MCU, thereby saving
power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements.
When enabled, the Brown-out Detector (BOD) actively monitors the power supply voltage during
the sleep periods. To further save power, it is possible to disable the BOD in some sleep modes.
See “Software BOD Disable” on page 34 for more details.
7.1
Sleep Modes
Figure 6-1 on page 25 presents the different clock systems in the ATtiny48/88, and their distribution. The figure is helpful in selecting an appropriate sleep mode. Table 7-1 shows the different
sleep modes, their wake up sources and the BOD disable ability.
Table 7-1.
Active Clock Domains and Wake-up Sources in the Different Sleep Modes
ADC Noise Reduction
clkADC
Main Clock
Source Enabled
INT1, INT0 and
Pin Change
TWI Address
Match
EEPROM
Ready
ADC
WDT
Other I/O
Wake-up Source
X
X
X
X
X
X
X
X
X
X
Power-down
Notes:
Oscillator
clkIO
Idle
clkFLASH
Sleep Mode
clkCPU
Active Clock Domain
X
(1)
X
X
X
X
X(1)
X
X
X
1. For INT1 and INT0, only level interrupt
To enter any of the sleep modes, the SE bit in SMCR must be written to logic one and a SLEEP
instruction must be executed. The SM1, and SM0 bits in the SMCR Register select which sleep
mode (Idle, ADC Noise Reduction, or Power-down) will be activated by the SLEEP instruction.
See Table 7-2 on page 36 for a summary.
If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU
is then halted for four cycles in addition to the start-up time, executes the interrupt routine, and
resumes execution from the instruction following SLEEP. The contents of the Register File and
SRAM are unaltered when the device wakes up from sleep. If a reset occurs during sleep mode,
the MCU wakes up and executes from the Reset Vector.
Note that if a level triggered interrupt is used for wake-up the changed level must be held for
some time to wake up the MCU (and for the MCU to enter the interrupt service routine). See
“External Interrupts” on page 48 for details.
7.1.1
Idle Mode
When the SM1..0 bits are written to 00, the SLEEP instruction makes the MCU enter Idle mode,
stopping the CPU but allowing the SPI, Analog Comparator, ADC, 2-wire Serial Interface,
Timer/Counters, Watchdog, and the interrupt system to continue operating. This sleep mode
basically halts clkCPU and clkFLASH, while allowing the other clocks to run.
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8008C–AVR–03/09
Idle mode enables the MCU to wake up from external triggered interrupts as well as internal
ones like the SPI interrupts. If wake-up from the Analog Comparator interrupt is not required, the
Analog Comparator can be powered down by setting the ACD bit in the Analog Comparator
Control and Status Register – ACSR. This will reduce power consumption in Idle mode. If the
ADC is enabled, a conversion starts automatically when this mode is entered.
7.1.2
ADC Noise Reduction Mode
When the SM1..0 bits are written to 01, the SLEEP instruction makes the MCU enter ADC Noise
Reduction mode, stopping the CPU but allowing the ADC, the external interrupts, the 2-wire
Serial Interface address watch and the Watchdog to continue operating (if enabled). This sleep
mode basically halts clkI/O, clkCPU, and clkFLASH, while allowing the other clocks to run.
This improves the noise environment for the ADC, enabling higher resolution measurements. If
the ADC is enabled, a conversion starts automatically when this mode is entered. Apart from the
ADC Conversion Complete interrupt, only an External Reset, a Watchdog System Reset, a
Watchdog Interrupt, a Brown-out Reset, a 2-wire Serial Interface address match, an EEPROM
ready interrupt, an external level interrupt on INT0 or INT1 or a pin change interrupt can wake up
the MCU from ADC Noise Reduction mode.
7.1.3
Power-down Mode
When the SM1..0 bits are written to 10, the SLEEP instruction makes the MCU enter Powerdown mode. In this mode, the external oscillator is stopped, while the external interrupts, the 2wire Serial Interface address watch, and the Watchdog continue operating (if enabled). Only an
External Reset, a Watchdog System Reset, a Watchdog Interrupt, a Brown-out Reset, a 2-wire
Serial Interface address match, an external level interrupt on INT0 or INT1, or a pin change
interrupt can wake up the MCU. This sleep mode basically halts all generated clocks, allowing
operation of asynchronous modules only.
Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed
level must be held for some time to wake up the MCU. Refer to “External Interrupts” on page 48
for details.
When waking up from Power-down mode, there is a delay from the wake-up condition occurs
until the wake-up becomes effective. This allows the clock to restart and become stable after
having been stopped. The wake-up period is defined by the same CKSEL Fuses that define the
Reset Time-out period, as described in “Clock Sources” on page 26.
7.2
Software BOD Disable
When the Brown-out Detector (BOD) is enabled by BODLEVEL fuses (see Table 20-4 on page
185), the BOD is actively monitoring the power supply voltage during a sleep period. To save
power, it is possible for software to disable the BOD in Power-Down Mode. The sleep mode
power consumption will then be at the same level as when BOD is globally disabled by fuses. If
disabled by software, the BOD is turned off immediately after entering the sleep mode and automatically turned on upon wake-up. This ensures safe operation in case the V CC level has
dropped during the sleep period.
When the BOD has been disabled the wake-up time from sleep mode will be the same as the
wake-up time from RESET. This is in order to ensure the BOD is working correctly before the
MCU continues executing code.
BOD disable is controlled by bit 6, BODS (BOD Sleep) in the control register MCUCR, see
“MCUCR – MCU Control Register” on page 37. Writing this bit to one turns off the BOD in
34
ATtiny48/88
8008C–AVR–03/09
ATtiny48/88
Power-Down Mode, while a zero in this bit keeps BOD active. The default setting is zero, i.e.
BOD active.
Writing to the BODS bit is controlled by a timed sequence and an enable bit, see “MCUCR –
MCU Control Register” on page 37.
7.3
Minimizing Power Consumption
There are several issues to consider when trying to minimize the power consumption in an AVR
controlled system. In general, sleep modes should be used as much as possible, and the sleep
mode should be selected so that as few as possible of the device’s functions are operating. All
functions not needed should be disabled. In particular, the following modules may need special
consideration when trying to achieve the lowest possible power consumption.
7.3.1
Analog to Digital Converter
If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be disabled before entering any sleep mode. When the ADC is turned off and on again, the next
conversion will be an extended conversion. Refer to “Analog-to-Digital Converter” on page 158
for details on ADC operation.
7.3.2
Analog Comparator
When entering Idle mode, the Analog Comparator should be disabled if not used. When entering
ADC Noise Reduction mode, the Analog Comparator should be disabled. In other sleep modes,
the Analog Comparator is automatically disabled. However, if the Analog Comparator is set up
to use the Internal Voltage Reference as input, the Analog Comparator should be disabled in all
sleep modes. Otherwise, the Internal Voltage Reference will be enabled, independent of sleep
mode. Refer to “Analog Comparator” on page 155 for details on how to configure the Analog
Comparator.
7.3.3
Brown-out Detector
If the Brown-out Detector is not needed by the application, this module should be turned off. If
the Brown-out Detector is enabled by the BODLEVEL Fuses, it will be enabled in all sleep
modes, and hence, always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption. Refer to “Brown-out Detection” on page 41 for details
on how to configure the Brown-out Detector.
7.3.4
Internal Voltage Reference
The Internal Voltage Reference will be enabled when needed by the Brown-out Detection, the
Analog Comparator or the ADC. If these modules are disabled as described in the sections
above, the internal voltage reference will be disabled and it will not be consuming power. When
turned on again, the user must allow the reference to start up before the output is used. If the
reference is kept on in sleep mode, the output can be used immediately. Refer to “Internal Voltage Reference” on page 42 for details on the start-up time.
7.3.5
Watchdog Timer
If the Watchdog Timer is not needed in the application, the module should be turned off. If the
Watchdog Timer is enabled, it will be enabled in all sleep modes and hence always consume
power. In the deeper sleep modes, this will contribute significantly to the total current consumption. Refer to “Watchdog Timer” on page 42 for details on how to configure the Watchdog Timer.
35
8008C–AVR–03/09
7.3.6
Port Pins
When entering a sleep mode, all port pins should be configured to use minimum power. The
most important is then to ensure that no pins drive resistive loads. In sleep modes where both
the I/O clock (clkI/O) and the ADC clock (clkADC) are stopped, the input buffers of the device will
be disabled. This ensures that no power is consumed by the input logic when not needed. In
some cases, the input logic is needed for detecting wake-up conditions, and it will then be
enabled. Refer to the section “Digital Input Enable and Sleep Modes” on page 60 for details on
which pins are enabled. If the input buffer is enabled and the input signal is left floating or have
an analog signal level close to VCC/2, the input buffer will use excessive power.
For analog input pins, the digital input buffer should be disabled at all times. An analog signal
level close to VCC/2 on an input pin can cause significant current even in active mode. Digital
input buffers can be disabled by writing to the Digital Input Disable Registers (DIDR1 and
DIDR0). Refer to “DIDR1 – Digital Input Disable Register 1” on page 157 and “DIDR0 – Digital
Input Disable Register 0” on page 174 for details.
7.3.7
7.4
7.4.1
On-chip Debug System
If the On-chip debug system is enabled by the DWEN Fuse and the chip enters sleep mode, the
main clock source is enabled and hence always consumes power. In the deeper sleep modes,
this will contribute significantly to the total current consumption.
Register Description
SMCR – Sleep Mode Control Register
The Sleep Mode Control Register contains control bits for power management.
Bit
7
6
5
4
3
2
1
0
–
–
–
–
–
SM1
SM0
SE
Read/Write
R
R
R
R
R
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
SMCR
• Bits 7..3 – Res: Reserved Bits
These bits are reserved and will always read zero.
• Bits 2..1 – SM1..0: Sleep Mode Select Bits 1 and 0
These bits select between the available sleep modes as shown in Table 7-2.
Table 7-2.
Sleep Mode Select
SM1
SM0
Sleep Mode
0
0
Idle
0
1
ADC Noise Reduction
1
0
Power-down
1
1
Reserved
• Bit 0 – SE: Sleep Enable
The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP
instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmer’s
purpose, it is recommended to write the Sleep Enable (SE) bit to one just before the execution of
the SLEEP instruction and to clear it immediately after waking up.
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ATtiny48/88
8008C–AVR–03/09
ATtiny48/88
7.4.2
MCUCR – MCU Control Register
Bit
7
6
5
4
3
2
1
0
–
BODS
BODSE
PUD
–
–
–
–
Read/Write
R
R/W
R/W
R/W
R
R
R
R
Initial Value
0
0
0
0
0
0
0
0
MCUCR
• Bits 7, 3..0 – Res: Reserved Bits
These bits are reserved and will always read zero.
• Bit 6 – BODS: BOD Sleep
The BODS bit must be written to logic one in order to turn off BOD during sleep, see Table 7-2
on page 36. Writing to the BODS bit is controlled by a timed sequence and an enable bit,
BODSE in MCUCR. To disable BOD in relevant sleep modes, both BODS and BODSE must first
be set to one. Then, to set the BODS bit, BODS must be set to one and BODSE must be set to
zero within four clock cycles.
The BODS bit is active three clock cycles after it is set. A sleep instruction must be executed
while BODS is active in order to turn off the BOD for the actual sleep mode. The BODS bit is
automatically cleared after three clock cycles.
• Bit 5 – BODSE: BOD Sleep Enable
BODSE enables setting of BODS control bit, as explained in BODS bit description. BOD disable
is controlled by a timed sequence.
7.4.3
PRR – Power Reduction Register
The Power Reduction Register (PRR) provides a method to stop the clock to individual peripherals to reduce power consumption. The current state of the peripheral is frozen and the I/O
registers can not be read or written. Resources used by the peripheral when stopping the clock
will remain occupied, hence the peripheral should in most cases be disabled before stopping the
clock. Waking up a module, which is done by clearing the bit in PRR, puts the module in the
same state as before shutdown.
Module shutdown can be used in Idle mode and Active mode to significantly reduce the overall
power consumption. In all other sleep modes, the clock is already stopped.
Bit
7
6
5
4
3
2
1
0
PRTWI
–
PRTIM0
–
PRTIM1
PRSPI
–
PRADC
Read/Write
R/W
R
R/W
R
R/W
R/W
R
R/W
Initial Value
0
0
0
0
0
0
0
0
PRR
• Bit 7 – PRTWI: Power Reduction TWI
Writing a logic one to this bit shuts down the TWI by stopping the clock to the module. When
waking up the TWI again, the TWI should be re initialized to ensure proper operation.
• Bits 6, 4, 1 – Res: Reserved
These bits are reserved and will always read zero.
• Bit 5 – PRTIM0: Power Reduction Timer/Counter0
Writing a logic one to this bit shuts down the Timer/Counter0 module. When the Timer/Counter0
is enabled, operation will continue like before the shutdown.
37
8008C–AVR–03/09
• Bit 3 – PRTIM1: Power Reduction Timer/Counter1
Writing a logic one to this bit shuts down the Timer/Counter1 module. When the Timer/Counter1
is enabled, operation will continue like before the shutdown.
• Bit 2 – PRSPI: Power Reduction Serial Peripheral Interface
If using debugWIRE On-chip Debug System, this bit should not be written to one.
Writing a logic one to this bit shuts down the Serial Peripheral Interface by stopping the clock to
the module. When waking up the SPI again, the SPI should be re initialized to ensure proper
operation.
• Bit 0 – PRADC: Power Reduction ADC
Writing a logic one to this bit shuts down the ADC. The ADC must be disabled before shut down.
The analog comparator cannot be used when the ADC is shut down.
38
ATtiny48/88
8008C–AVR–03/09
ATtiny48/88
8. System Control and Reset
8.1
Resetting the AVR
During reset, all I/O Registers are set to their initial values, and the program starts execution
from the Reset Vector. The instruction placed at the Reset Vector must be an RJMP – Relative
Jump – instruction to the reset handling routine. If the program never enables an interrupt
source, the Interrupt Vectors are not used, and regular program code can be placed at these
locations. The circuit diagram in Figure 8-1 shows the reset circuit. Table 21-3 on page 204
shows the electrical parameters of the reset circuitry.
Figure 8-1.
Reset Logic
DATA BUS
PORF
BORF
EXTRF
WDRF
MCU Status
Register (MCUSR)
Power-on Reset
Circuit
Brown-out
Reset Circuit
BODLEVEL [2..0]
Pull-up Resistor
SPIKE
FILTER
Watchdog
Oscillator
Clock
Generator
CK
Delay Counters
TIMEOUT
CKSEL[1:0]
SUT[1:0]
The I/O ports of the AVR are immediately reset to their initial state when a reset source goes
active. This does not require any clock source to be running.
After all reset sources have gone inactive, a delay counter is invoked, stretching the internal
reset. This allows the power to reach a stable level before normal operation starts. The time-out
period of the delay counter is defined by the user through the SUT and CKSEL Fuses. The different selections for the delay period are presented in “Clock Sources” on page 26.
39
8008C–AVR–03/09
8.2
Reset Sources
The ATtiny48/88 has four sources of reset:
• Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset
threshold (VPOT), or when the supply voltage falls rapidly.
• External Reset. The MCU is reset when a low level is present on the RESET pin for longer
than the required pulse length.
• Watchdog System Reset. The MCU is reset when the Watchdog Timer period expires and
the Watchdog System Reset mode is enabled.
• Brown-out Reset. The MCU is reset when the supply voltage VCC is below the Brown-out
Reset threshold (VBOT) and the Brown-out Detector is enabled.
8.2.1
Power-on Reset
A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level
is defined in Table 21-3 on page 204. The POR is activated whenever VCC is below the detection
level. The POR circuit can be used to trigger the start-up Reset, as well as to detect a failure in
supply voltage.
A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the
Power-on Reset threshold voltage invokes the delay counter, which determines how long the
device is kept in RESET after VCC rise. The RESET signal is activated again, without any delay,
when VCC decreases below the detection level.
Figure 8-2.
VCC
RESET
MCU Start-up, RESET Tied to VCC
VPOT
VRST
tTOUT
TIME-OUT
INTERNAL
RESET
Figure 8-3.
VCC
RESET
TIME-OUT
MCU Start-up, RESET Extended Externally
VPOT
VRST
tTOUT
INTERNAL
RESET
40
ATtiny48/88
8008C–AVR–03/09
ATtiny48/88
8.2.2
External Reset
An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the
minimum pulse width (see Table 21-3 on page 204) will generate a reset, even if the clock is not
running. Shorter pulses are not guaranteed to generate a reset. When the applied signal
reaches the Reset Threshold Voltage – VRST – on its positive edge, the delay counter starts the
MCU after the Time-out period – tTOUT – has expired. The External Reset can be disabled by the
RSTDISBL fuse, see Table 20-4 on page 185.
Figure 8-4.
External Reset During Operation
CC
8.2.3
Brown-out Detection
ATtiny48/88 has an On-chip Brown-out Detection (BOD) circuit for monitoring the VCC level during operation by comparing it to a fixed trigger level. The trigger level for the BOD can be
selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free
Brown-out Detection. The hysteresis on the detection level should be interpreted as VBOT+ =
VBOT + VHYST/2 and VBOT- = VBOT - VHYST/2. When the BOD is enabled, and VCC decreases to a
value below the trigger level (VBOT- in Figure 8-5), the Brown-out Reset is immediately activated.
When VCC increases above the trigger level (VBOT+ in Figure 8-5), the delay counter starts the
MCU after the Time-out period tTOUT has expired.
The BOD circuit will only detect a drop in VCC if the voltage stays below the trigger level for longer than tBOD given in “System and Reset Characterizations” on page 204.
Figure 8-5.
Brown-out Reset During Operation
VCC
VBOT-
VBOT+
RESET
TIME-OUT
tTOUT
INTERNAL
RESET
41
8008C–AVR–03/09
8.2.4
Watchdog Reset
When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On
the falling edge of this pulse, the delay timer starts counting the Time-out period tTOUT. Refer to
page 42 for details on operation of the Watchdog Timer.
Figure 8-6.
Watchdog System Reset During Operation
CC
CK
8.3
Internal Voltage Reference
ATtiny48/88 features an internal bandgap reference. This reference is used for Brown-out
Detection, and it can be used as an input to the Analog Comparator or the ADC.
8.3.1
Voltage Reference Enable Signals and Start-up Time
The voltage reference has a start-up time that may influence the way it should be used. The
start-up time is given in “System and Reset Characterizations” on page 204. To save power, the
reference is not always turned on. The reference is on during the following situations:
1. When the BOD is enabled (by programming the BODLEVEL [2:0] Fuses).
2. When the internal reference is connected to the Analog Comparator (by setting the
ACBG bit in ACSR).
3. When the ADC is enabled.
Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, the user
must always allow the reference to start up before the output from the Analog Comparator or
ADC is used. To reduce power consumption in Power-down mode, the user can avoid the three
conditions above to ensure that the reference is turned off before entering Power-down mode.
8.4
Watchdog Timer
The Watchdog Timer is clocked from an on-chip oscillator which runs at 128 kHz. By controlling
the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted as shown in Table
8-3 on page 45. The WDR – Watchdog Reset – instruction resets the Watchdog Timer. The
Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs. Ten different
clock cycle periods can be selected to determine the reset period. If the reset period expires
without another Watchdog Reset, the ATtiny48/88 resets and executes from the Reset Vector.
For timing details on the Watchdog Reset, refer to Table 8-3 on page 45.
The Wathdog Timer can also be configured to generate an interrupt instead of a reset. This can
be very helpful when using the Watchdog to wake-up from Power-down.
42
ATtiny48/88
8008C–AVR–03/09
ATtiny48/88
To prevent unintentional disabling of the Watchdog or unintentional change of time-out period,
two different safety levels are selected by the fuse WDTON as shown in Table 8-1. See “Timed
Sequences for Changing the Configuration of the Watchdog Timer” on page 43 for details.
Table 8-1.
WDT Configuration as a Function of the WDTON Fuse Setting
WDTON
Safety Level
WDT Initial State
Disable WDT
Change Time-out
Unprogrammed
1
Disabled
Timed sequence
No limitations
Programmed
2
Enabled
Always enabled
Timed sequence
Watchdog Timer
128kHz
OSCILLATOR
WATCHDOG
RESET
WDE
OSC/2K
OSC/4K
OSC/8K
OSC/16K
OSC/32K
OSC/64K
OSC/128K
OSC/256K
OSC/512K
OSC/1024K
Figure 8-7.
WDP0
WDP1
WDP2
WDP3
MCU RESET
WDIF
WDIE
INTERRUPT
8.4.1
Timed Sequences for Changing the Configuration of the Watchdog Timer
The sequence for changing configuration differs slightly between the two safety levels. Separate
procedures are described for each level.
8.4.2
Safety Level 1
In this mode, the Watchdog Timer is initially disabled, but can be enabled by writing the WDE bit
to one without any restriction. A timed sequence is needed when disabling an enabled Watchdog Timer. To disable an enabled Watchdog Timer, the following procedure must be followed:
1. In the same operation, write a logic one to WDCE and WDE. A logic one must be written to WDE regardless of the previous value of the WDE bit.
2. Within the next four clock cycles, in the same operation, write the WDE and WDP bits
as desired, but with the WDCE bit cleared.
8.4.3
Safety Level 2
In this mode, the Watchdog Timer is always enabled, and the WDE bit will always read as one. A
timed sequence is needed when changing the Watchdog Time-out period. To change the
Watchdog Time-out, the following procedure must be followed:
1. In the same operation, write a logical one to WDCE and WDE. Even though the WDE
always is set, the WDE must be written to one to start the timed sequence.
2. Within the next four clock cycles, in the same operation, write the WDP bits as desired,
but with the WDCE bit cleare d. The value written to the WDE bit is irrelevant.
43
8008C–AVR–03/09
8.5
8.5.1
Register Description
MCUSR – MCU Status Register
The MCU Status Register provides information on which reset source caused an MCU reset.
Bit
7
6
5
4
3
2
1
0
–
–
–
–
WDRF
BORF
EXTRF
PORF
Read/Write
R
R
R
R
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
MCUSR
See Bit Description
• Bit 7..4 – Res: Reserved Bits
These bits are reserved and will always read zero.
• Bit 3 – WDRF: Watchdog System Reset Flag
This bit is set if a Watchdog System Reset occurs. The bit is reset by a Power-on Reset, or by
writing a logic zero to the flag.
• Bit 2 – BORF: Brown-out Reset Flag
This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a
logic zero to the flag.
• Bit 1 – EXTRF: External Reset Flag
This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a
logic zero to the flag.
• Bit 0 – PORF: Power-on Reset Flag
This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag.
To make use of the Reset Flags to identify a reset condition, the user should read and then
Reset the MCUSR as early as possible in the program. If the register is cleared before another
reset occurs, the source of the reset can be found by examining the Reset Flags.
8.5.2
WDTCSR – Watchdog Timer Control Register
Bit
7
6
5
4
3
2
1
0
WDIF
WDIE
WDP3
WDCE
WDE
WDP2
WDP1
WDP0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
X
0
0
0
WDTCSR
• Bit 7 – WDIF: Watchdog Interrupt Flag
This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is configured for interrupt. WDIF is cleared by hardware when executing the corresponding interrupt
handling vector. Alternatively, WDIF is cleared by writing a logic one to the flag. When the I-bit in
SREG and WDIE are set, the Watchdog Time-out Interrupt is executed.
• Bit 6 – WDIE: Watchdog Interrupt Enable
When this bit is written to one and the I-bit in the Status Register is set, the Watchdog Interrupt is
enabled. If WDE is cleared in combination with this setting, the Watchdog Timer is in Interrupt
Mode, and the corresponding interrupt is executed if time-out in the Watchdog Timer occurs.
If WDE is set, the Watchdog Timer is in Interrupt and System Reset Mode. The first time-out in
the Watchdog Timer will set WDIF. Executing the corresponding interrupt vector will clear WDIE
and WDIF automatically by hardware (the Watchdog goes to System Reset Mode). This is use44
ATtiny48/88
8008C–AVR–03/09
ATtiny48/88
ful for keeping the Watchdog Timer security while using the interrupt. To stay in Interrupt and
System Reset Mode, WDIE must be set after each interrupt. This should however not be done
within the interrupt service routine itself, as this might compromise the safety-function of the
Watchdog System Reset mode. If the interrupt is not executed before the next time-out, a System Reset will be applied.
Table 8-2.
Watchdog Timer Configuration
WDTON
WDE
WDIE
Mode
Action on Time-out
0
0
0
Stopped
None
0
0
1
Interrupt Mode
Interrupt
0
1
0
System Reset Mode
Reset
0
1
1
Interrupt & System Reset Mode
Interrupt, then go to
System Reset Mode
1
X
X
System Reset Mode
Reset
• Bit 4 – WDCE: Watchdog Change Enable
This bit is used in timed sequences for changing WDE and prescaler bits. To clear the WDE bit,
and/or change the prescaler bits, WDCE must be set.
Once written to one, hardware will clear WDCE after four clock cycles.
• Bit 3 – WDE: Watchdog System Reset Enable
WDE is overridden by WDRF in MCUSR. This means that WDE is always set when WDRF is
set. To clear WDE, WDRF must be cleared first. This feature ensures multiple resets during conditions causing failure, and a safe start-up after the failure.
• Bits 5, 2..0 – WDP3..0: Watchdog Timer Prescaler Bits 3, 2, 1 and 0
The WDP3..0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is running. The different prescaling values and their corresponding time-out periods are shown in
Table 8-3 on page 45.
Table 8-3.
Watchdog Timer Prescale Select
WDP3
WDP2
WDP1
WDP0
Number of
WDT Oscillator Cycles
Typical Time-out at
VCC = 5.0V
0
0
0
0
2K (2048) cycles
16 ms
0
0
0
1
4K (4096) cycles
32 ms
0
0
1
0
8K (8192) cycles
64 ms
0
0
1
1
16K (16384) cycles
0.125 s
0
1
0
0
32K (32768) cycles
0.25 s
0
1
0
1
64K (65536) cycles
0.5 s
0
1
1
0
128K (131072) cycles
1.0 s
0
1
1
1
256K (262144) cycles
2.0 s
1
0
0
0
512K (524288) cycles
4.0 s
1
0
0
1
1024K (1048576) cycles
8.0 s
45
8008C–AVR–03/09
Table 8-3.
WDP3
WDP2
WDP1
WDP0
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
Notes:
46
Watchdog Timer Prescale Select
Number of
WDT Oscillator Cycles
Typical Time-out at
VCC = 5.0V
Reserved (1)
1. If selected, one of the valid settings below 0b1010 will be used.
ATtiny48/88
8008C–AVR–03/09
ATtiny48/88
9. Interrupts
This section describes the specifics of interrupt handling in ATtiny48/88. For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling” on page 13.
9.1
Interrupt Vectors
Table 9-1.
Reset and Interrupt Vectors in ATtiny48/88
Vector
No.
Program
Address
Source
Interrupt Definition
1
0x000
RESET
External/Power-on/Brown-out/Watchdog Reset
2
0x001
INT0
External Interrupt Request 0
3
0x002
INT1
External Interrupt Request 1
4
0x003
PCINT0
Pin Change Interrupt Request 0
5
0x004
PCINT1
Pin Change Interrupt Request 1
6
0x005
PCINT2
Pin Change Interrupt Request 2
7
0x006
PCINT3
Pin Change Interrupt Request 3
8
0x007
WDT
Watchdog Time-out Interrupt
9
0x008
TIMER1_CAPT
Timer/Counter1 Capture Event
10
0x009
TIMER1_COMPA
Timer/Counter1 Compare Match A
11
0x00A
TIMER1_COMPB
Timer/Counter1 Compare Match B
12
0x00B
TIMER1_OVF
Timer/Counter1 Overflow
13
0x00C
TIMER0_COMPA
Timer/Counter0 Compare Match A
14
0x00D
TIMER0_COMPB
Timer/Counter0 Compare Match B
15
0x00E
TIMER0_OVF
Timer/Counter0 Overflow
16
0x00F
SPI_STC
SPI Serial Transfer Complete
17
0x010
ADC
ADC Conversion Complete
18
0x011
EE_RDY
EEPROM Ready
19
0x012
ANA_COMP
Analog Comparator
20
0x013
TWI
2-wire Serial Interface
The most typical and general program setup for the Reset and Interrupt Vector Addresses in
ATtiny48/88 is:
Address Labels Code
Comments
0x000
rjmp
RESET
; Reset Handler
0x001
rjmp
INT0
; IRQ0 Handler
0x002
rjmp
INT1
; IRQ1 Handler
0x003
rjmp
PCINT0
; PCINT0 Handler
0x004
rjmp
PCINT1
; PCINT1 Handler
0x005
rjmp
PCINT2
; PCINT2 Handler
0x006
rjmp
PCINT3
; PCINT3 Handler
0x007
rjmp
WDT
; Watchdog Timer Handler
47
8008C–AVR–03/09
0x008
rjmp
TIMER1_CAPT
; Timer1 Capture Handler
0x009
rjmp
TIMER1_COMPA
; Timer1 Compare A Handler
0x00A
rjmp
TIMER1_COMPB
; Timer1 Compare B Handler
0x00B
rjmp
TIMER1_OVF
; Timer1 Overflow Handler
0x00C
rjmp
TIMER0_COMPA
; Timer0 Compare A Handler
0x00D
rjmp
TIMER0_COMPB
; Timer0 Compare B Handler
0x00E
rjmp
TIMER0_OVF
; Timer0 Overflow Handler
0x00F
rjmp
SPI_STC
; SPI Transfer Complete Handler
0x010
rjmp
ADC
; ADC Conversion Complete Handler
0x011
rjmp
EE_RDY
; EEPROM Ready Handler
0x012
rjmp
ANA_COMP
; Analog Comparator Handler
rjmp
TWI
; 2-wire Serial Interface Handler;
ldi
r16, high(RAMEND); Main program start
0x015
out
SPH,r16
0x016
ldi
r16, low(RAMEND)
0x017
out
SPL,r16
0x018
sei
0x013
0x014
RESET:
0x019
; Enable interrupts
<inst> xxx
...
9.2
; Set Stack Pointer to top of RAM
...
...
...
External Interrupts
The External Interrupts are triggered by the INT0 and INT1 pins or any of the PCINT27..0 pins.
Observe that, if enabled, the interrupts will trigger even if the INT0 and INT1 or PCINT27..0 pins
are configured as outputs. This feature provides a way of generating a software interrupt, as
follows.
• Pin Change Interrupt PCI3 triggers if a pin in PCINT27..24 is toggled while enabled
• Pin Change Interrupt PCI2 triggers if a pin in PCINT23..16 is toggled while enabled
• Pin Change Interrupt PCI1 triggers if a pin in PCINT15..8 is toggled while enabled
• Pin Change Interrupt PCI0 triggers if a pin in PCINT7..0 is toggled while enabled
The PCMSK3, PCMSK2, PCMSK1 and PCMSK0 registers control which pins contribute to the
pin change interrupts. Pin change interrupts on PCINT27..0 are detected asynchronously. This
means that these interrupts can be used for waking the part also from sleep modes other than
Idle mode.
The INT0 and INT1 interrupts can be triggered by a falling or rising edge, or a low level. This is
configured as described in “EICRA – External Interrupt Control Register A” on page 50. When
INT0 or INT1 interrupts are enabled and are configured as level triggered, the interrupts will trigger as long as the corresponding pin is held low. Note that recognition of falling or rising edge
interrupts on INT0 or INT1 requires the presence of an I/O clock, described in “Clock Systems
and their Distribution” on page 25.
9.2.1
48
Low Level Interrupt
Low level interrupts on INT0 and INT1 are detected asynchronously. This means that the interrupt sources can be used for waking the part also from sleep modes other than Idle (the I/O
clock is halted in all sleep modes except Idle mode).
ATtiny48/88
8008C–AVR–03/09
ATtiny48/88
Note that if a level triggered interrupt is used for wake-up from Power-down, the required level
must be held long enough for the MCU to complete the wake-up to trigger the level interrupt. If
the level disappears before the end of the Start-up Time, the MCU will still wake up, but no interrupt will be generated. The start-up time is defined by the SUT and CKSEL Fuses as described
in “System Clock and Clock Options” on page 25.
If the low level on the interrupt pin is removed before the device has woken up then program
execution will not be diverted to the interrupt service routine but continue from the instruction following the SLEEP command.
9.2.2
Pin Change Interrupt Timing
An example of timing of a pin change interrupt is shown in Figure 9-1.
Figure 9-1.
Timing of pin change interrupts
pin_lat
PCINT(0)
LE
clk
D
pcint_in_(0)
Q
pin_sync
PCINT(0) in PCMSK(x)
0
pcint_syn
pcint_setflag
PCIF
x
clk
clk
PCINT(0)
pin_lat
pin_sync
pcint_in_(0)
pcint_syn
pcint_setflag
PCIF
49
8008C–AVR–03/09
9.3
9.3.1
Register Description
EICRA – External Interrupt Control Register A
The External Interrupt Control Register A contains control bits for interrupt sense control.
Bit
7
6
5
4
3
2
1
0
–
–
–
–
ISC11
ISC10
ISC01
ISC00
Read/Write
R
R
R
R
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
EICRA
• Bits 7..4 – Res: Reserved Bits
These bits are reserved and will always read zero.
• Bits 3, 2 – ISC11, ISC10: Interrupt Sense Control 1 Bit 1 and Bit 0
The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corresponding interrupt mask are set. The level and edges on the external INT1 pin that activate the
interrupt are defined in Table 9-2. The value on the INT1 pin is sampled before detecting edges.
If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate
an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is
selected, the low level must be held until the completion of the currently executing instruction to
generate an interrupt.
Table 9-2.
Interrupt 1 Sense Control
ISC11
ISC10
Description
0
0
The low level of INT1 generates an interrupt request.
0
1
Any logical change on INT1 generates an interrupt request.
1
0
The falling edge of INT1 generates an interrupt request.
1
1
The rising edge of INT1 generates an interrupt request.
• Bits 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask are set. The level and edges on the external INT0 pin that activate the
interrupt are defined in Table 9-3. The value on the INT0 pin is sampled before detecting edges.
If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate
an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is
selected, the low level must be held until the completion of the currently executing instruction to
generate an interrupt.
Table 9-3.
50
Interrupt 0 Sense Control
ISC01
ISC00
Description
0
0
The low level of INT0 generates an interrupt request.
0
1
Any logical change on INT0 generates an interrupt request.
1
0
The falling edge of INT0 generates an interrupt request.
1
1
The rising edge of INT0 generates an interrupt request.
ATtiny48/88
8008C–AVR–03/09
ATtiny48/88
9.3.2
EIMSK – External Interrupt Mask Register
Bit
7
6
5
4
3
2
1
0
–
–
–
–
–
–
INT1
INT0
Read/Write
R
R
R
R
R
R
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
EIMSK
• Bits 7..2 – Res: Reserved Bits
These bits are unused in ATtiny48/88, and will always read as zero.
• Bit 1 – INT1: External Interrupt Request 1 Enable
When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control bits (ISC11 and ISC10) in the External
Interrupt Control Register A (EICRA) define whether the external interrupt is activated on rising
and/or falling edge of the INT1 pin or level sensed. Activity on the pin will cause an interrupt
request even if INT1 is configured as an output. The corresponding interrupt of External Interrupt
Request 1 is executed from the INT1 Interrupt Vector.
• Bit 0 – INT0: External Interrupt Request 0 Enable
When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is enabled. The Interrupt Sense Control bits (ISC01 and ISC00) in the External
Interrupt Control Register A (EICRA) define whether the external interrupt is activated on rising
and/or falling edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt
request even if INT0 is configured as an output. The corresponding interrupt of External Interrupt
Request 0 is executed from the INT0 Interrupt Vector.
9.3.3
EIFR – External Interrupt Flag Register
Bit
7
6
5
4
3
2
1
0
–
–
–
–
–
–
INTF1
INTF0
Read/Write
R
R
R
R
R
R
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
EIFR
• Bit 7..2 – Res: Reserved Bits
These bits are reserved and will always read zero.
• Bit 1 – INTF1: External Interrupt Flag 1
When an edge or logic change on the INT1 pin triggers an interrupt request, INTF1 becomes set
(one). If the I-bit in SREG and the INT1 bit in EIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed.
Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared
when INT1 is configured as a level interrupt.
• Bit 0 – INTF0: External Interrupt Flag 0
When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set
(one). If the I-bit in SREG and the INT0 bit in EIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed.
Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared
when INT0 is configured as a level interrupt.
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9.3.4
PCICR – Pin Change Interrupt Control Register
Bit
7
6
5
4
3
2
1
0
–
–
–
–
PCIE3
PCIE2
PCIE1
PCIE0
Read/Write
R
R
R
R
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
PCICR
• Bit 7..4 – Res: Reserved Bits
These bits are reserved and will always read zero.
• Bit 3 – PCIE3: Pin Change Interrupt Enable 3
When the PCIE3 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin
change interrupt 3 is enabled. Any change on any enabled PCINT27..24 pin will cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI3
Interrupt Vector. PCINT27..24 pins are enabled individually by the PCMSK3 Register.
• Bit 2 – PCIE2: Pin Change Interrupt Enable 2
When the PCIE2 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin
change interrupt 2 is enabled. Any change on any enabled PCINT23..16 pin will cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI2
Interrupt Vector. PCINT23..16 pins are enabled individually by the PCMSK2 Register.
• Bit 1 – PCIE1: Pin Change Interrupt Enable 1
When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin
change interrupt 1 is enabled. Any change on any enabled PCINT15..8 pin will cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI1
Interrupt Vector. PCINT15..8 pins are enabled individually by the PCMSK1 Register.
• Bit 0 – PCIE0: Pin Change Interrupt Enable 0
When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin
change interrupt 0 is enabled. Any change on any enabled PCINT7..0 pin will cause an interrupt.
The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI0 Interrupt Vector. PCINT7..0 pins are enabled individually by the PCMSK0 Register.
9.3.5
PCIFR – Pin Change Interrupt Flag Register
Bit
7
6
5
4
3
2
1
0
–
–
–
–
PCIF3
PCIF2
PCIF1
PCIF0
Read/Write
R
R
R
R
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
PCIFR
• Bit 7..4 – Res: Reserved Bits
These bits are reserved and will always read zero.
• Bit 3 – PCIF3: Pin Change Interrupt Flag 3
When a logic change on any PCINT27..24 pin triggers an interrupt request, PCIF3 becomes set
(one). If the I-bit in SREG and the PCIE3 bit in PCICR are set (one), the MCU will jump to the
corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.
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• Bit 2 – PCIF2: Pin Change Interrupt Flag 2
When a logic change on any PCINT23..16 pin triggers an interrupt request, PCIF2 becomes set
(one). If the I-bit in SREG and the PCIE2 bit in PCICR are set (one), the MCU will jump to the
corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.
• Bit 1 – PCIF1: Pin Change Interrupt Flag 1
When a logic change on any PCINT15..8 pin triggers an interrupt request, PCIF1 becomes set
(one). If the I-bit in SREG and the PCIE1 bit in PCICR are set (one), the MCU will jump to the
corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.
• Bit 0 – PCIF0: Pin Change Interrupt Flag 0
When a logic change on any PCINT7..0 pin triggers an interrupt request, PCIF0 becomes set
(one). If the I-bit in SREG and the PCIE0 bit in PCICR are set (one), the MCU will jump to the
corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.
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9.3.6
PCMSK3 – Pin Change Mask Register 3
Bit
7
6
5
4
3
2
1
0
-
-
-
-
PCINT27
PCINT26
PCINT25
PCINT24
Read/Write
R
R
R
R
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
PCMSK3
• Bit 7..4 – Res: Reserved Bits
These bits are reserved and will always read zero.
• Bit 3..0 – PCINT27..24: Pin Change Enable Mask 27..24
Each PCINT27..24-bit selects whether pin change interrupt is enabled on the corresponding I/O
pin. If PCINT27..24 is set and the PCIE3 bit in PCICR is set, pin change interrupt is enabled on
the corresponding I/O pin. If PCINT27..24 is cleared, pin change interrupt on the corresponding
I/O pin is disabled.
9.3.7
PCMSK2 – Pin Change Mask Register 2
Bit
7
6
5
4
3
2
1
0
PCINT23
PCINT22
PCINT21
PCINT20
PCINT19
PCINT18
PCINT17
PCINT16
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
PCMSK2
• Bit 7..0 – PCINT23..16: Pin Change Enable Mask 23..16
Each PCINT23..16-bit selects whether pin change interrupt is enabled on the corresponding I/O
pin. If PCINT23..16 is set and the PCIE2 bit in PCICR is set, pin change interrupt is enabled on
the corresponding I/O pin. If PCINT23..16 is cleared, pin change interrupt on the corresponding
I/O pin is disabled.
9.3.8
PCMSK1 – Pin Change Mask Register 1
Bit
7
6
5
4
3
2
1
0
PCINT15
PCINT14
PCINT13
PCINT12
PCINT11
PCINT10
PCINT9
PCINT8
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
PCMSK1
• Bit 7..0 – PCINT15..8: Pin Change Enable Mask 15..8
Each PCINT15..8-bit selects whether pin change interrupt is enabled on the corresponding I/O
pin. If PCINT15..8 is set and the PCIE1 bit in PCICR is set, pin change interrupt is enabled on
the corresponding I/O pin. If PCINT15..8 is cleared, pin change interrupt on the corresponding
I/O pin is disabled.
9.3.9
PCMSK0 – Pin Change Mask Register 0
Bit
7
6
5
4
3
2
1
0
PCINT7
PCINT6
PCINT5
PCINT4
PCINT3
PCINT2
PCINT1
PCINT0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
PCMSK0
• Bit 7..0 – PCINT7..0: Pin Change Enable Mask 7..0
Each PCINT7..0 bit selects whether pin change interrupt is enabled on the corresponding I/O
pin. If PCINT7..0 is set and the PCIE0 bit in PCICR is set, pin change interrupt is enabled on the
corresponding I/O pin. If PCINT7..0 is cleared, pin change interrupt on the corresponding I/O pin
is disabled.
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10. I/O-Ports
10.1
Introduction
All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports.
This means that the direction of one port pin can be changed without unintentionally changing
the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as
input). The pin driver is strong enough to drive LED displays directly. All port pins have individually selectable pull-up resistors with a supply-voltage invariant resistance. All I/O pins have
protection diodes to both VCC and Ground as indicated in Figure 10-1. Refer to “Electrical Characteristics” on page 201 for a complete list of parameters.
Figure 10-1. I/O Pin Equivalent Schematic
Rpu
Pxn
Logic
See Figure
"General Digital I/O" for
Details
All registers and bit references in this section are written in general form. A lower case “x” represents the numbering letter for the port, and a lower case “n” represents the bit number. However,
when using the register or bit defines in a program, the precise form must be used. For example,
PORTB3 for bit no. 3 in Port B, here documented generally as PORTxn. The physical I/O Registers and bit locations are listed in “Register Description” on page 72.
Three I/O memory address locations are allocated for each port, one each for the Data Register
– PORTx, Data Direction Register – DDRx, and the Port Input Pins – PINx. The Port Input Pins
I/O location is read only, while the Data Register and the Data Direction Register are read/write.
However, writing a logic one to a bit in the PINx Register, will result in a toggle in the corresponding bit in the Data Register. In addition, the Pull-up Disable – PUD bit in MCUCR disables the
pull-up function for all pins in all ports when set.
Using the I/O port as General Digital I/O is described in “Ports as General Digital I/O” on page
56. Most port pins are multiplexed with alternate functions for the peripheral features on the
device. How each alternate function interferes with the port pin is described in “Alternate Port
Functions” on page 60. Refer to the individual module sections for a full description of the alternate functions.
Note that enabling the alternate function of some of the port pins does not affect the use of the
other pins in the port as general digital I/O.
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8008C–AVR–03/09
10.2
Ports as General Digital I/O
The ports are bi-directional I/O ports with optional internal pull-ups. Figure 10-2 shows a functional description of one I/O-port pin, here generically called Pxn.
Figure 10-2. General Digital I/O(1)
PUD
Q
D
DDxn
Q CLR
WDx
RESET
DATA BUS
RDx
1
Q
Pxn
D
0
PORTxn
Q CLR
RESET
SLEEP
RRx
SYNCHRONIZER
D
Q
L
Q
D
WRx
WPx
RPx
Q
PINxn
Q
clk I/O
PUD:
SLEEP:
clkI/O:
Note:
10.2.1
PULLUP DISABLE
SLEEP CONTROL
I/O CLOCK
WDx:
RDx:
WRx:
RRx:
RPx:
WPx:
WRITE DDRx
READ DDRx
WRITE PORTx
READ PORTx REGISTER
READ PORTx PIN
WRITE PINx REGISTER
1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O,
SLEEP, and PUD are common to all ports.
Configuring the Pin
Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in “Register
Description” on page 72, the DDxn bits are accessed at the DDRx I/O address, the PORTxn bits
at the PORTx I/O address, and the PINxn bits at the PINx I/O address.
The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one,
Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input
pin.
If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is
activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has to
be configured as an output pin. The port pins are tri-stated when reset condition becomes active,
even if no clocks are running.
If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven
high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port
pin is driven low (zero).
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10.2.2
Toggling the Pin
Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn.
Note that the SBI instruction can be used to toggle one single bit in a port.
10.2.3
Break-Before-Make Switching
In the Break-Before-Make mode when switching the DDRxn bit from input to output an immediate tri-state period lasting one system clock cycle is introduced as indicated in Figure 10-3. For
example, if the system clock is 4 MHz and the DDRxn is written to make an output, the immediate tri-state period of 250 ns is introduced, before the value of PORTxn is seen on the port pin.
To avoid glitches it is recommended that the maximum DDRxn toggle frequency is two system
clock cycles. The Break-Before-Make is a port-wise mode and it is activated by the port-wise
BBMx enable bits. For details on BBMx bits, see “PORTCR – Port Control Register” on page 72.
When switching the DDRxn bit from output to input there is no immediate tri-state period
introduced.
Figure 10-3. Break Before Make, switching between input and output
SYSTEM CLK
R16
0x02
R17
0x01
INSTRUCTIONS
out DDRx, r16
nop
PORTx
DDRx
0x55
0x01
Px0
Px1
out DDRx, r17
0x02
tri-state
tri-state
tri-state
intermediate tri-state cycle
10.2.4
0x01
intermediate tri-state cycle
Switching Between Input and Output
When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn}
= 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output
low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully acceptable, as a high-impedant environment will not notice the difference between a strong high driver
and a pull-up. If this is not the case, the PUD bit in the MCUCR Register can be set to disable all
pull-ups in all ports.
Switching between input with pull-up and output low generates the same problem. The user
must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn}
= 0b11) as an intermediate step.
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Table 10-1 summarizes the control signals for the pin value.
Table 10-1.
DDxn
PORTxn
PUD
(in MCUCR) (1)
0
0
X
Input
No
Tri-state (Hi-Z)
0
1
0
Input
Yes
Pxn will source current if ext. pulled low.
0
1
1
Input
No
Tri-state (Hi-Z)
1
0
X
Output
No
Output Low (Sink)
1
1
X
Output
No
Output High (Source)
Note:
10.2.5
Port Pin Configurations
I/O
Pull-up
Comment
1. Or port-wise PUDx bit in PORTCR register.
Reading the Pin Value
Independent of the setting of Data Direction bit DDxn, the port pin can be read through the
PINxn Register bit. As shown in Figure 10-2, the PINxn Register bit and the preceding latch constitute a synchronizer. This is needed to avoid metastability if the physical pin changes value
near the edge of the internal clock, but it also introduces a delay. Figure 10-4 shows a timing diagram of the synchronization when reading an externally applied pin value. The maximum and
minimum propagation delays are denoted tpd,max and tpd,min respectively.
Figure 10-4. Synchronization when Reading an Externally Applied Pin value
SYSTEM CLK
INSTRUCTIONS
XXX
XXX
in r17, PINx
SYNC LATCH
PINxn
r17
0x00
0xFF
t pd, max
t pd, min
Consider the clock period starting shortly after the first falling edge of the system clock. The latch
is closed when the clock is low, and goes transparent when the clock is high, as indicated by the
shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock
goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As indicated by the two arrows tpd,max and tpd,min, a single signal transition on the pin will be delayed
between ½ and 1½ system clock period depending upon the time of assertion.
When reading back a software assigned pin value, a nop instruction must be inserted as indicated in Figure 10-5. The out instruction sets the “SYNC LATCH” signal at the positive edge of
the clock. In this case, the delay tpd through the synchronizer is 1 system clock period.
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ATtiny48/88
Figure 10-5. Synchronization when Reading a Software Assigned Pin Value
SYSTEM CLK
r16
INSTRUCTIONS
0xFF
out PORTx, r16
nop
in r17, PINx
SYNC LATCH
PINxn
r17
0x00
0xFF
t pd
The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define
the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. The resulting pin
values are read back again, but as previously discussed, a nop instruction is included to be able
to read back the value recently assigned to some of the pins.
Assembly Code Example(1)
...
; Define pull-ups and set outputs high
; Define directions for port pins
ldi
r16,(1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0)
ldi
r17,(1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0)
out
PORTB,r16
out
DDRB,r17
; Insert nop for synchronization
nop
; Read port pins
in
r16,PINB
...
Note:
1. For the assembly program, two temporary registers are used to minimize the time from pullups are set on pins 0, 1, 6, and 7, until the direction bits are correctly set, defining bit 2 and 3
as low and redefining bits 0 and 1 as strong high drivers.
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C Code Example
unsigned char i;
...
/* Define pull-ups and set outputs high */
/* Define directions for port pins */
PORTB = (1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0);
DDRB = (1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0);
/* Insert nop for synchronization*/
__no_operation();
/* Read port pins */
i = PINB;
...
10.2.6
Digital Input Enable and Sleep Modes
As shown in Figure 10-2, the digital input signal can be clamped to ground at the input of the
Schmitt Trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in
Power-down mode to avoid high power consumption if some input signals are left floating, or
have an analog signal level close to VCC/2.
SLEEP is overridden for port pins enabled as external interrupt pins. If the external interrupt
request is not enabled, SLEEP is active also for these pins. SLEEP is also overridden by various
other alternate functions as described in “Alternate Port Functions” on page 60.
If a logic high level (“one”) is present on an asynchronous external interrupt pin configured as
“Interrupt on Rising Edge, Falling Edge, or Any Logic Change on Pin” while the external interrupt
is not enabled, the corresponding External Interrupt Flag will be set when resuming from the
above mentioned Sleep mode, as the clamping in these sleep mode produces the requested
logic change.
10.2.7
Unconnected Pins
If some pins are unused, it is recommended to ensure that these pins have a defined level. Even
though most of the digital inputs are disabled in the deep sleep modes as described above, floating inputs should be avoided to reduce current consumption in all other modes where the digital
inputs are enabled (Reset, Active mode and Idle mode).
The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up.
In this case, the pull-up will be disabled during reset. If low power consumption during reset is
important, it is recommended to use an external pull-up or pull-down. Connecting unused pins
directly to VCC or GND is not recommended, since this may cause excessive currents if the pin is
accidentally configured as an output.
10.3
Alternate Port Functions
Most port pins have alternate functions in addition to being general digital I/Os. Figure 10-6
shows how the port pin control signals from the simplified Figure 10-2 can be overridden by
alternate functions. The overriding signals may not be present in all port pins, but the figure
serves as a generic description applicable to all port pins in the AVR microcontroller family.
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Figure 10-6. Alternate Port Functions(1)
PUOExn
PUOVxn
1
PUD
0
DDOExn
DDOVxn
1
Q D
DDxn
0
Q CLR
WDx
PVOExn
RESET
RDx
1
DATA BUS
PVOVxn
1
Pxn
Q
0
D
0
PORTxn
PTOExn
Q CLR
DIEOExn
DIEOVxn
WPx
RESET
WRx
1
0
RRx
SLEEP
SYNCHRONIZER
D
SET
Q
RPx
Q
D
PINxn
L
CLR
Q
CLR
Q
clk I/O
DIxn
AIOxn
PUOExn:
PUOVxn:
DDOExn:
DDOVxn:
PVOExn:
PVOVxn:
DIEOExn:
DIEOVxn:
SLEEP:
PTOExn:
Note:
Pxn PULL-UP OVERRIDE ENABLE
Pxn PULL-UP OVERRIDE VALUE
Pxn DATA DIRECTION OVERRIDE ENABLE
Pxn DATA DIRECTION OVERRIDE VALUE
Pxn PORT VALUE OVERRIDE ENABLE
Pxn PORT VALUE OVERRIDE VALUE
Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE
Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE
SLEEP CONTROL
Pxn, PORT TOGGLE OVERRIDE ENABLE
PUD:
WDx:
RDx:
RRx:
WRx:
RPx:
WPx:
clkI/O:
DIxn:
AIOxn:
PULLUP DISABLE
WRITE DDRx
READ DDRx
READ PORTx REGISTER
WRITE PORTx
READ PORTx PIN
WRITE PINx
I/O CLOCK
DIGITAL INPUT PIN n ON PORTx
ANALOG INPUT/OUTPUT PIN n ON PORTx
1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O,
SLEEP, and PUD are common to all ports. All other signals are unique for each pin.
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Table 10-2 summarizes the function of the overriding signals. The pin and port indexes from Figure 10-6 are not shown in the succeeding tables. The overriding signals are generated internally
in the modules having the alternate function.
Table 10-2.
Generic Description of Overriding Signals for Alternate Functions
Signal Name
Full Name
Description
PUOE
Pull-up Override
Enable
If this signal is set, the pull-up enable is controlled by the PUOV
signal. If this signal is cleared, the pull-up is enabled when
{DDxn, PORTxn, PUD} = 0b010.
PUOV
Pull-up Override
Value
If PUOE is set, the pull-up is enabled/disabled when PUOV is
set/cleared, regardless of the setting of the DDxn, PORTxn,
and PUD Register bits.
DDOE
Data Direction
Override Enable
If this signal is set, the Output Driver Enable is controlled by the
DDOV signal. If this signal is cleared, the Output driver is
enabled by the DDxn Register bit.
DDOV
Data Direction
Override Value
If DDOE is set, the Output Driver is enabled/disabled when
DDOV is set/cleared, regardless of the setting of the DDxn
Register bit.
PVOE
Port Value
Override Enable
If this signal is set and the Output Driver is enabled, the port
value is controlled by the PVOV signal. If PVOE is cleared, and
the Output Driver is enabled, the port Value is controlled by the
PORTxn Register bit.
PVOV
Port Value
Override Value
If PVOE is set, the port value is set to PVOV, regardless of the
setting of the PORTxn Register bit.
PTOE
Port Toggle
Override Enable
If PTOE is set, the PORTxn Register bit is inverted.
DIEOE
Digital Input
Enable Override
Enable
If this bit is set, the Digital Input Enable is controlled by the
DIEOV signal. If this signal is cleared, the Digital Input Enable
is determined by MCU state (Normal mode, sleep mode).
DIEOV
Digital Input
Enable Override
Value
If DIEOE is set, the Digital Input is enabled/disabled when
DIEOV is set/cleared, regardless of the MCU state (Normal
mode, sleep mode).
DI
Digital Input
This is the Digital Input to alternate functions. In the figure, the
signal is connected to the output of the Schmitt Trigger but
before the synchronizer. Unless the Digital Input is used as a
clock source, the module with the alternate function will use its
own synchronizer.
AIO
Analog
Input/Output
This is the Analog Input/output to/from alternate functions. The
signal is connected directly to the pad, and can be used bidirectionally.
The following subsections shortly describe the alternate functions for each port, and relate the
overriding signals to the alternate function. Refer to the alternate function description for further
details.
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10.3.1
Alternate Functions of Port A
The Port A pins with alternate functions are shown in Table 10-3.
Table 10-3.
Port A Pins Alternate Functions
Port Pin
Alternate Function
PA3
PCINT27 (Pin Change Interrupt 27)
PA2
PCINT26 (Pin Change Interrupt 26)
PA1
ADC7 (ADC Input Channel 7)
PCINT25 (Pin Change Interrupt 25)
PA0
ADC6 (ADC Input Channel 6)
PCINT24 (Pin Change Interrupt 24)
The alternate pin configuration is as follows:
• PCINT27 – Port A, Bit 3
PCINT27: Pin Change Interrupt source 27.
• PCINT26 – Port A, Bit 2
PCINT26: Pin Change Interrupt source 26.
• ADC7/PCINT25 – Port A, Bit 1
ADC7: PA1 can be used as ADC input Channel 7.
PCINT25: Pin Change Interrupt source 25.
• ADC6/PCINT24 – Port A, Bit 0
ADC6: PA0 can be used as ADC input Channel 6.
PCINT24: Pin Change Interrupt source 24.
Table 10-4 relate the alternate functions of Port A to the overriding signals shown in Figure 10-6
on page 61.
Table 10-4.
Overriding Signals for Alternate Functions in PA3..PA0
Signal Name
PA3/PCINT27
PA2/PCINT26
PA1/ADC7/PCINT25
PA0/ADC6/PCINT24
PUOE
0
0
0
0
PUO
0
0
0
0
DDOE
0
0
0
0
DDOV
0
0
0
0
PVOE
0
0
0
0
PVOV
0
0
0
0
DIEOE
PCINT27 •
PCIE3
PCINT26 •
PCIE3
PCINT25 • PCIE3 +
ADC7D
PCINT24 • PCIE3 +
ADC6D
DIEOV
1
1
1
1
DI
PCINT27 INPUT
PCINT26 INPUT
PCINT25 INPUT
PCINT24 INPUT
AIO
–
–
ADC7 INPUT
ADC6 INPUT
63
8008C–AVR–03/09
10.3.2
Alternate Functions of Port B
The Port B pins with alternate functions are shown in Table 10-5.
Table 10-5.
Port Pin
Port B Pins Alternate Functions
Alternate Functions
PB7
PCINT7 (Pin Change Interrupt 7)
PB6
CLKI (External clock input)
PCINT6 (Pin Change Interrupt 6)
PB5
SCK (SPI Bus Master clock Input)
PCINT5 (Pin Change Interrupt 5)
PB4
MISO (SPI Bus Master Input/Slave Output)
PCINT4 (Pin Change Interrupt 4)
PB3
MOSI (SPI Bus Master Output/Slave Input)
PCINT3 (Pin Change Interrupt 3)
PB2
SS (SPI Bus Master Slave select)
OC1B (Timer/Counter1 Output Compare Match B Output)
PCINT2 (Pin Change Interrupt 2)
PB1
OC1A (Timer/Counter1 Output Compare Match A Output)
PCINT1 (Pin Change Interrupt 1)
PB0
ICP1 (Timer/Counter1 Input Capture Input)
CLKO (Divided System Clock Output)
PCINT0 (Pin Change Interrupt 0)
The alternate pin configuration is as follows:
• PCINT7 – Port B, Bit 7
PCINT7: Pin Change Interrupt source 7. The PB7 pin can serve as an external interrupt source.
If PB7 is used as a clock pin, DDB7, PORTB7 and PINB7 will all read 0.
• CLKI/PCINT6 – Port B, Bit 6
CLKI: External clock input. When used as a clock pin, the pin can not be used as an I/O pin.
PCINT6: Pin Change Interrupt source 6. The PB6 pin can serve as an external interrupt source.
If PB6 is used as a clock pin, DDB6, PORTB6 and PINB6 will all read 0.
• SCK/PCINT5 – Port B, Bit 5
SCK: Master Clock output, Slave Clock input pin for SPI channel. When the SPI is enabled as a
Slave, this pin is configured as an input regardless of the setting of DDB5. When the SPI is
enabled as a Master, the data direction of this pin is controlled by DDB5. When the pin is forced
by the SPI to be an input, the pull-up can still be controlled by the PORTB5 bit.
PCINT5: Pin Change Interrupt source 5. The PB5 pin can serve as an external interrupt source.
• MISO/PCINT4 – Port B, Bit 4
MISO: Master Data input, Slave Data output pin for SPI channel. When the SPI is enabled as a
Master, this pin is configured as an input regardless of the setting of DDB4. When the SPI is
enabled as a Slave, the data direction of this pin is controlled by DDB4. When the pin is forced
by the SPI to be an input, the pull-up can still be controlled by the PORTB4 bit.
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ATtiny48/88
PCINT4: Pin Change Interrupt source 4. The PB4 pin can serve as an external interrupt source.
• MOSI/PCINT3 – Port B, Bit 3
MOSI: SPI Master Data output, Slave Data input for SPI channel. When the SPI is enabled as a
Slave, this pin is configured as an input regardless of the setting of DDB3. When the SPI is
enabled as a Master, the data direction of this pin is controlled by DDB3. When the pin is forced
by the SPI to be an input, the pull-up can still be controlled by the PORTB3 bit.
PCINT3: Pin Change Interrupt source 3. The PB3 pin can serve as an external interrupt source.
• SS/OC1B/PCINT2 – Port B, Bit 2
SS: Slave Select input. When the SPI is enabled as a Slave, this pin is configured as an input
regardless of the setting of DDB2. As a Slave, the SPI is activated when this pin is driven low.
When the SPI is enabled as a Master, the data direction of this pin is controlled by DDB2. When
the pin is forced by the SPI to be an input, the pull-up can still be controlled by the PORTB2 bit.
OC1B, Output Compare Match output: The PB2 pin can serve as an external output for the
Timer/Counter1 Compare Match B. The PB2 pin has to be configured as an output (DDB2 set
(one)) to serve this function. The OC1B pin is also the output pin for the PWM mode timer
function.
PCINT2: Pin Change Interrupt source 2. The PB2 pin can serve as an external interrupt source.
• OC1A/PCINT1 – Port B, Bit 1
OC1A, Output Compare Match output: The PB1 pin can serve as an external output for the
Timer/Counter1 Compare Match A. The PB1 pin has to be configured as an output (DDB1 set
(one)) to serve this function. The OC1A pin is also the output pin for the PWM mode timer
function.
PCINT1: Pin Change Interrupt source 1. The PB1 pin can serve as an external interrupt source.
• ICP1/CLKO/PCINT0 – Port B, Bit 0
ICP1, Input Capture Pin: The PB0 pin can act as an Input Capture Pin for Timer/Counter1.
CLKO, Divided System Clock: The divided system clock can be output on the PB0 pin. The
divided system clock will be output if the CKOUT Fuse is programmed, regardless of the
PORTB0 and DDB0 settings. It will also be output during reset.
PCINT0: Pin Change Interrupt source 0. The PB0 pin can serve as an external interrupt source.
Table 10-6 and Table 10-7 relate the alternate functions of Port B to the overriding signals
shown in Figure 10-6 on page 61. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the
MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT.
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Table 10-6.
Overriding Signals for Alternate Functions in PB7..PB4
Signal
Name
PB7/
PCINT7(1)
PB6/CLKI/
PCINT6(1)
PB5/SCK/
PCINT5
PB4/MISO/
PCINT4
PUOE
0
INTOSC
SPE • MSTR
SPE • MSTR
PUOV
0
0
PORTB5 • PUD
PORTB4 • PUD
DDOE
0
INTOSC
SPE • MSTR
SPE • MSTR
DDOV
0
0
0
0
PVOE
0
0
SPE • MSTR
SPE • MSTR
PVOV
0
0
SCK OUTPUT
SPI SLAVE
OUTPUT
DIEOE
PCINT7 • PCIE0
INTOSC + PCINT6 •
PCIE0
PCINT5 • PCIE0
PCINT4 • PCIE0
DIEOV
1
INTOSC
1
1
DI
PCINT7 INPUT
PCINT6 INPUT
PCINT5 INPUT
SCK INPUT
PCINT4 INPUT
SPI MSTR INPUT
–
Clock Input
–
–
AIO
Notes:
1. INTOSC means that one of the internal oscillators are selected (by the CKSEL fuses), EXTCK
means that external clock is selected (by the CKSEL fuses).
Table 10-7.
66
Overriding Signals for Alternate Functions in PB3..PB0
Signal
Name
PB3/MOSI/
PCINT3
PB2/SS/
OC1B/PCINT2
PB1/OC1A/
PCINT1
PB0/ICP1/
PCINT0
PUOE
SPE • MSTR
SPE • MSTR
0
0
PUOV
PORTB3 • PUD
PORTB2 • PUD
0
0
DDOE
SPE • MSTR
SPE • MSTR
0
0
DDOV
0
0
0
0
PVOE
SPE • MSTR
OC1B ENABLE
OC1A ENABLE
0
PVOV
SPI MSTR OUTPUT
OC1B
OC1A
0
DIEOE
PCINT3 • PCIE0
PCINT2 • PCIE0
PCINT1 • PCIE0
PCINT0 • PCIE0
DIEOV
1
1
1
1
DI
PCINT3 INPUT
SPI SLAVE INPUT
PCINT2 INPUT
SPI SS
PCINT1 INPUT
PCINT0 INPUT
ICP1 INPUT
AIO
–
–
–
–
ATtiny48/88
8008C–AVR–03/09
ATtiny48/88
10.3.3
Alternate Functions of Port C
The Port C pins with alternate functions are shown in Table 10-8.
Table 10-8.
Port Pin
Port C Pins Alternate Functions
Alternate Function
PC7
PCINT15 (Pin Change Interrupt 15)
PC6
RESET (Reset pin)
PCINT14 (Pin Change Interrupt 14)
PC5
ADC5 (ADC Input Channel 5)
SCL (2-wire Serial Bus Clock Line)
PCINT13 (Pin Change Interrupt 13)
PC4
ADC4 (ADC Input Channel 4)
SDA (2-wire Serial Bus Data Input/Output Line)
PCINT12 (Pin Change Interrupt 12)
PC3
ADC3 (ADC Input Channel 3)
PCINT11 (Pin Change Interrupt 11)
PC2
ADC2 (ADC Input Channel 2)
PCINT10 (Pin Change Interrupt 10)
PC1
ADC1 (ADC Input Channel 1)
PCINT9 (Pin Change Interrupt 9)
PC0
ADC0 (ADC Input Channel 0)
PCINT8 (Pin Change Interrupt 8)
The alternate pin configuration is as follows:
• PCINT15 – Port C, Bit 7
PCINT15: Pin Change Interrupt source 15. The PC7 pin can serve as an external interrupt
source.
• RESET/PCINT14 – Port C, Bit 6
RESET, Reset pin: When the RSTDISBL Fuse is programmed, this pin functions as a normal I/O
pin, and the part will have to rely on Power-on Reset and Brown-out Reset as its reset sources.
When the RSTDISBL Fuse is unprogrammed, the reset circuitry is connected to the pin, and the
pin can not be used as an I/O pin.
If PC6 is used as a reset pin, DDC6, PORTC6 and PINC6 will all read 0.
PCINT14: Pin Change Interrupt source 14. The PC6 pin can serve as an external interrupt
source.
• SCL/ADC5/PCINT13 – Port C, Bit 5
SCL, 2-wire Serial Interface Clock: When the TWEN bit in TWCR is set (one) to enable the 2wire Serial Interface, pin PC5 is disconnected from the port and becomes the Serial Clock I/O
pin for the 2-wire Serial Interface. In this mode, there is a spike filter on the pin to suppress
spikes shorter than 50 ns on the input signal, and the pin is driven by an open drain driver with
slew-rate limitation.
PC5 can also be used as ADC input Channel 5. Note that ADC input channel 5 uses digital
power.
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8008C–AVR–03/09
PCINT13: Pin Change Interrupt source 13. The PC5 pin can serve as an external interrupt
source.
• SDA/ADC4/PCINT12 – Port C, Bit 4
SDA, 2-wire Serial Interface Data: When the TWEN bit in TWCR is set (one) to enable the 2-wire
Serial Interface, pin PC4 is disconnected from the port and becomes the Serial Data I/O pin for
the 2-wire Serial Interface. In this mode, there is a spike filter on the pin to suppress spikes
shorter than 50 ns on the input signal, and the pin is driven by an open drain driver with slewrate limitation.
PC4 can also be used as ADC input Channel 4. Note that ADC input channel 4 uses digital
power.
PCINT12: Pin Change Interrupt source 12. The PC4 pin can serve as an external interrupt
source.
• ADC3/PCINT11 – Port C, Bit 3
PC3 can also be used as ADC input Channel 3. Note that ADC input channel 3 uses analog
power.
PCINT11: Pin Change Interrupt source 11. The PC3 pin can serve as an external interrupt
source.
• ADC2/PCINT10 – Port C, Bit 2
PC2 can also be used as ADC input Channel 2. Note that ADC input channel 2 uses analog
power.
PCINT10: Pin Change Interrupt source 10. The PC2 pin can serve as an external interrupt
source.
• ADC1/PCINT9 – Port C, Bit 1
PC1 can also be used as ADC input Channel 1. Note that ADC input channel 1 uses analog
power.
PCINT9: Pin Change Interrupt source 9. The PC1 pin can serve as an external interrupt source.
• ADC0/PCINT8 – Port C, Bit 0
PC0 can also be used as ADC input Channel 0. Note that ADC input channel 0 uses analog
power.
PCINT8: Pin Change Interrupt source 8. The PC0 pin can serve as an external interrupt source.
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ATtiny48/88
Table 10-9 and Table 10-10 relate the alternate functions of Port C to the overriding signals
shown in Figure 10-6 on page 61.
Overriding Signals for Alternate Functions in PC6..PC4(1)
Table 10-9.
PC7/PCINT15
PC6/RESET/
PCINT14
PC5/SCL/ADC5/
PCINT13
PC4/SDA/ADC4/
PCINT12
PUOE
0
RSTDISBL
TWEN
TWEN
PUOV
0
1
PORTC5 • PUD
PORTC4 • PUD
DDOE
0
RSTDISBL
TWEN
TWEN
DDOV
0
0
SCL_OUT
SDA_OUT
PVOE
0
0
TWEN
TWEN
PVOV
0
0
0
0
DIEOE
PCINT15 • PCIE1
RSTDISBL +
PCINT14 • PCIE1
PCINT13 • PCIE1 +
ADC5D
PCINT12 • PCIE1 +
ADC4D
DIEOV
1
RSTDISBL
PCINT13 • PCIE1
PCINT12 • PCIE1
DI
PCINT15 INPUT
PCINT14 INPUT
PCINT13 INPUT
PCINT12 INPUT
AIO
-
RESET INPUT
ADC5 INPUT / SCL
INPUT
ADC4 INPUT / SDA
INPUT
Signal
Name
Note:
1. When enabled, the 2-wire Serial Interface enables slew-rate controls on the output pins PC4
and PC5. This is not shown in the figure. In addition, spike filters are connected between the
AIO outputs shown in the port figure and the digital logic of the TWI module.
Table 10-10. Overriding Signals for Alternate Functions in PC3..PC0
Signal
Name
PC3/ADC3/
PCINT11
PC2/ADC2/
PCINT10
PC1/ADC1/
PCINT9
PC0/ADC0/
PCINT8
PUOE
0
0
0
0
PUOV
0
0
0
0
DDOE
0
0
0
0
DDOV
0
0
0
0
PVOE
0
0
0
0
PVOV
0
0
0
0
DIEOE
PCINT11 • PCIE1 +
ADC3D
PCINT10 • PCIE1 +
ADC2D
PCINT9 • PCIE1 +
ADC1D
PCINT8 • PCIE1 +
ADC0D
DIEOV
PCINT11 • PCIE1
PCINT10 • PCIE1
PCINT9 • PCIE1
PCINT8 • PCIE1
DI
PCINT11 INPUT
PCINT10 INPUT
PCINT9 INPUT
PCINT8 INPUT
AIO
ADC3 INPUT
ADC2 INPUT
ADC1 INPUT
ADC0 INPUT
69
8008C–AVR–03/09
10.3.4
Alternate Functions of Port D
The Port D pins with alternate functions are shown in Table 10-11.
Table 10-11. Port D Pins Alternate Functions
Port Pin
Alternate Function
PD7
AIN1 (Analog Comparator Negative Input)
PCINT23 (Pin Change Interrupt 23)
PD6
AIN0 (Analog Comparator Positive Input)
PCINT22 (Pin Change Interrupt 22)
PD5
T1 (Timer/Counter 1 External Counter Input)
PCINT21 (Pin Change Interrupt 21)
PD4
T0 (Timer/Counter 0 External Counter Input)
PCINT20 (Pin Change Interrupt 20)
PD3
INT1 (External Interrupt 1 Input)
PCINT19 (Pin Change Interrupt 19)
PD2
INT0 (External Interrupt 0 Input)
PCINT18 (Pin Change Interrupt 18)
PD1
PCINT17 (Pin Change Interrupt 17)
PD0
PCINT16 (Pin Change Interrupt 16)
The alternate pin configuration is as follows:
• AIN1/PCINT23 – Port D, Bit 7
AIN1: Analog Comparator Negative Input. Configure the port pin as input with the internal pull-up
switched off to avoid the digital port function from interfering with the function of the Analog
Comparator.
PCINT23: Pin Change Interrupt source 23. The PD7 pin can serve as an external interrupt
source.
• AIN0/PCINT22 – Port D, Bit 6
AIN0: Analog Comparator Positive Input. Configure the port pin as input with the internal pull-up
switched off to avoid the digital port function from interfering with the function of the Analog
Comparator.
PCINT22: Pin Change Interrupt source 22. The PD6 pin can serve as an external interrupt
source.
• T1/PCINT21 – Port D, Bit 5
T1: Timer/Counter1 counter source.
PCINT21: Pin Change Interrupt source 21. The PD5 pin can serve as an external interrupt
source.
• T0/PCINT20 – Port D, Bit 4
T0: Timer/Counter0 counter source.
PCINT20: Pin Change Interrupt source 20. The PD4 pin can serve as an external interrupt
source.
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ATtiny48/88
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ATtiny48/88
• INT1/PCINT19 – Port D, Bit 3
INT1, External Interrupt source 1: The PD3 pin can serve as an external interrupt source.
PCINT19: Pin Change Interrupt source 19. The PD3 pin can serve as an external interrupt
source.
• INT0/PCINT18 – Port D, Bit 2
INT0, External Interrupt source 0: The PD2 pin can serve as an external interrupt source.
PCINT18: Pin Change Interrupt source 18. The PD2 pin can serve as an external interrupt
source.
• PCINT17 – Port D, Bit 1
PCINT17: Pin Change Interrupt source 17. The PD1 pin can serve as an external interrupt
source.
• PCINT16 – Port D, Bit 0
PCINT16: Pin Change Interrupt source 16. The PD0 pin can serve as an external interrupt
source.
Table 10-12 and Table 10-13 relate the alternate functions of Port D to the overriding signals
shown in Figure 10-6 on page 61.
Table 10-12. Overriding Signals for Alternate Functions PD7..PD4
Signal
Name
PD7/AIN1/PCINT23
PD6/AIN0/PCINT22
PD5/T1/PCINT21
PD4/T0/PCINT20
PUOE
0
0
0
0
PUO
0
0
0
0
DDOE
0
0
0
0
DDOV
0
0
0
0
PVOE
0
0
0
0
PVOV
0
0
0
0
DIEOE
PCINT23 • PCIE2
PCINT22 • PCIE2
PCINT21 • PCIE2
PCINT20 • PCIE2
DIEOV
1
1
1
1
DI
PCINT23 INPUT
PCINT22 INPUT
PCINT21 INPUT
T1 INPUT
PCINT20 INPUT
T0 INPUT
AIO
AIN1 INPUT
AIN0 INPUT
–
–
71
8008C–AVR–03/09
Table 10-13. Overriding Signals for Alternate Functions in PD3..PD0
10.4
10.4.1
Signal
Name
PD3/INT1/PCINT19
PD2/INT0/PCINT18
PD1/PCINT17
PD0/PCINT16
PUOE
0
0
0
0
PUO
0
0
0
0
DDOE
0
0
0
0
DDOV
0
0
0
0
PVOE
0
0
0
0
PVOV
0
0
0
0
DIEOE
INT1 ENABLE +
PCINT19 • PCIE2
INT0 ENABLE +
PCINT18 • PCIE1
PCINT17 • PCIE2
PCINT16 • PCIE2
DIEOV
1
1
1
1
DI
PCINT19 INPUT
INT1 INPUT
PCINT18 INPUT
INT0 INPUT
PCINT17 INPUT
PCINT16 INPUT
AIO
–
–
–
–
Register Description
MCUCR – MCU Control Register
Bit
7
6
5
4
3
2
1
0
–
BPDS
BPDSE
PUD
–
–
–
–
Read/Write
R
R/W
R/W
R/W
R
R
R
R
Initial Value
0
0
0
0
0
0
0
0
MCUCR
• Bit 4 – PUD: Pull-up Disable
When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and
PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See “Configuring the Pin” on page 56 for more details about this feature.
10.4.2
PORTCR – Port Control Register
Bit
7
6
5
4
3
2
1
0
BBMD
BBMC
BBMB
BBMA
PUDD
PUDC
PUDB
PUDA
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
PORTCR
• Bits 7..4 – BBMx: Break-Before-Make Mode Enable
When these bits are written to one, the port-wise Break-Before-Make mode is activated. The
intermediate tri-state cycle is then inserted when writing DDRxn to make an output. For further
information, see “Break-Before-Make Switching” on page 57.
• Bits 3..0 – PUDx: Port-Wise Pull-up Disable
When these bits are written to one, the port-wise pull-ups in the defined I/O ports are disabled
even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn}
= 0b01). The Port-Wise Pull-up Disable bits are ORed with the global Pull-up Disable bit (PUD)
72
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ATtiny48/88
from the MCUCR register. See “Configuring the Pin” on page 56 for more details about this
feature.
10.4.3
PORTA – The Port A Data Register
Bit
10.4.4
7
6
5
4
3
2
1
0
-
-
-
-
PORTA3
PORTA2
PORTA1
PORTA0
Read/Write
R
R
R
R
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
DDRA – The Port A Data Direction Register
Bit
10.4.5
7
6
5
4
3
2
1
0
-
-
-
-
DDA3
DDA2
DDA1
DDA0
Read/Write
R
R
R
R
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
-
-
-
-
PINA3
PINA2
PINA1
PINA0
Read/Write
R
R
R
R
R
R
R
R
Initial Value
0
0
0
0
N/A
N/A
N/A
N/A
7
6
5
4
3
2
1
0
PORTB7
PORTB6
PORTB5
PORTB4
PORTB3
PORTB2
PORTB1
PORTB0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
DDB7
DDB6
DDB5
DDB4
DDB3
DDB2
DDB1
DDB0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
PINB7
PINB6
PINB5
PINB4
PINB3
PINB2
PINB1
PINB0
Read/Write
R
R
R
R
R
R
R
R
Initial Value
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
PINB
PORTC – The Port C Data Register
Bit
10.4.10
DDRB
PINB – The Port B Input Pins
Bit
10.4.9
PORTB
DDRB – The Port B Data Direction Register
Bit
10.4.8
PINA
PORTB – The Port B Data Register
Bit
10.4.7
DDRA
PINA – The Port A Input Pins
Bit
10.4.6
PORTA
7
6
5
4
3
2
1
0
PORTC6
PORTC6
PORTC5
PORTC4
PORTC3
PORTC2
PORTC1
PORTC0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
PORTC
DDRC – The Port C Data Direction Register
Bit
7
6
5
4
3
2
1
0
DDC7
DDC6
DDC5
DDC4
DDC3
DDC2
DDC1
DDC0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
DDRC
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8008C–AVR–03/09
10.4.11
PINC – The Port C Input Pins
Bit
10.4.12
7
6
5
4
3
2
1
0
PINC7
PINC6
PINC5
PINC4
PINC3
PINC2
PINC1
PINC0
Read/Write
R
R
R
R
R
R
R
R
Initial Value
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
PORTD – The Port D Data Register
Bit
10.4.13
7
6
5
4
3
2
1
0
PORTD7
PORTD6
PORTD5
PORTD4
PORTD3
PORTD2
PORTD1
PORTD0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
DDD7
DDD6
DDD5
DDD4
DDD3
DDD2
DDD1
DDD0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
DDRD
PIND – The Port D Input Pins
Bit
74
PORTD
DDRD – The Port D Data Direction Register
Bit
10.4.14
PINC
7
6
5
4
3
2
1
0
PIND7
PIND6
PIND5
PIND4
PIND3
PIND2
PIND1
PIND0
Read/Write
R
R
R
R
R
R
R
R
Initial Value
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
PIND
ATtiny48/88
8008C–AVR–03/09
ATtiny48/88
11. 8-bit Timer/Counter0
11.1
Features
• Two Independent Output Compare Units
• Clear Timer on Compare Match (Auto Reload)
• Three Independent Interrupt Sources (TOV0, OCF0A, and OCF0B)
11.2
Overview
Timer/Counter0 is a general purpose 8-bit Timer/Counter module, with two independent Output
Compare Units. It allows accurate program execution timing (event management). A simplified
block diagram of the 8-bit Timer/Counter is shown in Figure 11-1. For the actual placement of
I/O pins, refer to “Pinout of ATtiny48/88” on page 2. CPU accessible I/O Registers, including I/O
bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed
in the “8-bit Timer/Counter Register Description” on page 80.
The PRTIM0 bit in “PRR – Power Reduction Register” on page 37 must be written to zero to
enable Timer/Counter0 module.
Figure 11-1. 8-bit Timer/Counter Block Diagram
Count
Clear
TOVn
(Int.Req.)
Control Logic
clkTn
Clock Select
Edge
Detector
Tn
TOP
( From Prescaler )
Timer/Counter
TCNTn
=
=
OCnA (Int. Req.)
DATA BUS
OCRnA
Fixed
TOP
Value
=
OCnB (Int. Req.)
OCRnB
TCCRnA
11.2.1
Definitions
Many register and bit references in this section are written in general form, where a lower case
“n” replaces the Timer/Counter number (in this case 0) and a lower case “x” replaces the Output
Compare Unit (in this case Compare Unit A or Compare Unit B). However, when using the regis-
75
8008C–AVR–03/09
ter or bit defines in a program, the precise form must be used, i.e., TCNT0 for accessing
Timer/Counter0 counter value and so on.
The definitions in Table 11-1 are used extensively throughout the document.
Table 11-1.
11.2.2
Definitions
MAX
The counter reaches its MAXimum when it becomes 0xFF (decimal 255).
TOP
The counter reaches the TOP when it becomes equal to the highest value in the
count sequence. The TOP value can be assigned to be the fixed value 0xFF
(MAX) or the value stored in the OCR0A Register. The assignment is dependent on the mode of operation.
Registers
The Timer/Counter (TCNT0) and Output Compare Registers (OCR0A and OCR0B) are 8-bit
registers. Interrupt request (abbreviated to Int.Req. in the figure) signals are all visible in the
Timer Interrupt Flag Register (TIFR0). All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK0). TIFR0 and TIMSK0 are not shown in the figure.
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on
the T0 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter
uses to increment its value. The Timer/Counter is inactive when no clock source is selected. The
output from the Clock Select logic is referred to as the timer clock (clkT0).
The Output Compare Registers (OCR0A and OCR0B) are compared with the Timer/Counter
value at all times. The compare match event will also set the Compare Flag (OCF0A or OCF0B)
which can be used to generate an Output Compare interrupt request.
11.3
Timer/Counter Clock Sources
The Timer/Counter can be clocked by an internal or an external clock source. The clock source
is selected by the Clock Select logic which is controlled by the Clock Select (CS02:0) bits
located in the Timer/Counter Control Register (TCCR0A). For details on clock sources and prescaler, see “Timer/Counter0 and Timer/Counter1 Prescalers” on page 112.
11.4
Counter Unit
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure
11-2 shows a block diagram of the counter and its surroundings.
Figure 11-2. Counter Unit Block Diagram
TOVn
(Int.Req.)
DATA BUS
Clock Select
count
TCNTn
clear
Control Logic
clkTn
Edge
Detector
Tn
( From Prescaler )
top
76
ATtiny48/88
8008C–AVR–03/09
ATtiny48/88
Signal description (internal signals):
count
Increment or decrement TCNT0 by 1.
clear
Clear TCNT0 (set all bits to zero).
clkTn
Timer/Counter clock, referred to as clkT0 in the following.
top
Signalize that TCNT0 has reached maximum value.
Depending of the mode of operation used, the counter is cleared or incremented at each timer
clock (clkT0). clkT0 can be generated from an external or internal clock source, selected by the
Clock Select bits (CS02:0). When no clock source is selected (CS02:0 = 0) the timer is stopped.
However, the TCNT0 value can be accessed by the CPU, regardless of whether clkT0 is present
or not. A CPU write overrides (has priority over) all counter clear or count operations.
The counting sequence is determined by the setting of the Clear Timer on Compare Match bit
(CTC0) located in the Timer/Counter Control Register (TCCR0A). For more details about
advanced counting sequences, see “Modes of Operation” on page 78.
The Timer/Counter Overflow Flag (TOV0) is set according to the mode of operation selected by
the CTC0 bit. TOV0 can be used for generating a CPU interrupt.
11.5
Output Compare Unit
The 8-bit comparator continuously compares TCNT0 with the Output Compare Registers
(OCR0A and OCR0B). Whenever TCNT0 equals OCR0A or OCR0B, the comparator signals a
match. A match will set the Output Compare Flag (OCF0A or OCF0B) at the next timer clock
cycle. If the corresponding interrupt is enabled, the Output Compare Flag generates an Output
Compare interrupt. The Output Compare Flag is automatically cleared when the interrupt is executed. Alternatively, the flag can be cleared by software by writing a logical one to its I/O bit
location.
Figure 11-3 shows a block diagram of the Output Compare unit.
Figure 11-3. Output Compare Unit, Block Diagram
DATA BUS
OCRnx
TCNTn
= (8-bit Comparator )
OCFnx (Int.Req.)
11.5.1
Compare Match Blocking by TCNT0 Write
All CPU write operations to the TCNT0 Register will block any compare match that occur in the
next timer clock cycle, even when the timer is stopped. This feature allows OCR0x to be initial-
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8008C–AVR–03/09
ized to the same value as TCNT0 without triggering an interrupt when the Timer/Counter clock is
enabled.
11.5.2
11.6
Using the Output Compare Unit
Since writing TCNT0 in any mode of operation will block all compare matches for one timer clock
cycle, there are risks involved when changing TCNT0 when using the Output Compare Unit,
independently of whether the Timer/Counter is running or not. If the value written to TCNT0
equals the OCR0x value, the compare match will be missed, resulting in incorrect waveform
generation.
Modes of Operation
The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is
defined by the CTC0 bit.
For detailed timing information refer to “Timer/Counter Timing Diagrams” on page 79.
11.6.1
Normal Mode
The simplest mode of operation is the Normal mode (CTC0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns
when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bottom (0x00).
In normal operation the Timer/Counter Overflow Flag (TOV0) will be set in the same timer clock
cycle as the TCNT0 becomes zero. The TOV0 Flag in this case behaves like a ninth bit, except
that it is only set, not cleared. However, combined with the timer overflow interrupt that automatically clears the TOV0 Flag, the timer resolution can be increased by software. There are no
special cases to consider in the Normal mode, a new counter value can be written anytime.
The Output Compare unit can be used to generate interrupts at some given time.
11.6.2
Clear Timer on Compare Match (CTC) Mode
In Clear Timer on Compare or CTC mode (CTC0 = 1), the OCR0A Register is used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter value
(TCNT0) matches the OCR0A. The OCR0A defines the top value for the counter, hence also its
resolution. This mode allows greater control of the compare match output frequency. It also simplifies the operation of counting external events.
The timing diagram for the CTC mode is shown in Figure 11-4. The counter value (TCNT0)
increases until a compare match occurs between TCNT0 and OCR0A, and then counter
(TCNT0) is cleared.
Figure 11-4. CTC Mode, Timing Diagram
OCnx Interrupt Flag Set
TCNTn
Period
78
1
2
3
4
ATtiny48/88
8008C–AVR–03/09
ATtiny48/88
An interrupt can be generated each time the counter value reaches the TOP value by using the
OCF0A Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating
the TOP value. However, changing TOP to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not
have the double buffering feature. If the new value written to OCR0A is lower than the current
value of TCNT0, the counter will miss the compare match. The counter will then have to count to
its maximum value (0xFF) and wrap around starting at 0x00 before the compare match can
occur.
As for the Normal mode of operation, the TOV0 Flag is set in the same timer clock cycle that the
counter counts from MAX to 0x00.
11.7
Timer/Counter Timing Diagrams
The Timer/Counter is a synchronous design and the timer clock (clkT0) is therefore shown as a
clock enable signal in the following figures. The figures include information on when interrupt
flags are set. Figure 11-5 contains timing data for basic Timer/Counter operation. The figure
shows the count sequence close to the MAX value in all modes.
Figure 11-5. Timer/Counter Timing Diagram, no Prescaling
clkI/O
clkTn
(clkI/O /1)
TCNTn
MAX - 1
MAX
BOTTOM
BOTTOM + 1
TOVn
Figure 11-6 shows the same timing data, but with the prescaler enabled.
Figure 11-6. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)
clkI/O
clkTn
(clkI/O /8)
TCNTn
MAX - 1
MAX
BOTTOM
BOTTOM + 1
TOVn
Figure 11-7 shows the setting of OCF0B in all modes and OCF0A in all modes except CTC
mode.
79
8008C–AVR–03/09
Figure 11-7. Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (fclk_I/O/8)
clkI/O
clkTn
(clkI/O /8)
OCRnx - 1
TCNTn
OCRnx
OCRnx
OCRnx + 1
OCRnx + 2
OCRnx Value
OCFnx
Figure 11-8 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode where OCR0A
is TOP.
Figure 11-8. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Prescaler (fclk_I/O/8)
clkI/O
clkTn
(clkI/O /8)
TCNTn
(CTC)
TOP - 1
TOP
BOTTOM
BOTTOM + 1
TOP
OCRnx
OCFnx
11.8
11.8.1
8-bit Timer/Counter Register Description
TCCR0A – Timer/Counter Control Register A–
Bit
7
6
5
4
3
2
1
0
-
-
–
–
CTC0
CS02
CS01
CS00
Read/Write
R
R
R
R
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
TCCR0A
• Bits 7:4 – Res: Reserved Bits
These bits are reserved and will always read zero.
• Bit 3 – CTC0: Clear Timer on Compare Match Mode
This bit control the counting sequence of the counter, the source for maximum (TOP) counter
value, see Table 11-2. Modes of operation supported by the Timer/Counter unit are: Normal
mode (counter), Clear Timer on Compare Match (CTC) mode (see “Modes of Operation” on
page 78).
80
ATtiny48/88
8008C–AVR–03/09
ATtiny48/88
Table 11-2.
CTC Mode Bit Description
Timer/Counter
Mode of Operation
TOP
Update of
OCRx at
TOV Flag
Set on(1)
0
Normal
0xFF
Immediate
MAX
1
CTC
OCRA
Immediate
MAX
Mode
CTC0
0
1
Notes:
1. MAX
= 0xFF
• Bits 2:0 – CS02:0: Clock Select
The three Clock Select bits select the clock source to be used by the Timer/Counter.
Table 11-3.
Clock Select Bit Description
CS02
CS01
CS00
Description
0
0
0
No clock source (Timer/Counter stopped)
0
0
1
clkI/O (No prescaling)
0
1
0
clkI/O/8 (From prescaler)
0
1
1
clkI/O/64 (From prescaler)
1
0
0
clkI/O/256 (From prescaler)
1
0
1
clkI/O/1024 (From prescaler)
1
1
0
External clock source on T0 pin. Clock on falling edge.
1
1
1
External clock source on T0 pin. Clock on rising edge.
If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the
counter even if the pin is configured as an output. This feature allows software control of the
counting.
11.8.2
TCNT0 – Timer/Counter Register
Bit
7
6
5
4
3
2
1
0
TCNT0[7:0]
TCNT0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
The Timer/Counter Register gives direct access, both for read and write operations, to the
Timer/Counter unit 8-bit counter. Writing to the TCNT0 Register blocks (removes) the Compare
Match on the following timer clock. Modifying the counter (TCNT0) while the counter is running,
introduces a risk of missing a Compare Match between TCNT0 and the OCR0x Registers.
11.8.3
OCR0A – Output Compare Register A
Bit
7
6
5
4
3
2
1
0
OCR0A[7:0]
OCR0A
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
The Output Compare Register A contains an 8-bit value that is continuously compared with the
counter value (TCNT0). A match can be used to generate an Output Compare interrupt.
81
8008C–AVR–03/09
11.8.4
OCR0B – Output Compare Register B
Bit
7
6
5
4
3
2
1
0
OCR0B[7:0]
OCR0B
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
The Output Compare Register B contains an 8-bit value that is continuously compared with the
counter value (TCNT0). A match can be used to generate an Output Compare interrupt.
11.8.5
TIMSK0 – Timer/Counter Interrupt Mask Register
Bit
7
6
5
4
3
2
1
0
–
–
–
–
–
OCIE0B
OCIE0A
TOIE0
Read/Write
R
R
R
R
R
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
TIMSK0
• Bits 7..3 – Res: Reserved Bits
These bits are reserved and will always read zero.
• Bit 2 – OCIE0B: Timer/Counter Output Compare Match B Interrupt Enable
When the OCIE0B bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter Compare Match B interrupt is enabled. The corresponding interrupt is executed if
a Compare Match in Timer/Counter occurs, i.e., when the OCF0B bit is set in the Timer/Counter
Interrupt Flag Register – TIFR0.
• Bit 1 – OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable
When the OCIE0A bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter0 Compare Match A interrupt is enabled. The corresponding interrupt is executed
if a Compare Match in Timer/Counter0 occurs, i.e., when the OCF0A bit is set in the
Timer/Counter 0 Interrupt Flag Register – TIFR0.
• Bit 0 – TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is written to one, and the I-bit in the Status Register is set, the
Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an
overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Counter 0 Interrupt Flag Register – TIFR0.
11.8.6
TIFR0 – Timer/Counter 0 Interrupt Flag Register
Bit
7
6
5
4
3
2
1
0
–
–
–
–
–
OCF0B
OCF0A
TOV0
Read/Write
R
R
R
R
R
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
TIFR0
• Bits 7..3 – Res: Reserved Bits
These bits are reserved and will always read zero.
• Bit 2 – OCF0B: Timer/Counter 0 Output Compare B Match Flag
The OCF0B bit is set when a Compare Match occurs between the Timer/Counter and the data in
OCR0B – Output Compare Register0 B. OCF0B is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF0B is cleared by writing a logic one to
82
ATtiny48/88
8008C–AVR–03/09
ATtiny48/88
the flag. When the I-bit in SREG, OCIE0B (Timer/Counter Compare B Match Interrupt Enable),
and OCF0B are set, the Timer/Counter Compare Match Interrupt is executed.
• Bit 1 – OCF0A: Timer/Counter 0 Output Compare A Match Flag
The OCF0A bit is set when a Compare Match occurs between the Timer/Counter0 and the data
in OCR0A – Output Compare Register0. OCF0A is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, OCF0A is cleared by writing a logic one to
the flag. When the I-bit in SREG, OCIE0A (Timer/Counter0 Compare Match Interrupt Enable),
and OCF0A are set, the Timer/Counter0 Compare Match Interrupt is executed.
• Bit 0 – TOV0: Timer/Counter0 Overflow Flag
The bit TOV0 is set when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware
when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by
writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt
Enable), and TOV0 are set, the Timer/Counter0 Overflow interrupt is executed.
See Table 11-2, “CTC Mode Bit Description” on page 81.
83
8008C–AVR–03/09
12. 16-bit Timer/Counter1 with PWM
12.1
Features
•
•
•
•
•
•
•
•
•
•
•
12.2
True 16-bit Design (i.e., Allows 16-bit PWM)
Two independent Output Compare Units
Double Buffered Output Compare Registers
One Input Capture Unit
Input Capture Noise Canceler
Clear Timer on Compare Match (Auto Reload)
Glitch-free, Phase Correct Pulse Width Modulator (PWM)
Variable PWM Period
Frequency Generator
External Event Counter
Four independent interrupt Sources (TOV1, OCF1A, OCF1B, and ICF1)
Overview
Most register and bit references in this section are written in general form, where a lower case
“n” replaces the Timer/Counter number, and a lower case “x” replaces the Output Compare unit
channel. However, when using the register or bit defines in a program, the precise form must be
used, i.e., TCNT1 for accessing Timer/Counter1 counter value and so on.
The 16-bit Timer/Counter unit allows accurate program execution timing (event management),
wave generation, and signal timing measurement. A simplified block diagram of the 16-bit
Timer/Counter is shown in Figure 12-1.
Figure 12-1. 16-bit Timer/Counter Block Diagram(1)
Count
Clear
Direction
TOVn
(Int.Req.)
Control Logic
clkTn
Clock Select
Edge
Detector
TOP
Tn
BOTTOM
( From Prescaler )
Timer/Counter
TCNTn
=
=0
OCnA
(Int.Req.)
Waveform
Generation
=
OCnA
DATA BUS
OCRnA
OCnB
(Int.Req.)
Fixed
TOP
Values
Waveform
Generation
=
OCRnB
OCnB
( From Analog
Comparator Ouput )
ICFn (Int.Req.)
Edge
Detector
ICRn
Noise
Canceler
ICPn
TCCRnA
Note:
84
TCCRnB
1. Refer to Figure 1-1 on page 2, Table 10-5 on page 64 and Table 10-11 on page 70 for
Timer/Counter1 pin placement and description.
ATtiny48/88
8008C–AVR–03/09
ATtiny48/88
For actual placement of I/O pins, refer to “Pinout of ATtiny48/88” on page 2. CPU accessible I/O
Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register
and bit locations are listed in the “Register Description” on page 105.
The PRTIM1 bit in “PRR – Power Reduction Register” on page 37 must be written to zero to
enable Timer/Counter1 module.
12.2.1
Registers
The Timer/Counter (TCNT1), Output Compare Registers (OCR1A/B), and Input Capture Register (ICR1) are all 16-bit registers. Special procedures must be followed when accessing the 16bit registers. These procedures are described in the section “Accessing 16-bit Registers” on
page 86. The Timer/Counter Control Registers (TCCR1A/B) are 8-bit registers and have no CPU
access restrictions. Interrupt requests (abbreviated to Int.Req. in the figure) signals are all visible
in the Timer Interrupt Flag Register (TIFR1). All interrupts are individually masked with the Timer
Interrupt Mask Register (TIMSK1). TIFR1 and TIMSK1 are not shown in the figure.
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on
the T1 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter
uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source
is selected. The output from the Clock Select logic is referred to as the timer clock (clkT1).
The double buffered Output Compare Registers (OCR1A/B) are compared with the Timer/Counter value at all time. The result of the compare can be used by the Waveform Generator to
generate a PWM or variable frequency output on the Output Compare pin (OC1A/B). See “Output Compare Units” on page 92.. The compare match event will also set the Compare Match
Flag (OCF1A/B) which can be used to generate an Output Compare interrupt request.
The Input Capture Register can capture the Timer/Counter value at a given external (edge triggered) event on either the Input Capture pin (ICP1) or on the Analog Comparator pins (See
“Analog Comparator” on page 155.) The Input Capture unit includes a digital filtering unit (Noise
Canceler) for reducing the chance of capturing noise spikes.
The TOP value, or maximum Timer/Counter value, can in some modes of operation be defined
by either the OCR1A Register, the ICR1 Register, or by a set of fixed values. When using
OCR1A as TOP value in a PWM mode, the OCR1A Register can not be used for generating a
PWM output. However, the TOP value will in this case be double buffered allowing the TOP
value to be changed in run time. If a fixed TOP value is required, the ICR1 Register can be used
as an alternative, freeing the OCR1A to be used as PWM output.
12.2.2
Definitions
The following definitions are used extensively throughout the section:
Table 12-1.
BOTTOM
The counter reaches the BOTTOM when it becomes 0x0000.
MAX
The counter reaches its MAXimum when it becomes 0xFFFF (decimal 65535).
TOP
The counter reaches the TOP when it becomes equal to the highest value in the count
sequence. The TOP value can be assigned to be one of the fixed values: 0x00FF, 0x01FF,
or 0x03FF, or to the value stored in the OCR1A or ICR1 Register. The assignment is
dependent of the mode of operation.
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8008C–AVR–03/09
12.3
Accessing 16-bit Registers
The TCNT1, OCR1A/B, and ICR1 are 16-bit registers that can be accessed by the AVR CPU via
the 8-bit data bus. The 16-bit register must be byte accessed using two read or write operations.
Each 16-bit timer has a single 8-bit register for temporary storing of the high byte of the 16-bit
access. The same temporary register is shared between all 16-bit registers within each 16-bit
timer. Accessing the low byte triggers the 16-bit read or write operation. When the low byte of a
16-bit register is written by the CPU, the high byte stored in the temporary register, and the low
byte written are both copied into the 16-bit register in the same clock cycle. When the low byte of
a 16-bit register is read by the CPU, the high byte of the 16-bit register is copied into the temporary register in the same clock cycle as the low byte is read.
Not all 16-bit accesses uses the temporary register for the high byte. Reading the OCR1A/B 16bit registers does not involve using the temporary register.
To do a 16-bit write, the high byte must be written before the low byte. For a 16-bit read, the low
byte must be read before the high byte.
The following code examples show how to access the 16-bit Timer Registers assuming that no
interrupts updates the temporary register. The same principle can be used directly for accessing
the OCR1A/B and ICR1 Registers. Note that when using “C”, the compiler handles the 16-bit
access.
Assembly Code Examples(1)
...
; Set TCNT1 to 0x01FF
ldi r17,0x01
ldi r16,0xFF
out TCNT1H,r17
out TCNT1L,r16
; Read TCNT1 into r17:r16
in r16,TCNT1L
in r17,TCNT1H
...
C Code Examples(1)
unsigned int i;
...
/* Set TCNT1 to 0x01FF */
TCNT1 = 0x1FF;
/* Read TCNT1 into i */
i = TCNT1;
...
Note:
1. See ”About Code Examples” on page 7.
For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI”
instructions must be replaced with instructions that allow access to extended I/O. Typically
“LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.
The assembly code example returns the TCNT1 value in the r17:r16 register pair.
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It is important to notice that accessing 16-bit registers are atomic operations. If an interrupt
occurs between the two instructions accessing the 16-bit register, and the interrupt code
updates the temporary register by accessing the same or any other of the 16-bit Timer Registers, then the result of the access outside the interrupt will be corrupted. Therefore, when both
the main code and the interrupt code update the temporary register, the main code must disable
the interrupts during the 16-bit access.
The following code examples show how to do an atomic read of the TCNT1 Register contents.
Reading any of the OCR1A/B or ICR1 Registers can be done by using the same principle.
Assembly Code Example(1)
TIM16_ReadTCNT1:
; Save global interrupt flag
in r18,SREG
; Disable interrupts
cli
; Read TCNT1 into r17:r16
in r16,TCNT1L
in r17,TCNT1H
; Restore global interrupt flag
out SREG,r18
ret
C Code Example(1)
unsigned int TIM16_ReadTCNT1( void )
{
unsigned char sreg;
unsigned int i;
/* Save global interrupt flag */
sreg = SREG;
/* Disable interrupts */
_CLI();
/* Read TCNT1 into i */
i = TCNT1;
/* Restore global interrupt flag */
SREG = sreg;
return i;
}
Note:
1. See ”About Code Examples” on page 7.
For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI”
instructions must be replaced with instructions that allow access to extended I/O. Typically
“LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.
The assembly code example returns the TCNT1 value in the r17:r16 register pair.
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The following code examples show how to do an atomic write of the TCNT1 Register contents.
Writing any of the OCR1A/B or ICR1 Registers can be done by using the same principle.
Assembly Code Example(1)
TIM16_WriteTCNT1:
; Save global interrupt flag
in r18,SREG
; Disable interrupts
cli
; Set TCNT1 to r17:r16
out TCNT1H,r17
out TCNT1L,r16
; Restore global interrupt flag
out SREG,r18
ret
C Code Example(1)
void TIM16_WriteTCNT1( unsigned int i )
{
unsigned char sreg;
unsigned int i;
/* Save global interrupt flag */
sreg = SREG;
/* Disable interrupts */
_CLI();
/* Set TCNT1 to i */
TCNT1 = i;
/* Restore global interrupt flag */
SREG = sreg;
}
Note:
1. See ”About Code Examples” on page 7.
For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI”
instructions must be replaced with instructions that allow access to extended I/O. Typically
“LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.
The assembly code example requires that the r17:r16 register pair contains the value to be written to TCNT1.
12.3.1
12.4
Reusing the Temporary High Byte Register
If writing to more than one 16-bit register where the high byte is the same for all registers written,
then the high byte only needs to be written once. However, note that the same rule of atomic
operation described previously also applies in this case.
Timer/Counter Clock Sources
The Timer/Counter can be clocked by an internal or an external clock source. The clock source
is selected by the Clock Select logic which is controlled by the Clock Select (CS12:0) bits
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located in the Timer/Counter Control Register B (TCCR1B). For details on clock sources and
prescaler, see “Timer/Counter0 and Timer/Counter1 Prescalers” on page 112.
12.5
Counter Unit
The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit.
Figure 12-2 shows a block diagram of the counter and its surroundings.
Figure 12-2. Counter Unit Block Diagram
DATA BUS
(8-bit)
TOVn
(Int.Req.)
TEMP (8-bit)
Clock Select
Count
TCNTnH (8-bit)
TCNTnL (8-bit)
Clear
Direction
TCNTn (16-bit Counter)
Control Logic
clkTn
Edge
Detector
Tn
( From Prescaler )
TOP
BOTTOM
Signal description (internal signals):
Count
Increment or decrement TCNT1 by 1.
Direction
Select between increment and decrement.
Clear
Clear TCNT1 (set all bits to zero).
clkT1
Timer/Counter clock.
TOP
Signalize that TCNT1 has reached maximum value.
BOTTOM
Signalize that TCNT1 has reached minimum value (zero).
The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High (TCNT1H) containing the upper eight bits of the counter, and Counter Low (TCNT1L) containing the lower eight
bits. The TCNT1H Register can only be indirectly accessed by the CPU. When the CPU does an
access to the TCNT1H I/O location, the CPU accesses the high byte temporary register (TEMP).
The temporary register is updated with the TCNT1H value when the TCNT1L is read, and
TCNT1H is updated with the temporary register value when TCNT1L is written. This allows the
CPU to read or write the entire 16-bit counter value within one clock cycle via the 8-bit data bus.
It is important to notice that there are special cases of writing to the TCNT1 Register when the
counter is counting that will give unpredictable results. The special cases are described in the
sections where they are of importance.
Depending on the mode of operation used, the counter is cleared, incremented, or decremented
at each timer clock (clkT1). The clkT1 can be generated from an external or internal clock source,
selected by the Clock Select bits (CS12:0). When no clock source is selected (CS12:0 = 0) the
timer is stopped. However, the TCNT1 value can be accessed by the CPU, independent of
whether clkT1 is present or not. A CPU write overrides (has priority over) all counter clear or
count operations.
The counting sequence is determined by the setting of the Waveform Generation mode bits
(WGM13:0) located in the Timer/Counter Control Registers A and B (TCCR1A and TCCR1B).
There are close connections between how the counter behaves (counts) and how waveforms
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are generated on the Output Compare outputs OC1x. For more details about advanced counting
sequences and waveform generation, see “Modes of Operation” on page 95.
The Timer/Counter Overflow Flag (TOV1) is set according to the mode of operation selected by
the WGM13:0 bits. TOV1 can be used for generating a CPU interrupt.
12.6
Input Capture Unit
The Timer/Counter incorporates an Input Capture unit that can capture external events and give
them a time-stamp indicating time of occurrence. The external signal indicating an event, or multiple events, can be applied via the ICP1 pin or alternatively, via the analog-comparator unit. The
time-stamps can then be used to calculate frequency, duty-cycle, and other features of the signal applied. Alternatively the time-stamps can be used for creating a log of the events.
The Input Capture unit is illustrated by the block diagram shown in Figure 12-3. The elements of
the block diagram that are not directly a part of the Input Capture unit are gray shaded. The
small “n” in register and bit names indicates the Timer/Counter number.
Figure 12-3. Input Capture Unit Block Diagram
DATA BUS
(8-bit)
TEMP (8-bit)
ICRnH (8-bit)
WRITE
ICRnL (8-bit)
TCNTnH (8-bit)
ICRn (16-bit Register)
ACO*
Analog
Comparator
ACIC*
TCNTnL (8-bit)
TCNTn (16-bit Counter)
ICNC
ICES
Noise
Canceler
Edge
Detector
ICFn (Int.Req.)
ICPn
When a change of the logic level (an event) occurs on the Input Capture pin (ICP1), alternatively
on the Analog Comparator output (ACO), and this change confirms to the setting of the edge
detector, a capture will be triggered. When a capture is triggered, the 16-bit value of the counter
(TCNT1) is written to the Input Capture Register (ICR1). The Input Capture Flag (ICF1) is set at
the same system clock as the TCNT1 value is copied into ICR1 Register. If enabled (ICIE1 = 1),
the Input Capture Flag generates an Input Capture interrupt. The ICF1 Flag is automatically
cleared when the interrupt is executed. Alternatively the ICF1 Flag can be cleared by software
by writing a logical one to its I/O bit location.
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Reading the 16-bit value in the Input Capture Register (ICR1) is done by first reading the low
byte (ICR1L) and then the high byte (ICR1H). When the low byte is read the high byte is copied
into the high byte temporary register (TEMP). When the CPU reads the ICR1H I/O location it will
access the TEMP Register.
The ICR1 Register can only be written when using a Waveform Generation mode that utilizes
the ICR1 Register for defining the counter’s TOP value. In these cases the Waveform Generation mode (WGM13:0) bits must be set before the TOP value can be written to the ICR1
Register. When writing the ICR1 Register the high byte must be written to the ICR1H I/O location
before the low byte is written to ICR1L.
For more information on how to access the 16-bit registers refer to “Accessing 16-bit Registers”
on page 86.
12.6.1
Input Capture Trigger Source
The main trigger source for the Input Capture unit is the Input Capture pin (ICP1).
Timer/Counter1 can alternatively use the Analog Comparator output as trigger source for the
Input Capture unit. The Analog Comparator is selected as trigger source by setting the Analog
Comparator Input Capture (ACIC) bit in the Analog Comparator Control and Status Register
(ACSR). Be aware that changing trigger source can trigger a capture. The Input Capture Flag
must therefore be cleared after the change.
Both the Input Capture pin (ICP1) and the Analog Comparator output (ACO) inputs are sampled
using the same technique as for the T1 pin (Figure 13-1 on page 112). The edge detector is also
identical. However, when the noise canceler is enabled, additional logic is inserted before the
edge detector, which increases the delay by four system clock cycles. Note that the input of the
noise canceler and edge detector is always enabled unless the Timer/Counter is set in a Waveform Generation mode that uses ICR1 to define TOP.
An Input Capture can be triggered by software by controlling the port of the ICP1 pin.
12.6.2
Noise Canceler
The noise canceler improves noise immunity by using a simple digital filtering scheme. The
noise canceler input is monitored over four samples, and all four must be equal for changing the
output that in turn is used by the edge detector.
The noise canceler is enabled by setting the Input Capture Noise Canceler (ICNC1) bit in
Timer/Counter Control Register B (TCCR1B). When enabled the noise canceler introduces additional four system clock cycles of delay from a change applied to the input, to the update of the
ICR1 Register. The noise canceler uses the system clock and is therefore not affected by the
prescaler.
12.6.3
Using the Input Capture Unit
The main challenge when using the Input Capture unit is to assign enough processor capacity
for handling the incoming events. The time between two events is critical. If the processor has
not read the captured value in the ICR1 Register before the next event occurs, the ICR1 will be
overwritten with a new value. In this case the result of the capture will be incorrect.
When using the Input Capture interrupt, the ICR1 Register should be read as early in the interrupt handler routine as possible. Even though the Input Capture interrupt has relatively high
priority, the maximum interrupt response time is dependent on the maximum number of clock
cycles it takes to handle any of the other interrupt requests.
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Using the Input Capture unit in any mode of operation when the TOP value (resolution) is
actively changed during operation, is not recommended.
Measurement of an external signal’s duty cycle requires that the trigger edge is changed after
each capture. Changing the edge sensing must be done as early as possible after the ICR1
Register has been read. After a change of the edge, the Input Capture Flag (ICF1) must be
cleared by software (writing a logical one to the I/O bit location). For measuring frequency only,
the clearing of the ICF1 Flag is not required (if an interrupt handler is used).
12.7
Output Compare Units
The 16-bit comparator continuously compares TCNT1 with the Output Compare Register
(OCR1x). If TCNT equals OCR1x the comparator signals a match. A match will set the Output
Compare Flag (OCF1x) at the next timer clock cycle. If enabled (OCIE1x = 1), the Output Compare Flag generates an Output Compare interrupt. The OCF1x Flag is automatically cleared
when the interrupt is executed. Alternatively the OCF1x Flag can be cleared by software by writing a logical one to its I/O bit location. The Waveform Generator uses the match signal to
generate an output according to operating mode set by the Waveform Generation mode
(WGM13:0) bits and Compare Output mode (COM1x1:0) bits. The TOP and BOTTOM signals
are used by the Waveform Generator for handling the special cases of the extreme values in
some modes of operation (See “Modes of Operation” on page 95.)
A special feature of Output Compare unit A allows it to define the Timer/Counter TOP value (i.e.,
counter resolution). In addition to the counter resolution, the TOP value defines the period time
for waveforms generated by the Waveform Generator.
Figure 12-4 shows a block diagram of the Output Compare unit. The small “n” in the register and
bit names indicates the device number (n = 1 for Timer/Counter 1), and the “x” indicates Output
Compare unit (A/B). The elements of the block diagram that are not directly a part of the Output
Compare unit are gray shaded.
Figure 12-4. Output Compare Unit, Block Diagram
DATA BUS
(8-bit)
TEMP (8-bit)
OCRnxH Buf. (8-bit)
OCRnxL Buf. (8-bit)
TCNTnH (8-bit)
OCRnx Buffer (16-bit Register)
OCRnxH (8-bit)
TCNTnL (8-bit)
TCNTn (16-bit Counter)
OCRnxL (8-bit)
OCRnx (16-bit Register)
= (16-bit Comparator )
OCFnx (Int.Req.)
TOP
BOTTOM
Waveform Generator
WGMn3:0
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The OCR1x Register is double buffered when using any of the twelve Pulse Width Modulation
(PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the
double buffering is disabled. The double buffering synchronizes the update of the OCR1x Compare Register to either TOP or BOTTOM of the counting sequence. The synchronization
prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.
The OCR1x Register access may seem complex, but this is not case. When the double buffering
is enabled, the CPU has access to the OCR1x Buffer Register, and if double buffering is disabled the CPU will access the OCR1x directly. The content of the OCR1x (Buffer or Compare)
Register is only changed by a write operation (the Timer/Counter does not update this register
automatically as the TCNT1 and ICR1 Register). Therefore OCR1x is not read via the high byte
temporary register (TEMP). However, it is a good practice to read the low byte first as when
accessing other 16-bit registers. Writing the OCR1x Registers must be done via the TEMP Register since the compare of all 16 bits is done continuously. The high byte (OCR1xH) has to be
written first. When the high byte I/O location is written by the CPU, the TEMP Register will be
updated by the value written. Then when the low byte (OCR1xL) is written to the lower eight bits,
the high byte will be copied into the upper 8-bits of either the OCR1x buffer or OCR1x Compare
Register in the same system clock cycle.
For more information of how to access the 16-bit registers refer to “Accessing 16-bit Registers”
on page 86.
12.7.1
Force Output Compare
In non-PWM Waveform Generation modes, the match output of the comparator can be forced by
writing a one to the Force Output Compare (FOC1x) bit. Forcing compare match will not set the
OCF1x Flag or reload/clear the timer, but the OC1x pin will be updated as if a real compare
match had occurred (the COM11:0 bits settings define whether the OC1x pin is set, cleared or
toggled).
12.7.2
Compare Match Blocking by TCNT1 Write
All CPU writes to the TCNT1 Register will block any compare match that occurs in the next timer
clock cycle, even when the timer is stopped. This feature allows OCR1x to be initialized to the
same value as TCNT1 without triggering an interrupt when the Timer/Counter clock is enabled.
12.7.3
Using the Output Compare Unit
Since writing TCNT1 in any mode of operation will block all compare matches for one timer clock
cycle, there are risks involved when changing TCNT1 when using any of the Output Compare
channels, independent of whether the Timer/Counter is running or not. If the value written to
TCNT1 equals the OCR1x value, the compare match will be missed, resulting in incorrect waveform generation. Do not write the TCNT1 equal to TOP in PWM modes with variable TOP
values. The compare match for the TOP will be ignored and the counter will continue to 0xFFFF.
Similarly, do not write the TCNT1 value equal to BOTTOM when the counter is downcounting.
The setup of the OC1x should be performed before setting the Data Direction Register for the
port pin to output. The easiest way of setting the OC1x value is to use the Force Output Compare (FOC1x) strobe bits in Normal mode. The OC1x Register keeps its value even when
changing between Waveform Generation modes.
Be aware that the COM1x1:0 bits are not double buffered together with the compare value.
Changing the COM1x1:0 bits will take effect immediately.
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12.8
Compare Match Output Unit
The Compare Output mode (COM1x1:0) bits have two functions. The Waveform Generator uses
the COM1x1:0 bits for defining the Output Compare (OC1x) state at the next compare match.
Secondly the COM1x1:0 bits control the OC1x pin output source. Figure 12-5 shows a simplified
schematic of the logic affected by the COM1x1:0 bit setting. The I/O Registers, I/O bits, and I/O
pins in the figure are shown in bold. Only the parts of the general I/O Port Control Registers
(DDR and PORT) that are affected by the COM1x1:0 bits are shown. When referring to the
OC1x state, the reference is for the internal OC1x Register, not the OC1x pin. If a system reset
occur, the OC1x Register is reset to “0”.
Figure 12-5. Compare Match Output Unit (non-PWM Mode), Schematic
COMnx1
COMnx0
FOCnx
Waveform
Generator
D
Q
1
OCnx
DATA BUS
D
0
OCnx
Pin
Q
PORT
D
Q
DDR
clk I/O
The general I/O port function is overridden by the Output Compare (OC1x) from the Waveform
Generator if either of the COM1x1:0 bits are set. However, the OC1x pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction
Register bit for the OC1x pin (DDR_OC1x) must be set as output before the OC1x value is visible on the pin. The port override function is generally independent of the Waveform Generation
mode, but there are some exceptions. Refer to Table 12-2, Table 12-3 and Table 12-4 for
details.
The design of the Output Compare pin logic allows initialization of the OC1x state before the output is enabled. Note that some COM1x1:0 bit settings are reserved for certain modes of
operation. See “Register Description” on page 105.
The COM1x1:0 bits have no effect on the Input Capture unit.
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12.8.1
Compare Output Mode and Waveform Generation
The Waveform Generator uses the COM1x1:0 bits differently in normal, CTC, and PWM modes.
For all modes, setting the COM1x1:0 = 0 tells the Waveform Generator that no action on the
OC1x Register is to be performed on the next compare match. For compare output actions in the
non-PWM modes refer to Table 12-2 on page 105. For fast PWM mode refer to Table 12-3 on
page 105, and for phase correct and phase and frequency correct PWM refer to Table 12-4 on
page 106.
A change of the COM1x1:0 bits state will have effect at the first compare match after the bits are
written. For non-PWM modes, the action can be forced to have immediate effect by using the
FOC1x strobe bits.
12.9
Modes of Operation
The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is
defined by the combination of the Waveform Generation mode (WGM13:0) and Compare Output
mode (COM1x1:0) bits. The Compare Output mode bits do not affect the counting sequence,
while the Waveform Generation mode bits do. The COM1x1:0 bits control whether the PWM output generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes
the COM1x1:0 bits control whether the output should be set, cleared or toggle at a compare
match (See “Compare Match Output Unit” on page 94.)
For detailed timing information refer to “Timer/Counter Timing Diagrams” on page 102.
12.9.1
Normal Mode
The simplest mode of operation is the Normal mode (WGM13:0 = 0). In this mode the counting
direction is always up (incrementing), and no counter clear is performed. The counter simply
overruns when it passes its maximum 16-bit value (MAX = 0xFFFF) and then restarts from the
BOTTOM (0x0000). In normal operation the Timer/Counter Overflow Flag (TOV1) will be set in
the same timer clock cycle as the TCNT1 becomes zero. The TOV1 Flag in this case behaves
like a 17th bit, except that it is only set, not cleared. However, combined with the timer overflow
interrupt that automatically clears the TOV1 Flag, the timer resolution can be increased by software. There are no special cases to consider in the Normal mode, a new counter value can be
written anytime.
The Input Capture unit is easy to use in Normal mode. However, observe that the maximum
interval between the external events must not exceed the resolution of the counter. If the interval
between events are too long, the timer overflow interrupt or the prescaler must be used to
extend the resolution for the capture unit.
The Output Compare units can be used to generate interrupts at some given time. Using the
Output Compare to generate waveforms in Normal mode is not recommended, since this will
occupy too much of the CPU time.
12.9.2
Clear Timer on Compare Match (CTC) Mode
In Clear Timer on Compare or CTC mode (WGM13:0 = 4 or 12), the OCR1A or ICR1 Register
are used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when
the counter value (TCNT1) matches either the OCR1A (WGM13:0 = 4) or the ICR1 (WGM13:0 =
12). The OCR1A or ICR1 define the top value for the counter, hence also its resolution. This
mode allows greater control of the compare match output frequency. It also simplifies the operation of counting external events.
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The timing diagram for the CTC mode is shown in Figure 12-6. The counter value (TCNT1)
increases until a compare match occurs with either OCR1A or ICR1, and then counter (TCNT1)
is cleared.
Figure 12-6. CTC Mode, Timing Diagram
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
TCNTn
OCnA
(Toggle)
Period
(COMnA1:0 = 1)
1
2
3
4
An interrupt can be generated at each time the counter value reaches the TOP value by either
using the OCF1A or ICF1 Flag according to the register used to define the TOP value. If the
interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing the TOP to a value close to BOTTOM when the counter is running with none or a
low prescaler value must be done with care since the CTC mode does not have the double buffering feature. If the new value written to OCR1A or ICR1 is lower than the current value of
TCNT1, the counter will miss the compare match. The counter will then have to count to its maximum value (0xFFFF) and wrap around starting at 0x0000 before the compare match can occur.
In many cases this feature is not desirable. An alternative will then be to use the fast PWM mode
using OCR1A for defining TOP (WGM13:0 = 15) since the OCR1A then will be double buffered.
For generating a waveform output in CTC mode, the OC1A output can be set to toggle its logical
level on each compare match by setting the Compare Output mode bits to toggle mode
(COM1A1:0 = 1). The OC1A value will not be visible on the port pin unless the data direction for
the pin is set to output (DDR_OC1A = 1). The waveform generated will have a maximum frequency of fOC1A = fclk_I/O/2 when OCR1A is set to zero (0x0000). The waveform frequency is
defined by the following equation:
f clk_I/O
f OCnA = -------------------------------------------------2 ⋅ N ⋅ ( 1 + OCRnA )
The N variable represents the prescaler factor (1, 8, 64, 256, or 1024).
As for the Normal mode of operation, the TOV1 Flag is set in the same timer clock cycle that the
counter counts from MAX to 0x0000.
12.9.3
96
Fast PWM Mode
The fast Pulse Width Modulation or fast PWM mode (WGM13:0 = 5, 6, 7, 14, or 15) provides a
high frequency PWM waveform generation option. The fast PWM differs from the other PWM
options by its single-slope operation. The counter counts from BOTTOM to TOP then restarts
from BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC1x) is set on
the compare match between TCNT1 and OCR1x, and cleared at TOP. In inverting Compare
Output mode output is cleared on compare match and set at TOP. Due to the single-slope oper-
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ation, the operating frequency of the fast PWM mode can be twice as high as the phase correct
and phase and frequency correct PWM modes that use dual-slope operation. This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC
applications. High frequency allows physically small sized external components (coils, capacitors), hence reduces total system cost.
The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or
OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can be
calculated by using the following equation:
log ( TOP + 1 )
R FPWM = ----------------------------------log ( 2 )
In fast PWM mode the counter is incremented until the counter value matches either one of the
fixed values 0x00FF, 0x01FF, or 0x03FF (WGM13:0 = 5, 6, or 7), the value in ICR1 (WGM13:0 =
14), or the value in OCR1A (WGM13:0 = 15). The counter is then cleared at the following timer
clock cycle. The timing diagram for the fast PWM mode is shown in Figure 12-7. The figure
shows fast PWM mode when OCR1A or ICR1 is used to define TOP. The TCNT1 value is in the
timing diagram shown as a histogram for illustrating the single-slope operation. The diagram
includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT1
slopes represent compare matches between OCR1x and TCNT1. The OC1x Interrupt Flag will
be set when a compare match occurs.
Figure 12-7. Fast PWM Mode, Timing Diagram
OCRnx/TOP Update and
TOVn Interrupt Flag Set and
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
TCNTn
OCnx
(COMnx1:0 = 2)
OCnx
(COMnx1:0 = 3)
Period
1
2
3
4
5
6
7
8
The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches TOP. In addition
the OC1A or ICF1 Flag is set at the same timer clock cycle as TOV1 is set when either OCR1A
or ICR1 is used for defining the TOP value. If one of the interrupts are enabled, the interrupt handler routine can be used for updating the TOP and compare values.
When changing the TOP value the program must ensure that the new TOP value is higher or
equal to the value of all of the Compare Registers. If the TOP value is lower than any of the
Compare Registers, a compare match will never occur between the TCNT1 and the OCR1x.
Note that when using fixed TOP values the unused bits are masked to zero when any of the
OCR1x Registers are written.
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The procedure for updating ICR1 differs from updating OCR1A when used for defining the TOP
value. The ICR1 Register is not double buffered. This means that if ICR1 is changed to a low
value when the counter is running with none or a low prescaler value, there is a risk that the new
ICR1 value written is lower than the current value of TCNT1. The result will then be that the
counter will miss the compare match at the TOP value. The counter will then have to count to the
MAX value (0xFFFF) and wrap around starting at 0x0000 before the compare match can occur.
The OCR1A Register however, is double buffered. This feature allows the OCR1A I/O location
to be written anytime. When the OCR1A I/O location is written the value written will be put into
the OCR1A Buffer Register. The OCR1A Compare Register will then be updated with the value
in the Buffer Register at the next timer clock cycle the TCNT1 matches TOP. The update is done
at the same timer clock cycle as the TCNT1 is cleared and the TOV1 Flag is set.
Using the ICR1 Register for defining TOP works well when using fixed TOP values. By using
ICR1, the OCR1A Register is free to be used for generating a PWM output on OC1A. However,
if the base PWM frequency is actively changed (by changing the TOP value), using the OCR1A
as TOP is clearly a better choice due to its double buffer feature.
In fast PWM mode, the compare units allow generation of PWM waveforms on the OC1x pins.
Setting the COM1x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output
can be generated by setting the COM1x1:0 to three (see Table on page 105). The actual OC1x
value will only be visible on the port pin if the data direction for the port pin is set as output
(DDR_OC1x). The PWM waveform is generated by setting (or clearing) the OC1x Register at
the compare match between OCR1x and TCNT1, and clearing (or setting) the OC1x Register at
the timer clock cycle the counter is cleared (changes from TOP to BOTTOM).
The PWM frequency for the output can be calculated by the following equation:
f clk_I/O
f OCnxPWM = ---------------------------------N ⋅ ( 1 + TOP )
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCR1x Register represents special cases when generating a PWM
waveform output in the fast PWM mode. If the OCR1x is set equal to BOTTOM (0x0000) the output will be a narrow spike for each TOP+1 timer clock cycle. Setting the OCR1x equal to TOP
will result in a constant high or low output (depending on the polarity of the output set by the
COM1x1:0 bits.)
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OC1A to toggle its logical level on each compare match (COM1A1:0 = 1). This applies only
if OCR1A is used to define the TOP value (WGM13:0 = 15). The waveform generated will have
a maximum frequency of fOC1A = fclk_I/O/2 when OCR1A is set to zero (0x0000). This feature is
similar to the OC1A toggle in CTC mode, except the double buffer feature of the Output Compare unit is enabled in the fast PWM mode.
12.9.4
98
Phase Correct PWM Mode
The phase correct Pulse Width Modulation or phase correct PWM mode (WGM13:0 = 1, 2, 3,
10, or 11) provides a high resolution phase correct PWM waveform generation option. The
phase correct PWM mode is, like the phase and frequency correct PWM mode, based on a dualslope operation. The counter counts repeatedly from BOTTOM (0x0000) to TOP and then from
TOP to BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC1x) is
cleared on the compare match between TCNT1 and OCR1x while upcounting, and set on the
compare match while downcounting. In inverting Output Compare mode, the operation is
ATtiny48/88
8008C–AVR–03/09
ATtiny48/88
inverted. The dual-slope operation has lower maximum operation frequency than single slope
operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes
are preferred for motor control applications.
The PWM resolution for the phase correct PWM mode can be fixed to 8-, 9-, or 10-bit, or defined
by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to
0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can be calculated by using the following equation:
log ( TOP + 1 )
R PCPWM = ----------------------------------log ( 2 )
In phase correct PWM mode the counter is incremented until the counter value matches either
one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGM13:0 = 1, 2, or 3), the value in ICR1
(WGM13:0 = 10), or the value in OCR1A (WGM13:0 = 11). The counter has then reached the
TOP and changes the count direction. The TCNT1 value will be equal to TOP for one timer clock
cycle. The timing diagram for the phase correct PWM mode is shown on Figure 12-8. The figure
shows phase correct PWM mode when OCR1A or ICR1 is used to define TOP. The TCNT1
value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The
diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on
the TCNT1 slopes represent compare matches between OCR1x and TCNT1. The OC1x Interrupt Flag will be set when a compare match occurs.
Figure 12-8. Phase Correct PWM Mode, Timing Diagram
OCRnx/TOP Update and
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
TOVn Interrupt Flag Set
(Interrupt on Bottom)
TCNTn
OCnx
(COMnx1:0 = 2)
OCnx
(COMnx1:0 = 3)
Period
1
2
3
4
The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches BOTTOM. When
either OCR1A or ICR1 is used for defining the TOP value, the OC1A or ICF1 Flag is set accordingly at the same timer clock cycle as the OCR1x Registers are updated with the double buffer
value (at TOP). The Interrupt Flags can be used to generate an interrupt each time the counter
reaches the TOP or BOTTOM value.
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8008C–AVR–03/09
When changing the TOP value the program must ensure that the new TOP value is higher or
equal to the value of all of the Compare Registers. If the TOP value is lower than any of the
Compare Registers, a compare match will never occur between the TCNT1 and the OCR1x.
Note that when using fixed TOP values, the unused bits are masked to zero when any of the
OCR1x Registers are written. As the third period shown in Figure 12-8 illustrates, changing the
TOP actively while the Timer/Counter is running in the phase correct mode can result in an
unsymmetrical output. The reason for this can be found in the time of update of the OCR1x Register. Since the OCR1x update occurs at TOP, the PWM period starts and ends at TOP. This
implies that the length of the falling slope is determined by the previous TOP value, while the
length of the rising slope is determined by the new TOP value. When these two values differ the
two slopes of the period will differ in length. The difference in length gives the unsymmetrical
result on the output.
It is recommended to use the phase and frequency correct mode instead of the phase correct
mode when changing the TOP value while the Timer/Counter is running. When using a static
TOP value there are practically no differences between the two modes of operation.
In phase correct PWM mode, the compare units allow generation of PWM waveforms on the
OC1x pins. Setting the COM1x1:0 bits to two will produce a non-inverted PWM and an inverted
PWM output can be generated by setting the COM1x1:0 to three (See Table on page 106). The
actual OC1x value will only be visible on the port pin if the data direction for the port pin is set as
output (DDR_OC1x). The PWM waveform is generated by setting (or clearing) the OC1x Register at the compare match between OCR1x and TCNT1 when the counter increments, and
clearing (or setting) the OC1x Register at compare match between OCR1x and TCNT1 when
the counter decrements. The PWM frequency for the output when using phase correct PWM can
be calculated by the following equation:
f clk_I/O
f OCnxPCPWM = --------------------------2 ⋅ N ⋅ TOP
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCR1x Register represent special cases when generating a PWM
waveform output in the phase correct PWM mode. If the OCR1x is set equal to BOTTOM the
output will be continuously low and if set equal to TOP the output will be continuously high for
non-inverted PWM mode. For inverted PWM the output will have the opposite logic values. If
OCR1A is used to define the TOP value (WGM13:0 = 11) and COM1A1:0 = 1, the OC1A output
will toggle with a 50% duty cycle.
12.9.5
100
Phase and Frequency Correct PWM Mode
The phase and frequency correct Pulse Width Modulation, or phase and frequency correct PWM
mode (WGM13:0 = 8 or 9) provides a high resolution phase and frequency correct PWM waveform generation option. The phase and frequency correct PWM mode is, like the phase correct
PWM mode, based on a dual-slope operation. The counter counts repeatedly from BOTTOM
(0x0000) to TOP and then from TOP to BOTTOM. In non-inverting Compare Output mode, the
Output Compare (OC1x) is cleared on the compare match between TCNT1 and OCR1x while
upcounting, and set on the compare match while downcounting. In inverting Compare Output
mode, the operation is inverted. The dual-slope operation gives a lower maximum operation frequency compared to the single-slope operation. However, due to the symmetric feature of the
dual-slope PWM modes, these modes are preferred for motor control applications.
ATtiny48/88
8008C–AVR–03/09
ATtiny48/88
The main difference between the phase correct, and the phase and frequency correct PWM
mode is the time the OCR1x Register is updated by the OCR1x Buffer Register, (see Figure 128 and Figure 12-9).
The PWM resolution for the phase and frequency correct PWM mode can be defined by either
ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and
the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can
be calculated using the following equation:
log ( TOP + 1 )
R PFCPWM = ----------------------------------log ( 2 )
In phase and frequency correct PWM mode the counter is incremented until the counter value
matches either the value in ICR1 (WGM13:0 = 8), or the value in OCR1A (WGM13:0 = 9). The
counter has then reached the TOP and changes the count direction. The TCNT1 value will be
equal to TOP for one timer clock cycle. The timing diagram for the phase correct and frequency
correct PWM mode is shown on Figure 12-9. The figure shows phase and frequency correct
PWM mode when OCR1A or ICR1 is used to define TOP. The TCNT1 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram includes noninverted and inverted PWM outputs. The small horizontal line marks on the TCNT1 slopes represent compare matches between OCR1x and TCNT1. The OC1x Interrupt Flag will be set when a
compare match occurs.
Figure 12-9. Phase and Frequency Correct PWM Mode, Timing Diagram
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
OCRnx/TOP Updateand
TOVn Interrupt Flag Set
(Interrupt on Bottom)
TCNTn
OCnx
(COMnx1:0 = 2)
OCnx
(COMnx1:0 = 3)
Period
1
2
3
4
The Timer/Counter Overflow Flag (TOV1) is set at the same timer clock cycle as the OCR1x
Registers are updated with the double buffer value (at BOTTOM). When either OCR1A or ICR1
is used for defining the TOP value, the OC1A or ICF1 Flag set when TCNT1 has reached TOP.
The Interrupt Flags can then be used to generate an interrupt each time the counter reaches the
TOP or BOTTOM value.
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8008C–AVR–03/09
When changing the TOP value the program must ensure that the new TOP value is higher or
equal to the value of all of the Compare Registers. If the TOP value is lower than any of the
Compare Registers, a compare match will never occur between the TCNT1 and the OCR1x.
As Figure 12-9 shows the output generated is, in contrast to the phase correct mode, symmetrical in all periods. Since the OCR1x Registers are updated at BOTTOM, the length of the rising
and the falling slopes will always be equal. This gives symmetrical output pulses and is therefore
frequency correct.
Using the ICR1 Register for defining TOP works well when using fixed TOP values. By using
ICR1, the OCR1A Register is free to be used for generating a PWM output on OC1A. However,
if the base PWM frequency is actively changed by changing the TOP value, using the OCR1A as
TOP is clearly a better choice due to its double buffer feature.
In phase and frequency correct PWM mode, the compare units allow generation of PWM waveforms on the OC1x pins. Setting the COM1x1:0 bits to 0b10 will produce a non-inverted PWM
and an inverted PWM output can be generated by setting the COM1x1:0 to 0b11 (See Table 124 on page 106). The actual OC1x value will only be visible on the port pin if the data direction for
the port pin is set as output (DDR_OC1x). The PWM waveform is generated by setting (or clearing) the OC1x Register at the compare match between OCR1x and TCNT1 when the counter
increments, and clearing (or setting) the OC1x Register at compare match between OCR1x and
TCNT1 when the counter decrements. The PWM frequency for the output when using phase
and frequency correct PWM can be calculated by the following equation:
f clk_I/O
f OCnxPFCPWM = --------------------------2 ⋅ N ⋅ TOP
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCR1x Register represents special cases when generating a PWM
waveform output in the phase correct PWM mode. If the OCR1x is set equal to BOTTOM the
output will be continuously low and if set equal to TOP the output will be set to high for noninverted PWM mode. For inverted PWM the output will have the opposite logic values. If OCR1A
is used to define the TOP value and COM1A1:0 = 1, the OC1A output will toggle with a 50% duty
cycle.
12.10 Timer/Counter Timing Diagrams
The Timer/Counter is a synchronous design and the timer clock (clkT1) is therefore shown as a
clock enable signal in the following figures. The figures include information on when Interrupt
Flags are set, and when the OCR1x Register is updated with the OCR1x buffer value (only for
modes utilizing double buffering). Figure 12-10 shows a timing diagram for the setting of OCF1x.
102
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ATtiny48/88
Figure 12-10. Timer/Counter Timing Diagram, Setting of OCF1x, no Prescaling
clkI/O
clkTn
(clkI/O /1)
TCNTn
OCRnx - 1
OCRnx
OCRnx
OCRnx + 1
OCRnx + 2
OCRnx Value
OCFnx
Figure 12-11 shows the same timing data, but with the prescaler enabled.
Figure 12-11. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (fclk_I/O/8)
clkI/O
clkTn
(clkI/O /8)
TCNTn
OCRnx
OCRnx - 1
OCRnx
OCRnx + 1
OCRnx + 2
OCRnx Value
OCFnx
Figure 12-12 shows the count sequence close to TOP in various modes. When using phase and
frequency correct PWM mode the OCR1x Register is updated at BOTTOM. The timing diagrams
will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1 and so on.
The same renaming applies for modes that set the TOV1 Flag at BOTTOM.
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8008C–AVR–03/09
Figure 12-12. Timer/Counter Timing Diagram, no Prescaling
clkI/O
clkTn
(clkI/O /1)
TCNTn
(CTC and FPWM)
TCNTn
(PC and PFC PWM)
TOP - 1
TOP
BOTTOM
BOTTOM + 1
TOP - 1
TOP
TOP - 1
TOP - 2
TOVn (FPWM)
and ICFn (if used
as TOP)
OCRnx
(Update at TOP)
Old OCRnx Value
New OCRnx Value
Figure 12-13 shows the same timing data, but with the prescaler enabled.
Figure 12-13. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)
clkI/O
clkTn
(clkI/O/8)
TCNTn
(CTC and FPWM)
TCNTn
(PC and PFC PWM)
TOP - 1
TOP
BOTTOM
BOTTOM + 1
TOP - 1
TOP
TOP - 1
TOP - 2
TOVn (FPWM)
and ICF n (if used
as TOP)
OCRnx
(Update at TOP)
104
Old OCRnx Value
New OCRnx Value
ATtiny48/88
8008C–AVR–03/09
ATtiny48/88
12.11 Register Description
12.11.1
TCCR1A – Timer/Counter1 Control Register A
Bit
7
6
5
4
3
2
1
0
COM1A1
COM1A0
COM1B1
COM1B0
–
–
WGM11
WGM10
Read/Write
R/W
R/W
R/W
R/W
R
R
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
TCCR1A
• Bit 7:6 – COM1A1:0: Compare Output Mode for Channel A
• Bit 5:4 – COM1B1:0: Compare Output Mode for Channel B
The COM1A1:0 and COM1B1:0 control the Output Compare pins (OC1A and OC1B respectively) behavior. If one or both of the COM1A1:0 bits are written to one, the OC1A output
overrides the normal port functionality of the I/O pin it is connected to. If one or both of the
COM1B1:0 bit are written to one, the OC1B output overrides the normal port functionality of the
I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit corresponding to the OC1A or OC1B pin must be set in order to enable the output driver.
When the OC1A or OC1B is connected to the pin, the function of the COM1x1:0 bits is dependent of the WGM13:0 bits setting. Table 12-2 shows the COM1x1:0 bit functionality when the
WGM13:0 bits are set to a Normal or a CTC mode (non-PWM).
Table 12-2.
Compare Output Mode, non-PWM
COM1A1/COM1B1
COM1A0/COM1B0
Description
0
0
Normal port operation, OC1A/OC1B disconnected.
0
1
Toggle OC1A/OC1B on Compare Match.
1
0
Clear OC1A/OC1B on Compare Match (Set output to
low level).
1
1
Set OC1A/OC1B on Compare Match (Set output to
high level).
Table 12-3 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the fast
PWM mode.
Table 12-3.
Compare Output Mode, Fast PWM(1)
COM1A1/COM1B1
COM1A0/COM1B0
0
0
Normal port operation, OC1A/OC1B disconnected.
0
1
WGM13:0 = 14 or 15: Toggle OC1A on Compare
Match, OC1B disconnected (normal port operation).
For all other WGM1 settings, normal port operation,
OC1A/OC1B disconnected.
1
0
Clear OC1A/OC1B on Compare Match, set
OC1A/OC1B at TOP
1
1
Set OC1A/OC1B on Compare Match, clear
OC1A/OC1B at TOP
Note:
Description
1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. In
this case the compare match is ignored, but the set or clear is done at TOP. See “Fast PWM
Mode” on page 96. for more details.
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8008C–AVR–03/09
Table 12-4 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the phase
correct or the phase and frequency correct, PWM mode.
Table 12-4.
Compare Output Mode, Phase Correct and Phase & Frequency Correct PWM(1)
COM1A1
COM1B1
COM1A0
COM1B0
0
0
Normal port operation, OC1A/OC1B disconnected.
0
1
WGM13:0 = 8, 9, 10 or 11: Toggle OC1A on Compare Match, OC1B
disconnected (normal port operation). For all other WGM1 settings, normal
port operation, OC1A/OC1B disconnected.
1
0
Clear OC1A/OC1B on Compare Match when up-counting. Set OC1A/OC1B
on Compare Match when downcounting.
1
1
Set OC1A/OC1B on Compare Match when up-counting. Clear OC1A/OC1B
on Compare Match when downcounting.
Note:
Description
1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. See
“Phase Correct PWM Mode” on page 98. for more details.
• Bits 3,2 – Reserved
These bits are reserved and will always read zero.
• Bit 1:0 – WGM11:0: Waveform Generation Mode
Combined with the WGM13:2 bits found in the TCCR1B Register, these bits control the counting
sequence of the counter, the source for maximum (TOP) counter value, and what type of waveform generation to be used, see Table 12-5.
Table 12-5.
Waveform Generation Mode Bit Description
Mode
WGM
13
WGM
12
WGM
11
WGM
10
Timer/Counter
Mode of Operation
TOP
Update of
OCR1x at
TOV1 Flag
Set on
0
0
0
0
0
Normal
0xFFFF
Immediate
MAX
1
0
0
0
1
PWM, Phase Correct, 8-bit
0x00FF
TOP
BOTTOM
2
0
0
1
0
PWM, Phase Correct, 9-bit
0x01FF
TOP
BOTTOM
3
0
0
1
1
PWM, Phase Correct, 10-bit
0x03FF
TOP
BOTTOM
4
0
1
0
0
CTC
OCR1A
Immediate
MAX
5
0
1
0
1
Fast PWM, 8-bit
0x00FF
TOP
TOP
6
0
1
1
0
Fast PWM, 9-bit
0x01FF
TOP
TOP
7
0
1
1
1
Fast PWM, 10-bit
0x03FF
TOP
TOP
8
1
0
0
0
PWM, Phase & Frequency Correct
ICR1
BOTTOM
BOTTOM
9
1
0
0
1
PWM, Phase & Frequency Correct
OCR1A
BOTTOM
BOTTOM
10
1
0
1
0
PWM, Phase Correct
ICR1
TOP
BOTTOM
11
1
0
1
1
PWM, Phase Correct
OCR1A
TOP
BOTTOM
12
1
1
0
0
CTC
ICR1
Immediate
MAX
13
1
1
0
1
(Reserved)
–
–
–
14
1
1
1
0
Fast PWM
ICR1
TOP
TOP
15
1
1
1
1
Fast PWM
OCR1A
TOP
TOP
106
ATtiny48/88
8008C–AVR–03/09
ATtiny48/88
Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear
Timer on Compare match (CTC) mode, and three types of Pulse Width Modulation (PWM)
modes. (See “Modes of Operation” on page 95.).
12.11.2
TCCR1B – Timer/Counter1 Control Register B
Bit
7
6
5
4
3
2
1
0
ICNC1
ICES1
–
WGM13
WGM12
CS12
CS11
CS10
Read/Write
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
TCCR1B
• Bit 7 – ICNC1: Input Capture Noise Canceler
Setting this bit (to one) activates the Input Capture Noise Canceler. When the noise canceler is
activated, the input from the Input Capture pin (ICP1) is filtered. The filter function requires four
successive equal valued samples of the ICP1 pin for changing its output. The Input Capture is
therefore delayed by four oscillator cycles when the noise canceler is enabled.
• Bit 6 – ICES1: Input Capture Edge Select
This bit selects which edge on the Input Capture pin (ICP1) that is used to trigger a capture
event. When the ICES1 bit is written to zero, a falling (negative) edge is used as trigger, and
when the ICES1 bit is written to one, a rising (positive) edge will trigger the capture.
When a capture is triggered according to the ICES1 setting, the counter value is copied into the
Input Capture Register (ICR1). The event will also set the Input Capture Flag (ICF1), and this
can be used to cause an Input Capture Interrupt, if this interrupt is enabled.
When the ICR1 is used as TOP value (see description of the WGM13:0 bits located in the
TCCR1A and the TCCR1B Register), the ICP1 is disconnected and consequently the Input Capture function is disabled.
• Bit 5 – Reserved Bit
This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be
written to zero when TCCR1B is written.
• Bit 4:3 – WGM13:2: Waveform Generation Mode
See TCCR1A Register description.
• Bit 2:0 – CS12:0: Clock Select
The three Clock Select bits select the clock source to be used by the Timer/Counter, see Figure
12-10 and Figure 12-11.
Table 12-6.
Clock Select Bit Description
CS12
CS11
CS10
Description
0
0
0
No clock source (Timer/Counter stopped).
0
0
1
clkI/O/1 (No prescaling)
0
1
0
clkI/O/8 (From prescaler)
0
1
1
clkI/O/64 (From prescaler)
1
0
0
clkI/O/256 (From prescaler)
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8008C–AVR–03/09
Table 12-6.
Clock Select Bit Description (Continued)
CS12
CS11
CS10
Description
1
0
1
clkI/O/1024 (From prescaler)
1
1
0
External clock source on T1 pin. Clock on falling edge.
1
1
1
External clock source on T1 pin. Clock on rising edge.
If external pin modes are used for the Timer/Counter1, transitions on the T1 pin will clock the
counter even if the pin is configured as an output. This feature allows software control of the
counting.
12.11.3
TCCR1C – Timer/Counter1 Control Register C
Bit
7
6
5
4
3
2
1
FOC1A
FOC1B
–
–
–
–
–
0
–
Read/Write
R/W
R/W
R
R
R
R
R
R
Initial Value
0
0
0
0
0
0
0
0
TCCR1C
• Bit 7 – FOC1A: Force Output Compare for Channel A
• Bit 6 – FOC1B: Force Output Compare for Channel B
The FOC1A/FOC1B bits are only active when the WGM13:0 bits specifies a non-PWM mode.
However, for ensuring compatibility with future devices, these bits must be set to zero when
TCCR1A is written when operating in a PWM mode. When writing a logical one to the
FOC1A/FOC1B bit, an immediate compare match is forced on the Waveform Generation unit.
The OC1A/OC1B output is changed according to its COM1x1:0 bits setting. Note that the
FOC1A/FOC1B bits are implemented as strobes. Therefore it is the value present in the
COM1x1:0 bits that determine the effect of the forced compare.
A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer
on Compare match (CTC) mode using OCR1A as TOP.
The FOC1A/FOC1B bits are always read as zero.
• Bits 5..0 – Reserved
These bits are reserved and will always read zero.
12.11.4
TCNT1H and TCNT1L – Timer/Counter1
Bit
7
6
5
4
3
2
1
0
TCNT1[15:8]
TCNT1H
TCNT1[7:0]
TCNT1L
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
The two Timer/Counter I/O locations (TCNT1H and TCNT1L, combined TCNT1) give direct
access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To
ensure that both the high and low bytes are read and written simultaneously when the CPU
accesses these registers, the access is performed using an 8-bit temporary High Byte Register
(TEMP). This temporary register is shared by all the other 16-bit registers. See “Accessing 16-bit
Registers” on page 86.
Modifying the counter (TCNT1) while the counter is running introduces a risk of missing a compare match between TCNT1 and one of the OCR1x Registers.
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Writing to the TCNT1 Register blocks (removes) the compare match on the following timer clock
for all compare units.
12.11.5
OCR1AH and OCR1AL – Output Compare Register 1 A
Bit
7
6
5
4
3
2
1
0
OCR1A[15:8]
OCR1AH
OCR1A[7:0]
12.11.6
OCR1AL
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
4
3
2
1
0
OCR1BH and OCR1BL – Output Compare Register 1 B
Bit
7
6
5
OCR1B[15:8]
OCR1BH
OCR1B[7:0]
OCR1BL
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
The Output Compare Registers contain a 16-bit value that is continuously compared with the
counter value (TCNT1). A match can be used to generate an Output Compare interrupt, or to
generate a waveform output on the OC1x pin.
The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are
written simultaneously when the CPU writes to these registers, the access is performed using an
8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other
16-bit registers. See “Accessing 16-bit Registers” on page 86.
12.11.7
ICR1H and ICR1L – Input Capture Register 1
Bit
7
6
5
4
3
2
1
0
ICR1[15:8]
ICR1H
ICR1[7:0]
ICR1L
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the
ICP1 pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture
can be used for defining the counter TOP value.
The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read
simultaneously when the CPU accesses these registers, the access is performed using an 8-bit
temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit
registers. See “Accessing 16-bit Registers” on page 86.
12.11.8
TIMSK1 – Timer/Counter1 Interrupt Mask Register
Bit
7
6
5
4
3
2
1
0
–
–
ICIE1
–
–
OCIE1B
OCIE1A
TOIE1
Read/Write
R
R
R/W
R
R
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
TIMSK1
• Bit 7, 6 – Res: Reserved Bits
These bits are reserved and will always read zero.
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• Bit 5 – ICIE1: Timer/Counter1, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt
Vector (see “Interrupts” on page 47) is executed when the ICF1 Flag, located in TIFR1, is set.
• Bit 4, 3 – Res: Reserved Bits
These bits are reserved and will always read zero.
• Bit 2 – OCIE1B: Timer/Counter1, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Output Compare B Match interrupt is enabled. The corresponding
Interrupt Vector (see “Interrupts” on page 47) is executed when the OCF1B Flag, located in
TIFR1, is set.
• Bit 1 – OCIE1A: Timer/Counter1, Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Output Compare A Match interrupt is enabled. The corresponding
Interrupt Vector (see “Interrupts” on page 47) is executed when the OCF1A Flag, located in
TIFR1, is set.
• Bit 0 – TOIE1: Timer/Counter1, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Overflow interrupt is enabled. The corresponding Interrupt Vector
(See “Watchdog Timer” on page 42.) is executed when the TOV1 Flag, located in TIFR1, is set.
12.11.9
TIFR1 – Timer/Counter1 Interrupt Flag Register
Bit
7
6
5
4
3
2
1
0
–
–
ICF1
–
–
OCF1B
OCF1A
TOV1
Read/Write
R
R
R/W
R
R
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
TIFR1
• Bit 7, 6 – Res: Reserved Bits
These bits are reserved and will always read zero.
• Bit 5 – ICF1: Timer/Counter1, Input Capture Flag
This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register
(ICR1) is set by the WGM13:0 to be used as the TOP value, the ICF1 Flag is set when the counter reaches the TOP value.
ICF1 is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively,
ICF1 can be cleared by writing a logic one to its bit location.
• Bit 4, 3 – Res: Reserved Bits
These bits are reserved and will always read zero.
• Bit 2 – OCF1B: Timer/Counter1, Output Compare B Match Flag
This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output
Compare Register B (OCR1B).
Note that a Forced Output Compare (FOC1B) strobe will not set the OCF1B Flag.
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OCF1B is automatically cleared when the Output Compare Match B Interrupt Vector is executed. Alternatively, OCF1B can be cleared by writing a logic one to its bit location.
• Bit 1 – OCF1A: Timer/Counter1, Output Compare A Match Flag
This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output
Compare Register A (OCR1A).
Note that a Forced Output Compare (FOC1A) strobe will not set the OCF1A Flag.
OCF1A is automatically cleared when the Output Compare Match A Interrupt Vector is executed. Alternatively, OCF1A can be cleared by writing a logic one to its bit location.
• Bit 0 – TOV1: Timer/Counter1, Overflow Flag
The setting of this flag is dependent of the WGM13:0 bits setting. In Normal and CTC modes,
the TOV1 Flag is set when the timer overflows. Refer to Table 12-5 on page 106 for the TOV1
Flag behavior when using another WGM13:0 bit setting.
TOV1 is automatically cleared when the Timer/Counter1 Overflow Interrupt Vector is executed.
Alternatively, TOV1 can be cleared by writing a logic one to its bit location.
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13. Timer/Counter0 and Timer/Counter1 Prescalers
“8-bit Timer/Counter0” on page 75 and “16-bit Timer/Counter1 with PWM” on page 84 share the
same prescaler module, but the Timer/Counters can have different prescaler settings. The
description below applies to both Timer/Counter1 and Timer/Counter0.
13.1
Internal Clock Source
The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1). This
provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system
clock frequency (fCLK_I/O). Alternatively, one of four taps from the prescaler can be used as a
clock source. The prescaled clock has a frequency of either fCLK_I/O/8, fCLK_I/O/64, fCLK_I/O/256, or
fCLK_I/O/1024.
13.2
Prescaler Reset
The prescaler is free running, i.e., operates independently of the Clock Select logic of the
Timer/Counter, and it is shared by Timer/Counter1 and Timer/Counter0. Since the prescaler is
not affected by the Timer/Counter’s clock select, the state of the prescaler will have implications
for situations where a prescaled clock is used. One example of prescaling artifacts occurs when
the timer is enabled and clocked by the prescaler (CSn2:0 = 0b010, 0b011, 0b100, or 0b101).
The number of system clock cycles from when the timer is enabled to the first count occurs can
be from 1 to N+1 system clock cycles, where N equals the prescaler divisor (8, 64, 256, or
1024).
It is possible to use the prescaler reset for synchronizing the Timer/Counter to program execution. However, care must be taken if the other Timer/Counter that shares the same prescaler
also uses prescaling. A prescaler reset will affect the prescaler period for all Timer/Counters it is
connected to.
13.3
External Clock Source
An external clock source applied to the T1/T0 pin can be used as Timer/Counter clock
(clkT1/clkT0). The T1/T0 pin is sampled once every system clock cycle by the pin synchronization
logic. The synchronized (sampled) signal is then passed through the edge detector. Figure 13-1
shows a functional equivalent block diagram of the T1/T0 synchronization and edge detector
logic. The registers are clocked at the positive edge of the internal system clock (clkI/O). The latch
is transparent in the high period of the internal system clock.
The edge detector generates one clkT1/clkT0 pulse for each positive (CSn2:0 = 7) or negative
(CSn2:0 = 6) edge it detects.
Figure 13-1. T1/T0 Pin Sampling
Tn
D
Q
D
Q
D
Tn_sync
(To Clock
Select Logic)
Q
LE
clk I/O
Synchronization
Edge Detector
The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles
from an edge has been applied to the T1/T0 pin to the counter is updated.
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Enabling and disabling of the clock input must be done when T1/T0 has been stable for at least
one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.
Each half period of the external clock applied must be longer than one system clock cycle to
ensure correct sampling. The external clock must be guaranteed to have less than half the system clock frequency (fExtClk < fclk_I/O/2) given a 50% duty cycle. Since the edge detector uses
sampling, the maximum frequency of an external clock it can detect is half the sampling frequency (Nyquist sampling theorem). However, due to variation of the system clock frequency
and duty cycle caused by oscillator source tolerances, it is recommended that maximum frequency of an external clock source is less than fclk_I/O/2.5.
An external clock source can not be prescaled.
Figure 13-2. Prescaler for Timer/Counter0 and Timer/Counter1(1)
clk I/O
Clear
PSRSYNC
T0
Synchronization
T1
Synchronization
clkT1
Note:
13.4
13.4.1
clkT0
1. The synchronization logic on the input pins (T1/T0) is shown in Figure 13-1.
Register Description
GTCCR – General Timer/Counter Control Register
Bit
7
6
5
4
3
2
1
0
TSM
–
–
–
–
–
–
PSRSYNC
Read/Write
R/W
R
R
R
R
R
R
R/W
Initial Value
0
0
0
0
0
0
0
0
GTCCR
• Bit 7 – TSM: Timer/Counter Synchronization Mode
Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the
value that is written to the PSRSYNC bit is kept, hence keeping the corresponding prescaler
reset signals asserted. This ensures that the corresponding Timer/Counters are halted and can
be configured to the same value without the risk of one of them advancing during configuration.
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When the TSM bit is written to zero, the PSRSYNC bit are cleared by hardware, and the
Timer/Counters start counting simultaneously.
• Bits 6..1 – Reserved
These bits are reserved and will always read zero.
• Bit 0 – PSRSYNC: Prescaler Reset
When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is normally cleared immediately by hardware, except if the TSM bit is set. Note that Timer/Counter1
and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both
timers.
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14. Serial Peripheral Interface – SPI
14.1
Features
•
•
•
•
•
•
•
•
14.2
Full-duplex, Three-wire Synchronous Data Transfer
Master or Slave Operation
LSB First or MSB First Data Transfer
Seven Programmable Bit Rates
End of Transmission Interrupt Flag
Write Collision Flag Protection
Wake-up from Idle Mode
Double Speed (CK/2) Master SPI Mode
Overview
The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the
ATtiny48/88 and peripheral devices or between several AVR devices.
Figure 14-1. SPI Block Diagram(1)
SPI2X
SPI2X
DIVIDER
/2/4/8/16/32/64/128
Note:
1. Refer to Figure 1-1 on page 2, and Table 10-5 on page 64 for SPI pin placement.
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The PRSPI bit in “PRR – Power Reduction Register” on page 37 must be written to zero to
enable the SPI module.
The interconnection between Master and Slave CPUs with SPI is shown in Figure 14-2. The system consists of two shift Registers, and a Master clock generator. The SPI Master initiates the
communication cycle when pulling low the Slave Select SS pin of the desired Slave. Master and
Slave prepare the data to be sent in their respective shift Registers, and the Master generates
the required clock pulses on the SCK line to interchange data. Data is always shifted from Master to Slave on the Master Out – Slave In, MOSI, line, and from Slave to Master on the Master In
– Slave Out, MISO, line. After each data packet, the Master will synchronize the Slave by pulling
high the Slave Select, SS, line.
When configured as a Master, the SPI interface has no automatic control of the SS line. This
must be handled by user software before communication can start. When this is done, writing a
byte to the SPI Data Register starts the SPI clock generator, and the hardware shifts the eight
bits into the Slave. After shifting one byte, the SPI clock generator stops, setting the end of
Transmission Flag (SPIF). If the SPI Interrupt Enable bit (SPIE) in the SPCR Register is set, an
interrupt is requested. The Master may continue to shift the next byte by writing it into SPDR, or
signal the end of packet by pulling high the Slave Select, SS line. The last incoming byte will be
kept in the Buffer Register for later use.
When configured as a Slave, the SPI interface will remain sleeping with MISO tri-stated as long
as the SS pin is driven high. In this state, software may update the contents of the SPI Data
Register, SPDR, but the data will not be shifted out by incoming clock pulses on the SCK pin
until the SS pin is driven low. As one byte has been completely shifted, the end of Transmission
Flag, SPIF is set. If the SPI Interrupt Enable bit, SPIE, in the SPCR Register is set, an interrupt
is requested. The Slave may continue to place new data to be sent into SPDR before reading
the incoming data. The last incoming byte will be kept in the Buffer Register for later use.
Figure 14-2. SPI Master-slave Interconnection
SHIFT
ENABLE
The system is single buffered in the transmit direction and double buffered in the receive direction. This means that bytes to be transmitted cannot be written to the SPI Data Register before
the entire shift cycle is completed. When receiving data, however, a received character must be
read from the SPI Data Register before the next character has been completely shifted in. Otherwise, the first byte is lost.
In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure
correct sampling of the clock signal, the frequency of the SPI clock should never exceed fosc/4.
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When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden
according to Table 14-1 on page 117. For more details on automatic port overrides, refer to
“Alternate Port Functions” on page 60.
Table 14-1.
Pin
SPI Pin Overrides(Note:)
Direction, Master SPI
Direction, Slave SPI
MOSI
User Defined
Input
MISO
Input
User Defined
SCK
User Defined
Input
SS
User Defined
Input
Note:
See “Alternate Functions of Port B” on page 64 for a detailed description of how to define the
direction of the user defined SPI pins.
The following code examples show how to initialize the SPI as a Master and how to perform a
simple transmission. DDR_SPI in the examples must be replaced by the actual Data Direction
Register controlling the SPI pins. DD_MOSI, DD_MISO and DD_SCK must be replaced by the
actual data direction bits for these pins. E.g. if MOSI is placed on pin PB5, replace DD_MOSI
with DDB5 and DDR_SPI with DDRB.
Assembly Code Example(1)
SPI_MasterInit:
; Set MOSI and SCK output, all others input
ldi
r17,(1<<DD_MOSI)|(1<<DD_SCK)
out
DDR_SPI,r17
; Enable SPI, Master, set clock rate fck/16
ldi
r17,(1<<SPE)|(1<<MSTR)|(1<<SPR0)
out
SPCR,r17
ret
SPI_MasterTransmit:
; Start transmission of data (r16)
out
SPDR,r16
Wait_Transmit:
; Wait for transmission complete
sbis SPSR,SPIF
rjmp Wait_Transmit
ret
Note:
1. See ”About Code Examples” on page 7.
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C Code Example(1)
void SPI_MasterInit(void)
{
/* Set MOSI and SCK output, all others input */
DDR_SPI = (1<<DD_MOSI)|(1<<DD_SCK);
/* Enable SPI, Master, set clock rate fck/16 */
SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0);
}
void SPI_MasterTransmit(char cData)
{
/* Start transmission */
SPDR = cData;
/* Wait for transmission complete */
while(!(SPSR & (1<<SPIF)))
;
}
Note:
1. See ”About Code Examples” on page 7.
The following code examples show how to initialize the SPI as a Slave and how to perform a
simple reception.
Assembly Code Example(1)
SPI_SlaveInit:
; Set MISO output, all others input
ldi
r17,(1<<DD_MISO)
out
DDR_SPI,r17
; Enable SPI
ldi
r17,(1<<SPE)
out
SPCR,r17
ret
SPI_SlaveReceive:
; Wait for reception complete
sbis SPSR,SPIF
rjmp SPI_SlaveReceive
; Read received data and return
in
r16,SPDR
ret
Note:
118
1. See ”About Code Examples” on page 7.
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C Code Example(1)
void SPI_SlaveInit(void)
{
/* Set MISO output, all others input */
DDR_SPI = (1<<DD_MISO);
/* Enable SPI */
SPCR = (1<<SPE);
}
char SPI_SlaveReceive(void)
{
/* Wait for reception complete */
while(!(SPSR & (1<<SPIF)))
;
/* Return Data Register */
return SPDR;
}
14.3
14.3.1
SS Pin Functionality
Slave Mode
When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is
held low, the SPI is activated, and MISO becomes an output if configured so by the user. All
other pins are inputs. When SS is driven high, all pins are inputs, and the SPI is passive, which
means that it will not receive incoming data. Note that the SPI logic will be reset once the SS pin
is driven high.
The SS pin is useful for packet/byte synchronization to keep the slave bit counter synchronous
with the master clock generator. When the SS pin is driven high, the SPI slave will immediately
reset the send and receive logic, and drop any partially received data in the Shift Register.
14.3.2
Master Mode
When the SPI is configured as a Master (MSTR in SPCR is set), the user can determine the
direction of the SS pin.
If SS is configured as an output, the pin is a general output pin which does not affect the SPI
system. Typically, the pin will be driving the SS pin of the SPI Slave.
If SS is configured as an input, it must be held high to ensure Master SPI operation. If the SS pin
is driven low by peripheral circuitry when the SPI is configured as a Master with the SS pin
defined as an input, the SPI system interprets this as another master selecting the SPI as a
slave and starting to send data to it. To avoid bus contention, the SPI system takes the following
actions:
1. The MSTR bit in SPCR is cleared and the SPI system becomes a Slave. As a result of
the SPI becoming a Slave, the MOSI and SCK pins become inputs.
2. The SPIF Flag in SPSR is set, and if the SPI interrupt is enabled, and the I-bit in SREG
is set, the interrupt routine will be executed.
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Thus, when interrupt-driven SPI transmission is used in Master mode, and there exists a possibility that SS is driven low, the interrupt should always check that the MSTR bit is still set. If the
MSTR bit has been cleared by a slave select, it must be set by the user to re-enable SPI Master
mode.
14.4
Data Modes
There are four combinations of SCK phase and polarity with respect to serial data, which are
determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in Figure
14-3 and Figure 14-4.
Figure 14-3. SPI Transfer Format with CPHA = 0
SCK (CPOL = 0)
mode 0
SCK (CPOL = 1)
mode 2
SAMPLE I
MOSI/MISO
CHANGE 0
MOSI PIN
CHANGE 0
MISO PIN
SS
MSB first (DORD = 0) MSB
LSB first (DORD = 1) LSB
Bit 6
Bit 1
Bit 5
Bit 2
Bit 4
Bit 3
Bit 3
Bit 4
Bit 2
Bit 5
Bit 1
Bit 6
LSB
MSB
Figure 14-4. SPI Transfer Format with CPHA = 1
SCK (CPOL = 0)
mode 1
SCK (CPOL = 1)
mode 3
SAMPLE I
MOSI/MISO
CHANGE 0
MOSI PIN
CHANGE 0
MISO PIN
SS
MSB first (DORD = 0)
LSB first (DORD = 1)
120
MSB
LSB
Bit 6
Bit 1
Bit 5
Bit 2
Bit 4
Bit 3
Bit 3
Bit 4
Bit 2
Bit 5
Bit 1
Bit 6
LSB
MSB
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ATtiny48/88
Data bits are shifted out and latched in on opposite edges of the SCK signal, ensuring sufficient
time for data signals to stabilize. This is clearly seen by summarizing Table 14-3 on page 121
and Table 14-4 on page 122, as done in Table 14-2 below.
Table 14-2.
14.5
14.5.1
Setting SPI Mode using Control Bits CPOL and CPHA
CPOL
CPHA
SPI Mode
Leading Edge
Trailing eDge
0
0
0
Sample (Rising)
Setup (Falling)
0
1
1
Setup (Rising)
Sample (Falling)
1
0
2
Sample (Falling)
Setup (Rising)
1
1
3
Setup (Falling)
Sample (Rising)
Register Description
SPCR – SPI Control Register
Bit
7
6
5
4
3
2
1
0
SPIE
SPE
DORD
MSTR
CPOL
CPHA
SPR1
SPR0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
SPCR
• Bit 7 – SPIE: SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and the if
the Global Interrupt Enable bit in SREG is set.
• Bit 6 – SPE: SPI Enable
When the SPE bit is written to one, the SPI is enabled. This bit must be set to enable any SPI
operations.
• Bit 5 – DORD: Data Order
When the DORD bit is written to one, the LSB of the data word is transmitted first.
When the DORD bit is written to zero, the MSB of the data word is transmitted first.
• Bit 4 – MSTR: Master/Slave Select
This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic
zero. If SS is configured as an input and is driven low while MSTR is set, MSTR will be cleared,
and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI Master mode.
• Bit 3 – CPOL: Clock Polarity
When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low
when idle. Refer to Figure 14-3 and Figure 14-4 for an example. The CPOL functionality is summarized below:
Table 14-3.
CPOL Functionality
CPOL
Leading Edge
Trailing Edge
0
Rising
Falling
1
Falling
Rising
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• Bit 2 – CPHA: Clock Phase
The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading (first) or
trailing (last) edge of SCK. Refer to Figure 14-3 and Figure 14-4 for an example. The CPOL
functionality is summarized below:
Table 14-4.
CPHA Functionality
CPHA
Leading Edge
Trailing Edge
0
Sample
Setup
1
Setup
Sample
• Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0
These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have
no effect on the Slave. The relationship between SCK and the oscillator clock frequency fosc is
shown in the following table:
Table 14-5.
14.5.2
Relationship Between SCK and the Oscillator Frequency
SPI2X
SPR1
SPR0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
SCK Frequency
fosc/4
fosc/16
fosc/64
fosc/128
fosc/2
fosc/8
fosc/32
fosc/64
SPSR – SPI Status Register
Bit
7
6
5
4
3
2
1
0
SPIF
WCOL
–
–
–
–
–
SPI2X
Read/Write
R
R
R
R
R
R
R
R/W
Initial Value
0
0
0
0
0
0
0
0
SPSR
• Bit 7 – SPIF: SPI Interrupt Flag
When a serial transfer is complete, the SPIF Flag is set. An interrupt is generated if SPIE in
SPCR is set and global interrupts are enabled. If SS is an input and is driven low when the SPI is
in Master mode, this will also set the SPIF Flag. SPIF is cleared by hardware when executing the
corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first reading the
SPI Status Register with SPIF set, then accessing the SPI Data Register (SPDR).
• Bit 6 – WCOL: Write COLlision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer. The
WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status Register with WCOL set,
and then accessing the SPI Data Register.
• Bit 5..1 – Res: Reserved Bits
These bits are reserved and will always read zero.
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ATtiny48/88
• Bit 0 – SPI2X: Double SPI Speed Bit
When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI
is in Master mode (see Table 14-5). This means that the minimum SCK period will be two CPU
clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to work at fosc/4
or lower.
The SPI interface on the ATtiny48/88 is also used for program memory and EEPROM downloading or uploading. See page 196 for serial programming and verification.
14.5.3
SPDR – SPI Data Register
Bit
7
6
5
4
3
2
1
MSB
0
LSB
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
X
X
X
X
X
X
X
X
SPDR
Undefined
The SPI Data Register is a read/write register used for data transfer between the Register File
and the SPI Shift Register. Writing to the register initiates data transmission. Reading the register causes the Shift Register Receive buffer to be read.
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15. 2-Wire Serial Interface
15.1
Features
•
•
•
•
•
•
•
•
•
•
•
15.2
Simple Yet Powerful and Flexible Communication Interface, only two Bus Lines Needed
Both Master and Slave Operation Supported
Device can Operate as Transmitter or Receiver
7-bit Address Space Allows up to 128 Different Slave Addresses
Multi-master Arbitration Support
Data Transfer Speed Up to 400 kHz in Slave Mode
Slew-rate Limited Output Drivers
Noise Suppression Circuitry Rejects Spikes on Bus Lines
Fully Programmable Slave Address with General Call Support
Address Recognition Causes Wake-up When AVR is in Sleep Mode
Compatible with Philips I2C Protocol
2-wire Serial Interface Bus Definition
The 2-wire Serial Interface (TWI) is ideally suited for typical microcontroller applications. The
TWI protocol allows the systems designer to interconnect up to 128 different devices using only
two bi-directional bus lines, one for clock (SCL) and one for data (SDA). The only external hardware needed to implement the bus is a single pull-up resistor for each of the TWI bus lines. All
devices connected to the bus have individual addresses, and mechanisms for resolving bus
contention are inherent in the TWI protocol.
Figure 15-1. TWI Bus Interconnection
VCC
Device 1
Device 2
Device 3
........
Device n
R1
R2
SDA
SCL
15.2.1
TWI Terminology
The following definitions are frequently encountered in this section.
Table 15-1.
124
TWI Terminology
Term
Description
Master
The device that initiates and terminates a transmission and generates the SCL clock.
Slave
The device addressed by a Master.
Transmitter
The device placing data on the bus.
Receiver
The device reading data from the bus.
ATtiny48/88
8008C–AVR–03/09
ATtiny48/88
The PRTWI bit in “PRR – Power Reduction Register” on page 37 must be written to zero to
enable the 2-wire Serial Interface.
15.2.2
Electrical Interconnection
As depicted in Figure 15-1, both bus lines are connected to the positive supply voltage through
pull-up resistors. The bus drivers of all TWI-compliant devices are open-drain or open-collector.
This implements a wired-AND function which is essential to the operation of the interface. A low
level on a TWI bus line is generated when one or more TWI devices output a zero. A high level
is output when all TWI devices tri-state their outputs, allowing the pull-up resistors to pull the line
high. Note that all AVR devices connected to the TWI bus must be powered in order to allow any
bus operation.
The number of devices that can be connected to the bus is only limited by the bus capacitance
limit of 400 pF and the 7-bit slave address space. A detailed specification of the electrical characteristics of the TWI is given in “2-wire Serial Interface Characteristics” on page 207. Two
different sets of specifications are presented there, one relevant for bus speeds below 100 kHz,
and one valid for bus speeds up to 400 kHz.
15.3
15.3.1
Data Transfer and Frame Format
Transferring Bits
Each data bit transferred on the TWI bus is accompanied by a pulse on the clock line. The level
of the data line must be stable when the clock line is high. The only exception to this rule is for
generating start and stop conditions.
Figure 15-2. Data Validity
SDA
SCL
Data Stable
Data Stable
Data Change
15.3.2
START and STOP Conditions
The Master initiates and terminates a data transmission. The transmission is initiated when the
Master issues a START condition on the bus, and it is terminated when the Master issues a
STOP condition. Between a START and a STOP condition, the bus is considered busy, and no
other master should try to seize control of the bus. A special case occurs when a new START
condition is issued between a START and STOP condition. This is referred to as a REPEATED
START condition, and is used when the Master wishes to initiate a new transfer without relinquishing control of the bus. After a REPEATED START, the bus is considered busy until the next
STOP. This is identical to the START behavior, and therefore START is used to describe both
START and REPEATED START for the remainder of this datasheet, unless otherwise noted. As
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depicted below, START and STOP conditions are signalled by changing the level of the SDA
line when the SCL line is high.
Figure 15-3. START, REPEATED START and STOP conditions
SDA
SCL
START
15.3.3
STOP
REPEATED START
START
STOP
Address Packet Format
All address packets transmitted on the TWI bus are 9 bits long, consisting of 7 address bits, one
READ/WRITE control bit and an acknowledge bit. If the READ/WRITE bit is set, a read operation is to be performed, otherwise a write operation should be performed. When a Slave
recognizes that it is being addressed, it should acknowledge by pulling SDA low in the ninth SCL
(ACK) cycle. If the addressed Slave is busy, or for some other reason can not service the Master’s request, the SDA line should be left high in the ACK clock cycle. The Master can then
transmit a STOP condition, or a REPEATED START condition to initiate a new transmission. An
address packet consisting of a slave address and a READ or a WRITE bit is called SLA+R or
SLA+W, respectively.
Figure 15-4. Address Packet Format
Addr MSB
Addr LSB
R/W
ACK
7
8
9
SDA
SCL
1
2
START
The MSB of the address byte is transmitted first. Slave addresses can freely be allocated by the
designer, but the address 0000 000 is reserved for a general call.
When a general call is issued, all slaves should respond by pulling the SDA line low in the ACK
cycle. A general call is used when a Master wishes to transmit the same message to several
slaves in the system. When the general call address followed by a Write bit is transmitted on the
bus, all slaves set up to acknowledge the general call will pull the SDA line low in the ack cycle.
The following data packets will then be received by all the slaves that acknowledged the general
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ATtiny48/88
call. Note that transmitting the general call address followed by a Read bit is meaningless, as
this would cause contention if several slaves started transmitting different data.
All addresses of the format 1111 xxx should be reserved for future purposes.
15.3.4
Data Packet Format
All data packets transmitted on the TWI bus are nine bits long, consisting of one data byte and
an acknowledge bit. During a data transfer, the Master generates the clock and the START and
STOP conditions, while the Receiver is responsible for acknowledging the reception. An
Acknowledge (ACK) is signalled by the Receiver pulling the SDA line low during the ninth SCL
cycle. If the Receiver leaves the SDA line high, a NACK is signalled. When the Receiver has
received the last byte, or for some reason cannot receive any more bytes, it should inform the
Transmitter by sending a NACK after the final byte. The MSB of the data byte is transmitted first.
Figure 15-5. Data Packet Format
Data MSB
Data LSB
ACK
8
9
Aggregate
SDA
SDA from
Transmitter
SDA from
Receiver
SCL from
Master
1
SLA+R/W
15.3.5
2
7
Data Byte
STOP, REPEATED
START or Next
Data Byte
Combining Address and Data Packets into a Transmission
A transmission basically consists of a START condition, a SLA+R/W, one or more data packets
and a STOP condition. An empty message, consisting of a START followed by a STOP condition, is illegal. Note that the Wired-ANDing of the SCL line can be used to implement
handshaking between the Master and the Slave. The Slave can extend the SCL low period by
pulling the SCL line low. This is useful if the clock speed set up by the Master is too fast for the
Slave, or the Slave needs extra time for processing between the data transmissions. The Slave
extending the SCL low period will not affect the SCL high period, which is determined by the
Master. As a consequence, the Slave can reduce the TWI data transfer speed by prolonging the
SCL duty cycle.
Figure 15-6 shows a typical data transmission. Note that several data bytes can be transmitted
between the SLA+R/W and the STOP condition, depending on the software protocol implemented by the application software.
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Figure 15-6. Typical Data Transmission
Addr MSB
Addr LSB
R/W
ACK
Data MSB
7
8
9
1
Data LSB
ACK
8
9
SDA
SCL
1
START
15.4
2
SLA+R/W
2
7
STOP
Data Byte
Multi-master Bus Systems, Arbitration and Synchronization
The TWI protocol allows bus systems with several masters. Special concerns have been taken
in order to ensure that transmissions will proceed as normal, even if two or more masters initiate
a transmission at the same time. Two problems arise in multi-master systems:
• An algorithm must be implemented allowing only one of the masters to complete the
transmission. All other masters should cease transmission when they discover that they have
lost the selection process. This selection process is called arbitration. When a contending
master discovers that it has lost the arbitration process, it should immediately switch to Slave
mode to check whether it is being addressed by the winning master. The fact that multiple
masters have started transmission at the same time should not be detectable to the slaves,
i.e. the data being transferred on the bus must not be corrupted.
• Different masters may use different SCL frequencies. A scheme must be devised to
synchronize the serial clocks from all masters, in order to let the transmission proceed in a
lockstep fashion. This will facilitate the arbitration process.
Figure 15-7. SCL Synchronization Between Multiple Masters
TA low
TA high
SCL from
Master A
SCL from
Master B
SCL Bus
Line
TBlow
Masters Start
Counting Low Period
128
TBhigh
Masters Start
Counting High Period
ATtiny48/88
8008C–AVR–03/09
ATtiny48/88
The wired-ANDing of the bus lines is used to solve both these problems. The serial clocks from
all masters will be wired-ANDed, yielding a combined clock with a high period equal to the one
from the Master with the shortest high period. The low period of the combined clock is equal to
the low period of the Master with the longest low period. Note that all masters listen to the SCL
line, effectively starting to count their SCL high and low time-out periods when the combined
SCL line goes high or low, respectively.
Arbitration is carried out by all masters continuously monitoring the SDA line after outputting
data. If the value read from the SDA line does not match the value the Master had output, it has
lost the arbitration. Note that a Master can only lose arbitration when it outputs a high SDA value
while another Master outputs a low value. The losing Master should immediately go to Slave
mode, checking if it is being addressed by the winning Master. The SDA line should be left high,
but losing masters are allowed to generate a clock signal until the end of the current data or
address packet. Arbitration will continue until only one Master remains, and this may take many
bits. If several masters are trying to address the same Slave, arbitration will continue into the
data packet.
Figure 15-8. Arbitration Between Two Masters
START
SDA from
Master A
Master A Loses
Arbitration, SDAA SDA
SDA from
Master B
SDA Line
Synchronized
SCL Line
Note that arbitration is not allowed between:
• A REPEATED START condition and a data bit.
• A STOP condition and a data bit.
• A REPEATED START and a STOP condition.
It is the user software’s responsibility to ensure that these illegal arbitration conditions never
occur. This implies that in multi-master systems, all data transfers must use the same composition of SLA+R/W and data packets. In other words: All transmissions must contain the same
number of data packets, otherwise the result of the arbitration is undefined.
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15.5
Overview of the TWI Module
The TWI module is comprised of several submodules, as shown in Figure 15-9. All registers
drawn in a thick line are accessible through the AVR data bus.
Figure 15-9. Overview of the TWI Module
Slew-rate
Control
SDA
Spike
Filter
Slew-rate
Control
Spike
Filter
Bus Interface Unit
START / STOP
Control
Spike Suppression
Arbitration detection
Address/Data Shift
Register (TWDR)
Address Match Unit
Address Register
(TWAR)
Address Comparator
Bit Rate Generator
Prescaler
Bit Rate Register
(TWBR)
Ack
Control Unit
Status Register
(TWSR)
Control Register
(TWCR)
State Machine and
Status control
TWI Unit
SCL
15.5.1
SCL and SDA Pins
These pins interface the AVR TWI with the rest of the MCU system. The output drivers contain a
slew-rate limiter in order to conform to the TWI specification. The input stages contain a spike
suppression unit removing spikes shorter than 50 ns. Note that the internal pull-ups in the AVR
pads can be enabled by setting the PORT bits corresponding to the SCL and SDA pins, as
explained in the I/O Port section. The internal pull-ups can in some systems eliminate the need
for external ones.
15.5.2
Bit Rate Generator Unit
When operating in a Master mode this unit controls the period of SCL. The SCL period is controlled by settings in the TWI Bit Rate Register (TWBR) and the Prescaler bits in the TWI Status
Register (TWSR). Slave operation does not depend on bit rate or prescaler settings, but the
clock frequency in the slave must be at least 16 times higher than the SCL frequency. Note that
slaves may prolong the SCL low period, thereby reducing the average TWI bus clock period.
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The TWI can be set to operate in high-speed mode, as described in “TWHSR – TWI High Speed
Register” on page 154. In high-speed mode the TWI uses the system clock, whereas in normal
mode it relies on a prescaled version of the same. Depending on the clock signal used, the SCL
frequency is generated according to one of the following equations.
In normal mode:
clk I/O
f SCL = -------------------------------------------------------------------16 + ( 2 × TWBR × TWPS )
In high-speed mode:
clk TWIHS
f SCL = -------------------------------------------------------------------16 + ( 2 × TWBR × TWPS )
...where:
• clkI/O = prescaled system clock, see Figure 6-1 on page 25
• clkTWIHS = system clock, see Figure 6-1 on page 25
• TWBR = value of TWI Bit Rate Register, see “TWBR – TWI Bit Rate Register” on page 151
• TWPS = value of TWI prescaler, see Table 15-7 on page 153
Note:
15.5.3
In TWI Master mode TWBR must be 10, or higher .
Bus Interface Unit
This unit contains the Data and Address Shift Register (TWDR), a START/STOP Controller and
Arbitration detection hardware. The TWDR contains the address or data bytes to be transmitted,
or the address or data bytes received. In addition to the 8-bit TWDR, the Bus Interface Unit also
contains a register containing the (N)ACK bit to be transmitted or received. This (N)ACK Register is not directly accessible by the application software. However, when receiving, it can be set
or cleared by manipulating the TWI Control Register (TWCR). When in Transmitter mode, the
value of the received (N)ACK bit can be determined by the value in the TWSR.
The START/STOP Controller is responsible for generation and detection of START, REPEATED
START, and STOP conditions. The START/STOP controller is able to detect START and STOP
conditions even when the AVR MCU is in one of the sleep modes, enabling the MCU to wake up
if addressed by a Master.
If the TWI has initiated a transmission as Master, the Arbitration Detection hardware continuously monitors the transmission trying to determine if arbitration is in process. If the TWI has lost
an arbitration, the Control Unit is informed. Correct action can then be taken and appropriate
status codes generated.
15.5.4
Address Match Unit
The Address Match unit checks if received address bytes match the seven-bit address in the
TWI Address Register (TWAR). If the TWI General Call Recognition Enable (TWGCE) bit in the
TWAR is written to one, all incoming address bits will also be compared against the General Call
address. Upon an address match, the Control Unit is informed, allowing correct action to be
taken. The TWI may or may not acknowledge its address, depending on settings in the TWCR.
The Address Match unit is able to compare addresses even when the AVR MCU is in sleep
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mode, enabling the MCU to wake up if addressed by a Master. If another interrupt (e.g., INT0)
occurs during TWI Power-down address match and wakes up the CPU, the TWI aborts operation and return to it’s idle state. If this cause any problems, ensure that TWI Address Match is the
only enabled interrupt when entering Power-down.
15.5.5
Control Unit
The Control unit monitors the TWI bus and generates responses corresponding to settings in the
TWI Control Register (TWCR). When an event requiring the attention of the application occurs
on the TWI bus, the TWI Interrupt Flag (TWINT) is asserted. In the next clock cycle, the TWI Status Register (TWSR) is updated with a status code identifying the event. The TWSR only
contains relevant status information when the TWI Interrupt Flag is asserted. At all other times,
the TWSR contains a special status code indicating that no relevant status information is available. As long as the TWINT Flag is set, the SCL line is held low. This allows the application
software to complete its tasks before allowing the TWI transmission to continue.
The TWINT Flag is set in the following situations:
• After the TWI has transmitted a START/REPEATED START condition.
• After the TWI has transmitted SLA+R/W.
• After the TWI has transmitted an address byte.
• After the TWI has lost arbitration.
• After the TWI has been addressed by own slave address or general call.
• After the TWI has received a data byte.
• After a STOP or REPEATED START has been received while still addressed as a Slave.
• When a bus error has occurred due to an illegal START or STOP condition.
15.6
Using the TWI
The AVR TWI is byte-oriented and interrupt based. Interrupts are issued after all bus events, like
reception of a byte or transmission of a START condition. Because the TWI is interrupt-based,
the application software is free to carry on other operations during a TWI byte transfer. Note that
the TWI Interrupt Enable (TWIE) bit in TWCR together with the Global Interrupt Enable bit in
SREG allow the application to decide whether or not assertion of the TWINT Flag should generate an interrupt request. If the TWIE bit is cleared, the application must poll the TWINT Flag in
order to detect actions on the TWI bus.
When the TWINT Flag is asserted, the TWI has finished an operation and awaits application
response. In this case, the TWI Status Register (TWSR) contains a value indicating the current
state of the TWI bus. The application software can then decide how the TWI should behave in
the next TWI bus cycle by manipulating the TWCR and TWDR Registers.
Figure 15-10 is a simple example of how the application can interface to the TWI hardware. In
this example, a Master wishes to transmit a single data byte to a Slave. This description is quite
abstract, a more detailed explanation follows later in this section. A simple code example implementing the desired behavior is also presented.
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ATtiny48/88
Application
Action
Figure 15-10. Interfacing the Application to the TWI in a Typical Transmission
1. Application
writes to TWCR to
initiate
transmission of
START
TWI
Hardware
Action
TWI bus
3. Check TWSR to see if START was
sent. Application loads SLA+W into
TWDR, and loads appropriate control
signals into TWCR, makin sure that
TWINT is written to one,
and TWSTA is written to zero.
START
2. TWINT set.
Status code indicates
START condition sent
SLA+W
5. Check TWSR to see if SLA+W was
sent and ACK received.
Application loads data into TWDR, and
loads appropriate control signals into
TWCR, making sure that TWINT is
written to one
A
4. TWINT set.
Status code indicates
SLA+W sent, ACK
received
Data
7. Check TWSR to see if data was sent
and ACK received.
Application loads appropriate control
signals to send STOP into TWCR,
making sure that TWINT is written to one
A
6. TWINT set.
Status code indicates
data sent, ACK received
STOP
Indicates
TWINT set
1. The first step in a TWI transmission is to transmit a START condition. This is done by
writing a specific value into TWCR, instructing the TWI hardware to transmit a START
condition. Which value to write is described later on. However, it is important that the
TWINT bit is set in the value written. Writing a one to TWINT clears the flag. The TWI
will not start any operation as long as the TWINT bit in TWCR is set. Immediately after
the application has cleared TWINT, the TWI will initiate transmission of the START
condition.
2. When the START condition has been transmitted, the TWINT Flag in TWCR is set, and
TWSR is updated with a status code indicating that the START condition has successfully been sent.
3. The application software should now examine the value of TWSR, to make sure that the
START condition was successfully transmitted. If TWSR indicates otherwise, the application software might take some special action, like calling an error routine. Assuming
that the status code is as expected, the application must load SLA+W into TWDR.
Remember that TWDR is used both for address and data. After TWDR has been
loaded with the desired SLA+W, a specific value must be written to TWCR, instructing
the TWI hardware to transmit the SLA+W present in TWDR. Which value to write is
described later on. However, it is important that the TWINT bit is set in the value written.
Writing a one to TWINT clears the flag. The TWI will not start any operation as long as
the TWINT bit in TWCR is set. Immediately after the application has cleared TWINT,
the TWI will initiate transmission of the address packet.
4. When the address packet has been transmitted, the TWINT Flag in TWCR is set, and
TWSR is updated with a status code indicating that the address packet has successfully been sent. The status code will also reflect whether a Slave acknowledged the
packet or not.
5. The application software should now examine the value of TWSR, to make sure that the
address packet was successfully transmitted, and that the value of the ACK bit was as
expected. If TWSR indicates otherwise, the application software might take some special action, like calling an error routine. Assuming that the status code is as expected,
the application must load a data packet into TWDR. Subsequently, a specific value
must be written to TWCR, instructing the TWI hardware to transmit the data packet
present in TWDR. Which value to write is described later on. However, it is important
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8008C–AVR–03/09
that the TWINT bit is set in the value written. Writing a one to TWINT clears the flag.
The TWI will not start any operation as long as the TWINT bit in TWCR is set. Immediately after the application has cleared TWINT, the TWI will initiate transmission of the
data packet.
6. When the data packet has been transmitted, the TWINT Flag in TWCR is set, and
TWSR is updated with a status code indicating that the data packet has successfully
been sent. The status code will also reflect whether a Slave acknowledged the packet
or not.
7. The application software should now examine the value of TWSR, to make sure that the
data packet was successfully transmitted, and that the value of the ACK bit was as
expected. If TWSR indicates otherwise, the application software might take some special action, like calling an error routine. Assuming that the status code is as expected,
the application must write a specific value to TWCR, instructing the TWI hardware to
transmit a STOP condition. Which value to write is described later on. However, it is
important that the TWINT bit is set in the value written. Writing a one to TWINT clears
the flag. The TWI will not start any operation as long as the TWINT bit in TWCR is set.
Immediately after the application has cleared TWINT, the TWI will initiate transmission
of the STOP condition. Note that TWINT is NOT set after a STOP condition has been
sent.
Even though this example is simple, it shows the principles involved in all TWI transmissions.
These can be summarized as follows:
• When the TWI has finished an operation and expects application response, the TWINT Flag
is set. The SCL line is pulled low until TWINT is cleared.
• When the TWINT Flag is set, the user must update all TWI Registers with the value relevant
for the next TWI bus cycle. As an example, TWDR must be loaded with the value to be
transmitted in the next bus cycle.
• After all TWI Register updates and other pending application software tasks have been
completed, TWCR is written. When writing TWCR, the TWINT bit should be set. Writing a
one to TWINT clears the flag. The TWI will then commence executing whatever operation
was specified by the TWCR setting.
In the following an assembly and C implementation of the example is given. Note that the code
below assumes that several definitions have been made, for example by using include-files.
Assembly Code Example
ldi r16,
(1<<TWINT)|(1<<TWSTA)|
1
in
r16,TWCR
sbrs r16,TWINT
Comments
TWCR = (1<<TWINT)|(1<<TWSTA)|
(1<<TWEN)
(1<<TWEN)
out TWCR, r16
wait1:
2
C Example
Send START condition
while (!(TWCR & (1<<TWINT)))
;
Wait for TWINT Flag set. This
indicates that the START
condition has been transmitted
rjmp wait1
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ATtiny48/88
Assembly Code Example
in
r16,TWSR
andi r16, 0xF8
cpi
3
TWDR, r16
ldi r16, (1<<TWINT) |
(1<<TWEN)
out TWCR, r16
wait2:
4
in
r16,TWCR
andi r16, 0xF8
cpi
r16, MT_SLA_ACK
brne ERROR
ldi r16, DATA
out
TWDR, r16
ldi r16, (1<<TWINT) |
(1<<TWEN)
out TWCR, r16
wait3:
6
in
r16,TWCR
andi r16, 0xF8
cpi
r16, MT_DATA_ACK
brne ERROR
ldi r16,
(1<<TWINT)|(1<<TWEN)|
(1<<TWSTO)
out
15.7
Comments
Check value of TWI Status
Register. Mask prescaler bits. If
status different from START go to
ERROR
TWDR = SLA_W;
TWCR = (1<<TWINT) |
(1<<TWEN);
while (!(TWCR & (1<<TWINT)))
;
if ((TWSR & 0xF8) !=
MT_SLA_ACK)
ERROR();
Load SLA_W into TWDR
Register. Clear TWINT bit in
TWCR to start transmission of
address
Wait for TWINT Flag set. This
indicates that the SLA+W has
been transmitted, and
ACK/NACK has been received.
Check value of TWI Status
Register. Mask prescaler bits. If
status different from
MT_SLA_ACK go to ERROR
TWDR = DATA;
TWCR = (1<<TWINT) |
(1<<TWEN);
Load DATA into TWDR Register.
Clear TWINT bit in TWCR to
start transmission of data
while (!(TWCR & (1<<TWINT)))
Wait for TWINT Flag set. This
indicates that the DATA has been
transmitted, and ACK/NACK has
been received.
;
sbrs r16,TWINT
rjmp wait3
in
r16,TWSR
7
ERROR();
sbrs r16,TWINT
rjmp wait2
in
r16,TWSR
5
if ((TWSR & 0xF8) != START)
r16, START
brne ERROR
ldi r16, SLA_W
out
C Example
if ((TWSR & 0xF8) !=
MT_DATA_ACK)
ERROR();
Check value of TWI Status
Register. Mask prescaler bits. If
status different from
MT_DATA_ACK go to ERROR
TWCR = (1<<TWINT)|(1<<TWEN)|
(1<<TWSTO);
Transmit STOP condition
TWCR, r16
Transmission Modes
The TWI can operate in one of four major modes. These are named Master Transmitter (MT),
Master Receiver (MR), Slave Transmitter (ST) and Slave Receiver (SR). Several of these
modes can be used in the same application. As an example, the TWI can use MT mode to write
data into a TWI EEPROM, MR mode to read the data back from the EEPROM. If other masters
are present in the system, some of these might transmit data to the TWI, and then SR mode
would be used. It is the application software that decides which modes are legal.
135
8008C–AVR–03/09
The following sections describe each of these modes. Possible status codes are described
along with figures detailing data transmission in each of the modes. These figures contain the
following abbreviations:
S: START condition
Rs: REPEATED START condition
R: Read bit (high level at SDA)
W: Write bit (low level at SDA)
A: Acknowledge bit (low level at SDA)
A: Not acknowledge bit (high level at SDA)
Data: 8-bit data byte
P: STOP condition
SLA: Slave Address
In Figure 15-12 to Figure 15-18, circles are used to indicate that the TWINT Flag is set. The
numbers in the circles show the status code held in TWSR, with the prescaler bits masked to
zero. At these points, actions must be taken by the application to continue or complete the TWI
transfer. The TWI transfer is suspended until the TWINT Flag is cleared by software.
When the TWINT Flag is set, the status code in TWSR is used to determine the appropriate software action. For each status code, the required software action and details of the following serial
transfer are given in Table 15-2 to Table 15-5. Note that the prescaler bits are masked to zero in
these tables.
15.7.1
Master Transmitter Mode
In the Master Transmitter mode, a number of data bytes are transmitted to a Slave Receiver
(see Figure 15-11). In order to enter a Master mode, a START condition must be transmitted.
The format of the following address packet determines whether Master Transmitter or Master
Receiver mode is to be entered. If SLA+W is transmitted, MT mode is entered, if SLA+R is transmitted, MR mode is entered. All the status codes mentioned in this section assume that the
prescaler bits are zero or are masked to zero.
Figure 15-11. Data Transfer in Master Transmitter Mode
VCC
Device 1
Device 2
MASTER
TRANSMITTER
SLAVE
RECEIVER
Device 3
........
Device n
R1
R2
SDA
SCL
136
ATtiny48/88
8008C–AVR–03/09
ATtiny48/88
A START condition is sent by writing the following value to TWCR:
TWCR
value
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
–
TWIE
1
X
1
0
X
1
0
X
TWEN must be set to enable the 2-wire Serial Interface, TWSTA must be written to one to transmit a START condition and TWINT must be written to one to clear the TWINT Flag. The TWI will
then test the 2-wire Serial Bus and generate a START condition as soon as the bus becomes
free. After a START condition has been transmitted, the TWINT Flag is set by hardware, and the
status code in TWSR will be 0x08 (see Table 15-2). In order to enter MT mode, SLA+W must be
transmitted. This is done by writing SLA+W to TWDR. Thereafter the TWINT bit should be
cleared (by writing it to one) to continue the transfer. This is accomplished by writing the following value to TWCR:
TWCR
value
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
–
TWIE
1
X
0
0
X
1
0
X
When SLA+W have been transmitted and an acknowledgement bit has been received, TWINT is
set again and a number of status codes in TWSR are possible. Possible status codes in Master
mode are 0x18, 0x20, or 0x38. The appropriate action to be taken for each of these status codes
is detailed in Table 15-2.
When SLA+W has been successfully transmitted, a data packet should be transmitted. This is
done by writing the data byte to TWDR. TWDR must only be written when TWINT is high. If not,
the access will be discarded, and the Write Collision bit (TWWC) will be set in the TWCR Register. After updating TWDR, the TWINT bit should be cleared (by writing it to one) to continue the
transfer. This is accomplished by writing the following value to TWCR:
TWCR
value
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
–
TWIE
1
X
0
0
X
1
0
X
This scheme is repeated until the last byte has been sent and the transfer is ended by generating a STOP condition or a repeated START condition. A STOP condition is generated by writing
the following value to TWCR:
TWCR
value
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
–
TWIE
1
X
0
1
X
1
0
X
A REPEATED START condition is generated by writing the following value to TWCR:
TWCR
value
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
–
TWIE
1
X
1
0
X
1
0
X
After a repeated START condition (state 0x10) the 2-wire Serial Interface can access the same
Slave again, or a new Slave without transmitting a STOP condition. Repeated START enables
137
8008C–AVR–03/09
the Master to switch between Slaves, Master Transmitter mode and Master Receiver mode without losing control of the bus.
Table 15-2.
Status Code
(TWSR)
Prescaler Bits
are 0
Status codes for Master Transmitter Mode
Application Software Response
Status of the 2-wire Serial Bus
and 2-wire Serial Interface
Hardware
To/from TWDR
0x08
A START condition has been
transmitted
0x10
A repeated START condition
has been transmitted
0x18
0x20
0x28
0x30
0x38
138
SLA+W has been transmitted;
ACK has been received
SLA+W has been transmitted;
NOT ACK has been received
Data byte has been transmitted;
ACK has been received
Data byte has been transmitted;
NOT ACK has been received
Arbitration lost in SLA+W or
data bytes
To TWCR
STA
STO
TWIN
T
TWE
A
Load SLA+W
0
0
1
X
SLA+W will be transmitted;
ACK or NOT ACK will be received
Load SLA+W or
0
0
1
X
Load SLA+R
0
0
1
X
SLA+W will be transmitted;
ACK or NOT ACK will be received
SLA+R will be transmitted;
Logic will switch to Master Receiver mode
Load data byte or
0
0
1
X
No TWDR action or
No TWDR action or
1
0
0
1
1
1
X
X
No TWDR action
1
1
1
X
Load data byte or
0
0
1
X
No TWDR action or
No TWDR action or
1
0
0
1
1
1
X
X
No TWDR action
1
1
1
X
Load data byte or
0
0
1
X
No TWDR action or
No TWDR action or
1
0
0
1
1
1
X
X
No TWDR action
1
1
1
X
Load data byte or
0
0
1
X
No TWDR action or
No TWDR action or
1
0
0
1
1
1
X
X
No TWDR action
1
1
1
X
No TWDR action or
0
0
1
X
No TWDR action
1
0
1
X
Next Action Taken by TWI Hardware
Data byte will be transmitted and ACK or NOT ACK will
be received
Repeated START will be transmitted
STOP condition will be transmitted and
TWSTO Flag will be reset
STOP condition followed by a START condition will be
transmitted and TWSTO Flag will be reset
Data byte will be transmitted and ACK or NOT ACK will
be received
Repeated START will be transmitted
STOP condition will be transmitted and
TWSTO Flag will be reset
STOP condition followed by a START condition will be
transmitted and TWSTO Flag will be reset
Data byte will be transmitted and ACK or NOT ACK will
be received
Repeated START will be transmitted
STOP condition will be transmitted and
TWSTO Flag will be reset
STOP condition followed by a START condition will be
transmitted and TWSTO Flag will be reset
Data byte will be transmitted and ACK or NOT ACK will
be received
Repeated START will be transmitted
STOP condition will be transmitted and
TWSTO Flag will be reset
STOP condition followed by a START condition will be
transmitted and TWSTO Flag will be reset
2-wire Serial Bus will be released and not addressed
Slave mode entered
A START condition will be transmitted when the bus
becomes free
ATtiny48/88
8008C–AVR–03/09
ATtiny48/88
Figure 15-12. Formats and States in the Master Transmitter Mode
MT
Successfull
transmission
to a slave
receiver
S
SLA
$08
W
A
DATA
$18
A
P
$28
Next transfer
started with a
repeated start
condition
RS
SLA
W
$10
Not acknowledge
received after the
slave address
A
R
P
$20
MR
Not acknowledge
received after a data
byte
A
P
$30
Arbitration lost in slave
address or data byte
A or A
Other master
continues
$38
Arbitration lost and
addressed as slave
A
$68
From master to slave
From slave to master
15.7.2
A or A
Other master
continues
$38
Other master
continues
$78
DATA
To corresponding
states in slave mode
$B0
A
n
Any number of data bytes
and their associated acknowledge bits
This number (contained in TWSR) corresponds
to a defined state of the 2-Wire Serial Bus. The
prescaler bits are zero or masked to zero
Master Receiver Mode
In the Master Receiver mode, a number of data bytes are received from a Slave Transmitter
(Slave see Figure 15-13). In order to enter a Master mode, a START condition must be transmitted. The format of the following address packet determines whether Master Transmitter or
Master Receiver mode is to be entered. If SLA+W is transmitted, MT mode is entered, if SLA+R
is transmitted, MR mode is entered. All the status codes mentioned in this section assume that
the prescaler bits are zero or are masked to zero.
139
8008C–AVR–03/09
Figure 15-13. Data Transfer in Master Receiver Mode
VCC
Device 1
Device 2
MASTER
RECEIVER
SLAVE
TRANSMITTER
Device 3
........
R1
Device n
R2
SDA
SCL
A START condition is sent by writing the following value to TWCR:
TWCR
value
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
–
TWIE
1
X
1
0
X
1
0
X
TWEN must be written to one to enable the 2-wire Serial Interface, TWSTA must be written to
one to transmit a START condition and TWINT must be set to clear the TWINT Flag. The TWI
will then test the 2-wire Serial Bus and generate a START condition as soon as the bus
becomes free. After a START condition has been transmitted, the TWINT Flag is set by hardware, and the status code in TWSR will be 0x08 (See Table 15-2). In order to enter MR mode,
SLA+R must be transmitted. This is done by writing SLA+R to TWDR. Thereafter the TWINT bit
should be cleared (by writing it to one) to continue the transfer. This is accomplished by writing
the following value to TWCR:
TWCR
value
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
–
TWIE
1
X
0
0
X
1
0
X
When SLA+R have been transmitted and an acknowledgement bit has been received, TWINT is
set again and a number of status codes in TWSR are possible. Possible status codes in Master
mode are 0x38, 0x40, or 0x48. The appropriate action to be taken for each of these status codes
is detailed in Table 15-3. Received data can be read from the TWDR Register when the TWINT
Flag is set high by hardware. This scheme is repeated until the last byte has been received.
After the last byte has been received, the MR should inform the ST by sending a NACK after the
last received data byte. The transfer is ended by generating a STOP condition or a repeated
START condition. A STOP condition is generated by writing the following value to TWCR:
TWCR
value
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
–
TWIE
1
X
0
1
X
1
0
X
A REPEATED START condition is generated by writing the following value to TWCR:
TWCR
value
140
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
–
TWIE
1
X
1
0
X
1
0
X
ATtiny48/88
8008C–AVR–03/09
ATtiny48/88
After a repeated START condition (state 0x10) the 2-wire Serial Interface can access the same
Slave again, or a new Slave without transmitting a STOP condition. Repeated START enables
the Master to switch between Slaves, Master Transmitter mode and Master Receiver mode without losing control over the bus.
Table 15-3.
Status Code
(TWSR)
Prescaler Bits
are 0
Status codes for Master Receiver Mode
Application Software Response
Status of the 2-wire Serial Bus
and 2-wire Serial Interface
Hardware
To TWCR
To/from TWDR
STA
STO
TWIN
T
TWE
A
Next Action Taken by TWI Hardware
0x08
A START condition has been
transmitted
Load SLA+R
0
0
1
X
SLA+R will be transmitted
ACK or NOT ACK will be received
0x10
A repeated START condition
has been transmitted
Load SLA+R or
0
0
1
X
Load SLA+W
0
0
1
X
SLA+R will be transmitted
ACK or NOT ACK will be received
SLA+W will be transmitted
Logic will switch to Master Transmitter mode
No TWDR action or
0
0
1
X
No TWDR action
1
0
1
X
No TWDR action or
0
0
1
0
No TWDR action
0
0
1
1
No TWDR action or
No TWDR action or
1
0
0
1
1
1
X
X
No TWDR action
1
1
1
X
0
0
1
0
0x38
0x40
0x48
Arbitration lost in SLA+R or
NOT ACK bit
SLA+R has been transmitted;
ACK has been received
SLA+R has been transmitted;
NOT ACK has been received
0x50
Data byte has been received;
ACK has been returned
Read data byte or
Read data byte
0
0
1
1
0x58
Data byte has been received;
NOT ACK has been returned
Read data byte or
Read data byte or
1
0
0
1
1
1
X
X
Read data byte
1
1
1
X
2-wire Serial Bus will be released and not addressed
Slave mode will be entered
A START condition will be transmitted when the bus
becomes free
Data byte will be received and NOT ACK will be
returned
Data byte will be received and ACK will be returned
Repeated START will be transmitted
STOP condition will be transmitted and TWSTO Flag
will be reset
STOP condition followed by a START condition will be
transmitted and TWSTO Flag will be reset
Data byte will be received and NOT ACK will be
returned
Data byte will be received and ACK will be returned
Repeated START will be transmitted
STOP condition will be transmitted and TWSTO Flag
will be reset
STOP condition followed by a START condition will be
transmitted and TWSTO Flag will be reset
141
8008C–AVR–03/09
Figure 15-14. Formats and States in the Master Receiver Mode
MR
Successfull
reception
from a slave
receiver
S
SLA
$08
R
A
DATA
A
$40
DATA
$50
A
P
$58
Next transfer
started with a
repeated start
condition
RS
SLA
R
$10
Not acknowledge
received after the
slave address
A
W
P
$48
MT
Arbitration lost in slave
address or data byte
A or A
Other master
continues
A
$38
Arbitration lost and
addressed as slave
A
$68
From master to slave
15.7.3
$38
Other master
continues
$78
DATA
From slave to master
Other master
continues
To corresponding
states in slave mode
$B0
A
n
Any number of data bytes
and their associated acknowledge bits
This number (contained in TWSR) corresponds
to a defined state of the 2-Wire Serial Bus. The
prescaler bits are zero or masked to zero
Slave Receiver Mode
In the Slave Receiver mode, a number of data bytes are received from a Master Transmitter
(see Figure 15-15). All the status codes mentioned in this section assume that the prescaler bits
are zero or are masked to zero.
Figure 15-15. Data transfer in Slave Receiver mode
VCC
Device 1
Device 2
SLAVE
RECEIVER
MASTER
TRANSMITTER
Device 3
........
Device n
R1
R2
SDA
SCL
142
ATtiny48/88
8008C–AVR–03/09
ATtiny48/88
To initiate the Slave Receiver mode, TWAR and TWCR must be initialized as follows:
TWAR
TWA6
TWA5
value
TWA4
TWA3
TWA2
TWA1
TWA0
TWGCE
Device’s Own Slave Address
The upper 7 bits are the address to which the 2-wire Serial Interface will respond when
addressed by a Master. If the LSB is set, the TWI will respond to the general call address (0x00),
otherwise it will ignore the general call address.
TWCR
value
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
–
TWIE
0
1
0
0
0
1
0
X
TWEN must be written to one to enable the TWI. The TWEA bit must be written to one to enable
the acknowledgement of the device’s own slave address or the general call address. TWSTA
and TWSTO must be written to zero.
When TWAR and TWCR have been initialized, the TWI waits until it is addressed by its own
slave address (or the general call address if enabled) followed by the data direction bit. If the
direction bit is “0” (write), the TWI will operate in SR mode, otherwise ST mode is entered. After
its own slave address and the write bit have been received, the TWINT Flag is set and a valid
status code can be read from TWSR. The status code is used to determine the appropriate software action. The appropriate action to be taken for each status code is detailed in Table 15-4.
The Slave Receiver mode may also be entered if arbitration is lost while the TWI is in the Master
mode (see states 0x68 and 0x78).
If the TWEA bit is reset during a transfer, the TWI will return a “Not Acknowledge” (“1”) to SDA
after the next received data byte. This can be used to indicate that the Slave is not able to
receive any more bytes. While TWEA is zero, the TWI does not acknowledge its own slave
address. However, the 2-wire Serial Bus is still monitored and address recognition may resume
at any time by setting TWEA. This implies that the TWEA bit may be used to temporarily isolate
the TWI from the 2-wire Serial Bus.
In all sleep modes other than Idle mode, the clock system to the TWI is turned off. If the TWEA
bit is set, the interface can still acknowledge its own slave address or the general call address by
using the 2-wire Serial Bus clock as a clock source. The part will then wake up from sleep and
the TWI will hold the SCL clock low during the wake up and until the TWINT Flag is cleared (by
writing it to one). Further data reception will be carried out as normal, with the AVR clocks running as normal. Observe that if the AVR is set up with a long start-up time, the SCL line may be
held low for a long time, blocking other data transmissions.
Note that the 2-wire Serial Interface Data Register – TWDR does not reflect the last byte present
on the bus when waking up from these Sleep modes.
143
8008C–AVR–03/09
Table 15-4.
Status Code
(TWSR)
Prescaler Bits
are 0
Status Codes for Slave Receiver Mode
Application Software Response
Status of the 2-wire Serial Bus
and 2-wire Serial Interface Hardware
To TWCR
To/from TWDR
STA
STO
TWIN
T
TWE
A
No TWDR action or
X
0
1
0
0x60
Own SLA+W has been received;
ACK has been returned
No TWDR action
X
0
1
1
0x68
Arbitration lost in SLA+R/W as
Master; own SLA+W has been
received; ACK has been returned
No TWDR action or
X
0
1
0
No TWDR action
X
0
1
1
0x70
General call address has been
received; ACK has been returned
No TWDR action or
X
0
1
0
No TWDR action
X
0
1
1
0x78
Arbitration lost in SLA+R/W as
Master; General call address has
been received; ACK has been
returned
No TWDR action or
X
0
1
0
No TWDR action
X
0
1
1
0x80
Previously addressed with own
SLA+W; data has been received;
ACK has been returned
Read data byte or
X
0
1
0
Read data byte
X
0
1
1
0x88
Previously addressed with own
SLA+W; data has been received;
NOT ACK has been returned
Read data byte or
0
0
1
0
Read data byte or
0
0
1
1
Read data byte or
1
0
1
0
Read data byte
1
0
1
1
0x90
Previously addressed with
general call; data has been received; ACK has been returned
Read data byte or
X
0
1
0
Read data byte
X
0
1
1
0x98
Previously addressed with
general call; data has been
received; NOT ACK has been
returned
Read data byte or
0
0
1
0
Read data byte or
0
0
1
1
Read data byte or
1
0
1
0
Read data byte
1
0
1
1
No action
0
0
1
0
0
0
1
1
1
0
1
0
1
0
1
1
0xA0
144
A STOP condition or repeated
START condition has been
received while still addressed as
Slave
Next Action Taken by TWI Hardware
Data byte will be received and NOT ACK will be
returned
Data byte will be received and ACK will be returned
Data byte will be received and NOT ACK will be
returned
Data byte will be received and ACK will be returned
Data byte will be received and NOT ACK will be
returned
Data byte will be received and ACK will be returned
Data byte will be received and NOT ACK will be
returned
Data byte will be received and ACK will be returned
Data byte will be received and NOT ACK will be
returned
Data byte will be received and ACK will be returned
Switched to the not addressed Slave mode;
no recognition of own SLA or GCA
Switched to the not addressed Slave mode;
own SLA will be recognized;
GCA will be recognized if TWGCE = “1”
Switched to the not addressed Slave mode;
no recognition of own SLA or GCA;
a START condition will be transmitted when the bus
becomes free
Switched to the not addressed Slave mode;
own SLA will be recognized;
GCA will be recognized if TWGCE = “1”;
a START condition will be transmitted when the bus
becomes free
Data byte will be received and NOT ACK will be
returned
Data byte will be received and ACK will be returned
Switched to the not addressed Slave mode;
no recognition of own SLA or GCA
Switched to the not addressed Slave mode;
own SLA will be recognized;
GCA will be recognized if TWGCE = “1”
Switched to the not addressed Slave mode;
no recognition of own SLA or GCA;
a START condition will be transmitted when the bus
becomes free
Switched to the not addressed Slave mode;
own SLA will be recognized;
GCA will be recognized if TWGCE = “1”;
a START condition will be transmitted when the bus
becomes free
Switched to the not addressed Slave mode;
no recognition of own SLA or GCA
Switched to the not addressed Slave mode;
own SLA will be recognized;
GCA will be recognized if TWGCE = “1”
Switched to the not addressed Slave mode;
no recognition of own SLA or GCA;
a START condition will be transmitted when the bus
becomes free
Switched to the not addressed Slave mode;
own SLA will be recognized;
GCA will be recognized if TWGCE = “1”;
a START condition will be transmitted when the bus
becomes free
ATtiny48/88
8008C–AVR–03/09
ATtiny48/88
Figure 15-16. Formats and States in the Slave Receiver Mode
Reception of the own
slave address and one or
more data bytes. All are
acknowledged
S
SLA
W
A
DATA
$60
A
DATA
$80
Last data byte received
is not acknowledged
A
P or S
$80
$A0
A
P or S
$88
Arbitration lost as master
and addressed as slave
A
$68
Reception of the general call
address and one or more data
bytes
General Call
A
DATA
$70
A
DATA
$90
Last data byte received is
not acknowledged
A
P or S
$90
$A0
A
P or S
$98
Arbitration lost as master and
addressed as slave by general call
A
$78
DATA
From master to slave
From slave to master
15.7.4
A
n
Any number of data bytes
and their associated acknowledge bits
This number (contained in TWSR) corresponds
to a defined state of the 2-Wire Serial Bus. The
prescaler bits are zero or masked to zero
Slave Transmitter Mode
In the Slave Transmitter mode, a number of data bytes are transmitted to a Master Receiver
(see Figure 15-17). All the status codes mentioned in this section assume that the prescaler bits
are zero or are masked to zero.
Figure 15-17. Data Transfer in Slave Transmitter Mode
VCC
Device 1
Device 2
SLAVE
TRANSMITTER
MASTER
RECEIVER
Device 3
........
Device n
R1
R2
SDA
SCL
145
8008C–AVR–03/09
To initiate the Slave Transmitter mode, TWAR and TWCR must be initialized as follows:
TWAR
TWA6
TWA5
value
TWA4
TWA3
TWA2
TWA1
TWA0
TWGCE
Device’s Own Slave Address
The upper seven bits are the address to which the 2-wire Serial Interface will respond when
addressed by a Master. If the LSB is set, the TWI will respond to the general call address (0x00),
otherwise it will ignore the general call address.
TWCR
value
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
–
TWIE
0
1
0
0
0
1
0
X
TWEN must be written to one to enable the TWI. The TWEA bit must be written to one to enable
the acknowledgement of the device’s own slave address or the general call address. TWSTA
and TWSTO must be written to zero.
When TWAR and TWCR have been initialized, the TWI waits until it is addressed by its own
slave address (or the general call address if enabled) followed by the data direction bit. If the
direction bit is “1” (read), the TWI will operate in ST mode, otherwise SR mode is entered. After
its own slave address and the write bit have been received, the TWINT Flag is set and a valid
status code can be read from TWSR. The status code is used to determine the appropriate software action. The appropriate action to be taken for each status code is detailed in Table 15-5.
The Slave Transmitter mode may also be entered if arbitration is lost while the TWI is in the
Master mode (see state 0xB0).
If the TWEA bit is written to zero during a transfer, the TWI will transmit the last byte of the transfer. State 0xC0 or state 0xC8 will be entered, depending on whether the Master Receiver
transmits a NACK or ACK after the final byte. The TWI is switched to the not addressed Slave
mode, and will ignore the Master if it continues the transfer. Thus the Master Receiver receives
all “1” as serial data. State 0xC8 is entered if the Master demands additional data bytes (by
transmitting ACK), even though the Slave has transmitted the last byte (TWEA zero and expecting NACK from the Master).
While TWEA is zero, the TWI does not respond to its own slave address. However, the 2-wire
Serial Bus is still monitored and address recognition may resume at any time by setting TWEA.
This implies that the TWEA bit may be used to temporarily isolate the TWI from the 2-wire Serial
Bus.
In all sleep modes other than Idle mode, the clock system to the TWI is turned off. If the TWEA
bit is set, the interface can still acknowledge its own slave address or the general call address by
using the 2-wire Serial Bus clock as a clock source. The part will then wake up from sleep and
the TWI will hold the SCL clock will low during the wake up and until the TWINT Flag is cleared
(by writing it to one). Further data transmission will be carried out as normal, with the AVR clocks
running as normal. Observe that if the AVR is set up with a long start-up time, the SCL line may
be held low for a long time, blocking other data transmissions.
Note that the 2-wire Serial Interface Data Register – TWDR does not reflect the last byte present
on the bus when waking up from these sleep modes.
146
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ATtiny48/88
Table 15-5.
Status Code
(TWSR)
Prescaler
Bits
are 0
0xA8
0xB0
0xB8
0xC0
0xC8
Status Codes for Slave Transmitter Mode
Application Software Response
Status of the 2-wire Serial Bus
and 2-wire Serial Interface Hardware
To TWCR
To/from TWDR
STA
STO
TWIN
T
TWE
A
Load data byte or
X
0
1
0
Load data byte
X
0
1
1
Arbitration lost in SLA+R/W as
Master; own SLA+R has been
received; ACK has been returned
Load data byte or
X
0
1
0
Load data byte
X
0
1
1
Data byte in TWDR has been
transmitted; ACK has been
received
Load data byte or
X
0
1
0
Load data byte
X
0
1
1
Data byte in TWDR has been
transmitted; NOT ACK has been
received
No TWDR action or
0
0
1
0
No TWDR action or
0
0
1
1
No TWDR action or
1
0
1
0
No TWDR action
1
0
1
1
No TWDR action or
0
0
1
0
No TWDR action or
0
0
1
1
No TWDR action or
1
0
1
0
No TWDR action
1
0
1
1
Own SLA+R has been received;
ACK has been returned
Last data byte in TWDR has been
transmitted (TWEA = “0”); ACK
has been received
Next Action Taken by TWI Hardware
Last data byte will be transmitted and NOT ACK should
be received
Data byte will be transmitted and ACK should be received
Last data byte will be transmitted and NOT ACK should
be received
Data byte will be transmitted and ACK should be received
Last data byte will be transmitted and NOT ACK should
be received
Data byte will be transmitted and ACK should be received
Switched to the not addressed Slave mode;
no recognition of own SLA or GCA
Switched to the not addressed Slave mode;
own SLA will be recognized;
GCA will be recognized if TWGCE = “1”
Switched to the not addressed Slave mode;
no recognition of own SLA or GCA;
a START condition will be transmitted when the bus
becomes free
Switched to the not addressed Slave mode;
own SLA will be recognized;
GCA will be recognized if TWGCE = “1”;
a START condition will be transmitted when the bus
becomes free
Switched to the not addressed Slave mode;
no recognition of own SLA or GCA
Switched to the not addressed Slave mode;
own SLA will be recognized;
GCA will be recognized if TWGCE = “1”
Switched to the not addressed Slave mode;
no recognition of own SLA or GCA;
a START condition will be transmitted when the bus
becomes free
Switched to the not addressed Slave mode;
own SLA will be recognized;
GCA will be recognized if TWGCE = “1”;
a START condition will be transmitted when the bus
becomes free
147
8008C–AVR–03/09
Figure 15-18. Formats and States in the Slave Transmitter Mode
Reception of the own
slave address and one or
more data bytes
S
SLA
R
A
DATA
$A8
Arbitration lost as master
and addressed as slave
A
DATA
$B8
A
P or S
$C0
A
$B0
Last data byte transmitted.
Switched to not addressed
slave (TWEA = '0')
A
All 1's
P or S
$C8
DATA
From master to slave
From slave to master
15.7.5
Any number of data bytes
and their associated acknowledge bits
A
This number (contained in TWSR) corresponds
to a defined state of the 2-Wire Serial Bus. The
prescaler bits are zero or masked to zero
n
Miscellaneous States
There are two status codes that do not correspond to a defined TWI state, see Table 15-6.
Status 0xF8 indicates that no relevant information is available because the TWINT Flag is not
set. This occurs between other states, and when the TWI is not involved in a serial transfer.
Status 0x00 indicates that a bus error has occurred during a 2-wire Serial Bus transfer. A bus
error occurs when a START or STOP condition occurs at an illegal position in the format frame.
Examples of such illegal positions are during the serial transfer of an address byte, a data byte,
or an acknowledge bit. When a bus error occurs, TWINT is set. To recover from a bus error, the
TWSTO Flag must set and TWINT must be cleared by writing a logic one to it. This causes the
TWI to enter the not addressed Slave mode and to clear the TWSTO Flag (no other bits in
TWCR are affected). The SDA and SCL lines are released, and no STOP condition is
transmitted.
Table 15-6.
Miscellaneous States
Status Code
(TWSR)
Prescaler Bits
are 0
Status of the 2-wire Serial Bus
and 2-wire Serial Interface
Hardware
Application Software Response
To TWCR
To/from TWDR
0xF8
No relevant state information
available; TWINT = “0”
No TWDR action
0x00
Bus error due to an illegal
START or STOP condition
No TWDR action
148
STA
STO
TWIN
T
TWE
A
No TWCR action
0
1
1
Next Action Taken by TWI Hardware
Wait or proceed current transfer
X
Only the internal hardware is affected, no STOP condition is sent on the bus. In all cases, the bus is released
and TWSTO is cleared.
ATtiny48/88
8008C–AVR–03/09
ATtiny48/88
15.7.6
Combining Several TWI Modes
In some cases, several TWI modes must be combined in order to complete the desired action.
Consider for example reading data from a serial EEPROM. Typically, such a transfer involves
the following steps:
1. The transfer must be initiated.
2. The EEPROM must be instructed what location should be read.
3. The reading must be performed.
4. The transfer must be finished.
Note that data is transmitted both from Master to Slave and vice versa. The Master must instruct
the Slave what location it wants to read, requiring the use of the MT mode. Subsequently, data
must be read from the Slave, implying the use of the MR mode. Thus, the transfer direction must
be changed. The Master must keep control of the bus during all these steps, and the steps
should be carried out as an atomical operation. If this principle is violated in a multi master system, another Master can alter the data pointer in the EEPROM between steps 2 and 3, and the
Master will read the wrong data location. Such a change in transfer direction is accomplished by
transmitting a REPEATED START between the transmission of the address byte and reception
of the data. After a REPEATED START, the Master keeps ownership of the bus. The following
figure shows the flow in this transfer.
Figure 15-19. Combining Several TWI Modes to Access a Serial EEPROM
Master Transmitter
S
SLA+W
A
ADDRESS
S = START
Transmitted from master to slave
15.8
Master Receiver
A
Rs
SLA+R
A
Rs = REPEATED START
DATA
A
P
P = STOP
Transmitted from slave to master
Multi-master Systems and Arbitration
If multiple masters are connected to the same bus, transmissions may be initiated simultaneously by one or more of them. The TWI standard ensures that such situations are handled in
such a way that one of the masters will be allowed to proceed with the transfer, and that no data
will be lost in the process. An example of an arbitration situation is depicted below, where two
masters are trying to transmit data to a Slave Receiver.
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8008C–AVR–03/09
Figure 15-20. An Arbitration Example
VCC
Device 1
Device 2
Device 3
MASTER
TRANSMITTER
MASTER
TRANSMITTER
SLAVE
RECEIVER
........
Device n
R1
R2
SDA
SCL
Several different scenarios may arise during arbitration, as described below:
• Two or more masters are performing identical communication with the same Slave. In this
case, neither the Slave nor any of the masters will know about the bus contention.
• Two or more masters are accessing the same Slave with different data or direction bit. In this
case, arbitration will occur, either in the READ/WRITE bit or in the data bits. The masters
trying to output a one on SDA while another Master outputs a zero will lose the arbitration.
Losing masters will switch to not addressed Slave mode or wait until the bus is free and
transmit a new START condition, depending on application software action.
• Two or more masters are accessing different slaves. In this case, arbitration will occur in the
SLA bits. Masters trying to output a one on SDA while another Master outputs a zero will lose
the arbitration. Masters losing arbitration in SLA will switch to Slave mode to check if they are
being addressed by the winning Master. If addressed, they will switch to SR or ST mode,
depending on the value of the READ/WRITE bit. If they are not being addressed, they will
switch to not addressed Slave mode or wait until the bus is free and transmit a new START
condition, depending on application software action.
This is summarized in Figure 15-21. Possible status values are given in circles.
Figure 15-21. Possible Status Codes Caused by Arbitration
START
SLA
Data
Arbitration lost in SLA
Own
Address / General Call
received
No
STOP
Arbitration lost in Data
38
TWI bus will be released and not addressed slave mode will be entered
A START condition will be transmitted when the bus becomes free
Yes
Direction
Write
68/78
Read
B0
150
Data byte will be received and NOT ACK will be returned
Data byte will be received and ACK will be returned
Last data byte will be transmitted and NOT ACK should be received
Data byte will be transmitted and ACK should be received
ATtiny48/88
8008C–AVR–03/09
ATtiny48/88
15.9
15.9.1
Register Description
TWBR – TWI Bit Rate Register
Bit
7
6
5
4
3
2
1
0
TWBR7
TWBR6
TWBR5
TWBR4
TWBR3
TWBR2
TWBR1
TWBR0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
TWBR
• Bits 7..0 – TWI Bit Rate Register
TWBR selects the division factor for the bit rate generator. The bit rate generator is a frequency
divider which generates the SCL clock frequency in the Master modes. See “Bit Rate Generator
Unit” on page 130 for calculating bit rates.
If the TWI operates in Master mode TWBR must be set to 10, or higher.
15.9.2
TWCR – TWI Control Register
Bit
7
6
5
4
3
2
1
0
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
–
TWIE
Read/Write
R/W
R/W
R/W
R/W
R
R/W
R
R/W
Initial Value
0
0
0
0
0
0
0
0
TWCR
The TWCR is used to control the operation of the TWI. It is used to enable the TWI, to initiate a
Master access by applying a START condition to the bus, to generate a Receiver acknowledge,
to generate a stop condition, and to control halting of the bus while the data to be written to the
bus are written to the TWDR. It also indicates a write collision if data is attempted written to
TWDR while the register is inaccessible.
• Bit 7 – TWINT: TWI Interrupt Flag
This bit is set by hardware when the TWI has finished its current job and expects application
software response. If the I-bit in SREG and TWIE in TWCR are set, the MCU will jump to the
TWI Interrupt Vector. While the TWINT Flag is set, the SCL low period is stretched. The TWINT
Flag must be cleared by software by writing a logic one to it. Note that this flag is not automatically cleared by hardware when executing the interrupt routine. Also note that clearing this flag
starts the operation of the TWI, so all accesses to the TWI Address Register (TWAR), TWI Status Register (TWSR), and TWI Data Register (TWDR) must be complete before clearing this
flag.
• Bit 6 – TWEA: TWI Enable Acknowledge Bit
The TWEA bit controls the generation of the acknowledge pulse. If the TWEA bit is written to
one, the ACK pulse is generated on the TWI bus if the following conditions are met:
1. The device’s own slave address has been received.
2. A general call has been received, while the TWGCE bit in the TWAR is set.
3. A data byte has been received in Master Receiver or Slave Receiver mode.
By writing the TWEA bit to zero, the device can be virtually disconnected from the 2-wire Serial
Bus temporarily. Address recognition can then be resumed by writing the TWEA bit to one
again.
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8008C–AVR–03/09
• Bit 5 – TWSTA: TWI START Condition Bit
The application writes the TWSTA bit to one when it desires to become a Master on the 2-wire
Serial Bus. The TWI hardware checks if the bus is available, and generates a START condition
on the bus if it is free. However, if the bus is not free, the TWI waits until a STOP condition is
detected, and then generates a new START condition to claim the bus Master status. TWSTA
must be cleared by software when the START condition has been transmitted.
• Bit 4 – TWSTO: TWI STOP Condition Bit
Writing the TWSTO bit to one in Master mode will generate a STOP condition on the 2-wire
Serial Bus. When the STOP condition is executed on the bus, the TWSTO bit is cleared automatically. In Slave mode, setting the TWSTO bit can be used to recover from an error condition.
This will not generate a STOP condition, but the TWI returns to a well-defined unaddressed
Slave mode and releases the SCL and SDA lines to a high impedance state.
• Bit 3 – TWWC: TWI Write Collision Flag
The TWWC bit is set when attempting to write to the TWI Data Register – TWDR when TWINT is
low. This flag is cleared by writing the TWDR Register when TWINT is high.
• Bit 2 – TWEN: TWI Enable Bit
The TWEN bit enables TWI operation and activates the TWI interface. When TWEN is written to
one, the TWI takes control over the I/O pins connected to the SCL and SDA pins, enabling the
slew-rate limiters and spike filters. If this bit is written to zero, the TWI is switched off and all TWI
transmissions are terminated, regardless of any ongoing operation.
• Bit 1 – Res: Reserved Bit
This bit is a reserved bit and will always read as zero.
• Bit 0 – TWIE: TWI Interrupt Enable
When this bit is written to one, and the I-bit in SREG is set, the TWI interrupt request will be activated for as long as the TWINT Flag is high.
15.9.3
TWSR – TWI Status Register
Bit
7
6
5
4
3
2
1
0
TWS7
TWS6
TWS5
TWS4
TWS3
–
TWPS1
TWPS0
Read/Write
R
R
R
R
R
R
R/W
R/W
Initial Value
1
1
1
1
1
0
0
0
TWSR
• Bits 7..3 – TWS: TWI Status
These 5 bits reflect the status of the TWI logic and the 2-wire Serial Bus. The different status
codes are described later in this section. Note that the value read from TWSR contains both the
5-bit status value and the 2-bit prescaler value. The application designer should mask the prescaler bits to zero when checking the Status bits. This makes status checking independent of
prescaler setting. This approach is used in this datasheet, unless otherwise noted.
• Bit 2 – Res: Reserved Bit
This bit is reserved and will always read as zero.
152
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ATtiny48/88
• Bits 1..0 – TWPS: TWI Prescaler Bits
These bits can be read and written, and control the bit rate prescaler.
Table 15-7.
TWI Bit Rate Prescaler
TWPS1
TWPS0
Prescaler Value
0
0
1
0
1
4
1
0
16
1
1
64
To calculate bit rates, see “Bit Rate Generator Unit” on page 130. The value of TWPS1..0 is
used in the equation.
15.9.4
TWDR – TWI Data Register
Bit
7
6
5
4
3
2
1
0
TWD7
TWD6
TWD5
TWD4
TWD3
TWD2
TWD1
TWD0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
1
1
1
1
1
1
1
1
TWDR
In Transmit mode, TWDR contains the next byte to be transmitted. In Receive mode, the TWDR
contains the last byte received. It is writable while the TWI is not in the process of shifting a byte.
This occurs when the TWI Interrupt Flag (TWINT) is set by hardware. Note that the Data Register cannot be initialized by the user before the first interrupt occurs. The data in TWDR remains
stable as long as TWINT is set. While data is shifted out, data on the bus is simultaneously
shifted in. TWDR always contains the last byte present on the bus, except after a wake up from
a sleep mode by the TWI interrupt. In this case, the contents of TWDR is undefined. In the case
of a lost bus arbitration, no data is lost in the transition from Master to Slave. Handling of the
ACK bit is controlled automatically by the TWI logic, the CPU cannot access the ACK bit directly.
• Bits 7..0 – TWD: TWI Data Register
These eight bits constitute the next data byte to be transmitted, or the latest data byte received
on the 2-wire Serial Bus.
15.9.5
TWAR – TWI (Slave) Address Register
Bit
7
6
5
4
3
2
1
0
TWA6
TWA5
TWA4
TWA3
TWA2
TWA1
TWA0
TWGCE
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
1
1
1
1
1
1
1
0
TWAR
The TWAR should be loaded with the 7-bit Slave address (in the seven most significant bits of
TWAR) to which the TWI will respond when programmed as a Slave Transmitter or Receiver,
and not needed in the Master modes. In multi master systems, TWAR must be set in masters
which can be addressed as Slaves by other Masters.
The LSB of TWAR is used to enable recognition of the general call address (0x00). There is an
associated address comparator that looks for the slave address (or general call address if
enabled) in the received serial address. If a match is found, an interrupt request is generated.
• Bits 7..1 – TWA: TWI (Slave) Address Register
These seven bits constitute the slave address of the TWI unit.
153
8008C–AVR–03/09
• Bit 0 – TWGCE: TWI General Call Recognition Enable Bit
If set, this bit enables the recognition of a General Call given over the 2-wire Serial Bus.
15.9.6
TWAMR – TWI (Slave) Address Mask Register–
Bit
7
6
5
4
3
2
1
TWAM[6:0]
0
–
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
Initial Value
0
0
0
0
0
0
0
0
TWAMR
• Bits 7..1 – TWAM: TWI Address Mask
The TWAMR can be loaded with a 7-bit Salve Address mask. Each of the bits in TWAMR can
mask (disable) the corresponding address bits in the TWI Address Register (TWAR). If the mask
bit is set to one then the address match logic ignores the compare between the incoming
address bit and the corresponding bit in TWAR. Figure 15-22 shown the address match logic in
detail.
Figure 15-22. TWI Address Match Logic, Block Diagram
TWAR0
Address
Match
Address
Bit 0
TWAMR0
Address Bit Comparator 0
Address Bit Comparator 6..1
• Bit 0 – Res: Reserved Bit
These bits are reserved and will always read zero.
15.9.7
TWHSR – TWI High Speed Register
Bit
7
6
5
4
3
2
1
0
–
–
–
–
–
–
–
TWHS
Read/Write
R
R
R
R
R
R
R
R/W
Initial Value
0
0
0
0
0
0
0
0
TWHSR
• Bits 7..1 – Res: Reserved Bits
These bits are reserved and will always read zero.
• Bit 0 – TWHS: TWI High Speed Enable
TWI High Speed mode is enabled by writing this bit to one. In this mode the undivided system
clock is selected as TWI clock. See Figure 6-1 on page 25.
The TWI High Speed mode requires that the high-speed clock, clkTWIHS, is exactly two times
higher than the I/O clock frequency, clkI/O. This means the user must make sure the I/O clock
frequency clkI/O is scaled down by a factor of 2. For example, if the internal 8 MHz oscillator has
been selected as source clock, the user must set the prescaler to scale the system clock (and,
hence, the I/O clock) down to 4 MHz. For more information about clock systems, see “Clock
Systems and their Distribution” on page 25.
154
ATtiny48/88
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ATtiny48/88
16. Analog Comparator
The Analog Comparator compares the input values on the positive pin AIN0 and negative pin
AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin
AIN1, the Analog Comparator output, ACO, is set. The comparator’s output can be set to trigger
the Timer/Counter1 Input Capture function. In addition, the comparator can trigger a separate
interrupt, exclusive to the Analog Comparator. The user can select Interrupt triggering on comparator output rise, fall or toggle. A block diagram of the comparator and its surrounding logic is
shown in Figure 16-1.
The ADC Power Reduction bit, PRADC, must be disabled in order to use the ADC input multiplexer. This is done by clearing the PRADC bit in the Power Reduction Register, PRR. See
“PRR – Power Reduction Register” on page 37 for more details.
Figure 16-1. Analog Comparator Block Diagram(2)
BANDGAP
REFERENCE
ACBG
ACME
ADEN
ADC MULTIPLEXER
OUTPUT (1)
Notes:
16.1
1. See Table 16-1 on page 155.
2. Refer to Figure 1-1 on page 2 and Table 10-11 on page 70 for Analog Comparator pin
placement.
Analog Comparator Multiplexed Input
It is possible to select any of the ADC7..0 pins to replace the negative input to the Analog Comparator. The ADC multiplexer is used to select this input, and consequently, the ADC must be
switched off to utilize this feature. If the Analog Comparator Multiplexer Enable bit (ACME in
ADCSRB) is set and the ADC is switched off (ADEN in ADCSRA is zero), MUX2..0 in ADMUX
select the input pin to replace the negative input to the Analog Comparator, as shown in Table
16-1. If ACME is cleared or ADEN is set, AIN1 is applied to the negative input to the Analog
Comparator.
Table 16-1.
Analog Comparator Multiplexed Input
ACME
ADEN
MUX2..0
Analog Comparator Negative Input
0
x
xxx
AIN1
1
1
xxx
AIN1
1
0
000
ADC0
1
0
001
ADC1
155
8008C–AVR–03/09
Table 16-1.
16.2
16.2.1
Analog Comparator Multiplexed Input
ACME
ADEN
MUX2..0
Analog Comparator Negative Input
1
0
010
ADC2
1
0
011
ADC3
1
0
100
ADC4
1
0
101
ADC5
1
0
110
ADC6
1
0
111
ADC7
Register Description
ADCSRB – ADC Control and Status Register B
Bit
7
6
5
4
3
2
1
0
–
ACME
–
–
–
ADTS2
ADTS1
ADTS0
Read/Write
R
R/W
R
R
R
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
ADCSRB
• Bit 6 – ACME: Analog Comparator Multiplexer Enable
When this bit is written logic one and the ADC is switched off (ADEN in ADCSRA is zero), the
ADC multiplexer selects the negative input to the Analog Comparator. When this bit is written
logic zero, AIN1 is applied to the negative input of the Analog Comparator. For a detailed
description of this bit, see “Analog Comparator Multiplexed Input” on page 155.
16.2.2
ACSR – Analog Comparator Control and Status Register
Bit
7
6
5
4
3
2
1
0
ACD
ACBG
ACO
ACI
ACIE
ACIC
ACIS1
ACIS0
Read/Write
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
N/A
0
0
0
0
0
ACSR
• Bit 7 – ACD: Analog Comparator Disable
When this bit is written logic one, the power to the Analog Comparator is switched off. This bit
can be set at any time to turn off the Analog Comparator. This will reduce power consumption in
Active and Idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be
disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is
changed.
• Bit 6 – ACBG: Analog Comparator Bandgap Select
When this bit is set, a fixed internal bandgap reference voltage replaces the positive input to the
Analog Comparator. When this bit is cleared, AIN0 is applied to the positive input of the Analog
Comparator. See “Internal Voltage Reference” on page 42.
• Bit 5 – ACO: Analog Comparator Output
The output of the Analog Comparator is synchronized and then directly connected to ACO. The
synchronization introduces a delay of 1 – 2 clock cycles.
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• Bit 4 – ACI: Analog Comparator Interrupt Flag
This bit is set by hardware when a comparator output event triggers the interrupt mode defined
by ACIS1 and ACIS0. The Analog Comparator interrupt routine is executed if the ACIE bit is set
and the I-bit in SREG is set. ACI is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag.
• Bit 3 – ACIE: Analog Comparator Interrupt Enable
When the ACIE bit is written logic one and the I-bit in the Status Register is set, the Analog Comparator interrupt is activated. When written logic zero, the interrupt is disabled.
• Bit 2 – ACIC: Analog Comparator Input Capture Enable
When written logic one, this bit enables the input capture function in Timer/Counter1 to be triggered by the Analog Comparator. The comparator output is in this case directly connected to the
input capture front-end logic, making the comparator utilize the noise canceler and edge select
features of the Timer/Counter1 Input Capture interrupt. When written logic zero, no connection
between the Analog Comparator and the input capture function exists. To make the comparator
trigger the Timer/Counter1 Input Capture interrupt, the ICIE1 bit in the Timer Interrupt Mask
Register (TIMSK1) must be set.
• Bits 1, 0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode Select
These bits determine which comparator events that trigger the Analog Comparator interrupt. The
different settings are shown in Table 16-2.
Table 16-2.
ACIS1/ACIS0 Settings
ACIS1
ACIS0
Interrupt Mode
0
0
Comparator Interrupt on Output Toggle.
0
1
Reserved
1
0
Comparator Interrupt on Falling Output Edge.
1
1
Comparator Interrupt on Rising Output Edge.
When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be disabled by
clearing its Interrupt Enable bit in the ACSR Register. Otherwise an interrupt can occur when the
bits are changed.
16.2.3
DIDR1 – Digital Input Disable Register 1
Bit
7
6
5
4
3
2
1
0
–
–
–
–
–
–
AIN1D
AIN0D
Read/Write
R
R
R
R
R
R
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
DIDR1
• Bit 7..2 – Res: Reserved Bits
These bits are reserved and will always read zero.
• Bit 1, 0 – AIN1D, AIN0D: AIN1, AIN0 Digital Input Disable
When this bit is written logic one, the digital input buffer on the AIN1/0 pin is disabled. The corresponding PIN Register bit will always read as zero when this bit is set. When an analog signal is
applied to the AIN1/0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer.
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17. Analog-to-Digital Converter
17.1
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
17.2
10-bit Resolution
1 LSB Integral Non-linearity
± 2 LSB Absolute Accuracy
14 µs Conversion Time
15 kSPS at Maximum Resolution
Six Multiplexed Single Ended Input Channels
Two Additional Multiplexed Single Ended Input Channels (TQFP and QFN/MLF Packages, Only)
Temperature Sensor Input Channel
Optional Left Adjustment for ADC Result Readout
0 – VCC ADC Input Voltage Range
Selectable 1.1V ADC Reference Voltage
Free Running or Single Conversion Mode
Interrupt on ADC Conversion Complete
Sleep Mode Noise Canceler
Overview
ATtiny48/88 features a 10-bit, successive approximation Analog-to-Digital Converter (ADC). The
ADC is wired to a nine-channel analog multiplexer, which allows the ADC to measure the voltage at six (or eight, in 32-lead packages) single-ended input pins and from one internal, singleended voltage channel coming from the internal temperature sensor. Single-ended voltage
inputs are referred to 0V (GND).
The ADC contains a Sample and Hold circuit which ensures that the input voltage to the ADC is
held at a constant level during conversion. A block diagram of the ADC is shown in Figure 17-1
on page 159.
There is a separate analog supply voltage pin for the ADC, AVCC. Analog supply voltage is connected to the ADC via a passive switch. The voltage difference between supply voltage pins VCC
and AVCC may not exceed. See section “ADC Noise Canceler” on page 165 on how to connect
the analog suplly voltage pin.
Internal reference voltage of nominally 1.1V is provided on-chip. Alternatively, VCC can be used
as reference voltage.
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Figure 17-1. Analog to Digital Converter Block Schematic Operation
ADC CONVERSION
COMPLETE IRQ
0
ADC DATA REGISTER
(ADCH/ADCL)
ADC[9:0]
ADPS1
ADPS0
ADPS2
ADIF
ADFR
ADEN
ADSC
MUX1
15
ADC CTRL. & STATUS
REGISTER (ADCSRA)
MUX0
MUX3
MUX2
ADLAR
REFS0
ADC MULTIPLEXER
SELECT (ADMUX)
ADIE
ADIF
8-BIT DATA BUS
MUX DECODER
CHANNEL SELECTION
PRESCALER
AVCC
CONVERSION LOGIC
INTERNAL 1.1V
REFERENCE
SAMPLE & HOLD
COMPARATOR
10-BIT DAC
+
GND
BANDGAP
REFERENCE
TEMPERATURE
SENSOR
ADC7
ADC6
INPUT
MUX
ADC MULTIPLEXER
OUTPUT
ADC5
ADC4
ADC3
ADC2
ADC1
ADC0
17.3
Operation
In order to be able to use the ADC the Power Reduction bit, PRADC, in the Power Reduction
Register must be disabled. This is done by clearing the PRADC bit. See “PRR – Power Reduction Register” on page 37 for more details.
The ADC converts an analog input voltage to a 10-bit digital value through successive approximation. The minimum value represents GND and the maximum value represents the reference
voltage. The ADC voltage reference may be selected by writing the REFS0 bit in the ADMUX
register. Alternatives are the VCC supply pin and the internal 1.1V voltage reference.
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The analog input channel is selected by writing to the MUX bits in ADMUX. Any of the ADC input
pins, as well as GND and a fixed bandgap voltage reference, can be selected as single ended
inputs to the ADC.
The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSRA. Voltage reference and
input channel selections will not go into effect until ADEN is set. The ADC does not consume
power when ADEN is cleared, so it is recommended to switch off the ADC before entering power
saving sleep modes.
The ADC generates a 10-bit result which is presented in the ADC Data Registers, ADCH and
ADCL. By default, the result is presented right adjusted, but can optionally be presented left
adjusted by setting the ADLAR bit in ADMUX.
If the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read
ADCH, only. Otherwise, ADCL must be read first, then ADCH, to ensure that the content of the
Data Registers belongs to the same conversion. Once ADCL is read, ADC access to Data Registers is blocked. This means that if ADCL has been read, and a conversion completes before
ADCH is read, neither register is updated and the result from the conversion is lost. When ADCH
is read, ADC access to the ADCH and ADCL Registers is re-enabled.
The ADC has its own interrupt which can be triggered when a conversion completes. When ADC
access to the Data Registers is prohibited between reading of ADCH and ADCL, the interrupt
will trigger even if the result is lost.
17.4
Starting a Conversion
Make sure the ADC is powered by clearing the ADC Power Reduction bit, PRADC, in the Power
Reduction Register, PRR (see “PRR – Power Reduction Register” on page 37). A single conversion is started by writing a logical one to the ADC Start Conversion bit, ADSC. This bit stays high
as long as the conversion is in progress and will be cleared by hardware when the conversion is
completed. If a different data channel is selected while a conversion is in progress, the ADC will
finish the current conversion before performing the channel change.
Alternatively, a conversion can be triggered automatically by various sources. Auto Triggering is
enabled by setting the ADC Auto Trigger Enable bit, ADATE in ADCSRA. The trigger source is
selected by setting the ADC Trigger Select bits, ADTS in ADCSRB (See description of the ADTS
bits for a list of the trigger sources). When a positive edge occurs on the selected trigger signal,
the ADC prescaler is reset and a conversion is started. This provides a method of starting conversions at fixed intervals. If the trigger signal still is set when the conversion completes, a new
conversion will not be started. If another positive edge occurs on the trigger signal during conversion, the edge will be ignored. Note that an Interrupt Flag will be set even if the specific
interrupt is disabled or the Global Interrupt Enable bit in SREG is cleared. A conversion can thus
be triggered without causing an interrupt. However, the Interrupt Flag must be cleared in order to
trigger a new conversion at the next interrupt event.
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Figure 17-2. ADC Auto Trigger Logic
ADTS[2:0]
PRESCALER
START
ADIF
CLKADC
ADATE
SOURCE 1
.
.
.
.
CONVERSION
LOGIC
EDGE
DETECTOR
SOURCE n
ADSC
Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion as soon
as the ongoing conversion has finished. The ADC then operates in Free Running mode, constantly sampling and updating the ADC Data Register. The first conversion must be started by
writing a logical one to the ADSC bit in ADCSRA. In this mode the ADC will perform successive
conversions independently of whether the ADC Interrupt Flag, ADIF is cleared or not.
If Auto Triggering is enabled, single conversions can be started by writing ADSC in ADCSRA to
one. ADSC can also be used to determine if a conversion is in progress. The ADSC bit will be
read as one during a conversion, independently of how the conversion was started.
17.5
Prescaling and Conversion Timing
By default, the successive approximation circuitry requires an input clock frequency between 50
kHz and 200 kHz to get maximum resolution. If a lower resolution than 10 bits is needed, the
input clock frequency to the ADC can be higher than 200 kHz to get a higher sample rate. It is
not recommended to use a higher input clock frequency than 1MHz.
Figure 17-3. ADC Prescaler
ADEN
START
Reset
7-BIT ADC PRESCALER
CK/64
CK/128
CK/32
CK/8
CK/16
CK/4
CK/2
CK
ADPS0
ADPS1
ADPS2
ADC CLOCK SOURCE
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The ADC module contains a prescaler, as illustrated in Figure 17-3 on page 161, which generates an acceptable ADC clock frequency from any CPU frequency above 100 kHz. The
prescaling is set by the ADPS bits in ADCSRA. The prescaler starts counting from the moment
the ADC is switched on by setting the ADEN bit in ADCSRA. The prescaler keeps running for as
long as the ADEN bit is set, and is continuously reset when ADEN is low.
When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion
starts at the following rising edge of the ADC clock cycle.
A normal conversion takes 13 ADC clock cycles. The first conversion after the ADC is switched
on (ADEN in ADCSRA is set) takes 25 ADC clock cycles in order to initialize the analog circuitry,
as shown in Figure 17-4 below.
Figure 17-4. ADC Timing Diagram, First Conversion (Single Conversion Mode)
Next
Conversion
First Conversion
Cycle Number
1
2
12
13
14
15
16
17
18
19
20
21
22
23
24
25
1
2
3
ADC Clock
ADEN
ADSC
ADIF
Sign and MSB of Result
ADCH
LSB of Result
ADCL
MUX and REFS
Update
Conversion
Complete
Sample & Hold
MUX and REFS
Update
The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of a normal conversion and 13.5 ADC clock cycles after the start of an first conversion. When a conversion is
complete, the result is written to the ADC Data Registers, and ADIF is set. In Single Conversion
mode, ADSC is cleared simultaneously. The software may then set ADSC again, and a new
conversion will be initiated on the first rising ADC clock edge.
Figure 17-5. ADC Timing Diagram, Single Conversion
One Conversion
Cycle Number
1
2
3
4
5
6
7
8
9
Next Conversion
10
11
12
13
1
2
3
ADC Clock
ADSC
ADIF
ADCH
Sign and MSB of Result
ADCL
LSB of Result
Sample & Hold
MUX and REFS
Update
162
Conversion
Complete
MUX and REFS
Update
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ATtiny48/88
When Auto Triggering is used, the prescaler is reset when the trigger event occurs, as shown in
Figure 17-6. This assures a fixed delay from the trigger event to the start of conversion. In this
mode, the sample-and-hold takes place two ADC clock cycles after the rising edge on the trigger
source signal. Three additional CPU clock cycles are used for synchronization logic.
Figure 17-6. ADC Timing Diagram, Auto Triggered Conversion
One Conversion
1
Cycle Number
2
3
4
5
6
7
8
Next Conversion
10
9
11
12
13
1
2
ADC Clock
Trigger
Source
ADATE
ADIF
ADCH
Sign and MSB of Result
ADCL
LSB of Result
Prescaler
Reset
Sample &
Hold
Prescaler
Reset
Conversion
Complete
MUX and REFS
Update
In Free Running mode, a new conversion will be started immediately after the conversion completes, while ADSC remains high. See Figure 17-7.
Figure 17-7. ADC Timing Diagram, Free Running Conversion
One Conversion
Cycle Number
12
13
Next Conversion
14
1
2
3
4
ADC Clock
ADSC
ADIF
ADCH
Sign and MSB of Result
ADCL
LSB of Result
Conversion
Complete
Sample & Hold
MUX and REFS
Update
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For a summary of conversion times, see Table 17-1.
Table 17-1.
ADC Conversion Time
Sample & Hold
(Cycles from Start of Conversion)
Conversion Time
(Cycles)
First conversion
13.5
25
Normal conversions, single ended
1.5
13
Auto Triggered conversions
2
13.5
Free Running conversions
2.5
14
Condition
17.6
Changing Channel or Reference Selection
Bits MUXn and REFS0 in the ADMUX Register are single buffered through a temporary register
to which the CPU has random access. This ensures that the channels and reference selection
only takes place at a safe point during the conversion. The channel and reference selection is
continuously updated until a conversion is started. Once the conversion starts, the channel and
reference selection is locked to ensure a sufficient sampling time for the ADC. Continuous
updating resumes in the last ADC clock cycle before the conversion completes (ADIF in ADCSRA is set). Note that the conversion starts on the following rising ADC clock edge after ADSC is
written. The user is thus advised not to write new channel or reference selection values to
ADMUX until one ADC clock cycle after ADSC is written.
If Auto Triggering is used, the exact time of the triggering event can be indeterministic. Special
care must be taken when updating the ADMUX Register, in order to control which conversion
will be affected by the new settings.
If both ADATE and ADEN is written to one, an interrupt event can occur at any time. If the
ADMUX Register is changed in this period, the user cannot tell if the next conversion is based
on the old or the new settings. ADMUX can be safely updated in the following ways:
• When ADATE or ADEN is cleared.
• During conversion, minimum one ADC clock cycle after the trigger event.
• After a conversion, before the Interrupt Flag used as trigger source is cleared.
When updating ADMUX in one of these conditions, the new settings will affect the next ADC
conversion.
17.6.1
ADC Input Channels
When changing channel selections, the user should observe the following guidelines to ensure
that the correct channel is selected:
In Single Conversion mode, always select the channel before starting the conversion. The channel selection may be changed one ADC clock cycle after writing one to ADSC. However, the
simplest method is to wait for the conversion to complete before changing the channel selection.
In Free Running mode, always select the channel before starting the first conversion. The channel selection may be changed one ADC clock cycle after writing one to ADSC. However, the
simplest method is to wait for the first conversion to complete, and then change the channel
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selection. Since the next conversion has already started automatically, the next result will reflect
the previous channel selection. Subsequent conversions will reflect the new channel selection.
17.6.2
ADC Voltage Reference
The ADC reference voltage (VREF) indicates the conversion range for the ADC. Single ended
channels that exceed VREF will result in codes close to 0x3FF. VREF can be selected as either
AVCC, or internal 1.1V reference. The internal 1.1V reference is generated from the internal
bandgap reference (VBG) through an internal amplifier.
The first ADC conversion result after switching reference voltage source may be inaccurate, and
the user is advised to discard this result.
17.7
ADC Noise Canceler
The ADC features a noise canceler that enables conversion during sleep mode. This reduces
noise induced from the CPU core and other I/O peripherals. The noise canceler can be used
with ADC Noise Reduction and Idle mode. To make use of this feature, the following procedure
should be used:
• Make sure that the ADC is enabled and is not busy converting. Single Conversion mode must
be selected and the ADC conversion complete interrupt must be enabled.
• Enter ADC Noise Reduction mode (or Idle mode). The ADC will start a conversion once the
CPU has been halted.
• If no other interrupts occur before the ADC conversion completes, the ADC interrupt will wake
up the CPU and execute the ADC Conversion Complete interrupt routine. If another interrupt
wakes up the CPU before the ADC conversion is complete, that interrupt will be executed,
and an ADC Conversion Complete interrupt request will be generated when the ADC
conversion completes. The CPU will remain in active mode until a new sleep command is
executed.
Note that the ADC will not automatically be turned off when entering other sleep modes than Idle
mode and ADC Noise Reduction mode. The user is advised to write zero to ADEN before entering such sleep modes to avoid excessive power consumption.
17.8
Analog Input Circuitry
The analog input circuitry for single ended channels is illustrated in Figure 17-8 An analog
source applied to ADCn is subjected to the pin capacitance and input leakage of that pin, regardless of whether that channel is selected as input for the ADC. When the channel is selected, the
source must drive the S/H capacitor through the series resistance (combined resistance in the
input path).
The ADC is optimized for analog signals with an output impedance of approximately 10kΩ or
less. If such a source is used, the sampling time will be negligible. If a source with higher impedance is used, the sampling time will depend on how long time the source needs to charge the
S/H capacitor, which can vary widely. With slowly varying signals the user is recommended to
use sources with low impedance, only, since this minimizes the required charge transfer to the
S/H capacitor.
In order to avoid distortion from unpredictable signal convolution, signal components higher than
the Nyquist frequency (fADC/2) should not be present. The user is advised to remove high frequency components with a low-pass filter before applying the signals as inputs to the ADC.
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Figure 17-8. Analog Input Circuitry
IIH
ADCn
1..100 kOhm
CS/H= 14 pF
IIL
VCC/2
Note:
17.9
The capacitor in the figure depicts the total capacitance, including the sample/hold capacitor and
any stray or parasitic capacitance inside the device. The value given is worst case.
Analog Noise Canceling Techniques
Digital circuitry inside and outside the device generates EMI which might affect the accuracy of
analog measurements. When conversion accuracy is critical, the noise level can be reduced by
applying the following techniques:
• Keep analog signal paths as short as possible.
• Make sure analog tracks run over the analog ground plane.
• Keep analog tracks well away from high-speed switching digital tracks.
• If any port pin is used as a digital output, it mustn’t switch while a conversion is in progress.
• The analog supply voltage pin (AVCC) should be connected to the digital supply voltage pin
(VCC) via an LC network as shown in Figure 17-9.
Analog Ground Plane
PC2 (ADC2)
PC3 (ADC3)
PC4 (ADC4/SDA)
PC5 (ADC5/SCL)
PC6
PD0
Figure 17-9. ADC Power Connections
PC1 (ADC1)
PC0 (ADC0)
VCC
PA1 (ADC7)
PA0 (ADC6)
10mH
PC7
100nF
GND
AVCC
PB5
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Where high ADC accuracy is required it is recommended to use ADC Noise Reduction Mode, as
described in Section 17.7 on page 165. This is especially the case when system clock frequency
is above 1 MHz, or when the ADC is used for reading the internal temperature sensor, as
described in Section 17.12 on page 169. A good system design with properly placed, external
bypass capacitors does reduce the need for using ADC Noise Reduction Mode
17.10 ADC Accuracy Definitions
An n-bit single-ended ADC converts a voltage linearly between GND and V REF in 2 n steps
(LSBs). The lowest code is read as 0, and the highest code is read as 2n-1.
Several parameters describe the deviation from the ideal behavior:
• Offset: The deviation of the first transition (0x000 to 0x001) compared to the ideal transition
(at 0.5 LSB). Ideal value: 0 LSB.
Figure 17-10. Offset Error
Output Code
Ideal ADC
Actual ADC
Offset
Error
VREF Input Voltage
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• Gain error: After adjusting for offset, the gain error is found as the deviation of the last
transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum).
Ideal value: 0 LSB
Figure 17-11. Gain Error
Gain
Error
Output Code
Ideal ADC
Actual ADC
VREF Input Voltage
• Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum
deviation of an actual transition compared to an ideal transition for any code. Ideal value: 0
LSB.
Figure 17-12. Integral Non-linearity (INL)
Output Code
INL
Ideal ADC
Actual ADC
VREF
168
Input Voltage
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• Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval
between two adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB.
Figure 17-13. Differential Non-linearity (DNL)
Output Code
0x3FF
1 LSB
DNL
0x000
0
VREF Input Voltage
• Quantization Error: Due to the quantization of the input voltage into a finite number of codes,
a range of input voltages (1 LSB wide) will code to the same value. Always ±0.5 LSB.
• Absolute accuracy: The maximum deviation of an actual (unadjusted) transition compared to
an ideal transition for any code. This is the compound effect of offset, gain error, differential
error, non-linearity, and quantization error. Ideal value: ±0.5 LSB.
17.11 ADC Conversion Result
After the conversion is complete (ADIF is high), the conversion result can be found in the ADC
Result Registers (ADCL, ADCH).
For single ended conversion, the result is
V IN ⋅ 1024
ADC = -------------------------V REF
where VIN is the voltage on the selected input pin and VREF the selected voltage reference (see
Table 17-3 on page 170 and Table 17-4 on page 171). 0x000 represents analog ground, and
0x3FF represents the selected reference voltage minus one LSB.
17.12 Temperature Measurement
The temperature measurement is based on an on-chip temperature sensor that is coupled to a
single-ended ADC8 channel. Selecting the ADC8 channel by writing the MUX3..0 bits in ADMUX
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register to “1000” enables the temperature sensor. The internal 1.1V voltage reference must
also be selected for the ADC voltage reference source in the temperature sensor measurement.
When the temperature sensor is enabled, the ADC converter can be used in single conversion
mode to measure the voltage over the temperature sensor.
The measured voltage has a linear relationship to the temperature as described in Table 17-2
The sensitivity is approximately 1 LSB / °C and the accuracy depends on the method of user calibration. Typically, the measurement accuracy after a single temperature calibration is ±10°C,
assuming calibration at room temperature. Better accuracies are achieved by using two
temperature points for calibration.
Table 17-2.
Temperature vs. Sensor Output Voltage (Typical Case)
Temperature
ADC
-40°C
+25°C
+85°C
230 LSB
300 LSB
370 LSB
The values described in Table 17-2 are typical values. However, due to process variation the
temperature sensor output voltage varies from one chip to another. To be capable of achieving
more accurate results the temperature measurement can be calibrated in the application software. The sofware calibration can be done using the formula:
T = k * [(ADCH << 8) | ADCL] + TOS
where ADCH and ADCL are the ADC data registers, k is the fixed slope coefficient and TOS is the
temperature sensor offset. Typically, k is very close to 1.0 and in single-point calibration the
coefficient may be omitted. Where higher accuracy is required the slope coefficient should be
evaluated based on measurements at two temperatures.
17.13 Register Description
17.13.1
ADMUX – ADC Multiplexer Selection Register
Bit
7
6
5
4
3
2
1
0
–
REFS0
ADLAR
–
MUX3
MUX2
MUX1
MUX0
Read/Write
R
R/W
R/W
R
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
ADMUX
• Bits 7,4 – Res: Reserved Bits
These bits are reserved and will always read zero.
• Bit 6 – REFS0: Reference Selection Bits
This bit select the voltage reference for the ADC, as shown in Table 17-3. If this bit is changed
during a conversion, the change will not go in effect until this conversion is complete (ADIF in
ADCSRA is set).
Table 17-3.
REFS0
170
Voltage Reference Selections for ADC
Voltage Reference Selection
0
Internal 1.1V Voltage Reference
1
AVCC Reference
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• Bit 5 – ADLAR: ADC Left Adjust Result
The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Register.
Write one to ADLAR to left adjust the result. Otherwise, the result is right adjusted. Changing the
ADLAR bit will affect the ADC Data Register immediately, regardless of any ongoing conversions. For a complete description of this bit, see “ADCL and ADCH – The ADC Data Register” on
page 173.
• Bits 3:0 – MUX3:0: Analog Channel Selection Bits
The value of these bits selects which analog inputs are connected to the ADC. Selecting the single-ended channel ADC8 enables the temperature measurement. See Table 17-4 for details. If
these bits are changed during a conversion, the change will not go in effect until this conversion
is complete (ADIF in ADCSRA is set).
Table 17-4.
Input Channel Selections
MUX3..0
Note:
17.13.2
Single Ended Input
0000
ADC0
0001
ADC1
0010
ADC2
0011
ADC3
0100
ADC4
0101
ADC5
0110
ADC6
0111
ADC7
1000
ADC8(1)
1001
(reserved)
1010
(reserved)
1011
(reserved)
1100
(reserved)
1101
(reserved)
1110
1.1V (VBG)
1111
0V (GND)
1. “Temperature Measurement” on page 169
ADCSRA – ADC Control and Status Register A
Bit
7
6
5
4
3
2
1
0
ADEN
ADSC
ADATE
ADIF
ADIE
ADPS2
ADPS1
ADPS0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
ADCSRA
• Bit 7 – ADEN: ADC Enable
Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning the
ADC off while a conversion is in progress, will terminate this conversion.
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• Bit 6 – ADSC: ADC Start Conversion
In Single Conversion mode, write this bit to one to start each conversion. In Free Running mode,
write this bit to one to start the first conversion. The first conversion after ADSC has been written
after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled,
will take 25 ADC clock cycles instead of the normal 13. This first conversion performs initialization of the ADC.
ADSC will read as one as long as a conversion is in progress. When the conversion is complete,
it returns to zero. Writing zero to this bit has no effect.
• Bit 5 – ADATE: ADC Auto Trigger Enable
When this bit is written to one, Auto Triggering of the ADC is enabled. The ADC will start a conversion on a positive edge of the selected trigger signal. The trigger source is selected by setting
the ADC Trigger Select bits, ADTS in ADCSRB.
• Bit 4 – ADIF: ADC Interrupt Flag
This bit is set when an ADC conversion completes and the Data Registers are updated. The
ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set.
ADIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ADIF is cleared by writing a logical one to the flag. Beware that if doing a Read-ModifyWrite on ADCSRA, a pending interrupt can be disabled. This also applies if the SBI and CBI
instructions are used.
• Bit 3 – ADIE: ADC Interrupt Enable
When this bit is written to one and the I-bit in SREG is set, the ADC Conversion Complete Interrupt is activated.
• Bits 2:0 – ADPS2:0: ADC Prescaler Select Bits
These bits determine the division factor between the system clock frequency and the input clock
to the ADC.
Table 17-5.
172
ADC Prescaler Selections
ADPS2
ADPS1
ADPS0
Division Factor
0
0
0
2
0
0
1
2
0
1
0
4
0
1
1
8
1
0
0
16
1
0
1
32
1
1
0
64
1
1
1
128
ATtiny48/88
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ATtiny48/88
17.13.3
17.13.3.1
ADCL and ADCH – The ADC Data Register
ADLAR = 0
Bit
Read/Write
Initial Value
17.13.3.2
15
14
13
12
11
10
9
8
–
–
–
–
–
–
ADC9
ADC8
ADCH
ADC7
ADC6
ADC5
ADC4
ADC3
ADC2
ADC1
ADC0
ADCL
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ADLAR = 1
Bit
Read/Write
Initial Value
15
14
13
12
11
10
9
8
ADC9
ADC8
ADC7
ADC6
ADC5
ADC4
ADC3
ADC2
ADCH
ADC1
ADC0
–
–
–
–
–
–
ADCL
7
6
5
4
3
2
1
0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
• ADC9:0: ADC Conversion Result
These bits represent the result from the conversion, as detailed in “ADC Conversion Result” on
page 169.
When an ADC conversion is complete, the result is found in these two registers.
When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if
the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read
ADCH. Otherwise, ADCL must be read first, then ADCH.
The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is read from
the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result
is right adjusted.
17.13.4
ADCSRB – ADC Control and Status Register B
Bit
7
6
5
4
3
2
1
0
–
ACME
–
–
–
ADTS2
ADTS1
ADTS0
Read/Write
R
R/W
R
R
R
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
ADCSRB
• Bit 7, 5:3 – Res: Reserved Bits
These bits are reserved for future use. To ensure compatibility with future devices, these bits
must be written to zero when ADCSRB is written.
• Bit 2:0 – ADTS2:0: ADC Auto Trigger Source
If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger
an ADC conversion. If ADATE is cleared, the ADTS2:0 settings will have no effect. A conversion
will be triggered by the rising edge of the selected Interrupt Flag. Note that switching from a trigger source that is cleared to a trigger source that is set, will generate a positive edge on the
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8008C–AVR–03/09
trigger signal. If ADEN in ADCSRA is set, this will start a conversion. Switching to Free Running
mode (ADTS[2:0]=0) will not cause a trigger event, even if the ADC Interrupt Flag is set.
Table 17-6.
17.13.5
ADC Auto Trigger Source Selections
ADTS2
ADTS1
ADTS0
Trigger Source
0
0
0
Free Running mode
0
0
1
Analog Comparator
0
1
0
External Interrupt Request 0
0
1
1
Timer/Counter0 Compare Match A
1
0
0
Timer/Counter0 Overflow
1
0
1
Timer/Counter1 Compare Match B
1
1
0
Timer/Counter1 Overflow
1
1
1
Timer/Counter1 Capture Event
DIDR0 – Digital Input Disable Register 0
Bit
7
6
5
4
3
2
1
0
ADC7D
ADC6D
ADC5D
ADC4D
ADC3D
ADC2D
ADC1D
ADC0D
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
DIDR0
• Bit 7:0 – ADC7D..ADC0D: ADC7..0 Digital Input Disable
When this bit is written logic one, the digital input buffer on the corresponding ADC pin is disabled. The corresponding PIN Register bit will always read as zero when this bit is set. When an
analog signal is applied to the ADC7..0 pin and the digital input from this pin is not needed, this
bit should be written logic one to reduce power consumption in the digital input buffer.
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ATtiny48/88
18. debugWIRE On-chip Debug System
18.1
Features
•
•
•
•
•
•
•
•
•
•
18.2
Complete Program Flow Control
Emulates All On-chip Functions, Both Digital and Analog, except RESET Pin
Real-time Operation
Symbolic Debugging Support (Both at C and Assembler Source Level, or for Other HLLs)
Unlimited Number of Program Break Points (Using Software Break Points)
Non-intrusive Operation
Electrical Characteristics Identical to Real Device
Automatic Configuration System
High-Speed Operation
Programming of Non-volatile Memories
Overview
The debugWIRE On-chip debug system uses a One-wire, bi-directional interface to control the
program flow, execute AVR instructions in the CPU and to program the different non-volatile
memories.
18.3
Physical Interface
When the debugWIRE Enable (DWEN) Fuse is programmed and Lock bits are unprogrammed,
the debugWIRE system within the target device is activated. The RESET port pin is configured
as a wire-AND (open-drain) bi-directional I/O pin with pull-up enabled and becomes the communication gateway between target and emulator.
Figure 18-1. The debugWIRE Setup
1.8 - 5.5V
VCC
dW
dW(RESET)
GND
Figure 18-1 shows the schematic of a target MCU, with debugWIRE enabled, and the emulator
connector. The system clock is not affected by debugWIRE and will always be the clock source
selected by the CKSEL Fuses.
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8008C–AVR–03/09
When designing a system where debugWIRE will be used, the following observations must be
made for correct operation:
• Pull-up resistors on the dW/(RESET) line must not be smaller than 10kΩ. The pull-up resistor
is not required for debugWIRE functionality.
• Connecting the RESET pin directly to VCC will not work.
• Capacitors connected to the RESET pin must be disconnected when using debugWire.
• All external reset sources must be disconnected.
18.4
Software Break Points
debugWIRE supports Program memory Break Points by the AVR Break instruction. Setting a
Break Point in AVR Studio® will insert a BREAK instruction in the Program memory. The instruction replaced by the BREAK instruction will be stored. When program execution is continued, the
stored instruction will be executed before continuing from the Program memory. A break can be
inserted manually by putting the BREAK instruction in the program.
The Flash must be re-programmed each time a Break Point is changed. This is automatically
handled by AVR Studio through the debugWIRE interface. The use of Break Points will therefore
reduce the Flash Data retention. Devices used for debugging purposes should not be shipped to
end customers.
18.5
Limitations of debugWIRE
The debugWIRE communication pin (dW) is physically located on the same pin as External
Reset (RESET). An External Reset source is therefore not supported when the debugWIRE is
enabled.
The debugWIRE system accurately emulates all I/O functions when running at full speed, i.e.,
when the program in the CPU is running. When the CPU is stopped, care must be taken while
accessing some of the I/O Registers via the debugger (AVR Studio).
The debugWIRE interface is asynchronous, which means that the debugger needs to synchronize to the system clock. If the system clock is changed by software (e.g. by writing CLKPS bits)
communication via debugWIRE may fail. Also, clock frequencies below 100 kHz may cause
communication problems.
A programmed DWEN Fuse enables some parts of the clock system to be running in all sleep
modes. This will increase the power consumption while in sleep. Thus, the DWEN Fuse should
be disabled when debugWire is not used.
18.6
18.6.1
Register Description
DWDR – debugWire Data Register
Bit
7
6
5
4
3
2
1
0
DWDR[7:0]
DWDR
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
The DWDR Register provides a communication channel from the running program in the MCU
to the debugger. This register is only accessible by the debugWIRE and can therefore not be
used as a general purpose register in the normal operations.
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ATtiny48/88
19. Self-Programming the Flash
The device provides a Self-Programming mechanism for downloading and uploading program
code by the MCU itself. The Self-Programming can use any available data interface and associated protocol to read code and write (program) that code into the Program memory. The SPM
instruction is disabled by default but it can be enabled by programming the SELFPRGEN fuse
(to “0”).
The Program memory is updated in a page by page fashion. Before programming a page with
the data stored in the temporary page buffer, the page must be erased. The temporary page buffer is filled one word at a time using SPM and the buffer can be filled either before the Page
Erase command or between a Page Erase and a Page Write operation:
Alternative 1, fill the buffer before a Page Erase:
• Fill temporary page buffer
• Perform a Page Erase
• Perform a Page Write
Alternative 2, fill the buffer after Page Erase:
• Perform a Page Erase
• Fill temporary page buffer
• Perform a Page Write
If only a part of the page needs to be changed, the rest of the page must be stored (for example
in the temporary page buffer) before the erase, and then be re-written. Alternative 1 provides an
effective Read-Modify-Write feature which allows the user software to first read the page, do the
necessary changes, and then write back the modified data. If alternative 2 is used, it is not possible to read the old data while loading since the page is already erased. The temporary page
buffer can be accessed in a random sequence. It is essential that the page address used in both
the Page Erase and Page Write operation is addressing the same page.
19.0.1
Performing Page Erase by SPM
To execute Page Erase, set up the address in the Z-pointer, write “00000011” to SPMCSR and
execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored.
The page address must be written to PCPAGE in the Z-register. Other bits in the Z-pointer will
be ignored during this operation.
The CPU is halted during the Page Erase operation.
19.0.2
Filling the Temporary Buffer (Page Loading)
To write an instruction word, set up the address in the Z-pointer and data in R1:R0, write
“00000001” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The
content of PCWORD in the Z-register is used to address the data in the temporary buffer. The
temporary buffer will auto-erase after a Page Write operation or by writing the CTPB bit in
SPMCSR. It is also erased after a system reset. Note that it is not possible to write more than
one time to each address without erasing the temporary buffer.
If the EEPROM is written in the middle of an SPM Page Load operation, all data loaded will be
lost.
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19.0.3
Performing a Page Write
To execute Page Write, set up the address in the Z-pointer, write “00000101” to SPMCSR and
execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored.
The page address must be written to PCPAGE. Other bits in the Z-pointer must be written to
zero during this operation.
The CPU is halted during the Page Write operation.
19.1
Addressing the Flash During Self-Programming
The Z-pointer is used to address the SPM commands.
Bit
15
14
13
12
11
10
9
8
ZH (R31)
Z15
Z14
Z13
Z12
Z11
Z10
Z9
Z8
ZL (R30)
Z7
Z6
Z5
Z4
Z3
Z2
Z1
Z0
7
6
5
4
3
2
1
0
Since the Flash is organized in pages (see Table 20-7 on page 187), the Program Counter can
be treated as having two different sections. One section, consisting of the least significant bits, is
addressing the words within a page, while the most significant bits are addressing the pages.
This is shown in Figure 19-1. Note that the Page Erase and Page Write operations are
addressed independently. Therefore it is of major importance that the software addresses the
same page in both the Page Erase and Page Write operation.
The LPM instruction uses the Z-pointer to store the address. Since this instruction addresses the
Flash byte-by-byte, also the LSB (bit Z0) of the Z-pointer is used.
Figure 19-1. Addressing the Flash During SPM(1)
BIT
15
ZPCMSB
ZPAGEMSB
Z - REGISTER
1 0
0
PCMSB
PROGRAM
COUNTER
PAGEMSB
PCPAGE
PAGE ADDRESS
WITHIN THE FLASH
PROGRAM MEMORY
PAGE
PCWORD
WORD ADDRESS
WITHIN A PAGE
PAGE
INSTRUCTION WORD
PCWORD[PAGEMSB:0]:
00
01
02
PAGEEND
Note:
178
1. The different variables used in Figure 19-1 are listed in Table 20-7 on page 187.
ATtiny48/88
8008C–AVR–03/09
ATtiny48/88
19.1.1
EEPROM Write Prevents Writing to SPMCSR
Note that an EEPROM write operation will block all software programming to Flash. Reading the
Fuses and Lock bits from software will also be prevented during the EEPROM write operation. It
is recommended that the user checks the status bit (EEPE) in the EECR Register and verifies
that the bit is cleared before writing to the SPMCSR Register.
19.1.2
Reading the Fuse and Lock Bits from Software
It is possible to read both the Fuse and Lock bits from software. To read the Lock bits, load the
Z-pointer with 0x0001 and set the RFLB and SELFPRGEN bits in SPMCSR. When an LPM
instruction is executed within three CPU cycles after the RFLB and SELFPRGEN bits are set in
SPMCSR, the value of the Lock bits will be loaded in the destination register. The RFLB and
SELFPRGEN bits will auto-clear upon completion of reading the Lock bits or if no LPM instruction is executed within three CPU cycles or no SPM instruction is executed within four CPU
cycles. When RFLB and SELFPRGEN are cleared, LPM will work as described in the Instruction
set Manual.
Bit
7
6
5
4
3
2
1
0
Rd
–
–
–
–
–
–
LB2
LB1
The algorithm for reading the Fuse Low byte is similar to the one described above for reading
the Lock bits. To read the Fuse Low byte, load the Z-pointer with 0x0000 and set the RFLB and
SELFPRGEN bits in SPMCSR. When an LPM instruction is executed within three cycles after
the RFLB and SELFPRGEN bits are set in the SPMCSR, the value of the Fuse Low byte (FLB)
will be loaded in the destination register as shown below.See Table 20-5 on page 186 for a
detailed description and mapping of the Fuse Low byte.
Bit
7
6
5
4
3
2
1
0
Rd
FLB7
FLB6
FLB5
FLB4
FLB3
FLB2
FLB1
FLB0
Similarly, when reading the Fuse High byte (FHB), load 0x0003 in the Z-pointer. When an LPM
instruction is executed within three cycles after the RFLB and SELFPRGEN bits are set in the
SPMCSR, the value of the Fuse High byte will be loaded in the destination register as shown
below. See Table 20-4 on page 185 for detailed description and mapping of the Fuse High byte.
Bit
7
6
5
4
3
2
1
0
Rd
FHB7
FHB6
FHB5
FHB4
FHB3
FHB2
FHB1
FHB0
Fuse Extended byte can be read by loading the Z-pointer with 0x0002. When an LPM instruction
is executed within three cycles after the RFLB and SPMEN bits are set in the SPMCSR, the
value of the Fuse Extended Byte (FEB) will be loaded in the destination register as shown
below. See Table 20-3 on page 184 for detailed description and mapping of the Fuse Extended
byte.
Bit
7
6
5
4
3
2
1
0
Rd
FEB7
FEB6
FEB5
FEB4
FEB3
FEB2
FEB1
FEB0
Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that are
unprogrammed, will be read as one.
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19.1.3
Preventing Flash Corruption
During periods of low VCC, the Flash program can be corrupted because the supply voltage is
too low for the CPU and the Flash to operate properly. These issues are the same as for board
level systems using the Flash, and the same design solutions should be applied.
A Flash program corruption can be caused by two situations when the voltage is too low. First, a
regular write sequence to the Flash requires a minimum voltage to operate correctly. Secondly,
the CPU itself can execute instructions incorrectly, if the supply voltage for executing instructions
is too low.
Flash corruption can easily be avoided by following these design recommendations (one is
sufficient):
1. Keep the AVR RESET active (low) during periods of insufficient power supply voltage.
This can be done by enabling the internal Brown-out Detector (BOD) if the operating
voltage matches the detection level. If not, an external low VCC reset protection circuit
can be used. If a reset occurs while a write operation is in progress, the write operation
will be completed provided that the power supply voltage is sufficient.
2. Keep the AVR core in Power-down sleep mode during periods of low VCC. This will prevent the CPU from attempting to decode and execute instructions, effectively protecting
the SPMCSR Register and thus the Flash from unintentional writes.
19.1.4
Programming Time for Flash when Using SPM
The calibrated oscillator is used to time Flash accesses. Table 19-1 shows the typical programming time for Flash accesses from the CPU.
Table 19-1.
SPM Programming Time
Symbol
Flash write (Page Erase, Page Write, and
write Lock bits by SPM)
19.1.5
Min Programming Time
Max Programming Time
3.7 ms
4.5 ms
Simple Assembly Code Example for a Boot Loader
Note that the RWWSB bit will always be read as zero in ATtiny48/88. Nevertheless, to ensure
compatibility with devices supporting Read-While-Write it is recommended to check this bit as
shown in the code example.
;-the routine writes one page of data from RAM to Flash
; the first data location in RAM is pointed to by the Y pointer
; the first data location in Flash is pointed to by the Z-pointer
;-error handling is not included
;-the routine must be placed inside the Boot space
; (at least the Do_spm sub routine). Only code inside NRWW section can
; be read during Self-Programming (Page Erase and Page Write).
;-registers used: r0, r1, temp1 (r16), temp2 (r17), looplo (r24),
; loophi (r25), spmcrval (r20)
; storing and restoring of registers is not included in the routine
; register usage can be optimized at the expense of code size
;-It is assumed that either the interrupt table is moved to the Boot
; loader section or that the interrupts are disabled.
.equ PAGESIZEB = PAGESIZE*2
;PAGESIZEB is page size in BYTES, not words
.org SMALLBOOTSTART
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ATtiny48/88
Write_page:
; Page Erase
ldi spmcrval, (1<<PGERS) | (1<<SELFPRGEN)
rcallDo_spm
; re-enable the RWW section
ldi spmcrval, (1<<CTPB) | (1<<SELFPRGEN)
rcallDo_spm
; transfer data from RAM to Flash page buffer
ldi looplo, low(PAGESIZEB)
;init loop variable
ldi loophi, high(PAGESIZEB) ;not required for PAGESIZEB<=256
Wrloop:
ld
r0, Y+
ld
r1, Y+
ldi spmcrval, (1<<SELFPRGEN)
rcallDo_spm
adiw ZH:ZL, 2
sbiw loophi:looplo, 2
;use subi for PAGESIZEB<=256
brne Wrloop
; execute Page Write
subi ZL, low(PAGESIZEB)
;restore pointer
sbci ZH, high(PAGESIZEB)
;not required for PAGESIZEB<=256
ldi spmcrval, (1<<PGWRT) | (1<<SELFPRGEN)
rcallDo_spm
; re-enable the RWW section
ldi spmcrval, (1<<CTPB) | (1<<SELFPRGEN)
rcallDo_spm
; read back and check, optional
ldi looplo, low(PAGESIZEB)
;init loop variable
ldi loophi, high(PAGESIZEB) ;not required for PAGESIZEB<=256
subi YL, low(PAGESIZEB)
;restore pointer
sbci YH, high(PAGESIZEB)
Rdloop:
lpm r0, Z+
ld
r1, Y+
cpse r0, r1
rjmp Error
sbiw loophi:looplo, 1
;use subi for PAGESIZEB<=256
brne Rdloop
; return to RWW section
; verify that RWW section is safe to read
Return:
in
temp1, SPMCSR
sbrs temp1, RWWSB
; If RWWSB is set, the RWW section is not ready yet
ret
; re-enable the RWW section
ldi spmcrval, (1<<CTPB) | (1<<SELFPRGEN)
rcallDo_spm
rjmp Return
Do_spm:
; check for previous SPM complete
Wait_spm:
in
temp1, SPMCSR
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8008C–AVR–03/09
sbrc temp1, SELFPRGEN
rjmp Wait_spm
; input: spmcrval determines SPM action
; disable interrupts if enabled, store status
in
temp2, SREG
cli
; check that no EEPROM write access is present
Wait_ee:
sbic EECR, EEPE
rjmp Wait_ee
; SPM timed sequence
out SPMCSR, spmcrval
spm
; restore SREG (to enable interrupts if originally enabled)
out SREG, temp2
ret
19.2
19.2.1
Register Description
SPMCSR – Store Program Memory Control and Status Register
The Store Program Memory Control and Status Register contains the control bits needed to control the Program memory operations.
Bit
7
6
5
4
3
2
1
0
-
RWWSB
–
CTPB
RFLB
PGWRT
PGERS
SELFPRGEN
Read/Write
R
R
R
R/W
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
SPMCSR
• Bit 7 – Res: Reserved Bit
These bits are reserved and will always read zero.
• Bit 6 – RWWSB: Read-While-Write Section Busy
This bit is for compatibility with devices supporting Read-While-Write. It will always read as zero
in ATtiny48/88.
• Bit 5 – Res: Reserved Bit
These bits are reserved and will always read zero.
• Bit 4 – CTPB: Clear Temporary Page Buffer
If the CTPB bit is written while filling the temporary page buffer, the temporary page buffer will be
cleared and the data will be lost.
• Bit 3 – RFLB: Read Fuse and Lock Bits
An LPM instruction within three cycles after RFLB and SELFPRGEN are set in the SPMCSR
Register, will read either the Lock bits or the Fuse bits (depending on Z0 in the Z-pointer) into the
destination register. See “Reading the Fuse and Lock Bits from Software” on page 179 for
details.
• Bit 2 – PGWRT: Page Write
If this bit is written to one at the same time as SELFPRGEN, the next SPM instruction within four
clock cycles executes Page Write, with the data stored in the temporary buffer. The page
address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The
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ATtiny48/88
PGWRT bit will auto-clear upon completion of a Page Write, or if no SPM instruction is executed
within four clock cycles. The CPU is halted during the entire Page Write operation.
• Bit 1 – PGERS: Page Erase
If this bit is written to one at the same time as SELFPRGEN, the next SPM instruction within four
clock cycles executes Page Erase. The page address is taken from the high part of the Zpointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a
Page Erase, or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire Page Write operation.
• Bit 0 – SELFPRGEN: Self Programming Enable
This bit enables the SPM instruction for the next four clock cycles. If written to one together with
either CTPB, RFLB, PGWRT, or PGERS, the following SPM instruction will have a special
meaning, see description above. If only SELFPRGEN is written, the following SPM instruction
will store the value in R1:R0 in the temporary page buffer addressed by the Z-pointer. The LSB
of the Z-pointer is ignored. The SELFPRGEN bit will auto-clear upon completion of an SPM
instruction, or if no SPM instruction is executed within four clock cycles. During Page Erase and
Page Write, the SELFPRGEN bit remains high until the operation is completed.
Writing any other combination than “10001”, “01001”, “00101”, “00011” or “00001” in the lower
five bits will have no effect.
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20. Memory Programming
20.1
Program And Data Memory Lock Bits
The ATtiny48/88 provides two Lock bits which can be left unprogrammed (“1”) or can be programmed (“0”) to obtain the additional features listed in Table 20-2. The Lock bits can only be
erased to “1” with the Chip Erase command. The ATtiny48/88 has no separate Boot Loader section. The SPM instruction is enabled for the whole Flash if the SELFPRGEN fuse is programmed
(“0”), otherwise it is disabled.
Table 20-1.
Lock Bit Byte(1)
Lock Bit Byte
Description
Default Value
7
–
1 (unprogrammed)
6
–
1 (unprogrammed)
5
–
1 (unprogrammed)
4
–
1 (unprogrammed)
3
–
1 (unprogrammed)
2
–
1 (unprogrammed)
LB2
1
Lock bit
1 (unprogrammed)
LB1
0
Lock bit
1 (unprogrammed)
Notes:
1. “1” means unprogrammed, “0” means programmed.
Table 20-2.
Bit No
Lock Bit Protection Modes(1)(2)
Memory Lock Bits
Protection Type
LB Mode
LB2
LB1
1
1
1
No memory lock features enabled.
2
1
0
Further programming of the Flash and EEPROM is disabled in
Parallel and Serial Programming mode. The Fuse bits are
locked in both Serial and Parallel Programming mode.(1)
3
0
0
Further programming and verification of the Flash and EEPROM
is disabled in Parallel and Serial Programming mode. The Fuse
bits are locked in both Serial and Parallel Programming mode.(1)
Notes:
1. Program the Fuse bits before programming the LB1 and LB2.
2. “1” means unprogrammed, “0” means programmed
20.2
Fuse Bits
The ATtiny48/88 has three Fuse bytes. Table 20-3 – Table 20-5 describe briefly the functionality
of all the fuses and how they are mapped into the Fuse bytes. Note that the fuses are read as
logical zero, “0”, if they are programmed.
Table 20-3.
Fuse Extended Byte
Fuse Extended Byte
184
Bit No
Description
Default Value
–
7
–
1
–
6
–
1
–
5
–
1
ATtiny48/88
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ATtiny48/88
Table 20-3.
Fuse Extended Byte
Fuse Extended Byte
Bit No
Description
Default Value
–
4
–
1
–
3
–
1
–
2
–
1
–
1
–
1
0
Self Programming Enable
1 (unprogrammed)
SELFPRGEN (1)
Notes:
1. Enables SPM instruction. See “Self-Programming the Flash” on page 177.
Table 20-4.
Fuse High Byte
Fuse High Byte
Bit No
Description
Default Value
RSTDISBL(1) (2)
7
External Reset Disable
1 (unprogrammed)
DWEN(2)
6
debugWIRE Enable
1 (unprogrammed)
SPIEN(3)
5
Enable Serial Program and Data
Downloading
0 (programmed)
(SPI programming enabled)
WDTON(4)
4
Watchdog Timer Always On
1 (unprogrammed)
EESAVE
3
EEPROM memory preserved
through chip erase
1 (unprogrammed)
(EEPROM not preserved)
BODLEVEL2(5)
2
Brown-out Detector trigger level
1 (unprogrammed)
BODLEVEL1(5)
1
Brown-out Detector trigger level
1 (unprogrammed)
(5)
0
Brown-out Detector trigger level
1 (unprogrammed)
BODLEVEL0
Notes:
1. See “Alternate Functions of Port C” on page 67 for description of RSTDISBL Fuse.
2. Programming this fuse bit will change the functionality of the RESET pin and render further
programming via the serial interface impossible. The fuse bit can be unprogrammed using the
parallel programming algorithm (see page 189).
3. The SPIEN Fuse is not accessible in serial programming mode.
4. See “WDTCSR – Watchdog Timer Control Register” on page 44 for details.
5. See Table 8-3 on page 45 for BODLEVEL Fuse decoding.
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Table 20-5.
Fuse Low Byte
Fuse Low Byte
Description
Default Value
7
Divide clock by 8
0 (programmed)
CKOUT(3)
6
Clock output
1 (unprogrammed)
SUT1
5
Select start-up time
1 (unprogrammed)(1)
SUT0
4
Select start-up time
0 (programmed)(1)
-
3
-
1 (unprogrammed)(2)
-
2
-
1 (unprogrammed)(2)
CKSEL1
1
Select Clock source
1 (unprogrammed)(2)
CKSEL0
0
Select Clock source
0 (programmed)(2)
(4)
CKDIV8
Note:
Bit No
1. The default value of SUT1..0 results in maximum start-up time for the default clock source.
See Table 6-4 on page 28 for details.
2. The default setting of CKSEL1..0 results in internal oscillator @ 8 MHz. See Table 6-3 on page
28 for details.
3. The CKOUT Fuse allows the system clock to be output on PORTB0. See “Clock Output Buffer”
on page 30 for details.
4. See “System Clock Prescaler” on page 30 for details.
The status of the Fuse bits is not affected by Chip Erase. Note that the Fuse bits are locked if
Lock bit1 (LB1) is programmed. Program the Fuse bits before programming the Lock bits.
20.2.1
20.3
Latching of Fuses
The fuse values are latched when the device enters programming mode and changes of the
fuse values will have no effect until the part leaves Programming mode. This does not apply to
the EESAVE Fuse which will take effect once it is programmed. The fuses are also latched on
Power-up in Normal mode.
Signature Bytes
All Atmel microcontrollers have a three-byte signature code which identifies the device. This
code can be read in both serial and parallel mode, also when the device is locked. The three
bytes reside in a separate address space. For the ATtiny48/88 the signature bytes are given in
Table 20-6.
Table 20-6.
Device ID
Signature Bytes Address
20.4
Part
0x000
0x001
0x002
ATtiny48
0x1E
0x92
0x09
ATtiny88
0x1E
0x93
0x11
Calibration Byte
The ATtiny48/88 has a byte calibration value for the internal oscillator. This byte resides in the
high byte of address 0x000 in the signature address space. During reset, this byte is automatically written into the OSCCAL Register to ensure correct frequency of the calibrated oscillator.
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20.5
Page Size
Table 20-7.
Device
Flash Size
Page Size
PCWORD
No. of
Pages
PCPAGE
PCMSB
ATtiny48
2K words
(4K bytes)
32 words
PC[4:0]
64
PC[10:5]
10
ATtiny88
4K words
(8K bytes)
32 words
PC[4:0]
128
PC[11:5]
11
Table 20-8.
20.6
No. of Words in a Page and No. of Pages in the Flash
No. of Words in a Page and No. of Pages in the EEPROM
Device
EEPROM
Size
Page
Size
PCWORD
No. of
Pages
PCPAGE
EEAMSB
ATtiny48
64 bytes
4 bytes
EEA[1:0]
16
EEA[5:2]
5
ATtiny88
64 bytes
4 bytes
EEA[1:0]
16
EEA[5:2]
5
Parallel Programming Parameters, Pin Mapping, and Commands
This section describes how to parallel program and verify Flash Program memory, EEPROM
Data memory, Memory Lock bits, and Fuse bits in the ATtiny48/88. Pulses are assumed to be at
least 250 ns unless otherwise noted.
20.6.1
Signal Names
In this section, some pins of the ATtiny48/88 are referenced by signal names describing their
functionality during parallel programming, see Figure 20-1 and Table 20-9. Pins not described in
the following table are referenced by pin names.
Figure 20-1. Parallel Programming
+4.5 - 5.5V
RDY/BSY
PD1
OE
PD2
WR
PD3
BS1
PD4
XA0
PD5
XA1
PD6
PAGEL
PD7
+12 V
BS2
VCC
+4.5 - 5.5V
AVCC
PC[1:0]:PB[5:0]
DATA
RESET
PC2
CLKI
GND
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Table 20-9.
Pin Name Mapping
Signal Name in
Programming Mode
Pin Name
I/O
Function
RDY/BSY
PD1
O
0: Device is busy programming, 1: Device is
ready for new command
OE
PD2
I
Output Enable (Active low)
WR
PD3
I
Write Pulse (Active low)
BS1
PD4
I
Byte Select 1 (“0” selects Low byte, “1” selects
High byte)
XA0
PD5
I
XTAL Action Bit 0
XA1
PD6
I
XTAL Action Bit 1
PAGEL
PD7
I
Program memory and EEPROM Data Page
Load
BS2
PC2
I
Byte Select 2 (“0” selects Low byte, “1” selects
2’nd High byte)
DATA
{PC[1:0]: PB[5:0]}
I/O
Bi-directional Data bus (Output when OE is low)
Note:
VCC - 0.3V < AVCC < VCC + 0.3V, however, AVCC should always be within 4.5 – 5.5V
Table 20-10. Pin Values Used to Enter Programming Mode
Pin
Symbol
Value
PAGEL
Prog_enable[3]
0
XA1
Prog_enable[2]
0
XA0
Prog_enable[1]
0
BS1
Prog_enable[0]
0
The XA1/XA0 pins determine the action executed when the CLKI pin is given a positive pulse.
The bit coding is shown in Table 20-11.
Table 20-11. XA1 and XA0 Coding
188
XA1
XA0
Action when CLKI is Pulsed
0
0
Load Flash or EEPROM Address (High or low address byte determined by BS1).
0
1
Load Data (High or Low data byte for Flash determined by BS1).
1
0
Load Command
1
1
No Action, Idle
ATtiny48/88
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ATtiny48/88
When pulsing WR or OE, the command loaded determines the action executed. The different
Commands are shown in Table 20-12.
Table 20-12. Command Byte Bit Coding
Command Byte
20.7
20.7.1
Command Executed
1000 0000
Chip Erase
0100 0000
Write Fuse bits
0010 0000
Write Lock bits
0001 0000
Write Flash
0001 0001
Write EEPROM
0000 1000
Read Signature Bytes and Calibration byte
0000 0100
Read Fuse and Lock bits
0000 0010
Read Flash
0000 0011
Read EEPROM
Parallel Programming
Enter Programming Mode
The following algorithm puts the device in Parallel (High-voltage) Programming mode:
1. Set Prog_enable pins listed in Table 20-10 on page 188 to “0000”, RESET pin to 0V
and VCC to 0V.
2. Apply 4.5 – 5.5V between VCC and GND.
Ensure that VCC reaches at least 1.8V within the next 20 µs.
3. Wait 20 – 60 µs, and apply 11.5 – 12.5V to RESET.
4. Keep the Prog_enable pins unchanged for at least 10µs after the High-voltage has
been applied to ensure the Prog_enable Signature has been latched.
5. Wait at least 300 µs before giving any parallel programming commands.
6. Exit Programming mode by power the device down or by bringing RESET pin to 0V.
If the rise time of the VCC is unable to fulfill the requirements listed above, the following alternative algorithm can be used.
1. Set Prog_enable pins listed in Table 20-10 on page 188 to “0000”, RESET pin to 0V
and VCC to 0V.
2. Apply 4.5 – 5.5V between VCC and GND.
3. Monitor VCC, and as soon as VCC reaches 0.9 – 1.1V, apply 11.5 – 12.5V to RESET.
4. Keep the Prog_enable pins unchanged for at least 10µs after the High-voltage has
been applied to ensure the Prog_enable Signature has been latched.
5. Wait until VCC actually reaches 4.5 -5.5V before giving any parallel programming
commands.
6. Exit Programming mode by power the device down or by bringing RESET pin to 0V.
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20.7.2
Considerations for Efficient Programming
The loaded command and address are retained in the device during programming. For efficient
programming, the following should be considered.
• The command needs only be loaded once when writing or reading multiple memory
locations.
• Skip writing the data value 0xFF, that is the contents of the entire EEPROM (unless the
EESAVE Fuse is programmed) and Flash after a Chip Erase.
• Address high byte needs only be loaded before programming or reading a new 256 word
window in Flash or 256 byte EEPROM. This consideration also applies to Signature bytes
reading.
20.7.3
Chip Erase
The Chip Erase will erase the Flash and EEPROM(Note:) memories plus Lock bits. The Lock bits
are not reset until the program memory has been completely erased. The Fuse bits are not
changed. A Chip Erase must be performed before the Flash and/or EEPROM are
reprogrammed.
Note:
The EEPROM memory is preserved during Chip Erase if the EESAVE Fuse is programmed.
Load Command “Chip Erase”:
1. Set XA1, XA0 to “10”. This enables command loading.
2. Set BS1 to “0”.
3. Set DATA to “1000 0000”. This is the command for Chip Erase.
4. Give CLKI a positive pulse. This loads the command.
5. Give WR a negative pulse. This starts the Chip Erase. RDY/BSY goes low.
6. Wait until RDY/BSY goes high before loading a new command.
20.7.4
Programming the Flash
The Flash is organized in pages, see Table 20-7 on page 187. When programming the Flash,
the program data is latched into a page buffer. This allows one page of program data to be programmed simultaneously. The following procedure describes how to program the entire Flash
memory:
A. Load Command “Write Flash”
1. Set XA1, XA0 to “10”. This enables command loading.
2. Set BS1 to “0”.
3. Set DATA to “0001 0000”. This is the command for Write Flash.
4. Give CLKI a positive pulse. This loads the command.
B. Load Address Low byte
1. Set XA1, XA0 to “00”. This enables address loading.
2. Set BS1 to “0”. This selects low address.
3. Set DATA = Address low byte (0x00 – 0xFF).
4. Give CLKI a positive pulse. This loads the address low byte.
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C. Load Data Low Byte
1. Set XA1, XA0 to “01”. This enables data loading.
2. Set DATA = Data low byte (0x00 – 0xFF).
3. Give CLKI a positive pulse. This loads the data byte.
D. Load Data High Byte
1. Set BS1 to “1”. This selects high data byte.
2. Set XA1, XA0 to “01”. This enables data loading.
3. Set DATA = Data high byte (0x00 – 0xFF).
4. Give CLKI a positive pulse. This loads the data byte.
E. Latch Data
1. Set BS1 to “1”. This selects high data byte.
2. Give PAGEL a positive pulse. This latches the data bytes. (See Figure 20-3 for signal
waveforms)
F. Repeat B through E until the entire buffer is filled or until all data within the page is loaded.
While the lower bits in the address are mapped to words within the page, the higher bits address
the pages within the FLASH. This is illustrated in Figure 20-2 on page 192. Note that if less than
eight bits are required to address words in the page (pagesize < 256), the most significant bit(s)
in the address low byte are used to address the page when performing a Page Write.
G. Load Address High byte
1. Set XA1, XA0 to “00”. This enables address loading.
2. Set BS1 to “1”. This selects high address.
3. Set DATA = Address high byte (0x00 – 0xFF).
4. Give CLKI a positive pulse. This loads the address high byte.
H. Program Page
1. Give WR a negative pulse. This starts programming of the entire page of data.
RDY/BSY goes low.
2. Wait until RDY/BSY goes high (See Figure 20-3 for signal waveforms).
I. Repeat B through H until the entire Flash is programmed or until all data has been
programmed.
J. End Page Programming
1. 1. Set XA1, XA0 to “10”. This enables command loading.
2. Set DATA to “0000 0000”. This is the command for No Operation.
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3. Give CLKI a positive pulse. This loads the command, and the internal write signals are
reset.
Figure 20-2. Addressing the Flash Which is Organized in Pages(1)
PCMSB
PROGRAM
COUNTER
PAGEMSB
PCPAGE
PCWORD
PAGE ADDRESS
WITHIN THE FLASH
WORD ADDRESS
WITHIN A PAGE
PROGRAM MEMORY
PAGE
PAGE
PCWORD[PAGEMSB:0]:
00
INSTRUCTION WORD
01
02
PAGEEND
Note:
1. PCPAGE and PCWORD are listed in Table 20-7 on page 187.
Figure 20-3. Programming the Flash Waveforms(1)
F
DATA
A
B
0x10
ADDR. LOW
C
DATA LOW
D
E
DATA HIGH
XX
B
ADDR. LOW
C
D
DATA LOW
DATA HIGH
E
XX
G
H
ADDR. HIGH
XX
XA1
XA0
BS1
CLKI
WR
RDY/BSY
RESET +12V
OE
PAGEL
BS2
Note:
20.7.5
192
1. “XX” is don’t care. The letters refer to the programming description above.
Programming the EEPROM
The EEPROM is organized in pages, see Table 20-8 on page 187. When programming the
EEPROM, the program data is latched into a page buffer. This allows one page of data to be
programmed simultaneously. The programming algorithm for the EEPROM data memory is as
ATtiny48/88
8008C–AVR–03/09
ATtiny48/88
follows (refer to “Programming the Flash” on page 190 for details on Command, Address and
Data loading):
1. A: Load Command “0001 0001”.
2. G: Load Address High Byte (0x00 – 0xFF).
3. B: Load Address Low Byte (0x00 – 0xFF).
4. C: Load Data (0x00 – 0xFF).
5. E: Latch data (give PAGEL a positive pulse).
K: Repeat 3 through 5 until the entire buffer is filled.
L: Program EEPROM page
1. Set BS1 to “0”.
2. Give WR a negative pulse. This starts programming of the EEPROM page. RDY/BSY
goes low.
3. Wait until to RDY/BSY goes high before programming the next page (See Figure 20-4
for signal waveforms).
Figure 20-4. Programming the EEPROM Waveforms
K
DATA
A
G
0x11
ADDR. HIGH
B
ADDR. LOW
C
E
DATA
XX
B
ADDR. LOW
C
DATA
E
L
XX
XA1
XA0
BS1
CLKI
WR
RDY/BSY
RESET +12V
OE
PAGEL
BS2
20.7.6
Reading the Flash
The algorithm for reading the Flash memory is as follows (refer to “Programming the Flash” on
page 190 for details on Command and Address loading):
1. A: Load Command “0000 0010”.
2. G: Load Address High Byte (0x00 – 0xFF).
3. B: Load Address Low Byte (0x00 – 0xFF).
4. Set OE to “0”, and BS1 to “0”. The Flash word low byte can now be read at DATA.
5. Set BS1 to “1”. The Flash word high byte can now be read at DATA.
6. Set OE to “1”.
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20.7.7
Reading the EEPROM
The algorithm for reading the EEPROM memory is as follows (refer to “Programming the Flash”
on page 190 for details on Command and Address loading):
1. A: Load Command “0000 0011”.
2. G: Load Address High Byte (0x00 – 0xFF).
3. B: Load Address Low Byte (0x00 – 0xFF).
4. Set OE to “0”, and BS1 to “0”. The EEPROM Data byte can now be read at DATA.
5. Set OE to “1”.
20.7.8
Programming the Fuse Low Bits
The algorithm for programming the Fuse Low bits is as follows (refer to “Programming the Flash”
on page 190 for details on Command and Data loading):
1. A: Load Command “0100 0000”.
2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.
3. Give WR a negative pulse and wait for RDY/BSY to go high.
20.7.9
Programming the Fuse High Bits
The algorithm for programming the Fuse High bits is as follows (refer to “Programming the
Flash” on page 190 for details on Command and Data loading):
1. A: Load Command “0100 0000”.
2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.
3. Set BS1 to “1” and BS2 to “0”. This selects high data byte.
4. Give WR a negative pulse and wait for RDY/BSY to go high.
5. Set BS1 to “0”. This selects low data byte.
20.7.10
Programming the Fuse Extended Bits
The algorithm for programming the Fuse Extended bits is as follows (refer to “Programming the
Flash” on page 190 for details on Command and Data loading):
1. 1. A: Load Command “0100 0000”.
2. 2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.
3. 3. Set BS1 to “0” and BS2 to “1”. This selects extended data byte.
4. 4. Give WR a negative pulse and wait for RDY/BSY to go high.
5. 5. Set BS2 to “0”. This selects low data byte.
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Figure 20-5. Programming the FUSES Waveforms
Write Fuse Low byte
DATA
A
C
0x40
DATA
XX
Write Fuse high byte
A
C
0x40
DATA
XX
Write Extended Fuse byte
A
C
0x40
DATA
XX
XA1
XA0
BS1
BS2
CLKI
WR
RDY/BSY
RESET +12V
OE
PAGEL
20.7.11
Programming the Lock Bits
The algorithm for programming the Lock bits is as follows (refer to “Programming the Flash” on
page 190 for details on Command and Data loading):
1. A: Load Command “0010 0000”.
2. C: Load Data Low Byte. Bit n = “0” programs the Lock bit. If LB mode 3 is programmed
(LB1 and LB2 is programmed), it is not possible to program the Lock Bits by any External Programming mode.
3. Give WR a negative pulse and wait for RDY/BSY to go high.
The Lock bits can only be cleared by executing Chip Erase.
20.7.12
Reading the Fuse and Lock Bits
The algorithm for reading the Fuse and Lock bits is as follows (refer to “Programming the Flash”
on page 190 for details on Command loading):
1. A: Load Command “0000 0100”.
2. Set OE to “0”, BS2 to “0” and BS1 to “0”. The status of the Fuse Low bits can now be
read at DATA (“0” means programmed).
3. Set OE to “0”, BS2 to “1” and BS1 to “1”. The status of the Fuse High bits can now be
read at DATA (“0” means programmed).
4. Set OE to “0”, BS2 to “1”, and BS1 to “0”. The status of the Fuse Extended bits can now
be read at DATA (“0” means programmed).
5. Set OE to “0”, BS2 to “0” and BS1 to “1”. The status of the Lock bits can now be read at
DATA (“0” means programmed).
6. Set OE to “1”.
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Figure 20-6. Mapping Between BS1, BS2 and the Fuse and Lock Bits During Read
0
Fuse Low Byte
0
Extended Fuse Byte
1
DATA
BS2
0
Lock Bits
1
Fuse High Byte
1
BS1
BS2
20.7.13
Reading the Signature Bytes
The algorithm for reading the Signature bytes is as follows (refer to “Programming the Flash” on
page 190 for details on Command and Address loading):
1. A: Load Command “0000 1000”.
2. B: Load Address Low Byte (0x00 – 0x02).
3. Set OE to “0”, and BS1 to “0”. The selected Signature byte can now be read at DATA.
4. Set OE to “1”.
20.7.14
Reading the Calibration Byte
The algorithm for reading the Calibration byte is as follows (refer to “Programming the Flash” on
page 190 for details on Command and Address loading):
1. A: Load Command “0000 1000”.
2. B: Load Address Low Byte, 0x00.
3. Set OE to “0”, and BS1 to “1”. The Calibration byte can now be read at DATA.
4. Set OE to “1”.
20.8
Serial Downloading
Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while
RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (output). After RESET is set low, the Programming Enable instruction needs to be executed first
before program/erase operations can be executed. NOTE, in Table 20-13 on page 197, the pin
mapping for SPI programming is listed. Not all parts use the SPI pins dedicated for the internal
SPI interface.
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Figure 20-7. Serial Programming and Verify(1)
+1.8 - 5.5V
VCC
+1.8 - 5.5V(2)
MOSI
AVCC
MISO
SCK
CLKI
RESET
GND
Notes:
1. If the device is clocked by the internal oscillator, it is no need to connect a clock source to the
CLKI pin.
2. VCC - 0.3V < AVCC < VCC + 0.3V, however, AVCC should always be within 1.8 – 5.5V
When programming the EEPROM, an auto-erase cycle is built into the self-timed programming
operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase
instruction. The Chip Erase operation turns the content of every memory location in both the
Program and EEPROM arrays into 0xFF.
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods
for the serial clock (SCK) input are defined as follows:
Low:> 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz
High:> 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz
20.8.1
Serial Programming Pin Mapping
Table 20-13. Pin Mapping Serial Programming
Symbol
Pins
I/O
Description
MOSI
PB3
I
Serial Data in
MISO
PB4
O
Serial Data out
SCK
PB5
I
Serial Clock
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20.8.2
Serial Programming Algorithm
When writing serial data to the ATtiny48/88, data is clocked on the rising edge of SCK.
When reading data from the ATtiny48/88, data is clocked on the falling edge of SCK. See Figure
21-9 on page 213 and Figure 21-10 on page 213 for timing details.
To program and verify the ATtiny48/88 in the serial programming mode, the following sequence
is recommended (See Serial Programming Instruction set in Table 20-15 on page 199):
1. Power-up sequence:
Apply power between VCC and GND while RESET and SCK are set to “0”. In some systems, the programmer can not guarantee that SCK is held low during power-up. In this
case, RESET must be given a positive pulse of at least two CPU clock cycles duration
after SCK has been set to “0”.
2. Wait for at least 20 ms and enable serial programming by sending the Programming
Enable serial instruction to pin MOSI.
3. The serial programming instructions will not work if the communication is out of synchronization. When in sync. the second byte (0x53), will echo back when issuing the
third byte of the Programming Enable instruction. Whether the echo is correct or not, all
four bytes of the instruction must be transmitted. If the 0x53 did not echo back, give
RESET a positive pulse and issue a new Programming Enable command.
4. The Flash is programmed one page at a time. The memory page is loaded one byte at
a time by supplying the 6 LSB of the address and data together with the Load Program
Memory Page instruction. To ensure correct loading of the page, the data low byte must
be loaded before data high byte is applied for a given address. The Program Memory
Page is stored by loading the Write Program Memory Page instruction with the 7 MSB
of the address. If polling (RDY/BSY) is not used, the user must wait at least tWD_FLASH
before issuing the next page (See Table 20-14). Accessing the serial programming
interface before the Flash write operation completes can result in incorrect
programming.
5. A: The EEPROM array is programmed one byte at a time by supplying the address and
data together with the appropriate Write instruction. An EEPROM memory location is
first automatically erased before new data is written. If polling (RDY/BSY) is not used,
the user must wait at least tWD_EEPROM before issuing the next byte (See Table 20-14).
In a chip erased device, no 0xFFs in the data file(s) need to be programmed.
B: The EEPROM array is programmed one page at a time. The Memory page is loaded
one byte at a time by supplying the 6 LSB of the address and data together with the
Load EEPROM Memory Page instruction. The EEPROM Memory Page is stored by
loading the Write EEPROM Memory Page Instruction with the 7 MSB of the address.
When using EEPROM page access only byte locations loaded with the Load EEPROM
Memory Page instruction is altered. The remaining locations remain unchanged. If polling (RDY/BSY) is not used, the used must wait at least tWD_EEPROM before issuing the
next byte (See Table 20-14). In a chip erased device, no 0xFF in the data file(s) need to
be programmed.
6. Any memory location can be verified by using the Read instruction which returns the
content at the selected address at serial output MISO.
7. At the end of the programming session, RESET can be set high to commence normal
operation.
8. Power-off sequence (if needed):
Set RESET to “1”.
Turn VCC power off.
198
ATtiny48/88
8008C–AVR–03/09
ATtiny48/88
Table 20-14. Typical Wait Delay Before Writing the Next Flash or EEPROM Location
20.8.3
Symbol
Minimum Wait Delay
tWD_FLASH
4.5 ms
tWD_EEPROM
3.6 ms
tWD_ERASE
9.0 ms
Serial Programming Instruction set
Table 20-15 on page 199 and Figure 20-8 on page 200 describes the Instruction set.
Table 20-15. Serial Programming Instruction Set (Hexadecimal values)
Instruction Format
Instruction/Operation
Byte 1
Byte 2
Byte 3
Byte4
Programming Enable
$AC
$53
$00
$00
Chip Erase (Program Memory/EEPROM)
$AC
$80
$00
$00
Poll RDY/BSY
$F0
$00
$00
data byte out
Load Extended Address byte(1)
$4D
$00
Extended adr
$00
Load Program Memory Page, High byte
$48
$00
adr LSB
high data byte in
Load Program Memory Page, Low byte
$40
$00
adr LSB
low data byte in
Load EEPROM Memory Page (page access)
$C1
$00
0000 000aa
data byte in
Read Program Memory, High byte
$28
adr MSB
adr LSB
high data byte out
Read Program Memory, Low byte
$20
adr MSB
adr LSB
low data byte out
Read EEPROM Memory
$A0
0000 00aa
aaaa aaaa
data byte out
Read Lock bits
$58
$00
$00
data byte out
Read Signature Byte
$30
$00
0000 000aa
data byte out
Read Fuse bits
$50
$00
$00
data byte out
Read Fuse High bits
$58
$08
$00
data byte out
Read Fuse Extended Bits
$50
$08
$00
data byte out
Read Calibration Byte
$38
$00
$00
data byte out
Write Program Memory Page
$4C
adr MSB
adr LSB
$00
Write EEPROM Memory
$C0
0000 00aa
aaaa aaaa
data byte in
Write EEPROM Memory Page (page access)
$C2
0000 00aa
aaaa aa00
$00
Write Lock bits
$AC
$E0
$00
data byte in
Write Fuse bits
$AC
$A0
$00
data byte in
Write Fuse High bits
$AC
$A8
$00
data byte in
Write Fuse Extended Bits
$AC
$A4
$00
data byte in
Load Instructions
Read Instructions
Write Instructions
199
8008C–AVR–03/09
Notes:
1.
2.
3.
4.
5.
Not all instructions are applicable for all parts.
a = address.
Bits are programmed ‘0’, unprogrammed ‘1’.
To ensure future compatibility, unused Fuses and Lock bits should be unprogrammed (‘1’) .
Refer to the correspondig section for Fuse and Lock bits, Calibration and Signature bytes and
Page size.
6. See htt://www.atmel.com/avr for Application Notes regarding programming and programmers.
If the LSB in RDY/BSY data byte out is ‘1’, a programming operation is still pending. Wait until
this bit returns ‘0’ before the next instruction is carried out.
Within the same page, the low data byte must be loaded prior to the high data byte.
After data is loaded to the page buffer, program the EEPROM page, see Figure 20-8 on page
200.
Figure 20-8. Serial Programming Instruction example
Serial Programming Instruction
Load Program Memory Page (High/Low Byte)/
Load EEPROM Memory Page (page access)
Byte 1
Byte 2
Adr
A
drr MS
M
MSB
SB
Bit 15 B
Byte 3
Write Program Memory Page/
Write EEPROM Memory Page
Byte 1
Byte 4
Byte 2
Adr LSB
Adr MSB
Bit 15 B
0
Byte 3
Byte 4
Adr
A
dr LS
LSB
SB
0
Page Buffer
Page Offset
Page 0
Page 1
Page 2
Page Number
Page N-1
Program Memory/
EEPROM Memory
200
ATtiny48/88
8008C–AVR–03/09
ATtiny48/88
21. Electrical Characteristics
21.1
Absolute Maximum Ratings*
Operating Temperature.................................. -55°C to +125°C
*NOTICE:
Storage Temperature ..................................... -65°C to +150°C
Voltage on any Pin except RESET
with respect to Ground ................................-0.5V to VCC+0.5V
Voltage on RESET with respect to Ground......-0.5V to +13.0V
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Maximum Operating Voltage ............................................ 6.0V
DC Current per I/O Pin ............................................... 40.0 mA
DC Current VCC and GND Pins................................ 200.0 mA
21.2
DC Characteristics
TA = -40°C to 85°C, VCC = 1.8V to 5.5V (unless otherwise noted) (1)
Symbol
Parameter
Input Low Voltage,
Except RESET pin
VIL
Input Low Voltage,
RESET pin as reset (3)
Input High Voltage,
Except RESET pin
VIH
Input High Voltage,
RESET pin as reset (3)
Output Low Voltage (5),
Except High Sink I/O pins
and RESET pin as I/O (6)
VOL
Output Low Voltage
High Sink I/O pins (7)
Output Low Voltage (3)
RESET pin as I/O (6)
Output High Voltage (8),
Except High Sink I/O pins
and RESET pin as I/O (6)
VOH
Output HighVoltage
High Sink I/O pins (7)
Condition
Min
Typ
Max
Units
(2)
V
VCC = 1.8V – 2.4V
-0.5
0.2VCC
VCC = 2.4V – 5.5V
-0.5
0.3VCC(2)
V
VCC = 1.8V – 5.5V
-0.5
0.2VCC(2)
V
VCC = 1.8V – 2.4V
0.7VCC(4)
VCC + 0.5
V
VCC = 2.4V – 5.5V
0.6VCC
(4)
VCC + 0.5
V
VCC = 1.8V – 5.5V
0.9VCC(4)
VCC + 0.5
V
IOL = 10 mA, VCC = 5V
0.7
V
IOL = 5 mA, VCC = 3V
0.5
V
IOL = 2 mA, VCC = 1.8V
0.4
V
IOL = 20 mA, VCC = 5V
0.7
V
IOL = 10 mA, VCC = 3V
0.5
V
IOL = 4 mA, VCC = 1.8V
0.4
V
IOL = 2 mA, VCC = 5V
0.7
V
IOL = 1 mA, VCC = 3V
0.5
V
IOL = 0.4 mA, VCC = 1.8V
0.4
V
IOH = -10 mA, VCC = 5V
4.3
V
IOH = -5 mA, VCC = 3V
2.5
V
IOH = -2 mA, VCC = 1.8V
1.4
V
IOH = -10 mA, VCC = 5V
4.3
V
IOH = -5 mA, VCC = 3V
2.5
V
IOH = -2 mA, VCC = 1.8V
1.4
V
201
8008C–AVR–03/09
TA = -40°C to 85°C, VCC = 1.8V to 5.5V (unless otherwise noted) (1) (Continued)
Symbol
Parameter
Condition
ILIL
Input Leakage
Current I/O Pin
ILIH
RPU
Typ
Max
Units
VCC = 5.5V, pin low
(absolute value)
<0.05
1 (9)
µA
Input Leakage
Current I/O Pin
VCC = 5.5V, pin high
(absolute value)
<0.05
1 (9)
µA
Pull-up Resistor, I/O Pin
VCC = 5.5V, input low
20
50
kΩ
Pull-up Resistor, Reset Pin
VCC = 5.5V, input low
30
60
kΩ
Supply Current,
Active Mode (10)
ICC
Supply Current,
Idle Mode
Supply Current,
Power-Down Mode (11)
Notes:
Min
f = 1MHz, VCC = 2V
0.2
0.4
mA
f = 4MHz, VCC = 3V
1.4
2.5
mA
f = 8MHz, VCC = 5V
4.5
8
mA
f = 1MHz, VCC = 2V
0.03
0.1
mA
f = 4MHz, VCC = 3V
0.25
0.6
mA
f = 8MHz, VCC = 5V
1
2
mA
WDT enabled, VCC = 3V
4
10
µA
WDT disabled, VCC = 3V
< 0.2
2
µA
1. All DC Characteristics contained in this data sheet are based on simulation and characterization of other AVR microcontrollers manufactured in the same process technology. These values are preliminary, representing design targets, and will be
updated after characterization of actual silicon.
2. “Max” means the highest value where the pin is guaranteed to be read as low
3. These parameters are not tested in production.
4. “Min” means the lowest value where the pin is guaranteed to be read as high
5. Although each I/O port can sink more than the test conditions (10 mA at VCC = 5V, 5 mA at VCC = 3V, 2 mA at VCC = 1.8V)
under steady state conditions (non-transient), the following must be observed:
• The sum of all IOL, for ports A0, A3, B0 – B7, C7, D5 – D7 should not exceed TBD mA.
• The sum of all IOL, for ports A1 – A2, C0 – C6, D0 – D4 should not exceed TBD mA.
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test condition.
6. The RESET pin must tolerate high voltages when entering and operating in programming modes and, as a consequence,
has a weak drive strength as compared to regular I/O pins. See Figure 22-28, Figure 22-29, Figure 22-30, Figure 22-31, Figure 22-32 and Figure 22-33 (starting on page 229).
7. High Sink I/O pins are PD0, PD1, PD2 and PD3.
8. Although each I/O port can source more than the test conditions (10 mA at VCC = 5V, 5mA at VCC = 3V, 2 mA at VCC = 1.8V)
under steady state conditions (non-transient), the following must be observed:
• The sum of all IOH, for ports A2 – A3, B0 – B7, C6, D0 – D7 should not exceed TBD mA.
• The sum of all IOH, for ports A0 – A1, C0 – C5, C7 should not exceed TBD mA.
If IIOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current
greater than the listed test condition.
9. These are test limits, which account for leakage currents of the test environment. Actual device leakage currents are lower.
10. Measured with all I/O modules turned off (PRR = 0xFF).
11. Measured with Brown-Out Detection (BOD) disabled.
202
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ATtiny48/88
21.3
Speed Grades
Maximum frequency is dependent on VCC. As shown in Figure 21-1, the Maximum Frequency vs.
VCC curve is linear between 1.8V < VCC < 4.5V.
Figure 21-1. Maximum Frequency vs. VCC
12 MHz
4 MHz
4.5V
1.8V
21.4
21.4.1
5.5V
Clock Characterizations
Calibrated Internal Oscillator Accuracy
It is possible to manually calibrate the internal oscillator to be more accurate than default factory
calibration. Please note that the oscillator frequency depends on temperature and voltage. Voltage and temperature characteristics can be found in TBD.
Table 21-1.
Calibration Accuracy of Internal Oscillator
Calibration
Method
Target Frequency
VCC
Temperature
Accuracy at given
Voltage & Temperature(1)
8.0 MHz
3V
25°C
±10%
Fixed frequency within:
7.3 – 8.1 MHz
Fixed voltage within:
1.8V – 5.5V
Fixed temperature within:
-40°C – 85°C
±1%
Factory Calibration
User Calibration
Notes:
21.4.2
1. Accuracy of oscillator frequency at calibration point (fixed temperature and fixed voltage).
External Clock Drive
Figure 21-2. External Clock Drive Waveforms
V IH1
V IL1
203
8008C–AVR–03/09
Table 21-2.
External Clock Drive
VCC=1.8-5.5V
VCC=4.5-5.5V
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Units
1/tCLCL
Oscillator
Frequency
0
2
0
6
0
12
MHz
tCLCL
Clock Period
250
166
83
ns
tCHCX
High Time
120
80
40
ns
tCLCX
Low Time
120
80
40
ns
tCLCH
Rise Time
2.0
1.6
0.5
μs
tCHCL
Fall Time
2.0
1.6
0.5
μs
ΔtCLCL
Change in period
from one clock
cycle to the next
2
2
2
%
Note:
21.5
VCC=2.7-5.5V
All DC Characteristics contained in this datasheet are based on simulation and characterization of
other AVR microcontrollers manufactured in the same process technology. These values are preliminary, representing design targets, and will be updated after characterization of actual silicon.
System and Reset Characterizations
Table 21-3.
Symbol
VPOT
Reset, Brown-out, and Internal Voltage Characteristics (1)
Parameter
Condition
Power-on Reset Threshold
Voltage (rising)
TA = -40 – 85°C
1.5
V
Power-on Reset Threshold
Voltage (falling)(2)
TA = -40 – 85°C
1.2
V
VRST
RESET Pin Threshold
Voltage
tRST
Minimum pulse width on
RESET Pin
Min
Typ
0.9VCC
0.2 VCC
VCC = 1.8V
VCC = 3V
VCC = 5V
Max
Units
V
2000
700
400
ns
VHYST
Brown-out Detector
Hysteresis
50
mV
tBOD
Min Pulse Width on
Brown-out Reset
2
µs
VBG
Internal bandgap reference
voltage
VCC = 5V
TA = 25°C
tBG
Internal bandgap reference
start-up time
IBG
Internal bandgap reference
current consumption
Note:
1.0
1.1
1.2
V
VCC = 5V
TA = 25°C
40
70
µs
VCC = 5V
TA = 25°C
15
µA
1. Values are guidelines, only
2. The Power-on Reset will not work unless the supply voltage has been below VPOT (falling)
204
ATtiny48/88
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ATtiny48/88
Table 21-4.
VBOT vs. BODLEVEL Fuse Coding(1)
BODLEVEL [2..0] Fuses
Min
111
21.6
Max
110
1.7
1.8
2.0
101
2.5
2.7
2.9
100
4.1
4.3
4.5
Reserved
1. VBOT may be below nominal minimum operating voltage for some devices. For devices where
this is the case, the device is tested down to VCC = VBOT during the production test. This guarantees that a Brown-out Reset will occur before VCC drops to a voltage where correct
operation of the microcontroller is no longer guaranteed.
Analog Comparator Characteristics, TA = -40°C - 85°C
Symbol
Parameter
Condition
VAIO
Input Offset Voltage
VCC = 5V, VIN = VCC / 2
ILAC
Input Leakage Current
VCC = 5V, VIN = VCC / 2
Analog Propagation Delay
(from saturation to slight overdrive)
VCC = 2.7V
750
VCC = 4.0V
500
Analog Propagation Delay
(large step change)
VCC = 2.7V
100
VCC = 4.0V
75
Digital Propagation Delay
VCC = 1.8V - 5.5
1
tAPD
Note:
V
Analog Comparator Characteristics
Table 21-5.
tDPD
Units
BOD Disabled
0XX
Note:
Typ
Min
Typ
Max
Units
< 10
40
mV
50
nA
-50
ns
2
CLK
All parameters are based on simulation results and are not tested in production
205
8008C–AVR–03/09
21.7
ADC Characteristics – Preliminary Data
Table 21-6.
Symbol
ADC Characteristics , Single Ended Channels. -40°C – 85°C
Parameter
Condition
Min
Typ
Resolution
Absolute accuracy (Including
INL, DNL, quantization error,
gain and offset error)
Max
Units
10
Bits
VREF = 4V, VCC = 4V,
ADC clock = 200 kHz
2
LSB
VREF = 4V, VCC = 4V,
ADC clock = 1 MHz
3
LSB
VREF = 4V, VCC = 4V,
ADC clock = 200 kHz
Noise Reduction Mode
1.5
LSB
VREF = 4V, VCC = 4V,
ADC clock = 1 MHz
Noise Reduction Mode
2.5
LSB
Integral Non-Linearity (INL)
VREF = 4V, VCC = 4V,
ADC clock = 200 kHz
1
LSB
Differential Non-Linearity
(DNL)
VREF = 4V, VCC = 4V,
ADC clock = 200 kHz
0.5
LSB
Gain Error
VREF = 4V, VCC = 4V,
ADC clock = 200 kHz
2.5
LSB
Offset Error
VREF = 4V, VCC = 4V,
ADC clock = 200 kHz
1.5
LSB
Conversion Time
Free Running Conversion
Clock Frequency
13
260
µs
50
1000
kHz
VCC - 0.3
VCC + 0.3
V
AVCC
Analog Supply Voltage (2)
VREF
Reference Voltage
VINT
AVCC
V
Input Voltage
GND
VREF
V
VIN
Input Bandwidth
38.5
VINT
Internal Voltage Reference
RREF
Reference Input Resistance
32
kΩ
RAIN
Analog Input Resistance
100
MΩ
Notes:
1.0
1.1
kHz
1.2
V
1. Values are preliminary.
2. AVCC absolute min/max: 1.8V/5.5V
206
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ATtiny48/88
21.8
2-wire Serial Interface Characteristics
Table 21-7 describes the requirements for devices connected to the 2-wire Serial Bus. The ATtiny48/88 2-wire Serial Interface meets or exceeds these requirements under the noted conditions.
Timing symbols refer to Figure 21-3.
Table 21-7.
2-wire Serial Bus Requirements
Symbol
Parameter
VIL
VIH
Vhys
(1)
(1)
VOL
(1)
Min
Max
Unit
Input Low-voltage
-0.5
0.3 VCC
V
Input High-voltage
0.7 VCC
VCC + 0.5
V
0.05 VCC(2)
–
V
0
Hysteresis of Schmitt Trigger Inputs
Output Low-voltage
tr
Rise Time for both SDA and SCL
(1)
tof
Output Fall Time from VIHmin to VILmax
(1)
tSP
Spikes Suppressed by Input Filter
Ii
Input Current each I/O Pin
Ci(1)
Capacitance for each I/O Pin
fSCL
SCL Clock Frequency
Rp
tHD;STA
3 mA sink current
Hold Time (repeated) START Condition
Low Period of the SCL Clock
tHIGH
High period of the SCL clock
tSU;STA
Set-up time for a repeated START condition
tHD;DAT
Data hold time
tSU;DAT
Data setup time
tSU;STO
Setup time for STOP condition
tBUF
Bus free time between a STOP and START
condition
0.4
V
(3)(2)
300
ns
20 + 0.1Cb(3)(2)
250
ns
(2)
ns
20 + 0.1Cb
10 pF < Cb < 400 pF(3)
0
0.1VCC < Vi < 0.9VCC
fCK(4) > max(16fSCL, 250kHz)(5)
50
-10
10
µA
–
10
pF
0
400
kHz
fSCL ≤ 100 kHz
V CC – 0,4V
---------------------------3mA
1000ns
------------------Cb
Ω
fSCL > 100 kHz
V CC – 0,4V
---------------------------3mA
300ns
---------------Cb
Ω
fSCL ≤ 100 kHz
4.0
–
µs
fSCL > 100 kHz
0.6
–
µs
fSCL ≤ 100 kHz
(6)
4.7
–
µs
fSCL > 100 kHz(7)
1.3
–
µs
fSCL ≤ 100 kHz
4.0
–
µs
fSCL > 100 kHz
0.6
–
µs
fSCL ≤ 100 kHz
4.7
–
µs
fSCL > 100 kHz
0.6
–
µs
fSCL ≤ 100 kHz
0
3.45
µs
fSCL > 100 kHz
0
0.9
µs
fSCL ≤ 100 kHz
250
–
ns
fSCL > 100 kHz
100
–
ns
fSCL ≤ 100 kHz
4.0
–
µs
fSCL > 100 kHz
0.6
–
µs
fSCL ≤ 100 kHz
4.7
–
µs
fSCL > 100 kHz
1.3
–
µs
Value of Pull-up resistor
tLOW
Notes:
Condition
1. This parameter is characterized, only, and not fully tested.
2. Required only for fSCL > 100 kHz.
3. Cb = capacitance of one bus line in pF.
207
8008C–AVR–03/09
4. fCK = CPU clock frequency
5. This requirement applies to all 2-wire serial interface operation in ATtiny48/88. Other devices connected to the 2-wire serial
bus need only obey the general fSCL requirement.
6. The actual low period generated by the 2-wire serial interface of ATtiny48/88 is (1/fSCL - 2/fCK), thus fCK must be greater than
6 MHz for the low time requirement to be strictly met at fSCL = 100 kHz.
7. The actual low period generated by the 2-wire serial interface of ATtiny48/88 is (1/fSCL - 2/fCK), thus the low time requirement
will not be strictly met for fSCL > 308 kHz when fCK = 8 MHz. Still, ATtiny48/88 devices connected to the bus may communicate at full speed (400 kHz) with other ATtiny48/88 devices, as well as any other device with a proper tLOW acceptance
margin.
Figure 21-3. 2-wire Serial Bus Timing
tof
tHIGH
tLOW
tr
tLOW
SCL
tSU;STA
tHD;STA
SDA
tHD;DAT
tSU;DAT
tSU;STO
tBUF
208
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8008C–AVR–03/09
ATtiny48/88
21.9
SPI Characteristics
See Figure 21-4 and Figure 21-5 for details.
Table 21-8.
SPI Timing Parameters
Description
Mode
1
SCK period
Master
See Table 14-5
2
SCK high/low
Master
50% duty cycle
3
Rise/Fall time
Master
3.6
4
Setup
Master
10
5
Hold
Master
10
6
Out to SCK
Master
0.5 • tsck
7
SCK to out
Master
10
8
SCK to out high
Master
10
9
SS low to out
Slave
15
10
SCK period
Slave
4 • tck
11
SCK high/low(1)
Slave
2 • tck
12
Rise/Fall time
Slave
13
Setup
Slave
10
14
Hold
Slave
tck
15
SCK to out
Slave
16
SCK to SS high
Slave
17
SS high to tri-state
Slave
18
SS low to SCK
Slave
Note:
Min
Typ
Max
ns
1600
15
20
10
20
1. In SPI Programming mode the minimum SCK high/low period is:
- 2 tCLCL for fCK < 12 MHz
- 3 tCLCL for fCK > 12 MHz
2. All DC Characteristics contained in this datasheet are based on simulation and characterization of other AVR microcontrollers manufactured in the same process technology. These
values are preliminary values representing design targets, and will be updated after characterization of actual silicon.
209
8008C–AVR–03/09
Figure 21-4. SPI Interface Timing Requirements (Master Mode)
SS
6
1
SCK
(CPOL = 0)
2
2
SCK
(CPOL = 1)
4
MISO
(Data Input)
5
3
MSB
...
LSB
7
MOSI
(Data Output)
MSB
8
...
LSB
Figure 21-5. SPI Interface Timing Requirements (Slave Mode)
SS
10
9
16
SCK
(CPOL = 0)
11
11
SCK
(CPOL = 1)
13
MOSI
(Data Input)
14
12
MSB
...
LSB
17
15
MISO
(Data Output)
210
MSB
...
LSB
X
ATtiny48/88
8008C–AVR–03/09
ATtiny48/88
21.10 Parallel Programming Characteristics
Figure 21-6. Parallel Programming Timing, Including some General Timing Requirements
tXLWL
tXHXL
CLKI
tDVXH
tXLDX
tBVPH
tPLBX t BVWL
Data & Contol
(DATA, XA0/1, BS1, BS2)
PAGEL
tWLBX
tPHPL
tWLWH
WR
tPLWL
WLRL
RDY/BSY
tWLRH
Figure 21-7. Parallel Programming Timing, Loading Sequence with Timing Requirements(1)
LOAD ADDRESS
(LOW BYTE)
LOAD DATA LOAD DATA
(HIGH BYTE)
LOAD DATA
(LOW BYTE)
t XLXH
tXLPH
LOAD ADDRESS
(LOW BYTE)
tPLXH
CLKI
BS1
PAGEL
z
DATA
ADDR0 (Low Byte)
DATA (Low Byte)
DATA (High Byte)
ADDR1 (Low Byte)
XA0
XA1
Note:
1. The timing requirements shown in Figure 21-6 (i.e., tDVXH, tXHXL, and tXLDX) also apply to loading operation.
211
8008C–AVR–03/09
Figure 21-8. Parallel Programming Timing, Reading Sequence (within the Same Page) with Timing Requirements(1)
LOAD ADDRESS
(LOW BYTE)
READ DATA
(LOW BYTE)
READ DATA
(HIGH BYTE)
LOAD ADDRESS
(LOW BYTE)
tXLOL
CLKI
tBVDV
BS1
tOLDV
OE
DATA
tOHDZ
ADDR0 (Low Byte)
ADDR1 (Low Byte)
DATA (High Byte)
DATA (Low Byte)
XA0
XA1
Note:
1. The timing requirements shown in Figure 21-6 (i.e., tDVXH, tXHXL, and tXLDX) also apply to reading operation.
Table 21-9.
Symbol
Parameter
Min
VPP
Programming Enable Voltage
11.5
IPP
Programming Enable Current
tDVXH
Data and Control Valid before CLKI High
67
ns
tXLXH
CLKI Low to CLKI High
200
ns
tXHXL
CLKI Pulse Width High
150
ns
tXLDX
Data and Control Hold after CLKI Low
67
ns
tXLWL
CLKI Low to WR Low
0
ns
tXLPH
CLKI Low to PAGEL high
0
ns
tPLXH
PAGEL low to CLKI high
150
ns
tBVPH
BS1 Valid before PAGEL High
67
ns
tPHPL
PAGEL Pulse Width High
150
ns
tPLBX
BS1 Hold after PAGEL Low
67
ns
tWLBX
BS2/1 Hold after WR Low
67
ns
tPLWL
PAGEL Low to WR Low
67
ns
tBVWL
BS1 Valid to WR Low
67
ns
tWLWH
WR Pulse Width Low
150
ns
tWLRL
WR Low to RDY/BSY Low
tWLRH
212
Parallel Programming Characteristics, TA = 25°C, VCC = 5V
(1)
WR Low to RDY/BSY High
Typ
Max
Units
12.5
V
250
μA
0
1
μs
3.7
4.5
ms
ATtiny48/88
8008C–AVR–03/09
ATtiny48/88
Table 21-9.
Symbol
Parallel Programming Characteristics, TA = 25°C, VCC = 5V (Continued)
Parameter
Min
(2)
tWLRH_CE
WR Low to RDY/BSY High for Chip Erase
tXLOL
CLKI Low to OE Low
0
tBVDV
BS1 Valid to DATA valid
0
tOLDV
tOHDZ
Notes:
Typ
7.5
Max
Units
9
ms
ns
250
ns
OE Low to DATA Valid
250
ns
OE High to DATA Tri-stated
250
ns
1.
tWLRH is valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock bits
commands.
2.
tWLRH_CE is valid for the Chip Erase command.
21.11 Serial Programming Characteristics
Figure 21-9. Serial Programming Timing
MOSI
SCK
tSLSH
tSHOX
tOVSH
tSHSL
MISO
tSLIV
Figure 21-10. Serial Programming Waveforms
SERIAL DATA INPUT
(MOSI)
MSB
LSB
SERIAL DATA OUTPUT
(MISO)
MSB
LSB
SERIAL CLOCK INPUT
(SCK)
SAMPLE
Table 21-10. Serial Programming Characteristics, TA = -40°C to 85°C, VCC = 1.8 – 5.5V
(Unless Otherwise Noted)
Symbol
Parameter
1/tCLCL
Oscillator Frequency (VCC = 2.7V – 5.5V)
tCLCL
1/tCLCL
Oscillator Period (VCC = 2.7V – 5.5V)
Oscillator Frequency (VCC = 4.5V – 5.5V)
Min
0
Typ
Max
Units
6
MHz
166
0
ns
12
MHz
213
8008C–AVR–03/09
Table 21-10. Serial Programming Characteristics, TA = -40°C to 85°C, VCC = 1.8 – 5.5V
(Unless Otherwise Noted) (Continued)
Symbol
214
Parameter
Min
Typ
Max
Units
tCLCL
Oscillator Period (VCC = 4.5V – 5.5V)
83
ns
tSHSL
SCK Pulse Width High
2 tCLCL*
ns
tSLSH
SCK Pulse Width Low
2 tCLCL*
ns
tOVSH
MOSI Setup to SCK High
tCLCL
ns
tSHOX
MOSI Hold after SCK High
2 tCLCL
ns
ATtiny48/88
8008C–AVR–03/09
ATtiny48/88
22. Typical Charateristics
The data contained in this section is largely based on simulations and characterization of similar
devices in the same process and design methods. Thus, the data should be treated as indications of how the part will behave.
The following charts show typical behavior. These figures are not tested during manufacturing.
All current consumption measurements are performed with all I/O pins configured as inputs and
with internal pull-ups enabled. A sine wave generator with rail-to-rail output is used as clock
source.
The power consumption in Power-down mode is independent of clock selection.
The current consumption is a function of several factors such as: operating voltage, operating
frequency, loading of I/O pins, switching rate of I/O pins, code executed and ambient temperature. The dominating factors are operating voltage and frequency.
The current drawn from capacitive loaded pins may be estimated (for one pin) as CL*VCC*f where
CL = load capacitance, VCC = operating voltage and f = average switching frequency of I/O pin.
The parts are characterized at frequencies higher than test limits. Parts are not guaranteed to
function properly at frequencies higher than the ordering code indicates.
The difference between current consumption in Power-down mode with Watchdog Timer
enabled and Power-down mode with Watchdog Timer disabled represents the differential current drawn by the Watchdog Timer.
22.1
Active Supply Current
Figure 22-1. Active Supply Current vs. Low Frequency (0.1 - 1.0 MHz)
ACTIVE SUPPLY CURRENT vs. LOW FREQUENCY
0.1 - 1.0 MHz
1
5.5 V
ICC (mA)
0.9
0.8
5.0 V
0.7
4.5 V
0.6
4.0 V
0.5
3.3 V
0.4
2.7 V
0.3
1.8 V
0.2
0.1
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Frequency (MHz)
215
8008C–AVR–03/09
Figure 22-2. Active Supply Current vs. Frequency (1 - 12 MHz)
ACTIVE SUPPLY CURRENT vs. FREQUENCY
1 - 12 MHz
8
5.5 V
7
5.0 V
6
4.5 V
ICC (mA)
5
4.0 V
4
3
3.3 V
2
2.7 V
1
1.8 V
0
0
2
4
6
8
10
12
Frequency (MHz)
Figure 22-3. Active Supply Current vs. VCC (Internal oscillator, 8 MHz)
ACTIVE SUPPLY CURRENT vs. VCC
INTERNAL RC OSCILLATOR, 8 MHz
7
6
85 °C
25 °C
5
ICC (mA)
-40 °C
4
3
2
1
0
1.5
2
2.5
3
3.5
4
4.5
5
5.5
VCC (V)
216
ATtiny48/88
8008C–AVR–03/09
ATtiny48/88
Figure 22-4. Active Supply Current vs. VCC (Internal Oscillator, 1 MHz)
ACTIVE SUPPLY CURRENT vs. VCC
INTERNAL RC OSCILLATOR, 1 MHz
1.2
85 °C
25 °C
-40 °C
1
ICC (mA)
0.8
0.6
0.4
0.2
0
1.5
2
2.5
3
3.5
4
4.5
5
5.5
VCC (V)
Figure 22-5. Active Supply Current vs. VCC (Internal Oscillator, 128 kHz)
ACTIVE SUPPLY CURRENT vs. VCC
INTERNAL RC OSCILLATOR, 128 KHz
0.15
-40 °C
25 °C
85 °C
ICC (mA)
0.1
0.05
0
1.5
2
2.5
3
3.5
4
4.5
5
5.5
VCC (V)
217
8008C–AVR–03/09
22.2
Idle Supply Current
Figure 22-6. Idle Supply Current vs. low Frequency (0.1 - 1.0 MHz)
IDLE SUPPLY CURRENT vs. LOW FREQUENCY
0.1 - 1.0 MHz
0.16
5.5 V
0.14
5.0 V
0.12
4.5 V
I CC (mA)
0.1
4.0 V
0.08
3.3 V
0.06
2.7 V
0.04
1.8 V
0.02
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Frequency (MHz)
Figure 22-7. Idle Supply Current vs. Frequency (1 - 12 MHz)
IDLE SUPPLY CURRENT vs. FREQUENCY
1 -12 MHz
2
5.5 V
5.0 V
1.5
4.5 V
ICC (mA)
4.0 V
1
3.3 V
0.5
2.7 V
1.8 V
0
0
2
4
6
8
10
12
Frequency (MHz)
218
ATtiny48/88
8008C–AVR–03/09
ATtiny48/88
Figure 22-8. Idle Supply Current vs. VCC (Internal Oscillator, 8 MHz)I
IDLE SUPPLY CURRENT vs. VCC
INTERNAL RC OSCILLATOR, 8 MHz
1.4
85 °C
25 °C
-40 °C
1.2
1
ICC (mA)
0.8
0.6
0.4
0.2
0
1.5
2
2.5
3
3.5
4
4.5
5
5.5
VCC (V)
Figure 22-9. Idle Supply Current vs. VCC (Internal Oscilllator, 1 MHz)
IDLE SUPPLY CURRENT vs. VCC
INTERNAL RC OSCILLATOR, 1 MHz
0.3
85 °C
25 °C
-40 °C
ICC (mA)
0.2
0.1
0
1.5
2
2.5
3
3.5
4
4.5
5
5.5
VCC (V)
219
8008C–AVR–03/09
Figure 22-10. Idle Supply Current vs. VCC (Internal Oscillator, 128 kHz)
IDLE SUPPLY CURRENT vs. VCC
INTERNAL RC OSCILLATOR, 128 KHz
0.025
-40 °C
25 °C
85 °C
0.02
I CC (mA)
0.015
0.01
0.005
0
1.5
2
2.5
3
3.5
4
4.5
5
5.5
VCC (V)
22.3
Power-down Supply Current
Figure 22-11. Power-down Supply Current vs. VCC (Watchdog Timer Disabled)
POWER-DOWN SUPPLY CURRENT vs. VCC
WATCHDOG TIMER DISABLED
0.7
0.6
0.5
I CC (uA)
85 °C
0.4
0.3
0.2
25 °C
0.1
-40 °C
0
1.5
2
2.5
3
3.5
4
4.5
5
5.5
VCC (V)
220
ATtiny48/88
8008C–AVR–03/09
ATtiny48/88
Figure 22-12. Power-down Supply Current vs. VCC (Watchdog Timer Enabled)
POWER-DOWN SUPPLY CURRENT vs. VCC
WATCHDOG TIMER ENABLED
9
8
7
I CC (uA)
6
5
-40 °C
4
25 °C
85 °C
3
2
1
0
1.5
2
2.5
3
3.5
4
4.5
5
5.5
VCC (V)
22.4
Pin Pull-up
Figure 22-13. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 1.8V)
I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE
VCC = 1.8V
60
50
IOP (uA)
40
30
20
-40 °C
10
25 °C
85 °C
0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
VOP (V)
221
8008C–AVR–03/09
Figure 22-14. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 2.7V)
I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE
VCC = 2.7
80
70
60
IOP (uA)
50
40
30
20
25 °C
10
-40 °C
85 °C
0
0
0.5
1
1.5
2
2.5
3
VOP (V)
Figure 22-15. I/O Pin Pull-up Resistor Current vs. Input Voltage (VCC = 5V)
I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE
VCC = 5V
160
140
120
IOP (uA)
100
80
60
40
-40 °C
20
25 °C
85 °C
0
0
1
2
3
4
5
6
VOP (V)
222
ATtiny48/88
8008C–AVR–03/09
ATtiny48/88
Figure 22-16. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V)
RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE
VCC = 1.8V
40
35
30
I RESET (uA)
25
20
15
10
-40 °C
5
25 °C
85 °C
0
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
VRESET(V)
Figure 22-17. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V)
RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE
VCC = 2.7V
60
50
IRESET (uA)
40
30
20
-40 °C
25 °C
85 °C
10
0
0
0.5
1
1.5
2
2.5
3
VRESET (V)
223
8008C–AVR–03/09
Figure 22-18. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V)
RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE
VCC = 5V
120
100
IRESET (uA)
80
60
40
-40 °C
20
25 °C
85 °C
0
0
1
2
3
4
5
6
VRESET (V)
22.5
Pin Driver Strength
Figure 22-19. High Sink I/O Pin Output Voltage vs. Sink Current (VCC = 1.8V)
HIGH SINK I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT
VCC = 1.8V
1
0.9
0.8
85 °C
0.7
V OL (V)
0.6
25 °C
0.5
-40 °C
0.4
0.3
0.2
0.1
0
0
1
2
3
4
5
6
7
8
9
10
IOL (mA)
224
ATtiny48/88
8008C–AVR–03/09
ATtiny48/88
Figure 22-20. High Sink I/O Pin Output Voltage vs. Sink Current (VCC = 3V)
HIGH SINK I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT
VCC = 3V
0.8
0.7
85 °C
0.6
25 °C
V OL (V)
0.5
-40 °C
0.4
0.3
0.2
0.1
0
0
5
10
15
20
25
IOL (mA)
Figure 22-21. High Sink I/O Pin Output Voltage vs. Sink Current (VCC = 5V)
HIGH SINK I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT
VCC = 5V
0.6
0.5
85 °C
V OL (V)
0.4
25 °C
-40 °C
0.3
0.2
0.1
0
0
5
10
15
20
25
IOL (mA)
225
8008C–AVR–03/09
Figure 22-22. Standard I/O Pin Output Voltage vs. Sink Current (VCC = 1.8V)
STANDARD I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT
VCC = 1.8V
1
0.8
85 °C
0.6
V OL (V)
25 °C
-40 °C
0.4
0.2
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
IOL (mA)
Figure 22-23. Standard I/O Pin Output Voltage vs. Sink Current (VCC = 3V)
STANDARD I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT
VCC = 3V
1.2
85 °C
1
25 °C
V OL (V)
0.8
-40 °C
0.6
0.4
0.2
0
0
2
4
6
8
10
12
14
IOL (mA)
226
ATtiny48/88
8008C–AVR–03/09
ATtiny48/88
Figure 22-24. Standard I/O Pin Output Voltage vs. Sink Current (VCC = 5V)
STANDARD I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT
VCC = 5V
1
85 °C
0,8
25 °C
0,6
V OL (V)
-40 °C
0,4
0,2
0
0
5
10
15
20
25
IOL (mA)
Figure 22-25. Standard I/O Pin Output Voltage vs. Source Current (VCC = 1.8V)
STANDARD I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT
VCC = 1.8V
2
1.8
1.6
1.4
V OH (V)
1.2
1
0.8
0.6
-40 °C
85 °C
0.4
0.2
0
0
1
2
3
4
5
25 °C
6
IOH (mA)
227
8008C–AVR–03/09
Figure 22-26. Standard I/O Pin Output Voltage vs. Source Current (VCC = 3V)
STANDARD I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT
VCC = 3V
3.1
2.9
2.7
V OH (V)
2.5
2.3
2.1
1.9
-40 °C
25 °C
85 °C
1.7
1.5
0
5
10
15
20
25
IOH (mA)
Figure 22-27. Standard I/O Pin Output Voltage vs. Source Current (VCC = 5V)
STANDARD I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT
VCC = 5V
5.2
5
V OH (V)
4.8
4.6
4.4
-40 °C
4.2
25 °C
85 °C
4
0
5
10
15
20
25
IOH (mA)
228
ATtiny48/88
8008C–AVR–03/09
ATtiny48/88
Figure 22-28. Reset Pin Output Voltage vs. Sink Current (VCC = 1.8V)
RESET I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT
VCC = 1.8V
0.3
85 °C
25 °C
0.2
V OL (V)
-40 °C
0.1
0
0
0.1
0.2
0.3
0.4
0.5
IOL (mA)
Figure 22-29. Reset Pin Output Voltage vs. Sink Current (VCC = 3V)
RESET I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT
VCC = 3V
1.5
85 °C
1
V OL (V)
25 °C
-40 °C
0.5
0
0
0.5
1
1.5
2
2.5
3
IOL (mA)
229
8008C–AVR–03/09
Figure 22-30. Reset Pin Output Voltage vs. Sink Current (VCC = 5V)
RESET I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT
VCC = 5V
6
5
85 °C
V OL (V)
4
3
25 °C
2
-40 °C
1
0
0
2
4
6
8
10
12
IOL (mA)
Figure 22-31. Reset Pin Output Voltage vs. Source Current (VCC = 1.8V)
RESET I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT
VCC = 1.8V
1.5
V OH (V)
1
0.5
-40 °C
85 °C
0
0
0.5
1
25 °C
1.5
2
2.5
IOH (mA)
230
ATtiny48/88
8008C–AVR–03/09
ATtiny48/88
Figure 22-32. Reset Pin Output Voltage vs. Source Current (VCC = 3V)
RESET I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT
VCC = 3V
3
2.5
V OH (V)
2
1.5
-40 °C
25 °C
85 °C
1
0.5
0
0
0.5
1
1.5
2
2.5
IOH (mA)
Figure 22-33. Reset Pin Output Voltage vs. Source Current (VCC = 5V)
RESET I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT
VCC = 5V
4.5
4
3.5
V OH (V)
3
-40 °C
25 °C
85 °C
2.5
2
1.5
1
0.5
0
0
0.5
1
1.5
2
2.5
IOH (mA)
231
8008C–AVR–03/09
22.6
Pin Threshold and Hysteresis
Figure 22-34. I/O Pin Input Threshold Voltage vs. VCC (VIH, IO Pin Read as ‘1’)
I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC
VIH, IO PIN READ AS '1'
3.5
85 °C
25 °C
-40 °C
3
Threshold (V)
2.5
2
1.5
1
0.5
0
1.5
2
2.5
3
3.5
4
4.5
5
5.5
VCC (V)
Figure 22-35. I/O Pin Input Threshold Voltage vs. VCC (VIL, IO Pin Read as ‘0’)
I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC
VIL, IO PIN READ AS '0'
2.5
85 °C
25 °C
-40 °C
Threshold (V)
2
1.5
1
0.5
0
1.5
2
2.5
3
3.5
4
4.5
5
5.5
VCC (V)
232
ATtiny48/88
8008C–AVR–03/09
ATtiny48/88
Figure 22-36. I/O Pin Input Hysteresis vs. VCC
I/O PIN INPUT HYSTERESIS vs. VCC
0.6
-40 °C
Input Hysteresis (V)
25 °C
0.4
85 °C
0.2
0
1.5
2
2.5
3
3.5
4
4.5
5
5.5
VCC (V)
Figure 22-37. Reset Input Threshold Voltage vs. VCC (VIH, IO Pin Read as ‘1’)
RESET INPUT THRESHOLD VOLTAGE vs. VCC
VIH, IO PIN READ AS '1'
2.5
Threshold (V)
2
-40 °C
1.5
25 °C
1
85 °C
0.5
0
1.5
2
2.5
3
3.5
4
4.5
5
5.5
VCC (V)
233
8008C–AVR–03/09
Figure 22-38. Reset Input Threshold Voltage vs, VCC (VIL, IO Pin Read as ‘0’)
RESET INPUT THRESHOLD VOLTAGE vs. VCC
VIL, IO PIN READ AS '0'
2.5
85 °C
25 °C
-40 °C
Threshold (V)
2
1.5
1
0.5
0
1.5
2
2.5
3
3.5
4
4.5
5
5.5
5
5.5
VCC (V)
Figure 22-39. Reset Pin Input Hysteresis vs. VCC
RESET PIN INPUT HYSTERESIS vs. VCC
0.6
0.5
Input Hysteresis (V)
-40 °C
0.4
25 °C
0.3
0.2
85 °C
0.1
0
1.5
2
2.5
3
3.5
4
4.5
VCC (V)
234
ATtiny48/88
8008C–AVR–03/09
ATtiny48/88
22.7
BOD Threshold
Figure 22-40. BOD Threshold vs. Temperature (BOD Level is 4.3V)
BOD THRESHOLDS vs. TEMPERATURE
BOD LEVEL IS 4.3V
4.34
4.33
Rising VCC
4.32
4.31
Threshold (V)
4.3
4.29
4.28
4.27
4.26
Falling VCC
4.25
4.24
4.23
-60
-40
-20
0
20
40
60
80
100
80
100
Temperature (C)
Figure 22-41. BOD Threshold vs. Temperature (BOD Level is 2.7V)
BOD THRESHOLDS vs. TEMPERATURE
BOD LEVEL IS 2.7V
2.76
2.75
Rising VCC
2.74
Threshold (V)
2.73
2.72
2.71
2.7
2.69
2.68
Falling VCC
2.67
2.66
-60
-40
-20
0
20
40
60
Temperature (C)
235
8008C–AVR–03/09
Figure 22-42. BOD Threshold vs. Temperature (BOD Level is 1.8V)
BOD THRESHOLDS vs. TEMPERATURE
BOD LEVEL IS 1.8V
1,825
1,82
Rising VCC
1,815
Threshold (V)
1,81
1,805
1,8
1,795
1,79
Falling VCC
1,785
1,78
1,775
-60
-40
-20
0
20
40
60
80
100
Temperature (C)
22.8
Internal Oscillator Speed
Figure 22-43. Watchdog Oscillator Frequency vs. VCC
WATCHDOG OSCILLATOR FREQUENCY vs. VCC
114
113
112
F RC (Hz)
111
-40 °C
110
25 °C
109
108
107
106
105
85 °C
104
1.5
2
2.5
3
3.5
4
4.5
5
5.5
VCC (V)
236
ATtiny48/88
8008C–AVR–03/09
ATtiny48/88
Figure 22-44. Watchdog Oscillator Frequency vs. Temperature
WATCHDOG OSCILLATOR FREQUENCY vs. TEMPERATURE
113
112
111
F RC (kHz)
110
109
1.8 V
108
2.7 V
107
3.3 V
106
4.0 V
5.5 V
105
104
-60
-40
-20
0
20
40
60
80
100
Temperature
Figure 22-45. Calibrated 8 MHz Oscillator Frequency vs. VCC
CALIBRATED 8 MHz RC OSCILLATOR FREQUENCY vs. VCC
8.6
85 °C
25 °C
8.5
8.4
-40 °C
F RC (MHz)
8.3
8.2
8.1
8
7.9
7.8
7.7
1.5
1.9
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
VCC (V)
237
8008C–AVR–03/09
Figure 22-46. Calibrated 8 MHz Oscillator Frequency vs. Temperature
CALIBRATED 8 MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE
8.7
8.6
5.5 V
8.5
FRC (MHz)
8.4
8.3
8.2
8.1
3.0 V
8
7.9
7.8
7.7
-60
-40
-20
0
20
40
60
80
100
Temperature
Figure 22-47. Calibrated 8 MHz Oscillator Frequency vs. OSCCAL Value
CALIBRATED 8 MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE
14
85 °C
25 °C
12
-40 °C
F RC (MHz)
10
8
6
4
2
0
0
16
32
48
64
80
96
112 128 144 160 176 192 208 224 240 256
OSCCAL (X1)
238
ATtiny48/88
8008C–AVR–03/09
ATtiny48/88
22.9
Current Consumption of Peripheral Units
Figure 22-48. Brownout Detector Current vs. VCC
BROWNOUT DETECTOR CURRENT vs. VCC
25
85 °C
25 °C
-40 °C
20
ICC (uA)
15
10
5
0
1.5
2
2.5
3
3.5
4
4.5
5
5.5
VCC (V)
Figure 22-49. ADC Current vs. VCC (AREF = AVCC)
ADC CURRENT vs. VCC
AREF = AVCC
350
85 °C
25 °C
-40 °C
300
ICC (uA)
250
200
150
100
50
0
1.5
2
2.5
3
3.5
4
4.5
5
5.5
VCC (V)
239
8008C–AVR–03/09
Figure 22-50. Analog Comparator Current vs. VCC
ANALOG COMPARATOR CURRENT vs. V CC
90
85 °C
25 °C
-40 °C
80
70
ICC (uA)
60
50
40
30
20
10
0
1.5
2
2.5
3
3.5
4
4.5
5
5.5
VCC (V)
Figure 22-51. Programming Current vs. VCC
PROGRAMMING CURRENT vs. VCC
9
-40 °C
8
7
ICC (mA)
6
25 °C
5
85 °C
4
3
2
1
0
1.5
2
2.5
3
3.5
4
4.5
5
5.5
VCC (V)
240
ATtiny48/88
8008C–AVR–03/09
ATtiny48/88
22.10 Current Consumption in Reset and Reset Pulsewidth
Figure 22-52. Reset Supply Current vs. Low Frequency (0.1 - 1.0 MHz)
RESET SUPPLY CURRENT vs. LOW FREQUENCY
0.1 - 1.0 MHz
0.16
0.14
5.5 V
0.12
ICC (mA)
5.0 V
0.1
4.5 V
0.08
4.0 V
0.06
3.3 V
2.7 V
0.04
1.8 V
0.02
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Frequency (MHz)
Figure 22-53. Reset Supply Current vs. Frequency (1 - 12 MHz)
RESET SUPPLY CURRENT vs. FREQUENCY
1 - 12 MHz
1.6
5.5 V
1.4
5.0 V
1.2
4.5 V
ICC (mA)
1
4.0 V
0.8
0.6
3.3 V
0.4
2.7 V
0.2
1.8 V
0
0
2
4
6
8
10
12
Frequency (MHz)
241
8008C–AVR–03/09
Figure 22-54. Minimum Reset Pulse Width vs. VCC
MINIMUM RESET PULSE WIDTH vs. VCC
2500
Pulsewidth (ns)
2000
1500
1000
85 °C
25 °C
-40 °C
500
0
1.5
2
2.5
3
3.5
4
4.5
5
5.5
VCC (V)
242
ATtiny48/88
8008C–AVR–03/09
ATtiny48/88
23. Register Summary
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(0xFF)
Reserved
–
–
–
–
–
–
–
–
(0xFE)
Reserved
–
–
–
–
–
–
–
–
(0xFD)
Reserved
–
–
–
–
–
–
–
–
(0xFC)
Reserved
–
–
–
–
–
–
–
–
(0xFB)
Reserved
–
–
–
–
–
–
–
–
(0xFA)
Reserved
–
–
–
–
–
–
–
–
(0xF9)
Reserved
–
–
–
–
–
–
–
–
(0xF8)
Reserved
–
–
–
–
–
–
–
–
(0xF7)
Reserved
–
–
–
–
–
–
–
–
(0xF6)
Reserved
–
–
–
–
–
–
–
–
(0xF5)
Reserved
–
–
–
–
–
–
–
–
(0xF4)
Reserved
–
–
–
–
–
–
–
–
(0xF3)
Reserved
–
–
–
–
–
–
–
–
(0xF2)
Reserved
–
–
–
–
–
–
–
–
(0xF1)
Reserved
–
–
–
–
–
–
–
–
(0xF0)
Reserved
–
–
–
–
–
–
–
–
(0xEF)
Reserved
–
–
–
–
–
–
–
–
(0xEE)
Reserved
–
–
–
–
–
–
–
–
(0xED)
Reserved
–
–
–
–
–
–
–
–
(0xEC)
Reserved
–
–
–
–
–
–
–
–
(0xEB)
Reserved
–
–
–
–
–
–
–
–
(0xEA)
Reserved
–
–
–
–
–
–
–
–
(0xE9)
Reserved
–
–
–
–
–
–
–
–
(0xE8)
Reserved
–
–
–
–
–
–
–
–
(0xE7)
Reserved
–
–
–
–
–
–
–
–
(0xE6)
Reserved
–
–
–
–
–
–
–
–
(0xE5)
Reserved
–
–
–
–
–
–
–
–
(0xE4)
Reserved
–
–
–
–
–
–
–
–
(0xE3)
Reserved
–
–
–
–
–
–
–
–
(0xE2)
Reserved
–
–
–
–
–
–
–
–
(0xE1)
Reserved
–
–
–
–
–
–
–
–
(0xE0)
Reserved
–
–
–
–
–
–
–
–
(0xDF)
Reserved
–
–
–
–
–
–
–
–
(0xDE)
Reserved
–
–
–
–
–
–
–
–
(0xDD)
Reserved
–
–
–
–
–
–
–
–
(0xDC)
Reserved
–
–
–
–
–
–
–
–
(0xDB)
Reserved
–
–
–
–
–
–
–
–
(0xDA)
Reserved
–
–
–
–
–
–
–
–
(0xD9)
Reserved
–
–
–
–
–
–
–
–
(0xD8)
Reserved
–
–
–
–
–
–
–
–
(0xD7)
Reserved
–
–
–
–
–
–
–
–
(0xD6)
Reserved
–
–
–
–
–
–
–
–
(0xD5)
Reserved
–
–
–
–
–
–
–
–
(0xD4)
Reserved
–
–
–
–
–
–
–
–
(0xD3)
Reserved
–
–
–
–
–
–
–
–
(0xD2)
Reserved
–
–
–
–
–
–
–
–
(0xD1)
Reserved
–
–
–
–
–
–
–
–
(0xD0)
Reserved
–
–
–
–
–
–
–
–
(0xCF)
Reserved
–
–
–
–
–
–
–
–
(0xCE)
Reserved
–
–
–
–
–
–
–
–
(0xCD)
Reserved
–
–
–
–
–
–
–
–
(0xCC)
Reserved
–
–
–
–
–
–
–
–
(0xCB)
Reserved
–
–
–
–
–
–
–
–
(0xCA)
Reserved
–
–
–
–
–
–
–
–
(0xC9)
Reserved
–
–
–
–
–
–
–
–
(0xC8)
Reserved
–
–
–
–
–
–
–
–
(0xC7)
Reserved
–
–
–
–
–
–
–
–
(0xC6)
Reserved
–
–
–
–
–
–
–
–
(0xC5)
Reserved
–
–
–
–
–
–
–
–
(0xC4)
Reserved
–
–
–
–
–
–
–
–
(0xC3)
Reserved
–
–
–
–
–
–
–
–
(0xC2)
Reserved
–
–
–
–
–
–
–
–
(0xC1)
Reserved
–
–
–
–
–
–
–
–
(0xC0)
Reserved
–
–
–
–
–
–
–
–
(0xBF)
Reserved
–
–
–
–
–
–
–
–
Page
243
8008C–AVR–03/09
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
(0xBE)
TWHSR
–
–
–
–
–
–
–
TWHS
154
(0xBD)
TWAMR
TWAM6
TWAM5
TWAM4
TWAM3
TWAM2
TWAM1
TWAM0
–
154
(0xBC)
TWCR
TWINT
TWEA
TWSTA
TWSTO
TWWC
TWEN
–
TWIE
151
(0xBB)
TWDR
(0xBA)
TWAR
TWA6
TWA5
TWA4
TWS7
TWS6
TWS5
244
2-wire Serial Interface Data Register
153
TWA3
TWA2
TWA1
TWA0
TWGCE
153
TWS4
TWS3
–
TWPS1
TWPS0
152
(0xB9)
TWSR
(0xB8)
TWBR
(0xB7)
Reserved
–
–
–
–
–
–
–
–
(0xB6)
Reserved
–
–
–
–
–
–
–
–
(0xB5)
Reserved
–
–
–
–
–
–
–
–
(0xB4)
Reserved
–
–
–
–
–
–
–
–
(0xB3)
Reserved
–
–
–
–
–
–
–
–
(0xB2)
Reserved
–
–
–
–
–
–
–
–
(0xB1)
Reserved
–
–
–
–
–
–
–
–
(0xB0)
Reserved
–
–
–
–
–
–
–
–
(0xAF)
Reserved
–
–
–
–
–
–
–
–
(0xAE)
Reserved
–
–
–
–
–
–
–
–
(0xAD)
Reserved
–
–
–
–
–
–
–
–
(0xAC)
Reserved
–
–
–
–
–
–
–
–
(0xAB)
Reserved
–
–
–
–
–
–
–
–
(0xAA)
Reserved
–
–
–
–
–
–
–
–
(0xA9)
Reserved
–
–
–
–
–
–
–
–
(0xA8)
Reserved
–
–
–
–
–
–
–
–
(0xA7)
Reserved
–
–
–
–
–
–
–
–
(0xA6)
Reserved
–
–
–
–
–
–
–
–
(0xA5)
Reserved
–
–
–
–
–
–
–
–
(0xA4)
Reserved
–
–
–
–
–
–
–
–
(0xA3)
Reserved
–
–
–
–
–
–
–
–
(0xA2)
Reserved
–
–
–
–
–
–
–
–
(0xA1)
Reserved
–
–
–
–
–
–
–
–
(0xA0)
Reserved
–
–
–
–
–
–
–
–
(0x9F)
Reserved
–
–
–
–
–
–
–
–
(0x9E)
Reserved
–
–
–
–
–
–
–
–
(0x9D)
Reserved
–
–
–
–
–
–
–
–
(0x9C)
Reserved
–
–
–
–
–
–
–
–
(0x9B)
Reserved
–
–
–
–
–
–
–
–
(0x9A)
Reserved
–
–
–
–
–
–
–
–
(0x99)
Reserved
–
–
–
–
–
–
–
–
(0x98)
Reserved
–
–
–
–
–
–
–
–
(0x97)
Reserved
–
–
–
–
–
–
–
–
(0x96)
Reserved
–
–
–
–
–
–
–
–
(0x95)
Reserved
–
–
–
–
–
–
–
–
(0x94)
Reserved
–
–
–
–
–
–
–
–
(0x93)
Reserved
–
–
–
–
–
–
–
–
(0x92)
Reserved
–
–
–
–
–
–
–
–
(0x91)
Reserved
–
–
–
–
–
–
–
–
(0x90)
Reserved
–
–
–
–
–
–
–
–
(0x8F)
Reserved
–
–
–
–
–
–
–
–
(0x8E)
Reserved
–
–
–
–
–
–
–
–
(0x8D)
Reserved
–
–
–
–
–
–
–
–
(0x8C)
Reserved
–
–
–
–
–
–
–
–
(0x8B)
OCR1BH
(0x8A)
OCR1BL
(0x89)
OCR1AH
(0x88)
OCR1AL
(0x87)
ICR1H
(0x86)
ICR1L
(0x85)
TCNT1H
2-wire Serial Interface Bit Rate Register
151
– Output Compare Register B High Byte
Timer/Counter1 – Output Compare Register B Low Byte
Timer/Counter1 – Output Compare Register A High Byte
Timer/Counter1 – Output Compare Register A Low Byte
Timer/Counter1 – Input Capture Register High Byte
Timer/Counter1 – Input Capture Register Low Byte
Timer/Counter1 – Counter Register High Byte
Timer/Counter1 – Counter Register Low Byte
109
Timer/Counter1
109
109
109
109
109
108
(0x84)
TCNT1L
(0x83)
Reserved
–
–
–
(0x82)
TCCR1C
FOC1A
FOC1B
–
–
–
–
–
–
(0x81)
TCCR1B
ICNC1
ICES1
–
WGM13
WGM12
CS12
CS11
CS10
107
(0x80)
TCCR1A
COM1A1
COM1A0
COM1B1
COM1B0
–
WGM11
WGM10
105
–
–
–
108
–
–
108
(0x7F)
DIDR1
–
–
–
–
–
–
–
AIN1D
AIN0D
157
(0x7E)
DIDR0
ADC7D
ADC6D
ADC5D
ADC4D
ADC3D
ADC2D
ADC1D
ADC0D
174
(0x7D)
Reserved
–
–
–
–
–
–
–
–
ATtiny48/88
8008C–AVR–03/09
ATtiny48/88
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
(0x7C)
ADMUX
–
REFS0
ADLAR
–
MUX3
MUX2
MUX1
MUX0
170
(0x7B)
ADCSRB
–
ACME
–
–
–
ADTS2
ADTS1
ADTS0
173
(0x7A)
ADCSRA
ADEN
ADSC
ADATE
ADIF
ADIE
ADPS2
ADPS1
ADPS0
(0x79)
ADCH
ADC Data Register High byte
171
173
(0x78)
ADCL
(0x77)
Reserved
–
–
–
ADC Data Register Low byte
–
–
–
–
–
173
(0x76)
Reserved
–
–
–
–
–
–
–
–
(0x75)
Reserved
–
–
–
–
–
–
–
–
(0x74)
Reserved
–
–
–
–
–
–
–
–
(0x73)
Reserved
–
–
–
–
–
–
–
–
(0x72)
Reserved
–
–
–
–
–
–
–
–
(0x71)
Reserved
–
–
–
–
–
–
–
–
(0x70)
Reserved
–
–
–
–
–
–
–
–
(0x6F)
TIMSK1
–
–
ICIE1
–
–
OCIE1B
OCIE1A
TOIE1
(0x6E)
TIMSK0
–
–
–
–
–
OCIE0B
OCIE0A
TOIE0
82
(0x6D)
PCMSK2
PCINT23
PCINT22
PCINT21
PCINT20
PCINT19
PCINT18
PCINT17
PCINT16
54
(0x6C)
PCMSK1
PCINT15
PCINT14
PCINT13
PCINT12
PCINT11
PCINT10
PCINT9
PCINT8
54
(0x6B)
PCMSK0
PCINT7
PCINT6
PCINT5
PCINT4
PCINT2
PCMSK3
–
–
-
-
PCINT26
PCINT1
PCINT25
PCINT0
PCINT24
54
(0x6A)
PCINT3
PCINT27
(0x69)
EICRA
–
–
–
–
ISC11
ISC10
ISC01
ISC00
50
(0x68)
PCICR
–
–
–
–
PCIE3
PCIE2
PCIE1
PCIE0
52
(0x67)
Reserved
–
–
–
–
–
–
–
–
Oscillator Calibration Register
109
54
(0x66)
OSCCAL
(0x65)
Reserved
–
–
–
–
–
–
–
–
31
(0x64)
PRR
PRTWI
–
PRTIM0
–
PRTIM1
PRSPI
–
PRADC
(0x63)
Reserved
–
–
–
–
–
–
–
–
(0x62)
Reserved
–
–
–
–
–
–
–
–
(0x61)
CLKPR
CLKPCE
–
–
–
CLKPS3
CLKPS2
CLKPS1
CLKPS0
31
(0x60)
WDTCSR
WDIF
WDIE
WDP3
WDCE
WDE
WDP2
WDP1
WDP0
44
9
37
0x3F (0x5F)
SREG
I
T
H
S
V
N
Z
C
0x3E (0x5E)
Reserved
–
–
–
–
–
–
–
–
0x3D (0x5D)
SPL
SP7
SP6
SP5
SP4
SP3
SP2
SP1
SP0
0x3C (0x5C)
Reserved
–
–
–
–
–
–
–
–
0x3B (0x5B)
Reserved
–
–
–
–
–
–
–
–
0x3A (0x5A)
Reserved
–
–
–
–
–
–
–
–
0x39 (0x59)
Reserved
–
–
–
–
–
–
–
–
0x38 (0x58)
Reserved
–
–
–
–
–
–
–
–
0x37 (0x57)
SPMCSR
–
RWWSB
–
CTPB
RFLB
PGWRT
PGERS
SELFPRGEN
0x36 (0x56)
Reserved
–
–
–
–
–
0x35 (0x55)
MCUCR
–
BPDS
BPDSE
PUD
–
–
–
–
0x34 (0x54)
MCUSR
–
–
–
–
WDRF
BORF
EXTRF
PORF
44
0x33 (0x53)
SMCR
–
–
–
–
–
SM1
SM0
SE
36
0x32 (0x52)
Reserved
–
–
–
–
–
–
0x31 (0x51)
DWDR
0x30 (0x50)
ACSR
ACD
ACBG
ACO
ACI
ACIE
ACIC
ACIS1
ACIS0
–
–
–
–
–
–
–
–
–
–
debugWire Data Register
12
182
176
156
0x2F (0x4F)
Reserved
0x2E (0x4E)
SPDR
0x2D (0x4D)
SPSR
SPIF
WCOL
–
0x2C (0x4C)
SPCR
SPIE
SPE
DORD
0x2B (0x4B)
GPIOR2
General Purpose I/O Register 2
0x2A (0x4A)
GPIOR1
General Purpose I/O Register 1
0x29 (0x49)
Reserved
0x28 (0x48)
OCR0B
Timer/Counter0 Output Compare Register B
0x27 (0x47)
OCR0A
Timer/Counter0 Output Compare Register A
81
0x26 (0x46)
TCNT0
Timer/Counter0 (8-bit)
81
SPI Data Register
–
–
–
123
–
–
–
–
SPI2X
122
MSTR
CPOL
CPHA
SPR1
SPR0
121
–
24
24
–
–
–
–
82
0x25 (0x45)
TCCR0A
–
–
–
–
CTC0
CS02
CS01
CS00
0x24 (0x44)
Reserved
–
–
–
–
–
–
–
–
0x23 (0x43)
GTCCR
TSM
–
–
–
–
–
–
PSRSYNC
0x22 (0x42)
Reserved
–
–
–
–
–
–
–
–
0x21 (0x41)
EEARL
EEPROM Address Register Low Byte
22
0x20 (0x40)
EEDR
EEPROM Data Register
22
0x1F (0x3F)
EECR
0x1E (0x3E)
GPIOR0
–
–
EEPM1
EEPM0
EERIE
0x1D (0x3D)
EIMSK
–
–
–
–
0x1C (0x3C)
EIFR
–
–
–
–
–
–
0x1B (0x3B)
PCIFR
–
–
–
–
PCIF3
PCIF2
113
EEMPE
EEPE
EERE
22
–
INT1
INT0
51
INTF1
INTF0
51
PCIF1
PCIF0
52
General Purpose I/O Register 0
–
80
24
245
8008C–AVR–03/09
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x1A (0x3A)
Reserved
–
–
–
–
–
–
–
–
Page
0x19 (0x39)
Reserved
–
–
–
–
–
–
–
–
0x18 (0x38)
Reserved
–
–
–
–
–
–
–
–
0x17 (0x37)
Reserved
–
–
–
–
–
–
–
–
0x16 (0x36)
TIFR1
–
–
ICF1
–
–
OCF1B
OCF1A
TOV1
110
0x15 (0x35)
TIFR0
–
–
–
–
–
OCF0B
OCF0A
TOV0
82
0x14 (0x34)
Reserved
–
–
–
–
–
–
–
–
0x13 (0x33)
Reserved
–
–
–
–
–
–
–
–
0x12 (0x32)
PORTCR
BBMD
BBMC
BBMB
BBMA
PUDD
PUDC
PUDB
PUDA
0x11 (0x31)
Reserved
–
–
–
–
–
–
–
–
–
72
0x10 (0x30)
Reserved
–
–
–
–
–
–
–
0x0F (0x2F)
Reserved
–
–
–
–
–
–
–
–
0x0E (0x2E)
PORTA
–
–
–
–
PORTA3
PORTA2
PORTA1
PORTA0
74
0x0D (0x2D)
DDRA
–
–
–
–
DDA3
DDA2
DDA1
DDA0
0x0C (0x2C)
PINA
–
–
–
–
PINA3
PINA2
PINA1
PINA0
74
74
0x0B (0x2B)
PORTD
PORTD7
PORTD6
PORTD5
PORTD4
PORTD3
PORTD2
PORTD1
PORTD0
74
0x0A (0x2A)
DDRD
DDD7
DDD6
DDD5
DDD4
DDD3
DDD2
DDD1
DDD0
74
74
0x09 (0x29)
PIND
PIND7
PIND6
PIND5
PIND4
PIND3
PIND2
PIND1
PIND0
0x08 (0x28)
PORTC
PORTC7
PORTC6
PORTC5
PORTC4
PORTC3
PORTC2
PORTC1
PORTC0
73
0x07 (0x27)
DDRC
DDC7
DDC6
DDC5
DDC4
DDC3
DDC2
DDC1
DDC0
73
0x06 (0x26)
PINC
PINC7
PINC6
PINC5
PINC4
PINC3
PINC2
PINC1
PINC0
74
0x05 (0x25)
PORTB
PORTB7
PORTB6
PORTB5
PORTB4
PORTB3
PORTB2
PORTB1
PORTB0
73
0x04 (0x24)
DDRB
DDB7
DDB6
DDB5
DDB4
DDB3
DDB2
DDB1
DDB0
73
0x03 (0x23)
PINB
PINB7
PINB6
PINB5
PINB4
PINB3
PINB2
PINB1
PINB0
73
0x02 (0x22)
Reserved
–
–
–
–
–
–
–
–
0x01 (0x21)
Reserved
–
–
–
–
–
–
–
–
0x00 (0x20)
Reserved
–
–
–
–
–
–
–
–
Note:
1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
2. I/O Registers within the address range 0x00 – 0x1F are directly bit-accessible using the SBI and CBI instructions. In these
registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI
instructions will only operate on the specified bit, and can therefore be used on registers containing such Status Flags. The
CBI and SBI instructions work with registers 0x00 to 0x1F only.
4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 – 0x3F must be used. When addressing I/O
Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The ATtiny48/88 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN
and OUT instructions. For the Extended I/O space from 0x60 – 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD
instructions can be used.
246
ATtiny48/88
8008C–AVR–03/09
ATtiny48/88
24. Instruction Set Summary
Mnemonics
Operands
Description
Operation
Flags
#Clocks
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD
Rd, Rr
Add two Registers
Rd ← Rd + Rr
Z,C,N,V,H
ADC
Rd, Rr
Add with Carry two Registers
Rd ← Rd + Rr + C
Z,C,N,V,H
1
ADIW
Rdl,K
Add Immediate to Word
Rdh:Rdl ← Rdh:Rdl + K
Z,C,N,V,S
2
SUB
Rd, Rr
Subtract two Registers
Rd ← Rd - Rr
Z,C,N,V,H
1
SUBI
Rd, K
Subtract Constant from Register
Rd ← Rd - K
Z,C,N,V,H
1
SBC
Rd, Rr
Subtract with Carry two Registers
Rd ← Rd - Rr - C
Z,C,N,V,H
1
SBCI
Rd, K
Subtract with Carry Constant from Reg.
Rd ← Rd - K - C
Z,C,N,V,H
1
SBIW
Rdl,K
Subtract Immediate from Word
Rdh:Rdl ← Rdh:Rdl - K
Z,C,N,V,S
2
AND
Rd, Rr
Logical AND Registers
Rd ← Rd • Rr
Z,N,V
1
ANDI
Rd, K
Logical AND Register and Constant
Rd ← Rd • K
Z,N,V
1
OR
Rd, Rr
Logical OR Registers
Rd ← Rd v Rr
Z,N,V
1
ORI
Rd, K
Logical OR Register and Constant
Rd ← Rd v K
Z,N,V
1
EOR
Rd, Rr
Exclusive OR Registers
Rd ← Rd ⊕ Rr
Z,N,V
1
1
COM
Rd
One’s Complement
Rd ← 0xFF − Rd
Z,C,N,V
1
NEG
Rd
Two’s Complement
Rd ← 0x00 − Rd
Z,C,N,V,H
1
SBR
Rd,K
Set Bit(s) in Register
Rd ← Rd v K
Z,N,V
1
CBR
Rd,K
Clear Bit(s) in Register
Rd ← Rd • (0xFF - K)
Z,N,V
1
INC
Rd
Increment
Rd ← Rd + 1
Z,N,V
1
DEC
Rd
Decrement
Rd ← Rd − 1
Z,N,V
1
TST
Rd
Test for Zero or Minus
Rd ← Rd • Rd
Z,N,V
1
CLR
Rd
Clear Register
Rd ← Rd ⊕ Rd
Z,N,V
1
SER
Rd
Set Register
Rd ← 0xFF
None
1
2
BRANCH INSTRUCTIONS
RJMP
k
IJMP
RCALL
k
Relative Jump
PC ← PC + k + 1
None
Indirect Jump to (Z)
PC ← Z
None
2
Relative Subroutine Call
PC ← PC + k + 1
None
3
3
ICALL
Indirect Call to (Z)
PC ← Z
None
RET
Subroutine Return
PC ← STACK
None
4
RETI
Interrupt Return
PC ← STACK
I
4
CPSE
Rd,Rr
Compare, Skip if Equal
if (Rd = Rr) PC ← PC + 2 or 3
None
CP
Rd,Rr
Compare
Rd − Rr
Z, N,V,C,H
1
CPC
Rd,Rr
Compare with Carry
Rd − Rr − C
Z, N,V,C,H
1
CPI
Rd,K
Compare Register with Immediate
Rd − K
Z, N,V,C,H
SBRC
Rr, b
Skip if Bit in Register Cleared
if (Rr(b)=0) PC ← PC + 2 or 3
None
1/2/3
1/2/3
1
SBRS
Rr, b
Skip if Bit in Register is Set
if (Rr(b)=1) PC ← PC + 2 or 3
None
1/2/3
SBIC
P, b
Skip if Bit in I/O Register Cleared
if (P(b)=0) PC ← PC + 2 or 3
None
1/2/3
SBIS
P, b
Skip if Bit in I/O Register is Set
if (P(b)=1) PC ← PC + 2 or 3
None
1/2/3
BRBS
s, k
Branch if Status Flag Set
if (SREG(s) = 1) then PC←PC+k + 1
None
1/2
BRBC
s, k
Branch if Status Flag Cleared
if (SREG(s) = 0) then PC←PC+k + 1
None
1/2
BREQ
k
Branch if Equal
if (Z = 1) then PC ← PC + k + 1
None
1/2
BRNE
k
Branch if Not Equal
if (Z = 0) then PC ← PC + k + 1
None
1/2
BRCS
k
Branch if Carry Set
if (C = 1) then PC ← PC + k + 1
None
1/2
BRCC
k
Branch if Carry Cleared
if (C = 0) then PC ← PC + k + 1
None
1/2
BRSH
k
Branch if Same or Higher
if (C = 0) then PC ← PC + k + 1
None
1/2
BRLO
k
Branch if Lower
if (C = 1) then PC ← PC + k + 1
None
1/2
BRMI
k
Branch if Minus
if (N = 1) then PC ← PC + k + 1
None
1/2
BRPL
k
Branch if Plus
if (N = 0) then PC ← PC + k + 1
None
1/2
BRGE
k
Branch if Greater or Equal, Signed
if (N ⊕ V= 0) then PC ← PC + k + 1
None
1/2
BRLT
k
Branch if Less Than Zero, Signed
if (N ⊕ V= 1) then PC ← PC + k + 1
None
1/2
BRHS
k
Branch if Half Carry Flag Set
if (H = 1) then PC ← PC + k + 1
None
1/2
BRHC
k
Branch if Half Carry Flag Cleared
if (H = 0) then PC ← PC + k + 1
None
1/2
BRTS
k
Branch if T Flag Set
if (T = 1) then PC ← PC + k + 1
None
1/2
BRTC
k
Branch if T Flag Cleared
if (T = 0) then PC ← PC + k + 1
None
1/2
BRVS
k
Branch if Overflow Flag is Set
if (V = 1) then PC ← PC + k + 1
None
1/2
BRVC
k
Branch if Overflow Flag is Cleared
if (V = 0) then PC ← PC + k + 1
None
1/2
BRIE
k
Branch if Interrupt Enabled
if ( I = 1) then PC ← PC + k + 1
None
1/2
BRID
k
Branch if Interrupt Disabled
if ( I = 0) then PC ← PC + k + 1
None
1/2
BIT AND BIT-TEST INSTRUCTIONS
SBI
P,b
Set Bit in I/O Register
I/O(P,b) ← 1
None
2
CBI
P,b
Clear Bit in I/O Register
I/O(P,b) ← 0
None
2
LSL
Rd
Logical Shift Left
Rd(n+1) ← Rd(n), Rd(0) ← 0
Z,C,N,V
1
LSR
Rd
Logical Shift Right
Rd(n) ← Rd(n+1), Rd(7) ← 0
Z,C,N,V
1
ROL
Rd
Rotate Left Through Carry
Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)
Z,C,N,V
1
ROR
Rd
Rotate Right Through Carry
Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)
Z,C,N,V
1
247
8008C–AVR–03/09
Mnemonics
Operands
Description
Operation
Flags
#Clocks
ASR
Rd
Arithmetic Shift Right
Rd(n) ← Rd(n+1), n=0..6
Z,C,N,V
1
SWAP
Rd
Swap Nibbles
Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)
None
1
BSET
s
Flag Set
SREG(s) ← 1
SREG(s)
1
BCLR
s
Flag Clear
SREG(s) ← 0
SREG(s)
1
BST
Rr, b
Bit Store from Register to T
T ← Rr(b)
T
1
BLD
Rd, b
Bit load from T to Register
Rd(b) ← T
None
1
SEC
Set Carry
C←1
C
1
CLC
Clear Carry
C←0
C
1
SEN
Set Negative Flag
N←1
N
1
CLN
Clear Negative Flag
N←0
N
1
SEZ
Set Zero Flag
Z←1
Z
1
CLZ
Clear Zero Flag
Z←0
Z
1
SEI
Global Interrupt Enable
I←1
I
1
CLI
Global Interrupt Disable
I←0
I
1
SES
Set Signed Test Flag
S←1
S
1
CLS
Clear Signed Test Flag
S←0
S
1
SEV
Set Twos Complement Overflow.
V←1
V
1
CLV
Clear Twos Complement Overflow
V←0
V
1
SET
Set T in SREG
T←1
T
1
CLT
Clear T in SREG
T←0
T
1
SEH
CLH
Set Half Carry Flag in SREG
Clear Half Carry Flag in SREG
H←1
H←0
H
H
1
1
Rd ← Rr
Rd+1:Rd ← Rr+1:Rr
None
1
None
1
1
DATA TRANSFER INSTRUCTIONS
MOV
Rd, Rr
Move Between Registers
MOVW
Rd, Rr
Copy Register Word
LDI
Rd, K
Load Immediate
Rd ← K
None
LD
Rd, X
Load Indirect
Rd ← (X)
None
2
LD
Rd, X+
Load Indirect and Post-Inc.
Rd ← (X), X ← X + 1
None
2
LD
Rd, - X
Load Indirect and Pre-Dec.
X ← X - 1, Rd ← (X)
None
2
LD
Rd, Y
Load Indirect
Rd ← (Y)
None
2
LD
Rd, Y+
Load Indirect and Post-Inc.
Rd ← (Y), Y ← Y + 1
None
2
LD
Rd, - Y
Load Indirect and Pre-Dec.
Y ← Y - 1, Rd ← (Y)
None
2
LDD
Rd,Y+q
Load Indirect with Displacement
Rd ← (Y + q)
None
2
LD
Rd, Z
Load Indirect
Rd ← (Z)
None
2
LD
Rd, Z+
Load Indirect and Post-Inc.
Rd ← (Z), Z ← Z+1
None
2
LD
Rd, -Z
Load Indirect and Pre-Dec.
Z ← Z - 1, Rd ← (Z)
None
2
LDD
Rd, Z+q
Load Indirect with Displacement
Rd ← (Z + q)
None
2
LDS
Rd, k
Load Direct from SRAM
Rd ← (k)
None
2
ST
X, Rr
Store Indirect
(X) ← Rr
None
2
ST
X+, Rr
Store Indirect and Post-Inc.
(X) ← Rr, X ← X + 1
None
2
ST
- X, Rr
Store Indirect and Pre-Dec.
X ← X - 1, (X) ← Rr
None
2
ST
Y, Rr
Store Indirect
(Y) ← Rr
None
2
ST
Y+, Rr
Store Indirect and Post-Inc.
(Y) ← Rr, Y ← Y + 1
None
2
ST
- Y, Rr
Store Indirect and Pre-Dec.
Y ← Y - 1, (Y) ← Rr
None
2
STD
Y+q,Rr
Store Indirect with Displacement
(Y + q) ← Rr
None
2
ST
Z, Rr
Store Indirect
(Z) ← Rr
None
2
ST
Z+, Rr
Store Indirect and Post-Inc.
(Z) ← Rr, Z ← Z + 1
None
2
ST
-Z, Rr
Store Indirect and Pre-Dec.
Z ← Z - 1, (Z) ← Rr
None
2
STD
Z+q,Rr
Store Indirect with Displacement
(Z + q) ← Rr
None
2
STS
k, Rr
Store Direct to SRAM
(k) ← Rr
None
2
Load Program Memory
R0 ← (Z)
None
3
LPM
LPM
Rd, Z
Load Program Memory
Rd ← (Z)
None
3
LPM
Rd, Z+
Load Program Memory and Post-Inc
Rd ← (Z), Z ← Z+1
None
3
Store Program Memory
(Z) ← R1:R0
None
-
IN
Rd, P
In Port
Rd ← P
None
1
OUT
P, Rr
Out Port
P ← Rr
None
1
PUSH
Rr
Push Register on Stack
STACK ← Rr
None
2
POP
Rd
Pop Register from Stack
Rd ← STACK
None
2
SPM
MCU CONTROL INSTRUCTIONS
NOP
No Operation
None
1
SLEEP
Sleep
(see specific descr. for Sleep function)
None
1
WDR
BREAK
Watchdog Reset
Break
(see specific descr. for WDR/timer)
For On-chip Debug Only
None
None
1
N/A
248
ATtiny48/88
8008C–AVR–03/09
ATtiny48/88
25. Ordering Information
25.1
ATtiny48
Speed (MHz)
12 (3)
Note:
Power Supply
Ordering Code
Package(1)
1.8 – 5.5
ATtiny48-AU
ATtiny48-MMU
ATtiny48-MMH
ATtiny48-MU
ATtiny48-PU
32A
28M1
28M1
32M1-A
28P3
Operational Range
Industrial
(-40°C to 85°C)
1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive).Also Halide free and fully Green.
3. Maximum frequency. See Figure 21-1 on page 203.
Package Type
32A
32-lead, Thin (1.0 mm) Plastic Quad Flat Package (TQFP)
28M1
28-pad, 4 x 4 x 1.0 body, Lead Pitch 0.45 mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
32M1-A
32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50 mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
28P3
28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP)
249
8008C–AVR–03/09
25.2
ATtiny88
Speed (MHz)
12 (3)
Note:
Power Supply
Ordering Code
Package(1)
1.8 – 5.5
ATtiny88-AU
ATtiny88-MMU
ATtiny88-MMH
ATtiny88-MU
ATtiny88-PU
32A
28M1
28M1
32M1-A
28P3
Operational Range
Industrial
(-40°C to 85°C)
1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive).Also Halide free and fully Green.
3. Maximum frequency. See Figure 21-1 on page 203.
Package Type
32A
32-lead, Thin (1.0 mm) Plastic Quad Flat Package (TQFP)
28M1
28-pad, 4 x 4 x 1.0 body, Lead Pitch 0.45 mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
32M1-A
32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50 mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
28P3
28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP)
250
ATtiny48/88
8008C–AVR–03/09
ATtiny48/88
26. Packaging Information
26.1
32A
PIN 1
B
PIN 1 IDENTIFIER
E1
e
E
D1
D
C
0˚~7˚
A1
A2
A
L
COMMON DIMENSIONS
(Unit of Measure = mm)
Notes:
1. This package conforms to JEDEC reference MS-026, Variation ABA.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
3. Lead coplanarity is 0.10 mm maximum.
SYMBOL
MIN
NOM
MAX
A
–
–
1.20
A1
0.05
–
0.15
A2
0.95
1.00
1.05
D
8.75
9.00
9.25
D1
6.90
7.00
7.10
E
8.75
9.00
9.25
E1
6.90
7.00
7.10
B
0.30
–
0.45
C
0.09
–
0.20
L
0.45
–
0.75
e
NOTE
Note 2
Note 2
0.80 TYP
10/5/2001
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
32A, 32-lead, 7 x 7 mm Body Size, 1.0 mm Body Thickness,
0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
DRAWING NO.
REV.
32A
B
251
8008C–AVR–03/09
26.2
28M1
C
1
2
Pin 1 ID
3
E
SIDE VIEW
A1
TOP VIEW
A
y
D2
K
1
0.45
2
R 0.20
3
E2
b
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
MIN
NOM
MAX
A
0.80
0.90
1.00
A1
0.00
0.02
0.05
b
0.17
0.22
0.27
C
L
e
0.4 Ref
(4x)
Note:
0.20 REF
D
3.95
4.00
4.05
D2
2.35
2.40
2.45
E
3.95
4.00
4.05
E2
2.35
2.40
2.45
e
BOTTOM VIEW
The terminal #1 ID is a Laser-marked Feature.
NOTE
0.45
L
0.35
0.40
0.45
y
0.00
–
0.08
K
0.20
–
–
10/24/08
Package Drawing Contact:
[email protected]
252
TITLE
28M1, 28-pad, 4 x 4 x 1.0 mm Body, Lead Pitch 0.45 mm,
2.4 x 2.4 mm Exposed Pad, Thermally Enhanced
Plastic Very Thin Quad Flat No Lead Package (VQFN)
GPC
ZBV
DRAWING NO.
REV.
28M1
B
ATtiny48/88
8008C–AVR–03/09
ATtiny48/88
26.3
28P3
D
PIN
1
E1
A
SEATING PLANE
L
B2
B1
B
A1
(4 PLACES)
e
E
0º ~ 15º
C
COMMON DIMENSIONS
(Unit of Measure = mm)
REF
eB
Note:
1. Dimensions D and E1 do not include mold Flash or Protrusion.
Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").
MIN
NOM
MAX
–
–
4.5724
A1
0.508
–
–
D
34.544
–
34.798
E
7.620
–
8.255
E1
7.112
–
7.493
B
0.381
–
0.533
B1
1.143
–
1.397
B2
0.762
–
1.143
SYMBOL
A
L
3.175
–
3.429
C
0.203
–
0.356
eB
–
–
10.160
e
NOTE
Note 1
Note 1
2.540 TYP
09/28/01
R
2325 Orchard Parkway
San Jose, CA 95131
TITLE
28P3, 28-lead (0.300"/7.62 mm Wide) Plastic Dual
Inline Package (PDIP)
DRAWING NO.
28P3
REV.
B
253
8008C–AVR–03/09
26.4
32M1-A
D
D1
1
2
3
0
Pin 1 ID
E1
SIDE VIEW
E
TOP VIEW
A3
A2
A1
A
K
0.08 C
P
D2
1
2
3
P
Pin #1 Notch
(0.20 R)
K
e
SYMBOL
MIN
NOM
MAX
A
0.80
0.90
1.00
A1
–
0.02
0.05
A2
–
0.65
1.00
A3
E2
b
COMMON DIMENSIONS
(Unit of Measure = mm)
L
BOTTOM VIEW
0.20 REF
b
0.18
0.23
0.30
D
4.90
5.00
5.10
D1
4.70
4.75
4.80
D2
2.95
3.10
3.25
E
4.90
5.00
5.10
E1
4.70
4.75
4.80
E2
2.95
3.10
3.25
e
Note: JEDEC Standard MO-220, Fig. 2 (Anvil Singulation), VHHD-2.
NOTE
0.50 BSC
L
0.30
0.40
0.50
P
–
–
0.60
o
12
0
–
K
0.20
–
–
–
5/25/06
R
254
2325 Orchard Parkway
San Jose, CA 95131
TITLE
32M1-A, 32-pad, 5 x 5 x 1.0 mm Body, Lead Pitch 0.50 mm,
3.10 mm Exposed Pad, Micro Lead Frame Package (MLF)
DRAWING NO.
32M1-A
REV.
E
ATtiny48/88
8008C–AVR–03/09
ATtiny48/88
27. Errata
27.1
ATtiny48
27.1.1
Rev. C
No known errata.
27.1.2
Rev. B
Not sampled.
27.1.3
Rev. A
Not sampled.
255
8008C–AVR–03/09
27.2
ATtiny88
27.2.1
Rev. C
No known errata.
27.2.2
Rev. B
No known errata.
27.2.3
Rev. A
Not sampled.
256
ATtiny48/88
8008C–AVR–03/09
ATtiny48/88
28. Datasheet Revision History
Please note that page references in this section refer to the current revision of this document.
28.1
Rev. 8008C - 03/09
1. Updated sections:
– “Features” on page 1
– “Reset and Interrupt Handling” on page 13
– “EECR – EEPROM Control Register” on page 22
– “Features” on page 124
– “Bit Rate Generator Unit” on page 130
– “TWBR – TWI Bit Rate Register” on page 151
– “TWHSR – TWI High Speed Register” on page 154
– “Analog Comparator” on page 155
– “Overview” on page 158
– “Operation” on page 159
– “Starting a Conversion” on page 160
– “Programming the Lock Bits” on page 195
– “Absolute Maximum Ratings*” on page 201
– “DC Characteristics” on page 201
– “Speed Grades” on page 203
– “Register Summary” on page 243
2. Added sections
– “High-Speed Two-Wire Interface Clock – clkTWIHS” on page 26
– “Analog Comparator Characteristics” on page 205
3. Updated Figure 6-1 on page 25.
4. Updated order codes on page 249 and page 250 to reflect changes in leadframe
composition.
28.2
Rev. 8008B - 06/08
1. Updated introduction of “I/O-Ports” on page 55.
2. Updated “DC Characteristics” on page 201.
3. Added “Typical Charateristics” on page 215.
28.3
Rev. 8008A - 06/08
1. Initial revision.
257
8008C–AVR–03/09
258
ATtiny48/88
8008C–AVR–03/09
ATtiny48/88
Table of Contents
Features ..................................................................................................... 1
1
Pin Configurations ................................................................................... 2
1.1
2
3
4
5
6
Pin Descriptions .................................................................................................3
Overview ................................................................................................... 5
2.1
Block Diagram ...................................................................................................5
2.2
Comparison Between ATtiny48 and ATtiny88 ...................................................6
Additional Information ............................................................................. 7
3.1
Resources .........................................................................................................7
3.2
About Code Examples .......................................................................................7
3.3
Data Retention ...................................................................................................7
3.4
Disclaimer ..........................................................................................................7
AVR CPU Core .......................................................................................... 8
4.1
Introduction ........................................................................................................8
4.2
Architectural Overview .......................................................................................8
4.3
ALU – Arithmetic Logic Unit ...............................................................................9
4.4
Status Register ..................................................................................................9
4.5
General Purpose Register File ........................................................................11
4.6
Stack Pointer ...................................................................................................12
4.7
Instruction Execution Timing ...........................................................................13
4.8
Reset and Interrupt Handling ...........................................................................13
Memories ................................................................................................ 16
5.1
In-System Reprogrammable Flash Program Memory .....................................16
5.2
SRAM Data Memory ........................................................................................17
5.3
EEPROM Data Memory ..................................................................................18
5.4
I/O Memory ......................................................................................................21
5.5
Register Description ........................................................................................22
System Clock and Clock Options ......................................................... 25
6.1
Clock Systems and their Distribution ...............................................................25
6.2
Clock Sources .................................................................................................26
6.3
Calibrated Internal Oscillator ...........................................................................27
6.4
128 kHz Internal Oscillator ..............................................................................28
6.5
External Clock .................................................................................................29
i
8008C–AVR–03/09
7
8
9
6.6
Clock Output Buffer .........................................................................................30
6.7
System Clock Prescaler ..................................................................................30
6.8
Register Description ........................................................................................31
Power Management and Sleep Modes ................................................. 33
7.1
Sleep Modes ....................................................................................................33
7.2
Software BOD Disable .....................................................................................34
7.3
Minimizing Power Consumption ......................................................................35
7.4
Register Description ........................................................................................36
System Control and Reset .................................................................... 39
8.1
Resetting the AVR ...........................................................................................39
8.2
Reset Sources .................................................................................................40
8.3
Internal Voltage Reference ..............................................................................42
8.4
Watchdog Timer ..............................................................................................42
8.5
Register Description ........................................................................................44
Interrupts ................................................................................................ 47
9.1
Interrupt Vectors ..............................................................................................47
9.2
External Interrupts ...........................................................................................48
9.3
Register Description ........................................................................................50
10 I/O-Ports .................................................................................................. 55
10.1
Introduction ......................................................................................................55
10.2
Ports as General Digital I/O .............................................................................56
10.3
Alternate Port Functions ..................................................................................60
10.4
Register Description ........................................................................................72
11 8-bit Timer/Counter0 .............................................................................. 75
11.1
Features ..........................................................................................................75
11.2
Overview ..........................................................................................................75
11.3
Timer/Counter Clock Sources .........................................................................76
11.4
Counter Unit ....................................................................................................76
11.5
Output Compare Unit .......................................................................................77
11.6
Modes of Operation .........................................................................................78
11.7
Timer/Counter Timing Diagrams .....................................................................79
11.8
8-bit Timer/Counter Register Description ........................................................80
12 16-bit Timer/Counter1 with PWM .......................................................... 84
12.1
ii
Features ..........................................................................................................84
ATtiny48/88
8008C–AVR–03/09
ATtiny48/88
12.2
Overview ..........................................................................................................84
12.3
Accessing 16-bit Registers ..............................................................................86
12.4
Timer/Counter Clock Sources .........................................................................88
12.5
Counter Unit ....................................................................................................89
12.6
Input Capture Unit ...........................................................................................90
12.7
Output Compare Units .....................................................................................92
12.8
Compare Match Output Unit ............................................................................94
12.9
Modes of Operation .........................................................................................95
12.10
Timer/Counter Timing Diagrams ...................................................................102
12.11
Register Description ......................................................................................105
13 Timer/Counter0 and Timer/Counter1 Prescalers .............................. 112
13.1
Internal Clock Source ....................................................................................112
13.2
Prescaler Reset .............................................................................................112
13.3
External Clock Source ...................................................................................112
13.4
Register Description ......................................................................................113
14 Serial Peripheral Interface – SPI ......................................................... 115
14.1
Features ........................................................................................................115
14.2
Overview ........................................................................................................115
14.3
SS Pin Functionality ......................................................................................119
14.4
Data Modes ...................................................................................................120
14.5
Register Description ......................................................................................121
15 2-Wire Serial Interface ......................................................................... 124
15.1
Features ........................................................................................................124
15.2
2-wire Serial Interface Bus Definition ............................................................124
15.3
Data Transfer and Frame Format ..................................................................125
15.4
Multi-master Bus Systems, Arbitration and Synchronization .........................128
15.5
Overview of the TWI Module .........................................................................130
15.6
Using the TWI ................................................................................................132
15.7
Transmission Modes .....................................................................................135
15.8
Multi-master Systems and Arbitration ............................................................149
15.9
Register Description ......................................................................................151
16 Analog Comparator ............................................................................. 155
16.1
Analog Comparator Multiplexed Input ...........................................................155
16.2
Register Description ......................................................................................156
iii
8008C–AVR–03/09
17 Analog-to-Digital Converter ................................................................ 158
17.1
Features ........................................................................................................158
17.2
Overview ........................................................................................................158
17.3
Operation .......................................................................................................159
17.4
Starting a Conversion ....................................................................................160
17.5
Prescaling and Conversion Timing ................................................................161
17.6
Changing Channel or Reference Selection ...................................................164
17.7
ADC Noise Canceler .....................................................................................165
17.8
Analog Input Circuitry ....................................................................................165
17.9
Analog Noise Canceling Techniques .............................................................166
17.10
ADC Accuracy Definitions .............................................................................167
17.11
ADC Conversion Result .................................................................................169
17.12
Temperature Measurement ...........................................................................169
17.13
Register Description ......................................................................................170
18 debugWIRE On-chip Debug System .................................................. 175
18.1
Features ........................................................................................................175
18.2
Overview ........................................................................................................175
18.3
Physical Interface ..........................................................................................175
18.4
Software Break Points ...................................................................................176
18.5
Limitations of debugWIRE .............................................................................176
18.6
Register Description ......................................................................................176
19 Self-Programming the Flash ............................................................... 177
19.1
Addressing the Flash During Self-Programming ...........................................178
19.2
Register Description ......................................................................................182
20 Memory Programming ......................................................................... 184
20.1
Program And Data Memory Lock Bits ...........................................................184
20.2
Fuse Bits ........................................................................................................184
20.3
Signature Bytes .............................................................................................186
20.4
Calibration Byte .............................................................................................186
20.5
Page Size ......................................................................................................187
20.6
Parallel Programming Parameters, Pin Mapping, and Commands ...............187
20.7
Parallel Programming ....................................................................................189
20.8
Serial Downloading ........................................................................................196
21 Electrical Characteristics .................................................................... 201
21.1
iv
Absolute Maximum Ratings* .........................................................................201
ATtiny48/88
8008C–AVR–03/09
ATtiny48/88
21.2
DC Characteristics .........................................................................................201
21.3
Speed Grades ...............................................................................................203
21.4
Clock Characterizations .................................................................................203
21.5
System and Reset Characterizations ............................................................204
21.6
Analog Comparator Characteristics ...............................................................205
21.7
ADC Characteristics – Preliminary Data ........................................................206
21.8
2-wire Serial Interface Characteristics ...........................................................207
21.9
SPI Characteristics ........................................................................................209
21.10
Parallel Programming Characteristics ...........................................................211
21.11
Serial Programming Characteristics ..............................................................213
22 Typical Charateristics .......................................................................... 215
22.1
Active Supply Current ....................................................................................215
22.2
Idle Supply Current ........................................................................................218
22.3
Power-down Supply Current ..........................................................................220
22.4
Pin Pull-up .....................................................................................................221
22.5
Pin Driver Strength ........................................................................................224
22.6
Pin Threshold and Hysteresis ........................................................................232
22.7
BOD Threshold ..............................................................................................235
22.8
Internal Oscillator Speed ...............................................................................236
22.9
Current Consumption of Peripheral Units ......................................................239
22.10
Current Consumption in Reset and Reset Pulsewidth ..................................241
23 Register Summary ............................................................................... 243
24 Instruction Set Summary .................................................................... 247
25 Ordering Information ........................................................................... 249
25.1
ATtiny48 ........................................................................................................249
25.2
ATtiny88 ........................................................................................................250
26 Packaging Information ........................................................................ 251
26.1
32A ................................................................................................................251
26.2
28M1 ..............................................................................................................252
26.3
28P3 ..............................................................................................................253
26.4
32M1-A ..........................................................................................................254
27 Errata ..................................................................................................... 255
27.1
ATtiny48 ........................................................................................................255
27.2
ATtiny88 ........................................................................................................256
v
8008C–AVR–03/09
28 Datasheet Revision History ................................................................ 257
28.1
Rev. 8008C - 03/09 .......................................................................................257
28.2
Rev. 8008B - 06/08 ........................................................................................257
28.3
Rev. 8008A - 06/08 ........................................................................................257
Table of Contents....................................................................................... i
vi
ATtiny48/88
8008C–AVR–03/09
ATtiny48/88
vii
8008C–AVR–03/09
Headquarters
International
Atmel Corporation
2325 Orchard Parkway
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USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
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Sales Contact
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8008C–AVR–03/09