DM74LS962 (DM86LS62) Dual Rank 8-Bit TRI-STATEÉ Shift Register General Description Features These circuits are TRI-STATE, edge-triggered, 8-bit I/O registers in parallel with 8-bit serial shift registers which are capable of operating in any of the following modes: parallel load from I/O pins to register ‘‘A’’, parallel transfer down from register ‘‘A’’ to serial shift register ‘‘B’’, parallel transfer up from shift register ‘‘B’’ to register ‘‘A’’, serial shift of register ‘‘B’’, or exchange data between register ‘‘A’’ and shift register ‘‘B’’. Since the registers are edge-triggered by the positive transition of the clock, the control lines which determine the mode or operation are completely independent of the logic level applied to the clock. Designed for bus-oriented systems, these circuits have their TRI-STATE inputs and outputs on the same pins. Y Y Y Y Y Y Y Y Y Registers are edge-triggered by the positive transition of the clock All inputs are PNP transistors Input disable dominates over output disable Output high impedance state does not impede any other mode of operation 8-bit I/O pins are TRI-STATE buffers Typical shift frequency is 36 MHz Typical power dissipation is 305 mW All control inputs are active when in an ‘‘L’’ logic state Devices can be cascaded into N-bit word Connection Diagram Dual-In-Line Package Pin Description DISOÐOutput disable ISÐSerial input DISIÐInput disable DISTUÐTransfer up disable DISTDÐTransfer down disable DISSÐShift disable OSÐSerial output CLKÐClock GNDÐGround I/O 1 . . . I/O 8Ð8-bit I/O pins VCCÐSupply Voltage TL/F/6438 – 1 Top View Order Number DM74LS962N or DM86LS62N See NS Package Number N18A TRI-STATEÉ is a registered trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation TL/F/6438 RRD-B30M105/Printed in U. S. A. DM74LS962 (DM86LS62) Dual Rank 8-Bit TRI-STATE Shift Register August 1991 Absolute Maximum Ratings (Note) Supply Voltage 7V Input Voltage 7V Note: The ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the ‘‘Electrical Characteristics’’ table are not guaranteed at the absolute maximum ratings. The ‘‘Recommended Operating Conditions’’ table will define the conditions for actual device operation. Operating Free Air Temperature Range DM74LS/DM86LS 0§ C to a 70§ C b 65§ C to a 150§ C Storage Temperature Range Lead Temperature (Soldering, 10 seconds) 300§ C Recommended Operating Conditions Symbol Parameter Min Typ Max Units 4.75 5 5.25 V VCC Supply Voltage VIH High-Level Input Voltage VIL Low-Level Input Voltage IOH High-Level Output Current IOL Low-Level Output Current fCLOCK Clock Frequency (Note 5) 0 Clock Pulse High Pulse Width (Note 5) 25 17 Low Pulse Width (Note 5) 15 7 tSET-UP Data Set-Up Time (Note 5) 10 ns tHOLD Data Hold Time (Note 5) 0 ns TA Free Air Operating Temperature 0 2 V 0.8 V b 5.2 mA 16 mA 25 MHz ns ns 70 §C Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter Conditions (1) VI Input Clamp Voltage VCC e Min, II e b18 mA VOH High-Level Output Voltage VCC e Min, VIH e 2 V, VIL e VIL Max VOL Low-Level Output Voltage VCC e Min, VIH e 2 V, VIL e VIL Max II Input Current at Maximum Input Voltage VCC e Max, VI e 5.5V IIH High-Level Input Current IIL Low-Level Input Current IOS Short-Circuit Output Current VCC e Max (3) ICC Supply Current VCC e Max (4) IOFF TRI-STATE I/O Current VCC e Max, VIH e 2V Min Typ (2) Max Units b 1.5 V IOH e b2.6 mA IOH e b5.2 mA V 2.4 IOL e 8 mA 0.25 0.4 IOL e 16 mA 0.35 0.5 V 0.1 mA VCC e Max, VI e 2.7V 20 mA VCC e Max, VI e 0.4V b 50 mA b 100 mA b 20 99 mA VO e 2.4V 61 20 mA VO e 0.4V b 20 mA Note 1: For conditions shown as min or max, use the appropriate value specified under recommended operating conditions. Note 2: All typical values are at VCC e 5V, TA e 25§ C. Note 3: Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second. Note 4: ICC is measured with serial output open, the clock and shift disable input at 2.4V. All other control inputs and I/O pins grounded. Note 5: TA e 25§ C and VCC e 5V. 2 Switching Characteristics VCC e 5V and TA e 25§ C Symbol Parameter Conditions Min Max Units fMAX Maximum Clock Frequency 25 tPLH Propagation Delay Time, Low-to-High-Level from Clock to Any Outputs 7 33 ns tPHL Propagation Delay Time, High-to-Low Level from Clock to Any Outputs 10 48 ns CL e 15 pF, RL e 1 kX MHz tENABLE Enable Time from Any Control Inputs 5 30 ns tDISABLE Disable Time from Any Control Inputs 6 30 ns tZH Output Enable Time to High Level 5 23 ns tZL Output Enable to Low Level 4 18 ns tHZ Output Disable Time from High Level 5 23 ns tLZ Output Disable Time from Low Level 6 27 ns CL e 5 pF, RL e 1 kX Logic Diagram TL/F/6438 – 2 3 4 H H L H H L H H L H H L H L X H L X H L X H L X A a1 . . . a8/b1 . . . b8 L L L L L L X X X X X X H H H H H H DISS u u u u u u u u u u u u u u u u X X CLK d d d d d d X X X X X X X X X X X X IS Hi-Z Output Input Hi-Z Output Input Hi-Z Output Input Hi-Z Output Input Hi-Z Output Input Hi-Z Output Input b1 b1 a1 a1 I1 b1 b1 a1 a1 I1 b1 b1 a1 a1 I1 A1 a4 a4 I4 A4 a5 a5 I5 A5 a6 a6 I6 A6 a7 a7 I7 A7 a8 a8 I8 a4 a4 I4 a5 a5 I5 a6 a6 I6 a7 a7 I7 a8 a8 I8 b3 b3 a3 a3 I3 a4 a4 I4 a5 a5 I5 a6 a6 I6 a7 a7 I7 a8 a8 I8 b4 b5 b6 b7 b8 b4 b5 b6 b7 b8 www DOR xxx b2 b2 a2 a2 I2 b3 b3 a3 a3 I3 b4 b5 b6 b7 b8 b4 b5 b6 b7 b8 www DOR xxx b2 b2 a2 a2 I2 b3 b3 a3 a3 I3 A3 b4 b5 b6 b7 b8 b4 b5 b6 b7 b8 www DOR xxx b2 b2 a2 a2 I2 A2 A8 Table I Content of Upper Reg. ‘‘A’’ b1 b1 b1 b1 b1 b1 a2 a2 a2 a2 a2 a2 b2 b2 b2 b2 b2 b2 b2 b2 b2 b2 b2 b2 a3 a3 a3 a3 a3 a3 b3 b3 b3 b3 b3 b3 B3 b3 b3 b3 b3 b3 b3 a4 a4 a4 a4 a4 a4 b4 b4 b4 b4 b4 b4 B4 u transition of the clock d d d d d d a1 a1 a1 a1 a1 a1 b1 b1 b1 b1 b1 b1 B2 b4 b4 b4 b4 b4 b4 a5 a5 a5 a5 a5 a5 b5 b5 b5 b5 b5 b5 B5 b5 b5 b5 b5 b5 b5 a6 a6 a6 a6 a6 a6 b6 b6 b6 b6 b6 b6 B6 b6 b6 b6 b6 b6 b6 a7 a7 a7 a7 a7 a7 b7 b7 b7 b7 b7 b7 B7 b7 b7 b7 b7 b7 b7 a8 a8 a8 a8 a8 a8 b8 b8 b8 b8 b8 b8 B8 Content of Lower Serial Shift Reg. ‘‘B’’ B1 The content of the upper register ‘‘A’’/the lower serial shift register ‘‘B’’ before the most recent High impedance state/output state/input state H H H H H H L L L L L L H H H H H H DISTD 8-Bit I/O Pins I1 . . . I8 A The level of steady state inputs of the I/O pins DOR A ‘‘Data ORing function’’ ORing data from both I/O pins and register ‘‘B’’, i.e., I1 a b1, I2 a b2, I3 a b3 . . . I8 a b8 d A Data of the serial input A Hi-Z/Output/Input/ L L L H H H L L L H H H L L L H H H DISTU Don’t Care H H L H L X A H H L H L X X DISI DISO Function Table b7 b7 b7 b7 b7 b7 a8 a8 a8 a8 a8 a8 b8 b8 b8 b8 b8 b8 OS Stable state DOR function and serial shifting Transfer up and serial shifting Entering data and serial shifting Serial shifting in the lower reg. ‘‘B’’ (1) Exchange data between registers (2) Beside data exchanging, reg. ‘‘A’’ (3) will ‘‘OR’’ data from I/O and reg. ‘‘B’’ Entering data and transfer down Transfer data down from reg. ‘‘A’’ to reg. ‘‘B’’ Reg. ‘‘A’’ will OR data from I/O to reg. ‘‘B’’ Transfer data up from reg. ‘‘B’’ to reg. ‘‘A’’ Entering data from I/O to reg. ‘‘A’’ Comments Timing Diagram TL/F/6438 – 3 5 AC Test Circuit and Switching Time Waveforms All diodes are 1N916 or 1N3064. CL includes probe and jig capacitance. TL/F/6438 – 4 TL/F/6438 – 5 All input pulses are supplied by generators having tr s 15 ns, tf s 6 ns, PRR s 1MHz, ZOUT & 50X. Cascading Packages Cascading Packages for N-Bit Word TL/F/6438 – 6 6 7 DM74LS962 (DM86LS62) Dual Rank 8-Bit TRI-STATE Shift Register Physical Dimensions inches (millimeters) 18-Lead Molded Dual-In-Line Package (N) Order Number DM74LS962N or DM86LS62N NS Package Number N18A LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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