AD AD9775 14-bit, 160 msps, 2/4/8 interpolating Datasheet

14-Bit, 160 MSPS, 2×/4×/8× Interpolating
Dual TxDAC+® Digital-to-Analog Converter
AD9775
FEATURES
Versatile input data interface
Twos complement/straight binary data coding
Dual-port or single-port interleaved input data
Single 3.3 V supply operation
Power dissipation: 1.2 W @ 3.3 V typical
On-chip, 1.2 V reference
80-lead, thin quad flat package, exposed pad (TQFP_EP)
14-bit resolution, 160 MSPS/400 MSPS input/output
data rate
Selectable 2×/4×/8× interpolating filter
Programmable channel gain and offset adjustment
fS/4, fS/8 digital quadrature modulation capability
Direct IF transmission mode for 70 MHz + IFs
Enables image rejection architecture
Fully compatible SPI® port
Excellent ac performance
SFDR: −71 dBc @ 2 MHz to 35 MHz
W-CDMA ACPR: −71 dB @ IF = 19.2 MHz
Internal PLL clock multiplier
Selectable internal clock divider
Versatile clock input
Differential/single-ended sine wave or TTL/CMOS/LVPECL
compatible
APPLICATIONS
Communications
Analog quadrature modulation architecture
3G, multicarrier GSM, TDMA, CDMA systems
Broadband wireless, point-to-point microwave radios
Instrumentation/ATE
FUNCTIONAL BLOCK DIAGRAM
IDAC
COS
AD9775
I AND Q
NONINTERLEAVED
OR INTERLEAVED
DATA
14
WRITE
SELECT
HALFBAND
FILTER3*
GAIN
DAC
OFFSET
DAC
SIN
I
LATCH
16
Q
LATCH
16
MUX
CONTROL
HALFBAND
FILTER2*
16
16
16
fDAC/2, 4, 8
16
16
SIN
16
FILTER
BYPASS
MUX
IMAGE
REJECTION/
DUAL DAC
MODE
BYPASS
MUX
I/Q DAC
GAIN/OFFSET
REGISTERS
IOFFSET
14
HALFBAND
FILTER1*
VREF
DATA
ASSEMBLER
COS
IDAC
/2
IOUT
(fDAC)
CLOCK OUT
/2
/2
/2
SPI INTERFACE AND
CONTROL REGISTERS
DIFFERENTIAL
CLK
PHASE DETECTOR
AND VCO
PLL CLOCK MULTIPLIER AND CLOCK DIVIDER
02858-001
* HALF-BAND FILTERS ALSO CAN BE
CONFIGURED FOR ZERO STUFFING ONLY
PRESCALER
Figure 1.
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
AD9775
TABLE OF CONTENTS
Features .............................................................................................. 1
1R/2R Mode ................................................................................ 25
Applications....................................................................................... 1
Clock Input Configurations...................................................... 25
Functional Block Diagram .............................................................. 1
Programmable PLL .................................................................... 26
Revision History ............................................................................... 3
Power Dissipation....................................................................... 27
General Description ......................................................................... 4
Sleep/Power-Down Modes........................................................ 28
Product Highlights ....................................................................... 4
Two-Port Data Input Mode ...................................................... 28
Specifications..................................................................................... 5
PLL Enabled, Two-Port Mode .................................................. 28
DC Specifications ......................................................................... 5
DATACLK Inversion.................................................................. 29
Dynamic Specifications ............................................................... 6
DATACLK Driver Strength....................................................... 29
Digital Specifications ................................................................... 7
PLL Enabled, One-Port Mode .................................................. 29
Digital Filter Specifications ......................................................... 8
ONEPORTCLK Inversion......................................................... 29
Absolute Maximum Ratings............................................................ 9
ONEPORTCLK Driver Strength.............................................. 30
ESD Caution.................................................................................. 9
IQ Pairing .................................................................................... 30
Thermal Resistance ...................................................................... 9
PLL Disabled, Two-Port Mode................................................. 30
Pin Configuration and Function Descriptions........................... 10
PLL Disabled, One-Port Mode ................................................. 30
Typical Performance Characteristics ........................................... 12
Digital Filter Modes ................................................................... 31
Terminology .................................................................................... 17
Amplitude Modulation.............................................................. 31
Mode Control (via SPI Port) ......................................................... 18
Modulation, No Interpolation .................................................. 32
Register Descriptions ..................................................................... 19
Modulation, Interpolation = 2× ............................................... 33
Address 0x00 ............................................................................... 19
Modulation, Interpolation = 4× ............................................... 34
Address 0x01 ............................................................................... 19
Modulation, Interpolation = 8× ............................................... 35
Address 0x02 ............................................................................... 19
Zero Stuffing ............................................................................... 36
Address 0x03 ............................................................................... 20
Interpolating (Complex Mix Mode)........................................ 36
Address 0x04 ............................................................................... 20
Operations on Complex Signals............................................... 36
Address 0x05, Address 0x09 ..................................................... 20
Complex Modulation and Image Rejection of Baseband
Signals .......................................................................................... 37
Address 0x06, Address 0x0A..................................................... 20
Address 0x07, Address 0x0B ..................................................... 20
Address 0x08, Address 0x0C..................................................... 20
Address 0x08, Address 0x0C..................................................... 20
Functional Description .................................................................. 21
Serial Interface for Register Control ........................................ 21
General Operation of the Serial Interface ............................... 21
Image Rejection and Sideband Suppression of Modulated
Carriers ........................................................................................ 38
Applying the Output Configurations........................................... 42
Unbuffered Differential Output, Equivalent Circuit ............. 42
Differential Coupling Using a Transformer............................ 42
Differential Coupling Using an Op Amp................................ 43
Instruction Byte .......................................................................... 22
Interfacing the AD9775 with the AD8345 Quadrature
Modulator.................................................................................... 43
Serial Interface Port Pin Descriptions ..................................... 22
Evaluation Board ............................................................................ 44
MSB/LSB Transfers..................................................................... 22
Outline Dimensions ....................................................................... 54
Notes on Serial Port Operation ................................................ 22
Ordering Guide .......................................................................... 54
DAC Operation........................................................................... 24
Rev. E | Page 2 of 56
AD9775
REVISION HISTORY
12/06—Rev. D to Rev. E
Changes to Figure 52, Figure 54, Figure 55, and Figure 56 .......29
1/06—Rev. C to Rev. D
Updated Formatting..........................................................Universal
Changes to Figure 32 .................................................................... 22
Changes to Figure 108 .................................................................. 55
Updated Outline Dimensions...................................................... 58
Changes to Ordering Guide......................................................... 58
6/04—Rev. B to Rev. C
Updated Layout .................................................................Universal
Changes to DC Specifications ....................................................... 5
Changes to Absolute Maximum Ratings...................................... 9
Changes to the DAC Operation Section .................................... 25
Inserted Figure 38.......................................................................... 25
Changes to Figure 40 .................................................................... 26
Changes to Table 11 ...................................................................... 28
Changes to Programmable PLL Section..................................... 28
Changes to Figures 49, 50, and 51............................................... 29
Changes to the PLL Enabled, One-Port Mode Section............ 30
Changes to the PLL Disabled, One-Port Mode Section........... 31
Changes to the Ordering Guide .................................................. 57
Updated Outline Dimensions...................................................... 57
3/03—Rev. A to Rev. B
Changes to Register Description—Address 04h ....................... 16
Changes to Equation 1.................................................................. 16
Changes to Figure 8....................................................................... 20
2/03—Rev. 0 to Rev. A
Edits to Features ...............................................................................1
Edits to DC Specifications ..............................................................3
Edits to Dynamic Specifications ....................................................4
Edits to Pin Function Descriptions ...............................................8
Edits to Table I ............................................................................... 14
Edits to Register Description—Address 02h ............................. 15
Edits to Register Description—Address 03h ............................. 16
Edits to Register Description—Address 07h, 0Bh.................... 16
Edits to Equation 1........................................................................ 16
Edits to MSB/LSB Transfers......................................................... 18
Edits to Programmable PLL......................................................... 21
Added New Figure 14 ................................................................... 22
Renumbered Figures 15–69 ......................................................... 22
Added Two-Port Data Input Mode Section............................... 23
Edits to PLL Enabled, Two-Port Mode ...................................... 24
Edits to Figure 19 .......................................................................... 24
Edits to Figure 21 .......................................................................... 25
Edits to PLL Disabled, Two-Port Mode ..................................... 25
Edits to Figure 22 .......................................................................... 25
Edits to Figure 23 .......................................................................... 26
Edits to Figure 26a ........................................................................ 27
Edits to Complex Modulation and Image Rejection of Baseband
Signals ............................................................................................. 31
Edits to Evaluation Board ............................................................ 39
Edits to Figures 56–59 .................................................................. 40
Replaced Figures 60–69................................................................ 42
Updated Outline Dimensions...................................................... 49
Rev. E | Page 3 of 56
AD9775
GENERAL DESCRIPTION
The AD97751 is the 14-bit member of the AD977x pincompatible, high performance, programmable 2×/4×/8×
interpolating TxDAC+ family. The AD977x family features a
serial port interface (SPI) that provides a high level of
programmability, thus allowing for enhanced system-level
options. These options include selectable 2×/4×/8×
interpolation filters; fS/2, fS/4, or fS/8 digital quadrature
modulation with image rejection; a direct IF mode;
programmable channel gain and offset control; programmable
internal clock divider; straight binary or twos complement data
interface; and a single-port or dual-port data interface.
The selectable 2×/4×/8× interpolation filters simplify the
requirements of the reconstruction filters while simultaneously
enhancing the pass-band noise/distortion performance of
TxDAC+ devices. The independent channel gain and offset
adjust registers allow the user to calibrate LO feedthrough and
sideband suppression errors associated with analog quadrature
modulators. The 6 dB of gain adjustment range can also be used
to control the output power level of each DAC.
The AD9775 can perform fS/2, fS/4, and fS/8 digital modulation
and image rejection when combined with an analog quadrature
modulator. In this mode, the AD9775 accepts I and Q complex
data (representing a single or multicarrier waveform), generates
a quadrature modulated IF signal along with its orthogonal
representation via its dual DACs, and presents these two
reconstructed orthogonal IF carriers to an analog quadrature
modulator to complete the image rejection upconversion
process. Another digital modulation mode (that is, the direct IF
mode) allows the original baseband signal representation to be
frequency translated such that pairs of images fall at multiples
of one-half the DAC update rate.
The AD977x family includes a flexible clock interface that
accepts differential or single-ended sine wave or digital logic
inputs. An internal PLL clock multiplier is included and
generates the necessary on-chip high frequency clocks. It can
also be disabled to allow the use of a higher performance
external clock source. An internal programmable divider
simplifies clock generation in the converter when using an
external clock source. A flexible data input interface allows for
straight binary or twos complement formats and supports
single-port interleaved or dual-port data.
Dual high performance DAC outputs provide a differential
current output programmable over a 2 mA to 20 mA range.
1
The AD9775 is manufactured on an advanced 0.35 micron
CMOS process, operates from a single supply of 3.1 V to 3.5 V,
and consumes 1.2 W of power.
Targeted at wide dynamic range, multicarrier and multistandard
systems, the superb baseband performance of the AD9775 is
ideal for wideband CDMA, multicarrier CDMA, multicarrier
TDMA, multicarrier GSM, and high performance systems
employing high order QAM modulation schemes. The image
rejection feature simplifies and can help reduce the number of
signal band filters needed in a transmit signal chain. The direct
IF mode helps to eliminate a costly mixer stage for a variety of
communications systems.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
The AD9775 is the 14-bit member of the AD977x pincompatible, high performance, programmable 2×/4×/8×
interpolating TxDAC+ family.
Direct IF transmission capability for 70 MHz + IFs through
a novel digital mixing process.
fS/2, fS/4, and fS/8 digital quadrature modulation and userselectable image rejection to simplify/remove cascaded
SAW filter stages.
A 2×/4×/8× user-selectable, interpolating filter eases data
rate and output signal reconstruction filter requirements.
User-selectable, twos complement/straight binary data
coding.
User-programmable, channel gain control over 1 dB range
in 0.01 dB increments.
User programmable channel offset control ±10% over the
FSR.
Ultrahigh speed 400 MSPS DAC conversion rate.
Internal clock divider provides data rate clock for easy
interfacing.
Flexible clock input with single-ended or differential input,
CMOS, or 1 V p-p LO sine wave input capability.
Low power: complete CMOS DAC operates on 1.2 W from
a 3.1 V to 3.5 V single supply. The 20 mA full-scale current
can be reduced for lower power operation and several sleep
functions are provided to reduce power during idle
periods.
On-chip voltage reference. The AD9775 includes a 1.20 V
temperature compensated band gap voltage reference.
80-lead, thin quad flat package, exposed pad (TQFP_EP).
Protected by U.S. Patent Numbers 5,568,145; 5,689,257; and 5,703,519. Other patents pending.
Rev. E | Page 4 of 56
AD9775
SPECIFICATIONS
DC SPECIFICATIONS
TMIN to TMAX, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, PLLVDD = 3.3 V, IOUTFS = 20 mA, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
DC Accuracy 1
Integral Nonlinearity
Differential Nonlinearity
ANALOG OUTPUT (for 1R and 2R Gain Setting Modes)
Offset Error
Gain Error (with Internal Reference)
Gain Matching
Full-Scale Output Current 2
Output Compliance Range
Output Resistance
Output Capacitance
Gain, Offset Cal DACs, Monotonicity Guaranteed
REFERENCE OUTPUT
Reference Voltage
Reference Output Current 3
REFERENCE INPUT
Input Compliance Range
Reference Input Resistance
Small Signal Bandwidth
TEMPERATURE COEFFICIENTS
Offset Drift
Gain Drift (with Internal Reference)
Reference Voltage Drift
POWER SUPPLY
AVDD
Voltage Range
Analog Supply Current (IAVDD) 4
IAVDD in SLEEP Mode
CLKVDD
Voltage Range
Clock Supply Current (ICLKVDD)4
CLKVDD (PLL ON)
Clock Supply Current (ICLKVDD)
DVDD
Voltage Range
Digital Supply Current (IDVDD)4
Nominal Power Dissipation
PDIS 5
PDIS IN PWDN
Power Supply Rejection Ratio—AVDD
OPERATING RANGE
Min
14
Typ
Max
Unit
Bits
−5
−3
±1.5
±1.0
+5
+3
LSB
LSB
−0.02
−1.0
−1.0
2
−1.0
±0.01
+0.02
+1.0
+1.0
20
+1.25
% of FSR
% of FSR
% of FSR
mA
V
kΩ
pF
1.26
V
nA
1.25
7
0.5
V
kΩ
MHz
0
50
±50
ppm of FSR/°C
ppm of FSR/°C
ppm/°C
±0.1
200
3
1.14
1.20
100
0.1
3.1
3.3
72.5
23.3
3.5
76
26
V
mA
mA
3.1
3.3
8.5
3.5
10.0
V
mA
23.5
3.1
−40
1
Measured at IOUTA driving a virtual ground.
Nominal full-scale current, IOUTFS, is 32 × the IREF current.
Use an external amplifier to drive any external load.
4
100 MSPS fDAC with fOUT = 1 MHz, all supplies = 3.3 V, no interpolation, no modulation.
5
400 MSPS fDAC = 50 MSPS, fS/2 modulation, PLL enabled.
2
3
Rev. E | Page 5 of 56
3.3
34
380
1.75
6.0
±0.4
mA
3.5
41
410
+85
V
mA
mW
W
mW
% of FSR/V
°C
AD9775
DYNAMIC SPECIFICATIONS
TMIN to TMAX, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, PLLVDD = 0 V, IOUTFS = 20 mA, interpolation = 2×, differential
transformer-coupled output, 50 Ω doubly terminated, unless otherwise noted.
Table 2.
Parameter
DYNAMIC PERFORMANCE
Maximum DAC Output Update Rate (fDAC)
Output Settling Time (tST) to 0.025%
Output Rise Time 10% to 90% 1
Output Fall Time 10% to 90%1
Output Noise, IOUTFS = 20 mA
AC LINEARITY—BASEBAND MODE
Spurious-Free Dynamic Range (SFDR) to Nyquist (fOUT = 0 dBFS)
fDATA = 100 MSPS, fOUT = 1 MHz
fDATA = 65 MSPS, fOUT = 1 MHz
fDATA = 65 MSPS, fOUT = 15 MHz
fDATA = 78 MSPS, fOUT = 1 MHz
fDATA = 78 MSPS, fOUT = 15 MHz
fDATA = 160 MSPS, fOUT = 1 MHz
fDATA = 160 MSPS, fOUT = 15 MHz
Spurious-Free Dynamic Range Within a 1 MHz Window
fOUT = 0 dBFS, fDATA = 100 MSPS, fOUT = 1 MHz
Two-Tone Intermodulation (IMD) to Nyquist (fOUT1 = fOUT2 = −6 dBFS)
fDATA = 65 MSPS, fOUT1 = 10 MHz; fOUT2 = 11 MHz
fDATA = 65 MSPS, fOUT1 = 20 MHz; fOUT2 = 21 MHz
fDATA = 78 MSPS, fOUT1 = 10 MHz; fOUT2 = 11 MHz
fDATA = 78 MSPS, fOUT1 = 20 MHz; fOUT2 = 21 MHz
fDATA = 160 MSPS, fOUT1 = 10 MHz; fOUT2 = 11 MHz
fDATA = 160 MSPS, fOUT1 = 20 MHz; fOUT2 = 21 MHz
Total Harmonic Distortion (THD)
fDATA = 100 MSPS, fOUT = 1 MHz; 0 dBFS
Signal-to-Noise Ratio (SNR)
fDATA = 78 MSPS, fOUT = 5 MHz; 0 dBFS
fDATA = 160 MSPS, fOUT = 5 MHz; 0 dBFS
Adjacent Channel Power Ratio (ACPR)
W-CDMA with 3.84 MHz BW, 5 MHz Channel Spacing
IF = Baseband, fDATA = 76.8 MSPS
IF = 19.2 MHz, fDATA = 76.8 MSPS
Four-Tone Intermodulation
21 MHz, 22 MHz, 23 MHz, and 24 MHz at −12 dBFS (fDATA = MSPS, Missing Center)
AC LINEARITY—IF MODE
Four-Tone Intermodulation at IF = 200 MHz
201 MHz, 202 MHz, 203 MHz, and 204 MHz at −12 dBFS (fDATA = 160 MSPS, fDAC = 320 MHz)
1
Measured single-ended into 50 Ω load.
Rev. E | Page 6 of 56
Min
Typ
400
Max
Unit
11
0.8
0.8
50
MSPS
ns
ns
ns
pA/√Hz
71
84.5
84
80
84
80
82
80
dBc
dBc
dBc
dBc
dBc
dBc
dBc
73
91.3
dBc
81
76
81
76
81
76
dBc
dBc
dBc
dBc
dBc
dBc
−82.5
dB
76
74
dB
dB
71
71
dBc
dBc
75
dBFS
72
dBFS
−71
AD9775
DIGITAL SPECIFICATIONS
TMIN to TMAX, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V, DVDD = 3.3 V, IOUTFS = 20 mA, unless otherwise noted.
Table 3.
Parameter
DIGITAL INPUTS
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Current
Logic 0 Current
Input Capacitance
CLOCK INPUTS
Input Voltage Range
Common-Mode Voltage
Differential Voltage
SERIAL CONTROL BUS
Maximum SCLK Frequency (fSLCK)
Minimum Clock Pulse Width High (tPWH)
Minimum Clock Pulse Width Low (tPWL)
Maximum Clock Rise/Fall Time
Minimum Data/Chip Select Setup Time (tDS)
Minimum Data Hold Time (tDH)
Maximum Data Valid Time (tDV)
RESET Pulse Width
Inputs (SDI, SDIO, SCLK, CSB)
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Current
Logic 0 Current
Input Capacitance
SDIO Output
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Current
Logic 0 Current
Min
Typ
2.1
3
0
−10
−10
Max
Unit
0.9
+10
+10
V
V
μA
μA
pF
5
0
0.75
0.5
1.5
1.5
3
2.25
15
30
30
1
25
0
30
1.5
2.1
3
0
−10
−10
0.9
+10
+10
5
DRVDD − 0.6
0.4
30
30
Rev. E | Page 7 of 56
50
50
V
V
V
MHz
ns
ns
ms
ns
ns
ns
ns
V
V
μA
μA
pF
V
V
mA
mA
AD9775
DIGITAL FILTER SPECIFICATIONS
20
Table 4. Half-Band Filter No. 1 (43 Coefficients)
0
ATTENUATION (dBFS)
–20
–40
–60
–80
–100
0.5
1.0
1.5
2.0
02858-002
0
2.0
02858-003
–120
8
02858-004
Coefficient
8
0
−29
0
67
0
−134
0
244
0
−414
0
673
0
−1079
0
1772
0
−3280
0
10,364
16,384
fOUT (NORMALIZED TO INPUT DATA RATE)
Figure 2. 2× Interpolating Filter Response
20
0
ATTENUATION (dBFS)
Tap
1, 43
2, 42
3, 41
4, 40
5, 39
6, 38
7, 37
8, 36
9, 35
10, 34
11, 33
12, 32
13, 31
14, 30
15, 29
16, 28
17, 27
18, 26
19, 25
20, 24
21, 23
22
–20
–40
–60
–80
Table 5. Half-Band Filter No. 2 (19 Coefficients)
Coefficient
19
0
−120
0
438
0
−1288
0
5,047
8,192
Table 6. Half-Band Filter No. 3 (11 Coefficients)
Tap
1, 11
2, 10
3, 9
4, 8
5, 7
6
Coefficient
7
0
−53
0
302
512
–100
–120
0
0.5
1.0
1.5
fOUT (NORMALIZED TO INPUT DATA RATE)
Figure 3. 4× Interpolating Filter Response
20
0
ATTENUATION (dBFS)
Tap
1, 19
2, 18
3, 17
4, 16
5, 15
6, 14
7, 13
8, 12
9, 11
10
–20
–40
–60
–80
–100
–120
0
2
4
6
fOUT (NORMALIZED TO INPUT DATA RATE)
Figure 4. 8× Interpolating Filter Response
Rev. E | Page 8 of 56
AD9775
ABSOLUTE MAXIMUM RATINGS
Table 7.
Parameter
AVDD, DVDD, CLKVDD
AVDD, DVDD, CLKVDD
AGND, DGND, CLKGND
REFIO, FSADJ1/FSADJ2
IOUTA, IOUTB
P1B13 to P1B0, P2B13 to P2B0, RESET
DATACLK, PLL_LOCK
CLK+, CLK–
LPF
SPI_CSB, SPI_CLK, SPI_SDIO, SPI_SDO
Junction Temperature
Storage Temperature
Lead Temperature (10 sec)
With Respect To
AGND, DGND, CLKGND
AVDD, DVDD, CLKVDD
AGND, DGND, CLKGND
AGND
AGND
DGND
DGND
CLKGND
CLKGND
DGND
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rating
−0.3 V to +4.0 V
−4.0 V to +4.0 V
−0.3 V to +0.3 V
−0.3 V to AVDD + 0.3 V
−1.0 V to AVDD + 0.3 V
−0.3 V to DVDD + 0.3 V
−0.3 V to DVDD + 0.3 V
−0.3 V to CLKVDD + 0.3 V
−0.3 V to CLKVDD + 0.3 V
−0.3 V to DVDD + 0.3 V
125°C
−65°C to +150°C
300°C
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 8. Thermal Resistance
Package Type
80-Lead Thin Quad Flat Package
(TQFP_EP), Exposed Pad
Rev. E | Page 9 of 56
θJA
23.5
Unit
°C/W
AD9775
AVDD
AGND
AVDD
AGND
AVDD
AGND
AGND
IOUTB2
IOUTA2
AGND
AGND
IOUTB1
IOUTA1
AGND
AGND
AVDD
AGND
AVDD
AGND
AVDD
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
CLKVDD 1
60
FSADJ1
59
FSADJ2
CLKVDD 3
58
REFIO
CLKGND
4
57
RESET
CLK+
5
56
SPI_CSB
CLK–
6
55
SPI_CLK
CLKGND
7
54
SPI_SDIO
DATACLK/PLL_LOCK
8
53
SPI_SDO
DGND
9
52
DGND
51
DVDD
P1B13 (MSB) 11
50
NC
P1B12 12
49
NC
P1B11 13
48
P2B0 (LSB)
P1B10 14
47
P2B1
P1B9 15
46
P2B2
P1B8 16
45
P2B3
DGND 17
44
DGND
DVDD 18
43
DVDD
P1B7 19
42
P2B4
P1B6 20
41
P2B5
LPF
PIN 1
2
AD9775
TxDAC+
TOP VIEW
(Not to Scale)
DVDD 10
Figure 5. Pin Configuration
Rev. E | Page 10 of 56
02858-005
P2B6
P2B7
P2B8
P2B9
DVDD
DGND
P2B10
P2B11
ONEPORTCLK/P2B12
IQSEL/P2B13 (MSB)
NC
NC
P1B0 (LSB)
P1B1
DVDD
DGND
P1B2
P1B3
P1B4
P1B5
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
NC = NO CONNECT
AD9775
Table 9. Pin Function Descriptions
Pin No.
1, 3
2
4, 7
5
6
8
Mnemonic
CLKVDD
LPF
CLKGND
CLK+
CLK−
DATACLK/PLL_LOCK
Description
Clock Supply Voltage.
PLL Loop Filter.
Clock Supply Common.
Differential Clock Input.
Differential Clock Input.
With the PLL enabled, this pin indicates the state of the PLL. A read of a Logic 1
indicates the PLL is in the locked state. Logic 0 indicates the PLL has not achieved
lock. This pin may also be programmed to act as either an input or output
(Address 02h, Bit 3) DATACLK signal running at the input data rate.
Digital Common.
Digital Supply Voltage.
Port 1 Data Inputs.
9, 17, 25, 35, 44, 52
10, 18, 26, 36, 43, 51
11 to 16, 19 to 24, 27, 28
29, 30, 49, 50
31
DGND
DVDD
P1B13 (MSB) to P1B0
(LSB)
NC
IQSEL/P2B13 (MSB)
32
ONEPORTCLK/P2B12
33, 34, 37 to 42, 45 to 48
53
P2B11 to P2B0 (LSB)
SPI_SDO
54
SPI_SDIO
55
SPI_CLK
56
SPI_CSB
57
RESET
58
59
60
61, 63, 65, 76, 78, 80
62, 64, 66, 67, 70, 71,
74, 75, 77, 79
68, 69
72, 73
REFIO
FSADJ2
FSADJ1
AVDD
AGND
No Connect.
In one-port mode, IQSEL = 1 followed by a rising edge of the differential input
clock latches the data into the I channel input register. IQSEL = 0 latches the data
into the Q channel input register. In two-port mode, this pin becomes the Port 2
MSB.
With the PLL disabled and the AD9775 in one-port mode, this pin becomes a
clock output that runs at twice the input data rate of the I and Q channels. This
allows the AD9775 to accept and demux interleaved I and Q data to the I and Q
input registers.
Port 2 Data Inputs.
In the case where SDIO is an input, SDO acts as an output. When SDIO becomes an
output, SDO enters a High-Z state. This pin can also be used as an output for the
data rate clock. For more information, see the Two-Port Data Input Mode section.
Bidirectional Data Pin. Data direction is controlled by Bit 7 of Register Address 0x00.
The default setting for this bit is 0, which sets SDIO as an input.
Data input to the SPI port is registered on the rising edge of SPI_CLK. Data output
on the SPI port is registered on the falling edge.
Chip Select/SPI Data Synchronization. On momentary logic high, resets SPI port
logic and initializes instruction cycle.
Logic 1 resets all of the SPI port registers, including Address 0x00, to their default
values. A software reset can also be done by writing a Logic 1 to SPI Register 00h,
Bit 5. However, the software reset has no effect on the bit in Address 0x00.
Reference Output, 1.2 V Nominal.
Full-Scale Current Adjust, Q Channel.
Full-Scale Current Adjust, I Channel.
Analog Supply Voltage.
Analog Common.
IOUTB2, IOUTA2
IOUTB1, IOUTA1
Differential DAC Current Outputs, Q Channel.
Differential DAC Current Outputs, I Channel.
Rev. E | Page 11 of 56
AD9775
TYPICAL PERFORMANCE CHARACTERISTICS
10
10
0
0
–10
–10
–20
–20
AMPLITUDE (dBm)
–30
–40
–50
–60
–30
–40
–50
–60
–70
–70
–80
–80
–90
65
130
FREQUENCY (MHz)
02858-006
–90
0
0
50
100
02858-009
AMPLITUDE (dBm)
T = 25°C, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, IOUTFS = 20 mA, interpolation = 2×, differential transformer-coupled output,
50 Ω doubly terminated, unless otherwise noted.
150
FREQUENCY (MHz)
Figure 6. Single-Tone Spectrum @ fDATA = 65 MSPS with fOUT = fDATA/3
Figure 9. Single-Tone Spectrum @ fDATA = 78 MSPS with fOUT = fDATA/3
90
90
0dBFS
0dBFS
85
85
–6dBFS
80
75
SFDR (dBc)
–12dBFS
70
65
75
–12dBFS
70
–6dBFS
65
60
60
55
55
5
10
15
20
25
30
FREQUENCY (MHz)
02858-007
0
0
5
10
15
20
25
30
02858-010
50
50
30
02858-011
SFDR (dBc)
80
FREQUENCY (MHz)
Figure 7. In-Band SFDR vs. fOUT @ fDATA = 65 MSPS
Figure 10. In-Band SFDR vs. fOUT @ fDATA = 78 MSPS
90
90
–6dBFS
85
85
–6dBFS
80
75
75
SFDR (dBc)
80
70
–12dBFS
65
0dBFS
70
–12dBFS
65
60
60
55
55
50
50
0
5
10
15
20
25
FREQUENCY (MHz)
30
02858-008
SFDR (dBc)
0dBFS
Figure 8. Out-of-Band SFDR vs. fOUT @ fDATA = 65 MSPS
0
5
10
15
20
25
FREQUENCY (MHz)
Figure 11. Out-of-Band SFDR vs. fOUT @ fDATA = 78 MSPS
Rev. E | Page 12 of 56
AD9775
10
90
–6dBFS
0
–3dBFS
85
–10
–30
IMD (dBc)
AMPLITUDE (dBm)
80
–20
–40
–50
75
0dBFS
70
65
–60
60
–70
55
–80
–90
200
300
FREQUENCY (MHz)
0
5
10
15
20
25
30
FREQUENCY (MHz)
Figure 12. Single-Tone Spectrum @ fDATA = 160 MSPS with fOUT = fDATA/3
02858-015
100
02858-012
50
0
Figure 15. Third-Order IMD Products vs. fOUT @ fDATA = 65 MSPS
90
90
–6dBFS
0dBFS
–6dBFS
85
85
80
80
75
75
IMD (dBc)
70
–12dBFS
70
–3dBFS
65
65
60
60
55
55
50
0
10
20
30
40
50
FREQUENCY (MHz)
02858-013
50
0
5
10
15
20
25
30
FREQUENCY (MHz)
Figure 13. In-Band SFDR vs. fOUT @ fDATA = 160 MSPS
02858-016
SFDR (dBc)
0dBFS
Figure 16. Third-Order IMD Products vs. fOUT @ fDATA = 78 MSPS
90
90
85
85
80
80
–6dBFS
IMD (dBc)
0dBFS
70
65
75
–3dBFS
70
0dBFS
65
60
60
–12dBFS
55
55
50
10
20
30
40
50
FREQUENCY (MHz)
Figure 14. Out-of-Band SFDR vs. fOUT @ fDATA = 160 MSPS
0
10
20
30
40
50
60
FREQUENCY (MHz)
Figure 17. Third-Order IMD Products vs. fOUT @ fDATA = 160 MSPS
Rev. E | Page 13 of 56
02858-017
50
0
02858-014
SFDR (dBc)
–6dBFS
75
AD9775
90
90
–3dBFS
85
85
80
80
4×
70
2×
1×
65
55
55
50
3.1
20
30
40
50
60
FREQUENCY (MHz)
02858-018
50
3.2
3.3
3.4
3.5
AVDD (V)
Figure 18. Third-Order IMD Products vs. fOUT and Interpolation Rate,
1× fDATA = 160 MSPS, 2× fDATA = 160 MSPS, 4× fDATA = 80 MSPS,
8× fDATA = 50 MSPS
Figure 21. Third-Order IMD Products vs. AVDD @ fOUT = 10 MHz,
fDAC = 320 MSPS, fDATA = 160 MSPS
90
90
4×
8×
85
85
80
80
1×
70
75
PLL OFF
70
65
65
60
60
55
55
50
–15
–10
–5
0
AOUT (dBFS)
PLL ON
50
0
50
100
150
INPUT DATA RATE (MSPS)
Figure 19. Third-Order IMD Products vs. AOUT and Interpolation Rate,
fDATA = 50 MSPS for All Cases, 1× fDAC = 50 MSPS, 2× fDAC = 100 MSPS,
4× fDAC = 200 MSPS, 8× fDAC = 400 MSPS
02858-022
2×
SNR (dB)
75
02858-019
IMD (dBc)
65
60
10
–6dBFS
70
60
0
0dBFS
75
02858-021
75
SFDR (dBc)
IMD (dBc)
8×
Figure 22. SNR vs. Data Rate for fOUT = 5 MHz
90
90
78MSPS
85
80
80
75
75
70
–12dBFS
–6dBFS
65
fDATA = 65MSPS
65
60
60
55
55
50
3.1
3.2
3.3
AVDD (V)
3.4
3.5
Figure 20. SFDR vs. AVDD @ fOUT = 10 MHz, fDAC = 320 MSPS, fDATA = 160 MSPS
Rev. E | Page 14 of 56
160MSPS
70
50
–50
0
50
TEMPERATURE (°C)
Figure 23. SFDR vs. Temperature @ fOUT = fDATA/11
100
02858-023
SFDR (dBc)
85
02858-020
SFDR (dBc)
0dBFS
0
0
–10
–10
–20
–20
–30
–30
AMPLITUDE (dBm)
–40
–50
–60
–70
–40
–50
–60
–70
–80
–80
–90
–100
0
50
100
150
FREQUENCY (MHz)
02858-024
–90
–100
0
5
10
15
20
25
30
35
40
45
50
FREQUENCY (MHz)
02858-027
AMPLITUDE (dBm)
AD9775
Figure 27. Two-Tone IMD Performance, fDATA = 150 MSPS, Interpolation = 4×
Figure 24. Single-Tone Spurious Performance, fOUT = 10 MHz,
fDATA = 150 MSPS, No Interpolation
0
0
–10
–20
–30
AMPLITUDE (dBm)
AMPLITUDE (dBm)
–20
–40
–60
–40
–50
–60
–70
–80
–80
–90
10
20
30
40
50
FREQUENCY (MHz)
0
02858-025
0
–10
–20
–20
–30
–30
AMPLITUDE (dBm)
–10
200
250
300
–40
–50
–60
–70
–70
–80
–80
–90
–90
0
50
100
150
200
250
300
FREQUENCY (MHz)
0
5
10
15
20
FREQUENCY (MHz)
Figure 29. Two-Tone IMD Performance, fOUT = 10 MHz,
fDATA = 50 MSPS, Interpolation = 8×
Figure 26. Single-Tone Spurious Performance, fOUT = 10 MHz,
fDATA = 150 MSPS, Interpolation = 2×
Rev. E | Page 15 of 56
25
02858-029
–100
–100
02858-026
AMPLITUDE (dBm)
0
–60
150
Figure 28. Single-Tone Spurious Performance, fOUT = 10 MHz,
fDATA = 80 MSPS, Interpolation = 4×
0
–50
100
FREQUENCY (MHz)
Figure 25. Two-Tone IMD Performance, fDATA = 150 MSPS, No Interpolation
–40
50
02858-028
–100
–100
AD9775
0
0
–10
–20
AMPLITUDE (dBm)
–30
–40
–50
–60
–70
–80
–40
–60
–80
–100
–90
0
100
200
300
400
FREQUENCY (MHz)
0
20
40
60
80
FREQUENCY (MHz)
Figure 31. Eight-Tone IMD Performance, fDATA = 160 MSPS,
Interpolation = 8×
Figure 30. Single-Tone Spurious Performance, fOUT = 10 MHz,
fDATA = 50 MSPS, Interpolation = 8×
Rev. E | Page 16 of 56
02858-031
–120
–100
02858-030
AMPLITUDE (dBm)
–20
AD9775
TERMINOLOGY
Adjacent Channel Power Ratio (ACPR)
A ratio in dBc between the measured power within a channel
relative to its adjacent channel.
Monotonicity
A DAC is monotonic if the output either increases or remains
constant as the digital input increases.
Complex Image Rejection
In a traditional two-part upconversion, two images are created
around the second IF frequency. These images are redundant
and have the effect of wasting transmitter power and system
bandwidth. By placing the real part of a second complex
modulator in series with the first complex modulator, either the
upper or lower frequency image near the second IF can be
rejected.
Offset Error
The deviation of the output current from the ideal of 0 is called
offset error. For IOUTA, 0 mA output is expected when the inputs
are all 0. For IOUTB, 0 mA output is expected when all inputs are
set to 1.
Complex Modulation
The process of passing the real and imaginary components of a
signal through a complex modulator (transfer function = ejωt =
cosωt + jsinωt) and realizing real and imaginary components
on the modulator output.
Differential Nonlinearity (DNL)
DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input
code.
Gain Error
The difference between the actual and ideal output span. The
actual span is determined by the output when all inputs are set
to 1 minus the output when all inputs are set to 0.
Output Compliance Range
The range of allowable voltage at the output of a current output
DAC. Operation beyond the maximum compliance limits may
cause either output stage saturation or breakdown, resulting in
nonlinear performance.
Pass Band
Frequency band in which any input applied therein passes
unattenuated to the DAC output.
Power Supply Rejection
The maximum change in the full-scale output as the supplies
are varied from minimum to maximum specified voltages.
Settling Time
The time required for the output to reach and remain within a
specified error band about its final value, measured from the
start of the output transition.
Glitch Impulse
Asymmetrical switching times in a DAC give rise to undesired
output transients that are quantified by a glitch impulse. It is
specified as the net area of the glitch in pV-s.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the measured output signal
to the rms sum of all other spectral components below the
Nyquist frequency, excluding the first six harmonics and dc.
The value for SNR is expressed in decibels.
Group Delay
Number of input clocks between an impulse applied at the
device input and the peak DAC output current. A half-band FIR
filter has constant group delay over its entire frequency range.
Spurious-Free Dynamic Range
The difference, in dB, between the rms amplitude of the output
signal and the peak spurious signal over the specified
bandwidth.
Impulse Response
Response of the device to an impulse applied to the input.
Stop-Band Rejection
The amount of attenuation of a frequency outside the pass band
applied to the DAC, relative to a full-scale signal applied at the
DAC input within the pass band.
Interpolation Filter
If the digital inputs to the DAC are sampled at a multiple rate of
fDATA (interpolation rate), a digital filter can be constructed with
a sharp transition band near fDATA/2. Images that would
typically appear around fDAC (output data rate) can be greatly
suppressed.
Linearity Error
(Also called integral nonlinearity or INL.) It is defined as the
maximum deviation of the actual analog output from the ideal
output, determined by a straight line drawn from zero scale to
full scale.
Temperature Drift
Temperature drift is specified as the maximum change from the
ambient (25°C) value to the value at either TMIN or TMAX. For
offset and gain drift, the drift is reported in ppm of full-scale
range (FSR) per °C. For reference drift, the drift is reported in
ppm per °C.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first six harmonic
components to the rms value of the measured fundamental. It is
expressed as a percentage or in decibels (dB).
Rev. E | Page 17 of 56
AD9775
MODE CONTROL (VIA SPI PORT)
Table 10. Mode Control via SPI Port1
Address
0x00
Bit 7
SDIO
Bidirectional
0 = Input
1 = I/O
Bit 6
LSB, MSB
First, 0 = MSB
1 = LSB
Bit 5
Software
Reset on
Logic 1
Bit 4
Sleep Mode
Logic 1
Shuts Down
the DAC
Output
Currents
Bit 3
Power-Down
Mode Logic 1
Shuts Down All
Digital and
Analog
Functions
0x 01
Filter
Interpolation
Rate (1×, 2×,
4×, 8×)
Filter
Interpolation
Rate (1×, 2×, 4×,
8×)
Modulation
Mode
(None, fS/2,
fS/4, fS/8)
Modulation
Mode
(None, fS/2,
fS/4, fS/8)
0 = No Zero
Stuffing on
Interpolation
Filters, Logic 1
Enables Zero
Stuffing.
0x 02
0 = Signed
Input Data
1 = Unsigned
0 = Two-Port
Mode
1 = One-Port
Mode
DATACLK
Driver
Strength
DATACLK
Invert
0 = No Invert
1 = Invert
0x 03
Data Rate
Clock Output2
0x 04
0 = PLL OFF2
1 = PLL ON
0x 05
0x 06
0x 07
0x 08
0x 0C
2
Bit 0
0 = e−jωt
1 = e+jωt
DATACLK/
PLL_LOCK2
Select
0 = PLLLOCK
1 = DATACLK
ONEPORTCLK
Invert
0 = No Invert
1 = Invert
IQSEL Invert
0 = No Invert
1 = Invert
Q First
0 = I First
1 = Q First
PLL Divide
(Prescaler)
Ratio
PLL Charge
Pump
Control
PLL Divide
(Prescaler)
Ratio
PLL Charge
Pump Control
IDAC Fine Gain Adjustment
IDAC Offset
Adjustment
Bit 9
IDAC IOFFSET
Direction
0 = IOFFSET
on IOUTA
1 = IOFFSET
on IOUTB
IDAC Offset
Adjustment
Bit 8
IDAC Offset
Adjustment
Bit 7
IDAC Offset
Adjustment
Bit 6
IDAC Offset
Adjustment
Bit 5
IDAC Coarse Gain Adjustment
IDAC Offset
IDAC Offset
Adjustment
Adjustment
Bit 4
Bit 3
IDAC Offset
Adjustment
Bit 1
IDAC Offset
Adjustment
Bit 2
IDAC Offset
Adjustment
Bit 0
QDAC Fine Gain Adjustment
QDAC Coarse Gain Adjustment
QDAC Offset
Adjustment
Bit 9
QDAC IOFFSET
Direction
0 = IOFFSET
on IOUTA
1 = IOFFSET
on IOUTB
QDAC Offset
Adjustment
Bit 8
QDAC Offset
Adjustment
Bit 7
QDAC Offset
Adjustment
Bit 6
QDAC Offset
Adjustment
Bit 5
0x 0D
1
Bit 1
PLL_LOCK
Indicator
PLL Charge
Pump
Control
0 = Automatic
Charge Pump
Control, 1 =
Programmable
0x 09
0x 0A
0x 0B
Bit 2
1R/2R Mode
DAC Output
Current Set
by One or
Two External
Resistors
0 = 2R,
1 = 1R
1 = Real
Mix Mode
0 = Complex
Mix Mode
QDAC Offset
Adjustment
Bit 4
QDAC Offset
Adjustment
Bit 3
QDAC Offset
Adjustment
Bit 1
Version Register
Default values are shown in bold.
See the Two-Port Data Input Mode section.
Rev. E | Page 18 of 56
QDAC Offset
Adjustment
Bit 2
QDAC Offset
Adjustment
Bit 0
AD9775
REGISTER DESCRIPTIONS
ADDRESS 0x00
Bit 3: Logic 1 enables zero-stuffing mode for interpolation filters.
Bit 7: Logic 0 (default) causes the SPI_SDIO pin to act as an
input during the data transfer (Phase 2) of the communications
cycle. When set to 1, SPI_SDIO can act as an input or output,
depending on Bit 7 of the instruction byte.
Bit 2: Default (1) enables the real mix mode. The I and Q data
channels are individually modulated by fS/2, fS/4, or fS/8 after
the interpolation filters. However, no complex modulation is
done. In the complex mix mode (Logic 0), the digital
modulators on the I and Q data channels are coupled to create a
digital complex modulator. When the AD9775 is applied in
conjunction with an external quadrature modulator, rejection
can be achieved of either the higher or lower frequency image
around the second IF frequency (that is, the LO of the analog
quadrature modulator external to the AD9775) according to the
bit value of Register 0x01, Bit 1.
Bit 6: Logic 0 (default) determines the direction (LSB/MSB
first) of the communications and data transfer communications
cycles. Refer to the MSB/LSB Transfers section for more details.
Bit 5: Writing 1 to this bit resets the registers to their default
values and restarts the chip. The RESET bit always reads back 0.
Register Address 0x00 bits are not cleared by this software reset.
However, a high level at the RESET pin forces all registers,
including those in Address 0x00, to their default state.
Bit 4: Sleep Mode. A Logic 1 to this bit shuts down the DAC
output currents.
Bit 3: Power Down. Logic 1 shuts down all analog and digital
functions except for the SPI port.
Bit 2: 1R/2R Mode. The default (0) places the AD9775 in tworesistor mode. In this mode, the IREF currents for the I and Q
DAC references are set separately by the RSET resistors on FSADJ1
and FSADJ2 (Pin 60 and Pin 59). In 2R mode, assuming the coarse
gain setting is full scale and the fine gain setting is zero,
IFULLSCALE1 = 32 × VREF/FSADJ1 and IFULLSCALE2 = 32 × VREF/FSADJ2.
With this bit set to 1, the reference currents for both I and Q
DACs are controlled by a single resistor on Pin 60. IFULLSCALE in
one-resistor mode for both of the I and Q DACs is half of what
it would be in 2R mode, assuming all other conditions (RSET,
register settings) remain unchanged. The full-scale current of
each DAC can still be set to 20 mA by choosing a resistor of half
the value of the RSET value used in 2R mode.
Bit 1: PLL_LOCK Indicator. When the PLL is enabled, reading
this bit gives the status of the PLL. A Logic 1 indicates the PLL
is locked. A Logic 0 indicates an unlocked state.
Bit 1: Logic 0 (default) causes the complex modulation to be of
the form e− jωt, resulting in the rejection of the higher frequency
image when the AD9775 is used with an external quadrature
modulator. A Logic 1 causes the modulation to be of the form
e+jωt, which causes rejection of the lower frequency image.
Bit 0: In two-port mode, a Logic 0 (default) causes Pin 8 to act
as a lock indicator for the internal PLL. A Logic 1 in this register
causes Pin 8 to act as a DATACLK. For more information, see
the Two-Port Data Input Mode section.
ADDRESS 0x02
Bit 7: Logic 0 (default) causes data to be accepted on the inputs
as twos complement binary. Logic 1 causes data to be accepted
as straight binary.
Bit 6: Logic 0 (default) places the AD9775 in two-port mode.
I and Q data enters the AD9775 via Ports 1 and 2, respectively.
A Logic 1 places the AD9775 in one-port mode in which
interleaved I and Q data is applied to Port 1. See Table 9 for
detailed information on how to use the DATACLK/PLL_LOCK,
IQSEL, and ONEPORTCLK modes.
Bit 7 and Bit 6: This is the filter interpolation rate according to
the following table.
Bit 5: DATACLK Driver Strength. With the internal PLL
disabled and this bit set to Logic 0, it is recommended that
DATACLK be buffered. When this bit is set to Logic 1,
DATACLK acts as a stronger driver capable of driving small
capacitive loads.
Table 11.
Bit 4: Logic 0 (default). A value of 1 inverts DATACLK at Pin 8.
ADDRESS 0x01
00
01
10
11
Bit 2: Logic 0 (default). A value of 1 inverts ONEPORTCLK at
Pin 32.
1×
2×
4×
8×
Bit 5 and Bit 4: This is the modulation mode according to the
following table.
Table 12.
00
01
10
11
Bit 1: Logic 0 (default) causes IQSEL = 0 to direct input data to
the I channel, while IQSEL = 1 directs input data to the Q
channel.
Bit 0: Logic 0 (default) defines IQ pairing as IQ, IQ… while
programming a Logic 1 causes the pair ordering to be QI, QI…
None
fS/2
fS/4
fS/8
Rev. E | Page 19 of 56
AD9775
ADDRESS 0x03
ADDRESS 0x05, ADDRESS 0x09
Bit 7: Allows the data rate clock (divided down from the DAC
clock) to be output at either the DATACLK/PLL_LOCK pin
(Pin 8) or at the SPI_SDO pin (Pin 53). The default of 0 in this
register enables the data rate clock at DATACLK/ PLL_LOCK,
while a 1 in this register causes the data rate clock to be output
at SPI_SDO. For more information, see the Two-Port Data
Input Mode section.
Bit 7 to Bit 0: These bits represent an 8-bit binary number
(Bit 7 MSB) that defines the fine gain adjustment of the I (0x05)
and Q (0x09) DAC, according to Equation 1.
Bit 1 and Bit 0: Setting this divide ratio to a higher number
allows the VCO in the PLL to run at a high rate (for best
performance) while the DAC input and output clocks run
substantially slower. The divider ratio is set according to the
following table.
Bit 3 to Bit 0: These bits represent a 4-bit binary number (Bit 3
MSB) that defines the coarse gain adjustment of the I (0x06)
and Q (0x0A) DACs, according to Equation 1.
ADDRESS 0x07, ADDRESS 0x0B
Bit 7 to Bit 0: These bits are used in conjunction with Address
0x08, 0x0C, Bit 1 and Bit 0.
ADDRESS 0x08, ADDRESS 0x0C
Table 13.
00
01
10
11
ADDRESS 0x06, ADDRESS 0x0A
Bit 1 and Bit 0: The 10 bits from these two address pairs
(0x07, 0x08 and 0x0B, 0x0C) represent a 10-bit binary number
that defines the offset adjustment of the I and Q DACs,
according to Equation 1 (0x07, 0x0B—Bit 7 MSB/0x08, 0x0C—
Bit 0 LSB).
÷1
÷2
÷4
÷8
ADDRESS 0x04
ADDRESS 0x08, ADDRESS 0x0C
Bit 7: Logic 0 (default) disables the internal PLL. Logic 1
enables the PLL.
Bit 7: This bit determines the direction of the offset of the
I (0x08) and Q (0x0C) DACs. A Logic 0 applies a positive offset
current to IOUTA, while a Logic 1 applies a positive offset current
to IOUTB. The magnitude of the offset current is defined by the
bits in Addresses 0x07, 0x0B, 0x08, and 0x0C, according to
Equation 1.
Bit 6: Logic 0 (default) sets the charge pump control to
automatic. In this mode, the charge pump bias current is
controlled by the divider ratio defined in Address 0x03, Bits 1
and 0. Logic 1 allows the user to manually define the charge
pump bias current using Address 0x04, Bits 2, 1, and 0.
Adjusting the charge pump bias current allows the user to
optimize the noise/settling performance of the PLL.
Bit 2 to Bit 0: With the charge pump control set to manual,
these bits define the charge pump bias current according to the
following table.
Equation 1 shows IOUTA and IOUTB as a function of fine gain,
coarse gain, and offset adjustment when using the 2R mode. In
1R mode, the current IREF is created by a single FSADJ resistor
(Pin 60). This current is divided equally into each channel so
that a scaling factor of one-half must be added to these
equations for full-scale currents for both DACs and the offset.
Table 14.
000
001
010
011
111
50 μA
100 μA
200 μA
400 μA
800 μA
⎡⎛ 6 × I REF
I OUTA = ⎢⎜⎜
8
⎣⎢⎝
⎞⎛ COARSE + 1 ⎞ ⎛ 3 × I REF
⎟⎟ − ⎜⎜
⎟⎟⎜⎜
16
⎠⎝
⎠ ⎝ 32
⎡⎛ 6 × I REF
I OUTB = ⎢⎜⎜
8
⎣⎢⎝
⎞⎛ COARSE + 1 ⎞ ⎛ 3 × I REF
⎟⎟ − ⎜⎜
⎟⎟⎜⎜
16
⎠⎝
⎠ ⎝ 32
⎞⎛ FINE ⎞⎤ ⎡⎛ 1024 ⎞⎛ DATA ⎞ ⎤
⎟⎟⎜
⎟⎥ × ⎢⎜
⎟⎜ 14 ⎟ ⎥ (A)
⎠⎦
⎠⎝ 256 ⎠⎦⎥ ⎣⎝ 24 ⎠⎝ 2
14
⎞⎛ FINE ⎞ ⎤ ⎡⎛ 1024 ⎞⎛⎜ 2 − DATA − 1 ⎞⎟⎤
⎥ (A)
⎟⎟⎜
⎟ ⎥ × ⎢⎜
⎟
⎟⎥
2 14
⎠⎝ 256 ⎠ ⎦⎥ ⎢⎣⎝ 24 ⎠⎜⎝
⎠⎦
⎛ OFFSET ⎞
I OFFSET = 4 × I REF ⎜
⎟ (A)
⎝ 1024 ⎠
Rev. E | Page 20 of 56
(1)
AD9775
FUNCTIONAL DESCRIPTION
The AD9775 dual interpolating DAC consists of two data
channels that can be operated independently or coupled to form
a complex modulator in an image reject transmit architecture.
Each channel includes three FIR filters, making the AD9775
capable of 2×, 4×, or 8× interpolation. High speed input and
output data rates can be achieved within the following
limitations.
SDO (PIN 53)
SPI_CLK (PIN 55)
CSB (PIN 56)
Figure 32. SPI Port Interface
Table 15.
Interpolation Rate
(MSPS)
1×
2×
4×
8×
AD9775 SPI PORT
INTERFACE
02858-032
SDIO (PIN 54)
Input Data Rate
(MSPS)
160
160
100
50
DAC Sample Rate
(MSPS)
160
320
400
400
Both data channels contain a digital modulator capable of
mixing the data stream with an LO of fDAC/2, fDAC/4, or fDAC/8,
where fDAC is the output data rate of the DAC. A zero-stuffing
feature is also included and can be used to improve pass-band
flatness for signals being attenuated by the sin(x)/x
characteristic of the DAC output. The speed of the AD9775,
combined with the digital modulation capability, enables direct
IF conversion architectures at 70 MHz and higher.
The digital modulators on the AD9775 can be coupled to form
a complex modulator. By using this feature with an external
analog quadrature modulator, such as the Analog Devices
AD8345, an image rejection architecture can be enabled. To
optimize the image rejection capability, as well as LO feedthrough in this architecture, the AD9775 offers programmable
(via the SPI port) gain and offset adjust for each DAC.
Also included on the AD9775 are a phase-locked loop (PLL)
clock multiplier and a 1.20 V band gap voltage reference. With
the PLL enabled, a clock applied to the CLK+/CLK− inputs is
frequency multiplied internally and generates all necessary
internal synchronization clocks. Each 14-bit DAC provides two
complementary current outputs whose full-scale currents can
be determined either from a single external resistor or
independently from two separate resistors (see the 1R/2R Mode
section). The AD9775 features a low jitter, differential clock
input that provides excellent noise rejection while accepting a
sine or square wave input. Separate voltage supply inputs are
provided for each functional block to ensure optimum noise
and distortion performance.
Sleep and power-down modes can be used to turn off the DAC
output current (sleep) or the entire digital and analog sections
(power-down) of the chip. An SPI-compliant serial port is used
to program the many features of the AD9775. Note that in
power-down mode, the SPI port is the only section of the chip
still active.
SERIAL INTERFACE FOR REGISTER CONTROL
The AD9775 serial port is a flexible, synchronous serial
communications port that allows easy interface to many
industry-standard microcontrollers and microprocessors.
The serial I/O is compatible with most synchronous transfer
formats, including both the Motorola SPI and Intel SSR
protocols. The interface allows read/write access to all registers
that configure the AD9775. Single- or multiple-byte transfers
are supported, as well as MSB-first or LSB-first transfer formats.
The AD9775 serial interface port can be configured as a single
pin I/O (SDIO) or two unidirectional pins for I/O (SDIO/SDO).
GENERAL OPERATION OF THE SERIAL INTERFACE
There are two phases to a communication cycle with the
AD9775. Phase 1 is the instruction cycle, which is the writing of
an instruction byte into the AD9775 coincident with the first
eight SCLK rising edges. The instruction byte provides the
AD9775 serial port controller with information regarding the
data transfer cycle, which is Phase 2 of the communication
cycle. The Phase 1 instruction byte defines whether the
upcoming data transfer is read or write, the number of bytes in
the data transfer, and the starting register address for the first
byte of the data transfer. The first eight SCLK rising edges of
each communication cycle are used to write the instruction byte
into the AD9775.
A Logic 1 on the SPI_CSB pin, followed by a logic low, resets
the SPI port timing to the initial state of the instruction cycle.
This is true regardless of the present state of the internal
registers or the other signal levels present at the inputs to the
SPI port. If the SPI port is in the middle of an instruction cycle
or a data transfer cycle, none of the present data is written.
The remaining SCLK edges are for Phase 2 of the
communication cycle. Phase 2 is the actual data transfer
between the AD9775 and the system controller. Phase 2 of the
communication cycle is a transfer of one to four data bytes as
determined by the instruction byte. Typically, using one
multibyte transfer is the preferred method. However, single byte
data transfers are useful to reduce CPU overhead when register
access requires one byte only. Registers change immediately
upon writing to the last bit of each transfer byte.
Rev. E | Page 21 of 56
AD9775
SPI_SDO (Pin 53)—Serial Data Out
Data is read from this pin for protocols that use separate lines
for transmitting and receiving data. In the case where the
AD9775 operates in a single bidirectional I/O mode, this pin
does not output data and is set to a high impedance state.
INSTRUCTION BYTE
The instruction byte contains the information shown next
Table 16.
N1
0
0
1
1
N0
0
1
0
1
Description
Transfer 1 Byte
Transfer 2 Bytes
Transfer 3 Bytes
Transfer 4 Bytes
MSB/LSB TRANSFERS
The AD9775 serial port can support both most significant bit
(MSB) first or least significant bit (LSB) first data formats. This
functionality is controlled by the LSB-first bit in Register 0. The
default is MSB first.
R/W
Bit 7 of the instruction byte determines whether a read or a
write data transfer occurs after the instruction byte write.
Logic 1 indicates read operation. Logic 0 indicates a write
operation.
When this bit is set active high, the AD9775 serial port is in
LSB-first format. In LSB-first mode, the instruction byte and
data bytes must be written from LSB to MSB. In LSB-first mode,
the serial port internal byte address generator increments for
each byte of the multibyte communication cycle.
N1, N0
Bit 6 and Bit 5 of the instruction byte determine the number of
bytes to be transferred during the data transfer cycle. The bit
decodes are shown next.
Table 17.
MSB
I7
I6
I5
I4
I3
I2
I1
LSB
I0
R/W
N1
N0
A4
A3
A2
A1
A0
A4, A3, A2, A1, A0
Bit 4 to Bit 0 of the instruction byte determine which register is
accessed during the data transfer portion of the communications
cycle. For multibyte transfers, this address is the starting byte
address. The remaining register addresses are generated by
the AD9775.
SERIAL INTERFACE PORT PIN DESCRIPTIONS
SPI_CLK (Pin 55)—Serial Clock
The serial clock pin is used to synchronize data to and from the
AD9775 and to run the internal state machines. SPI_CLK
maximum frequency is 15 MHz. All data input to the AD9775
is registered on the rising edge of SPI_CLK. All data is driven
out of the AD9775 on the falling edge of SPI_CLK.
SPI_CSB (Pin 56)—Chip Select
Active low input starts and gates a communication cycle. It
allows more than one device to be used on the same serial
communications lines. The SDO and SDIO pins go to a high
impedance state when this input is high. Chip select should stay
low during the entire communication cycle.
SPI_SDIO (Pin 54)—Serial Data I/O
Data is always written into the AD9775 on this pin. However,
this pin can be used as a bidirectional data line. The
configuration of this pin is controlled by Bit 7 of Register
Address 0x00. The default is Logic 0, which configures the
SDIO pin as unidirectional.
When this bit is set default low, the AD9775 serial port is in
MSB-first format. In MSB-first mode, the instruction byte and
data bytes must be written from MSB to LSB. In MSB-first
mode, the serial port internal byte address generator
decrements for each byte of the multibyte communication cycle.
When incrementing from 0x1F, the address generator changes
to 0x00. When decrementing from 0x00, the address generator
changes to 0x1F.
NOTES ON SERIAL PORT OPERATION
The AD9775 serial port configuration bits reside in Bit 6 and
Bit 7 of Register Address 0x00. It is important to note that the
configuration changes immediately upon writing to the last bit
of the register. For multibyte transfers, writing to this register
may occur during the middle of the communication cycle. Care
must be taken to compensate for this new configuration for the
remaining bytes of the current communication cycle.
The same considerations apply to setting the reset bit in
Register Address 0x00. All other registers are set to their
default values, but the software reset does not affect the bits in
Register Address 0x00.
It is recommended to use only single-byte transfers when
changing serial port configurations or initiating a software reset.
A write to Bit 1, Bit 2, and Bit 3 of Address 0x00 with the same
logic levels as for Bit 7, Bit 6, and Bit 5 (bit pattern is XY1001YX
binary) allows the user to reprogram a lost serial port
configuration and to reset the registers to their default values. A
second write to Address 0x00 with reset bit low and serial port
configuration as specified above (XY) reprograms the OSC IN
multiplier setting. A changed fSYSCLK frequency is stable after a
maximum of 200 fMCLK cycles (equals wake-up time).
Rev. E | Page 22 of 56
AD9775
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
CS
SDIO
I6(N)
R/W
I5(N)
I4
I3
I2
I1
I0
SDO
D7N
D6N
D20
D10
D00
D7N
D6N
D20
D10
D00
02858-033
SCLK
Figure 33. Serial Register Interface Timing MSB First
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
CS
I0
I1
I2
I3
I4
I5(N)
I6(N)
R/W
SDO
D00
D10
D20
D6N
D7N
D00
D10
D20
D6N
D7N
Figure 34. Serial Register Interface Timing LSB First
tSCLK
tDS
CS
tPWH
tPWL
SCLK
SDIO
tDH
INSTRUCTION BIT 7
T6
INSTRUCTION BIT
02858-035
tDS
Figure 35. Timing Diagram for Register Write to AD9775
CS
SCLK
tDV
SDIO
DATA BIT N
DATA BIT N–1
SDO
Figure 36. Timing Diagram for Register Read from AD9775
Rev. E | Page 23 of 56
02858-036
SDIO
02858-034
SCLK
AD9775
25
DAC OPERATION
COARSE REFERENCE CURRENT (mA)
The dual, 14-bit DAC output of the AD9775, along with the
reference circuitry, gain, and offset registers, is shown in Figure 37.
Note that an external reference can be used by simply overdriving
the internal reference with the external reference. Referring to the
transfer functions in Equation 1, a reference current is set by the
internal 1.2 V reference, the external RSET resistor, and the values
in the coarse gain register. The fine gain DAC subtracts a small
amount from this and the result is input to IDAC and QDAC,
where it is scaled by an amount equal to 1024/24. Figure 38 and
Figure 39 show the scaling effect of the coarse and fine adjust
DACs. IDAC and QDAC are PMOS current source arrays,
segmented in a 5-4-5 configuration. The 5 MSBs control an array
of 31 current sources. The next four bits consist of 15 current
sources whose values are all equal to 1/16 of an MSB current
source. The 5 LSBs are binary weighted fractions of the middle
bits’ current sources. All current sources are switched to either
IOUTA or IOUTB, depending on the input code.
20
2R MODE
15
10
1R MODE
5
0
5
10
20
15
02858-039
0
COARSE GAIN REGISTER CODE
(ASSUMING RSET1, RSET2 = 1.9kΩ)
Figure 38. Coarse Gain Effect on IFULLSCALE
FINE REFERENCE CURRENT (mA)
0
The fine adjustment of the gain of each channel allows for
improved balance of QAM modulated signals, resulting in
improved modulation accuracy and image rejection.
In the section Interfacing the AD9775 with the AD8345
Quadrature Modulator, the performance data shows to what
degree image rejection can be improved when the AD9775 is
used with an AD8345 quadrature modulator from Analog
Devices, Inc.
AVDD
–0.5
1R MODE
–1.0
2R MODE
–1.5
–2.0
–2.5
–3.0
200
400
600
800
FINE GAIN REGISTER CODE
(ASSUMING RSET1, RSET2 = 1.9kΩ)
REFIO
Figure 39. Fine Gain Effect on IFULLSCALE
7kΩ
02858-038
0.7V
Figure 37. Equivalent Internal Reference Circuit
OFFSET
CONTROL OFFSET
DAC
REGISTERS
FINE
GAIN
DAC
GAIN
CONTROL
REGISTERS
FINE
GAIN
DAC
1.2VREF
IDAC
IOUTA1
IOUTB1
REFIO
COARSE
GAIN
DAC
0.1μF
COARSE
GAIN
DAC
QDAC
IOUTA2
IOUTB2
FSADJ2
RSET1
RSET2
OFFSET
OFFSET
CONTROL
DAC
GAIN
REGISTERS
CONTROL
REGISTERS
Figure 40. DAC Outputs, Reference Current Scaling, and Gain/Offset Adjust
Rev. E | Page 24 of 56
02858-037
FSADJ1
1000
02858-040
0
84μA
AD9775
–10
OFFSET REGISTER 1 ADJUSTED
–20
–30
–40
–50
–60
OFFSET REGISTER 2
ADJUSTED, WITH OFFSET
REGISTER 1 SET
TO OPTIMIZED VALUE
–70
–80
–1024
–768
–512
–256
256
512
768
CLOCK INPUT CONFIGURATIONS
The clock inputs to the AD9775 can be driven differentially
or single-ended. The internal clock circuitry has supply and
ground (CLKVDD, CLKGND) separate from the other supplies
on the chip to minimize jitter from internal noise sources.
Figure 43 shows the AD9775 driven from a single-ended
clock source. The CLK+/CLK− pins form a differential input
(CLKIN) so that the statically terminated input must be dcbiased to the midswing voltage level of the clock driven input.
AD9775
5
4
RSERIES
CLK+
CLKVDD
CLK–
VTHRESHOLD
0.1μF
CLKGND
02858-043
In 2R mode, the reference current for each channel is set
independently by the FSADJ resistor on that channel. The
AD9775 can be programmed to derive its reference current
from a single resistor on Pin 60 by placing the part into 1R
mode. The transfer functions in Equation 1 are valid for 2R
mode. In 1R mode, the current developed in the single FSADJ
resistor is split equally between the two channels. The result is
that in 1R mode, a scale factor of 1/2 must be applied to the
formulas in Equation 1. The full-scale DAC current in 1R mode
can still be set to as high as 20 mA by using the internal 1.2 V
reference and a 950 Ω resistor instead of the 1.9 kΩ resistor
typically used in the 2R mode.
Figure 43. Single-Ended Clock Driving Clock Inputs
A configuration for differentially driving the clock inputs is
given in Figure 44. DC-blocking capacitors can be used to
couple a clock driver output whose voltage swings exceed
CLKVDD or CLKGND. If the driver voltage swings are within
the supply range of the AD9775, the dc-blocking capacitors and
bias resistors are not necessary.
AD9775
3
0.1μF
1kΩ
CLK+
2R MODE
1kΩ
2
ECL/PECL
0.1μF
0.1μF
1R MODE
CLKVDD
1kΩ
CLK–
1
CLKGND
200
400
600
800
COARSE GAIN REGISTER CODE
(ASSUMING RSET1, RSET2 = 1.9kΩ)
1000
02858-041
0
Figure 41. DAC Output Offset Current
Rev. E | Page 25 of 56
02858-044
1kΩ
0
1024
Figure 42. Offset Adjust Control, Effect on LO Suppression
1R/2R MODE
OFFSET CURRENT (mA)
0
DAC1, DAC2 (OFFSET REGISTER CODES)
02858-042
In Figure 42, the negative scale represents an offset added to IOUTB,
while the positive scale represents an offset added to IOUTA of the
respective DAC. Offset Register 1 corresponds to IDAC, while
Offset Register 2 corresponds to QDAC. Figure 42 represents the
AD9775 synthesizing a complex signal that is then dc-coupled to
an AD8345 quadrature modulator with an LO of 800 MHz. The
dc coupling allows the input offset of the AD8345 to be calibrated
out as well. The LO suppression at the AD8345 output was optimized first by adjusting Offset Register 1 in the AD9775. When
an optimal point was found (roughly Code 54), this code was
held in Offset Register 1, and Offset Register 2 was adjusted. The
resulting LO suppression is 70 dBFS. These are typical numbers;
the specific code for optimization varies from part to part.
0
LO SUPPRESSION (dBFS)
The offset control defines a small current that can be added to
IOUTA or IOUTB (not both) on the IDAC and QDAC. The selection
of which IOUT this offset current is directed toward is programmable
via Register 0x08, Bit 7 (IDAC) and Register 0x0C, Bit 7 (QDAC).
Figure 41 shows the scale of the offset current that can be added
to one of the complementary outputs on the IDAC and QDAC.
Offset control can be used for suppression of LO leakage resulting
from modulation of dc signal components. If the AD9775 is dccoupled to an external modulator, this feature can be used to
cancel the output offset on the AD9775 as well as the input offset
on the modulator. Figure 42 shows a typical example of the effect
that the offset control has on LO suppression.
Figure 44. Differential Clock Driving Clock Inputs
AD9775
A transformer, such as the T1-1T from Mini-Circuits®, can also
be used to convert a single-ended clock to differential. This
method is used on the AD9775 evaluation board so that an external
sine wave with no dc offset can be used as a differential clock.
INTERPOLATION
FILTERS,
MODULATORS,
AND DACS
2
The charge pump, VCO, differential clock input buffer, phase
detector, prescaler, and clock distribution are all powered from
CLKVDD. PLL lock status is indicated by the logic signal at the
DATACLK_PLL_LOCK pin, as well as by the status of Bit 1,
Register 0x00. To ensure optimum phase noise performance
from the PLL clock multiplier and distribution, CLKVDD
should originate from a clean analog supply. Table 18 defines
the minimum input data rates vs. the interpolation and PLL
divider setting. If the input data rate drops below the defined
minimum under these conditions, VCO noise may increase
significantly. The VCO speed is a function of the input data
rate, the interpolation rate, and the VCO prescaler, according to
the following function:
PRESCALER
VCO
LPF
PLL DIVIDER
(PRESCALER)
CONTROL
INTERNAL SPI
CONTROL
REGISTERS
INTERPOLATION
RATE
CONTROL
MODULATION
RATE
CONTROL
SPI PORT
PLL
CONTROL
(PLL ON)
Figure 45. PLL and Clock Circuitry with PLL Enabled
CLK+
CLK–
PLL_LOCK
1 = LOCK
0 = NO LOCK
AD9775
INTERPOLATION
FILTERS,
MODULATORS,
AND DACS
2
The PLL clock multiplier and distribution circuitry produce the
necessary internal synchronized 1×, 2×, 4×, and 8× clocks for
the rising edge triggered latches, interpolation filters,
modulators, and DACs. This circuitry consists of a phase
detector, charge pump, voltage controlled oscillator (VCO),
prescaler, clock distribution, and SPI port control.
CHARGE
PUMP
8
CLOCK
DISTRIBUTION
CIRCUITRY
INPUT
DATA
LATCHES
PROGRAMMABLE PLL
VCO Speed (MHz) =
Input Data Rate (MHz) × Interpolation Rate × Prescaler
4
PHASE
DETECTOR
1
The quality of the clock and data input signals is important in
achieving optimum performance. The external clock driver
circuitry should provide the AD9775 with a low jitter clock
input that meets the minimum/maximum logic levels while
providing fast edges. Although fast clock edges help minimize
any jitter that manifests itself as phase noise on a reconstructed
waveform, the high gain bandwidth product of the AD9775
clock input comparator can tolerate differential sine wave
inputs as low as 0.5 V p-p with minimal degradation of the
output noise floor.
CLKIN can function either as an input data rate clock (PLL
enabled) or as a DAC data rate clock (PLL disabled) according
to the state of Address 0x02, Bit 7 in the SPI port register. The
internal operation of the AD9775 clock circuitry in these two
modes is illustrated in Figure 45 and Figure 46.
PLLVDD
AD9775
02858-045
Optimum performance of the AD9775 is achieved when the
driver is placed very close to the AD9775 clock inputs, thereby
negating any transmission line effects such as reflections due to
mismatch.
CLK–
4
PHASE
DETECTOR
CHARGE
PUMP
PRESCALER
VCO
8
1
CLOCK
DISTRIBUTION
CIRCUITRY
INPUT
DATA
LATCHES
INTERPOLATION
RATE
CONTROL
PLL DIVIDER
(PRESCALER)
CONTROL
INTERNAL SPI
CONTROL
REGISTERS
SPI PORT
MODULATION
RATE
CONTROL
PLL
CONTROL
(PLL ON)
02858-046
PECL/ECL drivers require varying termination networks,
the details of which are left out of Figure 43 and Figure 44 but
can be found in application notes such as AND8020/D from
ON Semiconductor®. These networks depend on the assumed
transmission line impedance and power supply voltage of the
clock driver.
CLK+
PLL_LOCK
1 = LOCK
0 = NO LOCK
Figure 46. PLL and Clock Circuitry with PLL Disabled
Table 18. PLL Optimization
Interpolation
Rate
1
1
1
1
2
2
2
2
4
4
4
4
8
8
8
8
Rev. E | Page 26 of 56
Divider
Setting
1
2
4
8
1
2
4
8
1
2
4
8
1
2
4
8
Minimum
fDATA
32
16
8
4
24
12
6
3
24
12
6
3
24
12
6
3
Maximum
fDATA
160
160
112
56
160
112
56
28
100
56
28
14
50
28
14
7
AD9775
In addition, if the zero-stuffing option is enabled, the VCO
doubles its speed again. Phase noise may be slightly higher with
the PLL enabled. Figure 47 illustrates typical phase noise performance of the AD9775 with 2× interpolation and various input
data rates. The signal synthesized for the phase noise measurement
was a single carrier at a frequency of fDATA/4. The repetitive
nature of this signal eliminates quantization noise and distortion
spurs as a factor in the measurement. Although the curves blend
together in Figure 47, the different conditions are given for clarity
in Table 19. Figure 47 also contains a table detailing the maximum
and minimum fDATA rates for each combination of interpolation
rate and PLL divider setting. These rates are guaranteed over
the entire supply and operating temperature range. Figure 48
shows typical performance of the PLL lock signal (Pin 8 or
Pin 53) when the PLL is in the process of locking.
Table 19. Required PLL Prescaler Ratio vs. fDATA
fDATA
125 MSPS
125 MSPS
100 MSPS
75 MSPS
50 MSPS
PLL
Disabled
Enabled
Enabled
Enabled
Enabled
Prescaler Ratio
It is important to note that the resistor/capacitor needed for the
PLL loop filter is internal on the AD9775. This suffices unless the
input data rate is below 10 MHz, in which case an external series
RC is required between the LPF pin and CLKVDD pins.
POWER DISSIPATION
The AD9775 has three voltage supplies: DVDD, AVDD, and
CLKVDD. Figure 49 through Figure 51 show the current
required from each of these supplies when each is set to the 3.3 V
nominal specified for the AD9775. Power dissipation (PD) can
easily be extracted by multiplying the given curves by 3.3. As
Figure 49 shows, IDVDD is very dependent on the input data rate,
the interpolation rate, and the activation of the internal digital
modulator. IDVDD, however, is relatively insensitive to the
modulation rate by itself. In Figure 50, IAVDD shows the same type
of sensitivity to the data, the interpolation rate, and the modulator function but to a much lesser degree (<10%). In Figure 51,
ICLKVDD varies over a wide range yet is responsible for only a small
percentage of the overall AD9775 supply current requirements.
Div 1
Div 2
Div 2
Div 4
400
8×, (MOD. ON)
4×, (MOD. ON)
300
IDVDD (mA)
0
–10
–20
–30
8×
250
4×
2×
200
150
–40
–50
100
–60
50
1×
–70
0
50
100
150
200
–90
fDATA (MHz)
–100
Figure 49. IDVDD vs. fDATA vs. Interpolation Rate, PLL Disabled
02858-049
0
–80
0
1
2
3
4
5
FREQUENCY OFFSET (MHz)
02858-047
–110
76.0
4×, (MOD. ON)
8×, (MOD. ON)
75.5
Figure 47. Phase Noise Performance
2×, (MOD. ON)
IAVDD (mA)
75.0
74.5
8×
74.0
4×
73.5
2×
73.0
1×
72.5
0
50
100
150
200
fDATA (MHz)
Figure 48. PLL_LOCK Output Signal (Pin 8) in the Process of Locking
(Typical Lock Time)
Rev. E | Page 27 of 56
Figure 50. IAVDD vs. fDATA vs. Interpolation Rate, PLL Disabled
02858-050
72.0
02858-048
PHASE NOISE (dBFS)
2×, (MOD. ON)
350
AD9775
35
PLL On (Register 4, Bit 7 = 1)
8×
Register 3, Bit 7 = 0, Register 1, Bit 0 = 0; PLL lock indicator out
of Pin 8.
Register 3, Bit 7 = 1, Register 1, Bit 0 = 0; PLL lock indicator out
of Pin 53.
Register 3, Bit 7 = 0, Register 1, Bit 0 = 1; DATACLK out of Pin 8.
Register 3, Bit 7 = 1, Register 1, Bit 0 = 1; DATACLK out of Pin 53.
30
4×
2×
ICLKVDD (mA)
25
20
15
1×
10
5
0
50
100
150
02858-051
0
200
fDATA (MHz)
Figure 51 ICLKVDD vs. fDATA vs. Interpolation Rate, PLL Disabled
SLEEP/POWER-DOWN MODES
(Control Register 0x00, Bit 3 and Bit 4)
The AD9775 provides two methods for programmable
reduction in power savings. The sleep mode, when activated,
turns off the DAC output currents but the rest of the chip
remains functioning. When coming out of sleep mode, the
AD9775 immediately returns to full operation. Power-down
mode, on the other hand, turns off all analog and digital
circuitry in the AD9775 except for the SPI port. When
returning from power-down mode, enough clock cycles must
be allowed to flush the digital filters of random data acquired
during the power-down cycle.
TWO-PORT DATA INPUT MODE
The digital data input ports can be configured as two independent ports or as a single (one-port mode) port. In two-port mode,
data at the two input ports is latched into the AD9775 on every
rising edge of the data rate clock (DATACLK). Also, in two-port
mode, the AD9775 can be programmed to generate an externally
available DATACLK for the purpose of data synchronization.
This data rate clock can be programmed to be available at either
Pin 8 (DATACLK/PLL_LOCK) or Pin 53 (SPI_SDO). Because
Pin 8 can also function as a PLL lock indicator when the PLL is
enabled, there are several options for configuring Pin 8 and
Pin 53. The following sections describe the options.
PLL Off (Register 4, Bit 7 = 0)
Register 3, Bit 7 = 0; DATACLK out of Pin 8.
Register 3, Bit 7 = 1; DATACLK out of Pin 53.
In one-port mode, P2B14 and P2B15 from Input Data Port 2
are redefined as IQSEL and ONEPORTCLK, respectively. The
input data in one-port mode is steered to one of the two internal data channels based on the logic level of IQSEL. A clock
signal, ONEPORTCLK, is generated by the AD9775 in this
mode for the purpose of data synchronization. ONEPORTCLK
runs at the input interleaved data rate, which is 2× the data rate
at the internal input to either channel.
Figure 101 through Figure 104 illustrate the test configurations
showing the various clocks that are required and generated by
the AD9775 with the PLL enabled/disabled and in the oneport/two-port modes. Jumper positions needed to operate the
AD9775 evaluation board in these modes are given as well.
PLL ENABLED, TWO-PORT MODE
(Control Register 0x02, Bit 6 to Bit 0 and
Control Register 0x04, Bit 7 to Bit 1)
With the phase-locked loop (PLL) enabled and the AD9775 in
two-port mode, the speed of CLKIN is inherently that of the
input data rate. In two-port mode, Pin 8 (DATACLK/PLL_
LOCK) can be programmed (Control Register 0x01, Bit 0) to
function as either a lock indicator for the internal PLL or as a
clock running at the input data rate. When Pin 8 is used as a
clock output (DATACLK), its frequency is equal to that of
CLKIN. Data at the input ports is latched into the AD9775 on
the rising edge of the CLKIN. Figure 52 shows the delay, tOD,
inherent between the rising edge of CLKIN and the rising edge
of DATACLK, as well as the setup and hold requirements for
the data at Ports 1 and 2. The setup and hold times given in
Figure 52 are the input data transitions with respect to CLKIN.
Note that in two-port mode (PLL enabled or disabled), the data
rate at the interpolation filter inputs is the same as the input
data rate at Port 1 and Port 2.
The DAC output sample rate in two-port mode is equal to the
clock input rate multiplied by the interpolation rate. If zero
stuffing is used, another factor of 2 must be included to
calculate the DAC sample rate.
Rev. E | Page 28 of 56
AD9775
DATACLK INVERSION
PLL ENABLED, ONE-PORT MODE
(Control Register 0x02, Bit 4)
(Control Register 0x02, Bit 6 to Bit 1 and
Control Register 0x04, Bit 7 to Bit 1)
By programming this bit, the DATACLK signal shown in
Figure 52 can be inverted. With inversion enabled, tOD refers to
the time between the rising edge of CLKIN and the falling edge
of DATACLK. No other effect on timing occurs.
tOD
CLKIN
DATACLK
DATA AT PORTS
1 AND 2
tH
02858-052
tS
tOD = 1.5ns (MIN) TO 2.5ns (MAX)
tS = 0.0ns (MIN)
tH = 2.5ns (MIN)
Figure 52. Timing Requirements in Two-Port Input Mode, with PLL Enabled
DATACLK DRIVER STRENGTH
In one-port mode, the I and Q channels receive their data from an
interleaved stream at digital input Port 1. The function of Pin 32 is
defined as an output (ONEPORTCLK) that generates a clock at the
interleaved data rate, which is 2× the internal input data rate of the I
and Q channels. The frequency of CLKIN is equal to the internal
input data rate of the I and Q channels. The selection of the data for
the I or the Q channel is determined by the state of the logic level at
Pin 31 (IQSEL when the AD9775 is in one-port mode) on the
rising edge of ONEPORTCLK. Under these conditions, IQSEL = 0
latches the data into the I channel on the clock rising edge, while
IQSEL = 1 latches the data into the Q channel. It is possible to
invert the I and Q selection by setting Control Register 0x02, Bit 1
to the invert state (Logic 1). Figure 54 illustrates the timing
requirements for the data inputs as well as the IQSEL input. Note
that the 1× interpolation rate is not available in the one-port mode.
The DAC output sample rate in one-port mode is equal to
CLKIN multiplied by the interpolation rate. If zero stuffing is
used, another factor of 2 must be included to calculate the DAC
sample rate.
ONEPORTCLK INVERSION
(Control Register 0x02, Bit 2)
(Control Register 0x02, Bit 5)
The DATACLK output driver strength is capable of driving
>10 mA into a 330 Ω load while providing a rise time of 3 ns.
Figure 53 shows DATACLK driving a 330 Ω resistive load at a
frequency of 50 MHz. By enabling the drive strength option
(Control Register 0x02, Bit 5), the amplitude of DATACLK
under these conditions increases by approximately 200 mV.
By programming this bit, the ONEPORTCLK signal shown in
Figure 54 can be inverted. With inversion enabled, tOD refers to
the delay between the rising edge of the external clock and the
falling edge of ONEPORTCLK. The setup and hold times, tS
and tH, are with respect to the falling edge of ONEPORTCLK.
There is no other effect on timing.
tOD
3.0
tOD = 4.0ns (MIN)
TO 5.5ns (MAX)
CLKIN
2.5
tS = 3.0ns (MIN)
tH = –0.5ns (MIN)
tIQS = 3.5ns (MIN)
tIQH = –1.5ns (MIN)
1.5
ONEPORTCLK
1.0
0.5
I AND Q INTERLEAVED
INPUT DATA AT PORT 1
0
DELTA APPROX. 2.8ns
–0.5
10
20
30
40
50
TIME (ns)
Figure 53. DATACLK Driver Capability into 330 Ω at 50 MHz
tS tH
IQSEL
tIQS
tIQH
Figure 54. Timing Requirements in One-Port
Input Mode with the PLL Enabled
Rev. E | Page 29 of 56
02858-054
0
02858-053
AMPLITUDE (V)
2.0
AD9775
tOD
ONEPORTCLK DRIVER STRENGTH
The drive capability of ONEPORTCLK is identical to that of
DATACLK in the two-port mode. Refer to Figure 53 for
performance under load conditions.
CLKIN
IQ PAIRING
(Control Register 0x02, Bit 0)
DATACLK
DATA AT PORTS
1 AND 2
tS
Given the following interleaved data stream, where the data
indicates the value with respect to full scale:
tOD = 6.5ns (MIN) TO 8.0ns (MAX)
tS = 5.0ns (MIN)
tH = –3.2ns (MIN)
tH
02858-055
In one-port mode, the interleaved data is latched into the
AD9775 internal I and Q channels in pairs. The order of how
the pairs are latched internally is defined by this control register.
The following is an example of the effect that this has on
incoming interleaved data.
Figure 55. Timing Requirements in Two-Port Input Mode with PLL Disabled
Table 20.
I
0.5
Q
0.5
I
1
Q
1
I
0.5
Q
0.5
I
0
Q
0
I
0.5
tOD
Q
0.5
With the control register set to 0 (I first), the data appears at the
internal channel inputs in the following order in time:
CLKIN
Table 21.
I Channel
Q Channel
0.5
0.5
1
1
0.5
0.5
0
0
0.5
0.5
ONEPORTCLK
With the control register set to 1 (Q first), the data appears at
the internal channel inputs in the following order in time:
Table 22.
0.5
y
1
0.5
0.5
1
0
0.5
0.5
0
x
0.5
I AND Q INTERLEAVED
INPUT DATA AT PORT 1
The values x and y represent the next I value and the previous
Q value in the series.
tS tH
IQSEL
PLL DISABLED, TWO-PORT MODE
tOD = 4.0ns (MIN)
With the PLL disabled, a clock at the DAC output rate must be
applied to CLKIN. Internal clock dividers in the AD9775
synthesize the DATACLK signal at Pin 8, which runs at the
input data rate and can be used to synchronize the input data.
Data is latched into input Port 1 and Port 2 of the AD9775 on
the rising edge of DATACLK. DATACLK speed is defined as the
speed of CLKIN divided by the interpolation rate. With zero
stuffing enabled, this division increases by a factor of 2. Figure 55
illustrates the delay between the rising edge of CLKIN and the
rising edge of DATACLK, as well as tS and tH in this mode.
The programmable modes DATACLK inversion and DATACLK
driver strength described in the previous section (PLL Enabled,
Two-Port Mode) have identical functionality with the PLL
disabled.
The data rate clock created by dividing down the DAC clock in
this mode can be programmed (via Register 0x03, Bit 7) to be
output from the SPI_SDO pin rather than the DATACLK/
PLL_LOCK pin. In some applications, this may improve
complex image rejection. When SPI_SDO is used as data rate
clock out, tOD increases by 1.6 ns.
TO 5.5ns (MAX)
tS = 3.0ns (MIN)
tH = –1.0ns (MIN)
tIQS = 3.5ns (MIN)
tIQH = –1.5ns (MIN)
tIQS
tIQH
02858-056
I Channel
Q Channel
Figure 56. Timing Requirements in One-Port Input Mode with PLL Disabled
PLL DISABLED, ONE-PORT MODE
In one-port mode, data is received into the AD9775 as an
interleaved stream on Port 1. A clock signal (ONEPORTCLK)
running at the interleaved data rate, which is 2× the input data
rate of the internal I and Q channels, is available for data
synchronization at Pin 32.
With PLL disabled, a clock at the DAC output rate must be
applied to CLKIN. Internal dividers synthesize the
ONEPORTCLK signal at Pin 32. The selection of the data for
the I or Q channel is determined by the state of the logic level
applied to Pin 31 (IQSEL when the AD9775 is in one-port
mode) on the rising edge of ONEPORTCLK. Under these
conditions, IQSEL = 0 latches the data into the I channel on the
clock rising edge, while IQSEL = 1 latches the data into the Q
channel.
Rev. E | Page 30 of 56
AD9775
frequency images. This is shown graphically in the frequency
domain in Figure 57.
e–jωt/2j
SINE
DC
One-port mode is very useful when interfacing with devices
such as the Analog Devices AD6622 or AD6623 transmit signal
processors, in which two digital data channels have been
interleaved (multiplexed).
e–jωt/2j
e–jωt/2
e–jωt/2
COSINE
The programmable modes’ ONEPORTCLK inversion,
ONEPORTCLK driver strength, and IQ pairing described in
the PLL Enabled, One-Port Mode section have identical
functionality with the PLL disabled.
DIGITAL FILTER MODES
The I and Q datapaths of the AD9775 have their own
independent half-band FIR filters. Each datapath consists of
three FIR filters, providing up to 8× interpolation for each
channel. The rate of interpolation is determined by the state of
Control Register 0x01, Bit 7 and Bit 6. Figure 2 to Figure 4 show
the response of the digital filters when the AD9775 is set to 2×,
4×, and 8× modes. The frequency axes of these graphs are
normalized to the input data rate of the DAC. As the graphs
show, the digital filters can provide greater than 75 dB of
out-of-band rejection.
DC
02858-057
It is possible to invert the I and Q selection by setting control
Register 0x02, Bit 1 to the invert state (Logic 1). Figure 56
illustrates the timing requirements for the data inputs as well as
the IQSEL input. Note that the 1× interpolation rate is not
available in the one-port mode.
Figure 57. Real and Imaginary Components of
Sinusoidal and Cosinusoidal Waveforms
Amplitude modulating a baseband signal with a sine or a cosine
convolves the baseband signal with the modulating carrier in
the frequency domain. Amplitude scaling of the modulated
signal reduces the positive and negative frequency images by a
factor of 2.
This scaling is very important in the discussion of the various
modulation modes. The phase relationship of the modulated
signals is dependent on whether the modulating carrier is
sinusoidal or cosinusoidal, again with respect to the reference
point of the viewer. Examples of sine and cosine modulation are
given in Figure 58.
Ae–jωt/2j
An online tool is available for quick and easy analysis of the
AD9775 interpolation filters in the various modes. The link can
be accessed at www.analog.com/ad9777image.
AMPLITUDE MODULATION
SINUSOIDAL
MODULATION
DC
Ae–jωt/2j
Rev. E | Page 31 of 56
Ae–jωt/2
Ae–jωt/2
COSINUSOIDAL
MODULATION
DC
Figure 58. Baseband Signal, Amplitude Modulated
with Sine and Cosine Carriers
02858-058
Given two sine waves at the same frequency, but with a
90 degree phase difference, a point of view in time can be taken
such that the waveform that leads in phase is cosinusoidal and
the waveform that lags is sinusoidal. Analysis of complex
variables states that the cosine waveform can be defined as
having real positive and negative frequency components, while
the sine waveform consists of imaginary positive and negative
AD9775
MODULATION, NO INTERPOLATION
With Control Register 0x01, Bit 7 and Bit 6 set to 00, the
interpolation function on the AD9775 is disabled. Figure 59
through Figure 62 show the DAC output spectral characteristics
of the AD9775 in the various modulation modes, all with the
interpolation filters disabled. The modulation frequency is
determined by the state of Control Register 0x01, Bit 5 and Bit 4.
The tall rectangles represent the digital domain spectrum of a
baseband signal of narrow bandwidth. By comparing the digital
domain spectrum to the DAC sin(x)/x roll-off, an estimate can
be made for the characteristics required for the DAC reconstruction filter.
Note also, per the previous discussion on amplitude
modulation, that the spectral components (where modulation is
set to fS/4 or fS/8) are scaled by a factor of 2. In the situation
where the modulation is fS/2, the modulated spectral
components add constructively, and there is no
scaling effect.
0
0
–20
–20
AMPLITUDE (dBFS)
–40
–60
–40
–60
–80
–80
0.2
0.4
0.6
0.8
1.0
fOUT (×fDATA)
02858-059
0
0
0.4
0.6
0.8
1.0
1.0
fOUT (×fDATA)
Figure 59. No Interpolation, Modulation Disabled
Figure 61. No Interpolation, Modulation = fDAC/4
0
–20
–20
AMPLITUDE (dBFS)
0
–40
–60
–40
–60
–80
–80
–100
–100
0
0.2
0.4
0.6
0.8
fOUT (×fDATA)
1.0
02858-060
AMPLITUDE (dBFS)
0.2
02858-061
–100
–100
02858-062
AMPLITUDE (dBFS)
The Effects of the Digital Modulation on the DAC Output Spectrum, Interpolation Disabled
Figure 60. No Interpolation, Modulation = fDAC/2
0
0.2
0.4
0.6
0.8
fOUT (×fDATA)
Figure 62. No Interpolation, Modulation = fDAC/8
Rev. E | Page 32 of 56
AD9775
MODULATION, INTERPOLATION = 2×
With Control Register 0x01, Bit 7 and Bit 6 set to 01, the
interpolation rate of the AD9775 is 2×. Modulation is achieved
by multiplying successive samples at the interpolation filter
output by the sequence (+1, −1). Figure 63 through Figure 66
represent the spectral response of the AD9775 DAC output with
2× interpolation in the various modulation modes to a narrowband baseband signal (the tall rectangles in the graphic). The
advantage of interpolation becomes clear in Figure 63 through
Figure 66, where the images that would normally appear in the
spectrum around the input data rate frequency are suppressed
by >70 dB.
Another significant point is that the interpolation filtering is
done previous to the digital modulator. For this reason, as
Figure 63 through Figure 66 show, the pass band of the
interpolation filters can be frequency shifted, giving the equivalent
of a high-pass digital filter.
Note that when using the fS/4 modulation mode, there is no
true stop band as the band edges coincide with each other. In
the fS/8 modulation mode, amplitude scaling occurs over only a
portion of the digital filter pass band due to constructive
addition over just that section of the band.
0
0
–20
–20
AMPLITUDE (dBFS)
–40
–60
–40
–60
–80
–80
0.5
1.0
1.5
2.0
fOUT (×fDATA)
0
1.0
1.5
2.0
2.0
fOUT (×fDATA)
Figure 63. 2× Interpolation, Modulation = Disabled
Figure 65. 2× Interpolation, Modulation = fDAC/4
0
–20
–20
AMPLITUDE (dBFS)
0
–40
–60
–40
–60
–80
–80
–100
0
0.5
1.0
1.5
fOUT (×fDATA)
2.0
02858-064
AMPLITUDE (dBFS)
0.5
02858-065
–100
0
02858-063
–100
02858-066
AMPLITUDE (dBFS)
The Effects of the Digital Modulation on the DAC Output Spectrum, Interpolation = 2×
–100
Figure 64. 2× Interpolation, Modulation = fDAC/2
0
0.5
1.0
1.5
fOUT (×fDATA)
Figure 66. 2× Interpolation, Modulation = fDAC/8
Rev. E | Page 33 of 56
AD9775
MODULATION, INTERPOLATION = 4×
With Control Register 0x01, Bit 7 and Bit 6 set to 10, the
interpolation rate of the AD9775 is 4×. Modulation is achieved
by multiplying successive samples at the interpolation filter
output by the sequence (0, +1, 0, −1).
Figure 67 through Figure 70 represent the spectral response of
the AD9775 DAC output with 4× interpolation in the various
modulation modes to a narrow-band baseband signal.
0
0
–20
–20
AMPLITUDE (dBFS)
–40
–60
–40
–60
–80
–80
1
2
3
4
fOUT (×fDATA)
0
2
3
4
4
fOUT (×fDATA)
Figure 67. 4× Interpolation, Modulation Disabled
Figure 69. 4× Interpolation, Modulation = fDAC/2
0
–20
–20
AMPLITUDE (dBFS)
0
–40
–60
–40
–60
–80
–80
–100
–100
0
1
2
3
fOUT (×fDATA)
4
02858-068
AMPLITUDE (dBFS)
1
02858-069
–100
0
02858-067
–100
02858-070
AMPLITUDE (dBFS)
The Effects of the Digital Modulation on the DAC Output Spectrum, Interpolation = 4×
0
1
2
3
fOUT (×fDATA)
Figure 70. 4× Interpolation, Modulation = fDAC/8
Figure 68. 4× Interpolation, Modulation = fDAC/4
Rev. E | Page 34 of 56
AD9775
MODULATION, INTERPOLATION = 8×
With Control Register 0x01, Bit 7 and Bit 6 set to 11, the
interpolation rate of the AD9775 is 8×. Modulation is achieved
by multiplying successive samples at the interpolation filter
output by the sequence (0, +0.707, +1, +0.707, 0, −0.707, −1,
+0.707). Figure 71 through Figure 74 represent the spectral
response of the AD9775 DAC output with 8× interpolation in the
various modulation modes to a narrow-band baseband signal.
Looking at Figure 63 through Figure 74, the user can see how
higher interpolation rates reduce the complexity of the reconstruction filter needed at the DAC output. It also becomes
apparent that the ability to modulate by fS/2, fS/4, or fS/8 adds a
degree of flexibility in frequency planning.
0
0
–20
–20
AMPLITUDE (dBFS)
–40
–60
–40
–60
–80
–80
–100
2
3
4
fOUT (×fDATA)
0
2
3
4
5
6
7
8
8
fOUT (×fDATA)
Figure 73. 8× Interpolation, Modulation = fDAC/4
Figure 71. 8× Interpolation, Modulation Disabled
0
–20
–20
AMPLITUDE (dBFS)
0
–40
–60
–40
–60
–80
–80
–100
–100
0
1
2
3
fOUT (×fDATA)
4
02858-072
AMPLITUDE (dBFS)
1
02858-073
1
02858-071
–100
0
02858-074
AMPLITUDE (dBFS)
The Effects of the Digital Modulation on the DAC Output Spectrum, Interpolation = 8×
0
1
2
3
4
5
6
7
fOUT (×fDATA)
Figure 74. 8× Interpolation, Modulation = fDAC/8
Figure 72. 8× Interpolation, Modulation = fDAC/2
Rev. E | Page 35 of 56
AD9775
ZERO STUFFING
(Control Register 0x01, Bit 3)
As shown in Figure 75, a 0 or null in the output frequency
response of the DAC (after interpolation, modulation, and DAC
reconstruction) occurs at the final DAC sample rate (fDAC). This
is due to the inherent sin(x)/x roll-off response in the digital-toanalog conversion. In applications where the desired frequency
content is below fDAC/2, this may not be a problem. Note that at
fDAC/2 the loss due to sin(x)/x is 4 dB. In direct RF applications,
this roll-off may be problematic due to the increased pass-band
amplitude variation as well as the reduced amplitude of the
desired signal.
Consider an application where the digital data into the AD9775
represents a baseband signal around fDAC/4 with a pass band of
fDAC/10. The reconstructed signal out of the AD9775 would
experience only a 0.75 dB amplitude variation over its pass band.
However, the image of the same signal occurring at 3 × fDAC/4
suffers from a pass-band flatness variation of 3.93 dB. This image
may be the desired signal in an IF application using one of the
various modulation modes in the AD9775. This roll-off of image
frequencies can be seen in Figure 59 to Figure 74, where the effect
of the interpolation and modulation rate is apparent as well.
10
ZERO STUFFING
ENABLED
SIN (X)/X ROLL-OFF (dBFS)
0
INTERPOLATING (COMPLEX MIX MODE)
(Control Register 0x01, Bit 2)
In the complex mix mode, the two digital modulators on the
AD9775 are coupled to provide a complex modulation function.
In conjunction with an external quadrature modulator, this
complex modulation can be used to realize a transmit image
rejection architecture. The complex modulation function can be
programmed for e+jωt or e−jωt to give upper or lower image
rejection. As in the real modulation mode, the modulation
frequency ω can be programmed via the SPI port for fDAC/2,
fDAC/4, and fDAC/8, where fDAC represents the DAC output rate.
OPERATIONS ON COMPLEX SIGNALS
Truly complex signals cannot be realized outside of a computer
simulation. However, two data channels, both consisting of real
data, can be defined as the real and imaginary components of a
complex signal. I (real) and Q (imaginary) datapaths are often
defined this way. By using the architecture defined in Figure 76,
a system can be realized that operates on complex signals,
giving a complex (real and imaginary) output.
If a complex modulation function (e+jωt) is desired, the real and
imaginary components of the system correspond to the real and
imaginary components of e+jωt or cosωt and sinωt. As Figure 77
shows, the complex modulation function can be realized by
applying these components to the structure of the complex
system defined in Figure 76.
–10
–20
ZERO STUFFING
DISABLED
–30
Note that the zero-stuffing option by itself does not change the
location of the images but rather their amplitude, pass-band
flatness, and relative weighting. For instance, in the previous
example, the pass-band amplitude flatness of the image at
3 × fDATA/4 improved to +0.59 dB while the signal level increased
slightly from −10.5 dBFS to −8.1 dBFS.
–40
a(t)
1.5
2.0
c(t) × b(t) + d × b(t)
b(t)
IMAGINARY
INPUT
OUTPUT
b(t) × a(t) + c × b(t)
Figure 75. Effect of Zero Stuffing on DAC’s sin(x)/x Response
To improve upon the pass-band flatness of the desired image,
the zero stuffing mode can be enabled by setting the control
register bit to Logic 1. This option increases the ratio of
fDAC/fDATA by a factor of 2 by doubling the DAC sample rate and
inserting a midscale sample (that is, 1000 0000 0000 0000) after
every data sample originating from the interpolation filter. This
is important as it affects the PLL divider ratio needed to keep
the VCO within its optimum speed range. Note that the zero
stuffing takes place in the digital signal chain at the output of
the digital modulator before the DAC.
The net effect is to increase the DAC output sample rate by a
factor of 2× with the 0 in the sin(x)/x DAC transfer function
occurring at twice the original frequency. A 6 dB loss in
amplitude at low frequencies is also evident (see Figure 75).
Rev. E | Page 36 of 56
02858-076
1.0
OUTPUT
Figure 76. Realization of a Complex System
INPUT
(REAL)
OUTPUT
(REAL)
INPUT
(IMAGINARY)
90°
OUTPUT
(IMAGINARY)
e–jωt = COSωt + jSINωt
02858-077
0.5
02858-075
0
fOUT, NORMALIZED TO fDATA WITH ZERO STUFFING DISABLED (Hz)
INPUT
COMPLEX FILTER
= (c + jd)
–50
Figure 77. Implementation of a Complex Modulator
AD9775
the baseband real and imaginary channels, now modulated onto
orthogonal (cosine and negative sine) carriers at the transmit
frequency. It is important to remember that in this application
(two baseband data channels) the image rejection is not
dependent on the data at either of the AD9775 input channels.
In fact, image rejection still occurs with either one or both of
the AD9775 input channels active. Note that by changing the
sign of the sinusoidal multiplying term in the complex
modulator, the upper sideband image could have been
suppressed while passing the lower one. This is easily done in
the AD9775 by selecting the e+jωt bit (Register 0x01, Bit 1). In
purely complex terms, Figure 79 represents the two-stage
upconversion from complex baseband to carrier.
COMPLEX MODULATION AND IMAGE REJECTION
OF BASEBAND SIGNALS
In traditional transmit applications, a two-step upconversion is
done in which a baseband signal is modulated by one carrier to
an intermediate frequency (IF) and then modulated a second
time to the transmit frequency. Although this approach has
several benefits, a major drawback is that two images are
created near the transmit frequency. Only one image is needed,
the other being an exact duplicate. Unless the unwanted image
is filtered, typically with analog components, transmit power is
wasted and the usable bandwidth available in the system is reduced.
A more efficient method of suppressing the unwanted image
can be achieved by using a complex modulator followed by a
quadrature modulator. Figure 78 is a block diagram of a
quadrature modulator. Note that it is in fact the real output half
of a complex modulator. The complete upconversion can
actually be referred to as two complex upconversion stages, the
real output of which becomes the transmitted signal.
INPUT
(REAL)
OUTPUT
INPUT
(IMAGINARY)
90°
The entire upconversion, from baseband to transmit frequency,
is represented graphically in Figure 79. The resulting spectrum
shown in Figure 79 represents the complex data consisting of
COSωt
Figure 78. Quadrature Modulator
REAL CHANNEL (OUT)
A/2
A/2
–FC1
FC
–B/2J
B/2J
–FC
FC
REAL CHANNEL (IN)
A
DC
COMPLEX
MODULATOR
TO QUADRATURE
MODULATOR
IMAGINARY CHANNEL (OUT)
–A/2J
A/2J
–FC
–FC
B/2
B/2
–FC
FC
IMAGINARY CHANNEL (IN)
B
DC
A/4 + B/4J
A/4 – B/4J
A/4 + B/4J
A/4 – B/4J
–FQ2
–FQ – FC
–FQ + FC
F Q – FC
–A/4 – B/4J A/4 – B/4J
A/4 + B/4J –A/4 + B/4J
FQ
FQ + F C
OUT
REAL
QUADRATURE
MODULATOR
–FQ
IMAGINARY
FQ
REJECTED IMAGES
–FQ
A/2 – B/2J
FQ
1F = COMPLEX MODULATION FREQUENCY
C
2F = QUADRATURE MODULATION FREQUENCY
Q
Figure 79. Two-Stage Upconversion and Resulting Image Rejection
Rev. E | Page 37 of 56
02858-079
A/2 + B/2J
02858-078
SINωt
AD9775
data on any channel. Image rejection on a channel occurs if
either the real or imaginary data, or both, is present on the
baseband channel.
IMAGE REJECTION AND SIDEBAND SUPPRESSION
OF MODULATED CARRIERS
As shown in Figure 79, image rejection can be achieved by
applying baseband data to the AD9775 and following the
AD9775 with a quadrature modulator. To process multiple
carriers while still maintaining image reject capability, each
carrier must be complex modulated. As Figure 80 shows, single
or multiple complex modulators can be used to synthesize
complex carriers. These complex carriers are then summed and
applied to the real and imaginary inputs of the AD9775.
It is important to remember that the magnitude of a complex
signal can be 1.414× the magnitude of its real or imaginary
components. Due to this 3 dB increase in signal amplitude, the
real and imaginary inputs to the AD9775 must be kept at least
3 dB below full scale when operating with the complex modulator. Overranging in the complex modulator results in severe
distortion at the DAC output.
COMPLEX BASEBAND
SIGNAL
A system in which multiple baseband signals are complex
modulated and then applied to the AD9775 real and imaginary
inputs followed by a quadrature modulator is shown in Figure 82,
which also describes the transfer function of this system and the
spectral output. Note the similarity of the transfer functions
given in Figure 82 and Figure 80. Figure 82 adds an additional
complex modulator stage for the purpose of summing multiple
carriers at the AD9775 inputs. Also, as in Figure 79, the image
rejection is not dependent on the real or imaginary baseband
–ω1 – ω2
DC
ω1 + ω2
FREQUENCY
02858-080
= REAL
1/2
Figure 80. Two-Stage Complex Upconversion
R(1)
MULTICARRIER
REAL OUTPUT =
R(1) + R(2) + . . .R(N)
(TO REAL INPUT OF AD9775)
R(1)
R(2)
COMPLEX
MODULATOR 2
IMAGINARY INPUT
BASEBAND CHANNEL N
REAL INPUT
ej(ω1 + ω2)t
1/2
COMPLEX
MODULATOR 1
IMAGINARY INPUT
BASEBAND CHANNEL 2
REAL INPUT
×
MULTICARRIER
IMAGINARY OUTPUT =
I(1) + I(2) + . . .I(N)
(TO IMAGINARY INPUT OF AD9775)
R(2)
R(N)
COMPLEX
MODULATOR N
R(N) = REAL OUTPUT OF N
I(N) = IMAGINARY OUTPUT OF N
02858-081
BASEBAND CHANNEL 1
REAL INPUT
1
OUTPUT = REAL
R(N)
IMAGINARY INPUT
Figure 81. Synthesis of Multicarrier Complex Signal
MULTIPLE
BASEBAND
CHANNELS
IMAGINARY
MULTIPLE
COMPLEX
MODULATORS
FREQUENCY = ω1, ω2...ωN
REAL
AD9775
COMPLEX
MODULATOR
FREQUENCY = ωC
IMAGINARY
REAL
IMAGINARY
REAL
QUADRATURE
MODULATOR
FREQUENCY = ωQ
COMPLEX BASEBAND
SIGNAL
×
OUTPUT = REAL
–ω1 – ωC – ωQ
ej(ωN + ωC + ωQ)t
ω1 + ωC + ωQ
DC
REJECTED IMAGES
Figure 82. Image Rejection with Multicarrier Signals
Rev. E | Page 38 of 56
02858-082
REAL
AD9775
The complex carrier synthesized in the AD9775 digital
modulator is accomplished by creating two real digital carriers
in quadrature. Carriers in quadrature cannot be created with
the modulator running at fDAC/2. As a result, complex modulation only functions with modulation rates of fDAC/4 and fDAC/8.
Regions A and B of Figure 83 to Figure 88 are the result of the
complex signal described previously, when complex modulated
in the AD9775 by +ejωt. Regions C and D are the result of the
complex signal described previously, again with positive
frequency components only, modulated in the AD9775 by –ejωt.
The analog quadrature modulator after the AD9775 inherently
modulates by +ejωt.
Region A
Region A is a direct result of the upconversion of the complex
signal near baseband. If viewed as a complex signal, only the
images in Region A remain. The complex Signal A, consisting
of positive frequency components only in the digital domain,
has images in the positive odd Nyquist zones (1, 3, 5, …), as
well as images in the negative even Nyquist zones. The
appearance and rejection of images in every other Nyquist zone
becomes more apparent at the output of the quadrature
modulator. The A images appear on the real and the imaginary
outputs of the AD9775, as well as on the output of the quadrature
modulator, where the center of the spectral plot now represents
the quadrature modulator LO, and the horizontal scale now
represents the frequency offset from this LO.
the high end of the DAC output spectrum in these graphs is the
first null point for the sin(x)/x roll-off, and the asymmetry of the
DAC output images is representative of the sin(x)/x roll-off over the
spectrum. The internal PLL was enabled for these results. In
addition, a 35 MHz third-order low-pass filter was used at the
AD9775/AD8345 interface to suppress DAC images.
An important point can be made by looking at Figure 91 and
Figure 93. Figure 91 represents a group of positive frequencies
modulated by complex +fDAC/4, while Figure 93 represents a
group of negative frequencies modulated by complex −fDAC/4.
When looking at the real or imaginary outputs of the AD9775,
as shown in Figure 91 and Figure 93, the results look identical.
However, the spectrum analyzer cannot show the phase
relationship of these signals. The difference in phase between
the two signals becomes apparent when they are applied to the
AD8345 quadrature modulator, with the results shown in
Figure 92 and Figure 94.
0
–20
D
A
B
C
D
A
B
C
–40
–60
–80
Region B is the image (complex conjugate) of Region A. If a
spectrum analyzer is used to view the real or imaginary DAC
outputs of the AD9775, Region B appears in the spectrum.
However, on the output of the quadrature modulator, Region B
is rejected.
–100
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
02858-083
Region B
(LO)
fOUT (×fDATA)
Figure 83. 2× Interpolation, Complex fDAC/4 Modulation
Region C
Region C is most accurately described as a downconversion, as
the modulating carrier is –ejωt. If viewed as a complex signal, only
the images in Region C remain. This image appears on the real
and imaginary outputs of the AD9775, as well as on the output of
the quadrature modulator, where the center of the spectral plot
now represents the quadrature modulator LO and the horizontal
scale represents the frequency offset from this LO.
–20
Region D
–60
D
A
B
C
D
A
B
C
–40
–80
–100
–4.0
Figure 89 to Figure 96 show the measured response of the AD9775
and AD8345 given the complex input signal to the AD9775 in
Figure 89. The data in these graphs was taken with a data rate of
12.5 MSPS at the AD9775 inputs. The interpolation rate of 4× or 8×
gives a DAC output data rate of 50 MSPS or 100 MSPS. As a result,
Rev. E | Page 39 of 56
–3.0
–2.0
–1.0
0
1.0
2.0
3.0
4.0
(LO)
fOUT (×fDATA)
Figure 84. 4× Interpolation, Complex fDAC/4 Modulation
02858-084
Region D is the image (complex conjugate) of Region C. If a
spectrum analyzer is used to view the real or imaginary DAC
outputs of the AD9775, Region D appears in the spectrum.
However, on the output of the quadrature modulator, Region D
is rejected.
0
AD9775
0
–20
–20
D
A
B
C
D
A
B
DA
C
–40
–40
–60
–60
–80
–80
–6.0
–4.0
–2.0
0
2.0
4.0
6.0
–100
–8.0
8.0
–6.0
–4.0
–2.0
02858-085
–100
–8.0
BC
(LO)
fOUT (×fDATA)
DA
BC
0
2.0
4.0
6.0
8.0
02858-088
0
(LO)
fOUT (×fDATA)
Figure 85. 8× Interpolation, Complex fDAC/4 Modulation
Figure 88. 8× Interpolation, Complex fDAC/8 Modulation
0
0
–10
–20
–20
AMPLITUDE (dBm)
–40
D
A
B
CD
A
B
–30
C
–60
–40
–50
–60
–70
–80
–80
–90
–1.0
–0.5
0
0.5
1.0
1.5
–100
2.0
(LO)
fOUT (×fDATA)
0
10
20
30
40
50
FREQUENCY (MHz)
02858-089
–1.5
02858-086
–100
–2.0
Figure 89. AD9775 Real DAC Output of Complex Input Signal Near Baseband
(Positive Frequencies Only), Interpolation = 4×, No Modulation in AD9775
Figure 86. 2× Interpolation, Complex fDAC/8 Modulation
0
0
–10
–20
–20
AMPLITUDE (dBm)
–40
D A
B
C D
A
B
–30
C
–60
–40
–50
–60
–70
–80
–80
–2.0
–1.0
0
1.0
2.0
3.0
4.0
(LO)
fOUT (×fDATA)
02858-087
–3.0
–100
750
760
770
780
790
800
810
820
830
840
850
FREQUENCY (MHz)
Figure 90. AD9775 Complex Output from Figure 89,
Now Quadrature Modulated by AD8345 (LO = 800 MHz)
Figure 87. 4× Interpolation, Complex fDAC/8 Modulation
Rev. E | Page 40 of 56
02858-090
–90
–100
–4.0
0
0
–10
–10
–20
–20
–30
–30
AMPLITUDE (dBm)
–40
–50
–60
–70
–40
–50
–60
–70
–80
–80
–100
750
10
20
30
40
50
FREQUENCY (MHz)
02858-091
0
780
790
800
810
820
830
840
850
Figure 94. AD9775 Complex Output from Figure 93,
Now Quadrature Modulated by AD8345 (LO = 800 MHz)
0
0
–10
–10
–20
–20
–30
–30
AMPLITUDE (dBm)
–40
–50
–60
–70
–40
–50
–60
–70
–80
–80
–90
–90
760
770
780
790
800
810
820
830
840
850
FREQUENCY (MHz)
–100
02858-092
–100
750
0
20
40
60
80
100
FREQUENCY (MHz)
Figure 92. AD9775 Complex Output from Figure 91,
Now Quadrature Modulated by AD8345 (LO = 800 MHz)
02858-095
AMPLITUDE (dBm)
770
FREQUENCY (MHz)
Figure 91. AD9775 Real DAC Output of Complex Input Signal Near
Baseband (Positive Frequencies Only), Interpolation = 4×,
Complex Modulation in AD9775 = +fDAC/4
Figure 95. AD9775 Real DAC Output of Complex Input Signal Near
Baseband (Positive Frequencies Only), Interpolation = 8×,
Complex Modulation in AD9775 = +fDAC/8
0
–10
–10
–20
–20
–30
–30
AMPLITUDE (dBm)
0
–40
–50
–60
–70
–40
–50
–60
–70
–80
–80
–90
–90
–100
0
10
20
30
40
50
FREQUENCY (MHz)
02858-093
AMPLITUDE (dBm)
760
02858-094
–90
–90
–100
–100
700
Figure 93. AD9775 Real DAC Output of Complex Input Signal Near
Baseband (Negative Frequencies Only), Interpolation = 4×,
Complex Modulation in AD9775 = −fDAC/4
720
740
760
780
800
820
840
860
880
900
FREQUENCY (MHz)
Figure 96. AD9775 Complex Output from Figure 95,
Now Quadrature Modulated by AD8345 (LO = 800 MHz)
Rev. E | Page 41 of 56
02858-096
AMPLITUDE (dBm)
AD9775
AD9775
APPLYING THE OUTPUT CONFIGURATIONS
A single-ended output is suitable for applications requiring a
unipolar voltage output. A positive unipolar output voltage
results if IOUTA and/or IOUTB is connected to a load resistor, RLOAD,
referred to AGND. This configuration is most suitable for a
single-supply system requiring a dc-coupled, ground-referred
output voltage. Alternatively, an amplifier could be configured
as an I-V converter, thus converting IOUTA or IOUTB into a
negative unipolar voltage. This configuration provides the best
DAC dc linearity as IOUTA or IOUTB are maintained at ground or
virtual ground.
In many applications, it may be necessary to understand the
equivalent DAC output circuit. This is especially useful when
designing output filters or when driving inputs with finite input
impedances. Figure 97 illustrates the output of the AD9775 and
the equivalent circuit. A typical application where this
information may be useful is when designing an interface filter
between the AD9775 and Analog Devices’ AD8345 quadrature
modulator.
VOUT+
IOUTB
VOUT–
VSOURCE = 2 V p-p
R OUT = 100 Ω
Note that the output impedance of the AD9775 DAC itself is
greater than 100 kΩ and typically has no effect on the
impedance of the equivalent output circuit.
DIFFERENTIAL COUPLING USING A
TRANSFORMER
An RF transformer can be used to perform a differential-tosingle-ended signal conversion, as shown in Figure 98. A differentially coupled transformer output provides the optimum
distortion performance for output signals whose spectral content
lies within the transformer’s pass band. An RF transformer, such
as the Mini-Circuits T1-1T, provides excellent rejection of
common-mode distortion (that is, even-order harmonics) and
noise over a wide frequency range. It also provides electrical
isolation and the ability to deliver twice the power to the load.
Transformers with different impedance ratios can also be used for
impedance matching purposes.
IOUTA
DAC
IOUTB
02858-097
VOUT
(DIFFERENTIAL)
RLOAD
The center tap on the primary side of the transformer must be
connected to AGND to provide the necessary dc current path
for both IOUTA and IOUTB. The complementary voltages appearing
at IOUTA and IOUTB (that is, VOUTA and VOUTB) swing symmetrically
around AGND and should be maintained within the specified
output compliance range of the AD9775. A differential resistor,
RDIFF, can be inserted in applications where the output of the
transformer is connected to the load, RLOAD, via a passive
reconstruction filter or cable. RDIFF is determined by the
transformer’s impedance ratio and provides the proper source
termination that results in a low VSWR. Note that approximately half the signal power dissipates across RDIFF.
RA + R B
VSOURCE =
IOUTFS × (RA + RB)
p-p
MINI-CIRCUITS
T1-1T
Figure 98. Transformer-Coupled Output Circuit
UNBUFFERED DIFFERENTIAL OUTPUT,
EQUIVALENT CIRCUIT
IOUTA
For the typical situation, where IOUTFS = 20 mA and RA and RB
both equal 50 Ω, the equivalent circuit values become
02858-098
The following sections illustrate typical output configurations
for the AD9775. Unless otherwise noted, it is assumed that
IOUTFS is set to a nominal 20 mA. For applications requiring
optimum dynamic performance, a differential output configuration is suggested. A simple differential output may be
achieved by converting IOUTA and IOUTB to a voltage output
by terminating them to AGND via equal value resistors. This
type of configuration may be useful when driving a differential
voltage input device such as a modulator. If a conversion to a
single-ended signal is desired and the application allows for ac
coupling, an RF transformer may be useful, or if power gain is
required, an op amp may be used. The transformer configuration provides optimum high frequency noise and distortion
performance. The differential op amp configuration is suitable
for applications requiring dc coupling, signal gain, and/or level
shifting within the bandwidth of the chosen op amp.
Figure 97. DAC Output Equivalent Circuit
Rev. E | Page 42 of 56
AD9775
DIFFERENTIAL COUPLING USING AN OP AMP
Gain/Offset Adjust
An op amp can also be used to perform a differential-to-singleended conversion, as shown in Figure 99. This has the added
benefit of providing signal gain as well. In Figure 99, the
AD9775 is configured with two equal load resistors, RLOAD, of
25 Ω. The differential voltage developed across IOUTA and IOUTB is
converted to a single-ended signal via the differential op amp
configuration. An optional capacitor can be installed across
IOUTA and IOUTB, forming a real pole in a low-pass filter. The
addition of this capacitor also enhances the op amp distortion
performance by preventing the DAC fast slewing output from
overloading the input of the op amp.
The matching of the DAC output to the common-mode input
of the AD8345 allows the two components to be dc-coupled,
with no level shifting necessary. The combined voltage offset of
the two parts can therefore be compensated for via the AD9775
programmable offset adjust. This allows excellent LO cancellation at the AD8345 output. The programmable gain adjust
allows for optimal image rejection as well.
AD8021
DAC
IOUTB
COPT
225Ω
25Ω
500Ω
ROPT
225Ω
02858-099
AVDD
25Ω
Figure 99. Op Amp-Coupled Output Circuit
The common-mode (and second-order distortion) rejection of
this configuration is typically determined by the resistor
matching. The op amp used must operate from a dual supply
because its output is approximately ±1.0 V. A high speed
amplifier, such as the AD8021, capable of preserving the
differential performance of the AD9775 while meeting other
system level objectives (such as cost and power) is
recommended. The op amp differential gain, its gain setting
resistor values, and full-scale output swing capabilities should
all be considered when optimizing this circuit. ROPT is only
necessary if level shifting is required on the op amp output. In
Figure 99, AVDD, which is the positive analog supply for both
the AD9775 and the op amp, is also used to level shift the
differential output of the AD9775 to midsupply, that is,
AVDD/2.
INTERFACING THE AD9775 WITH THE AD8345
QUADRATURE MODULATOR
The AD9775 architecture was defined to operate in a transmit
signal chain using an image reject architecture. A quadrature
modulator is also required in this application and should be
designed to meet the output characteristics of the DAC as much
as possible. The AD8345 from Analog Devices meets many of
the requirements for interfacing with the AD9775. As with any
DAC output interface, there are a number of issues that have to
be resolved. The following sections list some of these issues.
The performance of the AD9775 and AD8345 in an image reject
transmitter, reconstructing three W-CDMA carriers, can be seen in
Figure 100. The LO of the AD8345 in this application is 800 MHz.
Image rejection (50 dB) and LO feedthrough (−78 dBFS) have been
optimized with the programmable features of the AD9775. The
average output power of the digital waveform for this test was set
to −15 dBFS to account for the peak-to-average ratio of the
W-CDMA signal.
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
762.5
DAC Compliance Voltage/Input Common-Mode Range
The dynamic range of the AD9775 is optimal when the DAC
outputs swing between ±1.0 V. The input common-mode range
of the AD8345, at 0.7 V, allows optimum dynamic range to be
achieved in both components.
Rev. E | Page 43 of 56
782.5
802.5
822.5
842.5
FREQUENCY (MHz)
Figure 100. AD9775/AD8345 Synthesizing a Three-Carrier
W-CDMA Signal at an LO of 800 MHz
02858-100
225Ω
IOUTA
AMPLITUDE (dBm)
500Ω
The AD9775 evaluation board includes an AD8345 and
recommended interface (Figure 104 and Figure 105). On the
output of the AD9775, R9 and R10 convert the DAC output
current to a voltage. R16 may be used to do a slight commonmode shift if necessary. The (now voltage) signal is applied to a
low-pass reconstruction filter to reject DAC images. The
components installed on the AD9775 provide a 35 MHz cutoff
but may be changed to fit the application. A balun (MiniCircuits ADTL1-12) is used to cross the ground plane boundary
to the AD8345. Another balun (Mini-Circuits ETC1-1-13) is
used to couple the LO input of the AD8345. The interface
requires a low ac impedance return path from the AD8345, so a
single connection between the AD9775 and AD8345 ground
planes is recommended.
AD9775
EVALUATION BOARD
The AD9775 evaluation board allows easy configuration of the
various modes, programmable via the SPI port. Software is
available for programming the SPI port from PCs running
Windows® 95, Windows 98, or Windows NT®/2000. The
evaluation board also contains an AD8345 quadrature
modulator and support circuitry that allows the user to
optimally configure the AD9775 in an image reject transmit
signal chain.
Figure 101 to Figure 104 show how to configure the evaluation
board in the one-port and two-port input modes with the PLL
enabled and disabled. Refer to Figure 105 to Figure 114, the
schematics, and the layout for the AD9775 evaluation board for
the jumper locations described in the DAC Single-Ended
Outputs section. The AD9775 outputs can be configured for
various applications by referring to the following instructions.
DAC Differential Outputs
Transformers T2 and T3 should be in place. Note that the lower
band of operation for these transformers is 300 kHz to 500 kHz.
Jumper 4, Jumper 8, Jumper 13 to Jumper 17, and Jumper 28 to
Jumper 30 should remain unsoldered. The outputs are taken
from S3 and S4.
Using the AD8345
Remove Transformers T2 and T3. Jumper JP4 and Jumper 28 to
Jumper 30 should remain unsoldered. Jumper 13 to Jumper 16
should be soldered. The desired components for the low-pass
interface filter L6, L7, C55, and C81 should be in place. The LO
drive is connected to the AD8345 via J10 and the balun T4, and
the AD8345 output is taken from J9.
DAC Single-Ended Outputs
Remove Transformers T2 and T3. Solder jumper links JP4 or JP28
to look at the DAC1 outputs. Solder jumper links JP29 or JP30 to
look at the DAC2 outputs. Jumper 8 and Jumper 13 to Jumper 17
should remain unsoldered. Jumper JP35 to Jumper JP38 can be
used to ground one of the DAC outputs while the other is
measured single ended. Optimum single-ended distortion
performance is typically achieved in this manner. The outputs
are taken from S3 and S4.
Rev. E | Page 44 of 56
AD9775
LECROY
TRIG
PULSE
INP
GENERATOR
SIGNAL GENERATOR
DATACLK
INPUT CLOCK
AWG2021
OR
DG2020
CLK+/CLK–
40-PIN RIBBON CABLE
DAC1, DB13–DB0
DAC2, DB13–DB0
AD9775
JUMPER CONFIGURATION FOR TWO-PORT MODE PLL ON
SOLDERED/IN
×
UNSOLDERED/OUT
×
×
×
×
×
×
×
×
×
×
×
×
NOTES
1. TO USE PECL CLOCK DRIVER, SOLDER JP41 AND JP42 AND REMOVE TRANSFORMER T1.
2. IN TWO-PORT MODE, IF DATACLK/PLL_LOCK IS PROGRAMMED TO OUTPUT PIN 8, JP25
AND JP39 SHOULD BE SOLDERED. IF DATACLK/PLL_LOCK IS PROGRAMMED TO OUTPUT
PIN 53, JP46 AND JP47 SHOULD BE SOLDERED. SEE THE TWO-PORT DATA INPUT MODE
FOR MORE INFORMATION.
02858-101
JP1 –
JP2 –
JP3 –
JP5 –
JP6 –
JP12 –
JP24 –
JP25 –
JP26 –
JP27 –
JP31 –
JP32 –
JP33 –
Figure 101. Test Configuration for AD9775 in Two-Port Mode with PLL Enabled, Signal Generator Frequency = Input Data Rate,
DAC Output Data Rate = Signal Generator Frequency × Interpolation Rate
LECROY
TRIG
PULSE
INP
GENERATOR
SIGNAL GENERATOR
ONEPORTCLK
INPUT CLOCK
AWG2021
OR
DG2020
CLK+/CLK–
DAC1, DB13–DB0
DAC2, DB13–DB0
AD9775
JUMPER CONFIGURATION FOR ONE-PORT MODE PLL ON
SOLDERED/IN
×
UNSOLDERED/OUT
×
×
×
×
×
×
×
×
×
×
×
×
NOTES
1. TO USE PECL CLOCK DRIVER, SOLDER JP41 AND JP42 AND REMOVE TRANSFORMER T1.
02858-102
JP1 –
JP2 –
JP3 –
JP5 –
JP6 –
JP12 –
JP24 –
JP25 –
JP26 –
JP27 –
JP31 –
JP32 –
JP33 –
Figure 102. Test Configuration for AD9775 in One-Port Mode with PLL Enabled, Signal Generator Frequency = One-Half Interleaved Input Data Rate,
ONEPORTCLK = Interleaved Input Data Rate, DAC Output Data Rate = Signal Generator Frequency × Interpolation Rate
Rev. E | Page 45 of 56
AD9775
LECROY
TRIG
PULSE
INP
GENERATOR
SIGNAL GENERATOR
DATACLK
INPUT CLOCK
AWG2021
OR
DG2020
CLK+/CLK–
40-PIN RIBBON CABLE
DAC1, DB13–DB0
DAC2, DB13–DB0
AD9775
JUMPER CONFIGURATION FOR TWO-PORT MODE PLL OFF
SOLDERED/IN
×
UNSOLDERED/OUT
×
×
×
×
×
×
×
×
×
×
×
×
NOTES
1. TO USE PECL CLOCK DRIVER, SOLDER JP41 AND JP42 AND REMOVE TRANSFORMER T1.
2. IN TWO-PORT MODE, IF DATACLK/PLL_LOCK IS PROGRAMMED TO OUTPUT PIN 8, JP25
AND JP39 SHOULD BE SOLDERED. IF DATACLK/PLL_LOCK IS PROGRAMMED TO OUTPUT
PIN 53, JP46 AND JP47 SHOULD BE SOLDERED. SEE THE TWO-PORT DATA INPUT MODE
FOR MORE INFORMATION.
02858-103
JP1 –
JP2 –
JP3 –
JP5 –
JP6 –
JP12 –
JP24 –
JP25 –
JP26 –
JP27 –
JP31 –
JP32 –
JP33 –
Figure 103. Test Configuration for AD9775 in Two-Port Mode with PLL Disabled, DAC Output Data Rate = Signal Generator Frequency,
DATACLK = Signal Generator Frequency/Interpolation Rate
LECROY
TRIG
PULSE
INP
GENERATOR
SIGNAL GENERATOR
ONEPORTCLK
INPUT CLOCK
AWG2021
OR
DG2020
CLK+/CLK–
DAC1, DB13–DB0
DAC2, DB13–DB0
AD9775
JUMPER CONFIGURATION FOR ONE-PORT MODE PLL OFF
SOLDERED/IN
×
UNSOLDERED/OUT
×
×
×
×
×
×
×
×
×
×
×
×
NOTES
1. TO USE PECL CLOCK DRIVER, SOLDER JP41 AND JP42 AND REMOVE TRANSFORMER T1.
02858-104
JP1 –
JP2 –
JP3 –
JP5 –
JP6 –
JP12 –
JP24 –
JP25 –
JP26 –
JP27 –
JP31 –
JP32 –
JP33 –
Figure 104. Test Configuration for AD9775 in One-Port Mode with PLL Disabled, DAC Output Data Rate = Signal Generator Frequency,
ONEPORTCLK = Interleaved Input Data Rate = 2× Signal Generator Frequency/Interpolation Rate
Rev. E | Page 46 of 56
Figure 105. AD8345 Circuitry on AD9775 Evaluation Board
O1P
O1N
2
+ C72
10V
10μF
02858-105
BCASE
VDDM
O2P
C54
DNP
CC0603
LC0805
CC0805
C78
0.1μF
C75
0.1μF
C73
L5 DNP
DNP
CC0805
LC0805
L4
DNP
C35
100pF CC0603
L7
DNP
LC0805
C81
DNP
1
3
P
1
T6
S
6
4
2
2
1
11 10
AD8345
3
4
RC0603
R36
51Ω
1
C77
100pF
CC0603
RC0603
7
8
P
CC0603
C80
DNP
T4
R37
DNP
RC0603
JP20
S
5
4
JP18
R26
1kΩ
VDDM
2
9
C76
100pF
3 ETC1-1-13
6
CC0603
R35
51Ω
5
U2
CC0603
C74
100pF
R34
DNP
R33
51Ω
12
4
T5
RC0603
JP19
CC0603
RC0603
RC0603
16 15 14 13
6
S
P
3
QBBP
IBBP
CC0805
QBBN
IBBN
LC0805
G1B
C55
DNP
LOIN
G2
O2N
G4B
G1A
C79
DNP
RC0603
ENBL
ADTL1-12
G4A
CC0603
VOUT
LOIP
G3
VPS1
VPS2
ADTL1-12
Rev. E | Page 47 of 56
CC0805
R32
51Ω
RC0603
L6
DNP
2
R30
DNP
2
2
J9
DGND2; 3, 4, 5
JP21
JP7
2
2
LOCAL OSC INPUT
R28 DGND2; 3, 4, 5
0Ω
J10
RC0603
RC0603
R23
0Ω
MODULATED OUTPUT
J7
J3
J6
J4
J5
J8
W12
W11
CGND
DCASE
CLKVDD_IN
AGND
DCASE
AVDD_IN
DGND
DCASE
DVDD_IN
DGND2
DCASE
VDDMIN
+ C63
16V
22μF
+ C64
16V
22μF
+ C65
16V
22μF
+ C28
16V
22μF
2
c
LC1210
L1
FERRITE
LC1210
L2
FERRITE
LC1210
L3
FERRITE
LC1210
L8
FERRITE
CC0805
CC0805
CC0805
CC0805
POWER INPUT FILTERS
DCASE
DCASE
C69
0.1μF
DCASE
JP11
C68
0.1μF
JP10
C67
0.1μF
JP9
C32
0.1μF
+ C62
16V
22μF
TP5
BLK
+ C61
16V
22μF
TP3
BLK
+ C66
16V
22μF
JP43
VDDM
JP44
TP7
BLK
TP6
RED
CLKVDD
TP4
RED
AVDD
TP2
RED
DVDD
JP45
AD9775
Figure 106. AD9775 Clock, Power Supplies, and Output Circuitry
2
3
JP12
CX2
CX1
02858-106
JP3
IQ
JP40
JP27
JP5
C29
0.1μF
JP25
RC0603
R39
1kΩ JP32
R5
49.9Ω
TP14
WHT
DVDD; 14
DGND; 7
11
DVDD; 14
DGND; 7
RC0603
R1
200Ω
DVDD
DVDD
DVDD
DVDD
c
+ C7
BCASE
10μF
6.3V
+ C8
10μF
6.3V
BCASE
+ C9
10μF
6.3V
BCASE
+ C10
10μF
6.3V
C42
0.1μF
CC0603
0.001μF
CC0603
C23
0.001μF
CC0603
C24
0.001μF
CC0603
C25
0.001μF
CC0603
C26
CLKN
CLKP
0.1μF
C11
CC0603
0.1μF
C12
BCASE
BCASE
C1 +
10μF
6.3V
R38 10kΩ
JP26
BD14
74VCX86
JP31
12
11
U4 13
U3
RC0603
JP23
74VCX86 CX3
C45
0.01μF
OPCLK
JP34
AGND; 3, 4, 5
OPCLK
S5
IQ
S6
DGND; 3, 4, 5
OPCLK_3
BD15
13
12
JP24
JP39
T1
T1-1T
JP33
ADCLK
1
5
4
JP22
6
ACLKX c CGND; 3, 4, 5
S1
CLKIN
JP2
JP1
C13
0.1μF
CC0603
R40
DVDD
5kΩ
DGND; 3, 4, 5
DATACLK
S2
c
TP15
WHT
R3
1kΩ
BD11
BD10
BD09
BD08
BD13
BD12
AD03
AD02
AD01
AD00
AD09
AD08
AD07
AD06
AD05
AD04
AD10
AD13
AD12
AD11
AD15
AD14
c
CC0603
1pF
C27
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
CC0805
DVDD
AD9775+TSP
CC0805
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
0.1μF
C36
VDDC1
VDDA6
VSSA10
LF
VDDC2
VDDA5
VSSC1
VSSA9
VDDA4
CLKP
CLKN
VSSA8
VSSA7
VSSC2
DCLK-PLLL
IOUT1P
VSSD1
IOUT1N
VDDD1
VSSA6
VSSA5
P1D15
IOUT2P
P1D14
IOUT2N
P1D13
VSSA4
P1D12
VSSA3
P1D11
VDDA3
P1D10
VSSD2
VSSA2
VDDD2
U1 VDDA2
P1D9
VSSA1
VDDA1
P1D8
FSADJ1
P1D7
FSADJ2
P1D6
REFOUT
P1D5
P1D4
RESET
VSSD3
SP-CSB
SP-CLK
VDDD3
SP-SDI
P1D3
SP-SDO
P1D2
P1D1
VSSD6
VDDD6
P1D0
P2D0
P2D15-IQSEL
P2D14-OPCLK
P2D1
P2D2
P2D13
P2D3
P2D12
P2D4
VSSD4
VDDD4
P2D5
P2D11
VSSD5
VDDD5
P2D10
P2D9
P2D6
P2D7
P2D8
CC0603
CLKVDD
CC0603
0.1μF
CC0805
C37
CC0603
BD07
BD06
C22
0.001μF
CC0603
CC0805
0.1μF
CC0603
C16
TP8
WHT
C6 +
10μF
6.3V
C5 +
10μF
6.3V
BCASE
DVDD
BCASE
JP38
JP36
J35
J37
IQ
JP46
R7
R8
2kΩ
1kΩ
0.01% 0.01%
+ C3
10μF
6.3V
DVDD
BCASE
0.1μF
+ C2
10μF
6.3V
AVDD
0.1μF
C41
AVDD
BCASE
C15
C4 +
10μF
6.3V
TP9
WHT
0.1μF
0.1μF
BCASE
C14
C58
DNP
CC0603
C17
CC0603
CC0805
0.1μF
C40
C58
DNP
CC0603
C19
0.1μF
C39
R6 0.1μF
1kΩ
BD00
C21
BD01
CC0603
BD02 0.001μF
BD03
BD04
BD05
SPCSP
SPCLK
SPSDI
SPSDO
TP10
WHT
0.1μF
TP11
WHT
CC0805
C18
C59
DNP
C57
DNP
0.1μF
CC0603
C20
0.1μF
CC0805
C38
CC0603
CC0603
RC0603
RC0603
CC0605
Rev. E | Page 48 of 56
CC0805
RC1206
CC0603
R2
1kΩ
5
6
2
1
U4
9
10
RC0603
RC0603
74VCX86
R11
51kΩ
JP47
R17
10kΩ
O1N
O1P
O2N
O2P
AGND; 3, 4, 5
OUT 2
S4
R42
49.9kΩ
RC1206
AGND; 3, 4, 5
OUT1
S3
RC0603
SPSDO
RC0603
CC0603
R43
49.9kΩ
T1-1T
JP17
R12
C70
51kΩ
0.1μF
4
3
T3
JP30
DVDD; 14
DGND; 7
8
JP14
JP15
JP29
JP16
JP13
5
6
2
1
JP8
CC0603
R16
10kΩ
4
T1-1T
T2
JP28
JP4
RC0603
RC0603
C70
0.1μF
3
R9
51kΩ
R10
51kΩ
AD9775
Rev. E | Page 49 of 56
02858-107
13
15
17
19
21
23
25
27
29
31
33
35
37
39
14
16
18
20
22
24
26
28
30
32
34
36
38
40
RC1206
R15
220Ω
11
12
RIBBON
J1
9
10
5
6
7
3
4
8
1
2
DATA-A
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
RP1
1
RP1
2
RP1
3
RP1
4
RP1
5
RP1
6
RP1
7
RP1
8
RP2
1
RP2
2
RP2
3
RP2
4
RP2
5
RP2
6
RP2
7
RP2
8
22Ω
16
22Ω
15
22Ω
14
22Ω
13
22Ω
12
22Ω
11
22Ω
10
22Ω
9
22Ω
16
22Ω
15
22Ω
14
22Ω
13
22Ω
12
22Ω
11
22Ω
10
22Ω
9
RCOM
RP5
50Ω
10
1
R1 R2 R3 R4 R5 R6 R7 R8 R9
2
3
4
5
6
7
8
9
ADCLK
OPCLK
Figure 107. AD9775 Evaluation Board Input (A Channel) and Clock Buffer Circuitry
K
2
74LCX112
U7
15
CLR
CLK
J
Q 5
1
OPCLK_2
Q 6
2
U4
OPCLK_3
3
DVDD; 14
AGND; 7
74VCX86
11
J
K
14
CLR
CLK
74LCX112
U7
13
12
10
PRE
1
3
6
C52 +
4.7μF
6.3V
DVDD
C31 +
4.7μF
6.3V
DVDD
CX3
C30 +
4.7μF
6.3V
DVDD
AGND; 8
DVDD; 16
Q 7
Q 9
DVDD; 14
AGND; 7
74VCX86
U4
8
DVDD; 14
AGND; 7
PRE
5
4
U3
6
DVDD; 14
AGND; 7
74VCX86
U3
3
DVDD; 14
AGND; 7
74VCX86
U3
74VCX86
4
DVDD
RP8
DNP
AD00
AD01
AD02
AD03
AD04
AD05
AD06
9
10
5
4
2
1
AD07
CX2
CX1
AD08
AD09
AD10
AD11
AD12
AD13
AD14
AD15
RP7
10 DNP
R1 R2 R3 R4 R5 R6 R7 R8 R9
9 10 RP6
1 2 3 4 5 6 7 8 9 10
50Ω
RCOM
RCOM
R1 R2 R3 R4 R5 R6 R7 R8 R9
R1 R2 R3 R4 R5 R6 R7 R8 R9
1
1
RCOM
ACASE
ACASE
ACASE
C53
0.1μF
C34
0.1μF
C33
0.1μF
CC0805
CC0805
CC0805
AD9775
Rev. E | Page 50 of 56
02858-108
33
35
37
39
34
36
38
40
RIBBON
J2
31
32
23
24
29
21
22
30
19
20
27
17
18
28
15
16
25
13
14
26
11
7
8
12
5
6
9
3
4
10
1
2
DATA-B
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
RP4 22Ω
RP4 22Ω
RP4 22Ω
RP4 22Ω
RP4 22Ω
RP4 22Ω
RP4 22Ω
RP4 22Ω
RP3 22Ω
RP3 22Ω
RP3 22Ω
RP3 22Ω
RP3 22Ω
RP3 22Ω
RP3 22Ω
RP3 22Ω
9
10
11
12
13
14
15
16
9
10
11
12
13
14
15
2
3
4
5
6
7
8
9
BD00
BD01
BD02
BD03
BD04
BD05
BD06
BD07
BD08
BD09
BD10
BD11
BD12
BD13
BD14
BD15
RP9
10 DNP
R1 R2 R3 R4 R5 R6 R7 R8 R9
16
RCOM
RP12
10 50Ω
1
R1 R2 R3 R4 R5 R6 R7 R8 R9
Figure 108. AD9775 Evaluation Board Input (B Channel) and SPI Port Circuitry
ACASE
DVDD
SPSDO
SPSDI
SPCLK
SPCSB
+
C43
4.7μF CC805
6.3V
9 10 RP11
1 2 3 4 5 6 7 8 9 10
RP10
50Ω
RCOM
DNP
RCOM
R1 R2 R3 R4 R5 R6 R7 R8 R9
R1 R2 R3 R4 R5 R6 R7 R8 R9
1
1
RCOM
C50
0.1μF
2
c
U5
+ C49
4.7μF
6.3V
U5
U5
U5
10
U5
74AC14
8
U5
U6
12
DGND; 7
DVDD; 14
U6
U6
6
DGND; 7
74AC14 DVDD; 14
5
DGND; 7
74AC14 DVDD; 14
3
U6
U6
8
DGND; 7
74AC14 DVDD; 14
9
DGND; 7
74AC14 DVDD; 14
11
10
13
9
DGND; 7
DVDD; 14
11
DGND; 7
DVDD; 14
12
RC0805
ACASE
DVDD
+
RC0805
C44
4.7μF
6.3V
RC0805
R24
DNP RC0805
R22
DNP
JP41
JP42
RC0805
R20
DNP
R21
DNP RC0805
RC0805
R45
9kΩ
R48
9kΩ
R50
9kΩ
CLKVDD; 8
CGND; 5
4
2
DGND; 7
DVDD; 14 74AC14
5
CC805
C48
1nF
R19
100Ω
CC805
MC100EPT22
3
6 U8
4
R18
200Ω
RC0805
DGND; 7
74AC14
DVDD; 14
3
c
1
2
CGND; 5
CLKVDD; 8
U8
13
c
RC0805
MC100EPT22
c
C47
1nF
DGND; 7
74AC14 DVDD; 14
U6
C60
0.1μF
c
7
R13
120Ω
DGND; 7
DVDD; 14
1
CC805
RC0805
R4
120Ω
R14
200Ω
DGND; 7
74AC14 DVDD; 14
1
74AC14
6
74AC14
4
74AC14
ACASE
CLKDD
ACLKX
CC805
C46
0.1μF
RC0805
CLKVDD
CLKVDD
CLKN
CLKP
CLKVDD
CC805
6
5
4
3
2
C51
0.1μF
SPI PORT
P1
1
c
c
AD9775
02858-109
AD9775
02858-110
Figure 109. AD9775 Evaluation Board Components, Top Side
Figure 110. AD9775 Evaluation Board Components, Bottom Side
Rev. E | Page 51 of 56
02858-111
AD9775
02858-112
Figure 111. AD9775 Evaluation Board Layout, Layer One (Top)
Figure 112. AD9775 Evaluation Board Layout, Layer Two (Ground Plane)
Rev. E | Page 52 of 56
02858-113
AD9775
02858-114
Figure 113. AD9775 Evaluation Board Layout, Layer Three (Power Plane)
Figure 114. AD9775 Evaluation Board Layout, Layer Four (Bottom)
Rev. E | Page 53 of 56
AD9775
OUTLINE DIMENSIONS
14.20
14.00 SQ
13.80
0.75
0.60
0.45
1.20
MAX
12.20
12.00 SQ
11.80
80
61
61
1
60
80
1
60
PIN 1
EXPOSED
PAD
TOP VIEW
(PINS DOWN)
BOTTOM VIEW
0° MIN
1.05
1.00
0.95
0.15
0.05
SEATING
PLANE
6.00
BSC SQ
0.20
0.09
7°
3.5°
0°
0.08 MAX
COPLANARITY
(PINS UP)
20
41
40
21
VIEW A
41
20
21
40
0.50 BSC
LEAD PITCH
0.27
0.22
0.17
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-ADD-HD
Figure 115. 80-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]
(SV-80-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD9775BSV
AD9775BSVRL
AD9775BSVZ 1
AD9775BSVZRL1
AD9775-EB
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
80-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]
80-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]
80-Lead, Thin Quad Flat Package, Exposed Pad [TQFP_EP]
80-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]
Evaluation Board
Z = Pb-free part.
Rev. E | Page 54 of 56
Package Option
SV-80-1
SV-80-1
SV-80-1
SV-80-1
AD9775
NOTES
Rev. E | Page 55 of 56
AD9775
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C02858-0-12/06(E)
Rev. E | Page 56 of 56
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