ESS ES6128 Vibratto-s dvd processor product brief Datasheet

ES6128
Vibratto-S DVD Processor
Product Brief
ESS Technology, Inc.
DESCRIPTION
FEATURES
The ES6128 VibrattoS DVD processor is a super highperformance single-chip MPEG video decoding solution
that integrates a state-of-the-art progressive-scan video
feature to provide brilliant and sharp, flicker-free output to
the video display, built-in CPRM, and S/PDIF input and
output support. The ES6128 performs audio/video stream
data processing, TV encoding, Macrovision  copy
protection, DVD system navigation, system control, and
housekeeping functions.
• Single-chip DVD processor.
• Integrated NTSC/PAL encoder with pixel-adaptive
The Vibratto-S DVD processor is built on the ESS
proprietar y dual CPU Programmable Multimedia
Processor (PMP) core consisting of 32-bit RISC and 64-bit
DSP processors and offers the best DVD feature set. The
processing units enable simultaneous parallel execution of
system commands and data processing to perform
specialized encoding and decoding tasks.
The RISC processor performs bit stream parsing, control
audio data output, transfer video and audio data to the
vector engine and service system control and
housekeeping functions. The vector engine performs
audio and video micro-code processing required by A/V
standards, such as Dolby Digital, MPEG and JPEG
imaging. These processing tasks include video motion
compensation and estimation, loop filtering, Discrete
Cosine Transforms (DCT), inverse DCT, quantization, and
inverse quantization.
The Vibratto-S DVD processor supports both parallel and
serial DVD loader interfaces, industry standard I2S audio
data input and output, EPROM and DRAM access, and
audio/video data buffering. It also supports both letterbox
and pan-and-scan displays, sub-picture overlay, and OnScreen Display (OSD). In addition, the Vibratto-S DVD
solution plays Karaoke, CD+G, HDCD, CD-DA, MP3, and
WMA.
The ES6128 DVD processor is available in a 208-pin
Plastic Quad Flat Pack (PQFP) device package.
ESS Technology, Inc.
de-interlacer and five 10-bit 54 MHz video DACs.
• High-quality progressive scan video output for flicker-free
video display.
• DVD-Video, DVD-VR, VCD 1.1 and 2.0, and SVCD.
• Media playback with CD-ROM, CD-R/RW, DVD-R/RW,
DVD+R/RW, and DVD-RAM.
• Up to 7.1 channel audio outputs.
•
•
•
•
Interface for IDE devices, A/V DVD loaders.
Interface for CF, MS, SD, MMC, and SM memory cards.
Direct interface of 8-/16-bit DRAM up to 128-Mb capacity.
Direct interface for up to 4 banks of 8-/16-bit EPROM or
Flash EPROM for up to 4-MB for each bank.
• Macrovision 7.1 for NTSC/PAL interlaced video.
• Macrovision NTSC/PAL (480p/576p) progressive scan
video.
• Simultaneous composite, S-video, and YUV outputs.
• CCIR 656/601 YUV 4:2:2 input and output.
• On-Screen Display controller supports 256 colors in 8
degrees of transparency.
• Subpicture Unit (SPU) decoder supports karaoke lyric,
subtitles, and EIA-608 compliant Line 21 Captioning.
• SmartLogo for custom JPEG wallpaper.
• JPEG digital photo support (Kodak Picture CD and
Fujifilm FujiColor CD).
• ESS Music Slideshow™.
•
•
•
•
•
•
•
•
•
Bass management.
Dolby Digital (AC-3), Dolby Pro Logic™, and Pro Logic II.
DTS surround.
S/PDIF digital audio input and output.
MPEG AAC and Multichannel.
SRS TruSurround and TruSurround XT.
Windows™ Media Audio decoding.
Professional karaoke with full scoring scheme.
Lead-free leads using 98%-Sn/2%-Cu or 98%-Sn/2%-Bi
available with ES6128FF.
SAM0481B-052705
1
VEE
LA4
LA5
LA6
LA7
LA8
LA9
VSS
VCC
LA10
LA11
LA12
LA13
LA14
LA15
LA16
VSS
VEE
LA17
LA18
LA19
LA20
LA21
RESET#
TDMDX/RSEL
VSS
VEE
TDMDR
TDMCLK
TDMFS
TDMTSC#
TWS/SEL_PLL2
TSD0/SEL_PLL0
VSS
VCC
TSD1/SEL_PLL1
TSD2
TSD3
MCLK
TBCK
SEL_PLL3/SPDIF_OUT
SPDIF_IN
VSS
VCC
RSD
RWS
RBCK
CAMIN3/PIXIN3
XIN
XOUT
AVEE
AVSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
VSS
HA1/AUX4[3]
HA0/AUX4[2]
HCS3FX#/AUX3[6]
HCS1FX#/AUX3[7]
HIOCS16#/AUX3[4]/CAMCLK/PIXIN_CLK
HRD#/DCI_ACK#/AUX4[6]
HWR#/DCI_CLK/AUX4[5]
VEE
VSS
HIORDY/AUX3[3]
HRST#/AUX3[5]
HIRQ/DCI_ERR#/AUX4[7]
HRRQ#/AUX4[0]/CAMIN2/PIXIN2
HWRQ#/DCI_REQ#/AUX4[1]
HD15/AUX2[7]/IR
HD14/AUX2[6]
VCC
VSS
HD13/AUX2[5]/SP
HD12/AUX2[4]/C2PO
HD11/AUX2[3]//IRQ
HD10/AUX2[2]
HD9/AUX2[1]
HD8/DCI_FDS#/AUX2[0]/VFD_CLK
HD7/DCI7/AUX1[7]/VFD_DIN
VEE
VSS
HD6/DCI6/AUX1[6]/VFD_DOUT
HD5/DCI5/AUX1[5]
HD4/DCI4/AUX1[4]
HD3/DCI3/AUX1[3]
HD2/DCI2/AUX1[2]
HD1/DCI1/AUX1[1]
HD0/DCI0/AUX1[0]
VCC
VSS
HSYNC#/AUX3[0]/CAMIN7/PIXIN7
VSYNC#/AUX3[1]/CAMIN6/PIXIN6
PCLKQSCN/AUX3[2]/CAMIN5/PIXIN5
PCLK2XSCN/CAMIN4/PIXIN4
FDAC/YUV7/PIXOUT7
VDAC/YUV6/PIXOUT6
YDAC/YUV5/PIXOUT5
ADVSS
ADVEE
RSET/YUV4/PIXOUT4
COMP/YUV3/PIXOUT3
CDAC/YUV2/PIXOUT2
VREF/YUV1/PIXOUT1
UDAC/YUV0/PIXOUT0
DCLK
ES6128 PRODUCT BRIEF
ES6128 PINOUT DIAGRAM
ES6128 PINOUT DIAGRAM
The device pinout for the ES6128 is shown in Figure 1.
VEE
HA2/AUX4[4]
VEE
I2CDATA/AUX0
I2C_CLK/AUX1
AUX2/IOW#
VSS
VEE
AUX3/IOR#
AUX4
AUX5
AUX6
AUX7
LOE#
VSS
VCC
LCS0#/PIXOUT_CLK
LCS1#
LCS2#
LCS3#
VSS
LD0
LD1
LD2
LD3
LD4
VEE
VSS
LD5
LD6
LD7
LD8
LD9
LD10
LD11
VSS
VEE
LD12
LD13
LD14
LD15
LWRLL#
LWRHL#
VSS
VEE
CAMIN0/PIXIN0
CAMIN1/PIXIN1
LA0
LA1
LA2
LA3
VSS
2
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
SAM0481B-052705
ES6128
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
VEE
VSS
DSCK
DQM
DCS0#
VEE
VSS
DCS1#
DB15
DB14
DB13
DB12
VEE
VSS
DB11
DB10
DB9
DB8
DB7
DB6
VSS
VCC
DB5
DB4
DB3
DB2
DB1
DB0
VSS
VEE
DMBS1
DMBS0
DRAS#
DWE#
DOE#/DSCK_EN
DCAS#
VEE
VSS
DMA11
DMA10
DMA9
DMA8
DMA7
DMA6
VSS
VEE
DMA5
DMA4
DMA3
DMA2
DMA1
DMA0
Figure 1 ES6128 Device Pinout
ESS Technology, Inc.
ES6128 PRODUCT BRIEF
ES6128 PIN DESCRIPTION
ES6128 PIN DESCRIPTION
Table 1 lists the pin descriptions for the ES6128.
Table 1
ES6128 Pin Description
Name
Pin Numbers
I/O
1,18, 27, 59, 68, 75,
92, 99, 104, 130,
148, 157, 159, 164,
183, 193, 201
P
I/O power supply.
2-7, 10-16, 19-23,
204-207
O
RISC port address bus.
8, 17, 26, 34, 43,
60, 67, 76, 84, 91,
98, 103, 120, 129,
138, 147, 156, 163,
171, 177, 184, 192,
200, 208
G
Ground.
9, 35, 44, 83, 121,
139, 172
P
Core power supply.
24
I
Reset input; (5V tolerant input).
TDMDX
O
TDM transmit data output.
RSEL
I
LCS3 ROM Boot Data Width Select. Strapped to VCC or ground via 4.7-kΩ
resistor; read only during reset.
VEE
LA[21:0]
VSS
VCC
RESET#
Definition
RSEL
25
Selection
0
16-bit ROM
1
8-bit ROM
TDMDR
28
I
TDM receive data input; (5V tolerant input).
TDMCLK
29
I
TDM clock input; (5V tolerant input).
TDMFS
30
I
TDM frame sync input; (5V tolerant input).
TDMTSC#
31
O
TDM output enable.
TWS
O
Audio transmit frame sync output.
SEL_PLL2
I
System and DSCK output clock frequency selection is made at the rising edge of
RESET#. The matrix below lists the available clock frequencies and their
respective PLL bit settings. Strapped to VCC or ground via 4.7-kΩ resistor; read
only during reset.
SEL_PLL2
32
TSD0
SEL_PLL1
SEL_PLL0
PLL Settings
0
0
0
DCLK × 4.5
0
0
1
DCLK × 5.0
0
1
0
Bypass
0
1
1
DCLK × 4.0
1
0
0
DCLK × 4.25
1
0
1
DCLK × 4.75
1
1
0
DCLK × 5.5
1
1
1
DCLK × 6.0
O
Audio transmit serial data output 0.
I
Refer to the description and matrix for SEL_PLL2 pin 32.
33
SEL_PLL0
ESS Technology, Inc.
SAM0481B-052705
3
ES6128 PRODUCT BRIEF
ES6128 PIN DESCRIPTION
Table 1
ES6128 Pin Description (Continued)
Name
Pin Numbers
TSD1
I/O
Definition
O
Audio transmit serial data output 1.
I
Refer to the description and matrix for SEL_PLL2 pin 32.
36
SEL_PLL1
TSD2
37
O
Audio transmit serial data output 2. This pin must be pulled down to VSS via a
4.7-kΩ resistor for proper operation.
TSD3
38
O
Audio transmit serial data output 3.
MCLK
39
I/O
Audio master clock for audio DAC.
TBCK
40
I/O
Audio transmit bit clock. TBCK is an input during reset and subsequently is
programmed as an output via the AUDIOXMT register (addr 0x2000D00Ch, bit 4).
I
Clock source select. Strapped to VCC or ground via 4.7-kΩ resistor; read only
during reset.
SEL_PLL3
SEL_PLL3
41
SPDIF_OUT
Clock Source
0
Crystal oscillator
1
DCLK input
O
S/PDIF output.
SPDIF_IN
42
I
S/PDIF input; (5V tolerant input).
RSD
45
I
Audio receive serial data; (5V tolerant input).
RWS
46
I
Audio receive frame sync; (5V tolerant input).
RBCK
47
I
Audio receive bit clock; (5V tolerant input).
I
Camera YUV 3.
I
CCIR656 input pixel 3.
CAMIN3
48
PIXIN3
XIN
49
I
27-MHz crystal input.
XOUT
50
O
27-MHz crystal output.
AVEE
51
P
Analog power for PLL.
AVSS
52
G
Analog ground for PLL.
53-58, 61-66
O
DRAM address bus.
69
O
DRAM column address strobe.
O
DRAM output enable.
O
DRAM clock enable.
DMA[11:0]
DCAS#
DOE#
70
DSCK_EN
DWE#
71
O
DRAM write enable.
DRAS#
72
O
DRAM row address strobe.
DMBS0
73
O
DRAM bank select 0.
DMBS1
74
O
DRAM bank select 1.
DB[15:0]
77-82, 85-90, 93-96
I/O
DRAM data bus.
97,100
O
DRAM chip select.
DQM
101
O
Data input/output mask.
DSCK
102
O
Output clock to DRAM.
DCLK
105
I
Clock input to PLL; (5V tolerant input).
DCS[1:0]#
4
SAM0481B-052705
ESS Technology, Inc.
ES6128 PRODUCT BRIEF
ES6128 PIN DESCRIPTION
Table 1
ES6128 Pin Description (Continued)
Name
Pin Numbers
UDAC
I/O
Definition
O
Video DAC output.
106
Value
F DAC
(pin 115)
V DAC
(pin 114)
Y DAC
C DAC
U DAC
(pin 113) (pin 108) (pin 106)
0
CVBS/Chroma
CVBS1
Y
C
N/A
1
CVBS/Chroma
CVBS1
Y
C
CVBS2
2
CVBS/Chroma
N/A
Y
C
N/A
3
CVBS/Chroma
CVBS1
N/A
N/A
CVBS2
4
CVBS/Chroma
CVBS1
N/A
N/A
N/A
5
CVBS/Chroma
CVBS1
Y
Pb
Pr
6
CVBS/Chroma
N/A
Y
Pb
Pr
7
N/A
SYNC
G
B
R
8
CVBS/Chroma
Chroma
Y
Pb
Pr
9
CVBS
CVBS1
G
B
R
10
CVBS
CVBS1
G
R
B
11
N/A
SYNC
G
R
B
12
CVBS/Chroma
N/A
Y
Pr
Pb
13
CVBS/Chroma
CVBS1
Y
Pr
Pb
14
Chroma
Y
G
R
B
F: CVBS/chroma signal for simultaneous mode.
Y: Luma component for YUV and Y/C processing.
C: Chrominance signal for Y/C processing.
U: Chrominance component signal for YUV mode.
V: Chrominance component signal for YUV mode.
YUV0
O
YUV pixel 0 output data.
PIXOUT0
O
CCIR656 output pixel 0.
VREF
I
Internal voltage reference to video DAC. Bypass to ground with 0.1-µF capacitor.
O
YUV pixel 1 output data.
PIXOUT1
O
CCIR656 output pixel 1.
CDAC
O
Video DAC output. Refer to description and matrix for UDAC pin 106.
O
YUV pixel 2 output data.
PIXOUT2
O
CCIR656 output pixel 2.
COMP
I
Compensation input. Bypass to ADVEE with 0.1-µF capacitor.
O
YUV pixel 3 output data.
PIXOUT3
O
CCIR656 output pixel 3.
RSET
I
DAC current adjustment resistor input.
O
YUV pixel 4 output data.
O
CCIR656 output pixel 4.
P
Analog power for video DAC.
YUV1
YUV2
YUV3
YUV4
107
108
109
110
PIXOUT4
ADVEE
ESS Technology, Inc.
111
SAM0481B-052705
5
ES6128 PRODUCT BRIEF
ES6128 PIN DESCRIPTION
Table 1
ES6128 Pin Description (Continued)
Name
Pin Numbers
I/O
Definition
112
G
Analog ground for video DAC.
O
Video DAC output. Refer to description and matrix for UDAC pin 106.
O
YUV pixel 5 output data
PIXOUT5
O
CCIR656 output pixel 5.
VDAC
O
Video DAC output. Refer to description and matrix for UDAC pin 106.
O
YUV pixel 6 output data.
PIXOUT6
O
CCIR656 output pixel 6.
FDAC
O
Video DAC output. Refer to description and matrix for UDAC pin 106.
O
YUV pixel 7 output data.
PIXOUT7
O
CCIR656 output pixel 7.
PCLK2XSCN
I/O
27-MHz video output pixel clock.
ADVSS
YDAC
YUV5
113
YUV6
114
YUV7
CAMIN4
115
116
I
Camera YUV 4.
PIXIN4
I
CCIR656 input pixel 4.
PCLKQSCN
O
13.5-MHz video output pixel clock.
I/O
Aux3 data I/O; (5V tolerant input).
AUX3[2]
117
CAMIN5
I
Camera YUV 5.
PIXIN5
I
CCIR656 input pixel 5.
VSYNC#
AUX3[1]
I/O
Vertical sync; (5V tolerant input).
I/O
Aux3 data I/O; (5V tolerant input).
118
CAMIN6
I
Camera YUV 6.
PIXIN6
I
CCIR656 input pixel 6.
HSYNC#
AUX3[0]
I/O
Horizontal sync; (5V tolerant input).
I/O
Aux3 data I/O; (5V tolerant input).
119
CAMIN7
I
Camera YUV 7.
PIXIN7
I
CCIR656 input pixel 7.
HD[5:0]
I/O
Host data bus lines; (5V tolerant input).
I/O
DVD channel data I/O; (5V tolerant input).
AUX1[5:0]
I/O
Aux1 data I/O; (5V tolerant input).
HD6
I/O
Host data bus line; (5V tolerant input).
I/O
DVD channel data I/O; (5V tolerant input).
I/O
Aux1 data I/O; (5V tolerant input).
DCI[5:0]
122-127
DCI6
128
AUX1[6]
VFD_DOUT
I
HD7
VFD data output.
I/O
Host data bus line; (5V tolerant input).
I/O
DVD channel data I/O; (5V tolerant input).
AUX1[7]
I/O
Aux1 data I/O; (5V tolerant input).
VFD_DIN
I
DCI7
131
6
SAM0481B-052705
VFD data input.
ESS Technology, Inc.
ES6128 PRODUCT BRIEF
ES6128 PIN DESCRIPTION
Table 1
ES6128 Pin Description (Continued)
Name
Pin Numbers
HD8
DCI_FDS#
I/O
Definition
I/O
Host data bus line; (5V tolerant input).
I/O
DVD input sector start; (5V tolerant input).
I/O
Aux2 data I/O; (5V tolerant input).
132
AUX2[0]
VFD_CLK
I
HD9
VFD clock input.
I/O
Host data bus line; (5V tolerant input).
I/O
Aux2 data I/O; (5V tolerant input).
I/O
Host data bus line; (5V tolerant input).
AUX2[2]
I/O
Aux2 data I/O; (5V tolerant input).
HD11
I/O
Host data bus line; (5V tolerant input).
I/O
Aux2 data I/O; (5V tolerant input).
IRQ
O
IRQ.
HD12
I/O
Host data bus line; (5V tolerant input).
I/O
Aux2 data I/O; (5V tolerant input).
133
AUX2[1]
HD10
134
AUX2[3]
AUX2[4]
135
136
C2PO
I
HD13
I/O
Host data bus line; (5V tolerant input).
I/O
Aux2 data I/O; (5V tolerant input).
AUX2[5]
137
SP
I
HD14
C2PO error correction flag from CD-ROM; (5V tolerant input).
16550 UART serial port input.
I/O
Host data bus line; (5V tolerant input).
AUX2[6]
I/O
Aux2 data I/O; (5V tolerant input).
HD15
I/O
Host data bus line; (5V tolerant input).
I/O
Aux2 data I/O; (5V tolerant input).
140
AUX2[7]
141
IR
I
IR remote control input; (5V tolerant input).
HWRQ#
O
Host write request.
O
DVD control interface request.
AUX4[1]
I/O
Aux4 data I/O; (5V tolerant input).
HRRQ#
O
Host read request.
I/O
Aux4 data I/O; (5V tolerant input).
DCI_REQ#
142
AUX4[0]
143
CAMIN2
I
Camera YUV 2.
PIXIN2
I
CCIR656 input pixel 2.
HIRQ
DCI_ERR#
144
AUX4[7]
HRST#
I/O
Host interrupt.
I/O
DVD channel data error; (5V tolerant input).
I/O
Aux4 data I/O; (5V tolerant input).
O
Host reset.
I/O
Aux3 data I/O; (5V tolerant input).
145
AUX3[5]
HIORDY
I
Host I/O ready.
146
AUX3[3]
ESS Technology, Inc.
I/O
Aux3 data I/O; (5V tolerant input).
SAM0481B-052705
7
ES6128 PRODUCT BRIEF
ES6128 PIN DESCRIPTION
Table 1
ES6128 Pin Description (Continued)
Name
Pin Numbers
I/O
Definition
I/O
Host write.
I/O
DVD channel data clock; (5V tolerant input).
AUX4[5]
I/O
Aux4 data I/O; (5V tolerant input).
HRD#
O
Host read.
I/O
DVD channel data valid; (5V tolerant input).
I/O
Aux4 data I/O; (5V tolerant input).
HWR#
DCI_CLK
149
DCI_ACK#
150
AUX4[6]
HIOCS16#
I
AUX3[4]
I/O
Device 16-bit data transfer.
Aux3 data I/O; (5V tolerant input).
151
CAMCLK
I
Camera port pixel clock input.
PIXIN_CLK
I
CCIR656 input pixel clock.
O
Host select 1.
I/O
Aux3 data I/O; (5V tolerant input).
O
Host select 3.
I/O
Aux3 data I/O; (5V tolerant input).
I/O
Host address bus.
I/O
Aux4 data I/Os; (5V tolerant input).
I/O
Auxiliary port 0 (open collector); (5V tolerant input).
I/O
I2C data I/O; (5V tolerant input).
I/O
Auxiliary port 1 (open collector); (5V tolerant input).
I/O
I2C clock I/O; (5V tolerant input).
I/O
Auxiliary port; (5V tolerant input).
O
I/O write strobe (LCS1).
I/O
Auxiliary port; (5V tolerant input).
O
I/O read strobe (LCS1).
166-169
I/O
Auxiliary ports; (5V tolerant input).
170
O
RISC port output enable.
O
RISC port chip select 0.
O
CCIR656 output pixel clock.
174-176
O
RISC port chip select [3:1].
LD[15:0]
178-182, 185-191,
194-197
I/O
RISC port data bus; (5V tolerant input).
LWRLL#
198
O
RISC port low-byte write enable.
LWRHL#
199
O
RISC port high-byte write enable.
I
Camera YUV 0.
I
CCIR656 input pixel 0.
I
Camera YUV 1.
I
CCIR656 input pixel 1.
HCS1FX#
152
AUX3[7]
HCS3FX#
153
AUX3[6]
HA[2:0]
154, 155, 158
AUX4[4:2]
AUX0
160
I2CDATA
AUX1
161
I2C_CLK
AUX2
162
IOW#
AUX3
165
IOR#
AUX4-7
LOE#
LCS0#
173
PIXOUT_CLK
LCS[3:1]#
CAMIN0
202
PIXIN0
CAMIN1
203
PIXIN1
8
SAM0481B-052705
ESS Technology, Inc.
ES6128 PRODUCT BRIEF
SYSTEM BLOCK DIAGRAM
SYSTEM BLOCK DIAGRAM
A sample system block diagram for the ES6128 Vibratto-S DVD
player board design is shown in Figure 2.
Analog Video
Digital Video (CCIR656/601)
ROM/Flash
SDRAM
(4/16 MB)
Audio DAC
ES6128
Vibratto-S
EEPROM
S/PDIF
DVD Drive
TV Display
Digital Devices
Speakers
A/V Receiver
Audio ADC
Microphone In
VFD Driver
VFD Panel
IR Remote
Figure 2 ES6128 Vibratto-S System Block Diagram
FUNCTIONAL DESCRIPTION
Figure 3 shows the internal block diagram for the ES6128 Vibratto-S DVD processor.
GPIO
32-Bit
RISC
Processor
SRAM/ROM
Interface
16 K Cache
OSD
Display
Subpicture
Controller
TDM
Interface
TV-Encoder
CCIR656/601
Output Interface
Gateway
+
DCI
Interface
DVD
Descrambler
+
Transport
DMA
Controller
Huffman
Decoder
DRAM
Interface
Host
Interface
Video
Processor
CCIR656/601
Input Interface
ROM
Serial Audio
Interface
RAM
Figure 3 ES6128 Vibratto-S Block Diagram
ESS Technology, Inc.
SAM0481B-052705
9
ES6128 PRODUCT BRIEF
ORDERING INFORMATION
ORDERING INFORMATION
Part Number
Description
Package
ES6128F
Vibratto-S DVD, Progressive scan, and TV encoder
208-pin PQFP
ES6128FF
Vibratto-S DVD, Progressive scan, and TV encoder with lead-free leads
208-pin PQFP
The letter F at the end of the part number identifies the package type PQFP. The second letter F indicates lead-free leads with
the device.
Other Vibratto-S DVD Processors
Part Number
Description
Package
ES6168FA
Vibratto-S DVD, Progressive scan, MPEG-4, DVD-Audio, and TV encoder
208-pin PQFP
ES6168FAF
Vibratto-S DVD, Progressive scan, MPEG-4, DVD-Audio, and TV encoder with lead-free
leads
208-pin PQFP
ES6178F
Vibratto-S DVD, Progressive scan, DivX (certified), DVD-Audio, and TV encoder
208-pin PQFP
ES6178FF
Vibratto-S DVD, Progressive scan, DivX (certified), DVD-Audio, and TV encoder with
lead-free leads
208-pin PQFP
The letter F at the end of the part number identifies the package type PQFP. The second letter F indicates lead-free leads with
the device.
No part of this publication may be reproduced, stored in a retrieval
system, transmitted, or translated in any form or by any means,
electronic, mechanical, manual, optical, or otherwise, without the prior
written permission of ESS Technology, Inc.
ESS Technology, Inc.
48401 Fremont Blvd.
Fremont, CA 94538
Tel: (510) 492-1088
Fax: (510) 492-1898
10
http://www.esstech.com
ESS Technology, Inc. makes no representations or warranties
regarding the content of this document.
All specifications are subject to change without prior notice.
ESS Technology, Inc. assumes no responsibility for any errors
contained herein.
U.S. patents pending.
© 2005 ESS Technology, Inc.
MPEG is the Moving Picture Experts Group of the ISO/IEC. References
to MPEG in this document refer to the ISO/IEC JTC1 SC29 committee
draft ISO 11172 dated January 9, 1992.
Vibratto, SmartBright, SmartLogo, SmartColor, and Music Slideshow
are trademarks of ESS Technology, Inc.
Dolby is a trademark of Dolby Laboratories, Inc.
Trusurround, Trusurround XT, SRS, and (o) symbol are trademarks of
SRS Labs., Inc.
All other trademarks are trademarks of their respective companies and
are used for identification purposes only.
SAM0481B-052705