EL4543 ® Data Sheet January 5, 2007 Triple Differential Twisted-Pair Driver with Common-Mode Sync Encoding The EL4543 is a high bandwidth triple differential amplifier with integrated encoding of video sync signals. The inputs are suitable for handling high speed video or other communications signals in either single-ended or differential form, and the common-mode input range extends all the way to the negative rail enabling ground-referenced signalling in single supply applications. The high bandwidth enables differential signalling onto standard twisted-pair or coax with very low harmonic distortion, while internal feedback ensures balanced gain and phase at the outputs reducing radiated EMI and harmonics. Embedded logic encodes standard video horizontal and vertical sync signals onto the common mode of the twisted pair(s), transmitting this additional information without the requirement for additional buffers or transmission lines. The EL4543 enables significant system cost savings when compared with discrete line driver alternatives. The EL4543 is available in a 24 Ld QSOP package and is specified for operation over the -40°C to +85°C temperature range. TABLE 1. SYNC SIGNAL ENCODING H V COMMON MODE A (RED) COMMON MODE B (GREEN) COMMON MODE C (BLUE) Low High 3.0 2.0 2.5 Low Low 2.5 3.0 2.0 High Low 2.0 3.0 2.5 High High 2.5 2.0 3.0 TABLE 2. INPUT LOGIC THRESHOLD (+5V SUPPLY) VLO, max 0.8V VHI, min 2V FN7325.9 Features • Fully differential inputs, outputs, and feedback • 350MHz -3dB bandwidth • 1200V/µs slew rate • -75dB distortion at 5MHz • Single 5V to 12V operation • 50mA minimum output current • Low power - 36mA total typical supply current • Pb-free plus anneal available (RoHS compliant) Applications • Twisted-pair drivers • Differential line drivers • VGA over twisted-pair • Transmission of analog signals in a noisy environment Ordering Information PART NUMBER PART TAPE & MARKING REEL PACKAGE PKG. DWG. # EL4543IU EL4543IU - 24 Ld QSOP MDP0040 EL4543IU-T7 EL4543IU 7” 24 Ld QSOP MDP0040 EL4543IU-T13 EL4543IU 13” 24 Ld QSOP MDP0040 EL4543IUZ (See Note) EL4543IUZ - 24 Ld QSOP (Pb-free) MDP0040 EL4543IUZ-T7 (See Note) EL4543IUZ 7” 24 Ld QSOP (Pb-free) MDP0040 EL4543IUZ-T13 EL4543IUZ (See Note) 13” 24 Ld QSOP (Pb-free) MDP0040 EL4543IL 4543IL - 20 Ld 4x4 QFN* MDP0046 EL4543IL-T7 EL4543IL-T13 4543IL 7” 20 Ld 4x4 QFN* MDP0046 4543IL 13” 20 Ld 4x4 QFN* MDP0046 EL4543ILZ (See Note) 4543ILZ - 20 Ld 4x4 QFN* MDP0046 (Pb-free) EL4543ILZ-T7 (See Note) 4543ILZ 7” 20 Ld 4x4 QFN* MDP0046 (Pb-free) EL4543ILZ-T13 4543ILZ (See Note) 13” 20 Ld 4x4 QFN* MDP0046 (Pb-free) NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. *20 Ld 4x4 QFN, exposed pad 2.7 x 2.7mm 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2004-2007. All Rights Reserved. All other trademarks mentioned are the property of their respective owners. EL4543 Pinouts 20 VS- HSYNC 6 19 NC 18 VOUTB+ NC 7 VINB+ 8 + - 17 VOUTB16 NC VINB- 9 15 VOUTC+ NC 10 VINC+ 11 + - 16 VOUTA- 17 VOUTA+ HSYNC 2 14 VSTHERMAL PAD NC 3 13 NC VINB+ 4 12 VOUTB+ VINB- 5 11 VOUTBVOUTC+ 10 VSYNC 5 VOUTC- 9 21 VS+ 15 VS+ NC 8 NC 4 VSYNC 1 VINC- 7 22 NC VINA- 3 18 EN 23 VOUTA- VINC+ 6 VINA+ 2 + - 20 VINA- 24 VOUTA+ EN 1 19 VINA+ EL4543 (20 LD QFN) TOP VIEW EL4543 (24 LD QSOP) TOP VIEW 14 VOUTC13 NC VINC- 12 2 FN7325.9 January 5, 2007 EL4543 Absolute Maximum Ratings (TA = +25°C) Supply Voltage (VS+ & VS-). . . . . . . . . . . . . . . . . . . . . . . . . . . .+12V Maximum Output Continuous Current . . . . . . . . . . . . . . . . . . ±70mA Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +135°C Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C VIN+, VINB . . . . . . . . . . . . . . . VS- + 0.8V (min) to VS+ - 0.8V (max) VIN- - VINB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±5V CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications PARAMETER VS+ = +5V, VS- = 0V, TA = +25°C, VIN = 0V, RL = 150Ω, unless otherwise specified. DESCRIPTION CONDITIONS MIN TYP MAX UNIT AC PERFORMANCE BW (-3dB) -3dB Bandwidth VOUT = 2VP-P SR Differential Slew Rate RL = 200Ω TSTL 350 MHz 1000 V/µs Settling Time to 0.1% 13.6 ns GBW Gain Bandwidth Product 700 MHz HD2 2nd Harmonic Distortion f = 20MHz, RL = 200Ω -70 dBc HD3 3rd Harmonic Distortion f = 20MHz, RL = 200Ω -70 dBc dP Differential Phase @ 3.58MHz 0.01 ° dG Differential Gain @ 3.58MHz 0.01 % 600 INPUT CHARACTERISTICS VOS Input Referred Offset Voltage -10 2 10 mV IIN Input Bias Current (VIN+, VIN+) -30 -15 -10 µA ZIN Differential Input Impedance CIN Input Capacitance VDIFF Differential Input Range VCM Input Common Mode Voltage Range VN Input Referred Voltage Noise CMRR Input Common Mode Rejection Ratio EN Threshold Capacitance between any single input pin and the power supplies VS+ = +5V, VS- = 0V. See Figure 7 for higher supply voltages. VCM = 0 to 2V 180 kΩ 4 pF ±0.75 V 0 60 2.3 V 27 nV/√Hz 80 dB 1.4 V 60 mA 12 pF OUTPUT CHARACTERISTICS IOUT Output Peak Current COUT Output Capacitance (Disabled) 40 Capacitance between any single output pin and the power supplies when disabled DC PERFORMANCE AV Voltage Gain VIN = 0.8VP-P 1.82 1.96 2.05 V/V 12 V 16.2 mA SUPPLY CHARACTERISTICS VSUPPLY Supply Operating Range IS Power Supply Current (per Channel) PSRR Power Supply Rejection Ratio 3 VS+ to VS- 5 12.3 14.5 70 80 dB FN7325.9 January 5, 2007 EL4543 Pin Descriptions PIN NUMBER PIN NAME 1 EN PIN DESCRIPTION EQUIVALENT CIRCUIT Disables video inputs and outputs EN VSM CIRCUIT 1 2 VINA+ Non-inventing input 3 VINA- Inverting input 4, 7, 10, 13, 16, 19, 22 NC Not connected 5 VSYNC Vertical sync logic input SYNC VSM CIRCUIT 2 6 HSYNC Horizontal sync logic input 8 VINB+ Non-inverting input 9 VINB- Inverting input 11 VINC+ Non-inverting input 12 VINC- Inverting input 14 VOUTC- Inverting output 15 VOUTC+ Non-inverting output 17 VOUTB- Inverting output 18 VOUTB+ Non-inverting output 20 VS- Negative supply 21 VS+ Positive supply 23 VOUTA- Non-inverting output 24 VOUTA+ Inverting output 4 Reference Circuit 2 FN7325.9 January 5, 2007 EL4543 Typical Performance Curves -42 VOLTAGE (0.5V/DIV) BLUE CM OUT (CH C) GREEN CM OUT (CH B) VOLTAGE (2.5V/DIV) RED CM OUT (CH A) VSYNC BALANCE ERROR (dB) BALANCE ERROR= 20 LOG(ΔVO,CM/ΔVO,DIFF) -46 -50 -54 -58 -62 100K HSYNC 1M TIME (0.5ms/DIV) FIGURE 2. BALANCE ERROR 4 4 CL=0pF RL=200Ω RL=500Ω RL=200Ω 2 NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 100M FREQUENCY (Hz) FIGURE 1. COMMON MODE OUTPUT 0 RL=100Ω -2 RL=50Ω -4 -6 100k 1M 100M 10M 8.2pF 0 2.2pF -2 -4 -6 100k 1G NORMALIZED GAIN (dB) 2.2pF -2 -4 10M 100M 1G FREQUENCY RESPONSE (Hz) FIGURE 5. DIFFERENTIAL FREQUENCY RESPONSE FOR VARIOUS CL - DIFF 5 1G RL=200Ω 8.2pF 4.7pF 1M 100M 0 12pF 0 -6 100k 10M FIGURE 4. DIFFFERENTIAL FREQUENCY RESPONSE FOR VARIOUS CL - DIFF 4 2 1M FREQUENCY RESPONSE (Hz) FIGURE 3. DIFFERENTIAL FREQUENCY RESPONSE FOR VARIOUS RL - DIFF RL=100Ω CL=2.2pF 22pF 12pF 2 FREQUENCY RESPONSE (Hz) NORMALIZED GAIN (dB) 10M 20 40 60 80 100 100k 1M 10M 100M 1G FREQUENCY RESPONSE (Hz) FIGURE 6. CMRR FN7325.9 January 5, 2007 EL4543 Typical Performance Curves (Continued) 4 THRESHOLD (V) RELATIVE TO NEGATIVE SUPPLY 12 10 CMIR (V) 8 6 4 2 3.5 3 2.5 VSWITCH 2 1.5 1 0.5 0 0 5 6 7 8 9 10 11 12 5 6 7 SUPPLY VOLTAGE (V) 8 9 10 11 12 SUPPLY VOLTAGE (V) FIGURE 7. COMMON MODE INPUT RANGE vs SUPPLY VOLTAGE FIGURE 8. HSYNC & VSYNC THRESHOLD vs SUPPLY VOLTAGE 0 45 SUPPLY CURRENT (mA) 40 PSRR (dB) -20 -40 -60 -80 35 30 25 20 15 10 5 0 -100 0 100k 10k 10M 1M 100M RL = 200Ω 0 1 2 3 4 5 6 7 8 9 10 11 12 SUPPLY VOLTAGE (V) FREQUENCY (Hz) FIGURE 9. PSRR vs FREQUENCY FIGURE 10. ISUPPLY vs VSUPPLY 3 VOLTAGE (2V/DIV) ENABLE DISABLE PIN (V) 3.5 2.5 2 1.5 1 2.5V 212ns ENABLE OUTPUT SIGNAL 0.5 0 5 6 7 8 9 10 11 12 TIME (200ns/DIV) SUPPLY VOLTAGE (V) FIGURE 11. ENABLE DISABLE vs SUPPLY VOLTAGE 6 FIGURE 12. ENABLE RESPONSE FN7325.9 January 5, 2007 EL4543 Typical Performance Curves (Continued) RL=200Ω DIFF CL=0pF VOLTAGE (2V/DIV) 2.5V VOLTAGE (120mV/DIV) ENABLE 900ns OUTPUT SIGNAL RISE Δt=25ns FALL Δt=1.94ns TIME (200ns/DIV) TIME (20ns/DIV) FIGURE 13. DISABLE RESPONSE FIGURE 14. DIFFERENTIAL SMALL SIGNAL TRANSIENT RESPONSE 9 RISE Δt=2.81ns COMMON MODE DC LEVEL (V) VOLTAGE (235mV/DIV) RL=200Ω DIFF CL=0pF FALL Δt=2.31ns LOGIC HSYNC=0V 8 VSYNC=0V 7 N EE GR B CM ED -A R CM UE C BL C M- 6 5 4 3 2 1 0 5 TIME (20ns/DIV) 6 7 8 9 10 11 12 SUPPLY VOLTAGE (V) FIGURE 16. COMMON MODE DC LEVEL vs SUPPLY VOLTAGE 9 9 LOGIC HSYNC=0V 8 VSYNC=3V LOGIC HSYNC=3V 8 VSYNC=0V 7 COMMON MODE DC LEVEL (V) COMMON MODE DC LEVEL (V) FIGURE 15. DIFFERENTIAL LARGE SIGNAL TRANSIENT RESPONSE D RE -A CM L UE -C B CM EEN B GR C M- 6 5 4 3 2 1 7 N EE GR -B M C L UE -C B CM D A RE C M- 6 5 4 3 2 1 0 0 5 6 7 8 9 10 11 12 SUPPLY VOLTAGE (V) FIGURE 17. COMMON MODE DC LEVEL vs SUPPLY VOLTAGE 7 5 6 7 8 9 10 11 12 SUPPLY VOLTAGE (V) FIGURE 18. COMMON MODE DC LEVEL vs SUPPLY VOLTAGE FN7325.9 January 5, 2007 EL4543 Typical Performance Curves (Continued) 50 LOGIC HSYNC=3V 8 VSYNC=3V AV=+2 7 C 6 M- C OUTPUT IMPEDANCE (Ω) COMMON MODE DC LEVEL (V) 9 UE BL ED -A R CM N REE BG C M- 5 4 3 2 40 30 20 10 1 0 5 6 7 8 9 10 11 0 10k 12 100k FIGURE 19. COMMON MODE DC LEVEL vs SUPPLY VOLTAGE 100M FIGURE 20. OUTPUT IMPEDANCE 1M 0 RL=200Ω DIFF CHAN A, B, C 100k -20 CROSSTALK (dB) OUTPUT IMPEDANCE (Ω) 10M FREQUENCY (Hz) SUPPLY VOLTAGE (V) 10k 1k 100 -40 -60 -80 10 1 10k 100k 1M 10M -100 100k 100M 1M FREQUENCY (Hz) 10M 100M 400M FREQUENCY (Hz) FIGURE 21. OUTPUT IMPEDANCE [DISABLED] FIGURE 22. CHANNEL ISOLATION vs FREQUENCY 5 NORMALIZED GAIN (dB) 10k VOLTAGE NOISE (nV/√Hz), CURRENT NOISE (pA/√Hz) 1M 1k 100 10 1 5 6 7 8 9 10 12 FREQUENCY (Hz) FIGURE 23. INPUT VOLTAGE AND CURRENT NOISE 8 3 1 VOP-P=200mV -1 VOP-P=2V -3 -5 100k 1M 10M 100M 1G FREQUENCY (Hz) FIGURE 24. FREQUENCY RESPONSE vs OUTPUT AMPLITUDE FN7325.9 January 5, 2007 EL4543 Typical Performance Curves (Continued) FIGURE 25. GAIN vs FREQUENCY - 2 CHANNELS FIGURE 26. GAIN vs FREQUENCY - 2 CHANNELS FIGURE 27. GAIN vs FREQUENCY - 2 CHANNELS FIGURE 28. PHASE vs FREQUENCY - 2 CHANNELS FIGURE 29. PHASE vs FREQUENCY - 2 CHANNELS FIGURE 30. PHASE vs FREQUENCY - 2 CHANNELS 9 FN7325.9 January 5, 2007 EL4543 Typical Performance Curves (Continued) FIGURE 31. HARMONIC DISTORTION FIGURE 32. HARMONIC DISTORTION POWER DISSIPATION (W) 1.4 JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1.136W 1.2 1 θ JA = 0.8 0.6 Q SO P 88 24 °C /W 0.4 0.2 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (°C) FIGURE 34. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE FIGURE 33. HARMONIC DISTORTION JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 0.8 1.2 JEDEC JESD51-3 AND SEMI G42-88 (SINGLE LAYER) TEST BOARD POWER DISSIPATION (W) POWER DISSIPATION (W) 0.7 667mW 1 870mW 0.8 θ JA = 0.6 QS 11 0.4 OP 5° C/ 24 W 0.2 0.6 θ (4 Q m F JA m x N2 0 = 0.5 15 4m 0° C m) /W 0.4 0.3 0.2 0.1 0 0 25 75 85 100 50 125 150 AMBIENT TEMPERATURE (°C) FIGURE 35. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE 10 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (°C) FIGURE 36. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE FN7325.9 January 5, 2007 EL4543 Typical Performance Curves (Continued) JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD - QFN EXPOSED DIEPAD SOLDERED TO PCB PER JESD51-5 3 POWER DISSIPATION (W) 2.500W 2.5 2 θ (4 Q m F m N 2 =4 x 4 0 0 ° mm C /W ) JA 1.5 1 0.5 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (°C) FIGURE 37. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE Operational Description and Application Information differential output signals, decoded and transmitted along with the RGB video signals to the video monitor. The EL4543 is designed to differentially drive composite RGB video signals onto twisted pair lines, while simultaneously encoding horizontal and vertical sync signals as common mode output. The entire video signal plus sync can therefore be transmitted on 3 twisted pairs of wire. When utilizing CAT-5 cable, the 4th available twisted pair can be used for transmission of audio, data or control information. The distribution of composite video over standard CAT-5 cable enables enormous cost and labor savings compared with traditional coaxial cable, when considering both the relative low price and ease of pulling CAT-5 cable. ENABLE/DISABLE Introduction VSYNC HSYNC EN 11 EN + - + OUTA - VREF RCM LOGIC DECODING + INB - EN + - + OUTB - VREF GCM BCM Functional Description The EL4543 provides three fully differential high-speed amplifiers, suitable for driving high-resolution composite video signals onto twisted pair or standard coaxial cable. The input common-mode range extends to the negative rail, allowing simple ground-referenced input termination to be used with a single supply. The amplifiers provide a fixed gain of +2 to compensate for standard video cable termination schemes. Horizontal and Vertical sync signals (HSYNC and VSYNC) are passed to an internal Logic Encoding Block to encode the sync information as three discrete signals of different voltage levels. Generally, in differential amplifiers an external VREF pin is used to control the common mode level of the differential output; in the case of the EL4543 the VREF of each of the three internal amplifier channels receives a signal from the Logic Encoding Block with encoded HSYNC and VSYNC information. The final output consists of three fully differential video signals, with sync encoded on the common mode of each of the three RGB differential signals. HSYNC and VSYNC can easily be separated from the + INA - + INC - EN + - + OUTC - VREF FIGURE 38. BLOCK DIAGRAM EL4543 Sync Transmission The EL4543 encodes HSYNC and VSYNC signals on the common mode output of the differential video signals; Red, Green and Blue respectively. Data Sheet Figures 16, 17 and 18 clearly illustrate that the sum of the common mode voltages results in a fixed average DC level with no AC content and illustrates the logic levels. This eliminates EMI radiation into any common mode signal along the twisted pairs of CAT 5 cable. FN7325.9 January 5, 2007 EL4543 Extract Common Mode Sync and Decode HSYNC and VSYNC HSYNC and VSYNC can be regenerated from the Common Mode sync output voltages. The relationships between HSYNC, VSYNC and the 3 common mode levels are given by Table 1. The common mode levels are easily separated from the differential outputs of the EL4543 using this simple resistor network at the cable receiver input of each differential channel; see Figure 39. Twisted Pair Termination The schematic in Figure 39 illustrates a termination scheme for 50Ω series termination and a 100Ω twisted pair cable. Note RCM is the common mode termination to allow measurement of VCM and should not be too small since it loads the EL4543; a little over a 100Ω is recommended for RCM. TYPICAL EL4543 TERMINATION DRIVER 50Ω + - TWISTED PAIR + 50Ω VCM 50Ω ZO =100Ω 50Ω - VREF 120Ω (RCM: SHOULD BE >100Ω) (FOR LOADING CONSIDERATIONS) FIGURE 39. TWISTED PAIR TERMINATION EL4543 Video Transmission The EL4543 is a twisted pair differential line driver directed at the transmission of Video Signals through cables up to 100 feet; however, as signal losses increase with transmission line length the EL4543 will need additional support to equalize video signals along longer twisted pair transmission lines. A full solution to accomplish this is the SXGA Video Transmission System presented in the EL4543 Data Sheet. Note the inclusion of the EL9110 for signal equalization of up to 1000ft of CAT-5 cable and common mode extraction; see Data Sheet for additional information on the EL9110. Long Distance Video Transmission The SXGA Video Transmission System makes it possible to transmit Red, Green and Blue (RGB) video plus sync up to 1000 feet through CAT-5 cable. The input to the SXGA Video Transmission System is the output of a video source transmitting RGB video signals plus sync. The signals are received initially by the EL4543; which converts the single ended input RGB signals to three fully differential waveforms with sync encoded on the discrete common modes of each color channel and then drives the signals through a length of CAT-5 cable. The signal is received by the EL9110, which can provide 6-pole equalization for both high and low frequency signal transmission line losses. Then the EL9110 converts the differential RGB video signals back into single ended format while extracting the common mode component for decoding. The single ended RGB signal is taken directly from the output of the El9110 and is ready for the output device. The Common Mode Decoder Circuit receives the 12 common mode signals directly from each of the three EL9110's common mode output pin, decodes and transmits HSYNC and VSYNC to the output device. Sync Transmission The EL4543 encodes HSYNC and VSYNC signals onto the common mode output of the differential video signals; Red, Green and Blue respectively. Data Sheet Figure 8 clearly illustrates that the sum of the common mode voltages results in a fixed DC level with no AC content; thus eliminating EMI interference. Output Drive Protection The EL4543 has internal short circuit protection set typically at 60mA. if the output is shorted for extended periods of time the increased power dissipation will eventually destroy the part. To realize maximum reliability the output current should never exceed 60mA. The 50Ω series back load matching resistor provides additional protection. Supply Voltage While the EL4543 can be operated on ±5V split rails, single supply 0V to 5V is the most common usage. It is very important to note that the input logic thresholds are relative to the negative supply pin, and therefore single supply, ground referenced logic will not work when driving the EL4543 on split rails. The amplifiers have an input common mode range from 0V to 2.3V with a 0V to 5V supply, increasing with supply voltage (see Figure 7). The common mode output DC level range is a linear function of the power supply (see Figures 16, 17, 18, and 19). The common mode input switching threshold as well as the Enable/Disable input is a linear function of the supply voltage (see Figures 8 and 11). Disable and Power Down The EL4543 provides an enable disable function which powers down, logic input high, in 900ns and powers up, logic input low, in 212ns. Disabled the amplifiers supply current is reduced to 1.8mA (Positive Supply) and 0mA (Negative Supply). Note that Enable/Disable threshold is a linear function of the supply voltage levels. The Enable/Disable threshold voltage level is compatible with standard TTL/CMOS and referenced to the lowest supply potential. FN7325.9 January 5, 2007 EL4543 Proper Layout Technique A critical concern with any PCB layout is the establishment of a “healthy” ground plane. It is imperative to provide ground planes terminated close to inputs to minimize input capacitance. Additionally, the ground plane can be selectively removed from inputs to prevent load and supply currents from flowing near the input nodes. Having obtained the application's power dissipation, the maximum junction temperature can be calculated: T JMAX = T MAX + Θ JA × PD where: • TJMAX is the maximum junction temperature (125°C) In general the following guidelines apply to all PCB layout: • TMAX is the maximum ambient operating temperature • Keep all traces as short as possible. • PD is the power dissipation calculated above • Keep power supply bypass components as close to the chip as possible - extremely close. • θJA is the thermal resistance, junction to ambient, of the application (package + PCB combination). Refer to the Package Power Dissipation curves. • Create a healthy ground with low impedance and continuous ground pathways available to all grounded components board-wide. • In high frequency applications on multi-level boards try to keep one level of board with continuous ground plane and minimum via cutouts - providing it is affordable. • Provide extremely short loops from power pin to ground. • If it is affordable, a ferrite bead is always of benefit to isolate device from Power Supply noise and the rest of the circuit from the noise of the device. Power Dissipation Calculation When switching at high speeds, or driving heavy loads, the EL4543 drive capability is ultimately limited by the rise in die temperature brought about by internal power dissipation. For reliable operation die temperature must be kept below TJMAX (125°C). It is necessary to calculate the power dissipation for a given application prior to selecting package type. Power dissipation may be calculated: Application Circuit Video Transmission Along CAT-5 Cable VGA input RGB plus sync is connected with 75Ω termination to the inputs of the EL4543. Single-ended RGB video is converted to differential mode signals with HSYNC and VSYNC encoded on the common-mode of the three differential signals, respectively. The 50Ω output-terminated EL4543 drives the differential RGB with sync encoded common-mode to CAT-5 twisted pair cables. Note this system, without signal frequency equalization, will satisfactorily transmit along up to 200ft of CAT-5 twisted-pair. For longer cable lengths, frequency and gain equalization to compensate for signal degradation is recommended (EL9110) and a delay line technology (EL9115) to adjust for phase mismatch between signals at the receiving end. ΔV O⎞ ⎛ PD = 3 × ⎜ V S × I SMAX + V S × ------------⎟ R LD ⎠ ⎝ where: • VS is the total power supply to the EL4543 (from VS+ to VS-) • ISMAX = Maximum quiescent supply current per channel • ΔVO = Maximum differential output voltage of the application • RLD = Differential load resistance • ILOAD = Load current 13 FN7325.9 January 5, 2007 EL4543 RED EN 2 EL4543 QSOP 24 OUTA+ INA+ OUTA- INA- N.C. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 GREEN 4 N.C. VS+ 5 RVSYNC 1K 6 VSYNC VS- EL4543IU 3 HSYNC RHSYNC 1K 7 N.C. 8 22 9 10 INB- N.C. 11 BLUE N.C. OUTC+ INC+ 18 OUTC- INC- N.C. 8 VS+ 2 C34 0.1uf +VS R31 75 7 _ +VS 0.1uf C35 3 RJOUTB+ 49.9 6 _ 4 16 15 RED GREEN C35a 200pF EL8201IS BLUE U3 R30 2K R29 2K RJOUTB49.9 RJOUTC+ 49.9 HSYNC VSYNC Blue Out Differential 14 13 5 VS- Green Out Differential 17 RJC+ 75 12 RJOUTA49.9 19 RJB+ 75 INPUT 75 1 20 OUTB+ OUTB- R32 Red Out Differential 21 N.C. INB+ CAT2 RJOUTA+ 49.9 23 RJA+ 75 8 7 6 5 4 3 2 1 CAT1 1 1 2 3 4 5 6 7 8 EL4543 and EL9110 Sync Extraction RJOUTC49.9 OUTPUT UJ1 -VS +VS DIODE D9 DIODE D10 DIODE D11 DIODE D12 -VS +VS +VS -VS DIODE D1 DIODE D2 DIODE D3 DIODE D4 -VS -VS +VS DIODE D5 DIODE D6 C5 1uf -VS C17 0.1uf 5 R23 49.9 C24 51 C33 1uf R33 NL R29 NL C25 VGAN 1 2 3 4 5 6 7 8 Ctrl-ref Vctrl Vinp Vinm Vsm Cmout Vgain Logic-ref 1uf C30 5 16 15 14 13 12 11 10 9 Cmext Vsp Enbl Vspo Vout Vsmo 0V X2 0.1uf C31 0.1uf C32 INDUCTOR 6 51 R32 0.1uf R28 49.9 75 R25 RED NL R27 1K R31 +VS -VS C18 1uf Rred4 3000 R26 5 R25 R32 INDUCTOR3 C16 1uf 5 R12 NL C23 R26 49.9 EL9110 GREEN B R20 330 VGAN INDUCTOR 4 75 R24 51 R22 NL R18 R31 330 EL9110 0.1uf NL C14 16 15 14 13 12 11 10 9 Cmext Vsp Enbl Vspo Vout Vsmo 0V X2 C22 C13 R17 49.9 Ctrl-ref Vctrl Vinp Vinm Vsm Cmout Vgain Logic-ref Red In Differential 0.1uf C11 0.1uf 49.9 +VS GREEN 1 2 3 4 5 6 7 8 EL9110 51 R21 R29 INDUCTOR 1 C7 1uf NL R16 R30 1K VadjRed VCRTL 1uf 330 INDUCTOR 2 NL C12 R15 49.9 EL9110 BLUE C R9 330 C6 0.1uf VGAN 16 15 14 13 12 11 10 9 Cmext Vsp Enbl Vspo Vout Vsmo 0V X2 C10 51 R11 NL R4 NL C3 Ctrl-ref Vctrl Vinp Vinm Vsm Cmout Vgain Logic-ref 0.1uf C4 0.1uf 1uf C2 1 2 3 4 5 6 7 8 EL9110 51 R10 R5 R3 49.9 5 R14 BLUE NL R2 R6 1K C20 VCRTL Green InDifferential 1uf 75 R13 NL C1 R1 49.9 DIODE D8 R19 R8 C9 Blue In Differential 49.9 -VS DIODE D7 3000 R7 330 +VS C21 0.1uf VadjBlu 1uf VCRTL C15 +VS +VS EL9110 RED A R27 330 C27 0.1uf C26 1uf C19 0.1uf -VS INDUCTOR 5 5 C28 1uf R28 C29 0.1uf C8 0.1uf +VS +VS +VS +VS +VS NL = Not Loaded R33 3.6K Inductor =Ferrite 68 Ohms R34 3.6K BANANA JACK R35 3.6K GND BANANA JACK R36 R37 VadjBlue 1K Pot 1K Pot VGAN R38 1K Pot VCRTL -VS + C36 + C38 4.7uf +VS C37 4.7uf R39 3.6K 0.1uF C39 R40 1K Pot 0.1uF VadjRed -VS BANANA JACK 14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 FN7325.9 January 5, 2007 EL4543 EL4543/EL5375/EL8201 CAT-5 RGB + Sync Video Transmission System compensation network can be manipulated to provide some measure of cable prop delay skew compensation for slight differences in cable lengths between CAT-5 pairs. Cable skew can best be done around the 300 ft range by under compensating the shortest color pair (color on the left side of a vertical line) and over compensate the longest color pair (color on the right side of a vertical line). Around 450ft only the shortest color pair can be under compensated. Introducing a low cost turn-key system for transmitting component video over short to moderate CAT-5 cable lengths (1 to 500 feet) with selectable cable loss and skew compensation. Using only 3 of the 4 pairs in standard CAT-5 the 4th pair is available for audio, function control or data transmission; an additional benefit. The board for the driver and receiver should use strip lines or strip line waveguides for the inputs and outputs of the drivers and receivers. The 75Ω input and output strip lines waveguide on 0.06 inch epoxy board with ground back plain should be 0.016 inch wide with 0.01 inch space to ground area around them. The diff pair strip line waveguides should be two 0.045 inch 50Ω lines spaced 0.01 inch apart and spaced 0.01 inch to ground area around them. This is a general guide and size values may very for many reasons. RGB video plus sync (5 channels) is received at the VGA terminal and presented single ended to the EL4543. The EL4543 converts single ended RGB into fully differential signals on three twisted pairs. Sync is encoded on the three RGB differential signals as differential common mode and then drives the differential signals with encoded sync through CAT-5 cable. The common mode of the signals is extracted from the differential signals with a passive network of resistors and passed to the EL8201 for sync decoding. The differential signal is passed directly to the EL5375 where it is amplified, converted back into single ended format. Signal attenuation occurs in all transmission lines as a function of increasing cable length; this application system utilizes individual channel 2-pole compensation for cable lengths of 150, 300 and 500 feet. Additionally, the The receiver feedback and gain resistor network which goes directly to the minus input should be connected very close with minimal trace length and minimal capacitance to ground. The ground plane on the backside of the board, in back of these resistors and the minus input pin should be removed as well. Output +5V R34 Open R35 1 U2 REF1 NC INP1 FB1 24 R40 2K 0 2 3 R36 Open 499 2K 499 R28 R28 2K R24 R13 57 R25 Output +5V R12 57 R37 4 5 INN1 OUT1 NC NC REF2 VSP 23 R41 2K 22 R14 49.9 Output +5V R38 Open 499 R30 2K 2K R26 R21 1K R27 C2 0.1uF 499 R31 7 R39 8 9 20 11 Red In 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 24 OUTA+ INA- N.C. N.C. VS+ VSYNC VS- 22 5 R2 1K 6 7 HSYNC OUTB+ INB+ OUTB- C3 0.1uF C1 0.1uf 20 18 9 10 Blue In 11 R5 INB- N.C. N.C. OUTC+ INC+ OUTC- 16 R9 49.9 15 R10 49.9 INC- NC OUT3 R56 33K R44 2K R49 500 Compensation Control Switch On Off 1 12 2 11 3 10 4 9 5 8 6 7 R50 1K 15 14 150 Feet Comp R57 300 Feet Comp 10K C12 10p C11 36p R58 68K R59 C13 68p 3.9K C14 22p R60 33K SW DIP-6 13 R51 1K R46 2K R52 500 300 Feet Comp R61 3.9K C15 C16 68p 22p 150 Feet Comp R63 R62 33K C17 36p 10K C18 10p R64 68K R63 75 R65 75 75 R66 75 R18 55 R19 55 R67 75 C19 0.1uF 1 R20 49.9 14 N.C. 13 2 R11 49.9 C4 0.1uF R23 1K C4a 220pF VS+ 3 4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 OUTPUT 8 7 _ Output +5V 6 _ 5 VS- EL8201IS U3 Input -5V JB1 JB2 +VS In -VS In Csup1 4.7uF JP+ JUMPER + + JB3 C10 22p R64 EL4543IU Input +5V C21 ~4pF 16 R22 1K Blue Out Differential 75 12 FB3 3.9K 17 R8 49.9 17 R4 75 INPUT INN3 R55 C9 68p 19 N.C. N.C. EN C22 ~4pF Green Out Differential 8 OUT2 INP3 R45 2K R7 49.9 21 R3 1K Green In FB2 REF3 R17 49.9 Input +5V 4 NC 300 Feet Comp R54 68K R43 2K 18Output -5V EL5375 23 OUTA- NC 10K C6 0.1uF 19 R6 49.9 Red Out Differential INA+ INN2 150 Feet Comp C7 C8 36p 10p 499 3 EL4543 QSOP EN 12 499 R33 2 R16 57 R32 1 R1 75 VSN R48 1K R53 0 10 R15 57 INP2 R47 500 C5 0.1uF 0 6 C20 ~4pF 21 Output +5V Csup2 4.7uF Ground JUMPER JPJUMPER Output +5V JB4 2 2 1 1 2 1 GND Output -5V JB5 -VS Out + Csup3 4.7uF + +VS Out Csup4 4.7uF JB6 15 8 7 6 5 4 3 2 1 1 2 3 4 5 6 7 8 GND OUTPUT INPUT FN7325.9 January 5, 2007 EL4543 QFN (Quad Flat No-Lead) Package Family MDP0046 QFN (QUAD FLAT NO-LEAD) PACKAGE FAMILY (COMPLIANT TO JEDEC MO-220) A SYMBOL QFN44 QFN38 D N (N-1) (N-2) B 1 2 3 PIN #1 I.D. MARK E (N/2) 2X 0.075 C 2X 0.075 C N LEADS TOP VIEW QFN32 TOLERANCE NOTES A 0.90 0.90 0.90 0.90 ±0.10 - A1 0.02 0.02 0.02 0.02 +0.03/-0.02 - b 0.25 0.25 0.23 0.22 ±0.02 - c 0.20 0.20 0.20 0.20 Reference - D 7.00 5.00 8.00 5.00 D2 5.10 3.80 5.80 3.60/2.48 E 7.00 7.00 8.00 E2 5.10 5.80 5.80 4.60/3.40 e 0.50 0.50 0.80 L 0.55 0.40 0.53 Basic - Reference 8 6.00 Basic - Reference 8 0.50 Basic - 0.50 ±0.05 - N 44 38 32 32 Reference 4 ND 11 7 8 7 Reference 6 NE 11 12 8 9 Reference 5 0.10 M C A B (N-2) (N-1) N b L PIN #1 I.D. 3 1 2 3 (E2) (N/2) NE 5 7 (D2) BOTTOM VIEW 0.10 C e C SYMBOL QFN28 QFN24 QFN20 QFN16 TOLERANCE NOTES A 0.90 0.90 0.90 0.90 0.90 ±0.10 - A1 0.02 0.02 0.02 0.02 0.02 +0.03/ -0.02 - b 0.25 0.25 0.30 0.25 0.33 ±0.02 - c 0.20 0.20 0.20 0.20 0.20 Reference - D 4.00 4.00 5.00 4.00 4.00 Basic - D2 2.65 2.80 3.70 2.70 2.40 Reference - E 5.00 5.00 5.00 4.00 4.00 Basic - E2 3.65 3.80 3.70 2.70 2.40 Reference - e 0.50 0.50 0.65 0.50 0.65 Basic - L 0.40 0.40 0.40 0.40 0.60 ±0.05 - N 28 24 20 20 16 Reference 4 ND 6 5 5 5 4 Reference 6 NE 8 7 5 5 4 Reference 5 Rev 10 12/04 SEATING PLANE NOTES: 0.08 C N LEADS & EXPOSED PAD 1. Dimensioning and tolerancing per ASME Y14.5M-1994. SEE DETAIL “X” 2. Tiebar view shown is a non-functional feature. 3. Bottom-side pin #1 I.D. is a diepad chamfer as shown. SIDE VIEW 4. N is the total number of terminals on the device. 5. NE is the number of terminals on the “E” side of the package (or Y-direction). (c) C 2 6. ND is the number of terminals on the “D” side of the package (or X-direction). ND = (N/2)-NE. A (L) A1 N LEADS DETAIL X 16 7. Inward end of terminal may be square or circular in shape with radius (b/2) as shown. 8. If two values are listed, multiple exposed pad options are available. Refer to device-specific datasheet. FN7325.9 January 5, 2007 EL4543 Quarter Size Outline Plastic Packages Family (QSOP) MDP0040 A QUARTER SIZE OUTLINE PLASTIC PACKAGES FAMILY D (N/2)+1 N E SYMBOL QSOP16 QSOP24 QSOP28 TOLERANCE NOTES PIN #1 I.D. MARK E1 1 (N/2) A 0.068 0.068 0.068 Max. - A1 0.006 0.006 0.006 ±0.002 - A2 0.056 0.056 0.056 ±0.004 - b 0.010 0.010 0.010 ±0.002 - c 0.008 0.008 0.008 ±0.001 - D 0.193 0.341 0.390 ±0.004 1, 3 E 0.236 0.236 0.236 ±0.008 - E1 0.154 0.154 0.154 ±0.004 2, 3 e 0.025 0.025 0.025 Basic - L 0.025 0.025 0.025 ±0.009 - L1 0.041 0.041 0.041 Basic - N 16 24 28 Reference - B 0.010 C A B e H C SEATING PLANE 0.007 0.004 C b C A B Rev. E 3/01 NOTES: 1. Plastic or metal protrusions of 0.006” maximum per side are not included. L1 A 2. Plastic interlead protrusions of 0.010” maximum per side are not included. 3. Dimensions “D” and “E1” are measured at Datum Plane “H”. c 4. Dimensioning and tolerancing per ASME Y14.5M-1994. SEE DETAIL “X” 0.010 A2 GAUGE PLANE L A1 4°±4° DETAIL X All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 17 FN7325.9 January 5, 2007