16-Bit, 65 MSPS A/D Converter AD10677 FEATURES FUNCTIONAL BLOCK DIAGRAM 65 MSPS sample rate 80 dBFS signal-to-noise ratio Transformer-coupled analog input Single PECL clock source Digital outputs True binary format 3.3 V and 5 V CMOS-compatible AIN AD10677 AIN 14 ADC DOUT0 14 ADC 14 ADC APPLICATIONS OUTPUT DATA BITS DOUT15 14 ADC ANALOG POWER AGND +5VA +3.3VE AGND CLOCK DISTRIBUTION CIRCUIT DGND +3.3V DGND ENCODE ENCODE DIGITAL POWER 03208-B-001 Low signature radar Medical imaging Communications instrumentation Instrumentation Antenna array processing DIGITAL POSTPROCESSING Figure 1. GENERAL DESCRIPTION PRODUCT HIGHLIGHTS The AD10677 is a 16-bit, high performance, analog-to-digital converter (ADC) for applications that demand increased SNR levels. Exceptional noise performance and a typical signal-tonoise ratio of 80 dBFS are obtained by digitally postprocessing the outputs of four ADCs. A single analog input and PECL sampling clock and 3.3 V and 5 V power supplies are required. 1. 2. 3. Guaranteed sample rate of 65 MSPS. Input signal conditioning with optimized noise performance. Fully tested and guaranteed performance. The AD10677 is assembled using a 0.062-inch laminate board with three sets of connector interface pads to accommodate analog and digital isolation. Analog Devices recommends using the FSI-110-03-G-D-AD-K-TR connector from Samtec. The overall card fits a 2.2 inch × 2.8 inch PCB specified from 0°C to 70°C. Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. AD10677 TABLE OF CONTENTS Features .............................................................................................. 1 Pin Configurations and Function Descriptions ............................7 Applications....................................................................................... 1 Typical Performance Characteristics ..............................................9 General Description ......................................................................... 1 Terminology .................................................................................... 11 Functional Block Diagram .............................................................. 1 Theory of Operation ...................................................................... 12 Product Highlights ........................................................................... 1 Thermal Considerations............................................................ 12 Revision History ............................................................................... 2 Input Stage................................................................................... 12 Specifications..................................................................................... 3 Encoding the AD10677 ............................................................. 12 DC Specifications ......................................................................... 3 Output Loading .......................................................................... 12 Digital Specifications ................................................................... 3 Analog and Digital Power Supplies.......................................... 12 AC Specifications.......................................................................... 4 Analog and Digital Grounding................................................. 13 Switching Specifications .............................................................. 4 Other Notes................................................................................. 13 Absolute Maximum Ratings............................................................ 5 Evaluation Board ........................................................................ 13 Explanation of Test Levels ........................................................... 5 Outline Dimensions ....................................................................... 18 Operating Range........................................................................... 5 Ordering Guide .......................................................................... 18 ESD Caution.................................................................................. 5 Test Circuits....................................................................................... 6 REVISION HISTORY 5/06—Rev. C to Rev. D Changes to Figure 9.......................................................................... 8 Edits to Table 8................................................................................ 13 Edits to Figure 19............................................................................ 14 3/05—Rev. B to Rev. C Changes to Figure 1.......................................................................... 1 Changes to Figure 2 and Figure 3................................................... 6 Added Figure 6 to Figure 8.............................................................. 7 Reformatted Table 7 ......................................................................... 7 Changes to Figure 9.......................................................................... 8 Changes to Figure 10 to Figure 13.................................................. 9 Reformatted Theory of Operation Section ................................. 12 Changes to Figure 19...................................................................... 14 12/03—Rev. A to Rev. B Updated Format..................................................................Universal Changes to Table 1 and Footnotes...................................................3 Changes to Theory of Operation.................................................. 12 Changes to Ordering Guide .......................................................... 20 8/03—Rev. 0 to Rev. A Changes to Specifications..................................................................2 Changes to Table 1..............................................................................4 Changes to Definition of Specifications ....................................... 10 Updated Outline Dimensions........................................................ 18 11/02—Revision 0: Initial Version Rev. D | Page 2 of 20 AD10677 SPECIFICATIONS DC SPECIFICATIONS AVCC = 5 V, EVCC = 3.3 V, VDD = 3.3 V, TA = 25°C, differential encode = 65 MSPS, CLOAD ≤ 10 pF, unless otherwise noted. Table 1. Parameter RESOLUTION Offset Error Gain Error Differential Nonlinearity (DNL) Integral Nonlinearity (INL) TEMPERATURE DRIFT Offset Error Gain Error POWER SUPPLY REJECTION RATIO (PSRR) ANALOG INPUTS (AIN, AIN) 1 Differential Input Voltage Range Differential Input Resistance Differential Input Capacitance Input Bandwidth VSWR 2 POWER SUPPLY 3 Supply Current IAVCC (AVCC = 5.0 V) IEVCC (EVCC = 3.3 V) IVDD (VDD = 3.3 V) Total Power Dissipation 4 Test Level Min I I V V –0.30 –7 Typ 16 +0.12 ±0.7 ±4 Unit Bits %FS %FS LSB LSB V V V 13 200 60 ppm/ºC ppm/ºC dB V V V IV V 2.15 50 2.5 V p-p Ω nF MHz Ratio 0.40 Max +0.30 +7 210 1.04:1 I I I I 0.95 0.15 0.49 6.86 1.05 0.2 0.625 7.5 A A A W 1 Measurement includes the recommended interface connector. Input VSWR, see Figure 15. Supply voltages should remain stable within 65% for normal operation. However, rated ac (harmonics) performance is valid only over the range AVCC = 5.0 V to 5.25 V. 4 Power dissipation measured with encode at rated speed and −1 dBFS analog input at 10 MHz. 2 3 DIGITAL SPECIFICATIONS AVCC = 5 V, EVCC = 3.3 V, VDD = 3.3 V, TA = 25°C, differential encode = 65 MSPS, CLOAD ≤ 10 pF, unless otherwise noted. Table 2. Parameter ENCODE INPUTS (ENCODE, ENCODE) Differential Input Voltage Range Differential Input Resistance Differential Input Capacitance LOGIC OUTPUTS (D15 to D0) Logic Compatibility Logic 1 Voltage ILOAD ≤ 100 mA Logic 0 Voltage ILOAD ≤ 100 mA Output Coding Series Output Resistance per Bit Test Level Min IV V V 0.4 Typ 100 160 CMOS 0.9 × VDD 0.4 True binary 120 IV IV Rev. D | Page 3 of 20 Max Unit V p-p Ω pF V V Ω AD10677 AC SPECIFICATIONS AVCC = 5 V, EVCC = 3.3 V, VDD = 3.3 V, TA = 25°C, differential encode = 65 MSPS, CLOAD ≤ 10 pF, unless otherwise noted. Table 3. Parameter SNR 1 Analog Input @ –1 dBFS SINAD 2 Analog Input @ –1 dBFS SFDR 3 Analog Input @ –1 dBFS Test Level Min Typ 2.5 MHz 10 MHz 30 MHz I I I 77.5 77.5 76.5 80 80 78.5 dBFS dBFS dBFS 2.5 MHz 10 MHz 30 MHz I I I 77.2 77.2 74.5 79 79 77 dBFS dBFS dBFS 2.5 MHz 10 MHz 30 MHz I I I 84 84 79.5 92 92 84 dBFS dBFS dBFS 96 dBFS TWO-TONE 4 Analog Input @ –7 dBFS—IMD f1 = 10 MHz, f2 = 12 MHz V Max Unit 1 Analog input signal power at –1 dBFS; signal-to-noise (SNR) is the ratio of signal level to total noise (first five harmonics removed). Encode = 65 MSPS. SNR is reported in dBFS, related back to converter full scale. Analog input signal power at –1 dBFS; signal-to-noise and distortion (SINAD) is the ratio of signal level to total noise + harmonics. Encode = 65 MSPS. SINAD is reported in dBFS, related back to converter full scale. 3 Analog input signal at –1 dBFS; SFDR is the ratio of converter full scale to the worst spur. 4 Both input tones at –7 dBFS; two-tone intermodulation distortion (IMD) rejection is the ratio of either tone to the worst third-order intermodulation product. 2 SWITCHING SPECIFICATIONS AVCC = 5 V, EVCC = 3.3 V, VDD = 3.3 V, TA = 25°C, differential encode = 65 MSPS, CLOAD ≤ 10 pF, unless otherwise noted. Table 4. Parameter MAXIMUM CONVERSION RATE MINIMUM CONVERSION RATE DUTY CYCLE ENCODE INPUT PARAMETERS Encode Period @ 65 MSPS, tENC Encode Pulse Width High @ 65 MSPS, tENCH Encode Pulse Width Low @ 65 MSPS, tENCL ENCODE/DATA (D15:D0) Propagation Delay, tPDH Valid Time, tPDL APERTURE DELAY, tA APERTURE UNCERTAINTY (JITTER), tJ PIPELINE DELAYS Test Level I IV IV Min 65 Typ Max 15 60 40 Unit MSPS MSPS % V V V 15.4 7.7 7.7 ns ns ns V V V 6.7 7.3 480 500 9 ns ns ps fs rms Cycles Rev. D | Page 4 of 20 AD10677 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter AVCC to AGND EVCC to AGND VDD to DGND Analog Input Voltage Analog Input Current Encode Input Voltage Digital Output Voltage Maximum Junction Temperature Storage Temperature Range Ambient Maximum Operating Temperature Ambient Rating 0 V to 7 V 0 V to 6 V –0.5 V to +3.8 V 0 V to AVCC 25 mA 0 V to 5 V –0.5 V to VDD 150°C –65°C to +150°C 92°C Table 6. Output Coding (True Binary) Code 65535 32768 32767 0 AIN (V) +1.1 . . . 0 –0.000034 . . . –1.1 Digital Output 1111 1111 1111 1111 . . . 1000 0000 0000 0000 0111 1111 1111 1111 . . . 0000 0000 0000 0000 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. EXPLANATION OF TEST LEVELS I. II 100% production tested. 100% production tested at 25°C and sample tested at specified temperatures. III. Sample tested only. IV. Parameter is guaranteed by design and characterization testing. V. Parameter is a typical value only. 100% production tested at 25°C; guaranteed by design and characterization testing for industrial temperature range; 100% production tested at temperature extremes for military devices. OPERATING RANGE Operating ambient temperature range: 0°C to 70°C. See the Thermal Considerations section. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. D | Page 5 of 20 AD10677 TEST CIRCUITS t0 N N+2 N+1 N+3 N+4 N+5 N+6 N+3 N+4 N+5 N+6 N–6 N–5 N–4 ANALOG INPUT ENCODE, ENCODE tENCL N N+1 DATA BITS, D[15:0] tENCH N+2 N–9 tPDH tPDL N–8 N–7 03208-B-002 tENC Figure 2. Timing Diagram VCH AVCC BUF AIN 200Ω 25Ω VCL BUF 500Ω VCH AIN T/H 500Ω 25Ω VREF AVCC 500Ω BUF ×4 T/H 03208-B-003 1:1 VCL Figure 3. Analog Input Stage VDD VDD P 37.5kΩ MACROCELL LOGIC 100Ω ENC PECL DRIVER 03208-B-004 ENC 120Ω N Figure 5. Digital Output Stage Figure 4. Equivalent Encode Input Rev. D | Page 6 of 20 D0–D15 03208-B-005 EVCC AD10677 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS DGND 1 2 DGND DGND 1 2 DGND +3.3VE 1 2 +5.0VA DOUT15 3 4 NC +3.3VD 3 4 DOUT0 +3.3VE 3 4 +5.0VA DOUT14 5 6 DGND +3.3VD 5 6 DOUT1 AGND 5 6 +5.0VA 8 NC +3.3VD 7 8 DOUT2 AGND 7 8 +5.0VA 10 DGND DGND 9 10 DOUT3 AGND 9 TOP VIEW DOUT11 11 (Not to Scale) 12 NC DOUT10 13 14 DGND 16 NC DOUT8 17 18 DGND DGND 19 20 NC TOP VIEW DGND 11 (Not to Scale) 12 DOUT4 DGND 13 14 DOUT5 DGND 15 16 DOUT6 03208-B-023 DOUT9 15 NC = NO CONNECT AD10677 +3.3VD 17 18 DOUT7 +3.3VD 19 20 DGND Figure 6. Pin Configuration P1 (See Figure 9) AD10677 10 AGND TOP VIEW AGND 11 (Not to Scale) 12 AIN AGND 13 14 AIN Figure 7. Pin Configuration P2 (See Figure 9) ENCODE 15 16 AGND ENCODE 17 18 AGND AGND 19 20 AGND 03208-B-025 DOUT12 9 AD10677 03208-B-024 DOUT13 7 Figure 8. Pin Configuration P3 (See Figure 9) Table 7. Pin Function Descriptions P1 Pin No. 1 1, 2, 6, 10, 14, 18, 19 3, 5, 7, 9, 11, 13, 15, 17 N/A 4, 8, 12, 16, 20 N/A N/A N/A N/A N/A N/A N/A P2 Pin No. 2 1, 2, 9, 11, 13, 15, 20 4, 6, 8, 10, 12, 14, 16, 18 3, 5, 7, 17, 19 N/A N/A N/A N/A N/A N/A N/A N/A P3 Pin No. 3 N/A N/A N/A N/A 1, 3 2, 4, 6, 8 5, 7, 9 to 11, 13, 16, 18 to 20 12 14 15 17 1 Equivalent pin configuration in Figure 19 is J12. Equivalent pin configuration in Figure 19 is J11. 3 Equivalent pin configuration in Figure 19 is J13. 2 Rev. D | Page 7 of 20 Mnemonic DGND DOUTx +3.3VD NC +3.3VE +5.0VA AGND AIN AIN ENCODE ENCODE Description Digital Ground. Data Bit Output. Digital Voltage (VDD). No Connection. Encode Voltage (EVCC). Analog Voltage (AVCC). Analog Ground. Analog Input. Analog Input (Complement). Encode Input. Encode Input (Complement). AD10677 0.466 P1 MH4 0.960 0.888 2.148 P3 1.223 MH2 1.693 0.433 0.925 0.805 0.900 MH1 0.526 P2 MH3 0.757 INTERFACE NOTES SUGGESTED INTERFACE MANUFACTURER: SAMTEC INTERFACE PART NUMBERS FOR P1-P3: FSI-110-03-G-D-AD-K-TR (20-PIN) HOLES 1–4 ACCOMMODATE 2-56 THREADED HARDWARE. USE FOUR 2-56 NUTS FOR SECURING THE PART TO INTERFACE PCB. MANUFACTURER: BUILDING FASTENERS PART NUMBER: HNSS256 DIGIKEY #: H723-ND ALL METAL HARDWARE TO BE TORQUED TO 1.0 INCH-POUND. CARE MUST BE TAKEN WHEN TIGHTENING HARDWARE ADJACENT TO SURFACE-MOUNTED COMPONENTS TO AVOID DAMAGE. TOLERANCES: 0.xxx = ±5mils Figure 9. Interface PCB Assembly, Top View (Dimensions Shown in Inches) Rev. D | Page 8 of 20 03208-D-006 0.955 AD10677 TYPICAL PERFORMANCE CHARACTERISTICS 0 –20 ENCODE = 65MSPS AIN = 10.1MHz AND 12.1MHz IMD = 97.03dBFS –10 –20 –30 –30 –40 –40 –50 –50 –60 –60 dBFS –70 –70 –80 –80 –90 –90 –100 –100 –110 –110 –120 –120 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0 32.5 FREQUENCY (MHz) –130 03208-B-007 –130 0 FREQUENCY (MHz) Figure 10. Single-Tone at 2.3 MHz 0 Figure 13. Two-Tone @ 10.1 MHz and 12.1 MHz 0 ENCODE = 65MSPS AIN = 10.1MHz SNR = 80.22dBFS SFDR = 94.3dBFS –10 –20 –0.2 –0.4 –30 AIN = –1dBFS –40 –0.6 –50 –0.8 dBFS dBFS 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0 32.5 03208-B-010 dBFS 0 ENCODE = 65MSPS AIN = 2.3MHz SNR = 80.1dBFS SFDR = 96.16dBFS –10 –60 –70 –1.0 –80 –1.2 –90 –1.4 –100 –1.6 –110 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0 32.5 FREQUENCY (MHz) –2.0 1.0 10.9 20.8 40.6 50.5 60.4 70.3 FREQUENCY (MHz) 80.2 90.1 100.0 1000.0 Figure 14. Gain Flatness Figure 11. Single-Tone at 10.1 MHz 0 ENCODE = 65MSPS –10 AIN = 31.7MHz –20 SNR = 78.95dBFS SFDR = 85.5dBFS –30 2.0 –40 1.7 –50 1.6 1.9 1.8 VSWR dBFS 30.7 03208-B-011 0 03208-B-008 –130 03208-B-012 –1.8 –120 –60 –70 1.5 –80 1.4 –90 1.3 –100 1.2 –110 1.1 –130 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 30.0 32.5 FREQUENCY (MHz) 03208-B-009 –120 Figure 12. Single-Tone at 31.7 MHz 1.0 0.1 1.0 10.0 FREQUENCY (MHz) 100.0 Figure 15. Analog Input VSWR Rev. D | Page 9 of 20 AD10677 100 96 90 94 80 92 SFDR 2.5MHz 70 90 88 SNR 30MHz dBc SFDR 30MHz 50 SFDR 10MHz 40 SFDR 86 84 SNR 2.5MHz 30 82 20 SNR 80 10 78 –70 –60 –50 –40 –30 –20 –10 FUNDAMENTAL LEVEL (dBFS) 0 Figure 16. SFDR and SNR vs. Analog Input Level 76 0 5 10 15 20 25 30 ANALOG INPUT FREQUENCY (MHz) Figure 17. SFDR and SNR vs. Analog Input Frequency Rev. D | Page 10 of 20 35 03208-B-014 SNR 10MHz 0 –80 03208-B-013 dBc 60 AD10677 TERMINOLOGY Analog Bandwidth The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Output Propagation Delay The delay between the 50% point of the rising edge of the ENCODE command and the time when all output data bits are within valid logic levels. Aperture Delay The delay between the 50% point on the rising edge of the ENCODE command and the instant at which the analog input is sampled. Power Supply Rejection Ratio (PSRR) The ratio of a change in output offset voltage to a change in power supply voltage. Differential Nonlinearity (DNL) The deviation of any code from an ideal 1 LSB step. Signal-to-Noise and Distortion (SINAD) The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, including the first five harmonics and dc. Can be reported in dBc (that is, degrades as signal level is lowered) or in dBFS (always related back to converter full scale). Encode Pulse Width/Duty Cycle Pulse width high is the minimum amount of time the encode pulse should be left in a Logic 1 state to achieve rated performance; pulse width low is the minimum time the encode pulse should be left in a low state. At a given clock rate, these specifications define an acceptable encode duty cycle. Signal-to-Noise Ratio (SNR) The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc. Can be reported in dBc (that is, degrades as the signal level is lowered) or in dBFS (always related back to converter full scale). Integral Nonlinearity (INL) The deviation of the transfer function from a reference line measured in fractions of 1 LSB using a best straight line determined by a least square curve fit. Spurious-Free Dynamic Range (SFDR) The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious component may or may not be an harmonic. SFDR can be reported in dBc (that is, degrades as signal level is lowered) or in dBFS (always related back to converter full scale). Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay. Harmonic Distortion The ratio of the rms signal amplitude to the rms value of the worst harmonic component. Two-Tone Intermodulation Distortion Rejection (IMD) The ratio of the rms value of an input tone to the rms value of the worst third-order intermodulation product; reported in dBc. Maximum Conversion Rate The encode rate at which parametric testing is performed. Minimum Conversion Rate The encode rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB or less below the guaranteed limit. Voltage Standing-Wave Ratio (VSWR) The ratio of the amplitude of the elective field at a voltage maximum to that at an adjacent voltage minimum. Rev. D | Page 11 of 20 AD10677 75 THEORY OF OPERATION The analog input meets a 50 Ω input impedance for easy interface to commercial cables, filters, drivers, and so on. The digital outputs from the four ADCs drive 120 Ω series output terminators and are applied to the CPLD for postprocessing. The digital outputs are added together in the complex programmable logic device through a ripple-carry adder, which provides the 16-bit data output. The AD10677 provides valid data following nine pipeline delays. The result is a 16-bit parallel digital CMOS-compatible word coded as true binary. THERMAL CONSIDERATIONS Due to the high power nature of the part, it is critical that the following thermal conditions be met for the part to perform to data sheet specifications. This also ensures that the maximum junction temperature (150°C) is not exceeded. • 60 55 50 45 40 35 30 0 50 100 150 200 AIR FLOW (AMBIENT) (LFM) 250 300 Figure 18. Temperature (Case) vs. Air Flow (Ambient) INPUT STAGE The AD10677 encode inputs are ac-coupled to a PECL differential receiver/driver. The output of the receiver/driver provides a clock source for a 1:5 PECL clock driver and a PECL-to-TTL translator. The 1:5 PECL clock driver provides the differential encode signal for each of the four high speed ADCs. The PECL-to-TTL translator provides a clock source for the complex programmable logic device (CPLD). • • 65 03208-B-016 The four high speed ADCs use a three-stage subrange architecture. The AD10677 provides complementary analog input pins, AIN and AIN. Each analog input is centered around 2.4 V and should swing ±0.55 V around the reference. Because AIN and AIN are 180 degrees out of phase, the differential analog input signal is 2.15 V p-p. TEMPERATURE (CASE) (°C) 70 The AD10677 uses four parallel high speed ADCs in a correlation technique to improve the dynamic range of the ADCs. The technique sums the parallel outputs of the four converters to reduce the uncorrelated noise introduced by the individual converters. Signals processed through the high speed adder are correlated and summed coherently. Noise is not correlated and sums on an rms basis. Operation temperature (TA) must be within 0°C to 70°C. All mounting standoffs should be fastened to the interface PCB assembly with 2-56 nuts. This ensures good thermal paths as well as excellent ground points. The unit rises to ~72°C (TC) on the heat sink in still air (0 linear feet per minute (LFM)). The minimum recommended air flow is 100 linear feet per minute (LFM) in either direction across the heat sink (see Figure 18). The user is provided with a single-to-differential transformercoupled input. The input impedance is 50 Ω and requires a 2.15 V p-p input level to achieve full scale. ENCODING THE AD10677 The AD10677 encode signal must be a high quality, low phase noise source to prevent performance degradation. The clock input must be treated as an analog input signal because aperture jitter can affect dynamic performance. For optimum performance, the AD10677 must be clocked differentially. OUTPUT LOADING Take care when designing the data receivers for the AD10677. The complex programmable logic device’s 16-bit outputs drive 120 Ω series resistors to limit the amount of current that can flow into the output stage. To minimize capacitive loading, there should be only one gate on each of the output pins. A typical CMOS gate combined with the PCB trace has a load of approximately 10 pF. Note that extra capacitive loading increases output timing and invalidates timing specifications. Digital output timing is guaranteed with 10 pF. ANALOG AND DIGITAL POWER SUPPLIES Care must be taken when selecting a power source. Linear supplies are recommended. Switching supplies tend to have radiated components that can be coupled into the ADCs. The AD10677 features separate analog and digital supply and ground currents, helping to minimize digital corruption of sensitive analog signals. The +3.3VE supply provides power to the clock distribution circuit. The +3.3VD supply provides power to the digital output section of the ADCs, the PECL-to-TTL translator, and the CPLD. Separate +3.3VE and +3.3VD supplies are used to prevent modulation of the clock signal with digital noise. Rev. D | Page 12 of 20 AD10677 The +5.0VA supply provides power to the analog sections of the ADCs. Decoupling capacitors are strategically placed throughout the circuit to provide low impedance noise shunts to ground. The +5.0VA supply (analog power) should be decoupled to analog ground (AGND) and +3.3VD (digital power) should be decoupled to digital ground (DGND). The +3.3VE supply (analog power) should be decoupled to AGND. The evaluation board schematic (Figure 19) and layout data (Figure 20 and Figure 21) show a PCB implementation of the AD10677. Table 8 shows the PCB bill of materials. OTHER NOTES The circuit is configured on a 2.2 inch × 2.8 inch laminate board with three sets of connector interface pads. The pads are configured to provide easy keying for the user. The pads are made for low profile applications and have a total height of 0.12 inches after mating. The part numbers for the header mates are provided in Figure 9. All pins of the analog and digital sections are described in the Pin Configurations and Function Descriptions section. EVALUATION BOARD ANALOG AND DIGITAL GROUNDING Although the AD10677 provides separate analog and digital ground pins, the device should be treated as an analog component. Proper grounding is essential in high speed, high resolution systems. Multilayer printed circuit boards are recommended to provide optimal grounding and power distribution. The use of power and ground planes provides distinct advantages. Power and ground planes minimize the loop area encompassed by a signal and its return path, minimize the impedance associated with power and ground paths, and provide a distributed capacitor formed by the power plane, printed circuit board material, and ground plane. The AD10677 has four metal standoffs (see Figure 9). MH2 is located in the center of the unit, and MH1 is located directly below analog header P3. Both of these standoffs are tied to analog ground and should be connected accordingly on the next level assembly for best performance. The two standoffs located near P1 and P2 (MH3 and MH4) are tied to digital ground and should be connected accordingly on the next level assembly. The AD10677 evaluation board provides an easy way to test the 16-bit, 65 MSPS ADC. The board requires a clock source, an analog input signal, two 3.3 V power supplies, and a 5 V power supply. The clock source is buffered on the board to provide a latch, a data ready signal, and the clock for the AD10677. The ADC digital outputs are latched on board by a 74LCX16374. The digital outputs and output clock are available on a 40-pin connector, J1. Power is supplied to the board via uninsulated metal banana jacks. The analog input is connected via an SMA connector, AIN. The analog input section provides a single-ended input option or a differential input option. The board is shipped in a singleended analog input option. Removing a ground tie at E17 converts the circuit to a differential analog input configuration. Table 8. PCB Bill of Materials Item 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Quantity 1 1 3 3 6 2 1 1 19 1 4 17 6 4 1 1 Reference Designator J1 U1 L1 to L3 J11 to J13 P1, P2, P8 to P10, P12 U5, U6 U7 R24 R0 to R16, R20, R23 R17 R18, R19, R21, R22 C1, C10 to C13, C16 to C18, C23 to C26, C28 to C32 C8, C9, C14, C15, C27, C33 J2, J3, J5, J6 A1 AD106xx Evaluation Board Description Connector, 40-position header, male straight IC, LV 16-bit, D-type flip-flop with 5 V tolerant IO Common-mode surface-mount ferrite bead 20 Ω Connector, 1 mm single-element interface Uninsulated banana jack, all metal IC, 3.3 V/5 V ECL differential receiver/driver IC, 3.3 V dual differential LVPECL-to-LVTTL translator RES 0.0 Ω 1/10 W 5% 0805 SMD RES 51.1 Ω 1/10 W 1% 0805 SMD RES 18.2 kΩ 1/10 W 1% 0805 SMD RES 100 Ω 1/10 W 1% 0805 SMD CAP 0.1 μF 16 V ceramic X7R 0805 CAP 10 μF 10 V ceramic Y5V 1206 Connector, SMA jack 200 mil STR gold Assembly, AD10677BWS GS04483 (PCB) Rev. D | Page 13 of 20 Figure 19. Evaluation Board Schematic C13 0.1μF 16V C10 0.1μF 16V 03208-B-015 AGND +5VA AGND +3.3VE L2 AGND AGND 2 4 C8 10μF 10V 1 3 P2 P9 +5VA AGND +3.3VE AGND 2 4 R21 R22 100Ω 100Ω C12 0.1μF 16V R30 DNI C11 0.1μF 16V AGND C15 10μF 10V C25 0.1μF 16V C26 0.1μF 16V AGND AGND AGND MC10EL16D 8 7 6 5 AGND R19 100Ω C9 10μF 10V 1 3 U6 NC VCC D Q D Q VBB VEE L1 1 2 3 4 +3.3VE AGND R18 100Ω P1 P10 8 7 6 5 +3.3VE MC10EL16D AGND NC VCC D Q D Q VBB VEE R17 18.2kΩ 1 2 3 4 U5 POWER CONNECTIONS R20 51.1Ω J5 ENCODE R16 51.1Ω J6 ENCODE C32 0.1μF 16V +3.3VE 1 J13 2 3 4 5 6 7 8 10 9 12 11 14 13 16 15 18 17 20 19 2 4 6 8 10 12 14 16 18 20 AGND C14 10μF 10V 8 7 6 5 E17 R27 DNI AGND R28 DNI R29 DNI R24 0.0Ω R23 51.1Ω R31 DNI AGND E2 AGND E6 DGND C18 0.1μF 16V C29 0.1μF 16V AGND E10 AGND E12 AGND E18 AGND E19 DGND DGND MH4 OPTIONAL EVALUATION BOARD GROUND TIES C16 0.1μF 16V DGND DRY C17 0.1μF 16V +3.3VD BUFMEM LATCH DGND BYPASS CAPACITORS +3.3VD MH2 AGND AGND J3 J2 ANALOG INPUT E15 DGND AGND AGND DGND SINGLE-ENDED DIFFERENTIAL INPUT OPTION INPUT OPTION DGND MC100ELT23D DGND VCC Q0 Q1 D1 GND 1 D0 2 D0 3 D1 4 +3.3VD U7 AGND FSI-110-03-G-D-AD-TR 1 3 5 7 9 11 13 15 17 19 C30 0.1μF 16V AGND +5VA J12 MH1–MH4 = DUT MOUNTING HOLES MH3 AGND E21 E4 C28 0.1μF 16V DGND E3 AGND AGND C23 0.1μF 16V +3.3VE DGND HEADER 732mm MH1 DRY 2 4 6 8 10 12 14 1 3 5 7 9 11 13 Rev. D | Page 14 of 20 J8 19 17 15 13 11 9 7 5 3 1 19 17 15 13 11 9 7 5 3 1 20 18 16 14 12 10 8 6 4 2 DGND E20 20 18 16 14 12 10 8 6 4 2 AD10677 PART OUTLINE SI-110-03-G-D-AD-TR J11 20 20 19 19 18 18 17 17 16 16 15 15 14 13 14 13 12 11 12 11 10 10 9 9 8 8 7 7 6 6 5 5 4 4 3 3 2 2 1 1 FSI-110-03-G-D-AD-TR DGND VCC VCC CP2 VCC OE2 VCC O15 I15 O14 I14 I13 O13 I12 O12 I11 O11 O10 I10 I9 O9 I8 O8 CP1 OE1 I7 O7 I6 O6 I5 O5 I4 O4 I3 O3 I2 O2 I1 O1 I0 O0 GND GND GND GND GND GND GND GND U1 DGND E22 DGND E13 DGND P12 P8 DGND AGND +3.3VD 12 11 9 8 6 5 3 2 21 15 10 4 42 31 7 18 23 22 20 19 17 16 14 13 DGND E1 E5 L3 2 4 DGND E9 E7 DGND E11 DGND C27 10μF 10V 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 40-PIN HMS 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 J1 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 C24 0.1μF 16V DGND E8 C1 0.1μF 16V +3.3VD R8 51.1Ω R9 51.1Ω R10 51.1Ω R11 51.1Ω R12 51.1Ω R13 51.1Ω R14 51.1Ω R15 51.1Ω +3.3VD DGND DGND 1 3 R25 DNI R0 51.1Ω R1 51.1Ω R2 51.1Ω R3 51.1Ω R4 51.1Ω R5 51.1Ω R6 51.1Ω R7 51.1Ω +3.3VD BUFMEM 74LCX16374MTD 25 24 26 27 29 30 32 33 35 36 48 1 37 38 40 41 43 44 46 47 28 34 39 45 C31 0.1μF 16V POWER CONNECTIONS R30 DNI DGND LATCH DGND C33 10μF 10V +3.3VD DGND 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 AD10677 AD10677 03208-B-017 AD10677/PCP EVALUATION BOARD 03208-B-018 Figure 20. Evaluation Board Mechanical Layout, Top View Figure 21. Evaluation Board Mechanical Layout, Bottom View Rev. D | Page 15 of 20 03208-B-019 AD10677 03208-B-020 Figure 22. Evaluation Board Top Layer Copper Figure 23. Evaluation Board Second Layer Copper Rev. D | Page 16 of 20 03208-B-021 AD10677 03208-B-022 Figure 24. Evaluation Board Third Layer Copper Figure 25. Evaluation Board Bottom Layer Copper Rev. D | Page 17 of 20 AD10677 OUTLINE DIMENSIONS 2.795 0.170 0.120 0.070 2.745 R33 2.695 C3 C27 R30 C42 C33 a C37 C38 U5 C30 R28 AD10677BWS LOT NUMBER DATA CODE USA U4 C34 R29 R32 C44 C28 C35 R2 R34 C32 R21 C45 C31 R7 C62 C66 C64 C12 C47 P1 C25 C26 R31 C24 C60 C61 U6 C8 R25 R19 R18 U1 C13 R4 U7 C20 C18 R38 C43 C41 R5 C65 U8 C19 R3 R8 C63 R37 C5 C6 R11 C9 C7 R10 C48 R6 C46 C36 MP4 C10 R13 R1 R9 T1 R35 R26 R39 C11 R14 C67 C59 C23 C40 U3 C49 C58 C57 R12 R16 C56 C55 P3 C21 C14 C52 C51 C4 C29 R27 C39 R40 C2 C22 C1 P2 MP5 C17 R41 MP3 2.220 2.170 2.120 U2 R17 R15 C15 C50 C54 C53 MP6 0.370 0.320 0.270 0.314 0.264 0.214 Top View Figure 26. AD10677 Outline Dimensions Dimensions shown in inches ORDERING GUIDE Model AD10677BWS AD10677/PCB Temperature Range 0°C to 70°C Package Description Non-Herm Hybrid Surface Mount (2.2" × 2.8") Evaluation Board Rev. D | Page 18 of 20 Package Option WS-120 AD10677 NOTES Rev. D | Page 19 of 20 AD10677 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C03208-0-5/06(D) Rev. D | Page 20 of 20