ADS7826 ADS7827 ADS7829 SLAS388 – JUNE 2003 10/8/12-BIT HIGH SPEED 2.7 V microPOWER™ SAMPLING ANALOG-TO-DIGITAL CONVERTER FEATURES DESCRIPTION • High Throughput at Low Supply Voltage (2.7 V VCC) – ADS7829: 12-bit 125 KSPS – ADS7826: 10-bit 200 KSPS – ADS7827: 8-bit 250 KSPS • Very Wide Operating Supply VoltageL: 2.7 V to 5.25 V (as Low as 2.0 V With Reduced Performance) Rail-to-Rail, Pseudo Differential Input Wide Reference Voltage: 50 mV to VCC Micropower Auto Power-Down: – Less Than 60 µW at 75 kHz, 2.7 V VCC The ADS7826/27/29 is a family of 10/8/12-bit sampling analog-to-digital converters (A/D) with assured specifications at 2.7-V supply voltage. It requires very little power even when operating at the full sample rate. At lower conversion rates, the high speed of the device enables it to spend most of its time in the power down mode— the power dissipation is less than 60 µW at 7.5 kHz. • • • • • Low Power Down Current: 3 µA Max Ultra Small Chip Scale Package: 8-pin 3 x 3 PDSO (SON, Same Size as QFN) • SPI™ Compatible Serial Interface The ADS7826/27/29 also features operation from 2.0 V to 5 V, a synchronous serial interface, and a differential input. The reference voltage can be set to any level within the range of 50 mV to VCC. Ultra-low power and small package size make the ADS7826/27/29 family ideal for battery operated systems. It is also a perfect fit for remote data acquisition modules, simultaneous multichannel systems, and isolated data acquisition. The ADS7826/27/29 family is available in a 3 x 3 8-pin PDSO (SON, same size as QFN) package. APPLICATIONS • • • • Battery Operated Systems Remote Data Acquisition Isolated Data Acquisition Simultaneous Sampling, Multichannel Systems Control SAR VREF D OUT +In Serial Interface CDAC –In S/H Amp Comparator DCLOCK CS/SHDN microPOWER is a trademark of Texas Instruments. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2003, Texas Instruments Incorporated ADS7826 ADS7827 ADS7829 www.ti.com SLAS388 – JUNE 2003 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. PACKAGE/ORDERING INFORMATION MAXIMUM LINERARITY ERROR (LSB) PRODUCT INTEGRAL DIFFERENTIAL PACKAGE (1) SPECIFICATION TEMPERATURE RANGE PACKAGE MARKING (2) ORDERING NUMBER TRANSPORT MEDIA ADS7829I ±2 ±2 SON-8 -40°C to 85°C F29 ADS7829IDRBR Tape and reel ADS7829IB ±1.25 -1/1.25 SON-8 -40°C to 85° F29 ADS7829IBDRBR Tape and reel ADS7826I ±1 ±1 SON-8 -40°C to 85°C F26 ADS7826IDRBR Tape and reel ADS7827I ±1 ±1 SON-8 -40°C to 85°C F27 ADS7827IDRBR Tape and reel ADS7829I ±2 ±2 SON-8 -40°C to 85°C F29 ADS7829IDRBT Tape and reel ADS7829IB ±1.25 -1/1.25 SON-8 -40°C to 85°C F29 ADS7829IBDRBT Tape and reel ADS7826I ±1 ±1 SON-8 -40°C to 85°C F26 ADS7826IDRBT Tape and reel ADS7827I ±1 ±1 SON-8 -40°C to 85°C F27 ADS7827IDRBT Tape and reel (1) (2) For detail drawing and dimension table, see end of this data sheet or package drawing file on web. Performance Grade information is marked on the reel. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VCC 6V Analog input Logic input -0.3 V to (VCC + 0.3 V) -0.3 V to 6 V Case temperature 100°C Junction temperature 150°C Storage temperature 125°C External reference voltage 5.5 V (1) 2 Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ADS7826 ADS7827 ADS7829 www.ti.com SLAS388 – JUNE 2003 SPECIFICATIONS At -40°C to 85°C, VCC = 2.7 V, Vref = 2.5 V, unless otherwise specified. TEST CONDITIONS PARAMETER ADS7829IB MIN TYP ADS7829 MAX MIN 0 Vref TYP ADS7826I MAX MIN 0 Vref TYP ADS7827I TYP MAX UNIT MAX MIN 0 Vref 0 Vref V V ANALOG INPUT Full-scale input span +In - (-In) Absolute input range +In -0.2 VCC +0.2 -0.2 VCC +0.2 -0.2 VCC +0.2 -0.2 VCC +0.2 -IN -0.2 1.0 -0.2 1.0 -0.2 1.0 -0.2 1.0 V Capacitance 25 25 25 25 pF Leakage current ±1 ±1 ±1 ±1 µA 8 Bits SYSTEM PERFORMANCE Resolution 12 No missing codes 12 12 Integral linearity error -1.25 10 11 ±0.4 1.25 -2 10 ±0.8 2 -1 8 ±0.3 1 -1 Bits ±0.2 1 LSB (1) Differential linearity error -1 ±0.4 1.25 -2 ±0.8 2 -1 ±0.3 1 -1 ±0.2 1 LSB Offset error -3 ±0.3 3 -3 ±0.6 3 -2 ±0.4 2 -1 ±0.4 1 LSB Gain error -2 ±0.3 2 -2 ±0.6 2 -1 ±0.3 1 -1 ±0.2 1 LSB Noise 33 33 33 33 µVrms Power supply rejection 82 82 94 98 dB SAMPLING DYNAMICS Conversion time 12 Acquisition time 12 1.5 fDCLOCK 1.5 16 x fsample Throughput (sample rate) fsample 10 8 1.5 16 x fsample 1.5 14 x fsample DCLOCK Cycles DCLOCK Cycles 12 x fsample kHz 2.7 V ≤ VCC ≤ 5.25 V (2) 125 125 200 250 kHz 2.0 V ≤ VCC < 2.7 V (3) (2) 75 75 85 100 kHz DYNAMIC CHARACTERISTICS Total harmonic distortion -82 -80 -78 -72 dB SINAD VIN = 2.5 Vpp at 1 kHz 72 70 62 50 dB Spurious free dynamic range (SFDR) VIN = 2.5 Vpp at 1 kHz 85 82 81 68 dB REFERENCE INPUT Voltage range Resistance Current drain 2.7 V ≤VCC≤3.6 V 0.05 CS = GND, fSAMPLE = 0 Hz VCC-0.2 0.05 5 CS = VCC 5 Full speed at Vref/2 12 fSAMPLE = 7.5 kHz 0.8 CS = VCC 0.001 VCC-0.2 0.05 5 5 60 12 0.001 0.05 20 24 0.001 GΩ 120 µA 3 µA 0.8 3 0.001 V GΩ 5 100 0.8 3 VCC-0.2 5 5 60 0.8 3 VCC-0.2 5 µA DIGITAL INPUT/OUTPUT Logic family CMOS CMOS CMOS CMOS Logic levels VIH IIH = +5 µA 2.0 5.5 2.0 5.5 2.0 5.5 2.0 5.5 V VIL IIL = +5 µA -0.3 0.8 -0.3 0.8 -0.3 0.8 -0.3 0.8 V (1) (2) (3) LSB means Least Significant Bit and is equal to Vref / 2 N where N is the resolution of ADC. For example, with Vref equal to 2.5 V, one LSB is 0.61 mV for a 12 bit ADC (ADS7829). See the Typical Performance Curves for VCC = 5 V and Vref = 5 V. The maximum clock rate of the ADS7826/27/29 are less than 1.2 MHz at 2 V ≤VCC <2.7 V. The recommended regerence voltage is between 1.25 V to 1.024 V. 3 www.ti.com ADS7826 ADS7827 ADS7829 www.ti.com SLAS388 – JUNE 2003 SPECIFICATIONS (continued) At -40°C to 85°C, VCC = 2.7 V, Vref = 2.5 V, unless otherwise specified. ADS7829IB TEST CONDITIONS MIN VOH IOH = -250 µA 2.2 VOL IOL = 250 µA PARAMETER Data format TYP ADS7829 MAX MIN ADS7826I TYP MAX 2.1 MIN ADS7827I TYP MAX 2.1 0.4 Straight binary TYP UNIT MAX 2.1 0.4 Straight binary MIN V 0.4 Straight binary 0.4 V 3.6 V V Straight binary POWER SUPPLY REQUIREMENTS VCC Operating range Quiescent current See (3) and (2) See (2) 2.7 3.6 2.7 3.6 2.7 2.0 2.7 3.6 5.25 3.6 2.7 2.0 2.7 3.6 5.25 2.0 2.7 2.0 2.7 3.6 5.25 3.6 5.25 V 350 µA Full speed (4) 220 fSAMPLE = 7.5 kHz (5), 20 20 20 20 µA fSAMPLE = 7.5 kHz (6) 180 180 180 180 µA Power down 350 CS = VCC 220 350 3 250 350 3 260 3 3 µA 85 °C TEMPERATURE RANGE Specified performance (4) (5) (6) -40 85 -40 85 -40 85 -40 Full speed: 125 ksps for ADS7829, 200 ksps for ADS7826, and 250 ksps for ADS7827. fDCLOCK = 1.2 MHz, CS = VCC for 145 clock cycles out of every 160 for the ADS7829I and ADS7829IB. See the Power Dissipation section for more information regarding lower sample rates. At -40°C to 85°C, VCC = 5 V, Vref = 5 V, unless otherwise specified. PARAMETER TEST CONDITIONS ADS7829IB MIN TYP ADS7829 MAX MIN TYP ADS7826I MAX MIN TYP ADS7827I MAX MIN TYP MAX UNIT SYSTEM PERFORMANCE Resolution No missing codes 12 12 12 10 11 8 10 Bits 8 Bits Integral linearity error ±0.6 ±0.8 ±0.15 ±0.1 1 LSB (7) Differential linearity error ±0.5 ±0.8 ±0.15 ±0.1 1 LSB ANALOG INPUT Offset error ±2.6 ±2.6 ±1.2 ±0.7 LSB Gain error ±1.2 ±1.2 ±0.2 ±0.1 LSB REFERENCE INPUT Voltage range (7) 4 0.05 VCC 0.05 VCC 0.05 LSB means Least Significant Bit . With Vref equal to 5 V, one LSB is 1.22 mV for a 12 bit ADC. VCC 0.05 VCC V ADS7826 ADS7827 ADS7829 www.ti.com SLAS388 – JUNE 2003 DEVICE INFORMATION PIN DESCRIPTION PDSO (SON−8) PACKAGE (TOP VIEW) REF 1 8 +VDD +IN 2 7 DCLOCK −IN 3 6 DOUT GND 4 5 CS/ SHDN Terminal Functions PIN NAME DESCRIPTION 1 Vref Reference input 2 +In Noninverting input 3 -In Inverting input. Connect to ground or to remote ground sense point. 4 GND Ground 5 CS/SHDN Chip select when LOW, shutdown mode when HIGH 6 DOUT The serial output data word is comprised of 12 bits of data. In operation the data is valid on the falling edge of DCLOCK. The second clock pulse after the falling edge of CS enables the serial output. After one null bit, the data is valid for the next 12 edges. 7 DCLOCK Data Clock synchronizes the serial data transfer and determines conversion speed. 8 +VCC Power supply 5 www.ti.com ADS7826 ADS7827 ADS7829 www.ti.com SLAS388 – JUNE 2003 TYPICAL CHARACTERISTICS At TA = 25°C, VCC = 2.7 V, Vref = 25 V, (unless otherwise specified) ADS7829 INTEGRAL LINEARITY Integral Linearity - LSB 1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 0 512 1024 1536 2048 2560 3072 3584 768 896 Decimal Code Figure 1 Integral Linearity - LSB ADS7826 INTEGRAL LINEARITY 1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 0 128 256 384 512 640 Decimal Code Figure 2 Integral Linearity - LSB ADS7827 INTEGRAL LINEARITY 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 32 64 96 128 Decimal Code Figure 3 6 160 192 224 ADS7826 ADS7827 ADS7829 www.ti.com SLAS388 – JUNE 2003 TYPICAL CHARACTERISTICS (continued) At TA = 25°C, VCC = 2.7 V, Vref = 25 V, (unless otherwise specified) Differential Linearity - LSB ADS7829 DIFFERENTIAL LINEARITY 1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 0 512 1024 1536 2048 2560 Decimal Code Figure 4 3072 3584 768 896 Differential Linearity - LSB ADS7826 DIFFERENTIAL LINEARITY 1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 0 128 256 384 512 640 Decimal Code Figure 5 Differential Linearity - LSB ADS7827 DIFFERENTIAL LINEARITY 0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 32 64 96 128 160 192 224 Decimal Code Figure 6 7 www.ti.com ADS7826 ADS7827 ADS7829 www.ti.com SLAS388 – JUNE 2003 TYPICAL CHARACTERISTICS (continued) At TA = 25°C, VCC = 2.7 V, Vref = 25 V, (unless otherwise specified) CHANGE IN MAXIMUM INTEGRAL LINEARITY vs FREE-AIR TEMPERATURE 0.2 0.2 0.15 0.15 Delta From 25 ° C − LSB Delta From 25° C − LSB CHANGE IN MINIMUM INTEGRAL LINEARITY vs FREE-AIR TEMPERATURE 0.1 ADS7826 0.05 0 −0.05 ADS7827 −0.1 0 ADS7827 −0.05 −0.15 −40 −20 0 20 40 60 −0.2 80 −20 0 60 Figure 8. 0.3 Delta From 25° C − LSB 0.3 0.2 0.1 ADS7827 0 ADS7826 80 CHANGE IN MAXIMUM DIFFERENTIAL LINEARITY vs FREE-AIR TEMPERATURE 0.4 ADS7826 0.2 ADS7827 0.1 0 ADS7829 −0.1 −0.2 ADS7829 −0.3 −0.3 −0.4 −0.4 −40 −20 20 40 60 0 TA − Free-Air Temperature − ° C −40 80 −20 0 0.4 0.3 Delta From 25° C − LSB 0.4 0.3 ADS7829 0.2 0.1 ADS7827 80 ADS7826 0.2 ADS7829 0.1 0 ADS7827 −0.1 ADS7826 −0.1 −20 60 CHANGE IN GAIN ERROR vs FREE-AIR TEMPERATURE 0.5 −40 40 Figure 10. CHANGE IN OFFSET ERROR vs FREE-AIR TEMPERATURE 0 20 TA − Free-Air Temperature − ° C Figure 9. Delta From 25° C − LSB 40 Figure 7. −0.2 8 20 TA − Free-Air Temperature − ° C 0.4 −0.1 −40 TA − Free-Air Temperature − °C CHANGE IN MINIMUM DIFFERENTIAL LINEARITY vs FREE-AIR TEMPERATURE Delta From 25° C − LSB ADS7826 0.05 −0.1 ADS7829 −0.15 −0.2 ADS7829 0.1 0 20 40 60 80 −0.2 TA − Free-Air Temperature − ° C −40 −20 0 20 40 60 TA − Free-Air Temperature − ° C Figure 11. Figure 12. 80 ADS7826 ADS7827 ADS7829 www.ti.com SLAS388 – JUNE 2003 TYPICAL CHARACTERISTICS (continued) At TA = 25°C, VCC = 2.7 V, Vref = 25 V, (unless otherwise specified) CHANGE IN QUIESCENT CURRENT vs FREE-AIR TEMPERATURE CHANGE IN MAXIMUM INTEGRAL LINEARITY vs SUPPLY VOLTAGE 0.5 50 Vref = 2.5 V 0.4 30 Delta From 2.7 V − LSB I O − Quiescent Current − mA 40 20 10 0 −10 −20 −30 0.3 ADS7829 0.2 0.1 0 ADS7827 −0.1 −40 −50 −40 ADS7826 −0.2 TA − Free-Air Temperature − ° C 3.2 3.7 4.2 4.7 VCC − Supply Voltage − V Figure 13. Figure 14. −20 0 20 40 60 2.7 80 CHANGE IN MINIMUM INTEGRAL LINEARITY vs SUPPLY VOLTAGE CHANGE IN MAXIMUM DIFFERENTIAL LINEARITY vs SUPPLY VOLTAGE 0.3 0.2 Vref = 2.5 V Vref = 2.5 V 0.2 Delta From 2.7 V − LSB Delta From 2.7 V − LSB 0.1 ADS7827 0 ADS7826 −0.1 ADS7829 −0.2 −0.3 ADS7829 0.1 ADS7827 0 ADS7826 −0.1 −0.2 −0.4 −0.5 2.7 3.2 3.7 4.2 4.7 VCC − Supply Voltage − V −0.3 2.7 5.2 3.2 5.2 6 Vref = 2.5 V Vref = 2.5 V ADS7829 Delta From 2.7 V − LSB 5 ADS7827 0.04 0.02 0 ADS7826 −0.02 −0.04 −0.06 4 ADS7829 3 2 ADS7826 1 ADS7827 −0.08 −0.1 2.7 4.7 CHANGE IN OFFSET ERROR vs SUPPLY VOLTAGE 0.1 Delta From 2.7 V − LSB 4.2 Figure 16. CHANGE IN MINIMUM INTEGRAL LINEARITY vs SUPPLY VOLTAGE 0.06 3.7 VCC − Supply Voltage − V Figure 15. 0.08 5.2 0 3.2 3.7 4.2 4.7 VCC − Supply Voltage − V 5.2 2.7 3.2 3.7 4.2 4.7 5.2 VCC − Supply Voltage − V Figure 17. Figure 18. 9 www.ti.com ADS7826 ADS7827 ADS7829 www.ti.com SLAS388 – JUNE 2003 TYPICAL CHARACTERISTICS (continued) At TA = 25°C, VCC = 2.7 V, Vref = 25 V, (unless otherwise specified) CHANGE IN GAIN vs SUPPLY VOLTAGE CHANGE IN QUIESCENT CURRENT vs SUPPLY VOLTAGE 200 1.2 1 ADS7829 0.8 0.6 0.4 ADS7826 140 120 100 60 0 0 3.7 4.2 ADS7829 80 20 ADS7827 3.2 ADS7826 160 40 0.2 2.7 4.7 5.2 2.7 3.2 3.7 4.2 4.7 5.2 VCC − Supply Voltage − V VCC − Supply Voltage − V Figure 19. Figure 20. ADS7829 CHANGE IN OFFSET ERROR vs REFERENCE VOLTAGE REFERENCE CURRENT vs SAMPLE RATE 30 1.2 VCC = 5 V 1 25 0.8 Change in Offset - LSB Reference Current − µ A ADS7827 Vref = 2.5 V 180 Delta From 2.7 V − µ A Delta From 2.7 V − LSB Vref = 2.5 V 20 15 10 0.6 0.4 0.2 0 - 0.2 - 0.4 5 - 0.6 0 - 0.8 0 25 50 75 100 125 150 175 200 225 250 1 Sample Rate − kHz 2 3 Figure 21. ADS7829 PEAK-TO-PEAK NOISE vs REFERENCE VOLTAGE 2.5 10 VCC = 5 V 9 Peak-To-Peak Noise - LSB 2 Change in Gain - dB 5 Figure 22. ADS7829 CHANGE IN GAIN ERROR vs REFERENCE VOLTAGE 1.5 1 0.5 0 - 0.5 -1 VCC = 5 V 8 7 6 5 4 3 2 1 - 1.5 0 10 4 Reference Voltage - V 2 3 4 5 0 0.1 Reference Voltage - V 1 Reference Voltage - V Figure 23. Figure 24. 10 ADS7826 ADS7827 ADS7829 www.ti.com SLAS388 – JUNE 2003 TYPICAL CHARACTERISTICS (continued) At TA = 25°C, VCC = 2.7 V, Vref = 25 V, (unless otherwise specified) ADS7829 CHANGE IN INTEGRAL and DIFFERENTIAL LINEARITY vs REFERENCE VOLTAGE ADS7829 EFFECTIVE NUMBER OF BITS vs REFERENCE VOLTAGE 12 VCC = 5 V VCC = 5 V Effective Number of Bits - rms Data From 2.5 V Reference - LSB 0.20 0.15 Change in Integral Linearity - LSB 0.10 0.05 0 Change in Differential Linearity - LSB - 0.05 11.75 11.5 11.25 11 10.75 10.5 10.25 10 - 0.10 1 2 3 4 0.1 5 Reference Voltage - V Figure 25. Figure 26. ADS7829 SPURIOUS FREE DYNAMIC RANGE and SIGNAL-TO-NOISE RATIO vs SAMPLE FREQUENCY ADS7829 SIGNAL-TO-NOISE + DISTORTION vs FREQUENCY 100 100 Signal-To-Noise+Distortion - dB Spurious Free Dynamic Range Signal-To-Noise Ratio − dB 90 Spurious Free Dynamic Range 90 80 70 60 Signal-To-Noise 50 40 30 20 80 70 60 50 40 30 20 10 10 0 0 1 10 100 1 1000 10 100 1000 f - frequency - kHz f − Frequency − kHz Figure 27. Figure 28. ADS7826 SPURIOUS FREE DYNAMIC RANGE and SIGNAL-TO-NOISE RATIO vs FREQUENCY ADS7829 TOTAL HARMONIC DISTORTION vs FREQUENCY 0 100 - 10 90 Spurious Free Dynamic Range Signal-To-Noise Ratio − dB THD - Total Harmonic Distortion - dB 10 1 Reference Voltage - V - 20 - 30 - 40 - 50 - 60 - 70 - 80 - 90 Spurious Free Dynamic Range 80 70 60 50 Signal-To-Noise 40 30 20 10 - 100 0 1 10 100 1000 1 f - Frequency - kHz Figure 29. 10 100 f − Frequency − kHz 1000 Figure 30. 11 www.ti.com ADS7826 ADS7827 ADS7829 www.ti.com SLAS388 – JUNE 2003 TYPICAL CHARACTERISTICS (continued) At TA = 25°C, VCC = 2.7 V, Vref = 25 V, (unless otherwise specified) ADS7826 SIGNAL-TO-NOISE + DISTORTION vs FREQUENCY ADS7826 TOTAL HARMONIC DISTORTION vs FREQUENCY 100 THD - Total Harmonic Distortion - dB 0 Signal-To-Noise+Distortion - dB 90 80 70 60 50 40 30 20 10 - 10 - 20 - 30 - 40 - 50 - 60 - 70 - 80 - 90 - 100 0 1 10 100 1 1000 10 Figure 31. ADS7827 SIGNAL-TO-NOISE + DISTORTION vs FREQUENCY 100 80 Signal-To-Noise+Distortion - dB 100 Spurious Free Dynamic Range Signal-To-Noise Ratio − dB 1000 Figure 32. ADS7827 SPURIOUS FREE DYNAMIC RANGE and SIGNAL-TO-NOISE RATIO vs FREQUENCY Spurious Free Dynamic Range 60 40 Signal-To-Noise 20 80 60 40 20 0 0 1 10 100 f − Frequency − kHz 1 1000 10 100 f - frequency - kHz Figure 33. Figure 34. ADS7827 TOTAL HARMONIC DISTORTION vs FREQUENCY THD - Total Harmonic Distortion - dB 0 - 10 - 20 - 30 - 40 - 50 - 60 - 70 - 80 - 90 - 100 1 10 100 f - Frequency - kHz Figure 35. 12 100 f - Frequency - kHz f - frequency - kHz 1000 1000 ADS7826 ADS7827 ADS7829 www.ti.com SLAS388 – JUNE 2003 THEORY OF OPERATION The ADS7826/27/29 is a family of micropower classic successive approximation register (SAR) analog-to-digital (A/D) converters. The architecture is based on capacitive redistribution which inherently includes a sample/hold function. The converter is fabricated on a 0.6 µm CMOS process. The architecture and process allow the ADS7826/27/29 family to acquire and convert an analog signal at up to 200K/250K/125K conversions per second respectively while consuming very little power. The ADS7826/27/29 family requires an external reference, an external clock, and a single power source (VCC). The external reference can be any voltage between 50 mV and VCC. The value of the reference voltage directly sets the range of the analog input. The reference input current depends on the conversion rate of the ADS7826/27/29 family. The minimum external clock input to DCLOCK can be as low as 10 kHz. The maximum external clock frequency is 2 MHz for ADS7829, 2.8 MHz for ADS7826 and 3 MHz for ADS7827 respectively. The duty cycle of the clock is essentially unimportant as long as the minimum high and low times are at least 400 ns (VCC = 2.7 V or greater). The minimum DCLOCK frequency is set by the leakage on the capacitors internal to the ADS7826/27/29 family. The analog input is provided to two input pins: +In and -In. When a conversion is initiated, the differential input on these pins is sampled on the internal capacitor array. While a conversion is in progress, both inputs are disconnected from any internal function. The digital result of the conversion is clocked out by the DCLOCK input and is provided serially, most significant bit first, on the DOUT pin. The digital data that is provided on the DOUT pin is for the conversion currently in progress—there is no pipeline delay. ANALOG INPUT The +In and -In input pins allow for a differential input signal. Unlike some converters of this type, the -In input is not re-sampled later in the conversion cycle. When the converter goes into the hold mode, the voltage difference between +In and -In is captured on the internal capacitor array. The range of the -In input is limited to -0.2 V to 1 V. Because of this, the differential input can be used to reject only small signals that are common to both inputs. Thus, the -In input is best used to sense a remote signal ground that may move slightly with respect to the local ground potential. The input current on the analog inputs depends on a number of factors: sample rate, input voltage, source impedance, and power down mode. Essentially, the current into the ADS7826/27/29 family charges the internal capacitor array during the sample period. After this capacitance has been fully charged, there is no further input current. The source of the analog input voltage must be able to charge the input capacitance (25 pF) to a 10/8/12-bit settling level within 1.5 DCLOCK cycles. When the converter goes into the hold mode or while it is in the power down mode, the input impedance is greater than 1 GΩ. Care must be taken regarding the absolute analog input voltage. To maintain the linearity of the converter, the -In input should not drop below GND 200 mV or exceed GND + 1 V. The +In input should always remain within the range of GND - 200 mV to VCC + 200 mV. Outside of these ranges, the converter’s linearity may not meet specifications. REFERENCE INPUT The external reference sets the analog input range. The ADS7826/27/29 family operates with a reference in the range of 50 mV to VCC. There are several important implications of this. As the reference voltage is reduced, the analog voltage weight of each digital output code is reduced. This is often referred to as the LSB (least significant bit) size and is equal to the reference voltage divided by 2N (where N is 12 for ADS7829, 10 for ADS7826, and 8 for ADS7827). This means that any offset or gain error inherent in the A/D converter appears to increase, in terms of LSB size, as the reference voltage is reduced. The noise inherent in the converter also appears to increase with lower LSB size. With a 2.5 V reference, the internal noise of the converter typically contributes only 0.32 LSB peak-to-peak of potential error to the output code. When the external reference is 50 mV, the potential error contribution from the internal noise is 50 times larger —16 LSBs. The errors due to the internal noise are gaussian in nature and can be reduced by averaging consecutive conversion results. For more information regarding noise, consult the typical performance curves Effective Number of Bits vs Reference Voltage and Peak-to-Peak Noise vs Reference Voltage (only curves for ADS7829 are shown). Note that the effective number of bits (ENOB) figure is calculated based on the converter’s signal-to-(noise + distortion) ratio with a 1 kHz, 0 dB input signal. SINAD is related to ENOB as follows: 13 www.ti.com ADS7826 ADS7827 ADS7829 www.ti.com SLAS388 – JUNE 2003 SINAD = 6.02 × ENOB + 1.76 Serial Interface With lower reference voltages, extra care should be taken to provide a clean layout including adequate bypassing, a clean power supply, a low-noise reference, and a low-noise input signal. Because the LSB size is lower, the converter is more sensitive to external sources of error such as nearby digital signals and electromagnetic interference. The ADS7826/27/29 family communicates with microprocessors and other digital systems via a synchronous 3-wire serial interface. Timings for ADS7829 are shown in Figure 36 and Table 1. The DCLOCK signal synchronizes the data transfer with each bit being transmitted on the falling edge of DCLOCK. Most receiving systems capture the bitstream on the rising edge of DCLOCK. However, if the minimum hold time for DOUT is acceptable, the system can use the falling edge of DCLOCK to capture each bit. DIGITAL INTERFACE Signal Levels The digital inputs of the ADS7826/27/29 family can accommodate logic levels up to 6 V regardless of the value of VCC. Thus, the ADS7826/27/29 family can be powered at 3 V and still accept inputs from logic powered at 5 V. The timings for ADS7826 and ADS7827 serial interface are shown in Figure 37 and Table 1. The DCLOCK signal synchronizes the data transfer with each bit being transmitted on the falling edge of DCLOCK. Most receiving systems capture the bitstream on the rising edge of DCLOCK. However, if the minimum hold time for DOUT is acceptable, athe system can use the fallng edge of DCLOCK to capture each bit. The CMOS digital output (DOUT) swings 0 V to VCC. If VCC is 3 V and this output is connected to a 5-V CMOS logic input, then that IC may require more supply current than normal and may have a slightly longer propagation delay. tCYC CS/SHDN Power Down tSU(CS) DCLOCK tCSD Hi-Z Null Bit Hi-Z B11 B10 B9 B8 B7 B6 B5 B4 (MSB) DOUT B3 B2 B1 B01 tCONV tSMPL Null Bit B11 B10 B9 B8 tDATA After completing the data transfer, if further clocks are applied with CS LOW, the A/D outputs LSB-First data then followed with zeroes indefinitely. Figure 36. ADS7829 Timing tCYC CS/SHDN Power Down tSU(CS) DCLOCK tCSD ADS7826 DOUT Hi-Z ADS7827 DOUT Hi-Z tSMPL Null Bit Hi-Z B9 B8 (MSB) B4 B3 B2 B1 B01 MSB Null Bit Hi-Z B7 B6 (MSB) B4 B3 B2 B1 B01 Null Bit MSB tCONV Figure 37. ADS7826 and ADS7827 Timing 14 Null Bit ADS7826 ADS7827 ADS7829 www.ti.com SLAS388 – JUNE 2003 Table 1. Timing Specifications (VCC = 2.7 V and Above -40°C to 85°C SYMBOL DESCRIPTION tSAMPLE Analog input sample time MIN tCONV Conversion time TYP 1.5 ADS7829I or ADS7829IB 12 ADS7826I 11 ADS7827I tCYC Cycle time MAX UNIT 2.0 DCLOCK Cycles DCLOCK Cycles 9 ADS7829I or ADS7829IB 16 ADS7826 14 ADS7827 12 DCLOCK Cycles tCSD CS falling to DCLOCK LOW 0 tSU(CS) CS falling to DCLOCK rising 30 ns th(DO) DCLOCK falling to current DOUT not valid 15 ns td(DO) DCLOCK falling to next DOUT valid tdis CS rising to DOUT 3-state 40 80 ns ten DCLOCK falling to DOUT enabled 75 175 ns tf DOUT fall time 90 200 ns tr DOUT rise time 110 220 ns 130 A falling CS signal initiates the conversion and data transfer. The first 1.5 to 2.0 clock periods of the conversion cycle are used to sample the input signal. After the second falling DCLOCK edge, DOUT is enabled and outputs a LOW value for one clock period. For the next N (N is 12 for ADS7829, 10 for ADS7826, and 8 for ADS7827) DCLOCK periods, DOUT outputs the conversion result, most significant bit first. After the least significant bit has been sent, DOUT goes to 3-state after the rising edge of CS. A new conversion is initiated only when CS has been taken high and returned low again. 200 ns ns DATA FORMAT The output data from the ADS7826/27/29 family is in straight binary format. ADS7829 out is shown in Table 2, as an example. This table represents the ideal output code for the given input voltage and does not include the effects of offset, gain error, or noise. For ADS7826 the last two LSB’s are don’t cares, while for ADS7827 the last four LSB’s are don’t cares. Table 2. Ideal Input Voltages and Output Codes (ADS7829 Shown as an Example) DESCRIPTION ANALOG VALUE DIGITAL OUTPUT FULL SCALE RANGE Vref LEAST SIGNIFICANT BIT (LSB) Vref/4096 BINARY CODE STRAIGHT BINARY HEX CODE Full scale Vref - 1 LSB 1111 1111 1111 FFF Midscale Vref/2 1000 0000 0000 800 Midscale - 1 LSB Vref/2 - 1 LSB 0111 1111 1111 7FF Zero 0V 0000 0000 0000 000 15 www.ti.com ADS7826 ADS7827 ADS7829 www.ti.com SLAS388 – JUNE 2003 1.4 V 3 k VOH DOUT DOUT VOL Test Point tr 100 pF CLOAD tf Voltage Waveforms for DOUT Rise and Fall Times, tr, tf Load Circuit for tdDO, tr, and tf Test Point VIL DCLOCK VCC tdisWaveform 2, ten 3 k th(DO) DOUT VOH DOUT tdisWaveform 1 100 pF VOL CLOAD th(DO) Voltage Waveforms for DOUT Delay Times, tdDO CS/SHDN VIH DOUT Waveform 1 (1) Load Circuit for tdis and ten CS/SHDN 90% DCLOCK 1 2 tdis DOUT Waveform 2 (2) 10% DOUT VOL B11 ten Voltage Waveforms for tdis Voltage Waveforms for ten (1) Waveform 1 is for an output with internal conditions such that the output is HIGH unless disabled by the output control. (2) Waveform 2 is for an output with internal conditions such that the output is LOW unless disabled by the output control. Figure 38. Timing Diagrams and Test Circuits for the Parameters in Table 1. POWER DISSIPATION The architecture of the converter, the semiconductor fabrication process, and a careful design allows the ADS7826/27/29 family to convert at the full sample rate while requiring very little power. But, for the absolute lowest power dissipation, there are several things to keep in mind. The power dissipation of the ADS7826/27/29 family scales directly with conversion rate. Therefore, the first step to achieving the lowest power dissipation is to find the lowest conversion rate that satisfies the requirements of the system. In addition, the ADS7826/27/29 family is in power down mode under two conditions: when the conversion is complete and whenever CS is HIGH. Ideally, each conversion occurs as quickly as possible, preferably, at DCLOCK rate. 16 This way, the converter spends the longest possible time in the power down mode. This is very important as the converter not only uses power on each DCLOCK transition (as is typical for digital CMOS components) but also uses some current for the analog circuitry, such as the comparator. The analog section dissipates power continuously, until the power-down mode is entered. The current consumption of the ADS7826/27/29 family versus sample rate. For this graph, the converter is clocked at maximum DCLOCK rate regardless of the sample rate —CS is HIGH for the remaining sample period. Figure 4 also shows current consumption versus sample rate. However, in this case, the minimum DCLOCK cylce time is used—CS is HIGH for one DCLOCK cycle. ADS7826 ADS7827 ADS7829 www.ti.com SLAS388 – JUNE 2003 There is an important distinction between the power down mode that is entered after a conversion is complete and the full power-down mode which is enabled when CS is HIGH. While both shutdown the analog section, the digital section is completely shutdown only when CS is HIGH. Thus, if CS is left LOW at the end of a conversion and the converter is continually clocked, the power consumption is not as low as when CS is HIGH. Power dissipation can also be reduced by lowering the power supply voltage and the reference voltage. The ADS7826/27/29 family operates over a VCC range of 2.0 V to 5.25 V. However, at voltages below 2.7 V, the converter does not run at the maximum sample rate. See the typical performance curves for more information regarding power supply voltage and maximum sample rate. LAYOUT For optimum performance, care should be taken with the physical layout of the ADS7826/27/29 family circuitry. This is particularly true if the reference voltage is low and/or the conversion rate is high. At a 125-kHz to 250-kHz conversion rate, the ADS7826/27/29 family makes a bit decision every 800 ns to 400 ns. That is, for each subsequent bit decision, the digital output must be updated with the results of the last bit decision, the capacitor array appropriately switched and charged, and the input to the comparator settled, for example the ADS7829, to a 12-bit level all within one clock cycle. The basic SAR architecture is sensitive to spikes on the power supply, reference, and ground connections that occur just prior to latching the comparator output. Thus, during any single conversion for an n-bit SAR converter, there are n windows in which large external transient voltages can easily affect the conversion result. Such spikes might originate from switching power supplies, digital logic, and high power devices, to name a few. This particular source of error can be very difficult to track down if the glitch is almost synchronous to the converter’s DCLOCK signal—as the phase difference between the two changes with time and temperature, causing sporadic misoperation. With this in mind, power to the ADS7826/27/29 family should be clean and well bypassed. A 0.1-µF ceramic bypass capacitor should be placed as close to the ADS7826/27/29 family package as possible. In addition, a 1-µ to 10-µF capacitor and a 5-Ω or 10-Ω series resistor may be used to lowpass filter a noisy supply. The reference should be similarly bypassed with a 0.1-µF capacitor. Again, a series resistor and large capacitor can be used to lowpass filter the reference voltage. If the reference voltage originates from an op-amp, be careful that the op-amp can drive the bypass capacitor without oscillation (the series resistor can help in this case). Keep in mind that while the ADS7826/27/29 family draws very little current from the reference on average, there are still instantaneous current demands placed on the external reference circuitry. Also, keep in mind that the ADS7826/27/29 family offers no inherent rejection of noise or voltage variation in regards to the reference input. This is of particular concern when the reference input is tied to the power supply. Any noise and ripple from the supply appears directly in the digital results. While high frequency noise can be filtered out as described in the previous paragraph, voltage variation due to the line frequency (50 Hz or 60 Hz), can be difficult to remove. The GND pin on the ADS7826/27/29 family must be placed on a clean ground point. In many cases, this is the analog ground. Avoid connecting the GND pin too close to the grounding point for a microprocessor, microcontroller, or digital signal processor. If needed, run a ground trace directly from the converter to the power supply connection point. The ideal layout includes an analog ground plane for the converter and associated analog circuitry. APPLICATION CIRCUITS Figure 39 and Figure 40 show some typical application circuits the ADS7826/27/29 family. Figure 39 uses an ADS7826/27/29 and a multiplexer to provide for a flexible data acquisition circuit. A resistor string provides for various voltages at the multiplexer input. The selected voltage is buffered and driven into Vref. As shown in Figure 39, the input range of the ADS7826/27/29 family programmable to 100 mV, 200 mV, 300 mV, or 400 mV. The 100-mV range would be useful for sensors such as thermocouple shown. Figure 39 shows a basic data acquisition system. The ADS7826/27/29 family input range is 0 V to VCC, as the reference input is connected directly to the power supply. The 5-Ω resistor and 1-µF to 10-µF capacitor filters the microcontroller noise on the supply, as well as any high-frequency noise from the supply itself. The exact values should be picked such that the filter provides adequate rejection of the noise. 17 www.ti.com ADS7826 ADS7827 ADS7829 www.ti.com SLAS388 – JUNE 2003 +3 V +3 V +3 V R8 26 kΩ R1 1 TC1 C2 0.1 µ F R3 500 kΩ R2 59 kΩ 0.4 V R7 5Ω R6 1 MΩ R9 1 kΩ OPA237 0.3 V U2 C1 10 µ F VREF MUX 0.2 V DCLOCK C3 0.1 µ F TC2 ADS7826/27/29 DOUT A0 CS/SHDN A1 Thermocouple TC3 R4 1 kΩ ISO Thermal Block C4 10 µ F R10 1 kΩ U1 R5 500 Ω U3 C5 0.1 µ F R11 1 kΩ 0.1 V R12 1 kΩ µP U4 Figure 39. Thermocouple Application Using a MUX to Scale the Input Range of the ADS7826/27/29 family +2.7V to +3.6V 5 + 1 F to 10 F ADS7826/27/29 VREF VCC +In CS –In DOUT 0.1 F GND + 1 F to 10 F Microcontroller DCLOCK Figure 40. Basic Data Acquisition System 18 PACKAGE OPTION ADDENDUM www.ti.com 5-Feb-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) ADS7826IDRBR ACTIVE SON DRB 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 F26 ADS7826IDRBRG4 ACTIVE SON DRB 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 F26 ADS7826IDRBT ACTIVE SON DRB 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 F26 ADS7826IDRBTG4 ACTIVE SON DRB 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 F26 ADS7827IDRBR ACTIVE SON DRB 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 F27 ADS7827IDRBRG4 ACTIVE SON DRB 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 F27 ADS7827IDRBT ACTIVE SON DRB 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 F27 ADS7827IDRBTG4 ACTIVE SON DRB 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 F27 ADS7829IBDRBR ACTIVE SON DRB 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 F29 ADS7829IBDRBRG4 ACTIVE SON DRB 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 F29 ADS7829IBDRBT ACTIVE SON DRB 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 F29 ADS7829IBDRBTG4 ACTIVE SON DRB 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 F29 ADS7829IDRBR ACTIVE SON DRB 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 F29 ADS7829IDRBRG4 ACTIVE SON DRB 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 F29 ADS7829IDRBT ACTIVE SON DRB 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 F29 ADS7829IDRBTG4 ACTIVE SON DRB 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 F29 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 5-Feb-2015 LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing ADS7826IDRBR SON DRB 8 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 2500 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 ADS7826IDRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 ADS7827IDRBR SON DRB 8 2500 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 ADS7827IDRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 ADS7829IBDRBR SON DRB 8 2500 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 ADS7829IBDRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 ADS7829IDRBR SON DRB 8 2500 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 ADS7829IDRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS7826IDRBR SON DRB 8 2500 367.0 367.0 35.0 ADS7826IDRBT SON DRB 8 250 210.0 185.0 35.0 ADS7827IDRBR SON DRB 8 2500 367.0 367.0 35.0 ADS7827IDRBT SON DRB 8 250 210.0 185.0 35.0 ADS7829IBDRBR SON DRB 8 2500 367.0 367.0 35.0 ADS7829IBDRBT SON DRB 8 250 210.0 185.0 35.0 ADS7829IDRBR SON DRB 8 2500 367.0 367.0 35.0 ADS7829IDRBT SON DRB 8 250 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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