Stereo PDM-to-I2S or TDM Conversion IC ADAU7002 Data Sheet FEATURES GENERAL DESCRIPTION 64× decimation of a stereo pulse density modulation (PDM) bit stream to pulse code modulation (PCM) audio data Slave I2S or time division multiplexed (TDM) output interface Configurable TDM slots I/O supply operation: 1.62 V to 3.6 V 64× output sample rate PDM clock 64×/128×/192×/256×/384×/512× output sample rate BCLK Automatic BCLK ratio detection Output sample rate: 4 kHz to 96 kHz Automatic PDM CLK drive at 64× the sample rate Automatic power down with BCLK removal 0.67 mA operating current at 48 kHz and 1.8 V IOVDD supply Shutdown current: <1 µA 8-ball, 1.56 mm × 0.76 mm, 0.4 mm pitch WLCSP Power-on reset The ADAU7002 converts a stereo PDM bit stream into a PCM output. The source for the PDM data can be two microphones or other PDM sources. The PCM audio data is output on a serial audio interface port in either I2S or TDM format. The ADAU7002 is specified over the commercial temperature range (−40°C to +85°C). It is available in a halide-free, 8-ball, 1.56 mm × 0.76 mm, wafer level chip scale package (WLCSP). APPLICATIONS Mobile computing Portable electronics Consumer electronics FUNCTIONAL BLOCK DIAGRAM 1.62V TO 3.6V CONFIG GND IOVDD PDM_CLK BCLK PDM INPUT PORT DIGITAL DECIMATION FILTERING I2S OUTPUT PORT SDATA ADAU7002 11265-001 PDM_DAT LRCLK Figure 1. Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. 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Technical Support www.analog.com ADAU7002 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Pin Configuration and Function Descriptions..............................5 Applications ....................................................................................... 1 Typical Performance Characteristics ..............................................6 General Description ......................................................................... 1 Typical Application Circuits ............................................................8 Functional Block Diagram .............................................................. 1 Applications Information .................................................................9 Revision History ............................................................................... 2 Overview ........................................................................................9 Specifications..................................................................................... 3 Clocking..........................................................................................9 Absolute Maximum Ratings ............................................................ 4 Serial Audio Output Interface .....................................................9 Thermal Resistance ...................................................................... 4 Outline Dimensions ....................................................................... 13 ESD Caution .................................................................................. 4 Ordering Guide .......................................................................... 13 REVISION HISTORY 1/13—Revision 0: Initial Version Rev. 0 | Page 2 of 16 Data Sheet ADAU7002 SPECIFICATIONS IOVDD = 1.8 V, TA = 25°C, BCLK = 3.072 MHz, output = 48 kHz, I2S format, unless otherwise noted. Table 1. Parameter DIGITAL INPUT/OUTPUT High Level Input Voltage (VIH) Low Level Input Voltage (VIL) Input Leakage, High (IIH) Input Leakage, Low (IIL) Input Capacitance SDATA PDM_CLK PERFORMANCE Dynamic Range With A-Weighted Filter (RMS) Signal-to-Noise-Ratio Decimation Ratio Frequency Response Stop Band Stop-Band Attenuation Group Delay Gain Start-Up Time Bit Width Interchannel Phase CLOCKING Output Sampling Rate BCLK Frequency POWER SUPPLIES Supply Voltage Range Supply Current Shutdown Current Test Conditions/Comments Min Typ Max Unit 1 1 5 V V µA µA pF mA mA 0.7 × IOVDD 0.3 × IOVDD BCLK and LRCLK pins BCLK and LRCLK pins 4.5 9 20 Hz to 20 kHz, −60 dB input 110 110 64× A-weighted, fourth-order input DC to 0.45 output fS −0.1 dB dB +0.01 0.566 60 0.02 fS input signal PDM to PCM 3.31 0 48 20 0 Internal and output fS LRCLK pulse rate fBCLK 4 0.256 IOVDD IOVDDSY = 1.8 V IOVDD = 3.3 V IOVDD = 1.8 V, 16 kHz output IOVDD = 3.3 V, 16 kHz output IOVDDSD, no input clocks 1.62 Rev. 0 | Page 3 of 16 48 3.072 0.67 1.33 0.21 0.41 1 dB fS dB LRCLK cycles dB LRCLK cycles Bits Degrees 96 24.576 kHz MHz 3.6 V mA mA mA mA µA ADAU7002 Data Sheet ABSOLUTE MAXIMUM RATINGS Absolute maximum ratings apply at 25°C, unless otherwise noted. THERMAL RESISTANCE Table 2. θJA (junction to air) is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. θJA is determined according to JESD51-9 on a 4-layer printed circuit board (PCB) with natural convection cooling. Parameter IOVDD Supply Voltage Input Voltage ESD Susceptibility Storage Temperature Range Operating Temperature Range Junction Temperature Range Lead Temperature (Soldering, 60 sec) Rating 3.6 V 3.6 V 4 kV −65°C to +150°C −40°C to +85°C −65°C to +165°C 300°C Table 3. Thermal Resistance Package Type 8-ball, 1.56 mm × 0.76 mm WLCSP Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION Rev. 0 | Page 4 of 16 θJA 90 Unit °C/W Data Sheet ADAU7002 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 A PDM_ DAT PDM_ CLK B SDATA BCLK C GND LRCLK D IOVDD CONFIG 11265-002 BALL A1 CORNER TOP VIEW (BALL SIDE DOWN) Figure 2. Pin Configuration (Top Side View) Table 4. Pin Function Descriptions Pin No. A1 A2 B1 B2 C1 C2 D1 D2 Mnemonic PDM_DAT PDM_CLK SDATA BCLK GND LRCLK IOVDD CONFIG Type Input Output Output Input Ground Input Supply Input Description PDM Data Input PDM Clock Output Serial Data Output for I2S/TDM Bit Clock for I2S/TDM Ground Left/Right Clock for I2S/Frame Sync for TDM Input/Output and Digital Supply Configuration Pin Rev. 0 | Page 5 of 16 ADAU7002 Data Sheet 0 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 –160 –170 –180 –190 –20 THD + N (dBFS) –40 CH1 CH2 –60 –80 –100 100 1k FREQUENCY (Hz) 10k 20k –140 0.0001 0.01 0.1 1 Figure 6. Total Harmonic Distortion + Noise (THD + N) vs. Normalized Frequency (Relative to fS) 0.1 0 0 –20 THD + N LEVEL (dBFS) LEVEL (dBFS) Figure 3. FFT, fS = 48 kHz, −60 dBFS Input –0.1 –0.2 –0.3 –0.4 –40 –60 –80 –100 0.001 0.01 0.1 1 NORMALIZED FREQUENCY (RELATIVE TO fS) (Hz) –120 –120 11265-004 –0.5 0.0001 0.001 NORMALIZED FREQUENCY (RELATIVE TO fS) (Hz) –100 –80 –60 –40 –20 0 GENERATOR LEVEL (dBFS) 11265-007 20 11265-006 –120 11265-003 LEVEL (dBFS) TYPICAL PERFORMANCE CHARACTERISTICS Figure 7. THD + N Level vs. Generator Level Figure 4. Frequency Response 1.4 160 1.3 140 1.2 SUPPLY CURRENT (mA) 100 80 60 40 1.1 1.0 0.9 0.8 0.7 0.6 20 0.001 0.01 0.1 1 NORMALIZED FREQUENCY (RELATIVE TO fS) (Hz) 0.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 SUPPLY VOLTAGE (V) Figure 8. Supply Current vs. Supply Voltage Figure 5. Group Delay vs. Normalized Frequency (Relative to fS) Rev. 0 | Page 6 of 16 3.2 3.4 11265-009 0 0.0001 0.5 11265-005 GROUP DELAY (µs) 120 Data Sheet ADAU7002 0 –20 –60 –80 –100 –120 –140 –160 0 0.5 1.0 FREQUENCY (MHz) 1.5 11265-010 MAGNITUDE (dB) –40 Figure 9. Out-of-Band Frequency Response (48 kHz Output) Rev. 0 | Page 7 of 16 ADAU7002 Data Sheet TYPICAL APPLICATION CIRCUIT IOVDD 0.1µF IOVDD PDM_CLK PDM_CLK PDM_DAT PDM_DAT LRCLK BCLK LRCLK BCLK ADAU7002 SDATA CONFIG SDATA GND OPTIONAL PULL-DOWN RESISTOR 11265-011 CONFIG Figure 10. Typical Application Circuit Rev. 0 | Page 8 of 16 Data Sheet ADAU7002 APPLICATIONS INFORMATION OVERVIEW Table 5. PDM Timing Parameters The ADAU7002 provides stereo decimation from a 1-bit PDM source to a 20-bit PCM audio. The downsampling ratio is fixed at 64×. The 20-bit downsampled PCM audio is output via standard I2S or TDM formats. Parameter Data Setup Time, tSETUP Data Hold Time, tHOLD tMIN 10 7 tMAX Unit ns ns PDM data is latched on both edges of the clock. The input source for the ADAU7002 can be any device that has a PDM output, such as a digital microphone like the ADMP521. The output pins of these microphones can connect directly to the input pins of the ADAU7002. PDM_CLK tHOLD CLOCKING The ADAU7002 requires a BCLK rate that is a minimum of 64× the LRCLK sample rate. BCLK rates of 128×, 192×, 256×, 384×, and 512× the LRCLK rate are also supported. The ADAU7002 automatically detects the ratio between BCLK and LRCLK and generates a PDM clock output at 64× the LRCLK rate. The minimum sample rate is 4 kHz, and the maximum is 96 kHz, which correspond to a PDM clock range of 256 kHz to 6.144 MHz. Internally, all processing is done at the PDM_CLK rate. PDM_DAT R L R L 11265-012 tSETUP Figure 11. PDM Timing Diagram SERIAL AUDIO OUTPUT INTERFACE The ADAU7002 supports I2S and TDM serial output formats. Format selection and TDM slot placement is set with the CONFIG pin. The SDATA pin is in tristate mode, except when the port is driving serial data based on the CONFIG pin configuration. When BCLK is removed, the ADAU7002 powers down automatically. When BCLK is not present, the PDM_CLK output stops. Table 6. TDM Slot Selection Device Setting I2S Format TDM Slot 1 to Slot 2 Used/Driven, 32-Bit Slots TDM Slot 3 to Slot 4 Used/Driven, 32-Bit Slots TDM Slot 5 to Slot 6 Used/Driven, 32-Bit Slots CONFIG Pin Configuration Tie to IOVDD Tie to GND Open Tie to IOVDD through a 47 kΩ resistor TDM Slot 7 to Slot 8 Used/Driven, 32-Bit Slots Tie to GND through a 47 kΩ resistor Rev. 0 | Page 9 of 16 ADAU7002 Data Sheet Serial Port Timing tBIH BCLK tBIL tLIH tLIS LRCLK tSODM MSB MSB – 1 tSODM SDATA I2S JUSTIFIED MODE 11265-013 SDATA TDM MODE MSB Figure 12. Serial Port Timing Diagram Table 7. I2S/TDM Timing Parameters Parameter BCLK Pulse Width High BCLK Pulse Width Low LRCLK Setup Time LRCLK Hold Time Time from BCLK Falling Symbol tBIH tBIL tLIS tLIH tSODM tMIN 10 10 10 10 tMAX Unit ns ns ns ns ns 10 LRCLK BCLK 32 BCLKs I2S LEFT CHANNEL I2S RIGHT CHANNEL TRISTATE TRISTATE 11265-014 SDATA 20 BCLKs Figure 13. I2S, CONFIG Pin Tied to IOVDD LRCLK BCLK 32 BCLKs LEFT RIGHT TRISTATE TRISTATE TRISTATE TRISTATE TRISTATE TRISTATE SLOT 3 SLOT 4 SLOT 5 SLOT 6 SLOT 7 SLOT 8 20 BCLKs SLOT 1 SLOT 2 Figure 14. TDM8 Channel 1 and Channel 2, CONFIG Pin Tied to GND Rev. 0 | Page 10 of 16 11265-015 SDATA Data Sheet ADAU7002 LRCLK BCLK 32 BCLKs SDATA TRISTATE TRISTATE LEFT RIGHT TRISTATE TRISTATE TRISTATE TRISTATE SLOT 5 SLOT 6 SLOT 7 SLOT 8 TRISTATE TRISTATE SLOT 7 SLOT 8 SLOT 1 SLOT 2 SLOT 3 SLOT 4 11265-016 20 BCLKs Figure 15. TDM8 Channel 3 and Channel 4, CONFIG Pin Open LRCLK BCLK 32 BCLKs SDATA TRISTATE TRISTATE TRISTATE TRISTATE LEFT RIGHT SLOT 1 SLOT 2 SLOT 3 SLOT 4 SLOT 5 SLOT 6 11265-017 20 BCLKs Figure 16. TDM8 Channel 5 to Channel 6, CONFIG Pin Tied to IOVDD Through a 47 kΩ Resistor LRCLK BCLK 32 BCLKs TRISTATE TRISTATE TRISTATE TRISTATE TRISTATE TRISTATE LEFT RIGHT 20 BCLKs SLOT 1 SLOT 2 SLOT 3 SLOT 4 SLOT 5 SLOT 6 SLOT 7 Figure 17. TDM8 Channel 7 and Channel 8, CONFIG Pin Tied to GND Through a 47 kΩ Resistor Rev. 0 | Page 11 of 16 SLOT 8 11265-018 SDATA ADAU7002 Data Sheet LRCLK BCLK 32 BCLKs SDATA LEFT RIGHT TRISTATE TRISTATE SLOT 3 SLOT 4 SLOT 1 SLOT 2 11265-019 20 BCLKs Figure 18. TDM4 Channel 1 and Channel 2, CONFIG Pin Tied to IOVDD LRCLK BCLK 32 BCLKs TRISTATE TRISTATE LEFT RIGHT SLOT 1 SLOT 2 SLOT 3 SLOT 4 Figure 19. TDM4 Channel 3 and Channel 4, CONFIG Pin Open LRCLK BCLK 32 BCLKs SDATA LEFT RIGHT 20 BCLKs SLOT 1 SLOT 2 Figure 20. TDM2 Channel 1 and Channel 2, CONFIG Pin Tied to IOVDD Rev. 0 | Page 12 of 16 11265-020 20 BCLKs 11265-021 SDATA Data Sheet ADAU7002 OUTLINE DIMENSIONS 0.800 0.760 0.720 BOTTOM VIEW ORIENTATION IDENTIFIER (BALL SIDE UP) 2 1 A BALL A1 IDENTIFIER 1.600 1.560 1.520 1.20 REF B C 0.40 BSC 0.40 BSC TOP VIEW (BALL SIDE DOWN) SIDE VIEW SEATING PLANE 0.330 0.300 0.270 COPLANARITY 0.05 0.3000 0.260 0.220 0.230 0.200 0.170 01-21-2012-A 0.560 0.500 0.440 D Figure 21. 8-Ball Wafer Level Chip Scale Package [WLCSP] (CB-8-6) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADAU7002ACBZ-R7 ADAU7002ACBZ-RL EVAL-ADAU7002Z 1 Temperature Range −40°C to +85°C −40°C to +85°C Package Description 8-Ball Wafer Level Chip Scale Package [WLCSP], 7” Tape and Reel 8-Ball Wafer Level Chip Scale Package [WLCSP], 13” Tape and Reel Evaluation Board Z = RoHS Compliant Part. Rev. 0 | Page 13 of 16 Package Option CB-8-6 CB-8-6 Branding BE BE ADAU7002 Data Sheet NOTES Rev. 0 | Page 14 of 16 Data Sheet ADAU7002 NOTES Rev. 0 | Page 15 of 16 ADAU7002 Data Sheet NOTES ©2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D11265-0-1/13(0) Rev. 0 | Page 16 of 16