PSoC® 3: CY8C32 Family Data Sheet
®
Programmable System-on-Chip (PSoC )
General Description
PSoC® 3 is a true programmable embedded system-on-chip, integrating configurable analog and digital peripherals, memory, and a
microcontroller on a single chip. The PSoC 3 architecture boosts performance through:
8051 core plus DMA controller at up to 50 MHz
Ultra low power with industry's widest voltage range
Programmable digital and analog peripherals enable custom functions
Flexible routing of any analog or digital peripheral function to any pin
PSoC devices employ a highly configurable system-on-chip architecture for embedded control design. They integrate configurable
analog and digital circuits, controlled by an on-chip microcontroller. A single PSoC device can integrate as many as 100 digital and
analog peripheral functions, reducing design time, board space, power consumption, and system cost while improving system quality.
Features
Operating characteristics
Analog peripherals
Voltage range: 1.71 to 5.5 V, up to six power domains
[1]
Temperature range (ambient) –40 to 85 °C
DC to 50-MHz operation
Power modes
• Active mode 1.2 mA at 6 MHz, and 12 mA at 48 MHz
• 1-µA sleep mode
• 200-nA hibernate mode with RAM retention
Boost regulator from 0.5-V input up to 5-V output
Performance
8-bit 8051 CPU, 32 interrupt inputs
24-channel direct memory access (DMA) controller
Configurable 8- to 12-bit delta-sigma ADC
8-bit DAC
Two comparators
®
CapSense support, up to 62 sensors
1.024 V ±1% internal voltage reference
Memories
Up to 64 KB program flash, with cache and security features
Up to 8 KB additional flash for error correcting code (ECC)
Up to 8 KB RAM
Up to 2 KB EEPROM
Digital peripherals
Four 16-bit timer, counter, and PWM (TCPWM) blocks
I2C, 1 Mbps bus speed
USB 2.0 certified Full-Speed (FS) 12 Mbps peripheral
interface (TID#40770053) using internal oscillator[2]
16 to 24 universal digital blocks (UDB), programmable to
create any number of functions:
• 8-, 16-, 24-, and 32-bit timers, counters, and PWMs
• I2C, UART, SPI, I2S, LIN 2.0 interfaces
• Cyclic redundancy check (CRC)
• Pseudo random sequence (PRS) generators
• Quadrature decoders
• Gate-level logic functions
Versatile I/O system
29 to 72 I/O pins – up to 62 general-purpose I/Os (GPIOs)
Up to eight performance I/O (SIO) pins
• 25 mA current sink
• Programmable input threshold and output high voltages
• Can act as a general-purpose comparator
• Hot swap capability and overvoltage tolerance
Up to two USBIO pins that can be used as GPIOs
Route any digital or analog peripheral to any GPIO
LCD direct drive from any GPIO, up to 46 × 16 segments
CapSense support from any GPIO
1.2-V to 5.5-V interface voltages, up to four power domains
Programming and debug
JTAG (4-wire), serial wire debug (SWD) (2-wire), and single
wire viewer (SWV) interfaces
2
Bootloader programming through I C, SPI, UART, USB, and
other interfaces
Package options: 48-pin SSOP, 48-pin QFN, 68-pin QFN,
100-pin TQFP, and 72-pin WLCSP
Development support with free PSoC Creator™ tool
Programmable clocking
3- to 24-MHz internal oscillator, 2% accuracy at 3 MHz
4- to 25-MHz external crystal oscillator
Internal PLL clock generation up to 50 MHz
Low-power internal oscillator at 1, 33, and 100 kHz
32.768-kHz external watch crystal oscillator
12 clock dividers routable to any peripheral or I/O
Schematic and firmware design support
Over 100 PSoC Components™ integrate multiple ICs and
system interfaces into one PSoC. Components are free
embedded ICs represented by icons. Drag and drop
component icons to design systems in PSoC Creator.
Includes free Keil 8051 compiler
Supports device programming and debugging
Notes
1. The maximum storage temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. This feature on select devices only. See Ordering Information on page 111 for details.
Cypress Semiconductor Corporation
Document Number: 001-56955 Rev. *Y
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 27, 2016
PSoC® 3: CY8C32 Family Data Sheet
More Information
Cypress provides a wealth of data at www.cypress.com to help you to select the right PSoC device for your design, and to help you
to quickly and effectively integrate the device into your design. For a comprehensive list of resources, see the knowledge base article
KBA86521, How to Design with PSoC 3, PSoC 4, and PSoC 5LP. Following is an abbreviated list for PSoC 3:
Overview: PSoC Portfolio, PSoC Roadmap
Product Selectors: PSoC 1, PSoC 3, PSoC 4, PSoC 5LP
In addition, PSoC Creator includes a device selection tool.
Application notes: Cypress offers a large number of PSoC
application notes and code examples covering a broad range
of topics, from basic to advanced level. Recommended application notes for getting started with PSoC 3 are:
AN54181: Getting Started With PSoC 3
AN61290: Hardware Design Considerations
AN57821: Mixed Signal Circuit Board Layout
AN58304: Pin Selection for Analog Designs
AN81623: Digital Design Best Practices
AN73854: Introduction To Bootloaders
Development Kits:
CY8CKIT-030 is designed for analog performance, for developing high-precision analog, low-power, and low-voltage applications.
CY8CKIT-001 provides a common development platform for
any one of the PSoC 1, PSoC 3, PSoC 4, or PSoC 5LP
families of devices.
The MiniProg3 device provides an interface for flash programming and debug.
Technical Reference Manuals (TRM)
Architecture TRM
Registers TRM
Programming Specification
PSoC Creator
PSoC Creator is a free Windows-based Integrated Design Environment (IDE). It enables concurrent hardware and firmware design
of PSoC 3, PSoC 4, and PSoC 5LP based systems. Create designs using classic, familiar schematic capture supported by over 100
pre-verified, production-ready PSoC Components; see the list of component datasheets. With PSoC Creator, you can:
1. Drag and drop component icons to build your hardware
3. Configure components using the configuration tools
system design in the main design workspace
4. Explore the library of 100+ components
2. Codesign your application firmware with the PSoC hardware,
5. Review component datasheets
using the PSoC Creator IDE C compiler
Figure 1. Multiple-Sensor Example Project in PSoC Creator
Document Number: 001-56955 Rev. *Y
Page 2 of 128
PSoC® 3: CY8C32 Family Data Sheet
Contents
1. Architectural Overview ..................................................... 4
2. Pinouts ............................................................................... 6
3. Pin Descriptions .............................................................. 12
4. CPU ................................................................................... 13
4.1 8051 CPU ................................................................. 13
4.2 Addressing Modes .................................................... 13
4.3 Instruction Set .......................................................... 14
4.4 DMA and PHUB ....................................................... 18
4.5 Interrupt Controller ................................................... 20
5. Memory ............................................................................. 24
5.1 Static RAM ............................................................... 24
5.2 Flash Program Memory ............................................ 24
5.3 Flash Security ........................................................... 24
5.4 EEPROM .................................................................. 24
5.5 Nonvolatile Latches (NVLs) ...................................... 25
5.6 External Memory Interface ....................................... 26
5.7 Memory Map ............................................................ 26
6. System Integration .......................................................... 28
6.1 Clocking System ....................................................... 28
6.2 Power System .......................................................... 31
6.3 Reset ........................................................................ 36
6.4 I/O System and Routing ........................................... 37
9. Programming, Debug Interfaces, Resources ................ 62
9.1 JTAG Interface ......................................................... 62
9.2 Serial Wire Debug Interface ..................................... 64
9.3 Debug Features ........................................................ 65
9.4 Trace Features ......................................................... 65
9.5 Single Wire Viewer Interface .................................... 65
9.6 Programming Features ............................................. 65
9.7 Device Security ........................................................ 65
9.8 CSP Package Bootloader ......................................... 66
10. Development Support ................................................... 66
10.1 Documentation ....................................................... 66
10.2 Online ..................................................................... 66
10.3 Tools ....................................................................... 66
11. Electrical Specifications ............................................... 67
11.1 Absolute Maximum Ratings .................................... 67
11.2 Device Level Specifications .................................... 68
11.3 Power Regulators ................................................... 72
11.4 Inputs and Outputs ................................................. 76
11.5 Analog Peripherals ................................................. 84
11.6 Digital Peripherals .................................................. 96
11.7 Memory .................................................................. 99
11.8 PSoC System Resources ..................................... 105
11.9 Clocking ................................................................ 107
7. Digital Subsystem ........................................................... 45
7.1 Example Peripherals ................................................ 45
7.2 Universal Digital Block .............................................. 47
7.3 UDB Array Description ............................................. 50
7.4 DSI Routing Interface Description ............................ 50
7.5 USB .......................................................................... 52
7.6 Timers, Counters, and PWMs .................................. 52
7.7 I2C ............................................................................ 53
12. Ordering Information ................................................... 111
12.1 Part Numbering Conventions ............................... 112
8. Analog Subsystem .......................................................... 55
8.1 Analog Routing ......................................................... 56
8.2 Delta-sigma ADC ...................................................... 58
8.3 Comparators ............................................................. 59
8.4 LCD Direct Drive ...................................................... 60
8.5 CapSense ................................................................. 61
8.6 Temp Sensor ............................................................ 61
8.7 DAC .......................................................................... 61
17. Revision History .......................................................... 120
Document Number: 001-56955 Rev. *Y
13. Packaging ..................................................................... 113
14. Acronyms ..................................................................... 117
15. Reference Documents ................................................. 118
16. Document Conventions .............................................. 119
16.1 Units of Measure .................................................. 119
18. Sales, Solutions, and Legal Information ................... 128
Worldwide Sales and Design Support.......................... 128
Products ....................................................................... 128
PSoC® Solutions ......................................................... 128
Cypress Developer Community.................................... 128
Technical Support ........................................................ 128
Page 3 of 128
PSoC® 3: CY8C32 Family Data Sheet
1. Architectural Overview
Introducing the CY8C32 family of ultra low-power, flash Programmable System-on-Chip (PSoC®) devices, part of a scalable 8-bit
PSoC 3 and 32-bit PSoC 5 platform. The CY8C32 family provides configurable blocks of analog, digital, and interconnect circuitry
around a CPU subsystem. The combination of a CPU with a flexible analog subsystem, digital subsystem, routing, and I/O enables
a high level of integration in a wide variety of consumer, industrial, and medical applications.
Figure 1-1. Simplified Block Diagram
Analog Interconnect
Quadrature Decoder
UDB
Sequencer
Usage Example for UDB
IMO
I2C
Universal Digital Block Array (24 x UDB)
8- Bit
Timer
UDB
UDB
UDB
16- Bit
PWM
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
22
UDB
8- Bit
Timer
Logic
UDB
8- Bit SPI
I2C Slave
Master/
Slave
16- Bit PRS
FS USB
2.0
USB
PHY
12- Bit SPI
UDB
UDB
UDB
UDB
Logic
UDB
UDB
UDB
UART
UDB
GPIOs
GPIOs
Clock Tree
32.768 KHz
( Optional)
Digital System
System Wide
Resources
Xtal
Osc
SIO
4- 25 MHz
( Optional)
GPIOs
Digital Interconnect
12- Bit PWM
RTC
Timer
System Bus
GPIOs
EEPROM
EMIF
SRAM
CPU System
8051 or
Cortex M3
CPU
Interrupt
Controller
Program
Debug &
Trace
PHUB
DMA
FLASH
ILO
Program &
Debug
GPIOs
Memory System
WDT
and
Wake
Boundary
Scan
Clocking System
GPIOs
SIOs
Analog System
Power Management
System
LCD Direct
Drive
ADC
POR and
LVD
1.8V LDO
1x
Del Sig
ADC
Temperature
Sensor
DAC
SMP
+
2x
CMP
-
GPIOs
1.71 to
5.5V
Sleep
Power
CapSense
0. 5 to 5.5V
( Optional)
Figure 1-1 illustrates the major components of the CY8C32
family. They are:
8051 CPU subsystem
Nonvolatile subsystem
Programming, debug, and test subsystem
Inputs and outputs
Clocking
Power
PSoC’s digital subsystem provides half of its unique
configurability. It connects a digital signal from any peripheral to
any pin through the Digital System Interconnect (DSI). It also
provides functional flexibility through an array of small, fast,
low-power UDBs. PSoC Creator provides a library of prebuilt and
tested standard digital peripherals (UART, SPI, LIN, PRS, CRC,
timer, counter, PWM, AND, OR, and so on) that are mapped to
the UDB array. You can also easily create a digital circuit using
boolean primitives by means of graphical design entry. Each
UDB contains programmable array logic (PAL)/programmable
logic device (PLD) functionality, together with a small state
machine engine to support a wide variety of peripherals.
Digital subsystem
Analog subsystem
Document Number: 001-56955 Rev. *Y
Page 4 of 128
PSoC® 3: CY8C32 Family Data Sheet
In addition to the flexibility of the UDB array, PSoC also provides
configurable digital blocks targeted at specific functions. For the
CY8C32 family these blocks can include four 16-bit timers,
counters, and PWM blocks; I2C slave, master, and multimaster;
and FS USB.
For more details on the peripherals see the “Example
Peripherals” section on page 45 of this datasheet. For
information on UDBs, DSI, and other digital blocks, see the
“Digital Subsystem” section on page 45 of this datasheet.
PSoC’s analog subsystem is the second half of its unique
configurability. All analog performance is based on a highly
accurate absolute voltage reference with less than 1-percent
error over temperature and voltage. The configurable analog
subsystem includes:
Analog muxes
Comparators
Voltage references
ADC
DAC
All GPIO pins can route analog signals into and out of the device
using the internal analog bus. This allows the device to interface
up to 62 discrete analog signals. The heart of the analog
subsystem is a fast, accurate, configurable delta-sigma ADC
with these features:
Less than 100 µV offset
A gain error of 0.2 percent
INL less than ±1 LSB
DNL less than ±1 LSB
SINAD better than 66 dB
This converter addresses a wide variety of precision analog
applications, including some of the most demanding sensors.
A high-speed voltage or current DAC supports 8-bit output
signals at an update rate of 8 Msps in current DAC (IDAC) and
1 Msps in voltage DAC (VDAC). It can be routed out of any GPIO
pin. You can create higher resolution voltage PWM DAC outputs
using the UDB array. This can be used to create a pulse width
modulated (PWM) DAC of up to 10 bits, at up to 48 kHz. The
digital DACs in each UDB support PWM, PRS, or delta-sigma
algorithms with programmable widths.
In addition to the ADC and DAC, the analog subsystem provides
multiple comparators.
See the “Analog Subsystem” section on page 55 of this
datasheet for more details.
PSoC’s 8051 CPU subsystem is built around a single cycle
pipelined 8051 8-bit processor running at up to 50 MHz. The
CPU subsystem includes a programmable nested vector
interrupt controller, DMA controller, and RAM. PSoC’s nested
vector interrupt controller provides low latency by allowing the
CPU to vector directly to the first address of the interrupt service
routine, bypassing the jump instruction required by other
architectures. The DMA controller enables peripherals to
exchange data without CPU involvement. This allows the CPU
to run slower (saving power) or use those CPU cycles to improve
the performance of firmware algorithms. The single cycle 8051
CPU runs ten times faster than a standard 8051 processor. The
processor speed itself is configurable, allowing you to tune active
power consumption for specific applications.
PSoC’s nonvolatile subsystem consists of flash, byte-writeable
EEPROM, and nonvolatile configuration options. It provides up
to 64 KB of on-chip flash. The CPU can reprogram individual
blocks of flash, enabling bootloaders. You can enable an ECC
for high reliability applications. A powerful and flexible protection
model secures the user's sensitive information, allowing
selective memory block locking for read and write protection. Up
to 2 KB of byte-writeable EEPROM is available on-chip to store
application data. Additionally, selected configuration options
such as boot speed and pin drive mode are stored in nonvolatile
memory. This allows settings to activate immediately after POR.
The three types of PSoC I/O are extremely flexible. All I/Os have
many drive modes that are set at POR. PSoC also provides up
to four I/O voltage domains through the VDDIO pins. Every GPIO
has analog I/O, LCD drive[3], CapSense[4], flexible interrupt
generation, slew rate control, and digital I/O capability. The SIOs
on PSoC allow Voh to be set independently of VDDIO when used
as outputs. When SIOs are in input mode they are high
impedance. This is true even when the device is not powered or
when the pin voltage goes above the supply voltage. This makes
the SIO ideally suited for use on an I2C bus where the PSoC may
not be powered when other devices on the bus are. The SIO pins
also have high current sink capability for applications such as
LED drives. The programmable input threshold feature of the
SIO can be used to make the SIO function as a general purpose
analog comparator. For devices with FS USB the USB physical
interface is also provided (USBIO). When not using USB these
pins may also be used for limited digital functionality and device
programming. All of the features of the PSoC I/Os are covered
in detail in the “I/O System and Routing” section on page 37 of
this datasheet.
The PSoC device incorporates flexible internal clock generators,
designed for high stability and factory trimmed for high accuracy.
The Internal Main Oscillator (IMO) is the clock base for the
system, and has 2-percent accuracy at 3 MHz. The IMO can be
configured to run from 3 MHz up to 24 MHz. Multiple clock
derivatives can be generated from the main clock frequency to
meet application needs. The device provides a PLL to generate
clock frequencies up to 50 MHz from the IMO, external crystal,
or external reference clock. It also contains a separate, very
low-power Internal Low-Speed Oscillator (ILO) for the sleep and
watchdog timers. A 32.768-kHz external watch crystal is also
supported for use in RTC applications. The clocks, together with
programmable clock dividers, provide the flexibility to integrate
most timing requirements.
The CY8C32 family supports a wide supply operating range from
1.71 V to 5.5 V. This allows operation from regulated supplies
such as 1.8 ± 5 percent, 2.5 V ±10 percent, 3.3 V ± 10 percent,
or 5.0 V ± 10 percent, or directly from a wide range of battery
types. In addition, it provides an integrated high efficiency
synchronous boost converter that can power the device from
supply voltages as low as 0.5 V.
Notes
3. This feature on select devices only. See Ordering Information on page 111 for details.
4. GPIOs with opamp outputs are not recommended for use with CapSense.
Document Number: 001-56955 Rev. *Y
Page 5 of 128
PSoC® 3: CY8C32 Family Data Sheet
This enables the device to be powered directly from a single
battery or solar cell. In addition, you can use the boost converter
to generate other voltages required by the device, such as a
3.3-V supply for LCD glass drive. The boost’s output is available
on the VBOOST pin, allowing other devices in the application to
be powered from the PSoC.
PSoC supports a wide range of low-power modes. These include
a 200-nA hibernate mode with RAM retention and a 1-µA sleep
mode with RTC. In the second mode the optional 32.768-kHz
watch crystal runs continuously and maintains an accurate RTC.
Power to all major functional blocks, including the programmable
digital and analog peripherals, can be controlled independently
by firmware. This allows low-power background processing
when some peripherals are not in use. This, in turn, provides a
total device current of only 1.2 mA when the CPU is running at
6 MHz, or 0.8 mA running at 3 MHz.
2. Pinouts
Each VDDIO pin powers a specific set of I/O pins. (The USBIOs
are powered from VDDD.) Using the VDDIO pins, a single PSoC
can support multiple voltage levels, reducing the need for
off-chip level shifters. The black lines drawn on the pinout
diagrams in Figure 2-3 through Figure 2-6, as well as Table 2-1,
show the pins that are powered by each VDDIO.
Each VDDIO may source up to 100 mA total to its associated I/O
pins, as shown in Figure 2-1.
Figure 2-1. VDDIO Current Limit
IDDIO X = 100 mA
VDDIO X
I/O Pins
The details of the PSoC power modes are covered in the “Power
System” section on page 31 of this datasheet.
PSoC uses JTAG (4-wire) or SWD (2-wire) interfaces for
programming, debug, and test. The 1-wire SWV may also be
used for “printf” style debugging. By combining SWD and SWV,
you can implement a full debugging interface with just three pins.
Using these standard interfaces enables you to debug or
program the PSoC with a variety of hardware solutions from
Cypress or third party vendors. PSoC supports on-chip break
points and 4-KB instruction and data race memory for debug.
Details of the programming, test, and debugging interfaces are
discussed in the “Programming, Debug Interfaces, Resources”
section on page 62 of this datasheet.
PSoC
Conversely, for the 100-pin and 68-pin devices, the set of I/O
pins associated with any VDDIO may sink up to 100 mA total, as
shown in Figure 2-2.
Figure 2-2. I/O Pins Current Limit
Ipins = 100 mA
VDDIO X
I/O Pins
PSoC
VSSD
For the 48-pin devices, the set of I/O pins associated with
VDDIO0 plus VDDIO2 may sink up to 100 mA total. The set of
I/O pins associated with VDDIO1 plus VDDIO3 may sink up to a
total of 100 mA.
Document Number: 001-56955 Rev. *Y
Page 6 of 128
PSoC® 3: CY8C32 Family Data Sheet
Figure 2-3. 48-pin SSOP Part Pinout
(SIO) P12[2]
(SIO) P12[3]
(GPIO) P0[0]
(GPIO) P0[1]
(GPIO) P0[2]
(EXTREF0, GPIO) P0[3]
VDDIO0
(GPIO) P0[4]
(GPIO) P0[5]
(IDAC0, GPIO) P0[6]
(GPIO) P0[7]
VCCD
VSSD
VDDD
(GPIO) P2[3]
(GPIO) P2[4]
VDDIO2
(GPIO) P2[5]
(GPIO) P2[6]
(GPIO) P2[7]
VSSB
IND
VBOOST
VBAT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
VDDA
VSSA
VCCA
P15[3] (GPIO, KHZ XTAL: XI)
P15[2] (GPIO, KHZ XTAL: XO)
P12[1] (SIO, I2C1: SDA)
P12[0] (SIO, I2C1: SCL)
VDDIO3
P15[1] (GPIO, MHZ XTAL: XI)
P15[0] (GPIO, MHZ XTAL: XO)
VCCD
VSSD
VDDD
[5]
P15[7] (USBIO, D-, SWDCK) [5]
P15[6] (USBIO, D+, SWDIO)
P1[7] (GPIO)
P1[6] (GPIO)
VDDIO1
P1[5] (GPIO, NTRST)
P1[4] (GPIO, TDI)
P1[3] (GPIO, TDO, SWV)
P1[2] (GPIO, CONFIGURABLE XRES)
P1[1] (GPIO, TCK, SWDCK)
P1[0] (GPIO, TMS, SWDIO)
48
47
Lines show 46
VDDIO to I/O
45
supply
association 44
43
42
41
40
39
38
37
SSOP
36
35
34
33
32
31
30
29
28
27
26
25
7
8
9
10
[5]
VDDIO0
P0[4] (GPIO)
38
37
P0[6] (GPIO, IDAC0)
P0[5] (GPIO)
VCCD
P0[7] (GPIO)
41
40
39
43
42
P0[3] (EXTREF0, GPIO)
P0[2] (GPIO)
34
33
32
31
P0[1] (GPIO)
P0[0] (GPIO)
P12[2] (SIO)
VDDA
VSSA
VCCA
P15[3] (GPIO, KHZ XTAL: XI)
P15[2] (GPIO, KHZ XTAL: XO)
P12[1] (SIO, I2C1: SDA)
(SIO, I2C1: SCL) P12[0]
(GPIO, MHZ XTAL: XI) P15[1]
VDDIO3
(GPIO, MHZ XTAL: XO) P15[0]
17
18
19
20
21
22
23
24
26
25
P12[3] (SIO)
[5]
15
16
(GPIO) P1[7]
(USBIO, D+, SWDIO) P15[6]
(USBIO, D-, SWDCK) P15[7]
11
12
36
35
30
29
28
27
( TOP VIEW)
13
14
(GPIO, TDI) P1[4]
(GPIO, NTRST) P1[5]
QFN
VDDIO1
(GPIO, Configurable XRES) P1[2]
(GPIO, TDO, SWV) P1[3]
5
6
(GPIO) P1[6]
VBAT
(GPIO, TMS, SWDIO) P1[0]
(GPIO, TCK, SWDCK) P1[1]
Lines show
VDDIO to I/O
supply
association
VSSD
VCCD
3
4
IND
VBOOST
2
VDDD
VSSB
P2[3] (GPIO)
P2[4] (GPIO)
46
45
44
1
VDDD
VSSD
P2[5] (GPIO)
VDDIO2
(GPIO) P2[6]
(GPIO) P2[7]
47
48
Figure 2-4. 48-pin QFN Part Pinout[6]
Notes
5. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating.
6. The center pad on the QFN package should be connected to digital ground (VSSD) for best mechanical, thermal, and electrical performance. If not connected to
ground, it should be electrically floated and not connected to any other signal. For more information, see AN72845, Design Guidelines for QFN Devices.
Document Number: 001-56955 Rev. *Y
Page 7 of 128
PSoC® 3: CY8C32 Family Data Sheet
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
P0[5] (GPIO)
P0[4] (GPIO)
VDDIO0
53
52
P0[7] (GPIO)
P0[6] (GPIO, IDAC0)
55
54
58
57
56
P15[5] (GPOI)
P15[4] (GPIO)
VDDD
VSSD
VCCD
P2[2] (GPIO)
P2[1] (GPIO)
P2[0] (GPIO)
63
62
61
60
59
64
VDDIO2
P2[4] (GPIO)
P2[3] (GPIO)
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
Lines show VDDIO
to I/O supply
association
QFN
P12[1] (SIO, I2C1: SDA)
P12[0] (SIO, 12C1: SCL)
34
P3[7] (GPIO)
P3[6] (GPIO)
VDDIO3
(GPIO) P3[5]
28
29
30
(MHZ XTAL: XI, GPIO) P15[1]
(GPIO) P3[0]
(GPIO) P3[1]
(EXTREF1, GPIO) P3[2]
(GPIO) P3[3]
(GPIO) P3[4]
24
25
26
27
VDDD
VSSD
VCCD
(MHZ XTAL: XO, GPIO) P15[0]
31
32
33
23
P0[3] (GPIO, EXTREF0)
P0[2] (GPIO)
P0[1] (GPIO)
P0[0] (GPIO)
P12[3] (SIO)
P12[2] (SIO)
VSSD
VDDA
VSSA
VCCA
P15[3] (GPIO, KHZ XTAL: XI)
P15[2] (GPIO, KHZ XTAL: XO)
[8]
20
21
22
[8]
(GPIO) P1[6]
18
19
(TOP VIEW)
(GPIO) P1[7]
(SIO) P12[6]
(SIO) P12[7]
(USBIO, D+, SWDIO) P15[6]
(USBIO, D-, SWDCK) P15[7]
(GPIO) P2[6]
(GPIO) P2[7]
(I2C0: SCL, SIO) P12[4]
(I2C0: SDA, SIO) P12[5]
VSSB
IND
VBOOST
VBAT
VSSD
XRES
(TMS, SWDIO, GPIO) P1[0]
(TCK, SWDCK, GPIO) P1[1]
(Configurable XRES, GPIO) P1[2]
(TDO, SWV, GPIO) P1[3]
(TDI, GPIO) P1[4]
(NTRST, GPIO) P1[5]
VDDIO1
66
65
68
67
P2[5] (GPIO)
Figure 2-5. 68-pin QFN Part Pinout[7]
Notes
7. The center pad on the QFN package should be connected to digital ground (VSSD) for best mechanical, thermal, and electrical performance. If not connected to
ground, it should be electrically floated and not connected to any other signal. For more information, see AN72845, Design Guidelines for QFN Devices.
8. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating.
Document Number: 001-56955 Rev. *Y
Page 8 of 128
PSoC® 3: CY8C32 Family Data Sheet
P0[6] (GPIO, IDAC0)
P0[5] (GPIO)
P0[4] (GPIO)
47
48
49
50
(GPIO) P3[5]
VDDIO3
46
43
44
45
(GPIO) P3[0]
(GPIO) P3[1]
(EXTREF1, GPIO) P3[2]
(GPIO) P3[3]
(GPIO) P3[4]
42
(MHZ XTAL: XO, GPIO) P15[0]
(MHZ XTAL: XI, GPIO) P15[1]
NC
NC
39
40
41
36
37
38
(USBIO, D-, SWDCK) P15[7]
VDDD
VSSD
VCCD
54
53
52
51
VDDIO0
P0[3] (GPIO,EXTREF0)
P0[2] (GPIO)
P0[1] (GPIO)
P0[0] (GPIO)
P4[1] (GPIO)
P4[0] (GPIO)
P12[3] (SIO)
P12[2] (SIO)
VSSD
VDDA
VSSA
VCCA
NC
NC
NC
NC
NC
NC
P15[3] (GPIO, KHZ XTAL: XI)
P15[2] (GPIO, KHZ XTAL: XO)
P12[1] (SIO, I2C1: SDA)
P12[0] (SIO, I2C1: SCL)
P3[7] (GPIO)
P3[6] (GPIO)
[9]
32
33
34
35
(GPIO) P5[5]
(GPIO) P5[6]
(GPIO) P5[7]
(USBIO, D+, SWDIO) P15[6]
[9]
31
77
76
79
78
80
P4[5] (GPIO)
P4[4] (GPIO)
P4[3] (GPIO)
P4[2] (GPIO)
P0[7] (GPIO)
82
81
VCCD
P4[7] (GPIO)
P4[6] (GPIO)
85
84
83
VDDD
VSSD
87
86
90
89
88
P15[4] (GPIO)
P6[3] (GPIO)
P6[2] (GPIO)
P6[1] (GPIO)
P6[0] (GPIO)
P2[1] (GPIO)
P2[0] (GPIO)
P15[5] (GPIO)
95
94
93
92
91
96
P2[4] (GPIO)
P2[3] (GPIO)
P2[2] (GPIO)
98
97
28
29
30
TQFP
26
27
GPIO) P1[1]
GPIO) P1[2]
GPIO) P1[3]
GPIO) P1[4]
GPIO) P1[5]
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
Lines show VDDIO
to I/O supply
association
VDDIO1
(TCK, SWDCK,
(Configurable XRES,
(TDO, SWV,
(TDI,
(NTRST,
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
(GPIO) P1[6]
(GPIO) P1[7]
(SIO) P12[6]
(SIO) P12[7]
(GPIO) P5[4]
(GPIO) P2[5]
(GPIO) P2[6]
(GPIO) P2[7]
(I2C0: SCL, SIO) P12[4]
(I2C0: SDA, SIO) P12[5]
(GPIO) P6[4]
(GPIO) P6[5]
(GPIO) P6[6]
(GPIO) P6[7]
VSSB
IND
VBOOST
VBAT
VSSD
XRES
(GPIO) P5[0]
(GPIO) P5[1]
(GPIO) P5[2]
(GPIO) P5[3]
(TMS, SWDIO, GPIO) P1[0]
100
99
VDDIO2
Figure 2-6. 100-pin TQFP Part Pinout
Table 2-1. VDDIO and Port Pin Associations
VDDIO
Port Pins
VDDIO0
P0[7:0], P4[7:0], P12[3:2]
VDDIO1
P1[7:0], P5[7:0], P12[7:6]
VDDIO2
P2[7:0], P6[7:0], P12[5:4], P15[5:4]
VDDIO3
P3[7:0], P12[1:0], P15[3:0]
VDDD
P15[7:6] (USB D+, D-)
Note
9. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating.
Document Number: 001-56955 Rev. *Y
Page 9 of 128
PSoC® 3: CY8C32 Family Data Sheet
Table 2-2 shows the pinout for the 72-pin CSP package. Since there are four VDDIO pins, the set of I/O pins associated with any VDDIO
may sink up to 100 mA total, same as for the 100-pin and 68-pin devices.
Table 2-2. CSP Pinout
Ball
Name
Ball
Name
Ball
Name
G6
P2[5]
F1
VDDD
A5
VDDA
E5
P2[6]
E1
VSSD
A6
VSSD
F5
P2[7]
E2
VCCD
B6
P12[2]
J7
P12[4]
C1
P15[0]
C6
P12[3]
H6
P12[5]
C2
P15[1]
A7
P0[0]
J6
VSSB
D2
P3[0]
B7
P0[1]
J5
Ind
D3
P3[1]
B5
P0[2]
H5
VBOOST
D4
P3[2]
C5
P0[3]
J4
VBAT
D5
P3[3]
A8
VIO0
H4
VSSD
B4
P3[4]
D6
P0[4]
J3
XRES_N
B3
P3[5]
D7
P0[5]
H3
P1[0]
A1
VIO3
C7
P0[6]
G3
P1[1]
B2
P3[6]
C8
P0[7]
H2
P1[2]
A2
P3[7]
E8
VCCD
J2
P1[3]
C3
P12[0]
F8
VSSD
G4
P1[4]
C4
P12[1]
G8
VDDD
G5
P1[5]
E3
P15[2]
E7
P15[4]
J1
VIO1
E4
F4
P1[6]
P15[3]
F7
P15[5]
B1
[10]
NC
G7
P2[0]
[10]
F3
P1[7]
B8
NC
H7
P2[1]
H1
P12[6]
D1[10]
NC
H8
P2[2]
G1
P12[7]
[10]
NC
F6
P2[3]
G2
P15[6]
A3
VCCA
E6
P2[4]
F2
P15[7]
A4
VSSA
J8
VIO2
D8
Figure 2-7 and Figure 2-8 show an example schematic and an example PCB layout, for the 100-pin TQFP part, for optimal analog
performance on a two layer board.
The two pins labeled VDDD must be connected together.
The two pins labeled VCCD must be connected together, with capacitance added, as shown in Figure 2-7 and Power System on
page 31. The trace between the two VCCD pins should be as short as possible.
The two pins labeled VSSD must be connected together.
For information on circuit board layout issues for mixed signals, refer to the application note AN57821 - Mixed Signal Circuit Board
Layout Considerations for PSoC® 3 and PSoC 5.
Note
10. These pins are Do Not Use (DNU); they must be left floating.
Document Number: 001-56955 Rev. *Y
Page 10 of 128
PSoC® 3: CY8C32 Family Data Sheet
Figure 2-7. Example Schematic for 100-pin TQFP Part with Power Connections
VDDD
C1
1uF
VDDD
VSSD
VSSD
VSSD
VDDD
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VDDA
C8
0.1uF
VSSD
VSSD
VDDA
VSSA
VCCA
C17
1uF
VSSA
VDDA
C9
1uF
C10
0.1uF
VSSA
VDDD
C11
0.1uF
VCCD
VDDD
VSSD
C12
0.1uF
VSSD
VDDD
VDDIO0
OA0-, REF0, P0[3]
OA0+, P0[2]
OA0OUT, P0[1]
OA2OUT, P0[0]
P4[1]
P4[0]
SIO, P12[3]
SIO, P12[2]
VSSD
VDDA
VSSA
VCCA
NC
NC
NC
NC
NC
NC
KHZXIN, P15[3]
KHZXOUT, P15[2]
SIO, P12[1]
SIO, P12[0]
OA3OUT, P3[7]
OA1OUT, P3[6]
VDDIO1
P1[6]
P1[7]
P12[6], SIO
P12[7], SIO
P5[4]
P5[5]
P5[6]
P5[7]
P15[6], USB D+
P15[7], USB DVDDD
VSSD
VCCD
NC
NC
P15[0], MHZXOUT
P15[1], MHZXIN
P3[0], IDAC1
P3[1], IDAC3
P3[2], OA3-, REF1
P3[3], OA3+
P3[4], OA1P3[5], OA1+
VDDIO3
P2[5]
P2[6]
P2[7]
P12[4], SIO
P12[5], SIO
P6[4]
P6[5]
P6[6]
P6[7]
VSSB
IND
VBOOST
VBAT
VSSD
XRES
P5[0]
P5[1]
P5[2]
P5[3]
P1[0], SWIO, TMS
P1[1], SWDIO, TCK
P1[2]
P1[3], SWV, TDO
P1[4], TDI
P1[5], NTRST
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VSSD
VCCD
VDDIO2
P2[4]
P2[3]
P2[2]
P2[1]
P2[0]
P15[5]
P15[4]
P6[3]
P6[2]
P6[1]
P6[0]
VDDD
VSSD
VCCD
P4[7]
P4[6]
P4[5]
P4[4]
P4[3]
P4[2]
IDAC2, P0[7]
IDAC0, P0[6]
OA2-, P0[5]
OA2+, P0[4]
VSSD
VSSD
C2
0.1uF
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
C6
0.1uF
VDDD
VDDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
VDDD
C15
1uF
C16
0.1uF
VSSD
VSSD
Note The two VCCD pins must be connected together with as short a trace as possible. A trace under the device is recommended,
as shown in Figure 2-8 on page 12.
For more information on pad layout, refer to http://www.cypress.com/cad-resources/psoc-3-cad-libraries.
Document Number: 001-56955 Rev. *Y
Page 11 of 128
PSoC® 3: CY8C32 Family Data Sheet
Figure 2-8. Example PCB Layout for 100-pin TQFP Part for Optimal Analog Performance
VSSA
VDDD
VSSD
VDDA
VSSA
Plane
VSSD
Plane
3. Pin Descriptions
nTRST
IDAC0
Optional JTAG test reset programming and debug port
connection to reset the JTAG connection.
Low resistance output pin for high current DAC (IDAC).
SIO
Extref0, Extref1
External reference input to the analog system.
GPIO
General purpose I/O pin provides interfaces to the CPU, digital
peripherals, analog peripherals, interrupts, LCD segment drive,
and CapSense.
I2C0: SCL, I2C1: SCL
Special I/O provides interfaces to the CPU, digital peripherals
and interrupts with a programmable high threshold voltage,
analog comparator, high sink current, and high impedance state
when the device is unpowered.
SWDCK
Serial wire debug clock programming and debug port
connection.
I2C SCL line providing wake from sleep on an address match.
Any I/O pin can be used for I2C SCL if wake from sleep is not
required.
SWDIO
I2C0: SDA, I2C1: SDA
SWV.
2
I C SDA line providing wake from sleep on an address match.
Any I/O pin can be used for I2C SDA if wake from sleep is not
required.
Ind
Inductor connection to boost pump.
kHz XTAL: Xo, kHz XTAL: Xi
32.768-kHz crystal oscillator pin.
MHz XTAL: Xo, MHz XTAL: Xi
4- to 25- MHz crystal oscillator pin.
Document Number: 001-56955 Rev. *Y
Serial wire debug input and output programming and debug port
connection.
Single wire viewer debug output.
TCK
JTAG test clock programming and debug port connection.
TDI
JTAG test data in programming and debug port connection.
TDO
JTAG test data out programming and debug port connection.
TMS
JTAG test mode select programming and debug port connection.
Page 12 of 128
PSoC® 3: CY8C32 Family Data Sheet
USBIO, D+
XRES (and configurable XRES)
Provides D+ connection directly to a USB 2.0 bus. May be used
as a digital I/O pin. Pins are Do Not Use (DNU) on devices
without USB.
External reset pin. Active low with internal pull-up. Pin P1[2] may
be configured to be a XRES pin; see “Nonvolatile Latches
(NVLs)” on page 25.
USBIO, D–
Provides D– connection directly to a USB 2.0 bus. May be used
as a digital I/O pin. Pins are No Connect (NC) on devices without
USB.
VBOOST
Power sense connection to boost pump.
VBAT
Battery supply to boost pump.
VCCA.
Output of the analog core regulator or the input to the
analog core. Requires a 1uF capacitor to VSSA. The regulator
output is not designed to drive external circuits. Note that if you
use the device with an external core regulator (externally
regulated mode), the voltage applied to this pin must not
exceed the allowable range of 1.71 V to 1.89 V. When using
the internal core regulator, (internally regulated mode, the
default), do not tie any power to this pin. For details see Power
System on page 31.
VCCD.
Output of the digital core regulator or the input to the digital
core. The two VCCD pins must be shorted together, with the
trace between them as short as possible, and a 1uF capacitor to
VSSD. The regulator output is not designed to drive external
circuits. Note that if you use the device with an external core
regulator (externally regulated mode), the voltage applied to
this pin must not exceed the allowable range of 1.71 V to
1.89 V. When using the internal core regulator (internally
regulated mode, the default), do not tie any power to this pin. For
details see Power System on page 31.
VDDA
Supply for all analog peripherals and analog core regulator.
VDDA must be the highest voltage present on the device. All
other supply pins must be less than or equal to VDDA.
VDDD
Supply for all digital peripherals and digital core regulator. VDDD
must be less than or equal to VDDA.
VSSA
Ground for all analog peripherals.
VSSB
Ground connection for boost pump.
VSSD
Ground for all digital logic and I/O pins.
VDDIO0, VDDIO1, VDDIO2, VDDIO3
Supply for I/O pins. See pinouts for specific I/O pin to VDDIO
mapping. Each VDDIO must be tied to a valid operating voltage
(1.71 V to 5.5 V), and must be less than or equal to VDDA.
Document Number: 001-56955 Rev. *Y
4. CPU
4.1 8051 CPU
The CY8C32 devices use a single cycle 8051 CPU, which is fully
compatible with the original MCS-51 instruction set. The
CY8C32 family uses a pipelined RISC architecture, which
executes most instructions in 1 to 2 cycles to provide peak
performance of up to 24 MIPS with an average of 2 cycles per
instruction. The single cycle 8051 CPU runs ten times faster than
a standard 8051 processor.
The 8051 CPU subsystem includes these features:
Single cycle 8051 CPU
Up to 64 KB of flash memory, up to 2 KB of EEPROM, and up
to 8 KB of SRAM
512-byte instruction cache between CPU and flash
Programmable nested vector interrupt controller
Direct memory access (DMA) controller
Peripheral HUB (PHUB)
External memory interface (EMIF)
4.2 Addressing Modes
The following addressing modes are supported by the 8051:
Direct Addressing: The operand is specified by a direct 8-bit
address field. Only the internal RAM and the SFRs can be
accessed using this mode.
Indirect Addressing: The instruction specifies the register which
contains the address of the operand. The registers R0 or R1
are used to specify the 8-bit address, while the data pointer
(DPTR) register is used to specify the 16-bit address.
Register Addressing: Certain instructions access one of the
registers (R0 to R7) in the specified register bank. These
instructions are more efficient because there is no need for an
address field.
Register Specific Instructions: Some instructions are specific
to certain registers. For example, some instructions always act
on the accumulator. In this case, there is no need to specify the
operand.
Immediate Constants: Some instructions carry the value of the
constants directly instead of an address.
Indexed Addressing: This type of addressing can be used only
for a read of the program memory. This mode uses the data
pointer as the base and the accumulator value as an offset to
read a program memory.
Bit Addressing: In this mode, the operand is one of 256 bits.
Page 13 of 128
PSoC® 3: CY8C32 Family Data Sheet
4.3 Instruction Set
4.3.1 Instruction Set Summary
The 8051 instruction set is highly optimized for 8-bit handling and
Boolean operations. The types of instructions supported include:
4.3.1.1 Arithmetic Instructions
Arithmetic instructions
Logical instructions
Data transfer instructions
Arithmetic instructions support the direct, indirect, register,
immediate constant, and register-specific instructions.
Arithmetic modes are used for addition, subtraction,
multiplication, division, increment, and decrement operations.
Table 4-1 lists the different arithmetic instructions.
Boolean instructions
Program branching instructions
Table 4-1. Arithmetic Instructions
Mnemonic
Description
Bytes
Cycles
ADD
A,Rn
Add register to accumulator
1
1
ADD
A,Direct
Add direct byte to accumulator
2
2
ADD
A,@Ri
Add indirect RAM to accumulator
1
2
ADD
A,#data
Add immediate data to accumulator
2
2
ADDC A,Rn
Add register to accumulator with carry
1
1
ADDC A,Direct
Add direct byte to accumulator with carry
2
2
ADDC A,@Ri
Add indirect RAM to accumulator with carry
1
2
ADDC A,#data
Add immediate data to accumulator with carry
2
2
SUBB A,Rn
Subtract register from accumulator with borrow
1
1
SUBB A,Direct
Subtract direct byte from accumulator with borrow
2
2
SUBB A,@Ri
Subtract indirect RAM from accumulator with borrow
1
2
SUBB A,#data
Subtract immediate data from accumulator with borrow
2
2
INC
A
Increment accumulator
1
1
INC
Rn
Increment register
1
2
INC
Direct
Increment direct byte
2
3
INC
@Ri
Increment indirect RAM
1
3
DEC
A
Decrement accumulator
1
1
DEC
Rn
Decrement register
1
2
DEC
Direct
Decrement direct byte
2
3
DEC
@Ri
Decrement indirect RAM
1
3
INC
DPTR
Increment data pointer
1
1
MUL
Multiply accumulator and B
1
2
DIV
Divide accumulator by B
1
6
DAA
Decimal adjust accumulator
1
3
Document Number: 001-56955 Rev. *Y
Page 14 of 128
PSoC® 3: CY8C32 Family Data Sheet
4.3.1.2 Logical Instructions
The logical instructions perform Boolean operations such as AND, OR, XOR on bytes, rotate of accumulator contents, and swap of
nibbles in an accumulator. The Boolean operations on the bytes are performed on the bit-by-bit basis. Table 4-2Table 4-2 on page 15
shows the list of logical instructions and their description.
Table 4-2. Logical Instructions
Mnemonic
Description
Bytes
Cycles
ANL
A,Rn
AND register to accumulator
1
1
ANL
A,Direct
AND direct byte to accumulator
2
2
ANL
A,@Ri
AND indirect RAM to accumulator
1
2
ANL
A,#data
AND immediate data to accumulator
2
2
ANL
Direct, A
AND accumulator to direct byte
2
3
ANL
Direct, #data
AND immediate data to direct byte
3
3
ORL
A,Rn
OR register to accumulator
1
1
ORL
A,Direct
OR direct byte to accumulator
2
2
ORL
A,@Ri
OR indirect RAM to accumulator
1
2
ORL
A,#data
OR immediate data to accumulator
2
2
ORL
Direct, A
OR accumulator to direct byte
2
3
ORL
Direct, #data
OR immediate data to direct byte
3
3
XRL
A,Rn
XOR register to accumulator
1
1
XRL
A,Direct
XOR direct byte to accumulator
2
2
XRL
A,@Ri
XOR indirect RAM to accumulator
1
2
XRL
A,#data
XOR immediate data to accumulator
2
2
XRL
Direct, A
XOR accumulator to direct byte
2
3
XRL
Direct, #data
XOR immediate data to direct byte
3
3
CLR
A
Clear accumulator
1
1
CPL
A
Complement accumulator
1
1
RL
A
Rotate accumulator left
1
1
RLC
A
Rotate accumulator left through carry
1
1
RR
A
Rotate accumulator right
1
1
RRC A
Rotate accumulator right though carry
1
1
SWAP A
Swap nibbles within accumulator
1
1
Document Number: 001-56955 Rev. *Y
Page 15 of 128
PSoC® 3: CY8C32 Family Data Sheet
4.3.1.3 Data Transfer Instructions
The data transfer instructions are of three types: the core RAM,
xdata RAM, and the lookup tables. The core RAM transfer
includes transfer between any two core RAM locations or SFRs.
These instructions can use direct, indirect, register, and
immediate addressing. The xdata RAM transfer includes only the
transfer between the accumulator and the xdata RAM location.
It can use only indirect addressing. The lookup tables involve
nothing but the read of program memory using the Indexed
addressing mode. Table 4-3 lists the various data transfer
instructions available.
4.3.1.4 Boolean Instructions
The 8051 core has a separate bit-addressable memory location.
It has 128 bits of bit addressable RAM and a set of SFRs that are
bit addressable. The instruction set includes the whole menu of
bit operations such as move, set, clear, toggle, OR, and AND
instructions and the conditional jump instructions. Table 4-4 on
page 17Table 4-4 lists the available Boolean instructions.
Table 4-3. Data Transfer Instructions
Mnemonic
Description
Bytes
Cycles
MOV
A,Rn
Move register to accumulator
1
1
MOV
A,Direct
Move direct byte to accumulator
2
2
MOV
A,@Ri
Move indirect RAM to accumulator
1
2
MOV
A,#data
Move immediate data to accumulator
2
2
MOV
Rn,A
Move accumulator to register
1
1
MOV
Rn,Direct
Move direct byte to register
2
3
MOV
Rn, #data
Move immediate data to register
2
2
MOV
Direct, A
Move accumulator to direct byte
2
2
MOV
Direct, Rn
Move register to direct byte
2
2
MOV
Direct, Direct
Move direct byte to direct byte
3
3
MOV
Direct, @Ri
Move indirect RAM to direct byte
2
3
MOV
Direct, #data
Move immediate data to direct byte
3
3
MOV
@Ri, A
Move accumulator to indirect RAM
1
2
MOV
@Ri, Direct
Move direct byte to indirect RAM
2
3
MOV
@Ri, #data
Move immediate data to indirect RAM
2
2
MOV
DPTR, #data16
Load data pointer with 16-bit constant
3
3
MOVC A, @A+DPTR
Move code byte relative to DPTR to accumulator
1
5
MOVC A, @A + PC
Move code byte relative to PC to accumulator
1
4
MOVX A,@Ri
Move external RAM (8-bit) to accumulator
1
4
MOVX A, @DPTR
Move external RAM (16-bit) to accumulator
1
3
MOVX @Ri, A
Move accumulator to external RAM (8-bit)
1
5
MOVX @DPTR, A
Move accumulator to external RAM (16-bit)
1
4
PUSH Direct
Push direct byte onto stack
2
3
POP
Direct
Pop direct byte from stack
2
2
XCH
A, Rn
Exchange register with accumulator
1
2
XCH
A, Direct
Exchange direct byte with accumulator
2
3
XCH
A, @Ri
Exchange indirect RAM with accumulator
1
3
Exchange low order indirect digit RAM with accumulator
1
3
XCHD A, @Ri
Document Number: 001-56955 Rev. *Y
Page 16 of 128
PSoC® 3: CY8C32 Family Data Sheet
Table 4-4. Boolean Instructions
Mnemonic
Description
Bytes
Cycles
CLR
C
Clear carry
1
1
CLR
bit
Clear direct bit
2
3
SETB C
Set carry
1
1
SETB bit
Set direct bit
2
3
CPL
C
Complement carry
1
1
CPL
bit
Complement direct bit
2
3
ANL
C, bit
AND direct bit to carry
2
2
ANL
C, /bit
AND complement of direct bit to carry
2
2
ORL C, bit
OR direct bit to carry
2
2
ORL C, /bit
OR complement of direct bit to carry
2
2
MOV C, bit
Move direct bit to carry
2
2
MOV bit, C
Move carry to direct bit
2
3
JC
Jump if carry is set
2
3
rel
JNC rel
Jump if no carry is set
2
3
JB
Jump if direct bit is set
3
5
JNB bit, rel
Jump if direct bit is not set
3
5
JBC bit, rel
Jump if direct bit is set and clear bit
3
5
bit, rel
Document Number: 001-56955 Rev. *Y
Page 17 of 128
PSoC® 3: CY8C32 Family Data Sheet
4.3.1.5 Program Branching Instructions
The 8051 supports a set of conditional and unconditional jump instructions that help to modify the program execution flow. Table 4-5
shows the list of jump instructions.
Table 4-5. Jump Instructions
Mnemonic
ACALL addr11
LCALL addr16
RET
RETI
AJMP addr11
LJMP addr16
SJMP rel
JMP @A + DPTR
JZ rel
JNZ rel
CJNE A,Direct, rel
CJNE A, #data, rel
CJNE Rn, #data, rel
CJNE @Ri, #data, rel
DJNZ Rn,rel
DJNZ Direct, rel
NOP
Description
Absolute subroutine call
Long subroutine call
Return from subroutine
Return from interrupt
Absolute jump
Long jump
Short jump (relative address)
Jump indirect relative to DPTR
Jump if accumulator is zero
Jump if accumulator is nonzero
Compare direct byte to accumulator and jump if not equal
Compare immediate data to accumulator and jump if not equal
Compare immediate data to register and jump if not equal
Compare immediate data to indirect RAM and jump if not equal
Decrement register and jump if not zero
Decrement direct byte and jump if not zero
No operation
Bytes
2
3
1
1
2
3
2
1
2
2
3
3
3
3
2
3
1
Cycles
4
4
4
4
3
4
3
5
4
4
5
4
4
5
4
5
1
4.4 DMA and PHUB
Simultaneous CPU and DMA access to peripherals located on
The PHUB and the DMA controller are responsible for data
transfer between the CPU and peripherals, and also data
transfers between peripherals. The PHUB and DMA also control
device configuration during boot. The PHUB consists of:
Simultaneous DMA source and destination burst transactions
A central hub that includes the DMA controller, arbiter, and
router
Multiple spokes that radiate outward from the hub to most
peripherals
There are two PHUB masters: the CPU and the DMA controller.
Both masters may initiate transactions on the bus. The DMA
channels can handle peripheral communication without CPU
intervention. The arbiter in the central hub determines which
DMA channel is the highest priority if there are multiple requests.
4.4.1 PHUB Features
CPU and DMA controller are both bus masters to the PHUB
Eight Multi-layer AHB Bus parallel access paths (spokes) for
peripheral access
Document Number: 001-56955 Rev. *Y
different spokes
on different spokes
Supports 8, 16, 24, and 32-bit addressing and data
Table 4-6. PHUB Spokes and Peripherals
PHUB Spokes
Peripherals
0
SRAM
1
IOs, PICU, EMIF
2
PHUB local configuration, Power manager,
Clocks, IC, SWV, EEPROM, Flash
programming interface
3
Analog interface and trim, Decimator
4
USB, USB, I2C, Timers, Counters, and PWMs
5
Reserved
6
UDBs group 1
7
UDBs group 2
Page 18 of 128
PSoC® 3: CY8C32 Family Data Sheet
4.4.2 DMA Features
Table 4-7. Priority Levels
24 DMA channels
Priority Level
% Bus Bandwidth
0
100.0
1
100.0
TDs can be dynamically updated
2
50.0
Eight levels of priority per channel
3
25.0
Any digitally routable signal, the CPU, or another DMA channel,
4
12.5
Each channel has one or more transaction descriptors (TDs)
to configure channel behavior. Up to 128 total TDs can be
defined
can trigger a transaction
5
6.2
Each channel can generate up to two interrupts per transfer
6
3.1
Transactions can be stalled or canceled
7
1.5
Supports transaction size of infinite or 1 to 64k bytes
TDs may be nested and/or chained for complex transactions
4.4.3 Priority Levels
The CPU always has higher priority than the DMA controller
when their accesses require the same bus resources. Due to the
system architecture, the CPU can never starve the DMA. DMA
channels of higher priority (lower priority number) may interrupt
current DMA transfers. In the case of an interrupt, the current
transfer is allowed to complete its current transaction. To ensure
latency limits when multiple DMA accesses are requested
simultaneously, a fairness algorithm guarantees an interleaved
minimum percentage of bus bandwidth for priority levels 2
through 7. Priority levels 0 and 1 do not take part in the fairness
algorithm and may use 100 percent of the bus bandwidth. If a tie
occurs on two DMA requests of the same priority level, a simple
round robin method is used to evenly share the allocated
bandwidth. The round robin allocation can be disabled for each
DMA channel, allowing it to always be at the head of the line.
Priority levels 2 to 7 are guaranteed the minimum bus bandwidth
shown in Table 4-7 after the CPU and DMA priority levels 0 and
1 have satisfied their requirements.
When the fairness algorithm is disabled, DMA access is granted
based solely on the priority level; no bus bandwidth guarantees
are made.
4.4.4 Transaction Modes Supported
The flexible configuration of each DMA channel and the ability to
chain multiple channels allow the creation of both simple and
complex use cases. General use cases include, but are not
limited to:
4.4.4.1 Simple DMA
In a simple DMA case, a single TD transfers data between a
source and sink (peripherals or memory location). The basic
timing diagrams of DMA read and write cycles are shown in
Figure 4-1. For more description on other transfer modes, refer
to the Technical Reference Manual.
Figure 4-1. DMA Timing Diagram
ADDRESS Phase
DATA Phase
ADDRESS Phase
CLK
ADDR 16/32
DATA Phase
CLK
A
ADDR 16/32
B
A
B
WRITE
WRITE
DATA (A)
DATA
DATA (A)
DATA
READY
READY
Basic DMA Read Transfer without wait states
4.4.4.2 Auto Repeat DMA
Auto repeat DMA is typically used when a static pattern is
repetitively read from system memory and written to a peripheral.
This is done with a single TD that chains to itself.
4.4.4.3 Ping Pong DMA
A ping pong DMA case uses double buffering to allow one buffer
to be filled by one client while another client is consuming the
Document Number: 001-56955 Rev. *Y
Basic DMA Write Transfer without wait states
data previously received in the other buffer. In its simplest form,
this is done by chaining two TDs together so that each TD calls
the opposite TD when complete.
4.4.4.4 Circular DMA
Circular DMA is similar to ping pong DMA except it contains more
than two buffers. In this case there are multiple TDs; after the last
TD is complete it chains back to the first TD.
Page 19 of 128
PSoC® 3: CY8C32 Family Data Sheet
4.4.4.5 Scatter Gather DMA
4.5 Interrupt Controller
In the case of scatter gather DMA, there are multiple
noncontiguous sources or destinations that are required to
effectively carry out an overall DMA transaction. For example, a
packet may need to be transmitted off of the device and the
packet elements, including the header, payload, and trailer, exist
in various noncontiguous locations in memory. Scatter gather
DMA allows the segments to be concatenated together by using
multiple TDs in a chain. The chain gathers the data from the
multiple locations. A similar concept applies for the reception of
data onto the device. Certain parts of the received data may need
to be scattered to various locations in memory for software
processing convenience. Each TD in the chain specifies the
location for each discrete element in the chain.
The interrupt controller provides a mechanism for hardware
resources to change program execution to a new address,
independent of the current task being executed by the main
code. The interrupt controller provides enhanced features not
found on original 8051 interrupt controllers:
4.4.4.6 Packet Queuing DMA
Packet queuing DMA is similar to scatter gather DMA but
specifically refers to packet protocols. With these protocols,
there may be separate configuration, data, and status phases
associated with sending or receiving a packet.
For instance, to transmit a packet, a memory mapped
configuration register can be written inside a peripheral,
specifying the overall length of the ensuing data phase. The CPU
can set up this configuration information anywhere in system
memory and copy it with a simple TD to the peripheral. After the
configuration phase, a data phase TD (or a series of data phase
TDs) can begin (potentially using scatter gather). When the data
phase TD(s) finish, a status phase TD can be invoked that reads
some memory mapped status information from the peripheral
and copies it to a location in system memory specified by the
CPU for later inspection. Multiple sets of configuration, data, and
status phase “subchains” can be strung together to create larger
chains that transmit multiple packets in this way. A similar
concept exists in the opposite direction to receive the packets.
4.4.4.7 Nested DMA
One TD may modify another TD, as the TD configuration space
is memory mapped similar to any other peripheral. For example,
a first TD loads a second TD’s configuration and then calls the
second TD. The second TD moves data as required by the
application. When complete, the second TD calls the first TD,
which again updates the second TD’s configuration. This
process repeats as often as necessary.
Thirty two interrupt vectors
Jumps directly to ISR anywhere in code space with dynamic
vector addresses
Multiple sources for each vector
Flexible interrupt to vector matching
Each interrupt vector is independently enabled or disabled
Each interrupt can be dynamically assigned one of eight
priorities
Eight level nestable interrupts
Multiple I/O interrupt vectors
Software can send interrupts
Software can clear pending interrupts
When an interrupt is pending, the current instruction is
completed and the program counter is pushed onto the stack.
Code execution then jumps to the program address provided by
the vector. After the ISR is completed, a RETI instruction is
executed and returns execution to the instruction following the
previously interrupted instruction. To do this the RETI instruction
pops the program counter from the stack.
If the same priority level is assigned to two or more interrupts,
the interrupt with the lower vector number is executed first. Each
interrupt vector may choose from three interrupt sources: Fixed
Function, DMA, and UDB. The fixed function interrupts are direct
connections to the most common interrupt sources and provide
the lowest resource cost connection. The DMA interrupt sources
provide direct connections to the two DMA interrupt sources
provided per DMA channel. The third interrupt source for vectors
is from the UDB digital routing array. This allows any digital signal
available to the UDB array to be used as an interrupt source.
Fixed function interrupts and all interrupt sources may be routed
to any interrupt vector using the UDB interrupt source
connections.
Figure 4-2 on page 21 represents typical flow of events when an
interrupt triggered. Figure 4-3 on page 22 shows the interrupt
structure and priority polling.
Document Number: 001-56955 Rev. *Y
Page 20 of 128
PSoC® 3: CY8C32 Family Data Sheet
Figure 4-2. Interrupt Processing Timing Diagram
1
2
3
4
5
6
7
8
9
10
11
S
CLK
Arrival of new Interrupt
INT_INPUT
S
Pend bit is set on next clock active edge
POST and PEND bits cleared after IRQ is sleared
PEND
S
Interrupt is posted to ascertain the priority
POST
S
Interrupt request sent to core for processing
IRQ
ACTIVE_INT_NUM
(#10)
NA
NA
INT_VECT_ADDR
0x0010
IRQ cleared after receiving IRA
S
S
The active interrupt
number is posted to core
The active interrupt ISR
address is posted to core
0x0000
S
S
NA
S
IRA
S
IRC
Interrupt generation and posting to CPU
CPU Response
Int. State
Clear
S
Completing current instruction and branching to vector address
Complete ISR and return
TIME
Notes
1: Interrupt triggered asynchronous to the clock
2: The PEND bit is set on next active clock edge to indicate the interrupt arrival
3: POST bit is set following the PEND bit
4: Interrupt request and the interrupt number sent to CPU core after evaluation priority (Takes 3 clocks)
5: ISR address is posted to CPU core for branching
6: CPU acknowledges the interrupt request
7: ISR address is read by CPU for branching
8, 9: PEND and POST bits are cleared respectively after receiving the IRA from core
10: IRA bit is cleared after completing the current instruction and starting the instruction execution from ISR location (Takes 7 cycles)
11: IRC is set to indicate the completion of ISR, Active int. status is restored with previous status
The total interrupt latency (ISR execution)
= POST + PEND + IRQ + IRA + Completing current instruction and branching
= 1+1+1+2+7 cycles
= 12 cycles
Document Number: 001-56955 Rev. *Y
Page 21 of 128
PSoC® 3: CY8C32 Family Data Sheet
Figure 4-3. Interrupt Structure
Interrupt Polling logic
Interrupts form Fixed
function blocks, DMA and
UDBs
Highest Priority
Interrupt Enable/
Disable, PEND and
POST logic
Interrupts 0 to 31
from UDBs
0
Interrupts 0 to 31
from Fixed
Function Blocks
1
IRQ
8 Level
Priority
decoder
for all
interrupts
Polling sequence
Interrupt
routing logic
to select 32
sources
Interrupt 2 to 30
Interrupts 0 to
31 from DMA
Individual
Enable Disable
bits
0 to 31
ACTIVE_INT_NUM
[15:0]
INT_VECT_ADDR
IRA
IRC
31
Global Enable
disable bit
Document Number: 001-56955 Rev. *Y
Lowest Priority
Page 22 of 128
PSoC® 3: CY8C32 Family Data Sheet
Table 4-8. Interrupt Vector Table
#
Fixed Function
DMA
UDB
0
LVD
phub_termout0[0]
udb_intr[0]
1
Cache/ECC
phub_termout0[1]
udb_intr[1]
2
Reserved
phub_termout0[2]
udb_intr[2]
3
Sleep (Pwr Mgr)
phub_termout0[3]
udb_intr[3]
4
PICU[0]
phub_termout0[4]
udb_intr[4]
5
PICU[1]
phub_termout0[5]
udb_intr[5]
6
PICU[2]
phub_termout0[6]
udb_intr[6]
7
PICU[3]
phub_termout0[7]
udb_intr[7]
8
PICU[4]
phub_termout0[8]
udb_intr[8]
9
PICU[5]
phub_termout0[9]
udb_intr[9]
10
PICU[6]
phub_termout0[10] udb_intr[10]
11
PICU[12]
phub_termout0[11] udb_intr[11]
12
PICU[15]
phub_termout0[12] udb_intr[12]
13
Comparators
Combined
phub_termout0[13] udb_intr[13]
14
Reserved
phub_termout0[14] udb_intr[14]
15
I2C
phub_termout0[15] udb_intr[15]
16
Reserved
phub_termout1[0]
udb_intr[16]
17
Timer/Counter0
phub_termout1[1]
udb_intr[17]
18
Timer/Counter1
phub_termout1[2]
udb_intr[18]
19
Timer/Counter2
phub_termout1[3]
udb_intr[19]
20
Timer/Counter3
phub_termout1[4]
udb_intr[20]
21
USB SOF Int
phub_termout1[5]
udb_intr[21]
22
USB Arb Int
phub_termout1[6]
udb_intr[22]
23
USB Bus Int
phub_termout1[7]
udb_intr[23]
24
USB Endpoint[0]
phub_termout1[8]
udb_intr[24]
25
USB Endpoint Data phub_termout1[9]
udb_intr[25]
26
Reserved
27
LCD
phub_termout1[11] udb_intr[27]
28
Reserved
phub_termout1[12] udb_intr[28]
29
Decimator Int
phub_termout1[13] udb_intr[29]
30
PHUB Error Int
phub_termout1[14] udb_intr[30]
31
EEPROM Fault Int
phub_termout1[15] udb_intr[31]
phub_termout1[10] udb_intr[26]
Document Number: 001-56955 Rev. *Y
Page 23 of 128
PSoC® 3: CY8C32 Family Data Sheet
5. Memory
5.1 Static RAM
CY8C32 Static RAM (SRAM) is used for temporary data storage.
Up to 8 KB of SRAM is provided and can be accessed by the
8051 or the DMA controller. See Memory Map on page 26.
Simultaneous access of SRAM by the 8051 and the DMA
controller is possible if different 4-KB blocks are accessed.
protecting your application from external access (see the
“Device Security” section on page 65). For more information
about how to take full advantage of the security features in
PSoC, see the PSoC 3 TRM.
Table 5-1. Flash Protection
Protection
Setting
Up to an additional 8 KB of flash space is available for Error
Correcting Codes (ECC). If ECC is not used this space can store
device configuration data and bulk user data. User code may not
be run out of the ECC flash memory section. ECC can correct
one bit error and detect two bit errors per 8 bytes of firmware
memory; an interrupt can be generated when an error is
detected.
The CPU reads instructions located in flash through a cache
controller. This improves instruction execution rate and reduces
system power consumption by requiring less frequent flash
access. The cache has 8 lines at 64 bytes per line for a total of
512 bytes. It is fully associative, automatically controls flash
power, and can be enabled or disabled. If ECC is enabled, the
cache controller also performs error checking and correction,
and interrupt generation.
Flash programming is performed through a special interface and
preempts code execution out of flash. The flash programming
interface performs flash erasing, programming and setting code
protection levels. Flash in-system serial programming (ISSP),
typically used for production programming, is possible through
both the SWD and JTAG interfaces. In-system programming,
typically used for bootloaders, is also possible using serial
interfaces such as I2C, USB, UART, and SPI, or any
communications protocol.
5.3 Flash Security
All PSoC devices include a flexible flash-protection model that
prevents access and visibility to on-chip flash memory. This
prevents duplication or reverse engineering of proprietary code.
Flash memory is organized in blocks, where each block contains
256 bytes of program or data and 32 bytes of ECC or
configuration data. A total of up to 256 blocks is provided on
64-KB flash devices.
The device offers the ability to assign one of four protection
levels to each row of flash. Table 5-1 lists the protection modes
available. Flash protection levels can only be changed by
performing a complete flash erase. The Full Protection and Field
Upgrade settings disable external access (through a debugging
tool such as PSoC Creator, for example). If your application
requires code update through a boot loader, then use the Field
Upgrade setting. Use the Unprotected setting only when no
security is needed in your application. The PSoC device also
offers an advanced security feature called Device Security which
permanently disables all test, programming, and debug ports,
Document Number: 001-56955 Rev. *Y
Not Allowed
Unprotected
External read and write –
+ internal read and write
Factory
Upgrade
External write + internal
read and write
5.2 Flash Program Memory
Flash memory in PSoC devices provides nonvolatile storage for
user firmware, user configuration data, bulk data storage, and
optional ECC data. The main flash memory area contains up to
64 KB of user program space.
Allowed
External read
Field Upgrade Internal read and write
External read and
write
Full Protection Internal read
External read and
write + internal write
Disclaimer
Note the following details of the flash code protection features on
Cypress devices.
Cypress products meet the specifications contained in their
particular Cypress datasheets. Cypress believes that its family of
products is one of the most secure families of its kind on the
market today, regardless of how they are used. There may be
methods, unknown to Cypress, that can breach the code
protection features. Any of these methods, to our knowledge,
would be dishonest and possibly illegal. Neither Cypress nor any
other semiconductor manufacturer can guarantee the security of
their code. Code protection does not mean that we are
guaranteeing the product as “unbreakable.”
Cypress is willing to work with the customer who is concerned
about the integrity of their code. Code protection is constantly
evolving. We at Cypress are committed to continuously
improving the code protection features of our products.
5.4 EEPROM
PSoC EEPROM memory is a byte-addressable nonvolatile
memory. The CY8C32 has up to 2 KB of EEPROM memory to
store user data. Reads from EEPROM are random access at the
byte level. Reads are done directly; writes are done by sending
write commands to an EEPROM programming interface. CPU
code execution can continue from flash during EEPROM writes.
EEPROM is erasable and writeable at the row level. The
EEPROM is divided into 128 rows of 16 bytes each. The factory
default values of all EEPROM bytes are 0.
Because the EEPROM is mapped to the 8051 xdata space, the
CPU cannot execute out of EEPROM. There is no ECC
hardware associated with EEPROM. If ECC is required it must
be handled in firmware.
It can take as much as 20 milliseconds to write to EEPROM or
flash. During this time the device should not be reset, or
unexpected changes may be made to portions of EEPROM or
flash. Reset sources (see Section 6.3.1) include XRES pin,
software reset, and watchdog; care should be taken to make
sure that these are not inadvertently activated. In addition, the
low voltage detect circuits should be configured to generate an
interrupt instead of a reset.
Page 24 of 128
PSoC® 3: CY8C32 Family Data Sheet
5.5 Nonvolatile Latches (NVLs)
PSoC has a 4-byte array of nonvolatile latches (NVLs) that are used to configure the device at reset. The NVL register map is shown
in Table 5-2.
Table 5-2. Device Configuration NVL Register Map
Register Address
7
6
5
4
3
2
1
0
0x00
PRT3RDM[1:0]
PRT2RDM[1:0]
PRT1RDM[1:0]
PRT0RDM[1:0]
0x01
PRT12RDM[1:0]
PRT6RDM[1:0]
PRT5RDM[1:0]
PRT4RDM[1:0]
0x02
XRESMEN
0x03
DBGEN
DIG_PHS_DLY[3:0]
PRT15RDM[1:0]
ECCEN
DPS[1:0]
The details for individual fields and their factory default settings are shown in Table 5-3:.
Table 5-3. Fields and Factory Default Settings
Field
Description
Settings
PRTxRDM[1:0]
Controls reset drive mode of the corresponding IO port. 00b (default) - high impedance analog
See “Reset Configuration” on page 44. All pins of the 01b - high impedance digital
port are set to the same mode.
10b - resistive pull up
11b - resistive pull down
XRESMEN
Controls whether pin P1[2] is used as a GPIO or as an 0 (default for 68-pin 72-pin, and 100-pin parts) - GPIO
1 (default for 48-pin parts) - external reset
external reset. See “Pin Descriptions” on page 12,
XRES description.
DBGEN
Debug Enable allows access to the debug system, for 0 - access disabled
third-party programmers.
1 (default) - access enabled
DPS[1:0]
Controls the usage of various P1 pins as a debug port. 00b - 5-wire JTAG
See “Programming, Debug Interfaces, Resources” on 01b (default) - 4-wire JTAG
page 62.
10b - SWD
11b - debug ports disabled
ECCEN
Controls whether ECC flash is used for ECC or for
general configuration and data storage. See “Flash
Program Memory” on page 24.
0 - ECC disabled
1 (default) - ECC enabled
DIG_PHS_DLY[3:0]
Selects the digital clock phase delay.
See the TRM for details.
Although PSoC Creator provides support for modifying the device configuration NVLs, the number of NVL erase / write cycles is limited
– see “Nonvolatile Latches (NVL))” on page 100.
Document Number: 001-56955 Rev. *Y
Page 25 of 128
PSoC® 3: CY8C32 Family Data Sheet
5.6 External Memory Interface
CY8C32 provides an external memory interface (EMIF) for
connecting to external memory devices. The connection allows
read and write accesses to external memories. The EMIF
operates in conjunction with UDBs, I/O ports, and other
hardware to generate external memory address and control
signals. At 33 MHz, each memory access cycle takes four bus
clock cycles.
Figure 5-1 is the EMIF block diagram. The EMIF supports
synchronous and asynchronous memories. The CY8C32
supports only one type of external memory device at a time.
External memory can be accessed via the 8051 xdata space; up
to 24 address bits can be used. See “xdata Space” section on
page 28. The memory can be 8 or 16 bits wide.
Figure 5-1. EMIF Block Diagram
Address Signals
External_ MEM_ ADDR[23:0]
I/O
PORTs
Data Signals
External_ MEM_ DATA[15:0]
I/O
PORTs
Control Signals
I/O
PORTs
Data,
Address,
and Control
Signals
I/O IF
PHUB
Data,
Address,
and Control
Signals
Control
DSI Dynamic Output
Control
UDB
DSI to Port
Data,
Address,
and Control
Signals
EM Control
Signals
Other
Control
Signals
EMIF
5.7 Memory Map
5.7.2 Internal Data Space
The CY8C32 8051 memory map is very similar to the MCS-51
memory map.
The CY8C32 8051 internal data space is 384 bytes, compressed
within a 256-byte space. This space consists of 256 bytes of
RAM (in addition to the SRAM mentioned in Static RAM on page
24) and a 128-byte space for Special Function Registers (SFRs).
See Figure 5-2. The lowest 32 bytes are used for 4 banks of
registers R0-R7. The next 16 bytes are bit-addressable.
5.7.1 Code Space
The CY8C32 8051 code space is 64 KB. Only main flash exists
in this space. See the “Flash Program Memory” section on
page 24.
Document Number: 001-56955 Rev. *Y
Page 26 of 128
PSoC® 3: CY8C32 Family Data Sheet
In addition to the register or bit address modes used with the
lower 48 bytes, the lower 128 bytes can be accessed with direct
or indirect addressing. With direct addressing mode, the upper
128 bytes map to the SFRs. With indirect addressing mode, the
upper 128 bytes map to RAM. Stack operations use indirect
addressing; the 8051 stack space is 256 bytes. See the
“Addressing Modes” section on page 13
Figure 5-2. 8051 Internal Data Space
0x00
4 Banks, R0-R7 Each
0x1F
0x20
0x2F
0x30
Bit-Addressable Area
Lower Core RAM Shared with Stack Space
(direct and indirect addressing)
0x7F
0x80
Upper Core RAM Shared
with Stack Space
(indirect addressing)
0xFF
SFR
Special Function Registers
(direct addressing)
5.7.3 SFRs
The special function register (SFR) space provides access to frequently accessed registers. The memory map for the SFR memory
space is shown in Table 5-4.
Table 5-4. SFR Map
Address
0×F8
0×F0
0×E8
0×E0
0×D8
0×D0
0×C8
0×C0
0×B8
0×B0
0×A8
0×A0
0×98
0×90
0×88
0×80
0/8
SFRPRT15DR
B
SFRPRT12DR
ACC
SFRPRT6DR
PSW
SFRPRT5DR
SFRPRT4DR
–
SFRPRT3DR
IE
P2AX
SFRPRT2DR
SFRPRT1DR
–
SFRPRT0DR
1/9
SFRPRT15PS
–
SFRPRT12PS
–
SFRPRT6PS
–
SFRPRT5PS
SFRPRT4PS
–
SFRPRT3PS
–
–
SFRPRT2PS
SFRPRT1PS
SFRPRT0PS
SP
2/A
SFRPRT15SEL
SFRPRT12SEL
MXAX
–
SFRPRT6SEL
–
SFRPRT5SEL
SFRPRT4SEL
–
SFRPRT3SEL
–
SFRPRT1SEL
SFRPRT2SEL
–
SFRPRT0SEL
DPL0
The CY8C32 family provides the standard set of registers found
on industry standard 8051 devices. In addition, the CY8C32
devices add SFRs to provide direct access to the I/O ports on the
device. The following sections describe the SFRs added to the
CY8C32 family.
5.7.3.1 XData Space Access SFRs
The 8051 core features dual DPTR registers for faster data
transfer operations. The data pointer select SFR, DPS, selects
which data pointer register, DPTR0 or DPTR1, is used for the
following instructions:
MOVX @DPTR, A
MOVX A, @DPTR
MOVC A, @A+DPTR
JMP @A+DPTR
INC DPTR
MOV DPTR, #data16
Document Number: 001-56955 Rev. *Y
3/B
–
–
–
–
–
–
–
–
–
–
–
–
–
DPX0
–
DPH0
4/C
–
–
–
–
–
–
–
–
–
–
–
–
–
–
DPL1
5/D
–
–
–
–
–
–
–
–
–
–
–
–
–
DPX1
–
DPH1
6/E
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
DPS
7/F
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
The extended data pointer SFRs, DPX0, DPX1, MXAX, and
P2AX, hold the most significant parts of memory addresses
during access to the xdata space. These SFRs are used only
with the MOVX instructions.
During a MOVX instruction using the DPTR0/DPTR1 register,
the most significant byte of the address is always equal to the
contents of DPX0/DPX1.
During a MOVX instruction using the R0 or R1 register, the most
significant byte of the address is always equal to the contents of
MXAX, and the next most significant byte is always equal to the
contents of P2AX.
5.7.3.2 I/O Port SFRs
The I/O ports provide digital input sensing, output drive, pin
interrupts, connectivity for analog inputs and outputs, LCD, and
access to peripherals through the DSI. Full information on I/O
ports is found in I/O System and Routing on page 37.
Page 27 of 128
PSoC® 3: CY8C32 Family Data Sheet
I/O ports are linked to the CPU through the PHUB and are also
available in the SFRs. Using the SFRs allows faster access to a
limited set of I/O port registers, while using the PHUB allows boot
configuration and access to all I/O port registers.
Each SFR supported I/O port provides three SFRs:
SFRPRTxDR sets the output data state of the port (where x is
port number and includes ports 0 – 6, 12 and 15).
The SFRPRTxSEL selects whether the PHUB PRTxDR
register or the SFRPRTxDR controls each pin’s output buffer
within the port. If a SFRPRTxSEL[y] bit is high, the
corresponding SFRPRTxDR[y] bit sets the output state for that
pin. If a SFRPRTxSEL[y] bit is low, the corresponding
PRTxDR[y] bit sets the output state of the pin (where y varies
from 0 to 7).
The SFRPRTxPS is a read only register that contains pin state
values of the port pins.
5.7.4 xdata Space
The 8051 xdata space is 24-bit, or 16 MB in size. The majority of
this space is not “external”—it is used by on-chip components.
See Table 5-5. External, that is, off-chip, memory can be
accessed using the EMIF. See External Memory Interface on
page 26.
6. System Integration
6.1 Clocking System
The clocking system generates, divides, and distributes clocks
throughout the PSoC system. For the majority of systems, no
external crystal is required. The IMO and PLL together can
generate up to a 50 MHz clock, accurate to ±2 percent over
voltage and temperature. Additional internal and external clock
sources allow each design to optimize accuracy, power, and
cost. Any of the clock sources can be used to generate other
clock frequencies in the 16-bit clock dividers and UDBs for
anything the user wants, for example a UART baud rate
generator.
Clock generation and distribution is automatically configured
through the PSoC Creator IDE graphical interface. This is based
on the complete system’s requirements. It greatly speeds the
design process. PSoC Creator allows you to build clocking
systems with minimal input. You can specify desired clock
frequencies and accuracies, and the software locates or builds a
clock that meets the required specifications. This is possible
because of the programmability inherent in PSoC.
Key features of the clocking system include:
Seven general purpose clock sources
0×00 4500 – 0×00 45FF
Ports interrupt control
0×00 4700 – 0×00 47FF
Flash programming interface
3- to 24-MHz IMO, ±2 percent at 3 MHz
4- to 25-MHz external crystal oscillator (MHzECO)
Clock doubler provides a doubled clock frequency output for
the USB block, see USB Clock Domain on page 31
DSI signal from an external I/O pin or other logic
24- to 50- MHz fractional PLL sourced from IMO, MHzECO,
or DSI
1-kHz, 33-kHz, 100-kHz ILO for watchdog timer (WDT) and
sleep timer
32.768-kHz external crystal oscillator (kHzECO) for RTC
IMO has a USB mode that auto locks to the USB bus clock
requiring no external crystal for USB. (USB equipped parts only)
0×00 4800 – 0×00 48FF
Cache controller
Independently sourced clock in all clock dividers
0×00 4900 – 0×00 49FF
I2
Eight 16-bit clock dividers for the digital system
Table 5-5. XDATA Data Address Map
Address Range
Purpose
0×00 0000 – 0×00 1FFF
SRAM
0×00 4000 – 0×00 42FF
Clocking, PLLs, and oscillators
0×00 4300 – 0×00 43FF
Power management
0×00 4400 – 0×00 44FF
Interrupt controller
C controller
0×00 4E00 – 0×00 4EFF Decimator
Four 16-bit clock dividers for the analog system
0×00 4F00 – 0×00 4FFF Fixed timer/counter/PWMs
Dedicated 16-bit divider for the bus clock
0×00 5000 – 0×00 51FF
I/O ports control
Dedicated 4-bit divider for the CPU clock
0×00 5400 – 0×00 54FF
External Memory Interface (EMIF)
control registers
Automatic clock configuration in PSoC Creator
0×00 5800 – 0×00 5FFF
Analog Subsystem interface
0×00 6000 – 0×00 60FF
USB controller
0×00 6400 – 0×00 6FFF
UDB Working Registers
0×00 7000 – 0×00 7FFF
PHUB configuration
0×00 8000 – 0×00 8FFF
EEPROM
0×01 0000 – 0×01 FFFF Digital Interconnect configuration
0×05 0220 – 0×05 02F0
Debug controller
0×08 0000 – 0×08 1FFF
Flash ECC bytes
0×80 0000 – 0×FF FFFF External Memory Interface
Document Number: 001-56955 Rev. *Y
Page 28 of 128
PSoC® 3: CY8C32 Family Data Sheet
Table 6-1. Oscillator Summary
Source
IMO
MHzECO
Fmin
3 MHz
4 MHz
Tolerance at Fmin
±2% over voltage and temperature
Crystal dependent
Fmax
24 MHz
25 MHz
Tolerance at Fmax
±4%
Crystal dependent
DSI
PLL
Doubler
ILO
0 MHz
24 MHz
48 MHz
1 kHz
Input dependent
Input dependent
Input dependent
–50%, +100%
33 MHz
50 MHz
48 MHz
100 kHz
Input dependent
Input dependent
Input dependent
–55%, +100%
kHzECO
32 kHz
Crystal dependent
32 kHz
Crystal dependent
Startup Time
13-µs max
5 ms typ, max is
crystal dependent
Input dependent
250 µs max
1 µs max
15 ms max in lowest
power mode
500 ms typ, max is
crystal dependent
Figure 6-1. Clocking Subsystem
3-24 MHz
IMO
4-25 MHz
ECO
External IO
or DSI
0-33 MHz
32 kHz ECO
1,33,100 kHz
ILO
CPU Clock Divider
4 bit
48 MHz
Doubler for
USB
24-50 MHz
PLL
Master
Mux
Bus
Clock
Bus Clock Divider
16 bit
7
Digital Clock
Divider 16 bit
Digital Clock
Divider 16 bit
Analog Clock
Divider 16 bit
s
k
e
w
Digital Clock
Divider 16 bit
Digital Clock
Divider 16 bit
Analog Clock
Divider 16 bit
s
k
e
w
Digital Clock
Divider 16 bit
Digital Clock
Divider 16 bit
Analog Clock
Divider 16 bit
s
k
e
w
Digital Clock
Divider 16 bit
Digital Clock
Divider 16 bit
Analog Clock
Divider 16 bit
s
k
e
w
7
Document Number: 001-56955 Rev. *Y
CPU
Clock
Page 29 of 128
PSoC® 3: CY8C32 Family Data Sheet
6.1.1 Internal Oscillators
Figure 6-1 shows that there are two internal oscillators. They can
be routed directly or divided. The direct routes may not have a
50% duty cycle. Divided clocks have a 50% duty cycle.
6.1.1.1 Internal Main Oscillator
In most designs the IMO is the only clock source required, due
to its ±2-percent accuracy. The IMO operates with no external
components and outputs a stable clock. A factory trim for each
frequency range is stored in the device. With the factory trim,
tolerance varies from ±2 percent at 3 MHz, up to ±4-percent at
24 MHz. The IMO, in conjunction with the PLL, allows generation
of other clocks up to the device's maximum frequency (see
Phase-locked Loop)
The IMO provides clock outputs at 3, 6, 12, and 24 MHz.
6.1.1.2 Clock Doubler
The clock doubler outputs a clock at twice the frequency of the
input clock. The doubler works at input frequency of 24 MHz,
providing 48 MHz for the USB. It can be configured to use a clock
from the IMO, MHzECO, or the DSI (external pin).
6.1.1.3 Phase-locked Loop
The PLL allows low-frequency, high-accuracy clocks to be
multiplied to higher frequencies. This is a tradeoff between
higher clock frequency and accuracy and, higher power
consumption and increased startup time.
The PLL block provides a mechanism for generating clock
frequencies based upon a variety of input sources. The PLL
outputs clock frequencies in the range of 24 to 50 MHz. Its input
and feedback dividers supply 4032 discrete ratios to create
almost any desired clock frequency. The accuracy of the PLL
output depends on the accuracy of the PLL input source. The
most common PLL use is to multiply the IMO clock at 3 MHz,
where it is most accurate to generate the other clocks up to the
device’s maximum frequency.
The PLL achieves phase lock within 250 µs (verified by bit
setting). It can be configured to use a clock from the IMO,
MHzECO or DSI (external pin). The PLL clock source can be
used until lock is complete and signaled with a lock bit. The lock
signal can be routed through the DSI to generate an interrupt.
Disable the PLL before entering low-power modes.
6.1.1.4 Internal Low-Speed Oscillator
The ILO provides clock frequencies for low-power consumption,
including the watchdog timer, and sleep timer. The ILO
generates up to three different clocks: 1 kHz, 33 kHz, and
100 kHz.
The 1 kHz clock (CLK1K) is typically used for a background
‘heartbeat’ timer. This clock inherently lends itself to low-power
supervisory operations such as the watchdog timer and long
sleep intervals using the central timewheel (CTW).
The central timewheel is a 1 kHz, free running, 13-bit counter
clocked by the ILO. The central timewheel is always enabled,
except in hibernate mode and when the CPU is stopped during
debug on chip mode. It can be used to generate periodic
interrupts for timing purposes or to wake the system from a
low-power mode. Firmware can reset the central timewheel.
Systems that require accurate timing should use the RTC
capability instead of the central timewheel.
Document Number: 001-56955 Rev. *Y
The 100-kHz clock (CLK100K) can be used as a low power
master clock. It can also generate time intervals using the fast
timewheel.
The fast timewheel is a 5-bit counter, clocked by the 100-kHz
clock. It features programmable settings and automatically
resets when the terminal count is reached. An optional interrupt
can be generated each time the terminal count is reached. This
enables flexible, periodic interrupts of the CPU at a higher rate
than is allowed using the central timewheel.
The 33-kHz clock (CLK33K) comes from a divide-by-3 operation
on CLK100K. This output can be used as a reduced accuracy
version of the 32.768-kHz ECO clock with no need for a crystal.
6.1.2 External Oscillators
Figure 6-1 shows that there are two external oscillators. They
can be routed directly or divided. The direct routes may not have
a 50% duty cycle. Divided clocks have a 50% duty cycle.
6.1.2.1 MHz External Crystal Oscillator
The MHzECO provides high frequency, high precision clocking
using an external crystal (see Figure 6-2). It supports a wide
variety of crystal types, in the range of 4 to 25 MHz. When used
in conjunction with the PLL, it can generate other clocks up to the
device's maximum frequency (see “Phase-locked Loop” section
on page 30). The GPIO pins connecting to the external crystal
and capacitors are fixed. MHzECO accuracy depends on the
crystal chosen.
Figure 6-2. MHzECO Block Diagram
4 - 25 MHz
Crystal Osc
Xi
(Pin P15[1])
External
Components
XCLK_MHZ
Xo
(Pin P15[0])
4 – 25 MHz
crystal
Capacitors
6.1.2.2 32.768-kHz ECO
The 32.768-kHz External Crystal Oscillator (32kHzECO)
provides precision timing with minimal power consumption using
an external 32.768-kHz watch crystal (see Figure 6-3). The
32kHzECO also connects directly to the sleep timer and provides
the source for the RTC. The RTC uses a 1-second interrupt to
implement the RTC functionality in firmware.
The oscillator works in two distinct power modes. This allows
users to trade off power consumption with noise immunity from
neighboring circuits. The GPIO pins connected to the external
crystal and capacitors are fixed.
Page 30 of 128
PSoC® 3: CY8C32 Family Data Sheet
Figure 6-3. 32kHzECO Block Diagram
32 kHz
Crystal Osc
Xi
(Pin P15[3])
XCLK32K
Xo
(Pin P15[2])
External
Components
32 kHz
crystal
Capacitors
It is recommended that the external 32.768-kHz watch crystal
have a load capacitance (CL) of 6 pF or 12.5 pF. Check the
crystal manufacturer's datasheet. The two external capacitors,
CL1 and CL2, are typically of the same value, and their total
capacitance, CL1CL2 / (CL1 + CL2), including pin and trace
capacitance, should equal the crystal CL value. For more
information, refer to application note AN54439: PSoC 3 and
PSoC 5 External Oscillators. See also pin capacitance
specifications in the “GPIO” section on page 76.
6.1.2.3 Digital System Interconnect
The DSI provides routing for clocks taken from external clock
oscillators connected to I/O. The oscillators can also be
generated within the device in the digital system and Universal
Digital Blocks.
While the primary DSI clock input provides access to all clocking
resources, up to eight other DSI clocks (internally or externally
generated) may be routed directly to the eight digital clock
dividers. This is only possible if there are multiple precision clock
sources.
6.1.3 Clock Distribution
All seven clock sources are inputs to the central clock distribution
system. The distribution system is designed to create multiple
high precision clocks. These clocks are customized for the
design’s requirements and eliminate the common problems
found with limited resolution prescalers attached to peripherals.
The clock distribution system generates several types of clock
trees.
Bus Clock 16-bit divider uses the master clock to generate the
bus clock used for data transfers. Bus clock is the source clock
for the CPU clock divider.
Eight fully programmable 16-bit clock dividers generate digital
system clocks for general use in the digital system, as
configured by the design’s requirements. Digital system clocks
can generate custom clocks derived from any of the seven
clock sources for any purpose. Examples include baud rate
generators, accurate PWM periods, and timer clocks, and
many others. If more than eight digital clock dividers are
required, the Universal Digital Blocks (UDBs) and fixed function
Timer/Counter/PWMs can also generate clocks.
Four 16-bit clock dividers generate clocks for the analog system
components that require clocking, such as ADC. The analog
clock dividers include skew control to ensure that critical analog
events do not occur simultaneously with digital switching
events. This is done to reduce analog system noise.
Each clock divider consists of an 8-input multiplexer, a 16-bit
clock divider (divide by 2 and higher) that generates ~50 percent
duty cycle clocks, master clock resynchronization logic, and
deglitch logic. The outputs from each digital clock tree can be
routed into the digital system interconnect and then brought back
into the clock system as an input, allowing clock chaining of up
to 32 bits.
6.1.4 USB Clock Domain
The USB clock domain is unique in that it operates largely
asynchronously from the main clock network. The USB logic
contains a synchronous bus interface to the chip, while running
on an asynchronous clock to process USB data. The USB logic
requires a 48 MHz frequency. This frequency can be generated
from different sources, including DSI clock at 48 MHz or doubled
value of 24 MHz from internal oscillator, DSI signal, or crystal
oscillator.
6.2 Power System
The power system consists of separate analog, digital, and I/O
supply pins, labeled VDDA, VDDD, and VDDIOX, respectively. It
also includes two internal 1.8 V regulators that provide the digital
(VCCD) and analog (VCCA) supplies for the internal core logic.
The output pins of the regulators (VCCD and VCCA) and the
VDDIO pins must have capacitors connected as shown in
Figure 6-4. The two VCCD pins must be shorted together, with
as short a trace as possible, and connected to a 1-µF
±10-percent X5R capacitor. The power system also contains a
sleep regulator, an I2C regulator, and a hibernate regulator.
The master clock is used to select and supply the fastest clock
in the system for general clock requirements and clock
synchronization of the PSoC device.
Document Number: 001-56955 Rev. *Y
Page 31 of 128
PSoC® 3: CY8C32 Family Data Sheet
Figure 6-4. PSoC Power System
VDDD
1 µF
VDDIO2
VDDD
I/ O Supply
VSSD
VCCD
VDDIO 2
VDDIO0
0.1µF
0.1µF
I/O Supply
VDDIO0
0.1µF
I2C
Regulator
Sleep
Regulator
Digital
Domain
VDDA
VDDA
Analog
Regulator
Digital
Regulators
VSSB
VCCA
0.1µF
1 µF
VSSA
VDDD
VSSD
I/O Supply
VCCD
VDDIO1
Hibernate
Regulator
0.1µF
I/O Supply
VDDIO3
Analog
Domain
0.1µF
0.1µF
VDDIO1
VDDD
VDDIO3
Notes
The two VCCD pins must be connected together with as short a trace as possible. A trace under the device is recommended, as
shown in Figure 2-8 on page 12.
It is good practice to check the datasheets for your bypass capacitors, specifically the working voltage and the DC bias specifications.
With some capacitors, the actual capacitance can decrease considerably when the DC bias (VDDX or VCCX in Figure 6-4) is a
significant percentage of the rated working voltage.
You can power the device in internally regulated mode, where the voltage applied to the VDDx pins is as high as 5.5 V, and the
internal regulators provide the core voltages. In this mode, do not apply power to the VCCx pins, and do not tie the VDDx pins
to the VCCx pins.
You can also power the device in externally regulated mode, that is, by directly powering the VCCD and VCCA pins. In this
configuration, the VDDD pins should be shorted to the VCCD pins and the VDDA pin should be shorted to the VCCA pin. The
allowed supply range in this configuration is 1.71 V to 1.89 V. After power up in this configuration, the internal regulators are on by
default, and should be disabled to reduce power consumption.
Document Number: 001-56955 Rev. *Y
Page 32 of 128
PSoC® 3: CY8C32 Family Data Sheet
6.2.1 Power Modes
PSoC 3 devices have four different power modes, as shown in
Table 6-2 and Table 6-3. The power modes allow a design to
easily provide required functionality and processing power while
simultaneously minimizing power consumption and maximizing
battery life in low-power and portable devices.
PSoC 3 power modes, in order of decreasing power
consumption are:
Active
Alternate Active
Active is the main processing mode. Its functionality is
configurable. Each power controllable subsystem is enabled or
disabled by using separate power configuration template
registers. In alternate active mode, fewer subsystems are
enabled, reducing power. In sleep mode most resources are
disabled regardless of the template settings. Sleep mode is
optimized to provide timed sleep intervals and RTC functionality.
The lowest power mode is hibernate, which retains register and
SRAM state, but no clocks, and allows wakeup only from I/O
pins. Figure 6-5 illustrates the allowable transitions between
power modes. Sleep and hibernate modes should not be entered
until all VDDIO supplies are at valid voltage levels.
Sleep
Hibernate
Table 6-2. Power Modes
Power Modes
Description
Entry Condition Wakeup Source
Active Clocks
Regulator
Active
Primary mode of operation, all Wakeup, reset,
peripherals available (program- manual register
mable)
entry
Any interrupt
Any
All regulators available.
(programmable) Digital and analog
regulators can be disabled
if external regulation used.
Alternate
Active
Manual register
Similar to Active mode, and is
entry
typically configured to have
fewer peripherals active to
reduce power. One possible
configuration is to use the UDBs
for processing, with the CPU
turned off
Any interrupt
Any
All regulators available.
(programmable) Digital and analog
regulators can be disabled
if external regulation used.
Sleep
All subsystems automatically
disabled
Comparator,
ILO/kHzECO
PICU, I2C, RTC,
CTW, LVD
Both digital and analog
regulators buzzed.
Digital and analog
regulators can be disabled
if external regulation used.
Hibernate
All subsystems automatically
Manual register
disabled
entry
Lowest power consuming mode
with all peripherals and internal
regulators disabled, except
hibernate regulator is enabled
Configuration and memory
contents retained
PICU
Only hibernate regulator
active.
Manual register
entry
Table 6-3. Power Modes Wakeup Time and Power Consumption
Sleep
Modes
Wakeup
Time
Current
(typ)
Code
Execution
Digital
Resources
Analog
Resources
Clock Sources
Available
Wakeup Sources
Reset
Sources
Active
–
1.2 mA[11]
Yes
All
All
All
–
All
Alternate
Active
–
–
User
defined
All
All
All
–
All
<15 µs
1 µA
No
I2C
Comparator
ILO/kHzECO
Comparator,
PICU, I2C, RTC,
CTW, LVD
XRES, LVD,
WDR
<100 µs
200 nA
No
None
None
None
PICU
XRES
Sleep
Hibernate
Note
11. Bus clock off. Execute from cache at 6 MHz. See Table 11-2 on page 68.
Document Number: 001-56955 Rev. *Y
Page 33 of 128
PSoC® 3: CY8C32 Family Data Sheet
Figure 6-5. Power Mode Transitions
Active
Manual
Sleep
Hibernate
6.2.1.5 Wakeup Events
Wakeup events are configurable and can come from an interrupt
or device reset. A wakeup event restores the system to active
mode. Firmware enabled interrupt sources include internally
generated interrupts, power supervisor, central timewheel, and
I/O interrupts. Internal interrupt sources can come from a variety
of peripherals, such as analog comparators and UDBs. The
central timewheel provides periodic interrupts to allow the
system to wake up, poll peripherals, or perform real-time
functions. Reset event sources include the external reset I/O pin
(XRES), WDT, and Precision Reset (PRES).
6.2.2 Boost Converter
Alternate
Active
6.2.1.1 Active Mode
Active mode is the primary operating mode of the device. When
in active mode, the active configuration template bits control
which available resources are enabled or disabled. When a
resource is disabled, the digital clocks are gated, analog bias
currents are disabled, and leakage currents are reduced as
appropriate. User firmware can dynamically control subsystem
power by setting and clearing bits in the active configuration
template. The CPU can disable itself, in which case the CPU is
automatically reenabled at the next wakeup event.
When a wakeup event occurs, the global mode is always
returned to active, and the CPU is automatically enabled,
regardless of its template settings. Active mode is the default
global power mode upon boot.
6.2.1.2 Alternate Active Mode
Alternate Active mode is very similar to Active mode. In alternate
active mode, fewer subsystems are enabled, to reduce power
consumption. One possible configuration is to turn off the CPU
and flash, and run peripherals at full speed.
6.2.1.3 Sleep Mode
Sleep mode reduces power consumption when a resume time of
15 µs is acceptable. The wake time is used to ensure that the
regulator outputs are stable enough to directly enter active
mode.
6.2.1.4 Hibernate Mode
In hibernate mode nearly all of the internal functions are
disabled. Internal voltages are reduced to the minimal level to
keep vital systems alive. Configuration state is preserved in
hibernate mode and SRAM memory is retained. GPIOs
configured as digital outputs maintain their previous values and
external GPIO pin interrupt settings are preserved. The device
can only return from hibernate mode in response to an external
I/O interrupt. The resume time from hibernate mode is less than
100 µs.
To achieve an extremely low current, the hibernate regulator has
limited capacity. This limits the frequency of any signal present
on the input pins - no GPIO should toggle at a rate greater than
10 kHz while in hibernate mode. If pins must be toggled at a high
rate while in a low power mode, use sleep mode instead.
Document Number: 001-56955 Rev. *Y
Applications that use a supply voltage of less than 1.71 V, such
as solar panels or single cell battery supplies, may use the
on-chip boost converter to generate a minimum of 1.8 V supply
voltage. The boost converter may also be used in any system
that requires a higher operating voltage than the supply provides
such as driving 5.0 V LCD glass in a 3.3 V system. With the
addition of an inductor, Schottky diode, and capacitors, it
produces a selectable output voltage sourcing enough current to
operate the PSoC and other on-board components.
The boost converter accepts an input voltage VBAT from 0.5 V to
3.6 V, and can start up with VBAT as low as 0.5 V. The converter
provides a user configurable output voltage of 1.8 to 5.0 V (VOUT)
in 100 mV increments. VBAT is typically less than VOUT; if VBAT is
greater than or equal to VOUT, then VOUT will be slightly less than
VBAT due to resistive losses in the boost converter. The block can
deliver up to 50 mA (IBOOST) depending on configuration to both
the PSoC device and external components. The sum of all
current sinks in the design including the PSoC device, PSoC I/O
pin loads, and external component loads must be less than the
IBOOST specified maximum current.
Four pins are associated with the boost converter: VBAT, VSSB,
VBOOST, and IND. The boosted output voltage is sensed at the
VBOOST pin and must be connected directly to the chip’s supply
inputs, VDDA, VDDD, and VDDIO, if used to power the PSoC
device.
The boost converter requires four components in addition to
those required in a non-boost design, as shown in Figure 6-6 on
page 35. A 22-µF capacitor (CBAT) is required close to the VBAT
pin to provide local bulk storage of the battery voltage and
provide regulator stability. A diode between the battery and VBAT
pin should not be used for reverse polarity protection because
the diodes forward voltage drop reduces the VBAT voltage.
Between the VBAT and IND pins, an inductor of 4.7 µH, 10 µH,
or 22 µH is required. The inductor value can be optimized to
increase the boost converter efficiency based on input voltage,
output voltage, temperature, and current. Inductor size is
determined by following the design guidance in this section and
the electrical specifications. The inductor must be placed within
1 cm of the VBAT and IND pins and have a minimum saturation
current of 750 mA. Between the IND and VBOOST pins, place a
Schottky diode within 1 cm of the pins. This diode shall have a
forward current rating of at least 1.0 A and a reverse voltage of
at least 20 V. Connect a 22-µF bulk capacitor (CBOOST) close
to VBOOST to provide regulator output stability. It is important to
sum the total capacitance connected to the VBOOST pin and
ensure the maximum CBOOST specification is not exceeded. All
capacitors must be rated for a minimum of 10 V to minimize
capacitive losses due to voltage de-rating.
Page 34 of 128
PSoC® 3: CY8C32 Family Data Sheet
Figure 6-6. Application of Boost Converter powering PSoC device
PSoC
VDDA
External
Load
VDDD
VDDD
0.1 µF
1.0 µF
0.1 µF
1.0 µF
0.1 µF
1.0 µF
VBOOST
Schottky, 1A
IND
4.7 µH
10 µH
22 µH
VDDIO0
0.1 µF
Boost VDDIO2
Logic
VDDIO1
VBAT
22 µF
0.1 µF
0.1 µF
VDDIO3
VSSB
0.1 µF
0.5–3.6 V
VSSA
22 µF
VSSD
All components and values are required
The boost converter may also generate a supply that is not used
directly by the PSoC device. An example of this use case is
boosting a 1.8 V supply to 4.0 V to drive a white LED. If the boost
converter is not supplying the PSoC devices VDDA, VDDD, and
VDDIO it must comply with the same design rules as supplying
the PSoC device, but with a change to the bulk capacitor
requirements. A parallel arrangement 22 µF, 1.0 µF, and 0.1 µF
capacitors are all required on the Vout supply and must be
placed within 1 cm of the VBOOST pin to ensure regulator
stability.
Figure 6-7. Application of Boost Converter not powering PSoC device
VOUT
External
Load
PSoC
VDDA
VDDD
22 µF 1.0 µF 0.1 µF
VDDD
VBOOST
Schottky, 1A
4.7 µH
10 µH
22 µH
IND
VBAT
VDDIO0
VDDA, VDDD, and
VDDIO connections
per section 6.2
Power System.
Boost VDDIO2
Logic
VDDIO1
22 µF
VDDIO3
VSSB
0.5–3.6 V
VSSA
VSSD
All components and values are required
The switching frequency is set to 400 kHz using an oscillator
integrated into the boost converter. The boost converter can be
operated in two different modes: active and standby. Active
mode is the normal mode of operation where the boost regulator
Document Number: 001-56955 Rev. *Y
actively generates a regulated output voltage. In standby mode,
most boost functions are disabled, thus reducing power
consumption of the boost circuit. Only minimal power is provided,
typically < 5 µA to power the PSoC device in Sleep mode. The
Page 35 of 128
PSoC® 3: CY8C32 Family Data Sheet
boost typically draws 250 µA in active mode and 25 µA in
standby mode. The boost operating modes must be used in
conjunction with chip power modes to minimize total power
consumption. Table 6-4 lists the boost power modes available in
different chip power modes.
Table 6-4. Chip and Boost Power Modes Compatibility
Chip Power Modes
Boost Power Modes
Chip-active or alternate Boost must be operated in its active
active mode
mode.
Chip-sleep mode
Boost can be operated in either active
or standby mode. In boost standby
mode, the chip must wake up periodically for boost active-mode refresh.
Chip-hibernate mode
Boost can be operated in its active
mode. However, it is recommended not
to use the boost in chip hibernate mode
due to the higher current consumption
in boost active mode.
6.2.2.1 Boost Firmware Requirements
To ensure boost inrush current is within specification at startup,
the Enable Fast IMO During Startup value must be unchecked
in the PSoC Creator IDE. The Enable Fast IMO During Startup
option is found in PSoC Creator in the design wide resources
(cydwr) file System tab. Un-checking this option configures the
device to run at 12 MHz vs 48 MHz during startup while
configuring the device. The slower clock speed results in
reduced current draw through the boost circuit.
6.2.2.2 Boost Design Process
Correct operation of the boost converter requires specific
component values determined for each designs unique
operating conditions. The CBAT capacitor, Inductor, Schottky
diode, and CBOOST capacitor components are required with the
values specified in the electrical specifications, Table 11-7 on
page 74. The only variable component value is the inductor
LBOOST which is primarily sized for correct operation of the boost
across operating conditions and secondarily for efficiency.
Additional operating region constraints exist for VOUT, VBAT, IOUT,
and TA.
The following steps must be followed to determine boost
converter operating parameters and LBOOST value.
1. Choose desired VBAT, VOUT, TA, and IOUT operating condition
ranges for the application.
2. Determine if VBAT and VOUT ranges fit the boost operating
range based on the TA range over VBAT and VOUT chart,
Figure 11-8 on page 74. If the operating ranges are not met,
modify the operating conditions or use an external boost
regulator.
3. Determine if the desired ambient temperature (TA) range fits
the ambient temperature operating range based on the TA
range over VBAT and VOUT chart, Figure 11-8 on page 74. If
the temperature range is not met, modify the operating conditions and return to step 2, or use an external boost regulator.
4. Determine if the desired output current (IOUT) range fits the
output current operating range based on the IOUT range over
VBAT and VOUT chart, Figure 11-9 on page 74. If the output
Document Number: 001-56955 Rev. *Y
current range is not met, modify the operating conditions and
return to step 2, or use an external boost regulator.
5. Find the allowed inductor values based on the LBOOST values
over VBAT and VOUT chart, Figure 11-10 on page 74.
6. Based on the allowed inductor values, inductor dimensions,
inductor cost, boost efficiency, and VRIPPLE choose the
optimum inductor value for the system. Boost efficiency and
VRIPPLE typical values are provided in the Efficiency vs VBAT
and VRIPPLE vs VBAT charts, Figure 11-11 on page 75 through
Figure 11-14 on page 75. In general, if high efficiency and low
VRIPPLE are most important, then the highest allowed inductor
value should be used. If low inductor cost or small inductor
size are most important, then one of the smaller allowed
inductor values should be used. If the allowed inductor(s)
efficiency, VRIPPLE, cost or dimensions are not acceptable for
the application than an external boost regulator should be
used.
6.3 Reset
CY8C32 has multiple internal and external reset sources
available. The reset sources are:
Power source monitoring – The analog and digital power
voltages, VDDA, VDDD, VCCA, and VCCD are monitored in
several different modes during power up, active mode, and
sleep mode (buzzing). If any of the voltages goes outside
predetermined ranges then a reset is generated. The monitors
are programmable to generate an interrupt to the processor
under certain conditions before reaching the reset thresholds.
External – The device can be reset from an external source by
pulling the reset pin (XRES) low. The XRES pin includes an
internal pull-up to VDDIO1. VDDD, VDDA, and VDDIO1 must
all have voltage applied before the part comes out of reset.
Watchdog timer – A watchdog timer monitors the execution of
instructions by the processor. If the watchdog timer is not reset
by firmware within a certain period of time, the watchdog timer
generates a reset.
Software – The device can be reset under program control.
Figure 6-8. Resets
VDDD VDDA
Power
Voltage
Level
Monitors
Reset
Pin
External
Reset
Processor
Interrupt
Reset
Controller
System
Reset
Watchdog
Timer
Software
Reset
Register
Page 36 of 128
PSoC® 3: CY8C32 Family Data Sheet
The term device reset indicates that the processor as well as
analog and digital peripherals and registers are reset.
A reset status register shows some of the resets or power voltage
monitoring interrupts. The program may examine this register to
detect and report certain exception conditions. This register is
cleared after a power-on reset. For details see the Technical
Reference Manual.
6.3.1 Reset Sources
6.3.1.1 Power Voltage Level Monitors
IPOR – Initial Power-on Reset
At initial power on, IPOR monitors the power voltages VDDD,
VDDA, VCCD, and VCCA. The trip level is not precise. It is set
to approximately 1 volt, which is below the lowest specified
operating voltage but high enough for the internal circuits to be
reset and to hold their reset state. The monitor generates a
reset pulse that is at least 150 ns wide. It may be much wider
if one or more of the voltages ramps up slowly.
After boot, the IPOR circuit is disabled and voltage supervision
is handed off to the precise low-voltage reset (PRES) circuit.
PRES – Precise Low Voltage Reset
This circuit monitors the outputs of the analog and digital
internal regulators after power up. The regulator outputs are
compared to a precise reference voltage. The response to a
PRES trip is identical to an IPOR reset.
In normal operating mode, the program cannot disable the
digital PRES circuit. The analog regulator can be disabled,
which also disables the analog portion of the PRES. The PRES
circuit is disabled automatically during sleep and hibernate
modes, with one exception: During sleep mode the regulators
are periodically activated (buzzed) to provide supervisory
services and to reduce wakeup time. At these times the PRES
circuit is also buzzed to allow periodic voltage monitoring.
ALVI, DLVI, AHVI – Analog/Digital Low Voltage Interrupt,
The buzz frequency is adjustable, and should be set to be less
than the minimum time that any voltage is expected to be out
of range. For details on how to adjust the buzz frequency, see
the TRM.
6.3.1.2 Other Reset Sources
XRES – External Reset
PSoC 3 has either a single GPIO pin that is configured as an
external reset or a dedicated XRES pin. Either the dedicated
XRES pin or the GPIO pin, if configured, holds the part in reset
while held active (low). The response to an XRES is the same
as to an IPOR reset.
After XRES has been deasserted, at least 10 µs must elapse
before it can be reasserted.
The external reset is active low. It includes an internal pull-up
resistor. XRES is active during sleep and hibernate modes.
SRES – Software Reset
A reset can be commanded under program control by setting
a bit in the software reset register. This is done either directly
by the program or indirectly by DMA access. The response to
a SRES is the same as after an IPOR reset.
Another register bit exists to disable this function.
WRES – Watchdog Timer Reset
The watchdog reset detects when the software program is no
longer being executed correctly. To indicate to the watchdog
timer that it is running correctly, the program must periodically
reset the timer. If the timer is not reset before a user-specified
amount of time, then a reset is generated.
Note IPOR disables the watchdog function. The program must
enable the watchdog function at an appropriate point in the
code by setting a register bit. When this bit is set, it cannot be
cleared again except by an IPOR power-on reset event.
Analog High Voltage Interrupt
6.4 I/O System and Routing
Interrupt circuits are available to detect when VDDA and
VDDD go outside a voltage range. For AHVI, VDDA is
compared to a fixed trip level. For ALVI and DLVI, VDDA and
VDDD are compared to trip levels that are programmable, as
listed in Table 6-5. ALVI and DLVI can also be configured to
generate a device reset instead of an interrupt.
PSoC I/Os are extremely flexible. Every GPIO has analog and
digital I/O capability. All I/Os have a large number of drive modes,
which are set at POR. PSoC also provides up to four individual
I/O voltage domains through the VDDIO pins.
Table 6-5. Analog/Digital Low Voltage Interrupt, Analog High
Voltage Interrupt
Voltage Available Trip Settings
Interrupt Supply Normal
Range
DLVI
VDDD 1.71 V – 5.5 V
1.70 V – 5.45 V in 250
mV increments
ALVI
VDDA 1.71 V – 5.5 V
1.70 V – 5.45 V in 250
mV increments
AHVI
VDDA 1.71 V – 5.5 V
5.75 V
The monitors are disabled until after IPOR. During sleep mode
these circuits are periodically activated (buzzed). If an interrupt
occurs during buzzing then the system first enters its wake up
sequence. The interrupt is then recognized and may be
serviced.
Document Number: 001-56955 Rev. *Y
There are two types of I/O pins on every device; those with USB
provide a third type. Both GPIO and Special I/O (SIO) provide
similar digital functionality. The primary differences are their
analog capability and drive strength. Devices that include USB
also provide two USBIO pins that support specific USB
functionality as well as limited GPIO capability.
All I/O pins are available for use as digital inputs and outputs for
both the CPU and digital peripherals. In addition, all I/O pins can
generate an interrupt. The flexible and advanced capabilities of
the PSoC I/O, combined with any signal to any pin routability,
greatly simplify circuit design and board layout. All GPIO pins can
be used for analog input, CapSense, and LCD segment drive,
while SIO pins are used for voltages in excess of VDDA and for
programmable output voltages.
Features supported by both GPIO and SIO:
User programmable port reset state
Separate I/O supplies and voltages for up to four groups of I/O
Digital peripherals use DSI to connect the pins
Page 37 of 128
PSoC® 3: CY8C32 Family Data Sheet
Input or output or both for CPU and DMA
Eight drive modes
Every pin can be an interrupt source configured as rising
edge, falling edge or both edges. If required, level sensitive
interrupts are supported through the DSI
Dedicated port interrupt vector for each port
Slew rate controlled digital output drive mode
Access port control and configuration registers on either port
basis or pin basis
Separate port read (PS) and write (DR) data registers to avoid
read modify write errors
Special functionality on a pin by pin basis
Additional features only provided on the GPIO pins:
LCD segment drive on LCD equipped devices
CapSense
Analog input and output capability
Continuous 100 µA clamp current capability
Document Number: 001-56955 Rev. *Y
Standard drive strength down to 1.7 V
Additional features only provided on SIO pins:
Higher drive strength than GPIO
Hot swap capability (5 V tolerance at any operating VDD)
Programmable and regulated high input and output drive
levels down to 1.2 V
No analog input, CapSense, or LCD capability
Overvoltage tolerance up to 5.5 V
SIO can act as a general purpose analog comparator
USBIO features:
Full speed USB 2.0 compliant I/O
Highest drive strength for general purpose use
Input, output, or both for CPU and DMA
Input, output, or both for digital peripherals
Digital output (CMOS) drive mode
Each pin can be an interrupt source configured as rising
edge, falling edge, or both edges
Page 38 of 128
PSoC® 3: CY8C32 Family Data Sheet
Figure 6-9. GPIO Block Diagram
Digital Input Path
Naming Convention
‘x’ = Port Number
‘y’ = Pin Number
PRT[x]CTL
PRT[x]DBL_SYNC_IN
PRT[x]PS
Digital System Input
PICU[x]INTTYPE[y]
Input Buffer Disable
PICU[x]INTSTAT
Interrupt
Logic
Pin Interrupt Signal
PICU[x]INTSTAT
Digital Output Path
PRT[x]SLW
PRT[x]SYNC_OUT
Vddio Vddio
PRT[x]DR
0
Digital System Output
In
1
Vddio
PRT[x]BYP
Drive
Logic
PRT[x]DM2
PRT[x]DM1
PRT[x]DM0
Bidirectional Control
PRT[x]BIE
Analog
Slew
Cntl
PIN
OE
1
Capsense Global Control
0
1
0
1
CAPS[x]CFG1
Switches
PRT[x]AG
Analog Global
PRT[x]AMUX
Analog Mux
LCD
Display
Data
PRT[x]LCD_COM_SEG
Logic & MUX
PRT[x]LCD_EN
LCD Bias Bus
Document Number: 001-56955 Rev. *Y
5
Page 39 of 128
PSoC® 3: CY8C32 Family Data Sheet
Figure 6-10. SIO Input/Output Block Diagram
Digital Input Path
PRT[x]SIO_HYST_EN
PRT[x]SIO_DIFF
Reference Level
PRT[x]DBL_SYNC_IN
Naming Convention
‘x’ = Port Number
‘y’ = Pin Number
Buffer
Thresholds
PRT[x]PS
Digital System Input
PICU[x]INTTYPE[y]
Input Buffer Disable
PICU[x]INTSTAT
Interrupt
Logic
Pin Interrupt Signal
PICU[x]INTSTAT
Digital Output Path
Reference Level
PRT[x]SIO_CFG
PRT[x]SLW
PRT[x]SYNC_OUT
PRT[x]DR
Driver
Vhigh
0
Digital System Output
In
1
PRT[x]BYP
Drive
Logic
PRT[x]DM2
PRT[x]DM1
PRT[x]DM0
Bidirectional Control
PRT[x]BIE
Slew
Cntl
PIN
OE
Figure 6-11. USBIO Block Diagram
Digital Input Path
Naming Convention
‘y’ = Pin Number
USB Receiver Circuitry
PRT[15]DBL_SYNC_IN
PRT[15]PS[6,7]
USBIO_CR1[0,1]
Digital System Input
PICU[15]INTTYPE[y]
PICU[15]INTSTAT
Interrupt
Logic
Pin Interrupt Signal
PICU[15]INTSTAT
Digital Output Path
PRT[15]SYNC_OUT
USBIO_CR1[5]
USB or I/O
USBIO_CR1[2]
Vddd
USB SIE Control for USB Mode
PRT[15]DR1[7,6]
Digital System Output
PRT[15]BYP
1
In
Drive
Logic
D+ Open
Drain
PRT[15]DM0[7]
D- Open
Drain
PRT[15]DM1[7]
Document Number: 001-56955 Rev. *Y
0
PRT[15]DM0[6]
PRT[15]DM1[6]
D+ pin only
D+ 1.5 k
Vddd
5k
Vddd Vddd
1.5 k
PIN
D+ 5 k
D- 5 k
Page 40 of 128
PSoC® 3: CY8C32 Family Data Sheet
6.4.1 Drive Modes
Each GPIO and SIO pin is individually configurable into one of the eight drive modes listed in Table 6-6. Three configuration bits are
used for each pin (DM[2:0]) and set in the PRTxDM[2:0] registers. Figure 6-12 depicts a simplified pin view based on each of the eight
drive modes. Table 6-6 shows the I/O pin’s drive state based on the port data register value or digital array signal if bypass mode is
selected. Note that the actual I/O pin voltage is determined by a combination of the selected drive mode and the load at the pin. For
example, if a GPIO pin is configured for resistive pull-up mode and driven high while the pin is floating, the voltage measured at the
pin is a high logic state. If the same GPIO pin is externally tied to ground then the voltage unmeasured at the pin is a low logic state.
Figure 6-12. Drive Mode
VDD
Out
In
Pin
Out
In
Pin
Out
In
VDD
Pin
Out
In
Pin
An
An
An
An
0. High Impedance
Analog
1. High Impedance
Digital
2. Resistive Pull-Up
3. Resistive Pull-Down
VDD
Out
In
Pin
Out
In
VDD
Pin
Out
In
VDD
Pin
Out
In
Pin
An
An
An
An
4. Open Drain,
Drives Low
5. Open Drain,
Drives High
6. Strong Drive
7. Resistive Pull-Up
and Pull-Down
The ‘Out’ connection is driven from either the Digital System (when the Digital Output terminal is connected) or the Data Register
(when HW connection is disabled).
The ‘In’ connection drives the Pin State register, and the Digital System if the Digital Input terminal is enabled and connected.
The ‘An’ connection connects to the Analog System.
Table 6-6. Drive Modes
Diagram
PRTxDM2
PRTxDM1
PRTxDM0
PRTxDR = 1
PRTxDR = 0
0
High impedence analog
Drive Mode
0
0
0
High Z
High Z
1
High Impedance digital
0
0
1
High Z
High Z
2
Resistive pull-up[12]
0
1
0
Res High (5K)
Strong Low
3
Resistive pull-down[12]
0
1
1
Strong High
Res Low (5K)
4
Open drain, drives low
1
0
0
High Z
Strong Low
5
Open drain, drive high
1
0
1
Strong High
High Z
6
Strong drive
1
1
0
Strong High
Strong Low
7
Resistive pull-up and pull-down[12]
1
1
1
Res High (5K)
Res Low (5K)
Note
12. Resistive pull-up and pull-down are not available with SIO in regulated output mode.
Document Number: 001-56955 Rev. *Y
Page 41 of 128
PSoC® 3: CY8C32 Family Data Sheet
The USBIO pins (P15[7] and P15[6]), when enabled for I/O mode, have limited drive mode control. The drive mode is set using the
PRT15.DM0[7, 6] register. A resistive pull option is also available at the USBIO pins, which can be enabled using the PRT15.DM1[7,
6] register. When enabled for USB mode, the drive mode control has no impact on the configuration of the USB pins. Unlike the GPIO
and SIO configurations, the port wide configuration registers do not configure the USB drive mode bits. Table 6-7 shows the drive
mode configuration for the USBIO pins.
Table 6-7. USBIO Drive Modes (P15[7] and P15[6])
PRT15.DM1[7,6]
Pull up enable
PRT15.DM0[7,6]
Drive Mode enable
0
0
High Z
Strong Low
Open Drain, Strong Low
0
1
Strong High
Strong Low
Strong Outputs
1
0
Res High (5k)
Strong Low
Resistive Pull Up, Strong Low
1
1
Strong High
Strong Low
Strong Outputs
PRT15.DR[7,6] = 1
High Impedance Analog
The default reset state with both the output driver and digital
input buffer turned off. This prevents any current from flowing
in the I/O’s digital input buffer due to a floating voltage. This
state is recommended for pins that are floating or that support
an analog voltage. High impedance analog pins do not provide
digital input functionality.
To achieve the lowest chip current in sleep modes, all I/Os
must either be configured to the high impedance analog mode,
or have their pins driven to a power supply rail by the PSoC
device or by external circuitry.
High Impedance Digital
The input buffer is enabled for digital signal input. This is the
standard high impedance (HiZ) state recommended for digital
inputs.
Resistive pull-up or resistive pull-down
Resistive pull-up or pull-down, respectively, provides a series
resistance in one of the data states and strong drive in the
other. Pins can be used for digital input and output in these
modes. Interfacing to mechanical switches is a common
application for these modes. Resistive pull-up and pull-down
are not available with SIO in regulated output mode.
Open Drain, Drives High and Open Drain, Drives Low
Open drain modes provide high impedance in one of the data
states and strong drive in the other. Pins can be used for digital
input and output in these modes. A common application for
these modes is driving the I2C bus signal lines.
Strong Drive
Provides a strong CMOS output drive in either high or low
state. This is the standard output mode for pins. Strong Drive
mode pins must not be used as inputs under normal
circumstances. This mode is often used to drive digital output
signals or external FETs.
Document Number: 001-56955 Rev. *Y
PRT15.DR[7,6] = 0
Description
Resistive pull-up and pull-down
Similar to the resistive pull-up and resistive pull-down modes
except the pin is always in series with a resistor. The high data
state is pull-up while the low data state is pull-down. This mode
is most often used when other signals that may cause shorts
can drive the bus. Resistive pull-up and pull-down are not
available with SIO in regulated output mode.
6.4.2 Pin Registers
Registers to configure and interact with pins come in two forms
that may be used interchangeably.
All I/O registers are available in the standard port form, where
each bit of the register corresponds to one of the port pins. This
register form is efficient for quickly reconfiguring multiple port
pins at the same time.
I/O registers are also available in pin form, which combines the
eight most commonly used port register bits into a single register
for each pin. This enables very fast configuration changes to
individual pins with a single register write.
6.4.3 Bidirectional Mode
High-speed bidirectional capability allows pins to provide both
the high impedance digital drive mode for input signals and a
second user selected drive mode such as strong drive (set using
PRT×DM[2:0] registers) for output signals on the same pin,
based on the state of an auxiliary control bus signal. The
bidirectional capability is useful for processor busses and
communications interfaces such as the SPI Slave MISO pin that
requires dynamic hardware control of the output buffer.
The auxiliary control bus routes up to 16 UDB or digital peripheral
generated output enable signals to one or more pins.
6.4.4 Slew Rate Limited Mode
GPIO and SIO pins have fast and slow output slew rate options
for strong and open drain drive modes, not resistive drive modes.
Because it results in reduced EMI, the slow edge rate option is
recommended for signals that are not speed critical, generally
less than 1 MHz. The fast slew rate is for signals between 1 MHz
and 33 MHz. The slew rate is individually configurable for each
pin, and is set by the PRT×SLW registers.
Page 42 of 128
PSoC® 3: CY8C32 Family Data Sheet
6.4.5 Pin Interrupts
6.4.11 Adjustable Output Level
All GPIO and SIO pins are able to generate interrupts to the
system. All eight pins in each port interface to their own Port
Interrupt Control Unit (PICU) and associated interrupt vector.
Each pin of the port is independently configurable to detect rising
edge, falling edge, both edge interrupts, or to not generate an
interrupt.
This section applies only to SIO pins. SIO port pins support the
ability to provide a regulated high output level for interface to
external signals that are lower in voltage than the SIO’s
respective VDDIO. SIO pins are individually configurable to
output either the standard VDDIO level or the regulated output,
which is based on an internally generated reference. Typically
the voltage DAC (VDAC) is used to generate the reference (see
Figure 6-13). The “DAC” section on page 61 has more details on
VDAC use and reference routing to the SIO pins. Resistive
pull-up and pull-down drive modes are not available with SIO in
regulated output mode.
Depending on the configured mode for each pin, each time an
interrupt event occurs on a pin, its corresponding status bit of the
interrupt status register is set to “1” and an interrupt request is
sent to the interrupt controller. Each PICU has its own interrupt
vector in the interrupt controller and the pin status register
providing easy determination of the interrupt source down to the
pin level.
Port pin interrupts remain active in all sleep modes allowing the
PSoC device to wake from an externally generated interrupt.
While level sensitive interrupts are not directly supported;
Universal Digital Blocks (UDB) provide this functionality to the
system when needed.
6.4.6 Input Buffer Mode
6.4.12 Adjustable Input Level
This section applies only to SIO pins. SIO pins by default support
the standard CMOS and LVTTL input levels but also support a
differential mode with programmable levels. SIO pins are
grouped into pairs. Each pair shares a reference generator block
which, is used to set the digital input buffer reference level for
interface to external signals that differ in voltage from VDDIO.
The reference sets the pins voltage threshold for a high logic
level (see Figure 6-13). Available input thresholds are:
GPIO and SIO input buffers can be configured at the port level
for the default CMOS input thresholds or the optional LVTTL
input thresholds. All input buffers incorporate Schmitt triggers for
input hysteresis. Additionally, individual pin input buffers can be
disabled in any drive mode.
0.5 VDDIO
6.4.7 I/O Power Supplies
Typically the voltage DAC (VDAC) generates the VREF
reference. The “DAC” section on page 61 has more details on
VDAC use and reference routing to the SIO pins.
Up to four I/O pin power supplies are provided depending on the
device and package. Each I/O supply must be less than or equal
to the voltage on the chip’s analog (VDDA) pin. This feature
allows users to provide different I/O voltage levels for different
pins on the device. Refer to the specific device package pinout
to determine VDDIO capability for a given port and pin.
The SIO port pins support an additional regulated high output
capability, as described in Adjustable Output Level.
0.4 VDDIO
0.5 VREF
VREF
Figure 6-13. SIO Reference for Input and Output
Input Path
Digital
Input
Vinref
6.4.8 Analog Connections
These connections apply only to GPIO pins. All GPIO pins may
be used as analog inputs or outputs. The analog voltage present
on the pin must not exceed the VDDIO supply voltage to which
the GPIO belongs. Each GPIO may connect to one of the analog
global busses or to one of the analog mux buses to connect any
pin to any internal analog resource such as ADC or comparators.
In addition, one select pin provides direct connection to the high
current DAC.
Reference
Generator
SIO_Ref
PIN
Voutref
Output Path
Driver
Vhigh
6.4.9 CapSense
This section applies only to GPIO pins. All GPIO pins may be
used to create CapSense buttons and sliders. See the
“CapSense” section on page 61 for more information.
6.4.10 LCD Segment Drive
This section applies only to GPIO pins. All GPIO pins may be
used to generate Segment and Common drive signals for direct
glass drive of LCD glass. See the “LCD Direct Drive” section on
page 60 for details.
Document Number: 001-56955 Rev. *Y
Digital
Output
Drive
Logic
Page 43 of 128
PSoC® 3: CY8C32 Family Data Sheet
6.4.13 SIO as Comparator
This section applies only to SIO pins. The adjustable input level
feature of the SIOs as explained in the Adjustable Input Level
section can be used to construct a comparator. The threshold for
the comparator is provided by the SIO's reference generator. The
reference generator has the option to set the analog signal
routed through the analog global line as threshold for the
comparator. Note that a pair of SIO pins share the same
threshold.
The digital input path in Figure 6-10 on page 40 illustrates this
functionality. In the figure, ‘Reference level’ is the analog signal
routed through the analog global. The hysteresis feature can
also be enabled for the input buffer of the SIO, which increases
noise immunity for the comparator.
6.4.14 Hot Swap
This section applies only to SIO pins. SIO pins support ‘hot swap’
capability to plug into an application without loading the signals
that are connected to the SIO pins even when no power is
applied to the PSoC device. This allows the unpowered PSoC to
maintain a high impedance load to the external device while also
preventing the PSoC from being powered through a SIO pin’s
protection diode.
Powering the device up or down while connected to an
operational I2C bus may cause transient states on the SIO pins.
The overall I2C bus design should take this into account.
The SIO pin must be in one of the following modes: 0 (high
impedance analog), 1 (high impedance digital), or 4 (open drain
drives low). See Figure 6-12 for details. Absolute maximum
ratings for the device must be observed for all I/O pins.
6.4.16 Reset Configuration
While reset is active all I/Os are reset to and held in the High
Impedance Analog state. After reset is released, the state can be
reprogrammed on a port-by-port basis to pull-down or pull-up. To
ensure correct reset operation, the port reset configuration data
is stored in special nonvolatile registers. The stored reset data is
automatically transferred to the port reset configuration registers
at reset release.
6.4.17 Low-Power Functionality
In all low-power modes the I/O pins retain their state until the part
is awakened and changed or reset. To awaken the part, use a
pin interrupt, because the port interrupt logic continues to
function in all low-power modes.
6.4.18 Special Pin Functionality
Some pins on the device include additional special functionality
in addition to their GPIO or SIO functionality. The specific special
function pins are listed in Pinouts on page 6. The special features
are:
Digital
4- to 25- MHz crystal oscillator
32.768-kHz crystal oscillator
2
Wake from sleep on I C address match. Any pin can be used
2
for I C if wake from sleep is not required.
JTAG interface pins
SWD interface pins
SWV interface pins
External reset
6.4.15 Over Voltage Tolerance
All I/O pins provide an over voltage tolerance feature at any
operating VDD.
There are no current limitations for the SIO pins as they present a
high impedance load to the external circuit where VDDIO < VIN <
5.5 V.
The GPIO pins must be limited to 100 µA using a current limiting
resistor. GPIO pins clamp the pin voltage to approximately one
diode above the VDDIO supply where VDDIO < VIN < VDDA.
In case of a GPIO pin configured for analog input/output, the
analog voltage on the pin must not exceed the VDDIO supply
voltage to which the GPIO belongs.
A common application for this feature is connection to a bus such
as I2C where different devices are running from different supply
voltages. In the I2C case, the PSoC chip is configured into the
Open Drain, Drives Low mode for the SIO pin. This allows an
external pull-up to pull the I2C bus voltage above the PSoC pin
supply. For example, the PSoC chip could operate at 1.8 V, and
an external device could run from 5 V. Note that the SIO pin’s VIH
and VIL levels are determined by the associated VDDIO supply
pin.
Document Number: 001-56955 Rev. *Y
Analog
High current IDAC output
External reference inputs
6.4.19 JTAG Boundary Scan
The device supports standard JTAG boundary scan chains on all
I/O pins for board level test.
Page 44 of 128
PSoC® 3: CY8C32 Family Data Sheet
7. Digital Subsystem
7.1 Example Peripherals
The digital programmable system creates application specific
combinations of both standard and advanced digital peripherals
and custom logic functions. These peripherals and logic are then
interconnected to each other and to any pin on the device,
providing a high level of design flexibility and IP security.
The features of the digital programmable system are outlined
here to provide an overview of capabilities and architecture. You
do not need to interact directly with the programmable digital
system at the hardware and register level. PSoC Creator
provides a high level schematic capture graphical interface to
automatically place and route resources similar to PLDs.
The main components of the digital programmable system are:
Universal Digital Blocks (UDB) – These form the core
functionality of the digital programmable system. UDBs are a
collection of uncommitted logic (PLD) and structural logic
(Datapath) optimized to create all common embedded
peripherals and customized functionality that are application or
design specific.
Universal Digital Block Array – UDB blocks are arrayed within
a matrix of programmable interconnect. The UDB array
structure is homogeneous and allows for flexible mapping of
digital functions onto the array. The array supports extensive
and flexible routing interconnects between UDBs and the
Digital System Interconnect.
Digital System Interconnect (DSI) – Digital signals from
Universal Digital Blocks (UDBs), fixed function peripherals, I/O
pins, interrupts, DMA, and other system core signals are
attached to the Digital System Interconnect to implement full
featured device connectivity. The DSI allows any digital function
to any pin or other feature routability when used with the
Universal Digital Block Array.
Figure 7-1. CY8C32 Digital Programmable Architecture
The flexibility of the CY8C32 family’s Universal Digital Blocks
(UDBs) and Analog Blocks allow the user to create a wide range
of components (peripherals). The most common peripherals
were built and characterized by Cypress and are shown in the
PSoC Creator component catalog, however, users may also
create their own custom components using PSoC Creator. Using
PSoC Creator, users may also create their own components for
reuse within their organization, for example sensor interfaces,
proprietary algorithms, and display interfaces.
The number of components available through PSoC Creator is
too numerous to list in the datasheet, and the list is always
growing. An example of a component available for use in
CY8C32 family, but, not explicitly called out in this datasheet is
the UART component.
7.1.1 Example Digital Components
The following is a sample of the digital components available in
PSoC Creator for the CY8C32 family. The exact amount of
hardware resources (UDBs, routing, RAM, flash) used by a
component varies with the features selected in PSoC Creator for
the component.
Communications
2
I C
UART
SPI
Functions
EMIF
PWMs
Timers
Counters
Logic
NOT
OR
XOR
AND
7.1.2 Example Analog Components
DSI Routing Interface
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
Current
Voltage
PWM
Comparators
7.1.3 Example System Function Components
I/O Port
Digital Core System
and Fixed Function Peripherals
Delta-sigma
DACs
DSI Routing Interface
Document Number: 001-56955 Rev. *Y
The following is a sample of the analog components available in
PSoC Creator for the CY8C32 family. The exact amount of
hardware resources (routing, RAM, flash) used by a component
varies with the features selected in PSoC Creator for the
component.
ADC
UDB Array
UDB Array
I/O Port
I/O Port
I/O Port
Digital Core System
and Fixed Function Peripherals
The following is a sample of the system function components
available in PSoC Creator for the CY8C32 family. The exact
amount of hardware resources (UDBs, routing, RAM, flash) used
by a component varies with the features selected in PSoC
Creator for the component.
CapSense
LCD Drive
LCD Control
Page 45 of 128
PSoC® 3: CY8C32 Family Data Sheet
7.1.4 Designing with PSoC Creator
7.1.4.1 More Than a Typical IDE
A successful design tool allows for the rapid development and
deployment of both simple and complex designs. It reduces or
eliminates any learning curve. It makes the integration of a new
design into the production stream straightforward.
PSoC Creator is that design tool.
PSoC Creator is a full featured Integrated Development
Environment (IDE) for hardware and software design. It is
optimized specifically for PSoC devices and combines a modern,
powerful software development platform with a sophisticated
graphical design tool. This unique combination of tools makes
PSoC Creator the most flexible embedded design platform
available.
Graphical design entry simplifies the task of configuring a
particular part. You can select the required functionality from an
extensive catalog of components and place it in your design. All
components are parameterized and have an editor dialog that
allows you to tailor functionality to your needs.
PSoC Creator automatically configures clocks and routes the I/O
to the selected pins and then generates APIs to give the
application complete control over the hardware. Changing the
PSoC device configuration is as simple as adding a new
component, setting its parameters, and rebuilding the project.
At any stage of development you are free to change the
hardware configuration and even the target processor. To
retarget your application (hardware and software) to new
devices, even from 8- to 32-bit families, just select the new
device and rebuild.
You also have the ability to change the C compiler and evaluate
an alternative. Components are designed for portability and are
validated against all devices, from all families, and against all
supported tool chains. Switching compilers is as easy as editing
the from the project options and rebuilding the application with
no errors from the generated APIs or boot code.
7.1.4.2 Component Catalog
The component catalog is a repository of reusable design
elements that select device functionality and customize your
PSoC device. It is populated with an impressive selection of
content; from simple primitives such as logic gates and device
registers, through the digital timers, counters and PWMs, plus
Document Number: 001-56955 Rev. *Y
analog components such as ADC and DAC, and communication
protocols, such as I2C, and USB. See Example Peripherals on
page 45 for more details about available peripherals. All content
is fully characterized and carefully documented in datasheets
with code examples, AC/DC specifications, and user code ready
APIs.
7.1.4.3 Design Reuse
The symbol editor gives you the ability to develop reusable
components that can significantly reduce future design time. Just
draw a symbol and associate that symbol with your proven
design. PSoC Creator allows for the placement of the new
symbol anywhere in the component catalog along with the
content provided by Cypress. You can then reuse your content
as many times as you want, and in any number of projects,
without ever having to revisit the details of the implementation.
7.1.4.4 Software Development
Anchoring the tool is a modern, highly customizable user
interface. It includes project management and integrated editors
for C and assembler source code, as well the design entry tools.
Project build control leverages compiler technology from top
commercial vendors such as ARM® Limited, Keil™, and
CodeSourcery (GNU). Free versions of Keil C51 and GNU C
Compiler (GCC) for ARM, with no restrictions on code size or end
product distribution, are included with the tool distribution.
Upgrading to more optimizing compilers is a snap with support
for the professional Keil C51 product and ARM RealView™
compiler.
7.1.4.5 Nonintrusive Debugging
With JTAG (4-wire) and SWD (2-wire) debug connectivity
available on all devices, the PSoC Creator debugger offers full
control over the target device with minimum intrusion.
Breakpoints and code execution commands are all readily
available from toolbar buttons and an impressive lineup of
windows—register, locals, watch, call stack, memory and
peripherals—make for an unparalleled level of visibility into the
system.
PSoC Creator contains all the tools necessary to complete a
design, and then to maintain and extend that design for years to
come. All steps of the design flow are carefully integrated and
optimized for ease-of-use and to maximize productivity.
Page 46 of 128
PSoC® 3: CY8C32 Family Data Sheet
Status and Control Module – The primary role of this block is
7.2 Universal Digital Block
The Universal Digital Block (UDB) represents an evolutionary
step to the next generation of PSoC embedded digital peripheral
functionality. The architecture in first generation PSoC digital
blocks provides coarse programmability in which a few fixed
functions with a small number of options are available. The new
UDB architecture is the optimal balance between configuration
granularity and efficient implementation. A cornerstone of this
approach is to provide the ability to customize the devices digital
operation to match application requirements.
The primary purpose of the PLD blocks is to implement logic
expressions, state machines, sequencers, lookup tables, and
decoders. In the simplest use model, consider the PLD blocks as
a standalone resource onto which general purpose RTL is
synthesized and mapped. The more common and efficient use
model is to create digital functions from a combination of PLD
and datapath blocks, where the PLD implements only the
random logic and state portion of the function while the datapath
(ALU) implements the more structured elements.
Figure 7-3. PLD 12C4 Structure
PT3
PT4
PT5
PT6
PT7
Clock
and Reset
Control
PLD
12C4
(8 PTs)
PLD
12C4
(8 PTs)
7.2.1 PLD Module
PT2
PLD
Chaining
and reset selection and control.
PT1
Figure 7-2. UDB Block Diagram
Clock and Reset Module – This block provides the UDB clocks
PT0
To achieve this, UDBs consist of a combination of uncommitted
logic (PLD), structured logic (Datapath), and a flexible routing
scheme to provide interconnect between these elements, I/O
connections, and other peripherals. UDB functionality ranges
from simple self contained functions that are implemented in one
UDB, or even a portion of a UDB (unused resources are
available for other functions), to more complex functions that
require multiple UDBs. Examples of basic functions are timers,
counters, CRC generators, PWMs, dead band generators, and
communications functions, such as UARTs, SPI, and I2C. Also,
the PLD blocks and connectivity provide full featured general
purpose programmable logic within the limits of the available
resources.
to provide a way for CPU firmware to interact and synchronize
with UDB operation.
IN0
TC
TC
TC
TC
TC
TC
TC
TC
IN1
TC
TC
TC
TC
TC
TC
TC
TC
IN2
TC
TC
TC
TC
TC
TC
TC
TC
IN3
TC
TC
TC
TC
TC
TC
TC
TC
IN4
TC
TC
TC
TC
TC
TC
TC
TC
IN5
TC
TC
TC
TC
TC
TC
TC
TC
IN6
TC
TC
TC
TC
TC
TC
TC
TC
IN7
TC
TC
TC
TC
TC
TC
TC
TC
IN8
TC
TC
TC
TC
TC
TC
TC
TC
IN9
TC
TC
TC
TC
TC
TC
TC
TC
IN10
TC
TC
TC
TC
TC
TC
TC
TC
IN11
TC
TC
TC
TC
TC
TC
TC
TC
AND
Array
Carry In
Status and
Control
Datapath
Datapath
Chaining
Routing Channel
The main component blocks of the UDB are:
PLD blocks – There are two small PLDs per UDB. These blocks
take inputs from the routing array and form registered or
combinational sum-of-products logic. PLDs are used to
implement state machines, state bits, and combinational logic
equations. PLD configuration is automatically generated from
graphical primitives.
Datapath Module – This 8-bit wide datapath contains structured
logic to implement a dynamically configurable ALU, a variety
of compare configurations and condition generation. This block
also contains input/output FIFOs, which are the primary parallel
data interface between the CPU/DMA system and the UDB.
Document Number: 001-56955 Rev. *Y
T
T
T
T
T
T
T
T
MC0
OUT0
T
T
T
T
T
T
T
T
MC1
OUT1
T
T
T
T
T
T
T
T
MC2
OUT2
T
T
T
T
T
T
T
T
MC3
OUT3
OR
Array
Carry Out
One 12C4 PLD block is shown in Figure 7-3. This PLD has 12
inputs, which feed across eight product terms. Each product term
(AND function) can be from 1 to 12 inputs wide, and in a given
product term, the true (T) or complement (C) of each input can
be selected. The product terms are summed (OR function) to
create the PLD outputs. A sum can be from 1 to 8 product terms
wide. The 'C' in 12C4 indicates that the width of the OR gate (in
this case 8) is constant across all outputs (rather than variable
as in a 22V10 device). This PLA like structure gives maximum
flexibility and insures that all inputs and outputs are permutable
for ease of allocation by the software tools. There are two 12C4
PLDs in each UDB.
Page 47 of 128
PSoC® 3: CY8C32 Family Data Sheet
7.2.2 Datapath Module
The datapath contains an 8-bit single cycle ALU, with associated compare and condition generation logic. This datapath block is
optimized to implement embedded functions, such as timers, counters, integrators, PWMs, PRS, CRC, shifters and dead band
generators and many others.
Figure 7-4. Datapath Top Level
PHUB System Bus
R/W Access to All
Registers
6
F0
D1
Data Registers
A0
A1
D0
D1
D0
To/From
Previous
Datapath
A1
Conditions: 2 Compares,
2 Zero Detect, 2 Ones
Detect Overflow Detect
Input
Muxes
Datapath Control
Input from
Programmable
Routing
Dynamic Configuration RAM
8 Word X 16 Bit
F1
FIFOs
Chaining
Output
Muxes
6
Output to
Programmable
Routing
To/From
Next
Datapath
Accumulators
A0
PI
Parallel Input/Output
(To/From Programmable Routing)
PO
ALU
Shift
Mask
7.2.2.1 Working Registers
The datapath contains six primary working registers, which are
accessed by CPU firmware or DMA during normal operation.
Table 7-1. Working Datapath Registers
Name
Function
Description
A0 and A1 Accumulators
These are sources and sinks for
the ALU and also sources for the
compares.
D0 and D1 Data Registers
These are sources for the ALU
and sources for the compares.
F0 and F1 FIFOs
These are the primary interface
to the system bus. They can be a
data source for the data registers
and accumulators or they can
capture data from the accumulators or ALU. Each FIFO is four
bytes deep.
Document Number: 001-56955 Rev. *Y
7.2.2.2 Dynamic Configuration RAM
Dynamic configuration is the ability to change the datapath
function and internal configuration on a cycle-by-cycle basis,
under sequencer control. This is implemented using the
8-word × 16-bit configuration RAM, which stores eight unique
16-bit wide configurations. The address input to this RAM
controls the sequence, and can be routed from any block
connected to the UDB routing matrix, most typically PLD logic,
I/O pins, or from the outputs of this or other datapath blocks.
ALU
The ALU performs eight general purpose functions. They are:
Increment
Decrement
Add
Subtract
Logical AND
Logical OR
Logical XOR
Pass, used to pass a value through the ALU to the shift register,
mask, or another UDB register
Page 48 of 128
PSoC® 3: CY8C32 Family Data Sheet
Independent of the ALU operation, these functions are available:
7.2.2.7 Chaining
Shift left
Shift right
The datapath can be configured to chain conditions and signals
such as carries and shift data with neighboring datapaths to
create higher precision arithmetic, shift, CRC/PRS functions.
Nibble swap
7.2.2.8 Time Multiplexing
Bitwise OR mask
In applications that are over sampled, or do not need high clock
rates, the single ALU block in the datapath can be efficiently
shared with two sets of registers and condition generators. Carry
and shift out data from the ALU are registered and can be
selected as inputs in subsequent cycles. This provides support
for 16-bit functions in one (8-bit) datapath.
7.2.2.3 Conditionals
Each datapath has two compares, with bit masking options.
Compare operands include the two accumulators and the two
data registers in a variety of configurations. Other conditions
include zero detect, all ones detect, and overflow. These
conditions are the primary datapath outputs, a selection of which
can be driven out to the UDB routing matrix. Conditional
computation can use the built in chaining to neighboring UDBs
to operate on wider data widths without the need to use routing
resources.
7.2.2.4 Variable MSB
The most significant bit of an arithmetic and shift function can be
programmatically specified. This supports variable width CRC
and PRS functions, and in conjunction with ALU output masking,
can implement arbitrary width timers, counters and shift blocks.
7.2.2.5 Built in CRC/PRS
The datapath has built in support for single cycle Cyclic
Redundancy Check (CRC) computation and Pseudo Random
Sequence (PRS) generation of arbitrary width and arbitrary
polynomial. CRC/PRS functions longer than 8 bits may be
implemented in conjunction with PLD logic, or built in chaining
may be use to extend the function into neighboring UDBs.
Each datapath contains two four-byte deep FIFOs, which can be
independently configured as an input buffer (system bus writes
to the FIFO, datapath internal reads the FIFO), or an output
buffer (datapath internal writes to the FIFO, the system bus reads
from the FIFO). The FIFOs generate status that are selectable
as datapath outputs and can therefore be driven to the routing,
to interact with sequencers, interrupts, or DMA.
Figure 7-5. Example FIFO Configurations
System Bus
D0/D1
A0/A1/ALU
System Bus
F1
A0/A1/ALU
A0/A1/ALU
F0
F0
F1
D0
A0
D1
A1
F1
System Bus
System Bus
TX/RX
Dual Capture
There are six inputs and six outputs that connect the datapath to
the routing matrix. Inputs from the routing provide the
configuration for the datapath operation to perform in each cycle,
and the serial data inputs. Inputs can be routed from other UDB
blocks, other device peripherals, device I/O pins, and so on. The
outputs to the routing can be selected from the generated
conditions, and the serial data outputs. Outputs can be routed to
other UDB blocks, device peripherals, interrupt and DMA
controller, I/O pins, and so on.
7.2.3 Status and Control Module
The primary purpose of this circuitry is to coordinate CPU
firmware interaction with internal UDB operation.
Figure 7-6. Status and Control Registers
System Bus
8-bit Status Register
(Read Only)
7.2.2.6 Input/Output FIFOs
F0
7.2.2.9 Datapath I/O
Document Number: 001-56955 Rev. *Y
Dual Buffer
8-bit Control Register
(Write/Read)
Routing Channel
The bits of the control register, which may be written to by the
system bus, are used to drive into the routing matrix, and thus
provide firmware with the opportunity to control the state of UDB
processing. The status register is read-only and it allows internal
UDB state to be read out onto the system bus directly from
internal routing. This allows firmware to monitor the state of UDB
processing. Each bit of these registers has programmable
connections to the routing matrix and routing connections are
made depending on the requirements of the application.
7.2.3.1 Usage Examples
As an example of control input, a bit in the control register can
be allocated as a function enable bit. There are multiple ways to
enable a function. In one method the control bit output would be
routed to the clock control block in one or more UDBs and serve
as a clock enable for the selected UDB blocks. A status example
is a case where a PLD or datapath block generated a condition,
such as a “compare true” condition that is captured and latched
by the status register and then read (and cleared) by CPU
firmware.
Page 49 of 128
PSoC® 3: CY8C32 Family Data Sheet
Each subcomponent block of a UDB including the two PLDs, the
datapath, and Status and Control, has a clock selection and
control block. This promotes a fine granularity with respect to
allocating clocking resources to UDB component blocks and
allows unused UDB resources to be used by other functions for
maximum system efficiency.
7.3 UDB Array Description
Figure 7-7 shows an example of a 16 UDB array. In addition to
the array core, there are a DSI routing interfaces at the top and
bottom of the array. Other interfaces that are not explicitly shown
include the system interfaces for bus and clock distribution. The
UDB array includes multiple horizontal and vertical routing
channels each comprised of 96 wires. The wire connections to
UDBs, at horizontal/vertical intersection and at the DSI interface
are highly permutable providing efficient automatic routing in
PSoC Creator. Additionally the routing allows wire by wire
segmentation along the vertical and horizontal routing to further
increase routing flexibility and capability.
8-Bit
Timer
Quadrature Decoder
UDB
UDB
HV
A
UDB
UDB
HV
A
HV
B
UDB
8-Bit
Timer Logic
UDB
12-Bit SPI
UDB
HV
B
16-Bit PYRS
HV
A
UDB
UDB
16-Bit
PWM
HV
B
I2C Slave
System Connections
HV
A
Figure 7-8. Function Mapping Example in a Bank of UDBs
8-Bit SPI
Figure 7-7. Digital System Interface Structure
HV
B
An example of this is the 8-bit Timer in the upper left corner of
the array. This function only requires one datapath in the UDB,
and therefore the PLD resources may be allocated to another
function. A function such as a Quadrature Decoder may require
more PLD logic than one UDB can supply and in this case can
utilize the unused PLD blocks in the 8-bit Timer UDB.
Programmable resources in the UDB array are generally
homogeneous so functions can be mapped to arbitrary
boundaries in the array.
Sequencer
7.2.3.2 Clock Generation
UDB
HV
B
UDB
HV
A
UDB
HV
B
HV
A
Logic
UDB
UDB
UDB
UDB
UDB
HV
A
HV
B
HV
A
HV
B
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
HV
B
UDB
HV
A
UDB
HV
A
HV
B
UDB
HV
B
UART
UDB
UDB
12-Bit PWM
7.4 DSI Routing Interface Description
HV
A
UDB
HV
A
UDB
HV
B
System Connections
The DSI routing interface is a continuation of the horizontal and
vertical routing channels at the top and bottom of the UDB array
core. It provides general purpose programmable routing
between device peripherals, including UDBs, I/Os, analog
peripherals, interrupts, DMA and fixed function peripherals.
Figure 7-9 illustrates the concept of the digital system
interconnect, which connects the UDB array routing matrix with
other device peripherals. Any digital core or fixed function
peripheral that needs programmable routing is connected to this
interface.
Signals in this category include:
Interrupt requests from all digital peripherals in the system.
7.3.1 UDB Array Programmable Resources
Figure 7-8 shows an example of how functions are mapped into
a bank of 16 UDBs. The primary programmable resources of the
UDB are two PLDs, one datapath and one status/control register.
These resources are allocated independently, because they
have independently selectable clocks, and therefore unused
blocks are allocated to other unrelated functions.
DMA requests from all digital peripherals in the system.
Digital peripheral data signals that need flexible routing to I/Os.
Digital peripheral data signals that need connections to UDBs.
Connections to the interrupt and DMA controllers.
Connection to I/O pins.
Connection to analog system digital signals.
Document Number: 001-56955 Rev. *Y
Page 50 of 128
PSoC® 3: CY8C32 Family Data Sheet
Figure 7-9. Digital System Interconnect
Tim ers
C ounters
Interrupt
C ontroller
I2C
DMA
C ontroller
IO Port
Pins
G lobal
C locks
conjunction with drive strength control, this can implement a
bidirectional I/O pin. A data output signal has the option to be
single synchronized (pipelined) and a data input signal has the
option to be double synchronized. The synchronization clock is
the master clock (see Figure 6-1). Normally all inputs from pins
are synchronized as this is required if the CPU interacts with the
signal or any signal derived from it. Asynchronous inputs have
rare uses. An example of this is a feed through of combinational
PLD logic from input pins to output pins.
Figure 7-11. I/O Pin Synchronization Routing
D igital System R outing I/F
DO
UDB ARRAY
DI
D igital System R outing I/F
Figure 7-12. I/O Pin Output Connectivity
8 IO Data Output Connections from the
UDB Array Digital System Interface
G lobal
C locks
I/O Port
Pins
EM IF
D el-Sig
D AC
C om parators
Interrupt and DMA routing is very flexible in the CY8C32
programmable architecture. In addition to the numerous fixed
function peripherals that can generate interrupt requests, any
data signal in the UDB array routing can also be used to generate
a request. A single peripheral may generate multiple
independent interrupt requests simplifying system and firmware
design. Figure 7-10 shows the structure of the IDMUX
(Interrupt/DMA Multiplexer).
DO
PIN 0
DO
PIN1
DO
PIN2
Fixed Function IRQs
0
1
IRQs
UDB Array
2
Edge
Detect
Interrupt
Controller
DO
PIN4
DO
PIN5
DO
PIN6
DO
PIN7
Port i
Figure 7-10. Interrupt and DMA Processing in the IDMUX
Interrupt and DMA Processing in IDMUX
DO
PIN3
There are four more DSI connections to a given I/O port to
implement dynamic output enable control of pins. This
connectivity gives a range of options, from fully ganged 8-bits
controlled by one signal, to up to four individually controlled pins.
The output enable signal is useful for creating tri-state
bidirectional pins and buses.
Figure 7-13. I/O Pin Output Enable Connectivity
3
DRQs
DMA termout (IRQs)
4 IO Control Signal Connections from
UDB Array Digital System Interface
0
Fixed Function DRQs
1
Edge
Detect
DMA
Controller
2
7.4.1 I/O Port Routing
There are a total of 20 DSI routes to a typical 8-bit I/O port, 16
for data and four for drive strength control.
When an I/O pin is connected to the routing, there are two
primary connections available, an input and an output. In
Document Number: 001-56955 Rev. *Y
OE
PIN 0
OE
PIN1
OE
PIN2
OE
PIN3
OE
PIN4
OE
PIN5
OE
PIN6
OE
PIN7
Port i
Page 51 of 128
PSoC® 3: CY8C32 Family Data Sheet
7.5 USB
7.6 Timers, Counters, and PWMs
PSoC includes a dedicated Full-Speed (12 Mbps) USB 2.0
transceiver supporting all four USB transfer types: control,
interrupt, bulk, and isochronous. PSoC Creator provides full
configuration support. USB interfaces to hosts through two
dedicated USBIO pins, which are detailed in the “I/O System and
Routing” section on page 37.
The Timer/Counter/PWM peripheral is a 16-bit dedicated
peripheral providing three of the most common embedded
peripheral features. As almost all embedded systems use some
combination of timers, counters, and PWMs. Four of them have
been included on this PSoC device family. Additional and more
advanced functionality timers, counters, and PWMs can also be
instantiated in Universal Digital Blocks (UDBs) as required.
PSoC Creator allows you to choose the timer, counter, and PWM
features that they require. The tool set utilizes the most optimal
resources available.
USB includes the following features:
Eight unidirectional data endpoints
One bidirectional control endpoint 0 (EP0)
Shared 512-byte buffer for the eight data endpoints
Dedicated 8-byte buffer for EP0
Three memory modes
Manual Memory Management with No DMA Access
Manual Memory Management with Manual DMA Access
Automatic Memory Management with Automatic DMA
Access
Internal 3.3 V regulator for transceiver
Internal 48 MHz main oscillator mode that auto locks to USB
bus clock, requiring no external crystal for USB (USB equipped
parts only)
The Timer/Counter/PWM peripheral can select from multiple
clock sources, with input and output signals connected through
the DSI routing. DSI routing allows input and output connections
to any device pin and any internal digital signal accessible
through the DSI. Each of the four instances has a compare
output, terminal count output (optional complementary compare
output), and programmable interrupt request line. The
Timer/Counter/PWMs are configurable as free running, one shot,
or Enable input controlled. The peripheral has timer reset and
capture inputs, and a kill input for control of the comparator
outputs. The peripheral supports full 16-bit capture.
Timer/Counter/PWM features include:
16-bit Timer/Counter/PWM (down count only)
Interrupts on bus and each endpoint event, with device wakeup
Selectable clock source
USB Reset, Suspend, and Resume operations
PWM comparator (configurable for LT, LTE, EQ, GTE, GT)
Bus powered and self powered modes
Period reload on start, reset, and terminal count
Figure 7-14. USB
Interrupt on terminal count, compare true, or capture
Dynamic counter reads
System Bus
Arbiter
SIE
(Serial Interface
Engine)
Interrupts
512 X 8
SRAM
Timer capture mode
External 22
D+
Resistors
Count while enable signal is asserted mode
Free run mode
USB
I/O
D–
48 MHz
IMO
One Shot mode (stop at end of period)
Complementary PWM outputs with deadband
PWM output kill
Figure 7-15. Timer/Counter/PWM
Clock
Reset
Enable
Capture
Kill
Document Number: 001-56955 Rev. *Y
Timer / Counter /
PWM 16-bit
IRQ
TC / Compare!
Compare
Page 52 of 128
PSoC® 3: CY8C32 Family Data Sheet
7.7 I2C
I2C features include:
PSoC includes a single fixed-function I2C peripheral. Additional
I2C interfaces can be instantiated using Universal Digital Blocks
(UDBs) in PSoC Creator, as required.
Slave and Master, Transmitter, and Receiver operation
The I2C peripheral provides a synchronous two-wire interface
designed to interface the PSoC device with a two-wire I2C serial
communication bus. It is compatible[13] with I2C Standard-mode,
Fast-mode, and Fast-mode Plus devices as defined in the NXP
I2C-bus specification and user manual (UM10204). The I2C bus
I/O may be implemented with GPIO or SIO in open-drain modes.
Interrupt or polling CPU interface
To eliminate the need for excessive CPU intervention and
overhead, I2C specific support is provided for status detection
and generation of framing bits. I2C operates as a slave, a master,
or multimaster (Slave and Master)[14]. In slave mode, the unit
always listens for a start condition to begin sending or receiving
data. Master mode supplies the ability to generate the Start and
Stop conditions and initiate transactions. Multimaster mode
provides clock synchronization and arbitration to allow multiple
masters on the same bus. If Master mode is enabled and Slave
mode is not enabled, the block does not generate interrupts on
externally generated Start conditions. I2C interfaces through the
DSI routing and allows direct connections to any GPIO or SIO
pins.
Byte processing for low CPU overhead
Support for bus speeds up to 1 Mbps
7 or 10-bit addressing (10-bit addressing requires firmware
support)
SMBus operation (through firmware support – SMBus
supported in hardware in UDBs)
7-bit hardware address compare
Wake from low-power modes on address match
Glitch filtering (active and alternate-active modes only)
Data transfers follow the format shown in Figure 7-16. After the
START condition (S), a slave address is sent. This address is 7
bits long followed by an eighth bit which is a data direction bit
(R/W) - a 'zero' indicates a transmission (WRITE), a 'one'
indicates a request for data (READ). A data transfer is always
terminated by a STOP condition (P) generated by the master.
I2C provides hardware address detect of a 7-bit address without
CPU intervention. Additionally the device can wake from
low-power modes on a 7-bit hardware address match. If wakeup
functionality is required, I2C pin connections are limited to one
of two specific pairs of SIO pins. See descriptions of SCL and
SDA pins in Pin Descriptions on page 12.
Figure 7-16. I2C Complete Transfer Timing
SDA
1-7
SCL
START
Condition
ADDRESS
8
9
R/W
ACK
1-7
8
DATA
7.7.1 External Electrical Connections
As Figure 7-17 shows, the I2C bus requires external pull-up
resistors (RP). These resistors are primarily determined by the
supply voltage, bus speed, and bus capacitance. For detailed
9
ACK
1-7
8
DATA
9
ACK
STOP
Condition
information on how to calculate the optimum pull-up resistor
value for your design, we recommend using the UM10204
I2C-bus specification and user manual Rev 6, or newer, available
from the NXP website at www.nxp.com.
Notes
13. The I2C peripheral is non-compliant with the NXP I2C specification in the following areas: analog glitch filter, I/O VOL/IOL, I/O hysteresis. The I2C Block has a digital
glitch filter (not available in sleep mode). The Fast-mode minimum fall-time specification can be met by setting the I/Os to slow speed mode. See the I/O Electrical
Specifications in “Inputs and Outputs” section on page 76 for details.
14. Fixed-block I2C does not support undefined bus conditions, nor does it support Repeated Start in Slave mode. These conditions should be avoided, or the UDB-based
I2C component should be used instead.
Document Number: 001-56955 Rev. *Y
Page 53 of 128
PSoC® 3: CY8C32 Family Data Sheet
Figure 7-17. Connection of Devices to the I2C Bus
Equation 3:
R PMAX = V DD min – V IH min + V NH min I IH max
Equation parameters:
VDD = Nominal supply voltage for I2C bus
VOL = Maximum output low voltage of bus devices.
IOL= Low-level output current from I2C specification
TR = Rise Time of bus from I2C specification
CB = Capacitance of each bus line including pins and PCB traces
For most designs, the default values in Table 7-2 will provide
excellent performance without any calculations. The default
values were chosen to use standard resistor values between the
minimum and maximum limits. The values in Table 7-2 work for
designs with 1.8 V to 5.0V VDD, less than 200-pF bus capacitance (CB), up to 25 µA of total input leakage (IIL), up to 0.4 V
output voltage level (VOL), and a max VIH of 0.7 * VDD. Standard
Mode and Fast Mode can use either GPIO or SIO PSoC pins.
Fast Mode Plus requires use of SIO pins to meet the VOL spec
at 20 mA. Calculation of custom pull-up resistor values is
required; if your design does not meet the default assumptions,
you use series resistors (RS) to limit injected noise, or you need
to maximize the resistor value for low power consumption.
Table 7-2. Recommended default Pull-up Resistor Values
RP
Units
Standard Mode – 100 kbps
4.7 k, 5%
Ω
Fast Mode – 400 kbps
1.74 k, 1%
Ω
620, 5%
Ω
Fast Mode Plus – 1 Mbps
Calculation of the ideal pull-up resistor value involves finding a
value between the limits set by three equations detailed in the
NXP I2C specification. These equations are:
Equation 1:
R PMIN = V DD max – V OL max I OL min
VIH = Minimum high-level input voltage of all bus devices
VNH = Minimum high-level input noise margin from I2C specification
IIH = Total input leakage current of all devices on the bus
The supply voltage (VDD) limits the minimum pull-up resistor
value due to bus devices maximum low output voltage (VOL)
specifications. Lower pull-up resistance increases current
through the pins and can, therefore, exceed the spec conditions
of VOL. Equation 1 is derived using Ohm's law to determine the
minimum resistance that will still meet the VOL specification at
3 mA for standard and fast modes, and 20 mA for fast mode plus
at the given VDD.
Equation 2 determines the maximum pull-up resistance due to
bus capacitance. Total bus capacitance is comprised of all pin,
wire, and trace capacitance on the bus. The higher the bus
capacitance, the lower the pull-up resistance required to meet
the specified bus speeds rise time due to RC delays. Choosing
a pull-up resistance higher than allowed can result in failing
timing requirements resulting in communication errors. Most
designs with five or less I2C devices and up to 20 centimeters of
bus trace length have less than 100 pF of bus capacitance.
A secondary effect that limits the maximum pull-up resistor value
is total bus leakage calculated in Equation 3. The primary source
of leakage is I/O pins connected to the bus. If leakage is too high,
the pull-ups will have difficulty maintaining an acceptable VIH
level causing communication errors. Most designs with five or
less I2C devices on the bus have less than 10 µA of total leakage
current.
Equation 2:
R PMAX = T R max 0.8473 C B max
Document Number: 001-56955 Rev. *Y
Page 54 of 128
PSoC® 3: CY8C32 Family Data Sheet
High resolution delta-sigma ADC.
8. Analog Subsystem
The analog programmable system creates application specific
combinations of both standard and advanced analog signal
processing blocks. These blocks are then interconnected to
each other and also to any pin on the device, providing a high
level of design flexibility and IP security. The features of the
analog subsystem are outlined here to provide an overview of
capabilities and architecture.
One 8-bit DAC that provides either voltage or current output.
Two comparators with optional connection to configurable LUT
outputs.
CapSense subsystem to enable capacitive touch sensing.
Precision reference for generating an accurate analog voltage
for internal analog blocks.
Flexible, configurable analog routing architecture provided by
analog globals, analog mux bus, and analog local buses.
A
N
A
L
O
G
GPIO
Port
DelSig
ADC
Figure 8-1. Analog Subsystem Block Diagram
A
N
A
L
O
G
Precision
Reference
DAC
Comparators
R
O
U
T
I
N
G
CMP
R
O
U
T
I
N
G
CMP
CapSense Subsystem
Analog
Interface
DSI
Array
Clock
Distribution
Config &
Status
Registers
PHUB
GPIO
Port
CPU
Decimator
The PSoC Creator software program provides a user friendly interface to configure the analog connections between the GPIO and
various analog resources and connections from one analog resource to another. PSoC Creator also provides component libraries that
allow you to configure the various analog blocks to perform application specific functions. The tool also generates API interface
libraries that allow you to write firmware that allows the communication between the analog peripheral and CPU/Memory.
Document Number: 001-56955 Rev. *Y
Page 55 of 128
PSoC® 3: CY8C32 Family Data Sheet
8.1 Analog Routing
The CY8C32 family of devices has a flexible analog routing
architecture that provides the capability to connect GPIOs and
different analog blocks, and also route signals between different
analog blocks. One of the strong points of this flexible routing
architecture is that it allows dynamic routing of input and output
connections to the different analog blocks.
For information on how to make pin selections for optimal analog
routing, refer to the application note, AN58304 - PSoC® 3 and
PSoC® 5 - Pin Selection for Analog Designs.
8.1.1 Features
Flexible, configurable analog routing architecture
16 analog globals (AG) and two analog mux buses
(AMUXBUS) to connect GPIOs and the analog blocks
Each GPIO is connected to one analog global and one analog
Eight analog local buses (abus) to route signals between the
different analog blocks
Multiplexers and switches for input and output selection of the
analog blocks
8.1.2 Functional Description
Analog globals (AGs) and analog mux buses (AMUXBUS)
provide analog connectivity between GPIOs and the various
analog blocks. There are 16 AGs in the CY8C32 family. The
analog routing architecture is divided into four quadrants as
shown in Figure 8-2. Each quadrant has four analog globals
(AGL[0..3], AGL[4..7], AGR[0..3], AGR[4..7]). Each GPIO is
connected to the corresponding AG through an analog switch.
The analog mux bus is a shared routing resource that connects
to every GPIO through an analog switch. There are two
AMUXBUS routes in CY8C32, one in the left half (AMUXBUSL)
and one in the right half (AMUXBUSR), as shown in Figure 8-2.
mux bus
Document Number: 001-56955 Rev. *Y
Page 56 of 128
PSoC® 3: CY8C32 Family Data Sheet
Figure 8-2. CY8C32 Analog Interconnect
Vssd
Vcca
*
*
*
*
*
*
*
swinn
*
swfol
swinn
*
*
i0
LPF
in0
swout
abuf_vref_int
(1.024V)
in1
out0
swin
swout
out1
abuf_vref_int
(1.024V)
swin
ExVrefR
comp1 +
cmp1_vref
refbufl_
cmp
cmp0_vref
(1.024V)
cmp1_vref
GPIO
P4[2]
GPIO
P4[3]
GPIO
P4[4]
GPIO
P4[5]
GPIO
P4[6]
GPIO
P4[7]
comp0
+
-
COMPARATOR
refbufr_
cmp
i2
*
cmp_muxvn[1:0]
vref_cmp1
(0.256V)
cmp1_vref
bg_vda_res_en
Vdda
bg_vda_swabusl0
refbufr
out
ref
in
refbuf_vref1 (1.024V)
refbuf_vref2 (1.2V)
refsel[1:0]
Vssa
vssa
* P15[7]
VIDAC
USB IO
* P15[6]
GPIO
P5[7]
GPIO
P5[6]
GPIO
P5[5]
GPIO
P5[4]
SIO
P12[7]
SIO
P12[6]
GPIO
*P1[7]
GPIO
*P1[6]
dac_vref (0.256V)
+
DSM0
-
vssa
DSM
vcm
refs
qtz_ref
vref_vss_ext
dsm0_qtz_vref2 (1.2V)
dsm0_qtz_vref1 (1.024V)
Vdda/3
Vdda/4
ExVrefL
01 23456 7 0123
3210 76543210
LPF
AGL[3]
AGL[2]
AMUXBUSL
*
Vbat
Vssd
Ind
Vssb
Vboost
*
*
*
Large ( ~200 Ohms)
*
Switch Resistance
Small ( ~870 Ohms )
GPIO
P5[0]
GPIO
P5[1]
GPIO
P5[2]
GPIO
P5[3]
GPIO
P1[0]
GPIO
P1[1]
GPIO
P1[2]
GPIO
P1[3]
GPIO
P1[4]
GPIO
P1[5]
GPIO
P2[5]
GPIO
P2[6]
GPIO
P2[7]
SIO
P12[4]
SIO
P12[5]
GPIO
P6[4]
GPIO
P6[5]
GPIO
P6[6]
GPIO
P6[7]
*
*
Connection
*
AGR[2]
AGR[1]
AGR[0]
AMUXBUSR
*
Mux Group
Switch Group
AGR[3]
XRES
*
AGL[1]
AGL[0]
AGR[0]
AMUXBUSR
VBE
Vss ref
Notes:
* Denotes pins on all packages
LCD signals are not shown.
Vddio1
TS
ADC
AMUXBUSR
ANALOG ANALOG
BUS
GLOBALS
AGR[3]
AGR[2]
AGR[1]
:
AGL[1]
AGL[2]
AGL[3]
AMUXBUSL
AGL[0]
ANALOG ANALOG
GLOBALS
BUS
*
AMUXBUSL
ExVrefR
*
vssd
dsm0_vcm_vref1 (0.8V)
dsm0_vcm_vref2 (0.7V)
*
*
Vddio2
USB IO
v0
DAC0
i0
vcmsel[1:0]
Vssd
Vddd
ABUSR0
ABUSR1
ABUSR2
ABUSR3
*
*
Vddd
GPIO
P6[0]
GPIO
P6[1]
GPIO
P6[2]
GPIO
P6[3]
GPIO
P15[4]
GPIO
P15[5]
GPIO
P2[0]
GPIO
P2[1]
GPIO
P2[2]
GPIO
P2[3] *
GPIO
P2[4] *
ABUSL0
ABUSL1
ABUSL2
ABUSL3
*
*
Vssd
Vccd
*
Vccd
AGR[4]
AMUXBUSR
refsel[1:0]
AGR[7]
AGR[6]
AGR[5]
CAPSENSE
out
ref
in refbufl
refbuf_vref1 (1.024V)
refbuf_vref2
refbuf_vref2 (1.2V)
(1.2V)
*
AGL[6]
AGL[7]
GPIO
P3[5]
GPIO
swinp P3[4]
GPIO
swinn P3[3]
GPIO
P3[2]
GPIO
P3[1]
GPIO
P3[0]
GPXT
*P15[1]
GPXT
*P15[0]
3210 76543210
*
AGL[4]
AGL[5]
ExVrefL2
*
*
AMUXBUSL
*
AGR[6]
AGR[7]
01 2 3 4 56 7 0123
swinp
GPIO
P0[4]
GPIO
P0[5]
GPIO
P0[6]
GPIO
P0[7]
*
AGR[4]
AGR[5]
AGL[6]
AGL[7]
ExVrefL
ExVrefL1
*
*
AMUXBUSR
AMUXBUSL
AGL[4]
AGL[5]
Vddio3
GPIO
P3[6]
GPIO
P3[7]
SIO
P12[0]
SIO
P12[1]
GPIO
P15[2]
GPIO
P15[3]
swinp
*
*
Vssa
Vdda
SIO
P12[2]
SIO
P12[3]
GPIO
P4[0]
GPIO
P4[1]
GPIO
P0[0]
GPIO
P0[1]
GPIO
P0[2]
GPIO
P0[3]
Vddio0
swinn
Rev #60
13-Feb-2012
To preserve detail of this figure, this figure is best viewed with a PDF display program or printed on a 11" × 17" paper.
Document Number: 001-56955 Rev. *Y
Page 57 of 128
PSoC® 3: CY8C32 Family Data Sheet
Analog local buses (abus) are routing resources located within
the analog subsystem and are used to route signals between
different analog blocks. There are eight abus routes in CY8C32,
four in the left half (abusl [0:3]) and four in the right half (abusr
[0:3]) as shown in Figure 8-2. Using the abus saves the analog
globals and analog mux buses from being used for
interconnecting the analog blocks.
Multiplexers and switches exist on the various buses to direct
signals into and out of the analog blocks. A multiplexer can have
only one connection on at a time, whereas a switch can have
multiple connections on simultaneously. In Figure 8-2,
multiplexers are indicated by grayed ovals and switches are
indicated by transparent ovals.
speed data stream is not useful for most applications without
some type of post processing, and so is passed to the decimator
through the Analog Interface block. The decimator converts the
high speed serial data stream into parallel ADC results. The
modulator/decimator frequency response is [(sin x)/x]4.
Figure 8-4. Delta-sigma ADC Block Diagram
Positive
Input Mux
(Analog Routing)
Input
Buffer
Negative
Input Mux
8.2 Delta-sigma ADC
Delta
Sigma
Modulator
Decimator
12 to 20 Bit
Result
EOC
SOC
The CY8C32 device contains one delta-sigma ADC. This ADC
offers differential input, high resolution and excellent linearity,
making it a good ADC choice for measurement applications. The
converter can be configured to output 12-bit resolution at data
rates of up to 192 ksps. At a fixed clock rate, resolution can be
traded for faster data rates as shown in Table 8-1 and Figure 8-3.
Resolution and sample rate are controlled by the Decimator.
Data is pipelined in the decimator; the output is a function of the
last four samples. When the input multiplexer is switched, the
output data is not valid until after the fourth sample after the
switch.
Table 8-1. Delta-sigma ADC Performance
8.2.2 Operational Modes
Bits
Maximum Sample Rate
(sps)
SINAD (dB)
12
192 k
66
8
384 k
43
Figure 8-3. Delta-sigma ADC Sample Rates, Range = ±1.024 V
The ADC can be configured by the user to operate in one of four
modes: Single Sample, Multi Sample, Continuous, or Multi
Sample (Turbo). All four modes are started by either a write to
the start bit in a control register or an assertion of the Start of
Conversion (SoC) signal. When the conversion is complete, a
status bit is set and the output signal End of Conversion (EoC)
asserts high and remains high until the value is read by either the
DMA controller or the CPU.
8.2.2.1 Single Sample
1,000,000
In Single Sample mode, the ADC performs one sample
conversion on a trigger. In this mode, the ADC stays in standby
state waiting for the SoC signal to be asserted. When SoC is
signaled the ADC performs four successive conversions. The
first three conversions prime the decimator. The ADC result is
valid and available after the fourth conversion, at which time the
EoC signal is generated. To detect the end of conversion, the
system may poll a control register for status or configure the
external EoC signal to generate an interrupt or invoke a DMA
request. When the transfer is done the ADC reenters the standby
state where it stays until another SoC event.
Sample rates, sps
100,000
10,000
8.2.2.2 Continuous
1,000
Continuous
Multi-Sample
Resolution, bits
100
7
8
9
10
11
12
13
Continuous sample mode is used to take multiple successive
samples of a single input signal. Multiplexing multiple inputs
should not be done with this mode. There is a latency of three
conversion times before the first conversion result is available.
This is the time required to prime the decimator. After the first
result, successive conversions are available at the selected
sample rate.
8.2.1 Functional Description
8.2.2.3 Multi Sample
The ADC connects and configures three basic components,
input buffer, delta-sigma modulator, and decimator. The basic
block diagram is shown in Figure 8-4. The signal from the input
muxes is delivered to the delta-sigma modulator either directly or
through the input buffer. The delta-sigma modulator performs the
actual analog to digital conversion. The modulator over-samples
the input and generates a serial data stream output. This high
Multi sample mode is similar to continuous mode except that the
ADC is reset between samples. This mode is useful when the
input is switched between multiple signals. The decimator is
re-primed between each sample so that previous samples do not
affect the current conversion. Upon completion of a sample, the
next sample is automatically initiated. The results can be
transferred using either firmware polling, interrupt, or DMA.
Document Number: 001-56955 Rev. *Y
Page 58 of 128
PSoC® 3: CY8C32 Family Data Sheet
More information on output formats is provided in the Technical
Reference Manual.
8.2.3 Start of Conversion Input
Input offset factory trimmed to less than 5 mV
Rail-to-rail common mode input range (VSSA to VDDA)
Speed and power can be traded off by using one of three
modes: fast, slow, or ultra low-power
The SoC signal is used to start an ADC conversion. A digital
clock or UDB output can be used to drive this input. It can be
used when the sampling period must be longer than the ADC
conversion time or when the ADC must be synchronized to other
hardware. This signal is optional and does not need to be
connected if ADC is running in a continuous mode.
Comparator outputs can be routed to lookup tables to perform
8.2.4 End of Conversion Output
8.3.1 Input and Output Interface
The EoC signal goes high at the end of each ADC conversion.
This signal may be used to trigger either an interrupt or DMA
request.
The positive and negative inputs to the comparators come from
the analog global buses, the analog mux line, the analog local
bus and precision reference through multiplexers. The output
from each comparator could be routed to any of the two input
LUTs. The output of that LUT is routed to the UDB Digital System
Interface.
8.3 Comparators
The CY8C32 family of devices contains two comparators in a
device. Comparators have these features:
simple logic functions and then can also be routed to digital
blocks
The positive input of the comparators may be optionally passed
through a low pass filter. Two filters are provided
Comparator inputs can be connections to GPIO or DAC output
Figure 8-5. Analog Comparator
From
Analog
Routing
ANAIF
+
comp0
_
+
comp1
4
4
LUT0
4
4
4
LUT1
4
LUT2
4
_
From
Analog
Routing
4
LUT3
UDBs
Document Number: 001-56955 Rev. *Y
Page 59 of 128
PSoC® 3: CY8C32 Family Data Sheet
8.3.2 LUT
Static, 1/2, 1/3, 1/4, 1/5 bias voltage levels
The CY8C32 family of devices contains four LUTs. The LUT is a
two input, one output lookup table that is driven by any one or
two of the comparators in the chip. The output of any LUT is
routed to the digital system interface of the UDB array. From the
digital system interface of the UDB array, these signals can be
connected to UDBs, DMA controller, I/O, or the interrupt
controller.
Internal bias voltage generation through internal resistor ladder
The LUT control word written to a register sets the logic function
on the output. The available LUT functions and the associated
control word is shown in Table 8-2.
Drives up to 736 total segments (16 backplane × 46 front plane)
Table 8-2. LUT Function vs. Program Word and Inputs
Control Word
0000b
0001b
0010b
0011b
0100b
0101b
0110b
0111b
1000b
1001b
1010b
1011b
1100b
1101b
1110b
1111b
Output (A and B are LUT inputs)
FALSE (‘0’)
A AND B
A AND (NOT B)
A
(NOT A) AND B
B
A XOR B
A OR B
A NOR B
A XNOR B
NOT B
A OR (NOT B)
NOT A
(NOT A) OR B
A NAND B
TRUE (‘1’)
8.4 LCD Direct Drive
The PSoC Liquid Crystal Display (LCD) driver system is a highly
configurable peripheral designed to allow PSoC to directly drive
a broad range of LCD glass. All voltages are generated on chip,
eliminating the need for external components. With a high
multiplex ratio of up to 1/16, the CY8C32 family LCD driver
system can drive a maximum of 736 segments. The PSoC LCD
driver module was also designed with the conservative power
budget of portable devices in mind, enabling different LCD drive
modes and power down modes to conserve power.
PSoC Creator provides an LCD segment drive component. The
component wizard provides easy and flexible configuration of
LCD resources. You can specify pins for segments and
commons along with other options. The software configures the
device to meet the required specifications. This is possible
because of the programmability inherent to PSoC devices.
Key features of the PSoC LCD segment system are:
LCD panel direct driving
Type A (standard) and Type B (low-power) waveform support
Wide operating voltage range support (2 V to 5 V) for LCD
panels
Document Number: 001-56955 Rev. *Y
Up to 62 total common and segment outputs
Up to 1/16 multiplex for a maximum of 16 backplane/common
outputs
Up to 62 front plane/segment outputs for direct drive
Up to 64 levels of software controlled contrast
Ability to move display data from memory buffer to LCD driver
through DMA (without CPU intervention)
Adjustable LCD refresh rate from 10 Hz to 150 Hz
Ability to invert LCD display for negative image
Three LCD driver drive modes, allowing power optimization
Figure 8-6. LCD System
LCD
DAC
Global
Clock
UDB
LCD Driver
Block
DMA
PIN
Display
RAM
PHUB
8.4.1 LCD Segment Pin Driver
Each GPIO pin contains an LCD driver circuit. The LCD driver
buffers the appropriate output of the LCD DAC to directly drive
the glass of the LCD. A register setting determines whether the
pin is a common or segment. The pin’s LCD driver then selects
one of the six bias voltages to drive the I/O pin, as appropriate
for the display data.
8.4.2 Display Data Flow
The LCD segment driver system reads display data and
generates the proper output voltages to the LCD glass to
produce the desired image. Display data resides in a memory
buffer in the system SRAM. Each time you need to change the
common and segment driver voltages, the next set of pixel data
moves from the memory buffer into the Port Data Registers via
DMA.
8.4.3 UDB and LCD Segment Control
A UDB is configured to generate the global LCD control signals
and clocking. This set of signals is routed to each LCD pin driver
through a set of dedicated LCD global routing channels. In
addition to generating the global LCD control signals, the UDB
also produces a DMA request to initiate the transfer of the next
frame of LCD data.
Page 60 of 128
PSoC® 3: CY8C32 Family Data Sheet
8.4.4 LCD DAC
8.7 DAC
The LCD DAC generates the contrast control and bias voltage
for the LCD system. The LCD DAC produces up to five LCD drive
voltages plus ground, based on the selected bias ratio. The bias
voltages are driven out to GPIO pins on a dedicated LCD bias
bus, as required.
The CY8C32 parts contain a Digital to Analog Converter (DAC).
The DAC is 8-bit and can be configured for either voltage or
current output. The DAC supports CapSense, power supply
regulation, and waveform generation. The DAC has the following
features:
8.5 CapSense
Adjustable voltage or current output in 255 steps
The CapSense system provides a versatile and efficient means
for measuring capacitance in applications such as touch sense
buttons, sliders, proximity detection, etc. The CapSense system
uses a configuration of system resources, including a few
hardware functions primarily targeted for CapSense. Specific
resource usage is detailed in each CapSense component in
PSoC Creator.
Programmable step size (range selection)
A capacitive sensing method using a delta-sigma modulator
(CSD) is used. It provides capacitance sensing using a switched
capacitor technique with a delta-sigma modulator to convert the
sensing current to a digital code.
Eight bits of calibration to correct ± 25 percent of gain error
Source and sink option for current output
High and low speed / power modes
8 Msps conversion rate for current output
1 Msps conversion rate for voltage output
Monotonic in nature
Data and strobe inputs can be provided by the CPU or DMA,
or routed directly from the DSI
8.6 Temp Sensor
Die temperature is used to establish programming parameters
for writing flash. Die temperature is measured using a dedicated
sensor based on a forward biased transistor. The temperature
sensor has its own auxiliary ADC.
Dedicated low-resistance output pin for high-current mode
Figure 8-7. DAC Block Diagram
I source Range
1x , 8x , 64x
Reference
Source
Scaler
Vout
R
Iout
3R
I sink Range
1x , 8x , 64x
8.7.1 Current DAC
8.7.2 Voltage DAC
The current DAC (IDAC) can be configured for the ranges 0 to
31.875 µA, 0 to 255 µA, and 0 to 2.04 mA. The IDAC can be
configured to source or sink current.
For the voltage DAC (VDAC), the current DAC output is routed
through resistors. The two ranges available for the VDAC are 0
to 1.02 V and 0 to 4.08 V. In voltage mode any load connected
to the output of a DAC should be purely capacitive (the output of
the VDAC is not buffered).
Document Number: 001-56955 Rev. *Y
Page 61 of 128
PSoC® 3: CY8C32 Family Data Sheet
9. Programming, Debug Interfaces,
Resources
PSoC devices include extensive support for programming,
testing, debugging, and tracing both hardware and firmware.
Three interfaces are available: JTAG, SWD, and SWV. JTAG and
SWD support all programming and debug features of the device.
JTAG also supports standard JTAG scan chains for board level
test and chaining multiple JTAG devices to a single JTAG
connection.
For more information on PSoC 3 Programming, refer to the
PSoC® 3 Device Programming Specifications.
Complete Debug on Chip (DoC) functionality enables full device
debugging in the final system using the standard production
device. It does not require special interfaces, debugging pods,
simulators, or emulators. Only the standard programming
connections are required to fully support debug.
The PSoC Creator IDE software provides fully integrated
programming and debug support for PSoC devices. The low cost
MiniProg3 programmer and debugger is designed to provide full
programming and debug support of PSoC devices in conjunction
with the PSoC Creator IDE. PSoC JTAG, SWD, and SWV
interfaces are fully compatible with industry standard third party
tools.
All DOC circuits are disabled by default and can only be enabled
in firmware. If not enabled, the only way to reenable them is to
erase the entire device, clear flash protection, and reprogram the
device with new firmware that enables DOC. Disabling DOC
features, robust flash protection, and hiding custom analog and
digital functionality inside the PSoC device provide a level of
security not possible with multichip application solutions.
Additionally, all device interfaces can be permanently disabled
(Device Security) for applications concerned about phishing
attacks due to a maliciously reprogrammed device. Permanently
Document Number: 001-56955 Rev. *Y
disabling interfaces is not recommended in most applications
because you cannot access the device later. Because all
programming, debug, and test interfaces are disabled when
Device Security is enabled, PSoCs with Device Security enabled
may not be returned for failure analysis.
Table 9-1. Debug Configurations
Debug and Trace Configuration
All debug and trace disabled
JTAG
SWD
SWV
SWD + SWV
GPIO Pins Used
0
4 or 5
2
1
3
9.1 JTAG Interface
The IEEE 1149.1 compliant JTAG interface exists on four or five
pins (the nTRST pin is optional). The JTAG interface is used for
programming the flash memory, debugging, I/O scan chains, and
JTAG device chaining.
PSoC 3 has certain timing requirements to be met for entering
programming mode through the JTAG interface. Due to these
timing requirements, not all standard JTAG programmers, or
standard JTAG file formats such as SVF or STAPL, can support
PSoC 3 programming. The list of programmers that support
PSoC 3 programming is available at
http://www.cypress.com/go/programming.
The JTAG clock frequency can be up to 14 MHz, or 1/3 of the
CPU clock frequency for 8 and 16-bit transfers, or 1/5 of the CPU
clock frequency for 32-bit transfers. By default, the JTAG pins are
enabled on new devices but the JTAG interface can be disabled,
allowing these pins to be used as GPIO instead.
Page 62 of 128
PSoC® 3: CY8C32 Family Data Sheet
Figure 9-1. JTAG Interface Connections between PSoC 3 and Programmer
VDD
Host Programmer
PSoC 3
VDD
VDDD, VDDA, VDDIO0, VDDIO1, VDDIO2, VDDIO3 1, 2, 3, 4
TCK
TMS
TCK (P1[1]
5
TMS (P1[0])
5
TDO
TDI (P1[4])
TDI
TDO (P1[3])
nTRST 6
nTRST (P1[5]) 6
XRES
XRES or P1[2] 4, 7
GND
VSSD, VSSA
GND
1
The voltage levels of Host Programmer and the PSoC 3 voltage domains involved in Programming should be same. The
Port 1 JTAG pins, XRES pin (XRES_N or P1[2]) are powered by VDDIO1. So, VDDIO1 of PSoC 3 should be at same voltage
level as host VDD. Rest of PSoC 3 voltage domains ( VDDD, VDDA, VDDIO0, VDDIO2, VDDIO3) need not be at the same voltage level as
host Programmer.
2
Vdda must be greater than or equal to all other power supplies (Vddd, Vddio’s) in PSoC 3.
3
For Power cycle mode Programming, XRES pin is not required. But the Host programmer must have
the capability to toggle power (Vddd, Vdda, All Vddio’s) to PSoC 3. This may typically require external
interface circuitry to toggle power which will depend on the programming setup. The power supplies can
be brought up in any sequence, however, once stable, VDDA must be greater than or equal to all other
supplies.
4
For JTAG Programming, Device reset can also be done without connecting to the XRES pin or Power cycle mode by
using the TMS,TCK,TDI, TDO pins of PSoC 3, and writing to a specific register. But this requires that the DPS setting in
NVL is not equal to “Debug Ports Disabled”.
5
By default, PSoC 3 is configured for 4-wire JTAG mode unless user changes the DPS setting. So the TMS pin is
unidirectional. But if the DPS setting is changed to non-JTAG mode, the TMS pin in JTAG is bi-directional as the SWD
Protocol has to be used for acquiring the PSoC 3 device initially. After switching from SWD to JTAG mode, the TMS pin
will be uni-directional. In such a case, unidirectional buffer should not be used on TMS line.
6
nTRST JTAG pin (P1[5]) cannot be used to reset the JTAG TAP controlller during first time programming of PSoC 3 as
the default setting is 4-wire JTAG (nTRST disabled). Use the TMS, TCK pins to do a reset of JTAG TAP controller.
7
If XRES pin is used by host, P1[2] will be configured as XRES by default only for 48-pin devices (without dedicated XRES
pin). For devices with dedicated XRES pin, P1[2] is GPIO pin by default. So use P1[2] as Reset pin only for 48-pin
devices, but use dedicated XRES pin for rest of devices.
Document Number: 001-56955 Rev. *Y
Page 63 of 128
PSoC® 3: CY8C32 Family Data Sheet
9.2 Serial Wire Debug Interface
The SWD interface is the preferred alternative to the JTAG
interface. It requires only two pins instead of the four or five
needed by JTAG. SWD provides all of the programming and
debugging features of JTAG at the same speed. SWD does not
provide access to scan chains or device chaining. The SWD
clock frequency can be up to 1/3 of the CPU clock frequency.
SWD uses two pins, either two of the JTAG pins (TMS and TCK)
or the USBIO D+ and D– pins. The USBIO pins are useful for in
system programming of USB solutions that would otherwise
require a separate programming connector. One pin is used for
the data clock and the other is used for data input and output.
SWD can be enabled on only one of the pin pairs at a time. This
only happens if, within 8 μs (key window) after reset, that pin pair
(JTAG or USB) receives a predetermined acquire sequence of
1s and 0s. If the NVL latches are set for SWD (see Section 5.5),
this sequence need not be applied to the JTAG pin pair. The
acquire sequence must always be applied to the USB pin pair.
SWD is used for debugging or for programming the flash
memory.
The SWD interface can be enabled from the JTAG interface or
disabled, allowing its pins to be used as GPIO. Unlike JTAG, the
SWD interface can always be reacquired on any device during
the key window. It can then be used to reenable the JTAG
interface, if desired. When using SWD or JTAG pins as standard
GPIO, make sure that the GPIO functionality and PCB circuits do
not interfere with SWD or JTAG use.
Figure 9-2. SWD Interface Connections between PSoC 3 and Programmer
VDD
Host Programmer
VDDD, VDDA, VDDIO0, VDDIO1, VDDIO2, VDDIO3 1, 2, 3
VDD
SWDCK
SWDCK (P1[1] or P15[7])
SWDIO
SWDIO (P1[0] or P15[6])
XRES or P1[2]
XRES
GND
PSoC 3
GND
3, 4
VSSD, VSSA
1
The voltage levels of the Host Programmer and the PSoC 3 voltage domains involved in Programming
should be the same. XRES pin (XRES_N or P1[2]) is powered by VDDIO1. The USB SWD pins are
powered by VDDD. So for Programming using the USB SWD pins with XRES pin, the VDDD, VDDIO1 of
PSoC 3 should be at the same voltage level as Host VDD. Rest of PSoC 3 voltage domains ( VDDA, VDDIO0,
VDDIO2, VDDIO3) need not be at the same voltage level as host Programmer. The Port 1 SWD pins are
powered by VDDIO1. So VDDIO1 of PSoC 3 should be at same voltage level as host VDD for Port 1 SWD
programming. Rest of PSoC 3 voltage domains ( VDDD, VDDA, VDDIO0, VDDIO2, VDDIO3) need not be at the same
voltage level as host Programmer.
2
Vdda must be greater than or equal to all other power supplies (Vddd, Vddio’s) in PSoC 3.
3
For Power cycle mode Programming, XRES pin is not required. But the Host programmer must have
the capability to toggle power (Vddd, Vdda, All Vddio’s) to PSoC 3. This may typically require external
interface circuitry to toggle power which will depend on the programming setup. The power supplies can
be brought up in any sequence, however, once stable, VDDA must be greater than or equal to all other
supplies.
4
P1[2] will be configured as XRES by default only for 48-pin devices (without dedicated XRES pin). For
devices with dedicated XRES pin, P1[2] is GPIO pin by default. So use P1[2] as Reset pin only for 48pin devices, but use dedicated XRES pin for rest of devices.
Document Number: 001-56955 Rev. *Y
Page 64 of 128
PSoC® 3: CY8C32 Family Data Sheet
9.3 Debug Features
Using the JTAG or SWD interface, the CY8C32 supports the
following debug features:
Halt and single-step the CPU
View and change CPU and peripheral registers, and RAM
addresses
Eight program address breakpoints
One memory access breakpoint—break on reading or writing
any memory address and data value
Break on a sequence of breakpoints (non recursive)
Debugging at the full speed of the CPU
Compatible with PSoC Creator and MiniProg3 programmer and
debugger
Standard JTAG programming and debugging interfaces make
CY8C32 compatible with other popular third-party tools (for
example, ARM / Keil)
9.4 Trace Features
The CY8C32 supports the following trace features when using
JTAG or SWD:
Trace the 8051 program counter (PC), accumulator register
(ACC), and one SFR / 8051 core RAM register
Trace depth up to 1000 instructions if all registers are traced,
or 2000 instructions if only the PC is traced (on devices that
include trace memory)
Program address trigger to start tracing
Trace windowing, that is, only trace when the PC is within a
given range
Two modes for handling trace buffer full: continuous (overwriting
the oldest trace data) or break when trace buffer is full
9.5 Single Wire Viewer Interface
The SWV interface is closely associated with SWD but can also
be used independently. SWV data is output on the JTAG
interface’s TDO pin. If using SWV, you must configure the device
for SWD, not JTAG. SWV is not supported with the JTAG
interface.
SWV is ideal for application debug where it is helpful for the
firmware to output data similar to 'printf' debugging on PCs. The
SWV is ideal for data monitoring, because it requires only a
single pin and can output data in standard UART format or
Manchester encoded format. For example, it can be used to tune
a PID control loop in which the output and graphing of the three
error terms greatly simplifies coefficient tuning.
The following features are supported in SWV:
32 virtual channels, each 32 bits long
Simple, efficient packing and serializing protocol
Supports standard UART format (N81)
9.6 Programming Features
The JTAG and SWD interfaces provide full programming
support. The entire device can be erased, programmed, and
verified. You can increase flash protection levels to protect
firmware IP. Flash protection can only be reset after a full device
Document Number: 001-56955 Rev. *Y
erase. Individual flash blocks can be erased, programmed, and
verified, if block security settings permit.
9.7 Device Security
PSoC 3 offers an advanced security feature called device
security, which permanently disables all test, programming, and
debug ports, protecting your application from external access.
The device security is activated by programming a 32-bit key
(0×50536F43) to a Write Once Latch (WOL).
The Write Once Latch is a type of nonvolatile latch (NVL). The
cell itself is an NVL with additional logic wrapped around it. Each
WOL device contains four bytes (32 bits) of data. The wrapper
outputs a ‘1’ if a super-majority (28 of 32) of its bits match a
pre-determined pattern (0×50536F43); it outputs a ‘0’ if this
majority is not reached. When the output is 1, the Write Once NV
latch locks the part out of Debug and Test modes; it also
permanently gates off the ability to erase or alter the contents of
the latch. Matching all bits is intentionally not required, so that
single (or few) bit failures do not deassert the WOL output. The
state of the NVL bits after wafer processing is truly random with
no tendency toward 1 or 0.
The WOL only locks the part after the correct 32-bit key
(0×50536F43) is loaded into the NVL's volatile memory,
programmed into the NVL's nonvolatile cells, and the part is
reset. The output of the WOL is only sampled on reset and used
to disable the access. This precaution prevents anyone from
reading, erasing, or altering the contents of the internal memory.
The user can write the key into the WOL to lock out external
access only if no flash protection is set (see “Flash Security” on
page 24). However, after setting the values in the WOL, a user
still has access to the part until it is reset. Therefore, a user can
write the key into the WOL, program the flash protection data,
and then reset the part to lock it.
If the device is protected with a WOL setting, Cypress cannot
perform failure analysis and, therefore, cannot accept RMAs
from customers. The WOL can be read out via SWD port to
electrically identify protected parts. The user can write the key in
WOL to lock out external access only if no flash protection is set.
For more information on how to take full advantage of the
security features in PSoC see the PSoC 3 TRM.
Disclaimer
Note the following details of the flash code protection features on
Cypress devices.
Cypress products meet the specifications contained in their
particular Cypress datasheets. Cypress believes that its family of
products is one of the most secure families of its kind on the
market today, regardless of how they are used. There may be
methods, unknown to Cypress, that can breach the code
protection features. Any of these methods, to our knowledge,
would be dishonest and possibly illegal. Neither Cypress nor any
other semiconductor manufacturer can guarantee the security of
their code. Code protection does not mean that we are
guaranteeing the product as “unbreakable.”
Cypress is willing to work with the customer who is concerned
about the integrity of their code. Code protection is constantly
evolving. We at Cypress are committed to continuously
improving the code protection features of our products.
Page 65 of 128
PSoC® 3: CY8C32 Family Data Sheet
9.8 CSP Package Bootloader
A factory-installed bootloader program is included in all devices
with CSP packages. The bootloader is compatible with
PSoC Creator 3.0 bootloadable project files and has the
following features:
I2C-based
SCLK and SDAT available at P1[6] and P1[7], respectively
External pull-up resistors required
I2C slave, address 4, data rate = 100 kbps
Single application
Wait two seconds for bootload command
Other bootloader options are as set by the PSoC Creator 3.0
Bootloader Component default
Occupies the bottom 9K of flash
For more information on this bootloader, see the following
Cypress application notes:
AN89611 – PSoC® 3 AND PSoC 5LP - Getting Started With
Chip Scale Packages (CSP)
AN73854 – PSoC 3 and PSoC 5 LP Introduction to Bootloaders
AN60317 – PSoC 3 and PSoC 5 LP I2C Bootloader
10. Development Support
The CY8C32 family has a rich set of documentation,
development tools, and online resources to assist you during
your development process. Visit
psoc.cypress.com/getting-started to find out more.
10.1 Documentation
A suite of documentation, supports the CY8C32 family to ensure
that you can find answers to your questions quickly. This section
contains a list of some of the key documents.
Software User Guide: A step-by-step guide for using PSoC
Creator. The software user guide shows you how the PSoC
Creator build process works in detail, how to use source control
with PSoC Creator, and much more.
Component Datasheets: The flexibility of PSoC allows the
creation of new peripherals (components) long after the device
has gone into production. Component datasheets provide all of
the information needed to select and use a particular component,
including a functional description, API documentation, example
code, and AC/DC specifications.
Application Notes: PSoC application notes discuss a particular
application of PSoC in depth; examples include brushless DC
motor control and on-chip filtering. Application notes often
include example projects in addition to the application note
document.
Note that a PSoC Creator bootloadable project must be
associated with .hex and .elf files for a bootloader project that is
configured for the target device. Bootloader .hex and .elf files can
be found at www.cypress.com/go/PSoC3datasheet.
Technical Reference Manual: The Technical Reference Manual
(TRM) contains all the technical detail you need to use a PSoC
device, including a complete description of all PSoC registers.
The factory-installed bootloader can be overwritten using JTAG
or SWD programming.
10.2 Online
In addition to print documentation, the Cypress PSoC forums
connect you with fellow PSoC users and experts in PSoC from
around the world, 24 hours a day, 7 days a week.
10.3 Tools
With industry standard cores, programming, and debugging
interfaces, the CY8C32 family is part of a development tool
ecosystem. Visit us at www.cypress.com/go/psoccreator for the
latest information on the revolutionary, easy to use PSoC Creator
IDE, supported third party compilers, programmers, debuggers,
and development kits.
Document Number: 001-56955 Rev. *Y
Page 66 of 128
PSoC® 3: CY8C32 Family Data Sheet
11. Electrical Specifications
Specifications are valid for –40 °C TA 85 °C and TJ 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,
except where noted. The unique flexibility of the PSoC UDBs and analog blocks enable many functions to be implemented in PSoC
Creator components, see the component datasheets for full AC/DC specifications of individual functions. See the “Example
Peripherals” section on page 45 for further explanation of PSoC Creator components.
11.1 Absolute Maximum Ratings
Table 11-1. Absolute Maximum Ratings DC Specifications[15]
Min
Typ
Max
Units
VDDA
Parameter
Analog supply voltage relative to
VSSA
Description
–0.5
–
6
V
VDDD
Digital supply voltage relative to
VSSD
–0.5
–
6
V
VDDIO
I/O supply voltage relative to VSSD
–0.5
–
6
V
VCCA
Direct analog core voltage input
–0.5
–
1.95
V
VCCD
Direct digital core voltage input
–0.5
–
1.95
V
VSSA
Analog ground voltage
VSSD –0.5
–
VSSD +
0.5
V
VGPIO[16]
DC input voltage on GPIO
Includes signals sourced by VDDA
and routed internal to the pin
VSSD –0.5
–
VDDIO +
0.5
V
VSIO
DC input voltage on SIO
Output disabled
VSSD –0.5
–
7
V
Output enabled
VSSD –0.5
–
6
V
VIND
Voltage at boost converter input
VBAT
Boost converter supply
IVDDIO
Current per VDDIO supply pin
IGPIO
GPIO current
ISIO
SIO current
IUSBIO
USBIO current
VEXTREF
ADC external reference inputs
LU
Latch up current[17]
ESDHBM
Electrostatic discharge voltage,
Human body model
ESDCDM
Electrostatic discharge voltage,
Charge device model
Conditions
Pins P0[3], P3[2]
0.5
–
5.5
V
VSSD –0.5
–
5.5
V
–
–
100
mA
–30
–
41
mA
–49
–
28
mA
–56
–
59
mA
–
–
2
V
–140
–
140
mA
VSSA tied to VSSD
2200
–
–
V
VSSA not tied to VSSD
750
–
–
V
500
–
–
V
Notes
15. Usage above the absolute maximum conditions listed in Table 11-1 may cause permanent damage to the device. Exposure to Absolute Maximum conditions for
extended periods of time may affect device reliability. The Maximum Storage Temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High
Temperature Storage Life. When used below Absolute Maximum conditions but above normal operating conditions, the device may not operate to specification.
16. The VDDIO supply voltage must be greater than the maximum voltage on the associated GPIO pins. Maximum voltage on GPIO pin VDDIO VDDA.
17. Meets or exceeds JEDEC Spec EIA/JESD78 IC Latch-up Test.
Document Number: 001-56955 Rev. *Y
Page 67 of 128
PSoC® 3: CY8C32 Family Data Sheet
11.2 Device Level Specifications
Specifications are valid for –40 °C TA 85 °C and TJ 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,
except where noted.
11.2.1 Device Level Specifications
Table 11-2. DC Specifications
Parameter
Description
Conditions
Min
Typ[22] Max
Units
VDDA
Analog supply voltage and input to analog Analog core regulator enabled
core regulator
1.8
–
5.5
V
VDDA
Analog supply voltage, analog regulator
bypassed
Analog core regulator disabled
1.71
1.8
1.89
V
VDDD
Digital supply voltage relative to VSSD
Digital core regulator enabled
1.8
–
VDDA[18]
–
–
VDDA + 0.1[24]
VDDD
Digital supply voltage, digital regulator
bypassed
Digital core regulator disabled
1.71
1.8
1.89
V
VDDIO[19]
I/O supply voltage relative to VSSIO
1.71
–
VDDA[18]
V
–
–
VDDA + 0.1[24]
VCCA
Direct analog core voltage input (Analog
regulator bypass)
Analog core regulator disabled
1.71
1.8
1.89
V
VCCD
Direct digital core voltage input (Digital
regulator bypass)
Digital core regulator disabled
1.71
1.8
1.89
V
T = –40 °C
VDDX = 2.7 V – 5.5 V;
T = 25 °C
FCPU = 6 MHz[23]
T = 85 °C
–
1.2
2.9
–
1.2
3.1
–
4.9
7.7
T = –40 °C
–
1.3
2.9
–
1.6
3.2
–
4.8
7.5
T = –40 °C
VDDX = 2.7 V – 5.5 V;
T = 25 °C
FCPU = 6 MHz
T = 85 °C
–
2.1
3.7
–
2.3
3.9
–
5.6
8.5
VDDX = 2.7 V – 5.5 V; T = –40 °C
FCPU = 12 MHz[23]
T = 25 °C
–
3.5
5.2
–
3.8
5.5
T = 85 °C
–
7.1
9.8
VDDX = 2.7 V – 5.5 V; T = –40 °C
FCPU = 24 MHz[23]
T = 25 °C
–
6.3
8.1
–
6.6
8.3
V
Active Mode
Only IMO and CPU clock enabled. CPU
executing simple loop from instruction
buffer.
VDDX = 2.7 V – 5.5 V;
T = 25 °C
FCPU = 3 MHz[23]
T = 85 °C
IDD
[20, 21]
IMO enabled, bus clock and CPU clock
enabled. CPU executing program from
flash.
T = 85 °C
–
10
13
VDDX = 2.7 V – 5.5 V; T = –40 °C
FCPU = 48 MHz[23]
T = 25 °C
–
11.5
13.5
–
12
14
T = 85 °C
–
15.5
18.5
mA
Notes
18. The power supplies can be brought up in any sequence however once stable VDDA must be greater than or equal to all other supplies.
19. The VDDIO supply voltage must be greater than the maximum voltage on the associated GPIO pins. Maximum voltage on GPIO pin VDDIO VDDA.
20. Total current for all power domains: digital (IDDD), analog (IDDA), and I/Os (IDDIO0, 1, 2, 3). Boost not included. All I/Os floating.
21. The current consumption of additional peripherals that are implemented only in programmed logic blocks can be found in their respective datasheets, available in
PSoC Creator, the integrated design environment. To estimate total current, find the CPU current at the frequency of interest and add peripheral currents for your
particular system from the device datasheet and component datasheets.
22. VDDX = 3.3 V.
23. Based on device characterizations (Not production tested).
24. Guaranteed by design, not production tested.
Document Number: 001-56955 Rev. *Y
Page 68 of 128
PSoC® 3: CY8C32 Family Data Sheet
Table 11-2. DC Specifications (continued)
Parameter
Description
Conditions
Min
Typ[22] Max
Units
[25]
Sleep Mode
CPU = OFF
RTC = ON (= ECO32K ON, in low-power
mode)
Sleep timer = ON (= ILO ON at 1 kHz)[26]
WDT = OFF
I2C Wake = OFF
Comparator = OFF
POR = ON
Boost = OFF
SIO pins in single ended input, unregulated
output mode
VDD = VDDIO =
4.5 V - 5.5 V
VDD = VDDIO =
2.7 V – 3.6 V
T = –40 °C
–
1.1
2.3
T = 25 °C
–
1.1
2.2
T = 85 °C
–
15
30
µA
T = –40 °C
–
1
2.2
T = 25 °C
–
1
2.1
T = 85 °C
–
12
28
T = 25 °C
–
2.2
4.2
Comparator = ON
VDD = VDDIO =
CPU = OFF
2.7 V – 3.6 V[28]
RTC = OFF
Sleep timer = OFF
WDT = OFF
I2C Wake = OFF
POR = ON
Boost = OFF
SIO pins in single ended input, unregulated
output mode
T = 25 °C
–
2.2
2.7
VDD = VDDIO =
I2C Wake = ON
CPU = OFF
2.7 V – 3.6 V[28]
RTC = OFF
Sleep timer = OFF
WDT = OFF
Comparator = OFF
POR = ON
Boost = OFF
SIO pins in single ended input, unregulated
output mode
T = 25 °C
–
2.2
2.8
T = –40 °C
–
0.2
1.5
T = 25 °C
–
0.5
1.5
T = 85 °C
–
4.1
5.3
VDD = VDDIO =
2.7 V – 3.6 V
T = –40 °C
–
0.2
1.5
T = 25 °C
–
0.2
1.5
T = 85 °C
–
3.2
4.2
VDD = VDDIO =
1.71 V – 1.95 V[27]
T = –40 °C
–
0.2
1.5
T = 25 °C
–
0.3
1.5
T = 85 °C
–
3.3
4.3
Analog current consumption while device is VDDA 3.6 V
reset[29]
VDDA 3.6 V
–
0.3
0.6
mA
–
1.4
3.3
mA
Digital current consumption while device is VDDD 3.6 V
reset[29]
VDDD 3.6 V
–
1.1
3.1
mA
–
0.7
3.1
mA
VDD = VDDIO =
1.71 V – 1.95 V[27]
Hibernate Mode[25]
Hibernate mode current
All regulators and oscillators off
SRAM retention
GPIO interrupts are active
Boost = OFF
SIO pins in single ended input, unregulated
output
mode
IDDAR
IDDDR
Document Number: 001-56955 Rev. *Y
VDD = VDDIO =
4.5 V - 5.5 V
µA
Page 69 of 128
PSoC® 3: CY8C32 Family Data Sheet
Figure 11-1. Active Mode Current vs FCPU, VDD = 3.3 V,
Temperature = 25 °C
Figure 11-2. Active Mode Current vs Temperature and FCPU,
VDD = 3.3 V
Figure 11-3. Active Mode Current vs VDD and Temperature,
FCPU = 24 MHz
Notes
25. If VCCD and VCCA are externally regulated, the voltage difference between VCCD and VCCA must be less than 50 mV.
26. Sleep timer generates periodic interrupts to wake up the CPU. This specification applies only to those times that the CPU is off.
27. Externally regulated mode.
28. Based on device characterization (not production tested).
29. Based on device characterization (not production tested). USBIO pins tied to ground (VSSD).
Document Number: 001-56955 Rev. *Y
Page 70 of 128
PSoC® 3: CY8C32 Family Data Sheet
Table 11-3. AC Specifications[30]
Parameter
Description
Conditions
Min
Typ
Max
Units
FCPU
CPU frequency
1.71 V VDDD 5.5 V
DC
–
50.01
MHz
FBUSCLK
Bus frequency
1.71 V VDDD 5.5 V
DC
–
50.01
MHz
Svdd
VDD ramp rate
–
–
0.066
V/µs
TIO_INIT
Time from VDDD/VDDA/VCCD/VCCA
IPOR to I/O ports set to their reset
states
–
–
10
µs
TSTARTUP
Time from VDDD/VDDA/VCCD/VCCA VCCA/VCCD = regulated from
PRES to CPU executing code at VDDA/VDDD, no PLL used, IMO
reset vector
boot mode (12 MHz typ.)
–
–
74
µs
TSLEEP
Wakeup from sleep mode –
Application of non-LVD interrupt to
beginning of execution of next CPU
instruction
–
–
15
µs
THIBERNATE
Wakeup from hibernate mode –
Application of external interrupt to
beginning of execution of next CPU
instruction
–
–
100
µs
Figure 11-4. FCPU vs. VDD
Vdd Voltage
5.5 V
Valid Operating Region
3.3 V
1.71 V
Valid Operating Region with SMP
0.5 V
0V
DC
1 MHz
10 MHz
50 MHz
CPU Frequency
Note
30. Based on device characterization (Not production tested).
Document Number: 001-56955 Rev. *Y
Page 71 of 128
PSoC® 3: CY8C32 Family Data Sheet
11.3 Power Regulators
Specifications are valid for –40 °C TA 85 °C and TJ 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,
except where noted.
11.3.1 Digital Core Regulator
Table 11-4. Digital Core Regulator DC Specifications
Parameter
Description
Input voltage
VDDD
Output voltage
VCCD
Regulator output capacitor
Conditions
±10%, X5R ceramic or better. The two
VCCD pins must be shorted together, with
as short a trace as possible, see Power
System on page 31
Figure 11-5. Regulators VCC vs VDD
Min
1.8
–
0.9
Typ
–
1.80
1
Max
5.5
–
1.1
Units
V
V
µF
Figure 11-6. Digital Regulator PSRR vs Frequency and VDD
11.3.2 Analog Core Regulator
Table 11-5. Analog Core Regulator DC Specifications
Parameter
Description
Input voltage
VDDA
Output voltage
VCCA
Regulator output capacitor
Conditions
±10%, X5R ceramic or better
Min
1.8
–
0.9
Typ
–
1.80
1
Max
5.5
–
1.1
Units
V
V
µF
Figure 11-7. Analog Regulator PSRR vs Frequency and VDD
Document Number: 001-56955 Rev. *Y
Page 72 of 128
PSoC® 3: CY8C32 Family Data Sheet
11.3.3 Inductive Boost Regulator
Unless otherwise specified, operating conditions are: VBAT = 0.5 V–3.6 V, VOUT = 1.8 V–5.0 V, IOUT = 0 mA–50 mA,
LBOOST = 4.7 µH–22 µH, CBOOST = 22 µF || 3 × 1.0 µF || 3 × 0.1 µF, CBAT = 22 µF, IF = 1.0 A. Unless otherwise specified, all charts
and graphs show typical values.
Table 11-6. Inductive Boost Regulator DC Specifications
Parameter
Description
VOUT
Boost output
VBAT
Input voltage to boost[32]
IOUT
voltage[31]
Output current
Min
Typ
Max
Units
vsel = 1.8 V in register BOOST_CR0
vsel = 1.9 V in register BOOST_CR0
vsel = 2.0 V in register BOOST_CR0
vsel = 2.4 V in register BOOST_CR0
vsel = 2.7 V in register BOOST_CR0
vsel = 3.0 V in register BOOST_CR0
vsel = 3.3 V in register BOOST_CR0
vsel = 3.6 V in register BOOST_CR0
vsel = 5.0 V in register BOOST_CR0
IOUT = 0 mA–5 mA vsel = 1.8 V–2.0 V,
TA = 0 °C–70 °C
Conditions
1.71
1.81
1.90
2.16
2.43
2.70
2.97
3.24
4.50
0.5
1.8
1.90
2.00
2.40
2.70
3.00
3.30
3.60
5.00
–
1.89
2.00
2.10
2.64
2.97
3.30
3.63
3.96
5.50
0.8
V
V
V
V
V
V
V
V
V
V
IOUT = 0 mA–15 mA vsel = 1.8 V–5.0 V[33],
TA = –10 °C–85 °C
1.6
–
3.6
V
IOUT = 0 mA–25 mA vsel = 1.8 V–2.7 V,
TA = –10 °C–85 °C
0.8
–
1.6
V
IOUT = 0 mA–50 mA vsel = 1.8 V–3.3 V[33],
TA = –40 °C–85 °C
1.8
–
2.5
V
vsel = 1.8 V–3.3 V[33],
TA = –10 °C–85 °C
1.3
–
2.5
V
vsel = 2.5 V–5.0 V[33],
TA = –10 °C–85 °C
2.5
–
3.6
V
TA = 0 °C–70 °C
VBAT = 0.5 V–0.8 V
0
–
5
mA
TA = –10 °C–85 °C
VBAT = 1.6 V–3.6 V
0
–
15
mA
VBAT = 0.8 V–1.6 V
0
–
25
mA
VBAT = 1.3 V–2.5 V
0
–
50
mA
VBAT = 2.5 V–3.6 V
0
–
50
mA
VBAT = 1.8 V–2.5 V
0
–
50
mA
–
–
700
mA
–
–
250
25
–
–
µA
µA
TA = –40 °C–85 °C
ILPK
Inductor peak current
IQ
Quiescent current
RegLOAD
Load regulation
–
–
10
%
RegLINE
Line regulation
–
–
10
%
Boost active mode
Boost sleep mode, IOUT < 1 µA
Notes
31. Listed vsel options are characterized. Additional vsel options are valid and guaranteed by design.
32. The boost will start at all valid VBAT conditions including down to VBAT = 0.5 V.
33. If VBAT is greater than or equal to VOUT boost setting, then VOUT will be less than VBAT due to resistive losses in the boost circuit.
Document Number: 001-56955 Rev. *Y
Page 73 of 128
PSoC® 3: CY8C32 Family Data Sheet
Table 11-7. Recommended External Components for Boost Circuit
Parameter
LBOOST
Description
Conditions
Boost inductor
Min
Typ
Max
Units
4.7 µH nominal
3.7
4.7
5.7
µH
10 µH nominal
8.0
10.0
12.0
µH
22 µH nominal
17.0
22.0
27.0
µH
CBOOST
Total capacitance sum of
VDDD, VDDA, VDDIO[34]
17.0
26.0
31.0
µF
CBAT
Battery filter capacitor
17.0
22.0
27.0
µF
IF
Schottky diode average
forward current
1.0
–
–
A
VR
Schottky reverse voltage
20.0
–
–
V
Figure 11-8. TA range over VBAT and VOUT
Figure 11-9. IOUT range over VBAT and VOUT
± µ&
± &
P$
±
±
&
&
9%$79
9%$79
P$
P$
1R%RRVW
P$
1R%RRVW
±&
92879
P$
92879
Figure 11-10. LBOOST values over VBAT and VOUT
+
+
,287 P$++
,287 P$+
9%$79
+
+
+
+
+
+
+
1R%RRVW
+
92879
Note
34. Based on device characterization (Not production tested).
Document Number: 001-56955 Rev. *Y
Page 74 of 128
PSoC® 3: CY8C32 Family Data Sheet
Figure 11-11. Efficiency vs VBAT, LBOOST = 4.7 µH [35]
Figure 11-12. Efficiency vs VBAT, LBOOST = 10 µH [35]
100%
95%
Vout = 1.8 V
95%
90%
Vout = 2.4 V
90%
85%
Vout = 3.3 V
85%
80%
% Efficiency
% Efficiency
100%
Vout = 5.0 V
80%
75%
Vout = 1.8 V
70%
Vout = 2.4 V
65%
65%
Vout = 3
3.3
3V
60%
60%
Vout = 5.0 V
55%
55%
75%
70%
50%
50%
0
0.5
1
1.5
2
2.5
3
3.5
0
4
0.5
1
1.5
2
2.5
3
3.5
4
VBAT, V
VBAT, V
Figure 11-13. Efficiency vs VBAT, LBOOST = 22 µH [35]
Figure 11-14. VRIPPLE vs VBAT [35]
100%
300
95%
250
90%
200
VRIPPLE, mV
% Efficiency
85%
80%
Vout = 1.8 V
75%
Vout = 2.4 V
70%
150
Lboost = 4.7 uH
100
Lboost = 10 uH
Vout = 3.3 V
65%
Lboost = 22 uH
50
60%
55%
0
0
50%
0
0.5
1
1.5
2
2.5
3
3.5
4
0.5
1
1.5
2
2.5
3
3.5
4
VBAT, V
VBAT, V
Note
35. Typical example. Actual values may vary depending on external component selection, PCB layout, and other design parameters.
Document Number: 001-56955 Rev. *Y
Page 75 of 128
PSoC® 3: CY8C32 Family Data Sheet
11.4 Inputs and Outputs
Specifications are valid for –40 °C TA 85 °C and TJ 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,
except where noted. Unless otherwise specified, all charts and graphs show typical values.
When the power supplies ramp up, there are low-impedance connections between each GPIO pin and its VDDIO supply. This causes
the pin voltages to track VDDIO until both VDDIO and VDDA reach the IPOR voltage, which can be as high as 1.45 V. At that point, the
low-impedance connections no longer exist and the pins change to their normal NVL settings.
11.4.1 GPIO
Table 11-9. GPIO DC Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
VIH
Input voltage high threshold
CMOS Input, PRT[×]CTL = 0 0.7 VDDIO
–
–
V
VIL
Input voltage low threshold
CMOS Input, PRT[×]CTL = 0
–
–
0.3 VDDIO
V
VIH
Input voltage high threshold
LVTTL Input, PRT[×]CTL =
1, VDDIO < 2.7 V
0.7 × VDDIO
–
–
V
VIH
Input voltage high threshold
LVTTL Input, PRT[×]CTL =
1, VDDIO 2.7V
2.0
–
–
V
VIL
Input voltage low threshold
LVTTL Input, PRT[×]CTL =
1, VDDIO < 2.7 V
–
–
0.3 × VDDIO
V
VIL
Input voltage low threshold
LVTTL Input, PRT[×]CTL =
1, VDDIO 2.7V
–
–
0.8
V
VOH
Output voltage high
IOH = 4 mA at 3.3 VDDIO
VDDIO – 0.6
–
–
V
IOH = 1 mA at 1.8 VDDIO
VDDIO – 0.5
–
–
V
IOL = 8 mA at 3.3 VDDIO
–
–
0.6
V
IOL = 4 mA at 1.8 VDDIO
–
–
0.6
V
VOL
Output voltage low
IOL = 3 mA at 3.3 VDDIO
Rpullup
Pull-up resistor
Rpulldown Pull-down resistor
IIL
Input leakage current (absolute
CIN
Input capacitance[36]
value)[36]]
–
–
0.4
V
3.5
5.6
8.5
k
3.5
5.6
8.5
k
25 °C, VDDIO = 3.0 V
–
–
2
nA
GPIOs not shared with
opamp outputs, MHz ECO or
kHzECO
–
4
7
pF
GPIOs shared with MHz
ECO or kHzECO[37]
–
5
7
pF
GPIOs shared with opamp
outputs
–
–
18
pF
VH
Input voltage hysteresis (Schmitt-Trigger)[36]
–
40
–
mV
Idiode
Current through protection diode to VDDIO and
VSSIO
–
–
100
µA
Rglobal
Resistance pin to analog global bus
25 °C, VDDIO = 3.0 V
–
320
–
Rmux
Resistance pin to analog mux bus
25 °C, VDDIO = 3.0 V
–
220
–
Notes
36. Based on device characterization (Not production tested).
37. For information on designing with PSoC oscillators, refer to the application note, AN54439 - PSoC® 3 and PSoC 5 External Oscillator.
Document Number: 001-56955 Rev. *Y
Page 76 of 128
PSoC® 3: CY8C32 Family Data Sheet
Figure 11-15. GPIO Output High Voltage and Current
Figure 11-16. GPIO Output Low Voltage and Current
Table 11-10. GPIO AC Specifications
Parameter
TriseF
TfallF
TriseS
TfallS
Fgpioout
Fgpioin
Description
Rise time in Fast Strong Mode[38]
Fall time in Fast Strong Mode[38]
Rise time in Slow Strong Mode[38]
Fall time in Slow Strong Mode[38]
GPIO output operating frequency
2.7 V < VDDIO < 5.5 V, fast strong drive mode
1.71 V < VDDIO < 2.7 V, fast strong drive mode
3.3 V < VDDIO < 5.5 V, slow strong drive mode
1.71 V < VDDIO < 3.3 V, slow strong drive mode
GPIO input operating frequency
1.71 V < VDDIO < 5.5 V
Conditions
3.3 V VDDIO Cload = 25 pF
3.3 V VDDIO Cload = 25 pF
3.3 V VDDIO Cload = 25 pF
3.3 V VDDIO Cload = 25 pF
Min
–
–
–
–
Typ
–
–
–
–
Max
6
6
60
60
Units
ns
ns
ns
ns
90/10% VDDIO into 25 pF
90/10% VDDIO into 25 pF
90/10% VDDIO into 25 pF
90/10% VDDIO into 25 pF
–
–
–
–
–
–
–
–
33
20
7
3.5
MHz
MHz
MHz
MHz
90/10% VDDIO
–
–
33
MHz
Note
38. Based on device characterization (Not production tested).
Document Number: 001-56955 Rev. *Y
Page 77 of 128
PSoC® 3: CY8C32 Family Data Sheet
11.4.2 SIO
Table 11-11. SIO DC Specifications
Parameter
Description
Vinmax
Maximum input voltage
Vinref
Input voltage reference (Differential input mode)
Conditions
Min
Typ
Max
Units
All allowed values of VDDIO and
VDDD, see Section 11.1
–
–
5.5
V
0.5
–
0.52 VDDIO
V
VDDIO > 3.7
1
–
VDDIO – 1
V
VDDIO < 3.7
1
–
VDDIO – 0.5
V
Output voltage reference (Regulated output mode)
Voutref
Input voltage high threshold
VIH
0.7 VDDIO
–
–
V
SIO_ref + 0.2
–
–
V
CMOS input
–
–
0.3 VDDIO
V
Hysteresis disabled
–
–
SIO_ref – 0.2
V
GPIO mode
CMOS input
Differential input mode[39]
Hysteresis disabled
Input voltage low threshold
VIL
GPIO mode
Differential input
mode[39]
Output voltage high
VOH
Unregulated mode
IOH = 4 mA, VDDIO = 3.3 V
VDDIO – 0.4
–
–
V
Regulated mode[39]
IOH = 1 mA
SIO_ref – 0.65
–
SIO_ref + 0.2
V
IOH = 0.1 mA
SIO_ref – 0.3
–
SIO_ref + 0.2
V
–
–
0.8
V
Regulated
mode[39]
Output voltage low
VOL
VDDIO = 3.30 V, IOL = 25 mA
VDDIO = 3.30 V, IOL = 20 mA
–
–
0.4
V
VDDIO = 1.80 V, IOL = 4 mA
–
–
0.4
V
Rpullup
Pull-up resistor
3.5
5.6
8.5
k
Rpulldown
Pull-down resistor
3.5
5.6
8.5
k
IIL
Input leakage current (absolute
value)[40]
VIH < Vddsio
25 °C, Vddsio = 3.0 V, VIH = 3.0 V
–
–
14
nA
VIH > Vddsio
25 °C, Vddsio = 0 V, VIH = 3.0 V
–
–
10
µA
–
–
7
pF
Single ended mode (GPIO mode)
–
40
–
mV
Differential mode
–
35
–
mV
–
–
100
µA
CIN
Input Capacitance[40]
VH
Input voltage hysteresis
(Schmitt-Trigger)[40]
Idiode
Current through protection diode
to VSSIO
Notes
39. See Figure 6-10 on page 40 and Figure 6-13 on page 43 for more information on SIO reference
40. Based on device characterization (Not production tested).
Document Number: 001-56955 Rev. *Y
Page 78 of 128
PSoC® 3: CY8C32 Family Data Sheet
Figure 11-17. SIO Output High Voltage and Current,
Unregulated Mode
Figure 11-18. SIO Output Low Voltage and Current,
Unregulated Mode
Figure 11-19. SIO Output High Voltage and Current,
Regulated Mode
Table 11-12. SIO AC Specifications
Parameter
TriseF
TfallF
TriseS
TfallS
Description
Rise time in Fast Strong Mode
(90/10%)[41]
Fall time in Fast Strong Mode
(90/10%)[41]
Rise time in Slow Strong Mode
(90/10%)[41]
Fall time in Slow Strong Mode
(90/10%)[41]
Conditions
Cload = 25 pF, VDDIO = 3.3 V
Min
–
Typ
–
Max
12
Units
ns
Cload = 25 pF, VDDIO = 3.3 V
–
–
12
ns
Cload = 25 pF, VDDIO = 3.0 V
–
–
75
ns
Cload = 25 pF, VDDIO = 3.0 V
–
–
60
ns
Note
41. Based on device characterization (Not production tested).
Document Number: 001-56955 Rev. *Y
Page 79 of 128
PSoC® 3: CY8C32 Family Data Sheet
Table 11-12. SIO AC Specifications (continued)
Parameter
Fsioout
Fsioin
Description
SIO output operating frequency
2.7 V < VDDIO < 5.5 V, Unregulated output (GPIO) mode, fast
strong drive mode
1.71 V < VDDIO < 2.7 V, Unregulated output (GPIO) mode, fast
strong drive mode
3.3 V < VDDIO < 5.5 V, Unregulated output (GPIO) mode, slow
strong drive mode
1.71 V < VDDIO < 3.3 V, Unregulated output (GPIO) mode, slow
strong drive mode
2.7 V < VDDIO < 5.5 V, Regulated
output mode, fast strong drive
mode
1.71 V < VDDIO < 2.7 V, Regulated
output mode, fast strong drive
mode
1.71 V < VDDIO < 5.5 V, Regulated
output mode, slow strong drive
mode
SIO input operating frequency
1.71 V < VDDIO < 5.5 V
Conditions
Min
Typ
Max
Units
90/10% VDDIO into 25 pF
–
–
33
MHz
90/10% VDDIO into 25 pF
–
–
16
MHz
90/10% VDDIO into 25 pF
–
–
5
MHz
90/10% VDDIO into 25 pF
–
–
4
MHz
Output continuously switching
into 25 pF
–
–
20
MHz
Output continuously switching
into 25 pF
–
–
10
MHz
Output continuously switching
into 25 pF
–
–
2.5
MHz
90/10% VDDIO
–
–
33
MHz
Figure 11-20. SIO Output Rise and Fall Times, Fast Strong
Mode, VDDIO = 3.3 V, 25 pF Load
Document Number: 001-56955 Rev. *Y
Figure 11-21. SIO Output Rise and Fall Times, Slow Strong
Mode, VDDIO = 3.3 V, 25 pF Load
Page 80 of 128
PSoC® 3: CY8C32 Family Data Sheet
Table 11-13. SIO Comparator Specifications[42]
Parameter
Vos
Description
Conditions
Min
Typ
Max
Units
VDDIO = 2 V
–
–
68
mV
VDDIO = 2.7 V
–
–
72
Offset voltage
VDDIO = 5.5 V
TCVos
Offset voltage drift with temp
CMRR
Common mode rejection ratio
Tresp
–
–
82
–
–
250
μV/°C
VDDIO = 2 V
30
–
–
dB
VDDIO = 2.7 V
35
–
–
VDDIO = 5.5 V
40
–
–
–
–
30
Response time
ns
11.4.3 USBIO
For operation in GPIO mode, the standard range for VDDD applies, see Device Level Specifications on page 68.
Table 11-14. USBIO DC Specifications
Parameter
Rusbi
Description
USB D+ pull-up resistance
Min
Typ
Max
Units
With idle bus
Conditions
0.900
–
1.575
k
Rusba
USB D+ pull-up resistance
While receiving traffic
1.425
–
3.090
k
Vohusb
Static output high
15 k ±5% to Vss, internal pull-up
enabled
2.8
–
3.6
V
Volusb
Static output low
15 k ±5% to Vss, internal pull-up
enabled
–
–
0.3
V
Vohgpio
Output voltage high, GPIO mode
IOH = 4 mA, VDDD 3 V
2.4
–
–
V
Volgpio
Output voltage low, GPIO mode
IOL = 4 mA, VDDD 3 V
–
–
0.3
V
Vdi
Differential input sensitivity
|(D+)–(D–)|
–
–
0.2
V
Vcm
Differential input common mode
range
–
0.8
–
2.5
V
0.8
–
2
V
3
–
7
k
21.78
(–1%)
22
22.22
(+1%)
28
–
44
Vse
Single ended receiver threshold
–
Rps2
PS/2 pull-up resistance
In PS/2 mode, with PS/2 pull-up
enabled
External USB series resistor
In series with each USB pin
Zo
USB driver output impedance
Including Rext
CIN
USB transceiver input capacitance –
–
–
20
pF
IIL[42]
Input leakage current (absolute
value)
–
–
2
nA
Rext
25 °C, VDDD = 3.0 V
Note
42. Based on device characterization (Not production tested).
Document Number: 001-56955 Rev. *Y
Page 81 of 128
PSoC® 3: CY8C32 Family Data Sheet
Figure 11-22. USBIO Output High Voltage and Current, GPIO
Mode
Figure 11-23. USBIO Output Low Voltage and Current, GPIO
Mode
Table 11-15. USBIO AC Specifications
Parameter
Description
Tdrate
Full-speed data rate average bit rate
Tjr1
Tjr2
Tdj1
Tdj2
Tfdeop
Tfeopt
Tfeopr
Tfst
Fgpio_out
Tr_gpio
Tf_gpio
Conditions
Receiver data jitter tolerance to next
transition
Receiver data jitter tolerance to pair
transition
Driver differential jitter to next
transition
Driver differential jitter to pair transition
Source jitter for differential transition to
SE0 transition
Source SE0 interval of EOP
Receiver SE0 interval of EOP
Width of SE0 interval during differential transition
GPIO mode output operating
3 V VDDD 5.5 V
frequency
VDDD = 1.71 V
Rise time, GPIO mode, 10%/90%
VDDD > 3 V, 25 pF load
VDDD
VDDD = 1.71 V, 25 pF load
Fall time, GPIO mode, 90%/10% VDDD VDDD > 3 V, 25 pF load
VDDD = 1.71 V, 25 pF load
Min
12 – 0.25%
Typ
12
Units
MHz
–
Max
12 +
0.25%
8
–8
–5
–
5
ns
–3.5
–
3.5
ns
–4
–2
–
–
4
5
ns
ns
160
82
–
–
–
–
175
–
14
ns
ns
ns
–
–
–
–
–
–
–
–
–
–
–
–
20
6
12
40
12
40
MHz
MHz
ns
ns
ns
ns
ns
Figure 11-24. USBIO Output Rise and Fall Times, GPIO Mode,
Document Number: 001-56955 Rev. *Y
Page 82 of 128
PSoC® 3: CY8C32 Family Data Sheet
VDDD = 3.3 V, 25 pF Load
Table 11-16. USB Driver AC Specifications
Parameter
Description
Tr
Transition rise time
Tf
Transition fall time
TR
Rise/fall time matching
Vcrs
Conditions
VUSB_5, VUSB_3.3, see USB DC
Specifications on page 98
Output signal crossover voltage
Min
–
–
90%
Typ
–
–
–
Max
20
20
111%
Units
ns
ns
1.3
–
2
V
Min
0.7 VDDIO
–
Typ
–
–
Units
V
V
3.5
–
–
5.6
3
100
Max
–
0.3
VDDIO
8.5
–
–
–
–
100
µA
Min
1
Typ
–
Max
–
Units
µs
11.4.4 XRES
Table 11-17. XRES DC Specifications
Parameter
Description
VIH
Input voltage high threshold
VIL
Input voltage low threshold
Rpullup
CIN
VH
Idiode
Conditions
Pull-up resistor
Input capacitance[43]
Input voltage hysteresis
(Schmitt-Trigger)[43]
Current through protection diode to
VDDIO and VSSIO
k
pF
mV
Table 11-18. XRES AC Specifications
Parameter
Description
Reset pulse width
TRESET
Conditions
Note
43. Based on device characterization (Not production tested).
Document Number: 001-56955 Rev. *Y
Page 83 of 128
PSoC® 3: CY8C32 Family Data Sheet
11.5 Analog Peripherals
Specifications are valid for –40 °C TA 85 °C and TJ 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,
except where noted.
11.5.1 Delta-sigma ADC
Unless otherwise specified, operating conditions are:
Operation in continuous sample mode
fclk = 6.144 MHz
Reference = 1.024 V internal reference bypassed on P3.2 or P0.3
Unless otherwise specified, all charts and graphs show typical values
Table 11-19. 12-bit Delta-sigma ADC DC Specifications
Parameter
Description
Conditions
Resolution
Number of channels, single ended
Number of channels, differential
Monotonic
Ge
Gain error
Gd
Gain drift
Vos
Input offset voltage
Temperature coefficient, input offset
voltage
Input voltage range, single ended[45]
Input voltage range, differential unbuffered[45]
Input voltage range, differential,
buffered[45]
Integral non linearity[45]
Differential non linearity[45]
Integral non linearity[45]
Differential non linearity[45]
ADC input resistance
TCVos
INL12
DNL12
INL8
DNL8
Rin_Buff
Rin_ADC12 ADC input resistance
Differential pair is formed using a
pair of GPIOs.
Yes
Buffered, buffer gain = 1, Range =
±1.024 V, 25 °C
Buffered, buffer gain = 1, Range =
±1.024 V
Buffered, 12-bit mode
Buffer gain = 1, 12-bit,
Range = ±1.024 V
Range = ±1.024 V, unbuffered
Range = ±1.024 V, unbuffered
Range = ±1.024 V, unbuffered
Range = ±1.024 V, unbuffered
Input buffer used
Input buffer bypassed, 12 bit,
Range = ±1.024 V
Rin_ExtRef ADC external reference input resistance
ADC external reference input voltage, see
Vextref
also internal reference in Voltage
Pins P0[3], P3[2]
Reference on page 86
Current Consumption
IDD_12
IDDA + IDDD current consumption, 12 bit[45] 192 ksps, unbuffered
Buffer current consumption[45]
IBUFF
Min
8
Typ
–
Units
bits
–
Max
12
No. of
GPIO
No. of
GPIO/2
–
–
–
–
–
–
–
–
±0.2
%
–
–
50
–
–
±0.1
ppm/°
C
mV
–
–
1
µV/°C
VSSA
–
VDDA
V
VSSA
–
VDDA
V
VSSA
–
VDDA – 1
V
–
–
–
–
10
–
–
–
–
–
±1
±1
±1
±1
–
LSB
LSB
LSB
LSB
M
–
148[46]
–
k
–
70[46, 47]
–
k
0.9
–
1.3
V
–
–
–
–
1.95
2.5
mA
mA
–
–
–
Notes
45. Based on device characterization (not production tested).
46. By using switched capacitors at the ADC input an effective input resistance is created. Holding the gain and number of bits constant, the resistance is proportional to
the inverse of the clock frequency. This value is calculated, not measured. For more information see the Technical Reference Manual.
47. Recommend an external reference device with an output impedance <100 Ω, for example, the LM185/285/385 family. A 1-µF capacitor is recommended. For more
information, see AN61290 - PSoC® 3 and PSoC 5LP Hardware Design Considerations.
Document Number: 001-56955 Rev. *Y
Page 84 of 128
PSoC® 3: CY8C32 Family Data Sheet
Table 11-20. Delta-sigma ADC AC Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
–
–
4
Samples
Buffer gain = 1, 12-bit,
Range = ±1.024 V
–
–
0.0032
%
Range = ±1.024 V, unbuffered
4
–
192
ksps
Range = ±1.024 V, unbuffered
–
44
–
kHz
Range = ±1.024 V, unbuffered
66
–
–
dB
Startup time
Total harmonic distortion[48]
THD
12-Bit Resolution Mode
Sample rate, continuous, high power[48]
SR12
BW12
Input bandwidth at max sample rate
SINAD12int
Signal to noise ratio, 12-bit, internal
reference[48]
[48]
8-Bit Resolution Mode
SR8
Sample rate, continuous, high power[48]
Range = ±1.024 V, unbuffered
8
–
384
ksps
BW8
Input bandwidth at max sample rate[48]
Range = ±1.024 V, unbuffered
–
88
–
kHz
SINAD8int
Signal to noise ratio, 8-bit, internal
reference[48]
Range = ±1.024 V, unbuffered
43
–
–
dB
Table 11-21. Delta-sigma ADC Sample Rates, Range = ±1.024 V
Continuous
Resolution,
Bits
Min
Max
8
8000
9
6400
10
11
12
Multi-Sample
Min
Max
384000
1911
91701
307200
1543
74024
5566
267130
1348
64673
4741
227555
1154
55351
4000
192000
978
46900
Figure 11-25. Delta-sigma ADC IDD vs sps, Range = ±1.024 V,
Continuous Sample Mode, Input Buffer Bypassed
Note
48. Based on device characterization (Not production tested).
Document Number: 001-56955 Rev. *Y
Page 85 of 128
PSoC® 3: CY8C32 Family Data Sheet
11.5.2 Voltage Reference
Table 11-22. Voltage Reference Specifications
See also ADC external reference specifications in Section 11.5.1.
Parameter
VREF
Description
Conditions
Min
Typ
Max
Units
Initial trimming,
25 °C
1.014 (–1%)
1.024
1.034 (+1%)
V
Conditions
Min
Typ
Max
Units
Resistance pin-to-pin through P2[4], AGL0, DSM INP, VDDA = 3 V
AGL1, P2[5][49]
–
1472
2200
VDDA = 3 V
–
706
1100
Precision reference voltage
11.5.3 Analog Globals
Table 11-23. Analog Globals Specifications
Parameter
Rppag
Description
Rppmuxbus Resistance pin-to-pin through P2[3], amuxbusL,
P2[4][49]
11.5.4 Comparator
Table 11-24. Comparator DC Specifications
Parameter
VOS
Description
Conditions
Min
Input offset voltage in fast mode
Factory trim, VDDA > 2.7 V,
VIN 0.5 V
–
Input offset voltage in slow mode
Factory trim, VIN 0.5 V
–
Input offset voltage in fast mode[50]
Custom trim
–
Input offset voltage in slow
mode[50]
Typ
–
Max
Units
10
mV
9
mV
4
mV
Custom trim
–
–
4
mV
Input offset voltage in ultra low-power
mode
VDDA ≤ 4.6 V
–
±12
–
mV
VHYST
Hysteresis
Hysteresis enable mode
–
10
32
mV
VICM
Input common mode voltage
High current / fast mode
VSSA
–
VDDA
V
Low current / slow mode
VSSA
–
VDDA
V
Ultra low power mode
VDDA ≤ 4.6 V
VSSA
–
VDDA –
1.15
CMRR
Common mode rejection ratio
–
50
–
dB
ICMP
High current mode/fast mode[51]
–
–
400
µA
–
–
100
µA
–
6
–
µA
Low current mode/slow mode[51]
Ultra low-power mode[51]
VDDA ≤ 4.6 V
Table 11-25. Comparator AC Specifications
Parameter
Description
Response time, high current mode
Tresp
[51]
Response time, low current mode[51]
Response time, ultra low-power
mode[51]
Conditions
Min
Typ
Max
Units
50 mV overdrive, measured pin-to-pin
–
50 mV overdrive, measured pin-to-pin
–
75
110
ns
155
200
ns
50 mV overdrive, measured
pin-to-pin, VDDA ≤ 4.6 V
–
55
–
µs
Notes
49. The resistance of the analog global and analog mux bus is high if VDDA 2.7 V, and the chip is in either sleep or hibernate mode. Use of analog global and analog
mux bus under these conditions is not recommended
50. The recommended procedure for using a custom trim value for the on-chip comparators can be found in the TRM.
51. Based on device characterization (Not production tested).
Document Number: 001-56955 Rev. *Y
Page 86 of 128
PSoC® 3: CY8C32 Family Data Sheet
11.5.5 Current Digital-to-analog Converter (IDAC)
All specifications are based on use of the low-resistance IDAC output pins (see Pin Descriptions on page 12 for details). See the IDAC
component data sheet in PSoC Creator for full electrical specifications and APIs.
Unless otherwise specified, all charts and graphs show typical values.
Table 11-26. IDAC DC Specifications
Parameter
Description
Conditions
Resolution
IOUT
Output current at code = 255
Min
Typ
Max
Units
–
–
8
bits
Range = 2.04 mA, code = 255,
VDDA 2.7 V, Rload = 600
–
2.04
–
mA
Range = 2.04 mA, high speed
mode, code = 255, VDDA 2.7 V,
Rload = 300
–
2.04
–
mA
Range = 255 µA, code = 255, Rload
= 600
–
255
–
µA
Range = 31.875 µA, code = 255,
Rload = 600
–
31.875
–
µA
Monotonicity
–
–
Yes
Ezs
Zero scale error
–
0
±1
LSB
Eg
Gain error
Range = 2.04 mA, 25 °C
–
–
±2.5
%
Range = 255 µA, 25 ° C
–
–
±2.5
%
Range = 31.875 µA, 25 ° C
–
–
±3.5
%
Range = 2.04 mA
–
–
0.04
% / °C
Range = 255 µA
–
–
0.04
% / °C
Range = 31.875 µA
–
–
0.05
% / °C
Sink mode, range = 255 µA, Codes
8 – 255, Rload = 2.4 k, Cload =
15 pF
–
±0.9
±1
LSB
Source mode, range = 255 µA,
Codes 8 – 255, Rload = 2.4 k,
Cload = 15 pF
–
±1.2
±1.6
LSB
Sink mode, range = 255 µA, Rload
= 2.4 k, Cload = 15 pF
–
±0.3
±1
LSB
Source mode, range = 255 µA,
Rload = 2.4 k, Cload = 15 pF
–
±0.3
±1
LSB
Voltage headroom at max current,
Rload to VDDA or Rload to VSSA,
VDIFF from VDDA
1
–
–
V
TC_Eg
INL
DNL
Vcompliance
Temperature coefficient of gain
error
Integral nonlinearity
Differential nonlinearity
Dropout voltage, source or sink
mode
Document Number: 001-56955 Rev. *Y
Page 87 of 128
PSoC® 3: CY8C32 Family Data Sheet
Table 11-26. IDAC DC Specifications (continued)
Parameter
IDD
Description
Operating current, code = 0
Conditions
Min
Typ
Max
Units
Low speed mode, source mode,
range = 31.875 µA
–
44
100
µA
Low speed mode, source mode,
range = 255 µA,
–
33
100
µA
Low speed mode, source mode,
range = 2.04 mA
–
33
100
µA
Low speed mode, sink mode,
range = 31.875 µA
–
36
100
µA
Low speed mode, sink mode,
range = 255 µA
–
33
100
µA
Low speed mode, sink mode,
range = 2.04 mA
–
33
100
µA
High speed mode, source mode,
range = 31.875 µA
–
310
500
µA
High speed mode, source mode,
range = 255 µA
–
305
500
µA
High speed mode, source mode,
range = 2.04 mA
–
305
500
µA
High speed mode, sink mode,
range = 31.875 µA
–
310
500
µA
High speed mode, sink mode,
range = 255 µA
–
300
500
µA
High speed mode, sink mode,
range = 2.04 mA
–
300
500
µA
Figure 11-26. IDAC INL vs Input Code, Range = 255 µA,
Source Mode
Document Number: 001-56955 Rev. *Y
Figure 11-27. IDAC INL vs Input Code, Range = 255 µA, Sink
Mode
Page 88 of 128
PSoC® 3: CY8C32 Family Data Sheet
Figure 11-28. IDAC DNL vs Input Code, Range = 255 µA,
Source Mode
Figure 11-29. IDAC DNL vs Input Code, Range = 255 µA, Sink
Mode
Figure 11-30. IDAC INL vs Temperature, Range = 255 µA, High
speed mode
Figure 11-31. IDAC DNL vs Temperature, Range = 255 µA,
High speed mode
Document Number: 001-56955 Rev. *Y
Page 89 of 128
PSoC® 3: CY8C32 Family Data Sheet
Figure 11-32. IDAC Full Scale Error vs Temperature, Range
= 255 µA, Source Mode
Figure 11-33. IDAC Full Scale Error vs Temperature, Range
= 255 µA, Sink Mode
Figure 11-34. IDAC Operating Current vs Temperature,
Range = 255 µA, Code = 0, Source Mode
Figure 11-35. IDAC Operating Current vs Temperature,
Range = 255 µA, Code = 0, Sink Mode
Document Number: 001-56955 Rev. *Y
Page 90 of 128
PSoC® 3: CY8C32 Family Data Sheet
Table 11-27. IDAC AC Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
FDAC
Update rate
–
–
8
Msps
TSETTLE
Settling time to 0.5 LSB
Range = 31.875 µA or 255 µA, full
scale transition, High speed mode,
600 15-pF load
–
–
125
ns
Current noise
Range = 255 µA, source mode,
High speed mode, VDDA = 5 V,
10 kHz
–
340
–
pA/sqrtHz
Figure 11-36. IDAC Step Response, Codes 0x40 - 0xC0,
255 µA Mode, Source Mode, High speed mode, VDDA = 5 V
Figure 11-37. IDAC Glitch Response, Codes 0x7F - 0x80,
255 µA Mode, Source Mode, High speed mode, VDDA = 5 V
Figure 11-38. IDAC PSRR vs Frequency
Figure 11-39. IDAC Current Noise, 255 µA Mode,
Source Mode, High speed mode, VDDA = 5 V
60
PSRR, dB
P
50
40
30
20
10
0
0.1
1
10
100
1000
10000
Frequency, kHz
255 ȝA, code 0x7F
Document Number: 001-56955 Rev. *Y
255 ȝA, code 0xFF
Page 91 of 128
PSoC® 3: CY8C32 Family Data Sheet
11.5.6 Voltage Digital to Analog Converter (VDAC)
See the VDAC component datasheet in PSoC Creator for full electrical specifications and APIs.
Unless otherwise specified, all charts and graphs show typical values.
Table 11-28. VDAC DC Specifications
Parameter
Description
Conditions
Resolution
Min
Typ
Max
Units
–
8
–
bits
INL1
Integral nonlinearity
1 V scale
–
±2.1
±2.5
LSB
INL4
Integral nonlinearity[52]
4 V scale
–
±2.1
±2.5
LSB
DNL1
Differential nonlinearity
1 V scale
–
±0.3
±1
LSB
nonlinearity[52]
DNL4
Differential
4 V scale
–
±0.3
±1
LSB
Rout
Output resistance
1 V scale
–
4
–
k
4 V scale
–
16
–
k
VOUT
Output voltage range, code = 255
1 V scale
–
1.02
–
V
–
4.08
–
V
–
–
Yes
–
4 V scale, VDDA = 5 V
Monotonicity
VOS
Zero scale error
Eg
Gain error
TC_Eg
IDD
Operating current
–
0
±0.9
LSB
1 V scale
–
–
±2.5
%
4 V scale
–
–
±2.5
%
Temperature coefficient, gain error 1 V scale
–
–
0.03
%FSR / °C
Figure 11-40. VDAC INL vs Input Code, 1 V Mode
4 V scale
–
–
0.03
%FSR / °C
Low speed mode
–
–
100
µA
High speed mode
–
–
500
µA
Figure 11-41. VDAC DNL vs Input Code, 1 V Mode
Note
52. Based on device characterization (Not production tested).
Document Number: 001-56955 Rev. *Y
Page 92 of 128
PSoC® 3: CY8C32 Family Data Sheet
Figure 11-42. VDAC INL vs Temperature, 1 V Mode
Figure 11-43. VDAC DNL vs Temperature, 1 V Mode
Figure 11-44. VDAC Full Scale Error vs Temperature, 1 V
Mode
Figure 11-45. VDAC Full Scale Error vs Temperature, 4 V
Mode
Figure 11-46. VDAC Operating Current vs Temperature, 1V
Mode, Low speed mode
Figure 11-47. VDAC Operating Current vs Temperature, 1 V
Mode, High speed mode
Document Number: 001-56955 Rev. *Y
Page 93 of 128
PSoC® 3: CY8C32 Family Data Sheet
Table 11-29. VDAC AC Specifications t
Parameter
FDAC
Description
Conditions
Update rate
Min
Typ
Max
Units
1 V scale
–
–
1000
ksps
4 V scale
–
–
250
ksps
–
0.45
1
µs
TsettleP
Settling time to 0.1%, step 25% to 1 V scale, Cload = 15 pF
75%
4 V scale, Cload = 15 pF
–
0.8
3.2
µs
TsettleN
Settling time to 0.1%, step 75% to 1 V scale, Cload = 15 pF
25%
–
0.45
1
µs
4 V scale, Cload = 15 pF
–
0.7
3
µs
Range = 1 V, High speed mode,
VDDA = 5 V, 10 kHz
–
750
–
nV/sqrtHz
Voltage noise
Figure 11-48. VDAC Step Response, Codes 0x40 - 0xC0, 1 V
Mode, High speed mode, VDDA = 5 V
Figure 11-49. VDAC Glitch Response, Codes 0x7F - 0x80, 1 V
Mode, High speed mode, VDDA = 5 V
Figure 11-50. VDAC PSRR vs Frequency
Figure 11-51. VDAC Voltage Noise, 1 V Mode, High speed
mode, VDDA = 5 V
50
PSRR, dB
P
40
30
20
10
0
0.1
1
10
Frequency, kHz
4 V, code 0x7F
Document Number: 001-56955 Rev. *Y
100
1000
4 V, code 0xFF
Page 94 of 128
PSoC® 3: CY8C32 Family Data Sheet
11.5.7 Temperature Sensor
Table 11-30. Temperature Sensor Specifications
Parameter
Description
Temp sensor accuracy
Conditions
Range: –40 °C to +85 °C
Min
Typ
Max
Units
–
±5
–
°C
11.5.8 LCD Direct Drive
Table 11-31. LCD Direct Drive DC Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
ICC
LCD system operating current
Device sleep mode with wakeup at
400-Hz rate to refresh LCDs, bus
clock = 3 MHz, VDDIO = VDDA = 3 V,
4 commons, 16 segments, 1/4 duty
cycle, 50 Hz frame rate, no glass
connected
–
38
–
A
ICC_SEG
Current per segment driver
Strong drive mode
–
260
–
µA
VBIAS
LCD bias range (VBIAS refers to the VDDA 3 V and VDDA VBIAS
main output voltage(V0) of LCD DAC)
2
–
5
V
VDDA 3 V and VDDA VBIAS
–
9.1 × VDDA
–
mV
Drivers may be combined
–
500
5000
pF
LCD bias step size
LCD capacitance per
segment/common driver
Long term segment offset
IOUT
Output drive current per segment
driver)
VDDIO = 5.5V, strong drive mode
–
–
20
mV
355
–
710
µA
Min
10
Typ
50
Max
150
Units
Hz
Table 11-32. LCD Direct Drive AC Specifications
Parameter
Description
LCD frame rate
fLCD
Document Number: 001-56955 Rev. *Y
Conditions
Page 95 of 128
PSoC® 3: CY8C32 Family Data Sheet
11.6 Digital Peripherals
Specifications are valid for –40 °C TA 85 °C and TJ 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,
except where noted.
11.6.1 Timer
The following specifications apply to the Timer/Counter/PWM peripheral in timer mode. Timers can also be implemented in UDBs; for
more information, see the Timer component datasheet in PSoC Creator.
Table 11-33. Timer DC Specifications
Parameter
Description
Block current consumption
Conditions
16-bit timer, at listed input clock
frequency
3 MHz
Min
Typ
Max
Units
–
–
–
µA
–
15
–
µA
12 MHz
–
60
–
µA
50 MHz
–
260
–
µA
Min
Typ
Max
Units
Operating frequency
DC
–
50.01
MHz
Capture pulse width (Internal)
21
–
–
ns
Capture pulse width (external)
42
–
–
ns
Timer resolution
21
–
–
ns
Table 11-34. Timer AC Specifications
Parameter
Description
Conditions
Enable pulse width
21
–
–
ns
Enable pulse width (external)
42
–
–
ns
Reset pulse width
21
–
–
ns
Reset pulse width (external)
42
–
–
ns
11.6.2 Counter
The following specifications apply to the Timer/Counter/PWM peripheral, in counter mode. Counters can also be implemented in
UDBs; for more information, see the Counter component datasheet in PSoC Creator.
Table 11-35. Counter DC Specifications
Parameter
Description
Block current consumption
Conditions
16-bit counter, at listed input clock
frequency
3 MHz
12 MHz
50 MHz
Min
–
Typ
–
Max
–
Units
µA
–
–
–
15
60
260
–
–
–
µA
µA
µA
Min
DC
21
21
21
42
21
42
21
42
Typ
–
–
–
–
–
–
–
–
–
Max
50.01
–
–
–
–
–
–
–
–
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Table 11-36. Counter AC Specifications
Parameter
Description
Operating frequency
Capture pulse
Resolution
Pulse width
Pulse width (external)
Enable pulse width
Enable pulse width (external)
Reset pulse width
Reset pulse width (external)
Document Number: 001-56955 Rev. *Y
Conditions
Page 96 of 128
PSoC® 3: CY8C32 Family Data Sheet
11.6.3 Pulse Width Modulation
The following specifications apply to the Timer/Counter/PWM peripheral, in PWM mode. PWM components can also be implemented
in UDBs; for more information, see the PWM component datasheet in PSoC Creator.
Table 11-37. PWM DC Specifications
Parameter
Description
Block current consumption
Conditions
16-bit PWM, at listed input clock
frequency
Min
Typ
Max
Units
–
–
–
µA
3 MHz
–
15
–
µA
12 MHz
–
60
–
µA
50 MHz
–
260
–
µA
Min
Typ
Max
Units
DC
–
50.01
MHz
Pulse width
21
–
–
ns
Pulse width (external)
42
–
–
ns
Kill pulse width
21
–
–
ns
Kill pulse width (external)
42
–
–
ns
Table 11-38. Pulse Width Modulation (PWM) AC Specifications
Parameter
Description
Conditions
Operating frequency
Enable pulse width
21
–
–
ns
Enable pulse width (external)
42
–
–
ns
Reset pulse width
21
–
–
ns
Reset pulse width (external)
42
–
–
ns
Min
Typ
Max
Units
11.6.4 I2C
Table 11-39. Fixed I2C DC Specifications
Parameter
Description
Block current consumption
Conditions
Enabled, configured for 100 kbps
–
–
250
µA
Enabled, configured for 400 kbps
–
–
260
µA
Wake from sleep mode
–
–
30
µA
Min
Typ
Max
Units
–
–
1
Mbps
Typ
–
Max
200
Table 11-40. Fixed I2C AC Specifications
Parameter
Description
Conditions
Bit rate
11.6.5 Controller Area Network
Table 11-41. CAN DC Specifications[53]
Parameter
Description
Block current consumption
IDD
Conditions
Min
–
Units
µA
Conditions
Min
Typ
Max
Units
–
–
1
Mbit
Table 11-42. CAN AC Specifications[53]
Parameter
Description
Bit rate
Minimum 8 MHz clock
Note
53. Refer to ISO 11898 specification for details.
Document Number: 001-56955 Rev. *Y
Page 97 of 128
PSoC® 3: CY8C32 Family Data Sheet
11.6.6 USB
Table 11-43. USB DC Specifications
Parameter
Min
Typ
Max
Units
USB configured, USB regulator
enabled
4.35
–
5.25
V
VUSB_3.3
USB configured, USB regulator
bypassed
3.15
–
3.6
V
VUSB_3
USB configured, USB regulator
bypassed[54]
2.85
–
3.6
V
IUSB_Configured Device supply current in device active VDDD = 5 V, FCPU = 1.5 MHz
mode, bus clock and IMO = 24 MHz V
DDD = 3.3 V, FCPU = 1.5 MHz
–
10
–
mA
–
8
–
mA
IUSB_Suspended Device supply current in device sleep VDDD = 5 V, connected to USB
mode
host, PICU configured to wake on
USB resume signal
–
0.5
–
mA
VDDD = 5 V, disconnected from
USB host
–
0.3
–
mA
VDDD = 3.3 V, connected to USB
host, PICU configured to wake on
USB resume signal
–
0.5
–
mA
VDDD = 3.3 V, disconnected from
USB host
–
0.3
–
mA
VUSB_5
Description
Device supply (VDDD) for USB
operation
Conditions
11.6.7 Universal Digital Blocks (UDBs)
PSoC Creator provides a library of pre-built and tested standard digital peripherals (UART, SPI, LIN, PRS, CRC, timer, counter, PWM,
AND, OR, and so on) that are mapped to the UDB array. See the component datasheets in PSoC Creator for full AC/DC specifications,
APIs, and example code.
Table 11-44. UDB AC Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
FMAX_TIMER Maximum frequency of 16-bit timer in
a UDB pair
–
–
50.01
MHz
FMAX_ADDER Maximum frequency of 16-bit adder in
a UDB pair
–
–
50.01
MHz
–
–
50.01
MHz
–
–
50.01
MHz
Datapath Performance
FMAX_CRC
Maximum frequency of 16-bit
CRC/PRS in a UDB pair
PLD Performance
FMAX_PLD
Maximum frequency of a two-pass
PLD function in a UDB pair
Clock to Output Performance
tCLK_OUT
Propagation delay for clock in to data 25 °C, VDDD 2.7 V
out, see Figure 11-52 on page 99.
–
20
25
ns
tCLK_OUT
Propagation delay for clock in to data Worst-case placement, routing,
out, see Figure 11-52 on page 99.
and pin selection
–
–
55
ns
Note
54. Rise/fall time matching (TR) not guaranteed, see USB Driver AC Specifications on page 83.
Document Number: 001-56955 Rev. *Y
Page 98 of 128
PSoC® 3: CY8C32 Family Data Sheet
Figure 11-52. Clock to Output Performance
11.7 Memory
Specifications are valid for –40 °C TA 85 °C and TJ 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,
except where noted.
11.7.1 Flash
Table 11-45. Flash DC Specifications
Parameter
Description
Erase and program voltage
Conditions
VDDD pin
Min
Typ
Max
Units
1.71
–
5.5
V
Min
–
–
–
–
–
–
20
Typ
15
10
5
–
–
1.5
–
Max
20
13
7
35
15
2
–
Units
ms
ms
ms
ms
ms
seconds
years
10
–
–
Table 11-46. Flash AC Specifications
Parameter
Description
Row write time (erase + program)
TWRITE
Row erase time
TERASE
Row program time
Bulk erase time (16 KB to 64 KB)
TBULK
Sector erase time (8 KB to 16 KB)
Total device programming time
TPROG
Flash data retention time, retention
period measured from last erase cycle
Conditions
No overhead[55]
Average ambient temp.
TA 55 °C, 100 K erase/program
cycles
Average ambient temp.
TA 85 °C, 10 K erase/program
cycles
Note
55. See PSoC® 3 Device Programming Specifications for a description of a low-overhead method of programming PSoC 3 flash.
Document Number: 001-56955 Rev. *Y
Page 99 of 128
PSoC® 3: CY8C32 Family Data Sheet
11.7.2 EEPROM
Table 11-47. EEPROM DC Specifications
Parameter
Description
Erase and program voltage
Conditions
Min
1.71
Typ
–
Max
5.5
Units
V
Min
–
20
Typ
10
–
Max
20
–
Units
ms
years
20
–
–
10
–
–
Min
Typ
Max
Units
VDDD pin
1.71
–
5.5
V
Conditions
Programmed at 25 °C
Min
1K
Typ
–
Max
–
Programmed at 0 °C to 70 °C
100
–
–
Average ambient temp. TA ≤ 55 °C
Average ambient temp. TA ≤ 85 °C
20
10
–
–
–
–
Units
program/
erase
cycles
program/
erase
cycles
years
years
Conditions
Min
Typ
Max
Units
1.2
–
–
V
Min
Typ
Max
Units
DC
–
50.01
MHz
Table 11-48. EEPROM AC Specifications
Parameter
Description
Conditions
Single row erase/write cycle time
TWRITE
EEPROM data retention time, retention Average ambient temp, TA 25 °C,
period measured from last erase cycle 1M erase/program cycles
Average ambient temp, TA 55 °C,
100 K erase/program cycles
Average ambient temp.
TA 85 °C, 10 K erase/program
cycles
11.7.3 Nonvolatile Latches (NVL))
Table 11-49. NVL DC Specifications
Parameter
Description
Erase and program voltage
Conditions
Table 11-50. NVL AC Specifications
Parameter
Description
NVL endurance
NVL data retention time
11.7.4 SRAM
Table 11-51. SRAM DC Specifications
Parameter
VSRAM
Description
SRAM retention voltage
Table 11-52. SRAM AC Specifications
Parameter
FSRAM
Description
SRAM operating frequency
Document Number: 001-56955 Rev. *Y
Conditions
Page 100 of 128
PSoC® 3: CY8C32 Family Data Sheet
11.7.5 External Memory Interface
Figure 11-53. Asynchronous Write and Read Cycle Timing, No Wait States
Tbus_clock
Bus Clock
EM_Addr
EM_CE
EM_WE
EM_OE
Twr_setup
Trd_hold
Trd_setup
EM_Data
Write Cycle
Read Cycle
Minimum of 4 bus clock cycles between successive EMIF accesses
Table 11-53. Asynchronous Write and Read Timing Specifications[56]
Parameter
Description
Fbus_clock Bus clock
frequency[57]
Tbus_clock Bus clock period[58]
Conditions
Min
Typ
Max
Units
–
–
33
MHz
30.3
–
–
ns
Tbus_clock – 10
–
–
ns
Twr_Setup
Time from EM_data valid to rising edge of
EM_WE and EM_CE
Trd_setup
Time that EM_data must be valid before rising
edge of EM_OE
5
–
–
ns
Trd_hold
Time that EM_data must be valid after rising
edge of EM_OE
5
–
–
ns
Notes
56. Based on device characterization (Not production tested).
57. EMIF signal timings are limited by GPIO frequency limitations. See “GPIO” section on page 76.
58. EMIF output signals are generally synchronized to bus clock, so EMIF signal timings are dependent on bus clock frequency.
Document Number: 001-56955 Rev. *Y
Page 101 of 128
PSoC® 3: CY8C32 Family Data Sheet
Figure 11-54. Synchronous Write and Read Cycle Timing, No Wait States
Tbus_clock
Bus Clock
EM_Clock
EM_Addr
EM_CE
EM_ADSC
EM_WE
EM_OE
Twr_setup
Trd_hold
Trd_setup
EM_Data
Write Cycle
Read Cycle
Minimum of 4 bus clock cycles between successive EMIF accesses
Table 11-54. Synchronous Write and Read Timing Specifications[59]
Parameter
Description
frequency[60]
Fbus_clock
Bus clock
Tbus_clock
Bus clock period[61]
Twr_Setup
Conditions
Min
Typ
Max
Units
–
–
33
MHz
30.3
–
–
ns
Time from EM_data valid to rising edge
of EM_Clock
Tbus_clock – 10
–
–
ns
Trd_setup
Time that EM_data must be valid before
rising edge of EM_OE
5
–
–
ns
Trd_hold
Time that EM_data must be valid after
rising edge of EM_OE
5
–
–
ns
Notes
59. Based on device characterization (Not production tested).
60. EMIF signal timings are limited by GPIO frequency limitations. See “GPIO” section on page 76.
61. EMIF output signals are generally synchronized to bus clock, so EMIF signal timings are dependent on bus clock frequency.
Document Number: 001-56955 Rev. *Y
Page 102 of 128
PSoC® 3: CY8C32 Family Data Sheet
Figure 11-55. Synchronous Read Cycle Timing
Tcp/2
EM_ Clock
Tceld
Tcehd
EM_ CEn
Taddriv
Taddrv
EM_ Addr
Address
Toeld
Toehd
EM_ OEn
Tds
Data
EM_ Data
Tadscld
Tadschd
EM_ ADSCn
Table 11-55. Synchronous Read Cycle Specifications
Parameter
Description
period[62]
Conditions
VDDA 3.3 V
Min
Typ
Max
Units
30.3
–
–
ns
T/2
–
–
ns
T
EMIF clock
Tcp/2
EM_Clock pulse high
Tceld
EM_CEn low to EM_Clock high
5
–
–
ns
Tcehd
EM_Clock high to EM_CEn high
T/2 – 5
–
–
ns
Taddrv
EM_Addr valid to EM_Clock high
Taddriv
EM_Clock high to EM_Addr invalid
Toeld
Toehd
5
–
–
ns
T/2 – 5
–
–
ns
EM_OEn low to EM_Clock high
5
–
–
ns
EM_Clock high to EM_OEn high
T
–
–
ns
Tds
Data valid before EM_OEn high
T + 15
–
–
ns
Tadscld
EM_ADSCn low to EM_Clock high
5
–
–
ns
Tadschd
EM_Clock high to EM_ADSCn high
T/2 – 5
–
–
ns
Note
62. Limited by GPIO output frequency, see Table 11-10 on page 77.
Document Number: 001-56955 Rev. *Y
Page 103 of 128
PSoC® 3: CY8C32 Family Data Sheet
Figure 11-56. Synchronous Write Cycle Timing
Tcp/2
EM_ Clock
Tceld
Tcehd
EM_ CEn
Taddriv
Taddrv
EM_ Addr
Address
Tweld
Twehd
EM_ WEn
Tdh
Tds
Data
EM_ Data
Tadschd
Tadscld
EM_ ADSCn
Table 11-56. Synchronous Write Cycle Specifications
Parameter
Description
Period[63]
Conditions
VDDA 3.3 V
Min
Typ
Max
Units
30.3
–
–
ns
T/2
–
–
ns
T
EMIF clock
Tcp/2
EM_Clock pulse high
Tceld
EM_CEn low to EM_Clock high
5
–
–
ns
Tcehd
EM_Clock high to EM_CEn high
T/2 – 5
–
–
ns
Taddrv
EM_Addr valid to EM_Clock high
5
–
–
ns
Taddriv
EM_Clock high to EM_Addr invalid
T/2 – 5
–
–
ns
Tweld
EM_WEn low to EM_Clock high
5
–
–
ns
Twehd
EM_Clock high to EM_WEn high
T/2 – 5
–
–
ns
Tds
Data valid before EM_Clock high
5
–
–
ns
Tdh
Data invalid after EM_Clock high
T
–
–
ns
Tadscld
EM_ADSCn low to EM_Clock high
5
–
–
ns
Tadschd
EM_Clock high to EM_ADSCn high
T/2 – 5
–
–
ns
Note
63. Limited by GPIO output frequency, see Table 11-10 on page 77.
Document Number: 001-56955 Rev. *Y
Page 104 of 128
PSoC® 3: CY8C32 Family Data Sheet
11.8 PSoC System Resources
Specifications are valid for –40 °C TA 85 °C and TJ 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,
except where noted.
11.8.1 POR with Brown Out
For brown out detect in regulated mode, VDDD and VDDA must be 2.0 V. Brown out detect is not available in externally regulated
mode.
Table 11-57. Precise Low-Voltage Reset (PRES) with Brown Out DC Specifications
Parameter
Description
PRESR
Rising trip voltage
PRESF
Falling trip voltage
Conditions
Factory trim
Min
Typ
Max
Units
1.64
–
1.68
V
1.62
–
1.66
V
Min
Typ
Max
Units
–
–
0.5
µs
–
5
–
V/sec
Min
Typ
Max
Units
1.68
1.89
2.14
2.38
2.62
2.87
3.11
3.35
3.59
3.84
4.08
4.32
4.56
4.83
5.05
5.30
5.57
1.73
1.95
2.20
2.45
2.71
2.95
3.21
3.46
3.70
3.95
4.20
4.45
4.70
4.98
5.21
5.47
5.75
1.77
2.01
2.27
2.53
2.79
3.04
3.31
3.56
3.81
4.07
4.33
4.59
4.84
5.13
5.37
5.63
5.92
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Min
Typ
Max
Units
–
–
1
µs
Table 11-58. Power-on Reset (POR) with Brown Out AC Specifications
Parameter
Description
Conditions
PRES_TR Response time
VDDD/VDDA droop rate
Sleep mode
11.8.2 Voltage Monitors
Table 11-59. Voltage Monitors DC Specifications
Parameter
Description
LVI
Trip voltage
LVI_A/D_SEL[3:0] = 0000b
LVI_A/D_SEL[3:0] = 0001b
LVI_A/D_SEL[3:0] = 0010b
LVI_A/D_SEL[3:0] = 0011b
LVI_A/D_SEL[3:0] = 0100b
LVI_A/D_SEL[3:0] = 0101b
LVI_A/D_SEL[3:0] = 0110b
LVI_A/D_SEL[3:0] = 0111b
LVI_A/D_SEL[3:0] = 1000b
LVI_A/D_SEL[3:0] = 1001b
LVI_A/D_SEL[3:0] = 1010b
LVI_A/D_SEL[3:0] = 1011b
LVI_A/D_SEL[3:0] = 1100b
LVI_A/D_SEL[3:0] = 1101b
LVI_A/D_SEL[3:0] = 1110b
LVI_A/D_SEL[3:0] = 1111b
HVI
Trip voltage
Conditions
Table 11-60. Voltage Monitors AC Specifications
Parameter
Description
Response
time[64]
Conditions
Note
64. Based on device characterization (Not production tested).
Document Number: 001-56955 Rev. *Y
Page 105 of 128
PSoC® 3: CY8C32 Family Data Sheet
11.8.3 Interrupt Controller
Table 11-61. Interrupt Controller AC Specifications
Parameter
Description
Conditions
Delay from interrupt signal input to ISR Includes worse case completion of
code execution from ISR code
longest instruction DIV with 6
cycles
Min
Typ
Max
Units
–
–
25
Tcy CPU
11.8.4 JTAG Interface
Figure 11-57. JTAG Interface Timing
(1/f_TCK)
TCK
T_TDI_setup
T_TDI_hold
TDI
T_TDO_valid
T_TDO_hold
TDO
T_TMS_setup
T_TMS_hold
TMS
Table 11-62. JTAG Interface AC Specifications[65]
Parameter
f_TCK
Description
TCK frequency
Conditions
3.3 V VDDD 5 V
1.71 V VDDD < 3.3 V
T_TDI_setup
TDI setup before TCK high
T_TMS_setup
TMS setup before TCK high
T_TDI_hold
TDI, TMS hold after TCK high
T = 1/f_TCK max
Min
Typ
Max
Units
–
–
14[66]
MHz
–
–
7[66]
MHz
(T/10) – 5
–
–
ns
T/4
–
–
T/4
–
–
T_TDO_valid
TCK low to TDO valid
T = 1/f_TCK max
–
–
2T/5
T_TDO_hold
TDO hold after TCK high
T = 1/f_TCK max
T/4
–
–
Notes
65. Based on device characterization (Not production tested).
66. f_TCK must also be no more than 1/3 CPU clock frequency.
Document Number: 001-56955 Rev. *Y
Page 106 of 128
PSoC® 3: CY8C32 Family Data Sheet
11.8.5 SWD Interface
Figure 11-58. SWD Interface Timing
(1/f_S W D C K )
SW DCK
T _S W D I_setup T_ S W D I_ hold
S W D IO
(P S oC inp ut)
T _S W D O _hold
T _S W D O _ valid
S W D IO
(P S oC outp ut)
Table 11-63. SWD Interface AC Specifications[67]
Parameter
f_SWDCK
Description
SWDCLK frequency
Conditions
3.3 V VDDD 5 V
1.71 V VDDD < 3.3 V
1.71 V VDDD < 3.3 V,
SWD over USBIO pins
T_SWDI_setup SWDIO input setup before SWDCK high T = 1/f_SWDCK max
T_SWDI_hold SWDIO input hold after SWDCK high
T = 1/f_SWDCK max
T_SWDO_valid SWDCK high to SWDIO output
T = 1/f_SWDCK max
Min
–
–
–
Typ
–
–
–
Max
14[68]
7[68]
5.5[68]
Units
MHz
MHz
MHz
T/4
T/4
–
–
–
–
–
–
2T/5
Min
Typ
Max
Units
–
–
33
Mbit
11.8.6 SWV Interface
Table 11-64. SWV Interface AC Specifications[30]
Parameter
Description
Conditions
SWV mode SWV bit rate
11.9 Clocking
Specifications are valid for –40 °C TA 85 °C and TJ 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,
except where noted.
11.9.1 Internal Main Oscillator
Table 11-65. IMO DC Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
With oscillator locking to USB bus
–
–
500
µA
24 MHz – non USB mode
–
–
300
µA
12 MHz
–
–
200
µA
6 MHz
–
–
180
µA
3 MHz
–
–
150
µA
Supply current
24 MHz – USB mode
Notes
67. Based on device characterization (Not production tested).
68. f_SWDCK must also be no more than 1/3 CPU clock frequency.
Document Number: 001-56955 Rev. *Y
Page 107 of 128
PSoC® 3: CY8C32 Family Data Sheet
Figure 11-59. IMO Current vs. Frequency
Table 11-66. IMO AC Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
–4
–
4
%
IMO frequency stability (with factory trim)
24 MHz – Non USB mode
FIMO
24 MHz – USB mode
–0.25
–
0.25
%
12 MHz
–3
–
3
%
6 MHz
–2
–
2
%
3 MHz
–2
–
2
%
–
–
13
µs
F = 24 MHz
–
0.9
–
ns
F = 3 MHz
–
1.6
–
ns
F = 24 MHz
–
0.9
–
ns
F = 3 MHz
–
12
–
ns
Startup
time[69]
With oscillator locking to USB bus
From enable (during normal system
operation)
Jitter (peak to peak)[69]
Jp-p
Jitter (long term)[69]
Jperiod
Figure 11-60. IMO Frequency Variation vs. Temperature
Figure 11-61. IMO Frequency Variation vs. VCC
Note
69. Based on device characterization (Not production tested).
Document Number: 001-56955 Rev. *Y
Page 108 of 128
PSoC® 3: CY8C32 Family Data Sheet
11.9.2 Internal Low-Speed Oscillator
Table 11-67. ILO DC Specifications
Parameter
Description
Operating current
[70]
Conditions
Min
Typ
Max
Units
FOUT = 1 kHz
–
–
1.7
µA
FOUT = 33 kHz
–
–
2.6
µA
FOUT = 100 kHz
–
–
2.6
µA
Power down mode
–
–
15
nA
Min
Typ
Max
Units
–
–
2
ms
100 kHz
45
100
200
kHz
1 kHz
0.5
1
2
kHz
ICC
Leakage current[70]
Table 11-68. ILO AC Specifications
Parameter
Description
Startup time, all frequencies
FILO
Conditions
Turbo mode
ILO frequencies
Figure 11-62. ILO Frequency Variation vs. Temperature
Figure 11-63. ILO Frequency Variation vs. VDD
11.9.3 MHz External Crystal Oscillator
For more information on crystal or ceramic resonator selection for the MHzECO, refer to application note AN54439: PSoC 3 and PSoC
5 External Oscillators..
Table 11-69. MHzECO DC Specifications
Parameter
ICC
Description
Operating
current[71]
Conditions
13.56 MHz crystal
Min
Typ
Max
Units
–
3.8
–
mA
Min
Typ
Max
Units
4
–
25
MHz
Table 11-70. MHzECO AC Specifications
Parameter
F
Description
Crystal frequency range
Conditions
Notes
70. This value is calculated, not measured.
71. Based on device characterization (Not production tested).
Document Number: 001-56955 Rev. *Y
Page 109 of 128
PSoC® 3: CY8C32 Family Data Sheet
11.9.4 kHz External Crystal Oscillator
Table 11-71. kHzECO DC Specifications[72]
Parameter
Description
ICC
Operating current
DL
Drive level
Conditions
Low-power mode; CL = 6 pF
Min
Typ
Max
Units
–
0.25
1.0
µA
–
–
1
µW
Min
Typ
Max
Units
Table 11-72. kHzECO AC Specifications
Parameter
Description
F
Frequency
TON
Startup time
Conditions
High power mode
–
32.768
–
kHz
–
1
–
s
Min
Typ
Max
Units
0
–
33
MHz
11.9.5 External Clock Reference
Table 11-73. External Clock Reference AC Specifications[72]
Parameter
Description
Conditions
External frequency range
Input duty cycle range
Measured at VDDIO/2
30
50
70
%
Input edge rate
VIL to VIH
0.5
–
–
V/ns
Min
Typ
Max
Units
–
200
–
µA
Min
Typ
Max
Units
11.9.6 Phase–Locked Loop
Table 11-74. PLL DC Specifications
Parameter
IDD
Description
PLL operating current
Conditions
In = 3 MHz, Out = 24 MHz
Table 11-75. PLL AC Specifications
Parameter
Fpllin
Description
PLL input
1
–
48
MHz
1
–
3
MHz
PLL output frequency[73]
24
–
50
MHz
Lock time at startup
–
–
250
µs
(rms)[72]
–
–
250
ps
PLL intermediate frequency[74]
Fpllout
Conditions
frequency[73]
Jperiod-rms Jitter
Output of prescaler
Notes
72. Based on device characterization (Not production tested).
73. This specification is guaranteed by testing the PLL across the specified range using the IMO as the source for the PLL.
74. PLL input divider, Q, must be set so that the input frequency is divided down to the intermediate frequency range. Value for Q ranges from 1 to 16.
Document Number: 001-56955 Rev. *Y
Page 110 of 128
PSoC® 3: CY8C32 Family Data Sheet
12. Ordering Information
In addition to the features listed in Table 12-1, every CY8C32 device includes: a precision on-chip voltage reference, precision
oscillators, flash, ECC, DMA, a fixed function I2C, 4 KB trace RAM, JTAG/SWD programming and debug, external memory interface,
and more. In addition to these features, the flexible UDBs and analog subsection support a wide range of peripherals. To assist you
in selecting the ideal part, PSoC Creator makes a part recommendation after you choose the components required by your application.
All CY8C32 derivatives incorporate device and flash security in user-selectable security levels; see the TRM for details.
Table 12-1. CY8C32 Family with Single Cycle 8051
I/O[76]
12-bit Del-Sig
1
2
0
0
–
✔
16
4
–
–
70
62
8
0
100-pin TQFP
0×1E099069
✔
12-bit Del-Sig
1
2
0
0
–
✔
16
4
–
–
46
38
8
0
68-pin QFN
0×1E082069
CY8C3244LTI-123
50
16
2
0.5
✔
12-bit Del-Sig
1
2
0
0
–
✔
16
4
–
–
29
25
4
0
48-pin QFN
0×1E07B069
CY8C3244PVI-133
50
16
2
0.5
✔
12-bit Del-Sig
1
2
0
0
–
✔
16
4
–
–
29
25
4
0
48-pin SSOP
0×1E085069
JTAG ID[77]
USBIO
SIO
GPIO
Total I/O
CAN 2.0b
Package
FS USB
UDBs[75]
✔
0.5
CapSense
0.5
2
DFB
2
16
Opamps
EEPROM (KB)
16
Comparator
SRAM (KB)
50
50
DAC
Flash (KB)
CY8C3244AXI-153
CY8C3244LTI-130
Part Number
ADC
CPU Speed (MHz)
16-bit Timer/PWM
Digital
SC/CT Analog Blocks
Analog
LCD Segment Drive
MCU Core
16 KB Flash
32 KB Flash
CY8C3245AXI-158
50
32
4
1
✔
12-bit Del-Sig
1
2
0
0
–
✔
20
4
–
–
70
62
8
0
100-pin TQFP
0×1E09E069
CY8C3245LTI-163
50
32
4
1
✔
12-bit Del-Sig
1
2
0
0
–
✔
20
4
–
–
46
38
8
0
68-pin QFN
0×1E0A3069
0×1E08B069
CY8C3245LTI-139
50
32
4
1
✔
12-bit Del-Sig
1
2
0
0
–
✔
20
4
–
–
29
25
4
0
48-pin QFN
CY8C3245PVI-134
50
32
4
1
✔
12-bit Del-Sig
1
2
0
0
–
✔
20
4
–
–
29
25
4
0
48-pin SSOP
0×1E086069
CY8C3245AXI-166
50
32
4
1
✔
12-bit Del-Sig
1
2
0
0
–
✔
20
4
✔
–
72
62
8
2
100-pin TQFP
0×1E0A6069
0×1E090069
CY8C3245LTI-144
50
32
4
1
✔
12-bit Del-Sig
1
2
0
0
–
✔
20
4
✔
–
31
25
4
2
48-pin QFN
CY8C3245PVI-150
50
32
4
1
✔
12-bit Del-Sig
1
2
0
0
–
✔
20
4
✔
–
31
25
4
2
48-pin SSOP
0×1E096069
CY8C3245FNI-212
50
32
4
1
✔
12-bit Del-Sig
1
2
0
0
–
✔
20
4
–
–
46
38
8
0
72-pin WLCSP
0x1E0D4069
0×1E095069
64 KB Flash
CY8C3246LTI-149
50
64
8
2
✔
12-bit Del-Sig
1
2
0
0
–
✔
24
4
–
–
46
38
8
0
68-pin QFN
CY8C3246PVI-147
50
64
8
2
✔
12-bit Del-Sig
1
2
0
0
–
✔
24
4
✔
–
31
25
4
2
48-pin SSOP
0×1E093069
CY8C3246AXI-131
50
64
8
2
✔
12-bit Del-Sig
1
2
0
0
–
✔
24
4
–
–
70
62
8
0
100-pin TQFP
0×1E083069
0×1E0A2069
CY8C3246LTI-162
50
64
8
2
✔
12-bit Del-Sig
1
2
0
0
–
✔
24
4
–
–
29
25
4
0
48-pin QFN
CY8C3246PVI-122
50
64
8
2
✔
12-bit Del-Sig
1
2
0
0
–
✔
24
4
–
–
29
25
4
0
48-pin SSOP
0×1E07A069
CY8C3246AXI-138
50
64
8
2
✔
12-bit Del-Sig
1
2
0
0
–
✔
24
4
✔
–
72
62
8
2
100-pin TQFP
0×1E08A069
CY8C3246LTI-128
50
64
8
2
✔
12-bit Del-Sig
1
2
0
0
–
✔
24
4
✔
–
48
38
8
2
68-pin QFN
0×1E080069
CY8C3246LTI-125
50
64
8
2
✔
12-bit Del-Sig
1
2
0
0
–
✔
24
4
✔
–
31
25
4
2
48-pin QFN
0×1E07D069
CY8C3246FNI-213
50
64
8
2
✔
12-bit Del-Sig
1
2
–
–
–
✔
24
4
–
–
46
38
8
–
72-pin WLCSP
0x1E0D5069
Notes
75. UDBs support a wide variety of functionality including SPI, LIN, UART, timer, counter, PWM, PRS, and others. Individual functions may use a fraction of a UDB or
multiple UDBs. Multiple functions can share a single UDB. See the Example Peripherals on page 45 for more information on how UDBs can be used.
76. The I/O Count includes all types of digital I/O: GPIO, SIO, and the two USB I/O. See the I/O System and Routing on page 37 for details on the functionality of each of
these types of I/O.
77. The JTAG ID has three major fields. The most significant nibble (left digit) is the version, followed by a 2 byte part number and a 3 nibble manufacturer ID.
Document Number: 001-56955 Rev. *Y
Page 111 of 128
PSoC® 3: CY8C32 Family Data Sheet
12.1 Part Numbering Conventions
PSoC 3 devices follow the part numbering convention described here. All fields are single character alphanumeric (0, 1, 2, …, 9, A,
B, …, Z) unless stated otherwise.
CY8Cabcdefg-xxx
a: Architecture
ef: Package code
3: PSoC 3
5: PSoC 5
Two character alphanumeric
AX: TQFP
LT: QFN
PV: SSOP
FN: CSP
b: Family group within architecture
2: CY8C32 family
4: CY8C34 family
6: CY8C36 family
8: CY8C38 family
g: Temperature range
C: commercial
I: industrial
A: automotive
c: Speed grade
4: 50 MHz
6: 67 MHz
xxx: Peripheral set
d: Flash capacity
4: 16 KB
5: 32 KB
6: 64 KB
Three character numeric
No meaning is associated with these three characters.
Example
CY8C
3 2 4 6 P V
I
-
x x x
Cypress Prefix
3: PSoC 3
2: CY8C32 Family
Architecture
Family Group within Architecture
4: 50 MHz
Speed Grade
6: 64 KB
Flash Capacity
PV: SSOP
Package Code
I: Industrial
Temperature Range
Peripheral Set
Tape and reel versions of these devices are available and are marked with a "T" at the end of the part number.
All devices in the PSoC 3 CY8C32 family comply to RoHS-6 specifications, demonstrating the commitment by Cypress to lead-free
products. Lead (Pb) is an alloying element in solders that has resulted in environmental concerns due to potential toxicity. Cypress
uses nickel-palladium-gold (NiPdAu) technology for the majority of leadframe-based packages.
A high level review of the Cypress Pb-free position is available on our website. Specific package information is also available. Package
Material Declaration Datasheets (PMDDs) identify all substances contained within Cypress packages. PMDDs also confirm the
absence of many banned substances. The information in the PMDDs will help Cypress customers plan for recycling or other “end of
life” requirements.
Document Number: 001-56955 Rev. *Y
Page 112 of 128
PSoC® 3: CY8C32 Family Data Sheet
13. Packaging
Table 13-1. Package Characteristics
Parameter
Description
Conditions
Min
Typ
Max
Units
TA
Operating ambient temperature
–40
25.00
85
°C
TJ
Operating junction temperature
–40
–
100
°C
TJA
Package JA (48-pin SSOP)
–
49
–
°C/Watt
TJA
Package JA (48-pin QFN)
–
14
–
°C/Watt
TJA
Package JA (68-pin QFN)
–
15
–
°C/Watt
TJA
Package JA (100-pin TQFP)
–
34
–
°C/Watt
TJC
Package JC (48-pin SSOP)
–
24
–
°C/Watt
TJC
Package JC (48-pin QFN)
–
15
–
°C/Watt
TJC
Package JC (68-pin QFN)
–
13
–
°C/Watt
TJC
Package JC (100-pin TQFP)
–
10
–
°C/Watt
TJA
Package JA (72-pin CSP)
–
18
–
°C/Watt
TJC
Package JC (72-pin CSP)
–
0.13
–
°C/Watt
Table 13-2. Solder Reflow Peak Temperature
Package
Maximum Peak
Temperature
Maximum Time at Peak
Temperature
48-pin SSOP
260 °C
30 seconds
48-pin QFN
260 °C
30 seconds
68-pin QFN
260 °C
30 seconds
100-pin TQFP
260 °C
30 seconds
72-pin CSP
260 °C
30 seconds
Table 13-3. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2
Package
MSL
48-pin SSOP
MSL 3
48-pin QFN
MSL 3
68-pin QFN
MSL 3
100-pin TQFP
MSL 3
72-pin CSP
MSL 1
Document Number: 001-56955 Rev. *Y
Page 113 of 128
PSoC® 3: CY8C32 Family Data Sheet
Figure 13-1. 48-pin (300 mil) SSOP Package Outline
51-85061 *F
Figure 13-2. 48-pin QFN Package Outline
001-45616 *E
Document Number: 001-56955 Rev. *Y
Page 114 of 128
PSoC® 3: CY8C32 Family Data Sheet
Figure 13-3. 68-pin QFN 8×8 with 0.4 mm Pitch Package Outline (Sawn Version)
001-09618 *E
Figure 13-4. 100-pin TQFP (14 × 14 × 1.4 mm) Package Outline
51-85048 *J
Document Number: 001-56955 Rev. *Y
Page 115 of 128
PSoC® 3: CY8C32 Family Data Sheet
Figure 13-5. WLCSP Package (4.25 × 4.98 × 0.60 mm)
TOP VIEW
1
2
3
4
5
6
7
SIDE VIEW
8
A
BOTTOM VIEW
8
7
6
5
4
3
2
1
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
J
J
NOTES:
1. JEDEC Publication 95; Design Guide 4.18
2. ALL DIMENSIONS ARE IN MILLIMETERS
Document Number: 001-56955 Rev. *Y
001-82897 **
Page 116 of 128
PSoC® 3: CY8C32 Family Data Sheet
14. Acronyms
Table 14-1. Acronyms Used in this Document (continued)
Acronym
Table 14-1. Acronyms Used in this Document
Acronym
Description
Description
FIR
finite impulse response, see also IIR
FPB
flash patch and breakpoint
FS
full-speed
GPIO
general-purpose input/output, applies to a PSoC
pin
HVI
high-voltage interrupt, see also LVI, LVD
abus
analog local bus
ADC
analog-to-digital converter
AG
analog global
AHB
AMBA (advanced microcontroller bus architecture) high-performance bus, an ARM data
transfer bus
IC
integrated circuit
ALU
arithmetic logic unit
IDAC
current DAC, see also DAC, VDAC
AMUXBUS
analog multiplexer bus
IDE
integrated development environment
API
application programming interface
APSR
application program status register
ARM®
advanced RISC machine, a CPU architecture
ATM
automatic thump mode
BW
bandwidth
CAN
Controller Area Network, a communications
protocol
CMRR
2C,
I
or IIC
Inter-Integrated Circuit, a communications
protocol
IIR
infinite impulse response, see also FIR
ILO
internal low-speed oscillator, see also IMO
IMO
internal main oscillator, see also ILO
INL
integral nonlinearity, see also DNL
I/O
input/output, see also GPIO, DIO, SIO, USBIO
common-mode rejection ratio
IPOR
initial power-on reset
CPU
central processing unit
IPSR
interrupt program status register
CRC
cyclic redundancy check, an error-checking
protocol
IRQ
interrupt request
DAC
digital-to-analog converter, see also IDAC, VDAC
ITM
instrumentation trace macrocell
DFB
digital filter block
LCD
liquid crystal display
DIO
digital input/output, GPIO with only digital
capabilities, no analog. See GPIO.
LIN
Local Interconnect Network, a communications
protocol.
DMA
direct memory access, see also TD
LR
link register
DNL
differential nonlinearity, see also INL
LUT
lookup table
DNU
do not use
LVD
low-voltage detect, see also LVI
DR
port write data registers
LVI
low-voltage interrupt, see also HVI
DSI
digital system interconnect
LVTTL
low-voltage transistor-transistor logic
DWT
data watchpoint and trace
MAC
multiply-accumulate
ECC
error correcting code
MCU
microcontroller unit
ECO
external crystal oscillator
MISO
master-in slave-out
EEPROM
electrically erasable programmable read-only
memory
NC
no connect
NMI
nonmaskable interrupt
NRZ
non-return-to-zero
NVIC
nested vectored interrupt controller
NVL
nonvolatile latch, see also WOL
EMI
electromagnetic interference
EMIF
external memory interface
EOC
end of conversion
EOF
end of frame
EPSR
execution program status register
ESD
electrostatic discharge
ETM
embedded trace macrocell
Document Number: 001-56955 Rev. *Y
opamp
operational amplifier
PAL
programmable array logic, see also PLD
PC
program counter
PCB
printed circuit board
PGA
programmable gain amplifier
Page 117 of 128
PSoC® 3: CY8C32 Family Data Sheet
Table 14-1. Acronyms Used in this Document (continued)
Acronym
Description
Table 14-1. Acronyms Used in this Document (continued)
Acronym
Description
PHUB
peripheral hub
SOF
start of frame
PHY
physical layer
SPI
PICU
port interrupt control unit
Serial Peripheral Interface, a communications
protocol
PLA
programmable logic array
SR
slew rate
PLD
programmable logic device, see also PAL
SRAM
static random access memory
PLL
phase-locked loop
SRES
software reset
PMDD
package material declaration datasheet
SWD
serial wire debug, a test protocol
POR
power-on reset
SWV
single-wire viewer
PRES
precise low-voltage reset
TD
transaction descriptor, see also DMA
PRS
pseudo random sequence
THD
total harmonic distortion
PS
port read data register
TIA
transimpedance amplifier
PSoC®
Programmable System-on-Chip™
TRM
technical reference manual
PSRR
power supply rejection ratio
TTL
transistor-transistor logic
PWM
pulse-width modulator
TX
transmit
RAM
random-access memory
UART
Universal Asynchronous Transmitter Receiver, a
communications protocol
UDB
universal digital block
RISC
reduced-instruction-set computing
RMS
root-mean-square
RTC
real-time clock
RTL
register transfer language
RTR
RX
USB
Universal Serial Bus
USBIO
USB input/output, PSoC pins used to connect to
a USB port
remote transmission request
VDAC
voltage DAC, see also DAC, IDAC
receive
WDT
watchdog timer
SAR
successive approximation register
WOL
write once latch, see also NVL
SC/CT
switched capacitor/continuous time
WRES
watchdog timer reset
2C
serial clock
SCL
I
SDA
I2C serial data
S/H
sample and hold
SINAD
signal to noise and distortion ratio
SIO
special input/output, GPIO with advanced
features. See GPIO.
SOC
start of conversion
Document Number: 001-56955 Rev. *Y
XRES
external reset I/O pin
XTAL
crystal
15. Reference Documents
PSoC® 3, PSoC® 5 Architecture TRM
PSoC® 3 Registers TRM
Page 118 of 128
PSoC® 3: CY8C32 Family Data Sheet
16. Document Conventions
Table 16-1. Units of Measure (continued)
Symbol
16.1 Units of Measure
Table 16-1. Units of Measure
Symbol
Unit of Measure
°C
degrees Celsius
dB
decibels
fF
femtofarads
Hz
hertz
KB
1024 bytes
kbps
kilobits per second
Khr
kilohours
kHz
kilohertz
k
kilohms
ksps
kilosamples per second
LSB
least significant bit
Mbps
megabits per second
MHz
megahertz
M
megaohms
Msps
megasamples per second
µA
microamperes
Document Number: 001-56955 Rev. *Y
Unit of Measure
µF
microfarads
µH
microhenrys
µs
microseconds
µV
microvolts
µW
microwatts
mA
milliamperes
ms
milliseconds
mV
millivolts
nA
nanoamperes
ns
nanoseconds
nV
nanovolts
ohms
pF
picofarads
ppm
parts per million
ps
picoseconds
s
seconds
sps
samples per second
sqrtHz
square root of hertz
V
volts
Page 119 of 128
PSoC® 3: CY8C32 Family Data Sheet
17. Revision History
Description Title: PSoC® 3: CY8C32 Family Data Sheet Programmable System-on-Chip (PSoC®)
Document Number: 001-56955
Submission Orig. of
Revision
ECN
Description of Change
Date
Change
**
2796903
11/04/09
MKEA
New datasheet
*A
2824546
12/09/09
MKEA
Updated I2C section to reflect 1 Mbps. Updated Table 11-6 and 11- 7 (Boost AC
and DC specs); also added Shottky Diode specs. Changed current for
sleep/hibernate mode to include SIO; Added footnote to analog global specs.
Updated Figures 1-1, 6-2, 7-14, and 8-1. Updated Table 6-2 and Table 6-3
(Hibernate and Sleep rows) and Power Modes section. Updated GPIO and SIO
AC specifications. Updated Gain error in IDAC and VDAC specifications. Updated
description of VDDA spec in Table 11-1 and removed GPIO Clamp Current
parameter. Updated number of UDBs on page 1.
Moved FILO from ILO DC to AC table.
Added PCB Layout and PCB Schematic diagrams.
Updated Fgpioout spec (Table 11-9). Added duty cycle frequency in PLL AC spec
table. Added note for Sleep and Hibernate modes and Active Mode specs in Table
11-2. Linked URL in Section 10.3 to PSoC Creator site.
Updated Ja and Jc values in Table 13-1. Updated Single Sample Mode and Fast
FIR Mode sections. Updated Input Resistance specification in Del-Sig ADC table.
Added Tio_init parameter. Updated PGA and UGB AC Specs. Removed SPC
ADC. Updated Boost Converter section.
Added section 'SIO as Comparator'; updated Hysteresis spec (differential mode)
in Table 11-10.
Updated VBAT condition and deleted Vstart parameter in Table 11-6.
Added 'Bytes' column for Tables 4-1 to 4-5.
*B
2873322
02/04/10
MKEA
Changed maximum value of PPOR_TR to '1'. Updated VBIAS specification.
Updated PCB Schematic. Updated Figure 8-1 and Figure 6-3. Updated Interrupt
Vector table, Updated Sales links. Updated JTAG and SWD specifications.
Removed Jp-p and Jperiod from ECO AC Spec table. Added note on sleep timer
in Table 11-2. Updated ILO AC and DC specifications. Added Resolution
parameter in VDAC and IDAC tables. Updated IOUT typical and maximum values.
Changed Temperature Sensor range to –40 °C to +85 °C. Removed Latchup
specification from Table 11-1. Updated DAC details
Document Number: 001-56955 Rev. *Y
Page 120 of 128
PSoC® 3: CY8C32 Family Data Sheet
Description Title: PSoC® 3: CY8C32 Family Data Sheet Programmable System-on-Chip (PSoC®) (continued)
Document Number: 001-56955
Submission Orig. of
Revision
ECN
Description of Change
Date
Change
*C
2903576
04/01/10
MKEA
Updated Vb pin in PCB Schematic.
Updated Tstartup parameter in AC Specifications table.
Added Load regulation and Line regulation parameters to Inductive Boost
Regulator DC Specifications table.
Updated ICC parameter in LCD Direct Drive DC Specs table.
In page 1, updated internal oscillator range under Prescision programmable
clocking to start from 3 MHz.
Updated IOUT parameter in LCD Direct Drive DC Specs table.
Updated Table 6-2 and Table 6-3.
Added bullets on CapSense in page 1; added CapSense column in Section 12
Removed some references to footnote [1].
Changed INC_Rn cycles from 3 to 2 (Table 4-1).
Added footnote in PLL AC Specification table.
Added PLL intermediate frequency row with footnote in PLL AC Specs table.
Added UDBs subsection under 11.6 Digital Peripherals.
Updated Figure 2-6 (PCB Layout).
Updated Pin Descriptions section and modified Figures 6-6, 6-8, 6-9.
Updated LVD in Tables 6-2 and 6-3; modified Low-power modes bullet in page 1.
Added note to Figures 2-5 and 6-2; Updated Figure 6-2 to add capacitors for VDDA
and VDDD pins.
Updated boost converter section (6.2.2).
Updated Tstartup values in Table 11-3.
Removed IPOR rows from Table 11-53. Updated 6.3.1.1, Power Voltage Level
Monitors.
Updated section 5.2 and Table 11-2 to correct suggestion of execution from flash.
Updated IMO max frequency in Figure 6-1, Table 11-63, and Table 11-64.
Updated VREF specs in Table 11-19.
Updated IDAC uncompensated gain error in Table 11-23.
Updated Delay from Interrupt signal input to ISR code execution from ISR code
in Table-71. Removed other line in table.
Added sentence to last paragraph of section 6.1.1.3.
Updated Tresp, high and low-power modes, in Table 11-22.
Updated f_TCK values in Table 11-58 and f_SWDCK values in Table 11-59.
Updated SNR condition in Table 11-18.
Updated sleep wakeup time in Table 6-3 and Tsleep in Table 11-3.
Added 1.71 V <= VDDD < 3.3 V, SWD over USBIO pins value to Table 11-59.
Removed mention of hibernate reset (HRES) from page 1 features, Table 6-3,
Section 6.2.1.4, Section 6.3, and Section 6.3.1.1. Change PPOR/PRES to TBDs
in Section 6.3.1.1, Section 6.4.1.6 (changed PPOR to reset), Table 11-3 (changed
PPOR to PRES), Table 11-53 (changed title, values TBD), and Table 11-54
(changed PPOR_TR to PRES_TR).
Added sentence saying that LVD circuits can generate a reset to Section 6.3.1.1.
Changed IDD values on page 1, page 5, and Table 11-2.
Changed resume time value in Section 6.2.1.3.
Changed ESD HBM value in Table 11-1.
Changed sample rate row in Table 11-18.
Removed VDDA = 1.65 V rows and changed BWag value in Table 11-20.
Changed Vioff values and changed CMRR value in Table 11-21.
Changed INL max value in Table 11-25.
Changed occurrences of “Block” to “Row” and deleted the “ECC not included”
footnote in Table 11-41.
Changed max response time value in Tables 11-54 and 11-56.
Change the Startup time in Table 11-64.
Added condition to intermediate frequency row in Table 11-70.
Added row to Table 11-54.
Added brown out note to Section 11.8.1.
Document Number: 001-56955 Rev. *Y
Page 121 of 128
PSoC® 3: CY8C32 Family Data Sheet
Description Title: PSoC® 3: CY8C32 Family Data Sheet Programmable System-on-Chip (PSoC®) (continued)
Document Number: 001-56955
Submission Orig. of
Revision
ECN
Description of Change
Date
Change
*D
2938381
05/27/10
MKEA
Replaced VDDIO with VDDD in USBIO diagram and specification tables, added text
in USBIO section of Electrical Specifications.
Added Table 13-2 (Package MSL)
Modified Tstorag condition and changed max spec to 100
Added bullet (Pass) under ALU (section 7.2.2.2)
Added figures for kHzECO and MHzECO in the External Oscillator section
Updated Figure 6-1(Clocking Subsystem diagram)
Removed CPUCLK_DIV in table 5-2, Deleted Clock Divider SFR subsection
Updated PSoC Creator Framework image
Updated SIO DC Specifications (VIH and VIL parameters)
Updated bullets in Clocking System and Clocking Distribution sections
Updated Figure 8-2
Updated Table 11-10
Updated PCB Layout and Schematic, updated as per MTRB review comments
Updated Table 6-3 (power changed to current)
In 32kHZ EC DC Specifications table, changed ICC Max to 0.25
In IMO DC Specifications table, updated Supply Current values
Updated GPIO DC Specs table
Modified to support a maximum 50MHz CPU speed
*E
2958674
06/22/10
SHEA
Minor ECN to post datasheet to external website
*F
2989685
08/04/10
MKEA
Added USBIO 22 ohm DP and DM resistors to Simplified Block Diagram
Added to Table 6-6 a footnote and references to same.
Added sentences to the resistive pull-up and pull-down description bullets.
Added sentence to Section 6.4.11, Adjustable Output Level.
Updated section 5.5 External Memory Interface
Updated Table 11-73 JTAG Interface AC Specifications
Updated Table 11-74 SWD Interface AC Specifications
*G
3078568
11/04/10
MKEA
Updated “Current Digital-to-analog Converter (IDAC)” on page 87
Updated “Voltage Digital to Analog Converter (VDAC)” on page 92
Updated Table 11-2, “DC Specifications,” on page 68
*H
3107314 12/10/2010
MKEA
Updated delta-sigma tables and graphs.
Updated Flash AC specs
Formatted table 11.2.
Updated interrupt controller table
Updated transimpedance amplifier section
Updated SIO DC specs table
Updated Voltage Monitors DC Specifications table
Updated LCD Direct Drive DC specs table
Updated ESDHBM value.
Updated IDAC and VDAC sections
Removed ESO parts from ordering information
Changed USBIO pins from NC to DNU and removed redundant USBIO pin
description notes
Updated POR with brown out DC and AC specs
Updated 32 kHz External Crystal DC Specifications
Updated XRES IO specs
Updated Inductive boost regulator section
Delta sigma ADC spec updates
Updated comparator section
Removed buzz mode from Power Mode Transition diagram
*I
3179219
02/22/2011
MKEA
Updated conditions for flash data retention time.
Updated 100-pin TQFP package spec.
Updated EEPROM AC specifications.
Document Number: 001-56955 Rev. *Y
Page 122 of 128
PSoC® 3: CY8C32 Family Data Sheet
Description Title: PSoC® 3: CY8C32 Family Data Sheet Programmable System-on-Chip (PSoC®) (continued)
Document Number: 001-56955
Submission Orig. of
Revision
ECN
Description of Change
Date
Change
*J
3200146
03/28/2011
MKEA
Removed Preliminary status from the data sheet.
Updated JTAG ID
Deleted Cin_G1, ADC input capacitance from Delta-Sigma ADC DC spec table
Updated JTAG Interface AC Specifications and SWD Interface Specifications
tables
Updated USBIO DC specs
Added 0.01 to max speed
Updated Features on page 1
Added Section 5.5, Nonvolatile Latches
Updated Flash AC specs
Updated delta-sigma graphs, noise histogram figures and RMS Noise spec tables
Add reference to application note AN58304 in section 8.1
Updated 100-pin TQFP package spec
Added oscillator, I/O, VDAC, regulator graphs
Updated JTAG/SWD timing diagrams
Updated GPIO and SIO AC specs
Updated POR with Brown Out AC spec table
Updated IDAC graphs
Added DMA timing diagram, interrupt timing and interrupt vector, I2C timing
diagrams
Added full chip performance graphs
Changed MHzECO range.
Added “Solder Reflow Peak Temperature” table.
*K
3259185
05/17/2011
MKEA
Added JTAG and SWD interface connection diagrams
Updated TJA and TJC values in Table 13-1
Changed typ and max values for the TCVos parameter in Opamp DC
specifications table.
Updated Clocking subsystem diagram.
Changed VSSD to VSSB in the PSoC Power System diagram
Updated Ordering information.
Document Number: 001-56955 Rev. *Y
Page 123 of 128
PSoC® 3: CY8C32 Family Data Sheet
Description Title: PSoC® 3: CY8C32 Family Data Sheet Programmable System-on-Chip (PSoC®) (continued)
Document Number: 001-56955
Submission Orig. of
Revision
ECN
Description of Change
Date
Change
*L
3464258
12/14/2011
MKEA
Updated Analog Global specs
Updated IDAC range
Modified VDDIO description in Section 3
Added note on Sleep and Hibernate modes in the Power Modes section
Updated Boost Converter section
Updated conditions for Inductive boost AC specs
Added VDAC/IDAC noise graphs and specs
Added pin capacitance specs for ECO pins
Removed CL from 32 kHz External Crystal DC Specs table.
Added reference to AN54439 in Section 6.1.2.2
Deleted T_SWDO_hold row from the SWD Interface AC Specifications table
Removed Pin 46 connections in “Example Schematic for 100-pin TQFP Part with
Power Connections”
Updated Active Mode IDD description in Table 11-2.
Added IDDDR and IDDAR specs in Table 11-2.
Replaced “total device program time” with TPROG in Flash AC specs table
Added IGPIO, ISIO and IUSBIO specs in Absolute Maximum Ratings
Added conditions to ICC spec in 32 kHz External Crystal DC Specs table.
Updated TCVOS value
Removed Boost Efficiency vs VOUT graph
Updated boost graphs
Updated min value of GPIO input edge rate
Removed 3.4 Mbps in UDBs from I2C section
Updated USBIO Block diagram; added USBIO drive mode description
Updated Analog Interconnect diagram
Changed max IMO startup time to 12 µs
Added note for IIL spec in USBIO DC specs table
Updated GPIO Block diagram
Updated voltage reference specs
Added text explaining power supply ramp up in Section 11-4.
Document Number: 001-56955 Rev. *Y
Page 124 of 128
PSoC® 3: CY8C32 Family Data Sheet
Description Title: PSoC® 3: CY8C32 Family Data Sheet Programmable System-on-Chip (PSoC®) (continued)
Document Number: 001-56955
Submission Orig. of
Revision
ECN
Description of Change
Date
Change
*M
3645908 06/14/2012
MKEA
Added paragraph clarifying that to achieve low hibernate current, you must limit
the frequency of IO input signals.
Revised description of IPOR and clarified PRES term.
Changed footnote to state that all GPIO input voltages - not just analog voltages
- must be less than Vddio.
Updated 100-TQFP package drawing
Clarified description of opamp Iout spec
Changed “compliant with I2C” to “compatible with I2C”
Updated 48-QFN package drawing
Changed reset status register description text to clarify that not all reset sources
are in the register
Updated example PCB layout figure
Removed text stating that FTW is a wakeup source
Changed supply ramp rate spec from 1 V/ns to 0.066 V/µs
Added “based on char” footnote to voltage monitors response time spec
Changed analog global spec descriptions and values
Added spec for ESDhbm for when Vssa and Vssd are separate
Added a statement about support for JTAG programmers and file formats
Changed comparator specs and conditions
Added text describing flash cache, and updated related text
Changed text and added figures describing Vddio source and sink
Added a statement about support for JTAG programmers and file formats.
Changed comparator specs and conditions
Added text on adjustability of buzz frequency
Updated terminology for “master” and “system” clock
Deleted the text “debug operations are possible while the device is reset”
Deleted and updated text regarding SIO performance under certain power ramp
conditions
Removed from boost mention of 22 µH inductors. This included deleting some
graph figures.
Changed DAC high and low speed/power mode descriptions and conditions
Changed IMO startup time spec
Added text on XRES and PRES re-arm times
Added text about usage in externally regulated mode
Updated package diagram spec 001-45616 to *D revision.
Changed supply ramp rate spec from 1 V/ns to 0.066 V/µs
Changed text describing SIO modes for overvoltage tolerance
Added chip Idd specs for active and low-power modes, for multiple voltage,
temperature and usage conditions
Added chip Idd specs for active and low-power modes, for multiple voltage,
temperature and usage conditions
Updated del-sig ADC spec tables, to replace three the instances of “16 bit” with
“12 bit”
*N
3648803 06/18/2012
WKA/
No changes. EROS update.
MKEA
Document Number: 001-56955 Rev. *Y
Page 125 of 128
PSoC® 3: CY8C32 Family Data Sheet
Description Title: PSoC® 3: CY8C32 Family Data Sheet Programmable System-on-Chip (PSoC®) (continued)
Document Number: 001-56955
Submission Orig. of
Revision
ECN
Description of Change
Date
Change
*O
3732521 09/03/2012
MKEA
Replaced IDDDR and IDDAR specs in Table 11-2, “DC Specifications,” on page 68
that were dropped out in
*M revision.
Updated Table 11-19, “12-bit Delta-sigma ADC DC Specifications,” on page 84,
IDD_12 Max value from 1.4 to 1.95 mA
Replaced PSoC® 3 Programming AN62391 with TRM in footnote #55 and Section
Table 9., “Programming, Debug Interfaces, Resources,” on page 62
Removed Figure 11-8 (Efficiency vs Vout)
Removed 62-MHz sub-row in Table 11-2, “DC Specifications,” on page 68
Updated conditions for Storage Temperature in Table 11-1, “Absolute Maximum
Ratings DC Specifications[15],” on page 67
Updated conditions and min values for NVL data retention time in Table 11-50,
“NVL AC Specifications,” on page 100
Updated Table 11-67, “ILO DC Specifications,” on page 109.
Removed the pruned part CY8C3245LTI-129 from the “Ordering Information”
section on page 111.
Updated PSoC 3 boost circuit value throughout the document.
Updated package diagram 51-85061 to *F revision.
*P
3922905 03/06/2013
MKEA
Updated IDD_XX parameters under Table 11-19, “12-bit Delta-sigma ADC DC
Specifications,” on page 84.
Updated I2C section and updated GPIO and SIO DC specification tables.
*Q
4064707 07/18/2013
MKEA
Added USB test ID in Features.
Updated schematic in Section 2..
Added paragraph for device reset warning in Section 5.4.
Added NVL bit for DEBUG_EN in Section 5.5.
Updated UDB PLD array diagram in Section 7.2.1.
Changed Tstartup specs in Section 11.2.1.
Changed GPIO rise and fall time specs in Section 11.4.
Added IMO spec condition: pre-assembly in Section 11.9.1.
Added Appendix for CSP package (preliminary)
*R
4118845
09/10/2013
MKEA
Removed TSTG spec and added note clarifying the maximum storage temperature
range in Table 11-1.
Updated Vos spec conditions and TCVos in Table 11-19.
Updated 100-TQFP package diagram.
*S
4188568
11/14/2013
MKEA
Updated delta-sigma Vos spec conditions.
Added SIO Comparator specifications.
*T
4218210 12/12/2013
MKEA
Integrated 72-pin CSP package information in the datasheet.
*U
4385782 05/21/2014
MKEA
Updated General Description and Features.
Added More Information and PSoC Creator sections.
Updated 100-pin TQFP package diagram.
*V
4708125 03/31/2015
MKEA
Added INL4 and DNL4 specs in VDAC DC specs.
Updated Fig 6-11.
Added second note after Fig 6-4.
Added a reference to Fig 6-1 in Section 6.1.1 and Section 6.1.2
Updated Section 6.2.2.
Added Section 7.7.1.
Updated Boost specifications.
*W
4807497 06/23/2015
MKEA
Added reference to code examples in More Information.
Updated typ value of TWRITE from 2 to 10 in EEPROM AC specs table.
Changed “Device supply for USB operation" to "Device supply (VDDD) for USB
operation" in USB DC Specifications.
Clarified power supply sequencing and margin for VDDA and VDDD.
Updated Serial Wire Debug Interface with limitations of debugging on Port 15.
Updated Section 11.7.5.
Updated Delta-sigma ADC DC Specifications.
Document Number: 001-56955 Rev. *Y
Page 126 of 128
PSoC® 3: CY8C32 Family Data Sheet
Description Title: PSoC® 3: CY8C32 Family Data Sheet Programmable System-on-Chip (PSoC®) (continued)
Document Number: 001-56955
Submission Orig. of
Revision
ECN
Description of Change
Date
Change
*X
4932879 09/24/2015
MKEA
Changed the Regulator Output Capacitor min and max from "-" to 0.9 and 1.1,
respectively.
Added reference to AN54439 in Section 11.9.3.
Added MHz ECO DC specs table.
Removed references to IPOR rearm issues in Section 6.3.1.1.
Table 6-1: Changed DSI Fmax to 33 MHz.
Figure 6-1: Changed External I/O or DSI to 0-33 MHz.
Table 11-10: Changed Fgpioin Max to 33 MHz.
Table 11-12: Changed Fsioin Max to 33 MHz.
*Y
5322536 06/27/2016
MKEA
Updated More Information.
Corrected typos in External Electrical Connections.
Added links to CAD Libraries in Section 2.
Document Number: 001-56955 Rev. *Y
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PSoC® 3: CY8C32 Family Data Sheet
18. Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
Memory
PSoC
Touch Sensing
cypress.com/go/automotive
cypress.com/go/clocks
cypress.com/go/interface
cypress.com/go/powerpsoc
cypress.com/go/memory
cypress.com/go/psoc
cypress.com/go/touch
USB Controllers
Wireless/RF
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Cypress Developer Community
Community | Forums | Blogs | Video | Training
Technical Support
cypress.com/go/support
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2009-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United
States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-56955 Rev. *Y
ARM is a registered trademark, and Keil, and RealView are trademarks, of ARM Limited.
Revised June 27, 2016
Page 128 of 128