EL8171, EL8172 ® Data Sheet March 9, 2006 Micropower, Single Supply, Rail-to-Rail Input-Output Instrumentation Amplifiers The EL8171 and EL8172 are micropower instrumentation amplifiers optimized for operation at 2.9V to 5V single supplies. Inputs and outputs can operate rail-to-rail. As with all instrumentation amplifiers, a pair of inputs provide very high common-mode rejection and are completely independent from a pair of feedback terminals. The feedback terminals allow zero input to be translated to any output offset, including ground. A feedback divider controls the overall gain of the amplifier. The EL8172 is compensated for a gain of 100 or more, and the EL8171 is compensated for a gain of 10 or more. The EL8171 and EL8172 have PMOS input devices that provide sub-nA input bias currents. The amplifiers can be operated from one lithium cell or two Ni-Cd batteries. The EL8171 and EL8172 input range goes from below ground to slightly above positive rail. The output stage swings completely to ground or positive supply - no pull-up or pull-down resistors are needed. FN6293.1 Features • 78µA maximum supply current • Maximum input offset voltage - 300µV (EL8172) - 1000µV (EL8171) • 200pA maximum input bias current • 3µV/°C offset voltage drift • 450kHz -3dB bandwidth (G = 10) • 170kHz -3dB bandwidth (G = 100) • 0.5V/µs slew rate • Single supply operation - Input voltage range is rail-to-rail - Output swings rail-to-rail • Output sources and sinks ±29mA load current • 0.2% gain accuracy • Pb-free plus anneal available (RoHS compliant) Applications Pinout EL8171, EL8172 (8 LD SO) TOP VIEW • Battery- or solar-powered systems • Strain gauges • Current monitors ENABLE 1 IN- 2 + + Σ 8 FB+ IN+ 3 6 OUT VS- 4 5 FB- 1 • Thermocouple amplifiers 7 VS+ CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2005, 2006. All Rights Reserved. All other trademarks mentioned are the property of their respective owners. EL8171, EL8172 Ordering Information PART NUMBER PART MARKING TAPE & REEL PART NUMBER PART MARKING EL8171IS 8171IS - 8 Ld SO MDP0027 EL8172IS 8172IS - 8 Ld SO MDP0027 EL8171IS-T7 8171IS 7” 8 Ld SO MDP0027 EL8172IS-T7 8172IS 7” 8 Ld SO MDP0027 EL8171IS-T13 8171IS 13” 8 Ld SO MDP0027 EL8172IS-T13 8172IS 13” 8 Ld SO MDP0027 EL8171ISZ (See Note) 8171ISZ - 8 Ld SO (Pb-free) MDP0027 EL8172ISZ (See Note) 8172ISZ - 8 Ld SO (Pb-free) MDP0027 EL8171ISZ-T7 (See Note) 8171ISZ 7” 8 Ld SO (Pb-free) MDP0027 EL8172ISZ-T7 (See Note) 8172ISZ 7” 8 Ld SO (Pb-free) MDP0027 EL8171ISZ-T13 (See Note) 8171ISZ 13” 8 Ld SO (Pb-free) MDP0027 EL8172ISZ-T13 (See Note) 8172ISZ 13” 8 Ld SO (Pb-free) MDP0027 PACKAGE PKG. DWG. # TAPE & REEL PACKAGE PKG. DWG. # NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Pin Description EL8171/EL8172 PIN NAME PIN FUNCTION 1 ENABLE Active Low. When pulled up above 2V, the in-amp conserves 3µA disabled supply current and the output is in a high impedance state. An internal pull down defines the ENABLE low when left floating. 2 IN- 3 IN+ Inverting (IN-) and non-inverting (IN+) high impedance input terminals. The input terminals are equivalent to the gate of PMOS transistor. 5 FB- 8 FB+ High impedance feedback terminals. The feedback terminals have a very similar equivalent circuit as the input terminals. The negative feedback (FB-) pin connects to an external resistive network to set the gain of the in-amp. The positive feedback (FB+) pin can be used to shift the DC level of the output or as an output offset. 7 VS+ Positive supply terminal. 4 VS- Negative supply terminal. 6 VOUT Output Voltage. 2 FN6293.1 March 9, 2006 EL8171, EL8172 Absolute Maximum Ratings (TA = 25°C) Supply Voltage, VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V Differential Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5mA Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V VEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5V to VS+ + 0.5V ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3kV Output Short-Circuit Duration . . . . . . . . . . . . . . . . . . . . . . .Indefinite Ambient Operating Temperature . . . . . . . . . . . . . . . .-40°C to +85°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA Electrical Specifications PARAMETER VOS VS+ = +5V, VS- = GND, VCM = 1/2VS+ TA = 25°C, unless otherwise specified. DESCRIPTION Input Offset Voltage CONDITIONS MIN TYP MAX UNIT EL8171 400 1000 µV EL8172 150 300 µV TCVOS Input Offset Voltage Temperature Coefficient Temperature = -40°C to 85°C IOS Input Offset Current 10 200 pA IB Input Bias Current 10 200 pA eN Input Noise Voltage EL8171 3 f = 0.1Hz to 10Hz EL8172 Input Noise Voltage Density EL8171 fo = 1kHz EL8172 µV/°C 10 µVP-P 4 µVP-P 200 nV/√Hz 70 nV/√Hz 25 GΩ RIN Input Resistance VIN Input Voltage Range Guaranteed by CMRR test 0 CMRR Common Mode Rejection Ratio EL8172, VCM = 0V to +5V 80 108 dB EL8171, VCM = 0V to +5V 80 104 dB EL8172, VS = 2.4V to 5V 80 104 dB EL8171, VS = 2.4V to 5V 70 90 dB EL8172, RL = 100kΩ to 2.5V -1.5 +0.3 +1.5 % EL8171, RL = 100kΩ to 2.5V -0.8 +0.2 +0.8 % 0 4 10 mV 0.13 0.25 V PSRR EG VOUT Power Supply Rejection Ratio Gain Error Maximum Voltage Swing Output low, 100kΩ to 2.5V Output low, 1kΩ to 2.5V V Output high, 100kΩ to 2.5V 4.990 4.996 V Output high, 1kΩ to GND 4.75 4.88 V 0.3 0.5 SR Slew Rate RL = 1kΩ to GND -3dB BW -3dB Bandwidth EL8171 EL8172 3 5 0.7 V/µs Gain = 10V/V 450 kHz Gain = 20 210 kHz Gain = 50 66 kHz Gain = 100 33 kHz Gain = 100 172 kHz Gain = 200 70 kHz Gain = 500 25 kHz Gain = 1000 12 kHz FN6293.1 March 9, 2006 EL8171, EL8172 Electrical Specifications PARAMETER VS+ = +5V, VS- = GND, VCM = 1/2VS+ TA = 25°C, unless otherwise specified. (Continued) DESCRIPTION CONDITIONS IS,EN Supply Current, Enabled IS,DIS Supply Current, Disabled VENH Enable Pin for Shut-down VENL Enable Pin for Power-on VS Minimum Supply Voltage IO Output Current into 10Ω to VS/2 EN = VS+ MIN TYP MAX UNIT 40 60 78 µA 1.5 2.9 5 µA 2 V 2.2 0.8 V 2.4 V VS = 5V ±18 ±29 mA VS = 2.9V ±4 ±7.5 mA Typical Performance Curves 70 G=100 G=2000 40 30 G=1000 60 G=20 GAIN (dB) GAIN (dB) G=50 G=10 20 G=5 10 G=500 50 G=200 G=100 40 G=50 30 Vs=5V Vs=5V 20 0 1 10 100 1K 10K 100K 1 1M 10 FIGURE 1. EL8171 FREQUENCY RESPONSE vs CLOSED LOOP GAIN 10K 100K 1M 45 VS=±2.5V 35 MAGNITUDE (dB) VS=±1.25V 15 VS=±1V 10k 100k 1M FREQUENCY (Hz) FIGURE 3. EL8171 FREQUENCY RESPONSE vs SUPPLY VOLTAGE 4 VS=±2.5V 40 20 GAIN (dB) 1K FIGURE 2. EL8172 FREQUENCY RESPONSE vs CLOSED LOOP GAIN 25 10 A =10 V RL=10kΩ CL=10pF 5 R /R =9.08Ω F G RF=178kΩ RG=19.6kΩ 0 100 1k 100 FREQUENCY (Hz) FREQUENCY (Hz) VS=±1V 30 25 VS=±1.25V 20 AV=100 15 R =10kΩ L 10 CL=10pF RF/RG=99.02Ω 5 RF=221kΩ RG=2.23kΩ 0 100 1k 10k 100k 1M FREQUENCY (Hz) FIGURE 4. EL8172 FREQUENCY RESPONSE vs SUPPLY VOLTAGE FN6293.1 March 9, 2006 EL8171, EL8172 Typical Performance Curves (Continued) 30 50 25 CL=100pF 45 20 CL=27pF 15 A =10 10 VV=5V S RL=10kΩ R F/RG=9.08Ω 5 RF=178kΩ RG=19.6kΩ 0 100 1k 10k 100k CL=1000pF MAGNITUDE (dB) MAGNITUDE (dB) CL=47pF 40 CL=820pF 35 A =100 V VS=5V RL=10kΩ 30 R /R =99.02Ω F G RF=221kΩ RG=2.23kΩ 25 100 1k 1M FREQUENCY (Hz) AVERAGE INPUT BIAS CURRENT (pA) AVERAGE INPUT BIAS CURRENT (pA) 25C 25°C 2 0 Vs=2.9V Vs=3.3V Vs=5V 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 COMMON-MODE INPUT VOLTAGE (V) 5 1M -45°C -45C 2 0 Vs=2.9V -2 Vs=3.3V Vs=5V 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 COMMON-MODE INPUT VOLTAGE (V) FIGURE 8. EL8171 AND EL8172 AVERAGE INPUT BIAS CURRENT vs COMMON-MODE INPUT VOLTAGE @ -45°C 100 10 85°C 85C INPUT OFFSET CURRENT (pA) AVERAGE INPUT BIAS CURRENT (pA) 100k 4 -4 -0.5 5.5 FIGURE 7. EL8171 AND EL8172 AVERAGE INPUT BIAS CURRENT vs COMMON-MODE INPUT VOLTAGE @ 25°C 50 Vs=5V 0 -50 -100 -0.5 10k FIGURE 6. EL8172 FREQUENCY RESPONSE vs CLOAD 4 -4 -0.5 CL=390pF FREQUENCY (Hz) FIGURE 5. EL8171 FREQUENCY RESPONSE vs CLOAD -2 CL=2200pF Vs=2.9V 0 Vs=3.3V 0.5 1 1.5 2 2.5 3 3.5 4 4.5 COMMON-MODE INPUT VOLTAGE (V) 5 5.5 FIGURE 9. EL8171 AND EL8172 AVERAGE INPUT BIAS CURRENT vs COMMON-MODE INPUT VOLTAGE @ 85°C 5 Vs=5V 5 0 -5 -10 -0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 COMMON-MODE INPUT VOLTAGE (V) 5 5.5 FIGURE 10. EL8171 AND EL8172 INPUT OFFSET CURRENT vs COMMON-MODE INPUT VOLTAGE FN6293.1 March 9, 2006 EL8171, EL8172 Typical Performance Curves (Continued) 200 25°C 25C INPUT OFFSET VOLTAGE (uV) INPUT OFFSET VOLTAGE (uV) 600 500 400 Vs=5.0V 300 Vs=2.9V 200 Vs=3.3V 100 0 -0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 100 INPUT OFFSET VOLTAGE (uV) INPUT OFFSET VOLTAGE (uV) 0 FIGURE 12. EL8172 INPUT OFFSET VOLTAGE vs COMMONMODE INPUT VOLTAGE @ 25°C 600 -45°C -45C 500 400 Vs=5.0V 300 200 100 Vs=2.9V 0 0.5 1 1.5 2 2.5 Vs=3.3V 3 3.5 4 4.5 5 -45°C -45C 0 Vs=5V -100 -200 Vs=2.9V Vs=3.3V -300 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 5.5 COMMON-MODE INPUT VOLTAGE (V) COMMON-MODE INPUT VOLTAGE (V) FIGURE 13. EL8171 INPUT OFFSET VOLTAGE vs COMMONMODE INPUT VOLTAGE @ -45°C FIGURE 14. EL8172 INPUT OFFSET VOLTAGE vs COMMONMODE INPUT VOLTAGE @ -45°C 800 500 85°C 85C INPUT OFFSET VOLTAGE (uV) INPUT OFFSET VOLTAGE (uV) Vs=3.3V COMMON-MODE INPUT VOLTAGE (V) FIGURE 11. EL8171 INPUT OFFSET VOLTAGE vs COMMONMODE INPUT VOLTAGE @ 25°C 700 600 Vs=2.9V 500 Vs=5.0V Vs=3.3V 400 300 200 -0.5 Vs=2.9V -100 COMMON-MODE INPUT VOLTAGE (V) 0 -0.5 Vs=5V 100 -200 -0.5 5.5 25°C 25C 85°C 85C 400 Vs=5V 300 200 Vs=2.9V Vs=3.3V 5.5 100 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 FIGURE 15. EL8171 INPUT OFFSET VOLTAGE vs COMMONMODE INPUT VOLTAGE @ 85°C FIGURE 16. EL8172 INPUT OFFSET VOLTAGE vs COMMONMODE INPUT VOLTAGE @ 85°C 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 COMMON-MODE INPUT VOLTAGE (V) 6 COMMON-MODE INPUT VOLTAGE (V) FN6293.1 March 9, 2006 EL8171, EL8172 Typical Performance Curves (Continued) 120 120 110 110 100 GAIN=100 90 CMRR (dB) CMRR (dB) 100 80 70 90 80 60 60 50 50 GAIN=10 GAIN=1000 70 GAIN=100 40 40 1 10 100 1K 10K 100K 1 1M 10 1K 10K 100K 1M FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 17. EL8171 CMRR vs FREQUENCY FIGURE 18. EL8172 CMRR vs FREQUENCY 120 100 PSRR+ 100 80 PSRR (dB) PSRR (dB) 100 PSRR60 PSRR+ 80 PSRR- 60 40 1 10 100 1K 10K 100K 40 1M 1 FREQUENCY (Hz) 100 1K 10K 100K 1M FREQUENCY (Hz) FIGURE 19. EL8171 PSRR vs FREQUENCY FIGURE 20. EL8172 PSRR vs FREQUENCY 1K 1000 INPUT VOLTAGE NOISE (nV/√Hz) 1K INPUT VOLTAGE NOISE (nV/√Hz) 10 eN@ 1kHz = 200nV/√Hz 100 10 1K 100 10K FREQUENCY (Hz) FIGURE 21. EL8171 VOLTAGE NOISE SPECTRAL DENSITY 7 eN@ 1kHz = 70nV/√Hz 100 10 10 100 1K 1,000 10K 10,000 FREQUENCY (Hz) FIGURE 22. EL8172 VOLTAGE NOISE SPECTRAL DENSITY FN6293.1 March 9, 2006 EL8171, EL8172 5uV/DIV 1uV/DIV Typical Performance Curves (Continued) 1s/DIV 1s/DIV FIGURE 24. EL8172 0.1Hz to 10Hz INPUT VOLTAGE NOISE (GAIN = 100) FIGURE 23. EL8171 0.1Hz to 10Hz INPUT VOLTAGE NOISE (GAIN = 10) 70 SUPPLY CURRENT (µA) 60 50 40 30 20 10 0 2 2.5 3 3.5 4 4.5 5 5.5 SUPPLY VOLTAGE (V) FIGURE 25. EL8171 AND EL8172 SUPPLY CURRENT vs SUPPLY VOLTAGE JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1 1 909mW 0.8 θ JA = 0.6 SO 11 8 0° C/ W 0.4 0.2 0 JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 0.9 1.2 POWER DISSIPATION (W) POWER DISSIPATION (W) 1.4 0.8 0.7 625mW 0.6 θ 0.5 JA 0.4 =1 SO 8 60 0.3 °C /W 0.2 0.1 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (°C) FIGURE 26. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE 8 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (°C) FIGURE 27. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE FN6293.1 March 9, 2006 EL8171, EL8172 Description of Operation and Application Information Product Description The EL8171 and EL8172 are micropower instrumentation amplifiers (in-amps) which deliver rail-to-rail input amplification and rail-to-rail output swing on a single 2.4V to 5V supply. The EL8171 and EL8172 also deliver excellent DC and AC specifications while consuming only 60µA typical supply current. Because EL8171 and EL8172 provide an independent pair of feedback terminals to set the gain and to adjust the output level, these in-amps achieve high commonmode rejection ratio regardless of the tolerance of the gain setting resistors. The EL8171 is internally compensated for a minimum closed loop gain of 10 or greater, well suited for moderate to high gains. For higher gains, the EL8172 is internally compensated for a minimum gain of 100. An ENABLE pin is used to reduce power consumption, typically 2.9µA, while the instrumentation amplifier is disabled. Input Protection All input and feedback terminals of the EL8171 and EL8172 have internal ESD protection diodes to both positive and negative supply rails, limiting the input voltage to within one diode drop beyond the supply rails. If overdriving the inputs is necessary, the external input current must never exceed 5mA. External series resistor may be used as a protection to limit excessive external voltage and current from damaging the inputs. Input Stage and Input Voltage Range The input terminals (IN+ and IN-) of the EL8171 and EL8172 are single differential pair P-MOSFET devices aided by an Input Range Enhancement Circuit to increase the headroom of operation of the common-mode input voltage. The feedback terminals (FB+ and FB-) also have a similar topology. As a result, the input common-mode voltage range of both the EL8171 and EL8172 is rail-to-rail. These in-amps are able to handle input voltages that are at or slightly beyond the supply and ground making these in-amps well suited for single 5V or 3.3V low voltage supply systems. There is no need then to move the common-mode input of the in-amps to achieve symmetrical input voltage. Output Stage and Output Voltage Range A pair of complementary MOSFET devices drives the output VOUT to within a few mV of the supply rails. At a 100kΩ load, the PMOS sources current and pulls the output up to 4mV below the positive supply, while the NMOS sinks current and pulls the output down to 4mV above the negative supply, or ground in the case of a single supply operation. The current sinking and sourcing capability of the EL8171 and EL8172 are internally limited to 29mA. Gain Setting VIN, the potential difference across IN+ and IN-, is replicated (less the input offset voltage) across FB+ and FB-. The 9 obsession of the EL8171 and EL8172 in-amp is to maintain the differential voltage across FB+ and FB- equal to IN+ and IN-; (FB+ - FB-) = (IN+ - IN-). Consequently, the transfer function can be derived. The gain of the EL8171 and EL8172 is set by two external resistors, the feedback resistor RF, and the gain resistor RG. 2.9V to 5V 7 VIN/2 2 IN+ 3 IN- VIN/2 VCM 5 FB- 1 VS+ + - 8 FB+ + EN_BAR EN 6 EL8171/2 - VOUT VS4 RG RF FIGURE 28. CIRCUIT 1 - GAIN IS BY EXTERNAL RESISTORS RF AND RG R VOUT = 1 + -------F- VIN R G In Figure 28, the FB+ pin and one end of resistor RG are connected to GND. With this configuration, the above gain equation is only true for a positive swing in VIN; negative input swings will be ignored and the output will be at ground. Reference Connection Unlike a three-opamp instrumentation amplifier, a finite series resistance seen at the REF terminal does not degrade the EL8171 and EL8172's high CMRR performance eliminating the need for an additional external buffer amplifier. Circuit 2 (Figure 29) uses the FB+ pin to provide a high impedance REF terminal. 2.9V to 5V 7 VIN/2 2 IN+ 3 IN- VIN/2 8 FB+ VCM 5 FB- 2.9V to 5V VS+ + + EN_BAR 1 EL8171/2 - EN 6 VOUT VS4 R1 REF R2 RG RF FIGURE 29. CIRCUIT 2 - GAIN SETTING AND REFERENCE CONNECTION RF R VOUT = 1 + ------- ( VIN ) + 1 + -------F- ( VREF ) R G R G FN6293.1 March 9, 2006 EL8171, EL8172 The FB+ pin is used as a REF terminal to center or to adjust the output. Because the FB+ pin is a high impedance input, an economical resistor divider can be used to set the voltage at the REF terminal without degrading or affecting the CMRR performance. Any voltage applied to the REF terminal will shift VOUT by VREF times the closed loop gain, which is set by resistors RF and RG. See Circuit 2 (Figure 29). error due to the tolerance of the resistors used. The resulting non-ideal transfer function effectively becomes: The FB+ pin can also be connected to the other end of resistor, RG. See Circuit 3 (Figure 30). Keeping the basic concept that the EL8171 and EL8172 in-amps maintain constant differential voltage across the input terminals and feedback terminals (IN+ - IN- = FB+ - FB-), the transfer function of Circuit 3 can be derived. ERG = Tolerance of RG 2.9V to 5V 7 VIN/2 2 IN+ 3 IN- VIN/2 8 FB+ VCM 5 FB- 1 VS+ + + EN_BAR Where: ERF = Tolerance of RF EG = Gain Error of the EL8171 or EL8172 The term [1-(ERG +ERF +EG)] is the deviation from the theoretical gain. Thus, (ERG +ERF +EG) is the total gain error. For example, if 1% resistors are used for the EL8171, the total gain error would be: = ± ( E RG + E RF + E G ( typical ) ) EN = ± ( 0.01 + 0.01 + 0.003 ) EL8171/2 - 6 VOUT VS4 RG R VOUT = 1 + -------F- × [ 1 – ( E RG + E RF + E G ) ] × VIN R G RF VREF FIGURE 30. CIRCUIT 3 - REFERENCE CONNECTION WITH AN AVAILABLE VREF = ± 2.3% Disable/Power-Down The EL8171 and EL8172 can be powered down reducing the supply current to typically 2.9µA. When disabled, the output is in a high impedance state. The active low ENABLE bar pin has an internal pull down and hence can be left floating and the in-amp enabled by default. When the ENABLE bar is connected to an external logic, the in-amp will power down when ENABLE bar is pulled above 2V, and will power on when ENABLE bar is pulled below 0.8V. R VOUT = 1 + -------F- ( VIN ) + ( VREF ) R G A finite resistance Rs in series with the VREF source, adds an output offset of VIN*(RS/RG). As the series resistance Rs approaches zero, the gain equation is simplified to the above equation for Circuit 3. VOUT is simply shifted by an amount VREF. External Resistor Mismatches Because of the independent pair of feedback terminals provided by the EL8171 and EL8172, the CMRR is not degraded by any resistor mismatches. Hence, unlike a three opamp and especially a two opamp in-amp, the EL8171 and EL8172 reduce the cost of external components by allowing the use of 1% or more tolerance resistors without sacrificing CMRR performance. The EL8171 and EL8172 CMRR will be 108dB regardless of the tolerance of the resistors used. Gain Error and Accuracy The EL8172 has a Gain Error, EG, of 0.2% typical. The EL8171 has an EG of 0.3% typical. The gain error indicated in the electrical specifications table is the inherent gain error of the EL8171 and EL8172 and does not include the gain error contributed by the resistors. There is an additional gain 10 FN6293.1 March 9, 2006 EL8171, EL8172 Package Outline Drawing NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil website at http://www.intersil.com/design/packages/index.asp All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 11 FN6293.1 March 9, 2006