Harris DG200AK/883B Cmos dual/quad spst analog switch Datasheet

DG200, DG201
S E M I C O N D U C T O R
CMOS Dual/Quad SPST Analog Switches
December 1993
Features
Description
• Switches Greater than 28VP-P Signals with ±15 Supplies
The DG200 and DG201 solid state analog gates are
designed using an improved, high voltage CMOS monolithic
technology. They provide ease-of-use and performance
advantages not previously available from solid state
switches. Destructive latch-up of solid state analog gates
has been eliminated by Harris's CMOS technology.
• Break-Before-Make Switching tOFF 250ns, tON 700ns
Typical
• TTL, DTL, CMOS, PMOS Compatible
• Non-Latching with Supply Turn-Off
The DG200 and DG201 are completely specification and
pinout compatible with the industry standard devices.
• Complete Monolithic Construction
• Industry Standard (DG200, DG201)
Ordering Information
Applications
• Data Acquisition
• Sample and Hold Circuits
• Operational Amplifier Gain Switching Networks
PART NUMBER
TEMPERATURE
DG200AA
-55oC
DG200AK
-55oC
DG200BA
-25oC
DG200BK
-25oC to +85oC
DG200CJ
0oC
PACKAGE
to
+125oC
10 Pin Metal Can
to
+125oC
14 Lead Ceramic DIP
to
+85oC
10 Pin Metal Can
14 Lead Ceramic DIP
to
+70oC
14 Lead Plastic DIP
to
+125oC
10 Pin Metal Can
to
+125oC
14 Lead Ceramic DIP
DG200AA/883B
-55oC
DG200AK/883B
-55oC
DG201AK
-55oC to +125oC
16 Lead Ceramic DIP
DG201BK
-25oC
16 Lead Ceramic DIP
DG201CJ
0oC
DG201AK/883B
-55oC
to
+85oC
to
+70oC
16 Lead Plastic DIP
to
+125oC
16 Lead Ceramic DIP
Pinouts
DG200
(CDIP, PDIP)
TOP VIEW
DG200
(TO-100 METAL CAN)
TOP VIEW
DG201
(CDIP, PDIP)
TOP VIEW
V+
(SUBSTRATE AND CASE)
IN2 1
14 IN1
NC 2
13 NC
GND 3
12 V+ (SUBSTRATE)
IN1
IN2
10
1
9
2
S1
8
D1
IN1 1
16 IN2
D1
2
15 D2
S1
3
14 S2
V- 4
NC 4
11 NC
S2 5
10 S1
D2 6
9 D1
GND
V- 7
8 VREF
3
S2
7
4
6
5
D2
V-
VREF
GND 5
© Harris Corporation 1993
9-13
12 VREF
S4
6
11 S3
D4
7
10 D3
IN4 8
9 IN3
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper I.C. Handling Procedures.
Copyright
13 V+(SUBSTRATE)
File Number
3115
DG200, DG201
Schematic Diagram
(1/2 DG200, 1/4 DG201)
V+
V-
Q3
Q7
Q5
Q14
Q15
Q8
V+
Q1
VREF
Q10
Q12
Q13
Q2
Q9
GATE
PROTECTION
RESISTOR
Q11
S1
Q4
Q6
V-
INPUT
Functional Diagram
S
IN
P
N
D
DG200, DG201 SWITCH CELL
9-14
D1
Specifications DG200
Absolute Maximum Ratings
Thermal Information
V+, V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <36V
V+ - VD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <30V
VD - V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <30V
VD - VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <28V
VIN - GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <20V
Storage Temperature Range . . . . . . . . . . . . . . . . . -65oC to +150oC
Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300oC
Thermal Resistance
θJA
θJC
Ceramic DIP Package . . . . . . . . . . . . . . .
95oC/W
24oC/W
Plastic DIP Package . . . . . . . . . . . . . . . . 100oC/W
Metal Can Package . . . . . . . . . . . . . . . . . 136oC/W 65oC/W
Operating Temperature Range
“A” Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
“B” Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25oC to +85oC
“C” Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to +70oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications
(TA = +25oC, V+ = +15V, V- = -15V)
MILITARY
COMMERCIAL / INDUSTRIAL
-55oC
+25oC
+125oC
0oC TO
-25oC
+25oC
+70oC TO
+85oC
UNITS
VIN = 0.8V (Notes 2, 3)
±10
±1
±10
-
±10
±10
µA
Input Logic Current,
IN(OFF)
VIN = 2.4V (Notes 2, 3)
±10
±1
±10
-
±10
±10
µA
Drain-Source On Resistance, rDS(ON)
IS = 10mA, VANALOG =
±10V
70
70
100
80
80
100
Ω
Channel-to-Channel
rDS(ON) Match, rDS(ON)
-
25 (Typ)
-
-
30 (Typ)
-
Ω
Minimum Analog Signal
Handling Capability,
VANALOG
-
±15V
-
-
±15V
-
V
PARAMETER
TEST CONDITIONS
Input Logic Current,
IIN(ON)
Switch OFF Leakage
Current, ID(OFF)
VANALOG = -14V to +14V
-
±2
100
-
±5
100
nA
Switch OFF Leakage
Current, IS(OFF)
VANALOG = -14V to +14V
-
±2
100
-
±5
100
nA
Switch ON Leakage Cur- VD = VS = -14V to +14V
rent, ID(ON) + IS(ON)
-
±2
200
-
±10
200
nA
Switch “ON” Time
(Note 1), tON
RL = 1kΩ, VANALOG =
-10V to +10V (Figure 5)
-
1.0
-
-
1.0
-
µs
Switch “OFF” Time, tOFF
RL = 1kΩ, VANALOG =
-10V to +10V (Figure 5)
-
0.5
-
-
0.5
-
µs
Charge Injection, Q(INJ.)
Figure 6
-
15 (Typ)
-
-
20 (Typ)
-
mV
Minimum Off Isolation
Rejection Ratio, OIRR
f = 1MHz, RL = 100Ω,
CL ≤ 5pF
(Figure 7, Note 1)
-
54 (Typ)
-
-
50 (Typ)
-
dB
+Power Supply
Quiescent Current, IV1
VIN = 0V or VIN = 5V
1000
1000
2000
1000
1000
2000
µA
1000
1000
2000
1000
1000
2000
µA
-
54 (Typ)
-
-
50 (Typ)
-
dB
-Power Supply
Quiescent Current, IV2
Minimum Channel to
Channel Cross Coupling
Rejection Ratio, CCRR
One Channel Off
NOTES:
1. Pull Down Resistor must be ≤ 2kΩ.
2. Typical values are for design aid only, not guaranteed and not subject to production testing.
3. All channels are turned off by high “1” logic inputs and all channels are turned on by low “0” inputs; however 0.8V to 2.4V describes the
minimum range for switching properly. Peak input current required for transition is typically -120µA.
9-15
Specifications DG201
Absolute Maximum Ratings
Thermal Information
V+ to V-. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <36V
V+ to VD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <30V
VD to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <30V
VD to VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <28V
VREF to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <33V
VREF to VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <30V
VREF to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <20V
VIN to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <20V
Current (Any Terminal) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <30mA
Storage Temperature Range . . . . . . . . . . . . . . . . . -65oC to +150oC
Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300oC
Thermal Resistance
θJA
θJC
Ceramic DIP Package . . . . . . . . . . . . . . .
80oC/W
24oC/W
Plastic DIP Package . . . . . . . . . . . . . . . . 145oC/W
Operating Temperature Range
“A” Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
“B” Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25oC to +85oC
“C” Suffix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to +70oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Electrical Specifications
(TA = +25oC, V+ = +15V, V- = -15V)
MILITARY
PARAMETER
TEST CONDITIONS
COMMERCIAL / INDUSTRIAL
-55oC
+25oC
+125oC
0oC TO
-25oC
+25oC
+70oC TO
+85oC
UNITS
Input Logic Current,
IIN(ON)
VIN = 0.8V (Note 1)
10
±1
10
±1
±1
10
µA
Input Logic Current,
IN(OFF)
VIN = 2.4V (Note 1)
10
±1
10
±1
±1
10
µA
Drain-Source On Resistance, rDS(ON)
IS = 10mA, VANALOG =
±10V
80
80
125
100
100
125
Ω
Channel-to-Channel
rDS(ON) Match, rDS(ON)
-
25 (Typ)
-
-
30 (Typ)
-
Ω
Minimum Analog Signal
Handling Capability,
VANALOG
-
±15 (Typ)
-
-
±15 (Typ)
-
V
Switch OFF Leakage
Current, ID(OFF)
VANALOG = -14V to +14V
-
±1
100
-
±5
100
nA
Switch OFF Leakage
Current, IS(OFF)
VANALOG = -14V to +14V
-
±1
100
-
±5
100
nA
Switch ON Leakage Cur- VD = VS = -14V to +14V
rent, ID(ON) + IS(ON)
-
±2
200
-
±5
200
nA
Switch “ON” Time
(Note 2), tON
RL = 1kΩ, VANALOG =
-10V to +10V (Figure 5)
-
1.0
-
-
1.0
-
µs
Switch “OFF” Time
(Note 2), tOFF
RL = 1kΩ, VANALOG =
-10V to +10V (Figure 5)
-
0.5
-
-
0.5
-
µs
Charge Injection, Q(INJ.)
Figure 6
-
15 (Typ)
-
-
20 (Typ)
-
mV
Minimum Off Isolation
Rejection Ratio, OIRR
f = 1MHz, RL = 100Ω,
CL ≤ 5pF, (Figure 7)
-
54 (Typ)
-
-
50 (Typ)
-
dB
+Power Supply
Quiescent Current, I+Q
VIN = 0V or VIN = 5V
2000
1000
2000
2000
1000
2000
µA
2000
1000
2000
2000
1000
2000
µA
-
54 (Typ)
-
-
50 (Typ)
-
dB
-Power Supply
Quiescent Current, I-Q
Minimum Channel to
Channel Cross Coupling
Rejection Ratio, CCRR
One Channel Off
NOTES:
1. Typical values are for design aid only, not guaranteed and not subject to production testing.
2. All channels are turned off by high “1” logic inputs and all channels are turned on by low “0” inputs; however 0.8V to 2.4V describes the
minimum range for switching properly. Peak input current required for transition is typically -120µA.
9-16
DG200, DG201
V+ = +15V
V- = -15V
DRAIN SOURCE ON RESISTANCE (Ω)
DRAIN SOURCE ON RESISTANCE (Ω)
Performance Curves
100
+125oC
50
+25oC
-55oC
0
-15
-10
-5
0
5
DRAIN VOLTAGE (V)
10
SOURCE OR DRAIN OFF LEAKAGE CURRENT (nA)
CHANNEL ON LEAKAGE CURRENT (nA)
1
0.1
0.01
65
85
TEMPERATURE (oC)
105
C
B
50
A
A:
B:
C:
D:
-10
V+ = +15V, V- = -15V
V+ = +12V, V- = -12V
V+ = +10V, V- = -10V
V+ = +8V, V- = -8V
-5
0
5
DRAIN VOLTAGE (V)
10
15
FIGURE 2. rDS(ON) vs VD AND POWER SUPPLY VOLTAGE
10
45
D
0
-15
15
FIGURE 1. RDS(ON) vs VD AND TEMPERATURE
25
100
125
FIGURE 3. ID(ON) vs TEMPERATURE
10
1
0.1
0.01
25
45
65
85
TEMPERATURE (oC)
105
125
FIGURE 4. IS(OFF) OR ID(OFF) vs TEMPERATURE
Pin Description
DG201 (16 LEAD DIP)
DG200 (14 LEAD DIP)
PIN
SYMBOL
PIN
SYMBOL
1
IN2
Logic control for switch 2
1
IN1
Logic control for switch 1
2
NC
No Connection
2
D1
Drain (output) terminal for switch 1
3
GND
Ground Terminal (Logic Common)
3
S1
Source (input) terminal for switch 1
4
NC
No Connection
4
V-
Negative power supply terminal
5
S2
Source (input) terminal for switch 2
5
GND
6
D2
Drain (output) terminal for switch 2
6
S4
Source (input) terminal for switch 4
7
V-
Negative power supply terminal
7
D4
Drain (output) terminal for switch 4
8
VREF
Logic reference voltage
8
IN4
Logic control for switch 4
9
D1
Drain (output) terminal for switch 1
9
IN3
Logic control for switch 3
D3
Drain (output) terminal for switch 3
Source (input) terminal for switch 3
DESCRIPTION
DESCRIPTION
Ground terminal (Logic Common)
10
S1
Source (input) terminal for switch 1
10
11
NC
No Connection
11
S3
12
V+
Positive power supply terminal (substrate)
12
VREF
V+
Positive power supply terminal (substrate)
Logic reference voltage
13
NC
No Connection
13
14
IN1
Source (input) terminal for switch 1
14
S2
Source (input) terminal for switch 2
15
D2
Drain (output) terminal for switch 2
16
IN2
Logic control for switch 2
9-17
DG200, DG201
Test Circuits
ANALOG
INPUT 10V
ANALOG
INPUT 10V
3V
0V
VOUT
LOGIC
INPUT
≤2kΩ
3V
1kΩ
10pF
0V
VOUT
LOGIC
INPUT
NOTE: All channels are turned off by high “1” logic inputs and
all channels are turned on by low “0” inputs; however 0.8V to
2.4V describes the minimum range for switching properly.
Peak input current required for transition is typically -120µA.
10,000pF
FIGURE 5.
FIGURE 6.
2VP-P AT 1MHz
LOGIC
INPUT *
51Ω
VOUT
100Ω
* Pull Down Resistor must be ≤ 2kΩ.
FIGURE 7.
Typical Applications
Using the VREF Terminal
The DG200 and DG201 have an internal voltage divider setting the TTL threshold on the input control lines for V+ equal
to +15V. The schematic shown in Figure 8 with nominal
resistor values, gives approximately 2.4V on the VREF pin.
As the TTL input signal goes from +0.8V to +2.4V, Q1 and
Q2 switch states to turn the switch ON and OFF.
V+ (+15V)
If the power supply voltage is less than +15V, then a resistor
must be added between V+ and the VREF pin, to restore
+2.4V at VREF. The table shows the value of this resistor for
various supply voltages, to maintain TTL compatibility. If
CMOS logic levels on a +5V supply are being used, the
threshold shifts are less critical, but a separate column of
suitable values is given in the table. For logic swings of -5V
to + 5V, no resistor is needed.
In general, the “low” logic level should be <0.8V to prevent
Q1 and Q2 from both being ON together (this will cause
incorrect switch function).
TABLE 1.
31kΩ
REXT
TTL RESISTOR
(kΩ)
CMOS RESISTOR
(kΩ)
+15
-
-
+12
100
-
V+ SUPPLY (V)
VREF
Q1
6kΩ
Q2
GATE
PROTECTION
RESISTOR
INPUT
FIGURE 8.
9-18
+10
51
-
+9
(34)
34
+8
(27)
27
+7
18
18
DG200
Metallization Topology
DIE DIMENSIONS:
74 x 77 x 14 ± 1mils
METALLIZATION:
Type: Al
Thickness: 10kÅ ± 1kÅ
GLASSIVATION:
Type: SiO2/Si3N4
SiO2 Thickness: 7kÅ ± 1.4kÅ
Si3N4 Thickness: 8kÅ ± 1.2kÅ
WORST CASE CURRENT DENSITY:
1 x 105 A/cm2
Metallization Mask Layout
DG200
D1
V-
D2
(9)
(7)
(6)
S1 (10)
(5) S2
V- (SUBSTRATE)* (12)
(14)
IN1
(1)
IN2
(3)
GND
* Backside of Chip is V+
9-19
DG201
Metallization Topology
DIE DIMENSIONS:
94 x 101 x 14 ± 1mils
METALLIZATION:
Type: Al
Thickness: 10kÅ ± 1kÅ
GLASSIVATION:
Type: SiO2/Si3N4
SiO2 Thickness: 7kÅ ± 1.4kÅ
Si3N4 Thickness: 8kÅ ± 1.2kÅ
WORST CASE CURRENT DENSITY:
1 x 105 A/cm2
Metallization Mask Layout
DG201
D1
IN1
IN2
D2
(2)
(1)
(16)
(15)
S1 (3)
(14) S2
V- (4)
(13) V+ (SUBSTRATE)*
GND (5)
S4 (6)
(11) S3
(7)
D4
(8)
IN4
(9)
IN3
(10)
D3
* Backside of Chip is V+
9-20
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