AMD A400DB90VF 4 megabit (512 k x 8-bit/256 k x 16-bit) cmos 1.8 volt-only super low voltage flash memory Datasheet

Am29SL400D
Data Sheet
July 2003
The following document specifies Spansion memory products that are now offered by both Advanced
Micro Devices and Fujitsu. Although the document is marked with the name of the company that originally developed the specification, these products will be offered to customers of both AMD and
Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal datasheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appropriate,
and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order
these products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion
memory solutions.
Publication Number Am29SL400D Revision A
Amendment +1 Issue Date April 13, 2005
THIS PAGE LEFT INTENTIONALLY BLANK.
ADVANCE INFORMATION
Am29SL400D
4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS 1.8 Volt-only Super
Low Voltage Flash Memory
DISTINCTIVE CHARACTERISTICS
■ Single power supply operation
— 1.65 to 1.95 V for read, program, and erase
operations
— Ideal for battery-powered applications
■ Manufactured on 0.23 µm process technology
■ High performance
— Access times as fast as 90 ns
■ Ultra low power consumption (typical values at
5 MHz)
— 0.2 µA Automatic Sleep Mode current
— 0.2 µA standby mode current
■ Unlock Bypass Program Command
— Reduces overall programming time when
issuing multiple program command sequences
■ Top or bottom boot block configurations
available
■ Minimum 1,000,000 erase cycle guarantee per
sector
■ 20-year data retention at 125°C
■ Package option
— 48-ball FBGA
■ Compatibility with JEDEC standards
— 5 mA read current
— 15 mA program/erase current
■ Flexible sector architecture
— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and
seven 64 Kbyte sectors (byte mode)
— One 8 Kword, two 4 Kword, one 16 Kword, and
seven 32 Kword sectors (word mode)
— Pinout and software compatible with
single-power supply Flash
— Superior inadvertent write protection
■ Data# Polling and toggle bits
— Provides a software method of detecting
program or erase operation completion
■ Ready/Busy# pin (RY/BY#)
— Supports full chip erase
— Sector Protection features:
A hardware method of locking a sector to
prevent any program or erase operations within
that sector
Sectors can be locked in-system or via
programming equipment
Temporary Sector Unprotect feature allows code
changes in previously locked sectors
— Provides a hardware method of detecting
program or erase cycle completion
■ Erase Suspend/Erase Resume
— Suspends an erase operation to read data from,
or program data to, a sector that is not being
erased, then resumes the erase operation
■ Hardware reset pin (RESET#)
— Hardware method to reset the device to reading
array data
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
Pubication Am29SL400D Revision A Amendment +1
Issue Date: April 13, 2005
Visit www.amd.com for the latest information.
A D V A N C E
I N F O R M A T I O N
GENERAL DESCRIPTION
The Am29SL400D is an 4Mbit, 1.8 V volt-only Flash
memory organized as 524,288 bytes or 262,144 words.
The device is offered in a 48-ball FBGA package. The
word-wide data (x16) appears on DQ15–DQ0; the
byte-wide (x8) data appears on DQ7–DQ0. This device
is designed to be programmed and erased in-system
with a single 1.8 volt VCC supply. No VPP is required for
write or erase operations. The device can also be programmed in standard EPROM programmers.
The standard device offers access times of 90, 100,
and 120 ns, allowing high speed microprocessors to
operate without wait states. To eliminate bus contention
the device has separate chip enable (CE#), write
enable (WE#) and output enable (OE#) controls.
The device requires only a single 1.8 volt power
supply for both read and write functions. Internally
generated and regulated voltages are provided for the
program and erase operations.
The device is entirely command set compatible with the
JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents
serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles
also internally latch addresses and data needed for the
programming and erase operations. Reading data out
of the device is similar to reading from other Flash or
EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that automatically times the program pulse widths and verifies
proper cell margin. The Unlock Bypass mode facilitates faster programming times by requiring only two
write cycles to program data instead of four.
Device erasure occurs by executing the erase
command sequence. This initiates the Embedded
Erase algorithm—an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation.
During erase, the device automatically times the erase
pulse widths and verifies proper cell margin.
2
The host system can detect whether a program or
erase operation is complete by observing the RY/BY#
pin, or by reading the DQ7 (Data# Polling) and DQ6
(toggle) status bits. After a program or erase cycle has
been completed, the device is ready to read array data
or accept another command.
The sector erase architecture allows memory sectors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures include a low
VCC detector that automatically inhibits write operations during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of the sectors of
memory. This can be achieved in-system or via programming equipment.
The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure. True background erase can thus be achieved.
The hardware RESET# pin terminates any operation
in progress and resets the internal state machine to
reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memory.
The device offers two power-saving features. When
addresses have been stable for a specified amount of
time, the device enters the automatic sleep mode.
The system can also place the device into the standby
mode. Power consumption is greatly reduced in both
these modes.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effectiveness.
The device electrically erases all bits within a sector
simultaneously via Fowler-Nordheim tunneling. The
data is programmed using hot electron injection.
Am29SL400D
Rev. A Amend. +1 April 13, 2005
A D V A N C E
I N F O R M A T I O N
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Special Handling Instructions for FBGA Packages .................. 5
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 7
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 8
Table 1. Am29SL400D Device Bus Operations ................................8
Word/Byte Configuration .......................................................... 8
Requirements for Reading Array Data ..................................... 8
Writing Commands/Command Sequences .............................. 9
Program and Erase Operation Status ...................................... 9
Standby Mode .......................................................................... 9
Automatic Sleep Mode ............................................................. 9
RESET#: Hardware Reset Pin ................................................. 9
Output Disable Mode .............................................................. 10
Table 2. Am29SL400DT Top Boot Block Sector Address Table .....10
Table 3. Am29SL400DB Bottom Boot Block Sector Address Table 10
Autoselect Mode ..................................................................... 11
Table 4. Am29SL400D Autoselect Codes (High Voltage Method) ..11
Sector Protection/Unprotection ............................................... 11
Temporary Sector Unprotect .................................................. 11
Figure 1. In-system Sector Protection/Unprotection Algorithms ..... 12
Figure 2. Temporary Sector Unprotect Operation........................... 13
Hardware Data Protection ...................................................... 13
Low VCC Write Inhibit .............................................................. 13
Write Pulse “Glitch” Protection ............................................... 13
Logical Inhibit .......................................................................... 13
Power-Up Write Inhibit ............................................................ 13
Command Definitions . . . . . . . . . . . . . . . . . . . . . 13
Reading Array Data ................................................................ 13
Reset Command ..................................................................... 13
Autoselect Command Sequence ............................................ 14
Word/Byte Program Command Sequence ............................. 14
Unlock Bypass Command Sequence ..................................... 14
Figure 3. Program Operation .......................................................... 15
Chip Erase Command Sequence ........................................... 15
Sector Erase Command Sequence ........................................ 15
Figure 4. Erase Operation............................................................... 16
Table 5. Am29SL400D Command Definitions ................................17
Write Operation Status ........................................................... 18
DQ7: Data# Polling ................................................................. 18
Figure 5. Data# Polling Algorithm ................................................... 18
RY/BY#: Ready/Busy# ........................................................... 18
DQ6: Toggle Bit I .................................................................... 19
DQ2: Toggle Bit II ................................................................... 19
April 13, 2005 Rev. A Amend. +1
Reading Toggle Bits DQ6/DQ2 ............................................... 19
Figure 6. Toggle Bit Algorithm........................................................ 20
DQ5: Exceeded Timing Limits ................................................ 20
DQ3: Sector Erase Timer ....................................................... 20
Table 6. Write Operation Status ..................................................... 21
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 22
Figure 7. Maximum Negative Overshoot Waveform ...................... 22
Figure 8. Maximum Positive Overshoot Waveform........................ 22
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 22
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 9. ICC1 Current vs. Time (Showing Active and Automatic
Sleep Currents) .............................................................................. 24
Figure 10. Typical ICC1 vs. Frequency ........................................... 24
Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 11. Test Setup..................................................................... 25
Table 7. Test Specifications ........................................................... 25
Key to Switching Waveforms .................................................. 25
Figure 12. Input Waveforms and Measurement Levels ................. 25
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 26
Read Operations .................................................................... 26
Figure 13. Read Operations Timings ............................................. 26
Figure 14. RESET# Timings .......................................................... 27
Word/Byte Configuration (BYTE#) ........................................ 28
Figure 15. BYTE# Timings for Read Operations............................ 28
Figure 16. BYTE# Timings for Write Operations............................ 28
Erase/Program Operations ..................................................... 29
Figure 17. Program Operation Timings.......................................... 30
Figure 18. Chip/Sector Erase Operation Timings .......................... 31
AC Characteristics
. . . . . . . . . . . . . . . . . . . . . . 32
Figure 19. Data# Polling Timings (During Embedded Algorithms). 32
Figure 20. Toggle Bit Timings (During Embedded Algorithms)...... 32
Figure 21. DQ2 vs. DQ6................................................................. 33
Temporary Sector Unprotect .................................................. 33
Figure 22. Temporary Sector Unprotect Timing Diagram .............. 33
Figure 23. Sector Protect/Unprotect Timing Diagram .................... 34
Alternate CE# Controlled Erase/Program Operations ............ 35
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 24. Alternate CE# Controlled Write Operation Timings ...... 36
Erase and Programming Performance . . . . . . . 37
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 37
TSOP Pin and BGA Package Capacitance . . . . . 37
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 38
FBA048—48-Ball Fine-Pitch Ball Grid Array (FBGA) 6 x 8 mm
Package .................................................................................. 38
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 39
Am29SL400D
3
A D V A N C E
I N F O R M A T I O N
PRODUCT SELECTOR GUIDE
Family Part Number
Speed Options
Am29SL400D
Standard Voltage Range VCC = 1.65–1.95 V
90
100
120
Max access time, ns (tACC)
90
100
120
Max CE# access time, ns (tCE)
90
100
120
Max OE# access time, ns (tOE)
30
35
50
Note: See “AC Characteristics” for full specifications.
BLOCK DIAGRAM
DQ0–DQ15 (A-1)
RY/BY#
VCC
Sector Switches
VSS
Erase Voltage
Generator
RESET#
WE#
BYTE#
Input/Output
Buffers
State
Control
Command
Register
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
CE#
OE#
VCC Detector
Address Latch
STB
Timer
A0–A17
4
Am29SL400D
STB
Data
Latch
Y-Decoder
Y-Gating
X-Decoder
Cell Matrix
Rev. A Amend. +1 April 13, 2005
A D V A N C E
I N F O R M A T I O N
CONNECTION DIAGRAM
48-Ball FBGA
(Top View, Balls Facing Down)
A6
B6
C6
D6
E6
A13
A12
A14
A15
A16
A5
B5
C5
D5
E5
F5
G5
H5
A9
A8
A10
A11
DQ7
DQ14
DQ13
DQ6
A4
B4
C4
D4
E4
F4
G4
H4
WE#
RESET#
NC
NC
DQ5
DQ12
VCC
DQ4
A3
B3
C3
D3
E3
F3
G3
H3
RY/BY#
NC
NC
NC
DQ2
DQ10
DQ11
DQ3
A2
B2
C2
D2
E2
F2
G2
H2
A7
A17
A6
A5
DQ0
DQ8
DQ9
DQ1
A1
B1
C1
D1
E1
F1
G1
H1
A3
A4
A2
A1
A0
CE#
OE#
VSS
Special Handling Instructions for FBGA
Packages
Special handling is required for Flash Memory products
in molded packages (TSOP, BGA, PLCC, PDIP,
April 13, 2005 Rev. A Amend. +1
F6
G6
BYTE# DQ15/A-1
H6
VSS
SSOP). The package and/or data integrity may be
compromised if the package body is exposed to temperatures about 150°C for prolonged periods of time.
Am29SL400D
5
A D V A N C E
I N F O R M A T I O N
PIN CONFIGURATION
A0–A17
=
LOGIC SYMBOL
18 addresses
18
DQ0–DQ14 =
15 data inputs/outputs
DQ15/A-1
=
DQ15 (data input/output, word mode),
A-1 (LSB address input, byte mode)
BYTE#
=
Selects 8-bit or 16-bit mode
CE#
=
Chip enable
OE#
=
Output enable
WE#
=
Write enable
RESET#
RESET#
=
Hardware reset pin, active low
BYTE#
RY/BY#
=
Ready/Busy# output
VCC
=
1.65–1.95 V single power supply
VSS
=
Device ground
NC
=
Pin not connected internally
6
A0–A17
16 or 8
DQ0–DQ15
(A-1)
CE#
OE#
WE#
Am29SL400D
RY/BY#
Rev. A Amend. +1 April 13, 2005
A D V A N C E
I N F O R M A T I O N
ORDERING INFORMATION
Standard Products
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below.
Am29SL400D
T
90
E
C
TEMPERATURE RANGE
C
D
I
F
=
=
=
=
Commercial (0°C to +70°C)
Commercial (0°C to +70°C) with Pb-free Package
Industrial (–40°C to +85°C)
Industrial (–40°C to +85°C) with Pb-free Package
PACKAGE TYPE
WA =
48-Ball Fine-Pitch Ball Grid Array (FBGA)
0.80 mm pitch, 6 x 8 mm package (FBA048)
SPEED OPTION
See Product Selector Guide and Valid Combinations
BOOT CODE SECTOR ARCHITECTURE
T
B
=
=
Top Sector
Bottom Sector
DEVICE NUMBER/DESCRIPTION
Am29SL400D
4 Megabit (512 K x 8-Bit/256 K x 16-Bit) CMOS Flash Memory
1.8 Volt-only Read, Program, and Erase
Valid Combinations
Valid Combinations list configurations planned to be
supported in volume for this device. Consult the local
AMD sales office to confirm availability of specific valid
combinations and to check on newly released combinations.
Valid Combinations for FBGA Packages
Order Number
AM29SL400DT90,
AM29SL400DB90
AM29SL400DT100,
AM29SL400DB100
AM29SL400DT120,
AM29SL400DB120
Package Marking
WAC,
WAI,
WAD,
WAF
April 13, 2005 Rev. A Amend. +1
A400DT90V,
A400DB90V
A400DT10V,
A400DB10V
C, I,
D, F
A400DT12V,
A400DB12V
Am29SL400D
7
A D V A N C E
I N F O R M A T I O N
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register
itself does not occupy any addressable memory location. The register is composed of latches that store the
commands, along with the address and data information needed to execute the command. The contents of
Table 1.
the register serve as inputs to the internal state
machine. The state machine outputs dictate the function of the device. Table 1 lists the device bus operations, the inputs and control levels they require, and the
resulting output. The following subsections describe
each of these operations in further detail.
Am29SL400D Device Bus Operations
DQ8–DQ15
Operation
CE#
OE# WE# RESET#
Addresses
(Note 1)
DQ0–
DQ7
BYTE#
= VIH
BYTE#
= VIL
DQ8–DQ14 = High-Z,
DQ15 = A-1
Read
L
L
H
H
AIN
DOUT
DOUT
Write
L
H
L
H
AIN
DIN
DIN
VCC ±
0.2 V
X
X
VCC ±
0.2 V
X
High-Z
High-Z
High-Z
Output Disable
L
H
H
H
X
High-Z
High-Z
High-Z
Reset
X
X
X
L
X
High-Z
High-Z
High-Z
Sector Protect (Note 2)
L
H
L
VID
Sector Address,
A6 = L, A1 = H,
A0 = L
DIN
X
X
Sector Unprotect (Note 2)
L
H
L
VID
Sector Address,
A6 = H, A1 = H,
A0 = L
DIN
X
X
Temporary Sector Unprotect
X
X
X
VID
AIN
DIN
DIN
High-Z
Standby
Legend:
L = Logic Low = VIL, H = Logic High = VIH, VID = 10 ± 1.0 V, X = Don’t Care, AIN = Address In, DIN = Data In, DOUT = Data Out
Notes:
1. Addresses are A17:A0 in word mode (BYTE# = VIH), A17:A-1 in byte mode (BYTE# = VIL).
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector
Protection/Unprotection” section.
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O
pins DQ15–DQ0 operate in the byte or word configuration. If the BYTE# pin is set at logic ‘1’, the device is in
word configuration, DQ15–DQ0 are active and controlled by CE# and OE#.
If the BYTE# pin is set at logic ‘0’, the device is in byte
configuration, and only data I/O pins DQ0–DQ7 are
active and controlled by CE# and OE#. The data I/O
pins DQ8–DQ14 are tri-stated, and the DQ15 pin is
used as an input for the LSB (A-1) address function.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power
8
control and selects the device. OE# is the output
control and gates array data to the output pins. WE#
should remain at V IH . The BYTE# pin determines
whether the device outputs array data in words or
bytes.
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No
command is necessary in this mode to obtain array
data. Standard microprocessor read cycles that assert
valid addresses on the device address inputs produce
valid data on the device data outputs. The device
remains enabled for read access until the command
register contents are altered.
Am29SL400D
Rev. A Amend. +1 April 13, 2005
A D V A N C E
I N F O R M A T I O N
See “ Reading Array Data, on page 13 for more information. Refer to the AC Read Operations table for
timing specifications and to Figure 13, on page 26 for
the timing diagram. ICC1 in the DC Characteristics table
represents the active current specification for reading
array data.
Standby Mode
Writing Commands/Command Sequences
The device enters the CMOS standby mode when the
CE# and RESET# pins are both held at VCC ± 0.2 V.
(Note that this is a more restricted voltage range than
VIH.) If CE# and RESET# are held at VIH, but not within
VCC ± 0.2 V, the device will be in the standby mode, but
the standby current will be greater. The device requires
standard access time (tCE) for read access when the
device is in either of these standby modes, before it is
ready to read data.
To write a command or command sequence (which
includes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to VIL, and OE# to VIH.
For program operations, the BYTE# pin determines
whether the device accepts program data in bytes or
words. Refer to Word/Byte Configuration, on page 8
for more information.
The device features an Unlock Bypass mode to facilitate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are
required to program a word or byte, instead of four. The
Word/Byte Program Command Sequence, on page 14
has details on programming data to the device using
b o t h s t a n d a r d a n d U n l o ck B y p a s s c o m m a n d
sequences.
An erase operation can erase one sector, multiple sectors, or the entire device. Tables 2 and 3 indicate the
address space that each sector occupies. A “sector
address” consists of the address bits required to
u n i q u e l y s e l e c t a s e c t o r. T h e C o m m a n d
Definitions, on page 17 has details on erasing a sector
or the entire chip, or suspending/resuming the erase
operation.
After the system writes the autoselect command
sequence, the device enters the autoselect mode. The
system can then read autoselect codes from the
internal register (which is separate from the memory
array) on DQ7–DQ0. Standard read cycle timings apply
in this mode. Refer to the Autoselect Mode and Autoselect Command Sequence sections for more information.
ICC2 in the DC Characteristics table represents the
active current specification for the write mode. The AC
Characteristics, on page 26 contains timing specification tables and timing diagrams for write operations.
Program and Erase Operation Status
During an erase or program operation, the system may
check the status of the operation by reading the status
bits on DQ7–DQ0. Standard read cycle timings and ICC
read specifications apply. Refer to Write Operation
Status, on page 18 for more information, and to AC
Characteristics, on page 26 for timing diagrams.
April 13, 2005 Rev. A Amend. +1
When the system is not reading or writing to the device,
it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the
outputs are placed in the high impedance state, independent of the OE# input.
The device also enters the standby mode when the
RESET# pin is driven low. Refer to the next section,
RESET#: Hardware Reset Pin.
If the device is deselected during erasure or programming, the device draws active current until the
operation is completed.
ICC3 in the DC Characteristics table represents the
standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device
energy consumption. The device automatically enables
this mode when addresses remain stable for tACC + 50
ns. The automatic sleep mode is independent of the
CE#, WE#, and OE# control signals. Standard address
access timings provide new data when addresses are
changed. While in sleep mode, output data is latched
and always available to the system. ICC4 in the DC
Characteristics table represents the automatic sleep
mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of resetting the device to reading array data. When the
RESET# pin is driven low for at least a period of tRP, the
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state
machine to reading array data. The operation that was
interrupted should be reinitiated once the device is
ready to accept another command sequence, to
ensure data integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at VSS±0.2 V, the device
draws CMOS standby current (ICC4). If RESET# is held
at VIL but not within VSS±0.2 V, the standby current will
be greater.
Am29SL400D
9
A D V A N C E
I N F O R M A T I O N
The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firmware from the Flash memory.
If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a
time of tREADY (during Embedded Algorithms). The
system can thus monitor RY/BY# to determine whether
the reset operation is complete. If RESET# is asserted
when a program or erase operation is not executing
(RY/BY# pin is “1”), the reset operation is completed
Table 2.
within a time of tREADY (not during Embedded Algorithms). The system can read data t RH after the
RESET# pin returns to VIH.
Refer to AC Characteristics, on page 26 for RESET#
parameters and to Figure 14, on page 27 for the timing
diagram.
Output Disable Mode
When the OE# input is at VIH, output from the device is
disabled. The output pins are placed in the high impedance state.
Am29SL400DT Top Boot Block Sector Address Table
Sector
A17
A16
A15
A14
A13
A12
Sector Size
(Kbytes/
Kwords)
(x8) Address Range
(x16) Address Range
SA0
0
0
0
X
X
X
64/32
00000h–0FFFFh
00000h–07FFFh
SA1
0
0
1
X
X
X
64/32
10000h–1FFFFh
08000h–0FFFFh
SA2
0
1
0
X
X
X
64/32
20000h–2FFFFh
10000h–17FFFh
SA3
0
1
1
X
X
X
64/32
30000h–3FFFFh
18000h–1FFFFh
SA4
1
0
0
X
X
X
64/32
40000h–4FFFFh
20000h–27FFFh
SA5
1
0
1
X
X
X
64/32
50000h–5FFFFh
28000h–2FFFFh
SA6
1
1
0
X
X
X
64/32
60000h–6FFFFh
30000h–37FFFh
SA7
1
1
1
0
X
X
32/16
70000h–77FFFh
38000h–3BFFFh
SA8
1
1
1
1
0
0
8/4
78000h–79FFFh
3C000h–3CFFFh
SA9
1
1
1
1
0
1
8/4
7A000h–7BFFFh
3D000h–3DFFFh
SA10
1
1
1
1
1
X
16/8
7C000h–7FFFFh
3E000h–3FFFFh
Table 3.
Address Range (in hexadecimal)
Am29SL400DB Bottom Boot Block Sector Address Table
Sector
A17
A16
A15
A14
A13
A12
Sector Size
(Kbytes/
Kwords)
Address Range (in hexadecimal)
SA0
0
0
0
0
0
X
16/8
00000h–03FFFh
00000h–01FFFh
SA1
0
0
0
0
1
0
8/4
04000h–05FFFh
02000h–02FFFh
SA2
0
0
0
0
1
1
8/4
06000h–07FFFh
03000h–03FFFh
SA3
0
0
0
1
X
X
32/16
08000h–0FFFFh
04000h–07FFFh
SA4
0
0
1
X
X
X
64/32
10000h–1FFFFh
08000h–0FFFFh
SA5
0
1
0
X
X
X
64/32
20000h–2FFFFh
10000h–17FFFh
SA6
0
1
1
X
X
X
64/32
30000h–3FFFFh
18000h–1FFFFh
SA7
1
0
0
X
X
X
64/32
40000h–4FFFFh
20000h–27FFFh
SA8
1
0
1
X
X
X
64/32
50000h–5FFFFh
28000h–2FFFFh
SA9
1
1
0
X
X
X
64/32
60000h–6FFFFh
30000h–37FFFh
SA10
1
1
1
X
X
X
64/32
70000h–7FFFFh
38000h–3FFFFh
(x8) Address Range
(x16) Address Range
Note for Tables 2 and 3: Address range is A17:A-1 in byte mode and A17:A0 in word mode. See “Word/Byte Configuration”
section for more information.
10
Am29SL400D
Rev. A Amend. +1 April 13, 2005
A D V A N C E
I N F O R M A T I O N
Autoselect Mode
address must appear on the appropriate highest order
address bits (see Tables 2 and 3). Table 4 shows the
remaining address bits that are don’t care. When all
necessary bits have been set as required, the programming equipment may then read the corresponding
identifier code on DQ7–DQ0.
The autoselect mode provides manufacturer and
device identification, and sector protection verification,
through identifier codes output on DQ7–DQ0. This
mode is primarily intended for programming equipment
to automatically match a device to be programmed with
its corresponding programming algorithm. However,
the autoselect codes can also be accessed in-system
through the command register.
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in Table 5 on page 17.
This method does not require VID. See “ Command
Definitions, on page 13 for details on using the autoselect mode.
When using programming equipment, the autoselect
mode requires VID on address pin A9. Address pins
A6, A1, and A0 must be as shown in Table 4. In addition, when verifying sector protection, the sector
Table 4.
Description
Mode
Am29SL400D Autoselect Codes (High Voltage Method)
A17 A11
to
to
WE# A12 A10
CE#
OE#
Manufacturer ID: AMD
L
L
H
Device ID:
Am29SL400D
(Top Boot Block)
Word
L
L
H
Byte
L
L
H
Device ID:
Am29SL400D
(Bottom Boot Block)
Word
L
L
H
Sector Protection Verification
L
L
L
L
A1
A0
DQ8
to
DQ15
DQ7
to
DQ0
X
01h
22h
70h
X
70h
22h
F1h
X
F1h
X
01h
(protected)
X
00h
(unprotected)
X
VID
X
L
X
L
L
X
X
VID
X
L
X
L
H
VID
X
X
H
H
A6
A5
to
A2
X
X
Byte
A9
A8
to
A7
SA
X
VID
X
L
L
X
X
L
H
H
L
L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.
Sector Protection/Unprotection
The hardware sector protection feature disables both
program and erase operations in any sector. The hardware sector unprotection feature re-enables both
program and erase operations in previously protected
sectors. Sector protection/unprotection can be implemented via two methods.
Sector protection/unprotection requires V ID on the
RESET# pin only, and can be implemented either
in-system or via programming equipment. Figure 1, on
page 12 shows the algorithms and Figure 23, on
page 34 shows the timing diagram. This method uses
standard microprocessor bus cycle timing. For sector
unprotect, all unprotected sectors must first be protected prior to the first sector unprotect write cycle.
The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device
April 13, 2005 Rev. A Amend. +1
through AMD’s ExpressFlash™ Service. Contact an
AMD representative for details.
It is possible to determine whether a sector is protected
or unprotected. See Autoselect Mode, on page 11 for
details.
Temporary Sector Unprotect
This feature allows temporary unprotection of previously protected sectors to change data in-system. The
Sector Unprotect mode is activated by setting the
RESET# pin to VID. During this mode, formerly protected sectors can be programmed or erased by
selecting the sector addresses. Once VID is removed
from the RESET# pin, all the previously protected
sectors are protected again. Figure 2, on page 13
shows the algorithm, and Figure 22, on page 33 shows
the timing diagrams, for this feature.
Am29SL400D
11
A D V A N C E
I N F O R M A T I O N
START
START
Protect all sectors:
The indicated portion
of the sector protect
algorithm must be
performed for all
unprotected sectors
prior to issuing the
first sector
unprotect address
PLSCNT = 1
RESET# = VID
Wait 1 µs
Temporary Sector
Unprotect Mode
No
PLSCNT = 1
RESET# = VID
Wait 1 µs
No
First Write
Cycle = 60h?
First Write
Cycle = 60h?
Yes
Yes
Set up sector
address
No
All sectors
protected?
Sector Protect:
Write 60h to sector
address with
A6 = 0, A1 = 1,
A0 = 0
Yes
Set up first sector
address
Sector Unprotect:
Write 60h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Wait 150 µs
Increment
PLSCNT
Temporary Sector
Unprotect Mode
Verify Sector
Protect: Write 40h
to sector address
with A6 = 0,
A1 = 1, A0 = 0
Reset
PLSCNT = 1
Wait 15 ms
Read from
sector address
with A6 = 0,
A1 = 1, A0 = 0
Verify Sector
Unprotect: Write
40h to sector
address with
A6 = 1, A1 = 1,
A0 = 0
Increment
PLSCNT
No
No
PLSCNT
= 25?
Yes
Yes
No
Yes
Device failed
PLSCNT
= 1000?
Protect another
sector?
No
Yes
Remove VID
from RESET#
Device failed
Write reset
command
Sector Protect
Algorithm
Read from
sector address
with A6 = 1,
A1 = 1, A0 = 0
Data = 01h?
Sector Protect
complete
Set up
next sector
address
No
Data = 00h?
Yes
Last sector
verified?
No
Yes
Sector Unprotect
Algorithm
Remove VID
from RESET#
Write reset
command
Sector Unprotect
complete
Figure 1.
12
In-system Sector Protection/Unprotection Algorithms
Am29SL400D
Rev. A Amend. +1 April 13, 2005
A D V A N C E
I N F O R M A T I O N
for command definitions). In addition, the following
hardware data protection measures prevent accidental
erasure or programming, which might otherwise be
caused by spurious system level signals during VCC
power-up and power-down transitions, or from system
noise.
START
RESET# = VID
Low VCC Write Inhibit
When V CC is less than V LKO, the device does not
accept any write cycles. This protects data during VCC
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until VCC
is greater than V LKO. The system must provide the
proper signals to the control pins to prevent unintentional writes when VCC is greater than VLKO.
Perform Erase or
Program Operations
RESET# = VIH
Temporary Sector
Unprotect Completed
(Note 2)
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Notes:
1. All protected sectors unprotected.
Logical Inhibit
2. All previously protected sectors are protected once
again.
Figure 2.
Temporary Sector Unprotect Operation
Write cycles are inhibited by holding any one of OE# =
VIL, CE# = VIH or WE# = VIH. To initiate a write cycle,
CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to Table 5 on page 17
If WE# = CE# = VIL and OE# = VIH during power up, the
device does not accept commands on the rising edge
of WE#. The internal state machine is automatically
reset to reading array data on power-up.
COMMAND DEFINITIONS
Writing specific address and data commands or
sequences into the command register initiates device
operations. Table 5 on page 17 defines the valid register command sequences. Writing incorrect address
and data values or writing them in the improper
sequence resets the device to reading array data.
erase-suspended sectors, the device outputs status
data. After completing a programming operation in the
Erase Suspend mode, the system may once again
read array data with the same exception. See “Erase
Suspend/Erase Resume Commands” for more information on this mode.
All addresses are latched on the falling edge of WE# or
CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in AC
Characteristics, on page 26.
The system must issue the reset command to
re-enable the device for reading array data if DQ5 goes
high, or while in the autoselect mode. See the Reset
Command section, next.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after completing an Embedded Program or
Embedded Erase algorithm.
After the device accepts an Erase Suspend command,
the device enters the Erase Suspend mode. The
system can read array data using the standard read
timings, except that if it reads at an address within
April 13, 2005 Rev. A Amend. +1
See also Requirements for Reading Array Data, on
page 8 for more information. The Read Operations
table provides the read parameters, and Figure 13, on
page 26 shows the timing diagram.
Reset Command
Writing the reset command to the device resets the
device to reading array data. Address bits are don’t
care for this command.
The reset command may be written between the
sequence cycles in an erase command sequence
Am29SL400D
13
A D V A N C E
I N F O R M A T I O N
before erasing begins. This resets the device to reading
array data. Once erasure begins, however, the device
ignores reset commands until the operation is complete.
The reset command may be written between the
sequence cycles in a program command sequence
before programming begins. This resets the device to
reading array data (also applies to programming in
Erase Suspend mode). Once programming begins,
however, the device ignores reset commands until the
operation is complete.
The reset command may be written between the
sequence cycles in an autoselect command sequence.
Once in the autoselect mode, the reset command must
be written to return to reading array data (also applies
to autoselect during Erase Suspend).
If DQ5 goes high during a program or erase operation,
writing the reset command returns the device to
reading array data (also applies during Erase Suspend).
Autoselect Command Sequence
The autoselect command sequence allows the host
system to access the manufacturer and devices codes,
and determine whether or not a sector is protected.
Table 5 on page 17 shows the address and data
requirements. This method is an alternative to that
shown in Table 4 on page 11, which is intended for
PROM programmers and requires VID on address bit
A9.
The autoselect command sequence is initiated by
writing two unlock cycles, followed by the autoselect
command. The device then enters the autoselect
mode, and the system may read at any address any
number of times, without initiating another command
sequence. A read cycle at address XX00h retrieves the
manufacturer code. A read cycle at address 01h in
word mode (or 02h in byte mode) returns the device
code. A read cycle containing a sector address (SA)
and the address 02h in word mode (or 04h in byte
mode) returns 01h if that sector is protected, or 00h if it
is unprotected. Refer to Table 2 on page 10 and Table 3
on page 10 for valid sector addresses.
The system must write the reset command to exit the
autoselect mode and return to reading array data.
Word/Byte Program Command Sequence
The system may program the device by word or byte,
depending on the state of the BYTE# pin. Programming is a four-bus-cycle operation. The program
command sequence is initiated by writing two unlock
write cycles, followed by the program set-up command.
The program address and data are written next, which
in turn initiate the Embedded Program algorithm. The
system is not required to provide further controls or tim14
ings. The device automatically generates the program
pulses and verifies the programmed cell margin.
Table 5 on page 17 shows the address and data
r e q u i re m en t s fo r th e byt e pr o gra m c om m a n d
sequence.
When the Embedded Program algorithm is complete,
the device then returns to reading array data and
addresses are no longer latched. The system can
determine the status of the program operation by using
D Q 7, D Q 6, or RY/B Y# . Se e W r i te Op e ra tio n
Status, on page 18 for information on these status bits.
Any commands written to the device during the
Embedded Program Algorithm are ignored. Note that a
hardware reset immediately terminates the programm i n g o pe rat io n. T h e B yte Pr o gra m com m a n d
sequence should be reinitiated once the device has
reset to reading array data, to ensure data integrity.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from a “0” back to a “1”. Attempting to do so may halt
the operation and set DQ5 to “1”, or cause the Data#
Polling algorithm to indicate the operation was successful. However, a succeeding read will show that the
data is still “0”. Only erase operations can convert a “0”
to a “1”.
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to
program bytes or words to the device faster than using
the standard program command sequence. The unlock
bypass command sequence is initiated by first writing
two unlock cycles. This is followed by a third write cycle
containing the unlock bypass command, 20h. The
device then enters the unlock bypass mode. A
two-cycle unlock bypass program command sequence
is all that is required to program in this mode. The first
cycle in this sequence contains the unlock bypass
program command, A0h; the second cycle contains the
program address and data. Additional data is programmed in the same manner. This mode dispenses
with the initial two unlock cycles required in the standard program command sequence, resulting in faster
total programming time. Write Operation Status, on
page 18 shows the requirements for the command
sequence.
During the unlock bypass mode, only the Unlock
Bypass Program and Unlock Bypass Reset commands
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypas s reset
command sequence. The first cycle must contain the
data 90h; the second cycle the data 00h. Addresses
are don’t cares. The device then returns to reading
array data.
Figure 3, on page 15 illustrates the algorithm for the
program operation. See the Erase/Program
Am29SL400D
Rev. A Amend. +1 April 13, 2005
A D V A N C E
I N F O R M A T I O N
Operations, on page 29 for parameters, and to
Figure 17, on page 30 for timing diagrams.
START
The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. See Write
Operation Status, on page 18 for information on these
status bits. When the Embedded Erase algorithm is
complete, the device returns to reading array data and
addresses are no longer latched.
Write Program
Command Sequence
Figure 4, on page 16 illustrates the algorithm for the
erase operation. See the Erase/Program
Operations, on page 29 for parameters, and to
Figure 18, on page 31 for timing diagrams.
Data Poll
from System
Embedded
Program
algorithm
in progress
Sector Erase Command Sequence
Verify Data?
No
Yes
Increment Address
No
Last Address?
Programming
Completed
Note: See Table 5 on page 17 for program command
sequence.
Program Operation
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical
erase. The system is not required to provide any controls or timings during these operations. Table 5 on
page 17 shows the address and data requirements for
the chip erase command sequence.
Any c om mand s w r i tten to the chip du r ing th e
Embedded Erase algorithm are ignored. Note that a
April 13, 2005 Rev. A Amend. +1
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two
additional unlock write cycles are then followed by the
address of the sector to be erased, and the sector
erase command. Table 5 on page 17 shows the
address and data requirements for the sector erase
command sequence.
The device does not require the system to preprogram
the memory prior to erase. The Embedded Erase algorithm automatically programs and verifies the sector for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or
timings during these operations.
Yes
Figure 3.
hardware reset during the chip erase operation immediately terminates the operation. The Chip Erase
command sequence should be reinitiated once the
device has returned to reading array data, to ensure
data integrity.
After the command sequence is written, a sector erase
time-out of 50 µs begins. During the time-out period,
additional sector addresses and sector erase commands may be written. Loading the sector erase buffer
may be done in any sequence, and the number of
sectors may be from one sector to all sectors. The time
between these additional cycles must be less than 50
µs, otherwise the last address and command might not
be accepted, and erasure may begin. It is recommended that processor interrupts be disabled during
this time to ensure all commands are accepted. The
interrupts can be re-enabled after the last Sector Erase
command is written. If the time between additional
sector erase commands can be assumed to be less
than 50 µs, the system need not monitor DQ3. Any
command other than Sector Erase or Erase
Suspend during the time-out period resets the
device to reading array data. The system must
rewrite the command sequence and any additional
sector addresses and commands.
The system can monitor DQ3 to determine if the sector
erase timer has timed out. (See DQ3: Sector Erase
Timer, on page 20.) The time-out begins from the rising
edge of the final WE# pulse in the command sequence.
Am29SL400D
15
A D V A N C E
I N F O R M A T I O N
Once the sector erase operation has begun, only the
Erase Suspend command is valid. All other commands
are ignored. Note that a hardware reset during the
sector erase operation immediately terminates the
operation. The Sector Erase command sequence
should be reinitiated once the device has returned to
reading array data, to ensure data integrity.
When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are
no longer latched. The system can determine the
status of the erase operation by using DQ7, DQ6, DQ2,
or RY/BY#. (Refer to Write Operation Status, on
page 18 for information on these status bits.)
Figure 4 illustrates the algorithm for the erase operation. Refer to the Erase/Program Operations, on
page 29 for parameters, and to Figure 18, on page 31
for timing diagrams.
Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system to
interrupt a sector erase operation and then read data
from, or program data to, any sector not selected for
erasure. This command is valid only during the sector
erase operation, including the 50 µs time-out period
during the sector erase command sequence. The
Erase Suspend command is ignored if written during
the chip erase operation or Embedded Program algorithm. Writing the Erase Suspend command during the
Sector Erase time-out immediately terminates the
time-out period and suspends the erase operation.
Addresses are “don’t-cares” when writing the Erase
Suspend command.
non-suspended sectors. The system can determine
the status of the program operation using the DQ7 or
DQ6 status bits, just as in the standard program operation. See Write Operation Status, on page 18 for
more information.
The system may also write the autoselect command
sequence when the device is in the Erase Suspend
mode. The device allows reading autoselect codes
even at addresses within erasing sectors, since the
codes are not stored in the memory array. When the
device exits the autoselect mode, the device reverts to
the Erase Suspend mode, and is ready for another
valid operation. See Autoselect Com mand
Sequence, on page 14 for more information.
The system must write the Erase Resume command
(address bits are “don’t care”) to exit the erase suspend
mode and continue the sector erase operation. Further
writes of the Resume command are ignored. Another
Erase Suspend command can be written after the
device has resumed erasing.
START
Write Erase
Command Sequence
Data Poll
from System
When the Erase Suspend command is written during a
sector erase operation, the device requires a maximum
of 20 µs to suspend the erase operation. However,
when the Erase Suspend command is written during
the sector erase time-out, the device immediately terminates the time-out period and suspends the erase
operation.
After the erase operation has been suspended, the
system can read array data from or program data to
any sector not selected for erasure. (The device “erase
suspends” all sectors selected for erasure.) Normal
read and write timings and command definitions apply.
Reading at any address within erase-suspended
sectors produces status data on DQ7–DQ0. The
system can use DQ7, or DQ6 and DQ2 together, to
determine if a sector is actively erasing or is erase-suspended. See Write Operation Status, on page 18 for
information on these status bits.
No
Embedded
Erase
algorithm
in progress
Data = FFh?
Yes
Erasure Completed
Notes:
1. See Table 5 on page 17 for erase command sequence.
2. See DQ3: Sector Erase Timer, on page 20 for more information.
Figure 4.
Erase Operation
After an erase-suspended program operation is complete, the system can once again read array data within
16
Am29SL400D
Rev. A Amend. +1 April 13, 2005
A D V A N C E
I N F O R M A T I O N
Command Definitions
Table 5.
Read (Note 6)
Reset (Note 7)
Autoselect (Note 8)
Manufacturer ID
Word
Byte
Device ID,
Top Boot Block
Word
Device ID,
Bottom Boot Block
Word
Byte
Byte
Addr
Data
1
RA
RD
1
XXX
F0
4
4
4
Word
Sector Protect Verify
(Note 9)
Program
Unlock Bypass
Bus Cycles (Notes 2-5)
Cycles
Command
Sequence
(Note 1)
First
555
AAA
555
AAA
555
AAA
Byte
Byte
Word
Byte
Second
AA
AA
AA
555
4
Word
Am29SL400D Command Definitions
3
2AA
555
2AA
555
2AA
555
555
AAA
555
AAA
Data
AA
2AA
555
2AA
555
PA
PD
90
XXX
00
Sector Erase
Word
Byte
6
AAA
555
AAA
AA
Erase Suspend (Note 12)
1
XXX
B0
Erase Resume (Note 13)
1
XXX
30
555
2AA
555
555
AAA
555
55
A0
Byte
90
90
90
AAA
555
55
AAA
555
55
AAA
A0
Data
X00
01
X01
70h
X02
70h
X01
F1h
X02
F1h
(SA)
X02
XX00
(SA)
X04
00
PA
PD
90
55
XXX
AA
Data Addr
AAA
XXX
2AA
Fourth
555
2
6
555
AAA
55
2
Chip Erase
AAA
55
Unlock Bypass Reset (Note 11)
555
555
55
Unlock Bypass Program (Note 10)
Word
AAA
555
AA
Addr
555
55
2AA
AA
AAA
4
Addr
Third
Fifth
Sixth
Addr Data
Addr
Data
XX01
01
20
80
80
555
AAA
555
AAA
AA
AA
2AA
555
2AA
555
55
55
555
AAA
SA
10
30
Legend:
PD = Data to be programmed at location PA. Data latches on the
rising edge of WE# or CE# pulse, whichever happens first.
X = Don’t care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed.
Addresses latch on the falling edge of the WE# or CE# pulse,
whichever happens later.
SA = Address of the sector to be verified (in autoselect mode) or
erased. Address bits A17–A12 uniquely select any sector.
Notes:
1.
See Table 1 on page 8 for description of bus operations.
2. All values are in hexadecimal.
3. Except when reading array or autoselect data, all bus cycles are
write operations.
4. Data bits DQ15–DQ8 are don’t cares for unlock and command
cycles.
5. Address bits A17–A11 are don’t cares for unlock and command
cycles, unless SA or PA required.
6. No unlock or command cycles required when reading array data,
unless SA or PA required.
7. The Reset command is required to return to reading array data
when device is in the autoselect mode, or if DQ5 goes high (while
the device is providing status data).
9. The data is 00h for an unprotected sector and 01h for a protected
sector. See Autoselect Command Sequence, on page 14 for
more information.
10. The Unlock Bypass command is required prior to the Unlock
Bypass Program command.
11. The Unlock Bypass Reset command is required to return to
reading array data when the device is in the unlock bypass mode.
12. The system may read and program in non-erasing sectors, or
enter the autoselect mode, when in the Erase Suspend mode.
The Erase Suspend command is valid only during a sector erase
operation.
13. The Erase Resume command is valid only during the Erase Suspend
mode.
8. The fourth cycle of the autoselect command sequence is a read
cycle.
April 13, 2005 Rev. A Amend. +1
Am29SL400D
17
A D V A N C E
I N F O R M A T I O N
Write Operation Status
The device provides several bits to determine the status
of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7, and
RY/BY#. Table 6 on page 21 and the following subsections describe the functions of these bits. DQ7, RY/BY#,
and DQ6 each offer a method for determining whether
a program or erase operation is complete or in progress.
These three bits are discussed first.
START
Read DQ7–DQ0
Addr = VA
DQ7: Data# Polling
The Data# Polling bit, DQ7, indicates to the host system
whether an Embedded Algorithm is in progress or completed, or whether the device is in Erase Suspend.
Data# Polling is valid after the rising edge of the final
W E# p ulse in th e p rogram o r e ra se c o mm an d
sequence.
During the Embedded Program algorithm, the device
outputs on DQ7 the complement of the datum programmed to DQ7. This DQ7 status also applies to programming during Erase Suspend. When the Embedded
Program algorithm is complete, the device outputs the
datum programmed to DQ7. The system must provide
the program address to read valid status information on
DQ7. If a program address falls within a protected
sector, Data# Polling on DQ7 is active for approximately
1 µs, then the device returns to reading array data.
During the Embedded Erase algorithm, Data# Polling
produces a “0” on DQ7. When the Embedded Erase
algorithm is complete, or if the device enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
This is analogous to the complement/true datum output
described for the Embedded Program algorithm: the
erase function changes all the bits in a sector to “1”;
prior to this, the device outputs the “complement,” or “0.”
The system must provide an address within any of the
sectors selected for erasure to read valid status information on DQ7.
After an erase command sequence is written, if all
sectors selected for erasing are protected, Data#
Polling on DQ7 is active for approximately 100 µs, then
the device returns to reading array data. If not all
selected sectors are protected, the Embedded Erase
algorithm erases the unprotected sectors, and ignores
the selected sectors that are protected.
When the system detects DQ7 has changed from the
complement to true data, it can read valid data at
DQ7–DQ0 on the following read cycles. This is because
DQ7 may change asynchronously with DQ0–DQ6 while
Output Enable (OE#) is asserted low. Figure 19, on
page 32, Data# Polling Timings (During Embedded
Algorithms), illustrates this.
Table 6 on page 21 shows the outputs for Data# Polling
on DQ7. Figure 5 shows the Data# Polling algorithm.
18
Yes
DQ7 = Data?
No
No
DQ5 = 1?
Yes
Read DQ7–DQ0
Addr = VA
Yes
DQ7 = Data?
No
PASS
FAIL
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” because
DQ7 may change simultaneously with DQ5.
Figure 5.
Data# Polling Algorithm
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin that
indicates whether an Embedded Algorithm is in
progress or complete. The RY/BY# status is valid after
the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output,
several RY/BY# pins can be tied together in parallel with
a pull-up resistor to VCC.
Am29SL400D
Rev. A Amend. +1 April 13, 2005
A D V A N C E
I N F O R M A T I O N
If the output is low (Busy), the device is actively erasing
or programming. (This includes programming in the
Erase Suspend mode.) If the output is high (Ready),
the device is ready to read array data (including during
the Erase Suspend mode), or is in the standby mode.
Table 6 on page 21 shows the outputs for RY/BY#.
Figure 14, on page 27, Figure 17, on page 30 and
Figure 18, on page 31 shows RY/BY# for reset, program, and erase operations, respectively.
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase algorithm is in progress or complete,
or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is
valid after the rising edge of the final WE# pulse in the
command sequence (prior to the program or erase
operation), and during the sector erase time-out.
During an Embedded Program or Erase algorithm
operation, successive read cycles to any address
cause DQ6 to toggle (The system may use either OE#
or CE# to control the read cycles). When the operation
is complete, DQ6 stops toggling.
After an erase command sequence is written, if all
sectors selected for erasing are protected, DQ6 toggles
for approximately 100 µs, then returns to reading array
data. If not all selected sectors are protected, the
Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are protected.
The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is
erase-suspended. When the device is actively erasing
(that is, the Embedded Erase algorithm is in progress),
DQ6 toggles. When the device enters the Erase
Suspend mode, DQ6 stops toggling. However, the
system must also use DQ2 to determine which sectors
are erasing or erase-suspended. Alternatively, the
system can use DQ7 (see the subsection on DQ7:
Data# Polling).
If a program address falls within a protected sector,
DQ6 toggles for approximately 1 µs after the program
command sequence is written, then returns to reading
array data.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded
Program algorithm is complete.
Table 6 on page 21 shows the outputs for Toggle Bit I
on DQ6. Figure 6, on page 20 shows the toggle bit
algorithm. Figure 20, on page 32 shows the toggle bit
timing diagrams. Figure 21, on page 33 shows the differences between DQ2 and DQ6 in graphical form. See
also the subsection on DQ2: Toggle Bit II.
April 13, 2005 Rev. A Amend. +1
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indicates whether a particular sector is actively erasing
(that is, the Embedded Erase algorithm is in progress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence. The device toggles DQ2 with
each OE# or CE# read cycle.
DQ2 toggles when the system reads at addresses
within those sectors that have been selected for erasure. But DQ2 cannot distinguish whether the sector is
actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively
erasing, or is in Erase Suspend, but cannot distinguish
which sectors are selected for erasure. Thus, both
status bits are required for sector and mode information. Refer to Table 6 on page 21 to compare outputs
for DQ2 and DQ6.
Figure 6, on page 20 shows the toggle bit algorithm in
flowchart form, and the section “DQ2: Toggle Bit II”
explains the algorithm. See also the DQ6: Toggle Bit I
subsection. Figure 20, on page 32 shows the toggle bit
timing diagram. Figure 21, on page 33 shows the differences between DQ2 and DQ6 in graphical form.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 6, on page 20 for the following discussion. Whenever the system initially begins reading
toggle bit status, it must read DQ7–DQ0 at least twice
in a row to determine whether a toggle bit is toggling.
Typically, the system would note and store the value of
the toggle bit after the first read. After the second read,
the system would compare the new value of the toggle
bit with the first. If the toggle bit is not toggling, the
device has completed the program or erase operation.
The system can read array data on DQ7–DQ0 on the
following read cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the
system also should note whether the value of DQ5 is
high (see the section on DQ5). If it is, the system
should then determine again whether the toggle bit is
toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer
toggling, the device has successfully completed the
program or erase operation. If it is still toggling, the
device did not completed the operation successfully,
and the system must write the reset command to return
to reading array data.
The remaining scenario is that the system initially
determines that the toggle bit is toggling and DQ5 has
not gone high. The system may continue to monitor the
toggle bit and DQ5 through successive read cycles,
determining the status as described in the previous
paragraph. Alternatively, it may choose to perform
Am29SL400D
19
A D V A N C E
I N F O R M A T I O N
other system tasks. In this case, the system must start
at the beginning of the algorithm when it returns to
determine the status of the operation (top of Figure 6).
START
(Note 1)
Read DQ7–DQ0
Under both these conditions, the system must issue the
reset command to return the device to reading array
data.
DQ3: Sector Erase Timer
No
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not an
erase operation has begun. (The sector erase timer
does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire
time-out also applies after each additional sector erase
command. When the time-out is complete, DQ3
switches from “0” to “1.” If the time between additional
sector erase commands from the system can be
assumed to be less than 50 µs, the system need not
monitor DQ3. See also the “ Sector Erase Command
Sequence, on page 15 section.
Yes
No
DQ5 = 1?
Yes
Read DQ7–DQ0
Twice
Toggle Bit
= Toggle?
(Notes
1, 2)
No
Yes
Program/Erase
Operation Not
Complete, Write
Reset Command
DQ5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under
these conditions DQ5 produces a “1.” This is a failure
condition that indicates the program or erase cycle was
not successfully completed.
The DQ5 failure condition may appear if the system
tries to program a “1” to a location that is previously programmed to “0.” Only an erase operation can change
a “0” back to a “1.” Under this condition, the device
halts the operation, and when the operation has
exceeded the timing limits, DQ5 produces a “1.”
Read DQ7–DQ0
Toggle Bit
= Toggle?
DQ5: Exceeded Timing Limits
Program/Erase
Operation Complete
Notes:
1. Read toggle bit twice to determine whether or not it is
toggling. See text.
After the sector erase command sequence is written,
the system should read the status on DQ7 (Data#
Polling) or DQ6 (Toggle Bit I) to ensure the device has
accepted the command sequence, and then read DQ3.
If DQ3 is “1”, the internally controlled erase cycle has
begun; all further commands (other than Erase Suspend) are ignored until the erase operation is complete.
If DQ3 is “0”, the device will accept additional sector
erase commands. To ensure the command has been
accepted, the system software should check the status
of DQ3 prior to and following each subsequent sector
erase command. If DQ3 is high on the second status
check, the last command might not have been
accepted. Table 6 on page 21 shows the outputs for
DQ3.
2. Recheck toggle bit because it may stop toggling as DQ5
changes to “1” . See text.
Figure 6.
20
Toggle Bit Algorithm
Am29SL400D
Rev. A Amend. +1 April 13, 2005
A D V A N C E
Table 6.
Write Operation Status
DQ7
(Note 2)
DQ6
DQ5
(Note 1)
DQ3
DQ2
(Note 2)
RY/BY#
DQ7#
Toggle
0
N/A
No toggle
0
0
Toggle
0
1
Toggle
0
1
No toggle
0
N/A
Toggle
1
Reading within Non-Erase
Suspended Sector
Data
Data
Data
Data
Data
1
Erase-Suspend-Program
DQ7#
Toggle
0
N/A
N/A
0
Operation
Standard Embedded Program Algorithm
Mode
Embedded Erase Algorithm
Erase
Suspend
Mode
I N F O R M A T I O N
Reading within Erase
Suspended Sector
Notes:
1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.
See DQ5: Exceeded Timing Limits, on page 20 for more information.
2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
April 13, 2005 Rev. A Amend. +1
Am29SL400D
21
A D V A N C E
I N F O R M A T I O N
ABSOLUTE MAXIMUM RATINGS
Storage Temperature
Plastic Packages . . . . . . . . . . . . . . . –65°C to +150°C
Ambient Temperature
with Power Applied. . . . . . . . . . . . . . –65°C to +125°C
Voltage with Respect to Ground
20 ns
20 ns
0.0 V
–0.5 V
VCC (Note 1). . . . . . . . . . . . . . . . . . . .–0.5 V to +2.5 V
A9, OE#,
and RESET# (Note 2) . . . . . . . . . . .–0.5 V to +11.0 V
–2.0 V
20 ns
All other pins (Note 1) . . . . . . . . –0.5 V to VCC+0.5 V
Figure 7. Maximum Negative
Overshoot Waveform
Output Short Circuit Current (Note 3) . . . . . . 100 mA
Notes:
1. Minimum DC voltage on input or I/O pins is –0.5 V. During
voltage transitions, input or I/O pins may overshoot VSS to
–2.0 V for periods of up to 20 ns. See Figure 7. Maximum
DC voltage on input or I/O pins is VCC +0.5 V. During
voltage transitions, input or I/O pins may overshoot to VCC
+2.0 V for periods up to 20 ns. See Figure 8.
2. Minimum DC input voltage on pins A9, OE#, and RESET#
is –0.5 V. During voltage transitions, A9, OE#, and
RESET# may overshoot VSS to –2.0 V for periods of up to
20 ns. See Maximum DC input voltage on pin A9 is +11.0
V which may overshoot to 12.5 V for periods up to 20 ns.
3. No more than one output may be shorted to ground at a
time. Duration of the short circuit should not be greater
than one second.
20 ns
VCC
+2.0 V
VCC
+0.5 V
2.0 V
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device. This is
a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the
operational sections of this data sheet is not implied.
Exposure of the device to absolute maximum rating
conditions for extended periods may affect device reliability.
20 ns
20 ns
Figure 8. Maximum Positive
Overshoot Waveform
OPERATING RANGES
Commercial (C) Devices
Ambient Temperature (TA) . . . . . . . . . . . 0°C to +70°C
Industrial (I) Devices
Ambient Temperature (TA) . . . . . . . . . –40°C to +85°C
VCC Supply Voltages
VCC for all speed options . . . . . . . .+1.65 V to +1.95 V
Operating ranges define those limits between which the
functionality of the device is guaranteed.
22
Am29SL400D
Rev. A Amend. +1 April 13, 2005
A D V A N C E
I N F O R M A T I O N
DC CHARACTERISTICS
CMOS Compatible
Parameter
Description
Test Conditions
Min
ILI
Input Load Current
VIN = VSS to VCC,
VCC = VCC max
ILIT
A9 Input Load Current
VCC = VCC max; A9 = 11.0 V
ILO
Output Leakage Current
VOUT = VSS to VCC,
VCC = VCC max
ICC1
VCC Active Read Current
(Notes 1, 2)
CE# = VIL, OE# = VIH,
Byte Mode
Typ
Max
Unit
±1.0
µA
35
µA
±1.0
µA
5 MHz
5
10
1 MHz
1
3
5 MHz
5
10
1 MHz
1
3
mA
CE# = VIL, OE# = VIH,
Word Mode
ICC2
VCC Active Write Current
(Notes 2, 3, 5)
CE# = VIL, OE# = VIH
15
30
mA
ICC3
VCC Standby Current (Note 2)
CE#, RESET# = VCC ± 0.2 V
0.2
5
µA
ICC4
VCC Reset Current (Note 2)
RESET# = VSS ± 0.2 V
0.2
5
µA
ICC5
Automatic Sleep Mode
(Notes 2, 3)
VIH = VCC ± 0.2 V;
VIL = VSS ± 0.2 V
0.2
5
µA
VIL
Input Low Voltage
–0.5
0.3 x VCC
V
VIH
Input High Voltage
0.7 x VCC
VCC + 0.3
V
VID
Voltage for Autoselect and
Temporary Sector Unprotect
9.0
11.0
V
IOL = 2.0 mA, VCC = VCC min
0.25
V
IOL = 100 µA, VCC = VCC min
0.1
V
VOL1
Output Low Voltage
VOL2
VOH1
Output High Voltage
VOH2
VLKO
VCC = 2.0 V
IOH = –2.0 mA, VCC = VCC min
0.85 x VCC
V
IOH = –100 µA, VCC = VCC min
VCC–0.1
V
Low VCC Lock-Out Voltage
(Note 4)
1.2
1.5
V
Notes:
1. The ICC current listed is typically less than 1 mA/MHz, with OE# at VIH. Typical VCC is 2.0 V.
2. The maximum ICC specifications are tested with VCC = VCCmax.
3. ICC active while Embedded Erase or Embedded Program is in progress.
4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 50 ns.
5. Not 100% tested.
April 13, 2005 Rev. A Amend. +1
Am29SL400D
23
A D V A N C E
I N F O R M A T I O N
DC CHARACTERISTICS (Continued)
Zero Power Flash
Supply Current in mA
20
15
10
5
0
0
500
1000
1500
2000
2500
3000
3500
4000
Time in ns
Note: Addresses are switching at 1 MHz
Figure 9.
ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)
10
Supply Current in mA
8
6
4
1.8 V
2
0
1
2
3
4
5
Frequency in MHz
Note: T = 25 °C
Figure 10.
24
Typical ICC1 vs. Frequency
Am29SL400D
Rev. A Amend. +1 April 13, 2005
A D V A N C E
I N F O R M A T I O N
TEST CONDITIONS
Table 7.
Device
Under
Test
Test Condition
All Speed Options
Unit
Output Load Capacitance, CL
(including jig capacitance)
30
pF
Input Rise and Fall Times
5
ns
0.0–2.0
V
Input timing measurement
reference levels
1.0
V
Output timing measurement
reference levels
1.0
V
Input Pulse Levels
CL
Figure 11.
Test Specifications
Test Setup
Key to Switching Waveforms
WAVEFORM
INPUTS
OUTPUTS
Steady
Changing from H to L
Changing from L to H
2.0 V
Input
Don’t Care, Any Change Permitted
Changing, State Unknown
Does Not Apply
Center Line is High Impedance State (High Z)
1.0 V
Measurement Level
1.0 V
Output
0.0 V
Figure 12.
April 13, 2005 Rev. A Amend. +1
Input Waveforms and Measurement Levels
Am29SL400D
25
A D V A N C E
I N F O R M A T I O N
AC CHARACTERISTICS
Read Operations
Parameter
Speed Options
JEDEC
Std
tAVAV
tRC
Read Cycle Time (Note 1)
tAVQV
tACC
Address to Output Delay
tELQV
tCE
Chip Enable to Output Delay
tGLQV
tOE
tEHQZ
tGHQZ
tAXQX
Description
Test Setup
90
100
120
Unit
Min
90
100
120
ns
CE# = VIL
OE# = VIL
Max
90
100
120
ns
OE# = VIL
Max
90
100
120
ns
Output Enable to Output Delay
Max
30
35
50
ns
tDF
Chip Enable to Output High Z (Note 1)
Max
16
ns
tDF
Output Enable to Output High Z (Note 1)
Max
16
ns
Read
Min
0
ns
Toggle and
Data# Polling
Min
30
ns
Min
0
ns
tOEH
Output Enable
Hold Time (Note 1)
tOH
Output Hold Time From Addresses, CE# or
OE#, Whichever Occurs First (Note 1)
Notes:
1. Not 100% tested.
2. See Figure 11, on page 25 and Table 7 on page 25 for test specifications.
tRC
Addresses Stable
Addresses
tACC
CE#
tDF
tOE
OE#
tOEH
WE#
tCE
tOH
HIGH Z
HIGH Z
Output Valid
Outputs
RESET#
RY/BY#
0V
Figure 13.
26
Read Operations Timings
Am29SL400D
Rev. A Amend. +1 April 13, 2005
A D V A N C E
I N F O R M A T I O N
AC CHARACTERISTICS
Hardware Reset (RESET#)
Parameter
JEDEC
Std
Description
Test Setup
All Speed Options
Unit
tREADY
RESET# Pin Low (During Embedded
Algorithms) to Read or Write (See Note)
Max
20
µs
tREADY
RESET# Pin Low (NOT During Embedded
Algorithms) to Read or Write (See Note)
Max
500
ns
tRP
RESET# Pulse Width
Min
500
ns
tRH
RESET# High Time Before Read (See Note)
Min
200
ns
tRPD
RESET# Low to Standby Mode
Min
20
µs
tRB
RY/BY# Recovery Time
Min
0
ns
Note: Not 100% tested.
RY/BY#
CE#, OE#
tRH
RESET#
tRP
tReady
Reset Timings NOT during Embedded Algorithms
Reset Timings during Embedded Algorithms
tReady
RY/BY#
tRB
CE#, OE#
RESET#
tRP
Figure 14.
April 13, 2005 Rev. A Amend. +1
RESET# Timings
Am29SL400D
27
A D V A N C E
I N F O R M A T I O N
AC CHARACTERISTICS
Word/Byte Configuration (BYTE#)
Parameter
JEDEC
Speed Options
Std.
Description
90
100
120
Unit
tELFL/tELFH
CE# to BYTE# Switching Low or High
Max
tFLQZ
BYTE# Switching Low to Output HIGH Z
Max
50
50
60
ns
tFHQV
BYTE# Switching High to Output Active
Min
90
100
120
ns
10
ns
CE#
OE#
BYTE#
tELFL
BYTE#
Switching
from word
to byte
mode
Data Output
(DQ0–DQ14)
DQ0–DQ14
Address
Input
DQ15
Output
DQ15/A-1
Data Output
(DQ0–DQ7)
tFLQZ
tELFH
BYTE#
BYTE#
Switching
from byte
to word
mode
Data Output
(DQ0–DQ7)
DQ0–DQ14
Address
Input
DQ15/A-1
Data Output
(DQ0–DQ14)
DQ15
Output
tFHQV
Figure 15.
BYTE# Timings for Read Operations
CE#
The falling edge of the last WE# signal
WE#
BYTE#
tSET
(tAS)
tHOLD (tAH)
Note: Refer to the Erase/Program Operations, on page 29 for tAS and tAH specifications.
Figure 16.
28
BYTE# Timings for Write Operations
Am29SL400D
Rev. A Amend. +1 April 13, 2005
A D V A N C E
I N F O R M A T I O N
AC CHARACTERISTICS
Erase/Program Operations
Parameter
Speed Options
JEDEC
Std.
Description
90
100
120
Unit
tAVAV
tWC
Write Cycle Time (Note 1)
Min
90
100
120
ns
tAVWL
tAS
Address Setup Time
Min
tWLAX
tAH
Address Hold Time
Min
45
50
60
ns
tDVWH
tDS
Data Setup Time
Min
45
50
60
ns
tWHDX
tDH
Data Hold Time
Min
0
ns
tOES
Output Enable Setup Time
Min
0
ns
Read Recovery Time Before Write
(OE# High to WE# Low)
Min
0
ns
0
ns
tGHWL
tGHWL
tELWL
tCS
CE# Setup Time
Min
0
ns
tWHEH
tCH
CE# Hold Time
Min
0
ns
tWLWH
tWP
Write Pulse Width
Min
tWHWL
tWPH
Write Pulse Width High
Min
30
Byte
Typ
5
tWHWH1
tWHWH1
Programming Operation (Notes 1, 2)
Word
Typ
7
tWHWH2
tWHWH2
Sector Erase Operation (Notes 1, 2)
Typ
0.7
sec
tVCS
VCC Setup Time
Min
50
µs
tRB
Recovery Time from RY/BY#
Min
0
ns
Program/Erase Valid to RY/BY# Delay
Min
200
ns
tBUSY
45
50
60
ns
ns
µs
Notes:
1. Not 100% tested.
2. See Erase and Programming Performance, on page 37 for more information.
April 13, 2005 Rev. A Amend. +1
Am29SL400D
29
A D V A N C E
I N F O R M A T I O N
AC CHARACTERISTICS
Program Command Sequence (last two cycles)
tAS
tWC
Addresses
Read Status Data (last two cycles)
555h
PA
PA
PA
tAH
CE#
tCH
OE#
tWHWH1
tWP
WE#
tWPH
tCS
tDS
tDH
A0h
Data
PD
Status
tBUSY
DOUT
tRB
RY/BY#
VCC
tVCS
Notes:
1. PA = program address, PD = program data, DOUT is the true data at the program address.
2. Illustration shows device in word mode.
Figure 17.
30
Program Operation Timings
Am29SL400D
Rev. A Amend. +1 April 13, 2005
A D V A N C E
I N F O R M A T I O N
AC CHARACTERISTICS
Erase Command Sequence (last two cycles)
tAS
tWC
2AAh
Addresses
Read Status Data
VA
SA
VA
555h for chip erase
tAH
CE#
tCH
OE#
tWP
WE#
tWPH
tCS
tWHWH2
tDS
tDH
Data
55h
In
Progress
30h
Complete
10 for Chip Erase
tBUSY
tRB
RY/BY#
tVCS
VCC
Notes:
1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).
2. Illustration shows device in word mode.
Figure 18.
April 13, 2005 Rev. A Amend. +1
Chip/Sector Erase Operation Timings
Am29SL400D
31
A D V A N C E
I N F O R M A T I O N
AC CHARACTERISTICS
tRC
Addresses
VA
VA
VA
tACC
tCE
CE#
tCH
tOE
OE#
tOEH
tDF
WE#
tOH
High Z
DQ7
Complement
Complement
DQ0–DQ6
Status Data
Status Data
Valid Data
True
High Z
Valid Data
True
tBUSY
RY/BY#
Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle.
Figure 19.
Data# Polling Timings (During Embedded Algorithms)
tRC
Addresses
VA
VA
VA
VA
tACC
tCE
CE#
tCH
tOE
OE#
tOEH
tDF
WE#
tOH
High Z
DQ6/DQ2
tBUSY
Valid Status
Valid Status
(first read)
(second read)
Valid Status
Valid Data
(stops toggling)
RY/BY#
Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status
read cycle, and array data read cycle.
Figure 20.
32
Toggle Bit Timings (During Embedded Algorithms)
Am29SL400D
Rev. A Amend. +1 April 13, 2005
A D V A N C E
I N F O R M A T I O N
AC CHARACTERISTICS
Enter
Embedded
Erasing
Erase
Suspend
Erase
WE#
Enter Erase
Suspend Program
Erase Suspend
Read
Erase
Resume
Erase
Suspend
Program
Erase
Erase Suspend
Read
Erase
Complete
DQ6
DQ2
Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an
erase-suspended sector.
Figure 21.
DQ2 vs. DQ6
Temporary Sector Unprotect
Parameter
JEDEC
Std
Description
All Speed Options
Unit
tVIDR
VID Rise and Fall Time
Min
500
ns
tRSP
RESET# Setup Time for Temporary Sector
Unprotect
Min
4
µs
10 V
RESET#
0 or 1.8 V
0 or 1.8 V
tVIDR
tVIDR
Program or Erase Command Sequence
CE#
WE#
tRSP
RY/BY#
Figure 22.
April 13, 2005 Rev. A Amend. +1
Temporary Sector Unprotect Timing Diagram
Am29SL400D
33
A D V A N C E
I N F O R M A T I O N
AC CHARACTERISTICS
VID
VIH
RESET#
SA, A6,
A1, A0
Valid*
Valid*
Sector Protect/Unprotect
Data
60h
Valid*
Verify
60h
40h
Status
Sector Protect: 150 µs
Sector Unprotect: 15 ms
1 µs
CE#
WE#
OE#
* For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.
Figure 23.
34
Sector Protect/Unprotect Timing Diagram
Am29SL400D
Rev. A Amend. +1 April 13, 2005
A D V A N C E
I N F O R M A T I O N
AC CHARACTERISTICS
Alternate CE# Controlled Erase/Program Operations
Parameter
Speed Options
JEDEC
Std.
Description
90
100
120
Unit
tAVAV
tWC
Write Cycle Time (Note 1)
Min
90
100
120
ns
tAVEL
tAS
Address Setup Time
Min
tELAX
tAH
Address Hold Time
Min
45
50
60
ns
tDVEH
tDS
Data Setup Time
Min
45
50
60
ns
tEHDX
tDH
Data Hold Time
Min
0
ns
tOES
Output Enable Setup Time
Min
0
ns
tGHEL
tGHEL
Read Recovery Time Before Write
(OE# High to WE# Low)
Min
0
ns
tWLEL
tWS
WE# Setup Time
Min
0
ns
tEHWH
tWH
WE# Hold Time
Min
0
ns
tELEH
tCP
CE# Pulse Width
Min
tEHEL
tCPH
CE# Pulse Width High
Min
30
Typ
5
tWHWH1
Programming Operation
(Notes 1, 2)
Byte
tWHWH1
Word
Typ
7
tWHWH2
tWHWH2
Sector Erase Operation (Notes 1, 2)
Typ
0.7
0
45
50
ns
60
ns
ns
µs
sec
Notes:
1. Not 100% tested.
2. See Erase and Programming Performance, on page 37 for more information.
April 13, 2005 Rev. A Amend. +1
Am29SL400D
35
A D V A N C E
I N F O R M A T I O N
AC CHARACTERISTICS
555 for program
2AA for erase
PA for program
SA for sector erase
555 for chip erase
Data# Polling
Addresses
PA
tWC
tAS
tAH
tWH
WE#
tGHEL
OE#
tCP
CE#
tWS
tWHWH1 or 2
tCPH
tBUSY
tDS
tDH
DQ7#
Data
tRH
A0 for program
55 for erase
DOUT
PD for program
30 for sector erase
10 for chip erase
RESET#
RY/BY#
Notes:
1. PA = program address, PD = program data, DQ7# = complement of the data written, DOUT = data written
2. Figure indicates the last two bus cycles of command sequence.
3. Word mode address used as an example.
Figure 24.
36
Alternate CE# Controlled Write Operation Timings
Am29SL400D
Rev. A Amend. +1 April 13, 2005
A D V A N C E
I N F O R M A T I O N
ERASE AND PROGRAMMING PERFORMANCE
Parameter
Typ (Note 1)
Max (Note 2)
Unit
Sector Erase Time
0.7
15
s
Chip Erase Time
38
Byte Programming Time
10
300
µs
Word Programming Time
12
360
µs
Chip Programming Time
Byte Mode
5
40
s
(Note 3)
Word Mode
3.5
30
s
s
Comments
Excludes 00h programming
prior to erasure (Note 4)
Excludes system level
overhead (Note 5)
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 1.8 V VCC, 1,000,000 cycles. Additionally, programming
typicals assume checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 1.8 V, 1,000,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program
faster than the maximum program times listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.
5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 5
on page 17 for further information on command definitions.
6. The device has a minimum guaranteed erase and program cycle endurance of 1,000,000 cycles.
LATCHUP CHARACTERISTICS
Description
Min
Max
Input voltage with respect to VSS on all pins except I/O pins
(including A9, OE#, and RESET#)
–1.0 V
11.0 V
Input voltage with respect to VSS on all I/O pins
–0.5 V
VCC + 0.5 V
–100 mA
+100 mA
VCC Current
Includes all pins except VCC. Test conditions: VCC = 1.8 V, one pin at a time.
TSOP PIN AND BGA PACKAGE CAPACITANCE
Parameter Symbol
Parameter Description
CIN
Input Capacitance
COUT
Output Capacitance
CIN2
Control Pin Capacitance
Test Setup
VIN = 0
VOUT = 0
VIN = 0
Typ
Max
Unit
TSOP
6
7.5
pF
Fine-pitch BGA
4.2
5.0
pF
TSOP
8.5
12
pF
Fine-pitch BGA
5.4
6.5
pF
TSOP
7.5
9
pF
Fine-pitch BGA
3.9
4.7
pF
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
DATA RETENTION
Parameter
Test Conditions
Min
Unit
150°C
10
Years
125°C
20
Years
Minimum Pattern Data Retention Time
April 13, 2005 Rev. A Amend. +1
Am29SL400D
37
A D V A N C E
I N F O R M A T I O N
PHYSICAL DIMENSIONS
FBA048—48-Ball Fine-Pitch Ball Grid Array (FBGA) 6 x 8 mm Package
Dwg rev AF; 10/99
38
Am29SL400D
Rev. A Amend. +1 April 13, 2005
A D V A N C E
I N F O R M A T I O N
REVISION SUMMARY
Revision A (February 12, 2004)
Valid Combination Table,
Initial release.
Global
Added package designators for Pb-free options.
Added Colophon.
Revision A+1 (April 13, 2005)
Updated Trademark.
Ordering Information
Added Cover Page.
Added Commercial and Industrial Pb-free options.
Colophon
The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the
public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for
any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion LLC will not be liable
to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor
devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design
measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating
conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign
Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior authorization by the respective government entity will be required for export of those products.
Trademarks
Copyright ©2003-2005 Advanced Micro Devices, Inc. All rights reserved.
AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.
ExpressFlash is a trademark of Advanced Micro Devices, Inc.
Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
April 13, 2005 Rev. A Amend. +1
Am29SL400D
39