Sony CXD1265 Ccd camera timing generator Datasheet

CXD1265R
CCD Camera Timing Generator
Description
The CXD1265R generates the timing pulses
required by the CCD image sensors as well as
signal processing circuits.
64 pin LQFP (Plastic)
Features
• NTSC and PAL compatible
• Compatible with digital and analog camera
systems
• Black-and-white mode compatible
(EIA/CCIR compatible)
• Electronic shutter function
• H-driver
• Standby function
• Compatible with field/frame accumulation
modes∗1, ∗2
∗1 Characteristics of CCD image sensor are
guaranteed by field accumulation.
∗2 Low speed shutter can not be used during frame
accumulation mode.
Absolute Maximum Ratings (Ta = 25°C)
• Supply voltage
VDD Vss – 0.5 to +7.0 V
• Input voltage
VI Vss – 0.5 to VDD + 0.5 V
• Output voltage
VO Vss – 0.5 to VDD + 0.5 V
• Operating temperature Topr
–20 to +75
°C
• Storage temperature Tstg
–55 to +150
°C
• Supply voltage
VEE
–5 to Vss
V
• Allowable power dissipation
PD
500
mW
Applications
CCD cameras
Recommended Operating Conditions
• Supply voltage
VDD
5.0 ± 0.25
• Operating temperature Topr
–20 to +75
Structure
Silicon gate CMOS IC
V
°C
Applicable CCD Image Sensors
ICX038BNA, ICX038BNB, ICX038BLA
ICX039BNA, ICX039BNB, ICX039BLA
ICX058AK, ICX058AKB, ICX058AL
ICX059AK, ICX059AKB, ICX059AL
Block Diagram
VSS
8
28 40
VDD
VEE
24 25 56
21
15 16 17 18 19 20
62
60
MODE
SET
VD INITIALIZE
11
12
SYNC
GEN
13
14
59
HD INITIALIZE
57
63
AA
AA
AA
AA
AAA
AA
AA AAA
AAA
ADR . COUNT
ADR . COUNT
ADR . COUNT
H – ROM
V – ROM
ROG – ROM
1/2
64
1
LATCH
LATCH
GATE
GATE
LATCH
23
36
GATE
2
41
CONTROLLER
61
HTSG
42
43
44
45
46
22
4
HIGH-SPEED
PULSE
GENERATION
CIRCUIT
DRIVER
DECODER
5
MICROCOMPUTER
6
GATE
COUNTER
SHUT
ROM
DECODER
7
9
37
38 39
23 26 27
3
10 47 48 49 50 51 52 53
54 29
30 31 32 33 34 35 58 55
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E92611C52-ST
CXD1265R
Pin Description
Pin
No.
Symbol
I/O
1
OSCO
O
Inverter output for oscillation.
2
OSCI
I
Inverter input for oscillation.
3
EF
I
Not used. (With pull-up resistor)
4
ED0
I
Shutter speed setting. Strobe input for serial mode. (With pull-up resistor)
5
ED1
I
Shutter speed setting. Clock input for serial mode. (With pull-up resistor)
6
ED2
I
Shutter speed setting. Data input for serial mode. (With pull-up resistor)
7
SMD1
I
Shutter mode setting. (With pull-up resistor)
8
Vss
9
SMD2
I
Shutter mode setting. (With pull-up resistor)
10
XVCT
O
Not used. (Open)
11
D1
I
Fix at Low in normal operation. (With pull-down resistor)
12
D2
I
13
D3
I
Low: Color, High: Black-and-white. (With pull-down resistor)
Low: Field readout, High: Frame readout∗. (With pull-down resistor)
14
D4
I
Low: NTSC/EIA, High: PAL/CCIR. (With pull-down resistor)
15
A5
O
Not used. (Open)
16
A4
O
Not used. (Open)
17
A3
O
Not used. (Open)
18
A0
O
Not used. (Open)
19
A1
O
Not used. (Open)
20
A2
O
Not used. (Open)
21
VEE
—
GND
22
RG
O
Reset gate pulse output.
23
NC
—
Not used. (Open)
24
VDD
—
Power supply.
25
VDD
—
Power supply for H1 and H2.
26
H1
O
Clock output for CCD horizontal register drive.
27
H2
O
Clock output for CCD horizontal register drive.
28
Vss
—
GND for H1 and H2.
29
XSUB
O
CCD discharge pulse output.
30
XV2
O
Clock output for CCD vertical register drive.
31
XV1
O
Clock output for CCD vertical register drive.
32
XSG1
O
CCD sensor charge readout pulse output.
33
XV3
O
Clock output for CCD vertical register drive.
34
XSG2
O
CCD sensor charge readout pulse output.
—
Description
GND
35
Clock output for CCD vertical register drive.
XV4
O
∗ Characteristics of CCD image sensor are guaranteed by field accumulation.
–2–
CXD1265R
Pin
No.
Symbol
36
TEST2
I
Test input. Set at Low in normal operation.
37
MCK
O
NTSC: 910fH, PAL: 908fH. Clock output.
38
XSHP
O
Precharge level sample-and-hold pulse.
39
XSHD
O
Data sample-and-hold pulse.
40
Vss
—
GND
41
XSP1
O
Color separation sample-and-hold pulse. Halted for black-and-white mode.
42
XSP2
O
Color separation sample-and-hold pulse. Halted for black-and-white mode.
43
XSH1/
SHP
O
Switching sample-and-hold pulse/precharge level sample-and-hold pulse
(black-and-white mode).
44
XSH2/
SHD
O
Switching sample-and-hold pulse/data sample-and-hold pulse
(black-and-white mode).
45
XDL1
O
Delay line clock output. Halted for black-and-white mode.
46
XDL2
O
Delay line clock output. Halted for black-and-white mode.
47
BFG
O
Pulse output for chroma modulator in encoder. Halted for black-and-white mode.
48
CLP1
O
Clamp pulse output.
49
CLP2
I/O
Clamp pulse output. When GM is set at High, standby mode switching input.
50
CLP3
I/O
Clamp pulse output. When GM is set at High, standby mode switching input.
51
CLP4
O
Clamp pulse output.
52
PBLK
O
Blanking cleaning pulse output.
53
ID
O
Line identification output. Halted for black-and-white mode.
54
WEN
O
Write enable output for low-speed shutter operation.
55
GM
I
Low: Analog signal processing, High: Digital signal processing. (With pull-down resistor)
56
VDD
—
Power supply.
57
CL
O
NTSC/EIA: 910fH, PAL/CCIR: 908fH. Clock output.
58
PS
I
Switching for electronic shutter speed input method. (With pull-up resistor)
Low: Serial input, High: Parallel input.
59
HD
I
Horizontal synchronizing signal input.
60
VD
I
Vertical synchronizing signal input. (During Low, 9H for NTSC and 7.5H for PAL)
61
HTSG
I
Control input for XSG1 and XSG2. (With pull-up resistor)
Low: XSG1, XSG2 halted, High: XSG1, XSG2 generated.
62
TEST
I
Test input. Set at Low in normal operation. (With pull-down resistor)
63
XCK
O
NTSC/EIA: 1820fH, PAL/CCIR: 1816fH. Clock output.
64
CK
I
NTSC/EIA: 1820fH, PAL/CCIR: 1816fH. Clock input.
I/O
Description
–3–
CXD1265R
Electrical Characteristics
DC Characteristics
Item
(VDD = 5V ± 0.25V, Topr = –20 to +75°C)
Symbol
Conditions
Min.
Typ.
Max.
Unit
5.0
5.25
V
Supply voltage
VDD
4.75
Input voltage 1
VIH1
0.7VDD
V
(Input pins other than those below) VIL1
Input voltage 2
(Pins 59 and 60)
VIH2
Output voltage 1
VOH1
0.3VDD
2.2
(Output pins other than those below) VOL1
0.8
VDD – 0.5
0.4
VOH2
IOH = –4mA
VOL2
IOL = 8mA
Output voltage 3
(Pins 26 and 27)
VOH3
IOH = –8mA
VOL3
IOL = 8mA
Output voltage 4
(Pin 1)
VOH4
IOH = –1mA
VOL4
IOL = 1mA
Feedback resistor
RFB
VIN = Vss or VDD
500k
Pull-up resistor
RPU
VIL = 0V
Pull-down resistor
RPD
VIH = VDD
Current consumption
IDD
VDD = 5V
ICX058AK in normal
operating state
VDD – 0.5
VDD – 0.5
Min.
VDD/2
Typ.
V
V
VDD/2
V
2M
5M
Ω
40k
100k
250k
Ω
40k
100k
250k
Ω
74
Max.
Unit
Input pin capacitance
CIN
9
pF
Output pin capacitance
COUT
11
pF
I/O pin capacitance
CI/O
11
pF
–4–
V
V
0.4
(VDD = VI = 0V, fM = 1MHz)
Symbol
V
V
0.4
∗ Power consumption: 370mW typ., ICX058 load (in normal operating state)
I/O Pin Capacitances
V
V
IOL = 4mA
Output voltage 2
(Pins 22, 37, 38, 39, 57, and 63)
Item
V
VIL2
IOH = –2mA
V
mA
CXD1265R
Description of Operation
1. Mode Control
Symbol
GM∗2
Pin No.
L
H
55
Analog signal processing
Digital signal processing
PS
58
Serial shutter
speed setting
Parallel shutter
speed setting
EF
3
HTSG
61
D1
D2∗2
11
12
Color
D3
13
Field readout
Black-and-white
Frame readout∗1
D4
14
NTSC/EIA
PAL/CCIR
Fix at High in normal operation
XSG1, 2
OFF
XSG1, 2
ON
Fix at Low in normal operation
∗1 Characteristics of CCD image sensor are guaranteed by field accumulation.
∗2 Operation with GM = High and D2 = High (black-and-white digital signal processing) cannot be used.
–5–
CXD1265R
2. Changes in I/O Signals in Each Mode
Symbol
Pin No.
Analog color
Digital color 1
Digital color 2
Analog B/W
GM
55
L
H
H
L
D2
12
L
L
L
H
TEST2
36
L
L
H
L
XSP1
41
Color separation
sample-and-hold
pulse output
Halted at High
Color separation
sample-and-hold
pulse output
Halted at High
XSP2
42
Color separation
sample-and-hold
pulse output
Halted at High
Color separation
sample-and-hold
pulse output
Halted at High
XSH1
43
Switching sampleand-hold pulse
output
Halted at Low
Switching sampleand-hold pulse
output
Precharge level
sample-and-hold
pulse output
XSH2
44
Switching sampleand-hold pulse
output
Halted at Low
Switching sampleand-hold pulse
output
Data sample-andhold pulse output
XDL1
45
Delay line clock
Halted at High
Halted at High
Halted at High
XDL2
46
Delay line clock
Halted at Low
Halted at Low
Halted at Low
BFG
47
Burst flag gate
pulse output
Burst flag gate
pulse output
(normally not used)
Burst flag gate
pulse output
(normally not used)
Halted at Low
Standby control input
Low: Standby
High: Normal
operation
Standby control∗
Low: All circuits
halted for
standby mode
High: Only CL
output for
standby mode
Standby control input
Low: Standby
Clamp pulse output
High: Normal
operation
Standby control∗
Low: All circuits
halted for
Clamp pulse output
standby mode
(phase change)
High: Only CL
output for
standby mode
Line identification
output
Line identification
output
CLP2
49
Clamp pulse output
CLP3
50
Clamp pulse output
ID
53
Line identification
output
Halted at Low
∗ When CLP2 = High, normal operation occurs regardless of whether CLP3 is high or low.
(Mode combinations other than those shown above cannot be used.)
Note) In the standby mode described above, XCK, XSG1, XSG2, XV1, XV2, XV3, XV4, XSUB, H1, H2, RG,
XSHD, XSHP, XSP1, XSP2, XSH1, XSH2, XDL1, and XDL2 pins are halted at Low. MCK, CLP1, CLP4,
PBLK, ID, XVCT, WEN, BFG, A0, A1, A2, A3, A4, and A5 pins are halted at the state just before
standby.
–6–
CXD1265R
3. Electronic Shutter
<Shutter Modes>
SMD1
SMD2
L
L
L
H
H
L
H
H
Flickerless: Eliminates fluorescent frequency-induced flicker.
High-speed shutter: Shutter speed faster than 1/60 (NTSC), 1/50 (PAL)
Low-speed shutter: Shutter speed slower than 1/60 (NTSC), 1/50 (PAL)
No shutter operation
<Shutter Mode and Speed Setting Method>
PS = High: Parallel input; set by ED0 to ED2, SMD1, and SMD2.
PS = Low: Serial input; set by inputting ED0 (strobe), ED1 (clock), and ED2 (data) to each pin.
3-1. Parallel input (PS = H)
Shutter Speed Compatibility Chart
Mode
OFF
Flickerless
High-speed
shutter
Low-speed
shutter∗
NTSC/PAL
SMD1
SMD2
ED0
ED1
ED2
Shutter speed
X
H
H
X
X
X
Shutter off
NTSC
L
L
X
X
X
1/100 (S)
PAL
L
L
X
X
X
1/120 (S)
NTSC
L
H
H
H
H
1/60 (S)
PAL
L
H
H
H
H
1/50 (S)
X
L
H
L
H
H
1/125 (S)
X
L
H
H
L
H
1/250 (S)
X
L
H
L
L
H
1/500 (S)
X
L
H
H
H
L
1/1000 (S)
X
L
H
L
H
L
1/2000 (S)
X
L
H
H
L
L
1/4000 (S)
X
L
H
L
L
L
1/10000 (S)
X
H
L
H
H
H
2FLD
X
H
L
L
H
H
4FLD
X
H
L
H
L
H
6FLD
X
H
L
L
L
H
8FLD
X
H
L
H
H
L
10FLD
X
H
L
L
H
L
12FLD
X
H
L
H
L
L
14FLD
X
H
L
L
L
L
16FLD
∗ During frame accumulation mode, low speed shutter data set to ED0 to ED2 are all invalid.
Shutter speed is 1/30s for NTSC; 1/25s for PAL.
–7–
CXD1265R
3-2. serial input (PS=L)
For serial input (PS = L), SMD1 and SMD2 bits within ED2 (DATA) take priority over SMD1 (Pin 7) and SMD2
(Pin 9) pins as SMD1 and SMD2 (shutter mode control).
In this case, control by SMD1 and SMD2 pins is invalid.
ED1 (CLK)
ED2 (DATA)
D0
D1
D2
D3
D4
D5
D6
D7
D8
SMD1
SMD2
Dummy
ED0 (STB)
ED2 data is latched to the register at the rise of ED1, and transferred to the within during the Low period of ED0.
–8–
CXD1265R
AC Characteristics
ED2
ts2
th2
tw1
tw1
ED1
ts1
ts0
ED0
tw0
Symbol
tS2
th2
tS1
tW0
tS0
tW1
Min.
Max.
ED2 set-up time, activated by the rising edge of ED1
20ns
—
ED2 hold time, activated by the rising edge of ED1
20ns
—
ED1 rising set-up time, activated by the rising edge of ED0
20ns
—
ED0 pulse width
20ns
50µs
ED0 rising set-up time, activated by the rising edge of ED1
20ns
—
ED1 pulse width (serial input)
20ns
—
3-4. Low-speed shutter timing chart
(During field accumulation mode)
(ED2 : ED1 : ED0 = H : H : H)
O
E
O
E
O
E
O
E
O
E
O
E
O
E
VD
XSG1, 2
WEN
(ED2 : ED1 : ED0 = H : H : L)
XSG1, 2
WEN
(During frame accumulation mode)
(ED2 : ED1 : ED0 = X : X : X)
XSG1, 2
WEN
(Fixed at H)
–9–
CXD1265R
3-5. Shutter speed calculation formula
1. High-speed shutter
• NTSC (L16 = load value)
T = [26210 – (1FF16 – L16) ] × 63.56µs + 34.9µs
• PAL (L16= load value)
T = [31210 – (1FF16 – L16) ] × 64.00µs + 35.0µs
NTSC
Load value
Shutter speed
PAL
Calculated value
Load value
Shutter speed
Calculated value
0FA16
1/10000
1/10156
0C816
1/10000
1/10101
0FC16
1/4000
1/4433
0CA16
1/4000
1/4405
10016
1/2000
1/2084
0CE16
1/2000
1/2070
10816
1/1000
1/1012
0D616
1/1000
1/1005
11816
1/500
1/499
0E616
1/500
1/495
13716
1/250
1/252
10516
1/250
1/250
17616
1/125
1/125
14316
1/125
1/125
19616
1/100
1/100
14916
1/120
1/120
2. Low-speed shutter (Valid during field accumulation mode only)
Shutter speed calculation formula
N = 2 × (1FF16 – L16) FLD
However, "FF" cannot be used as the load value.
Load value
Shutter speed (FLD)
1FE16
2
1FD16
4
:
:
:
:
10116
508
10016
510
– 10 –
– 11 –
CLP4
CLP3
CLP2
CLP1
PBLK
CCD
XV4
XV3
XV2
XV1
ID
XSG2
XSG1
HD
BLK/VD
FLD
494
493
However, ID is halted for black-and-white mode
Timing Chart (1)
NTSC vertical direction
2 4 6 8
1 3 5 7 9
493
492 494
1 3 5 7 9
2 4 6 8 10
CXD1265R
– 12 –
CLP4
CLP3
CLP2
CLP1
PBLK
CCD
XV4
XV3
XV2
XV1
ID
XSG2
XSG1
HD
BLK/VD
FLD
However, ID is halted for black-and-white mode
582
581
Timing Chart (2)
PAL vertical direction
2 4 6 8
1 3 5 7 9
582
1 3 5 7 9
2 4 6 8 10
CXD1265R
– 13 –
0
7
14
10
(GM = L, D2=L, TEST2 = L)
BFG
ID
PBLK
CLP4
CLP3
CLP2
CLP1
XSUB
XV4
XV3
XV2
XV1
XDL2
XDL1
XSH2
XSH1
XSP2
XSP1
XSHD
XSHP
RG
H1
CL
BLK/HD
20
31
31
30
Timing Chart (3)
NTSC horizontal direction, analog color
35
38
35
44
40
51
53
50
71
70
75
81
80
80
80
86
89
90
98
96
103
100
114
113
110
120
135
130
Black painted portions indicate the optical black output timing of CCD.
62
60
140
140
140
140
155
150
160
170
180
CXD1265R
– 14 –
BFG
ID
PBLK
CLP4
CLP3
CLP2
CLP1
XSUB
XV4
XV3
XV2
0
7
10
(GM = H, D2 = L, TEST2 = L)
INPUT PIN
L
XDL2
XV1
L
H
L
XSH1
XDL1
H
XSP2
XSH2
H
XSP1
XSHD
XSHP
RG
H1
CL
BLK/HD
20
31
31
30
35
Timing Chart (4)
NTSC horizontal direction, digital color 1
35
44
40
53
50
71
70
81
80
80
80
86
89
90
96
98
103
100
114
113
110
120
135
130
Black painted portions indicate the optical black output timing of CCD.
62
60
140
140
140
140
155
150
160
170
180
CXD1265R
– 15 –
0
7
10
(GM = H, D2 = L, TEST2 = H)
BFG
ID
PBLK
CLP4
CLP3
CLP2
CLP1
XSUB
XV4
XV3
XV2
INPUT PIN
L
XDL2
XV1
H
XDL1
XSH2
XSH1
XSP2
XSP1
XSHD
XSHP
RG
H1
CL
BLK/HD
20
31
31
30
35
Timing Chart (5)
NTSC horizontal direction, digital color 2
35
44
40
53
50
71
70
81
80
80
80
86
89
90
98
96
103
100
114
113
110
120
135
130
Black painted portions indicate the optical black output timing of CCD.
62
60
140
140
140
140
155
150
160
170
180
CXD1265R
H
XSP2
L
XDL2
– 16 –
L
BFG
–6
0
7
7
14
10
(GM = L, D2 = H, TEST2 = L)
L
ID
PBLK
CLP4
CLP3
CLP2
CLP1
XSUB
XV4
XV3
XV2
XV1
H
XDL1
XSH2
XSH1
H
XSP1
XSHD
XSHP
RG
H1
CL
BLK/HD
20
31
31
31
30
35
38
35
44
40
Timing Chart (6)
EIA horizontal direction, analog black-and-white
53
50
71
70
80
80
80
89
90
98
103
100
114
113
110
120
135
130
Black painted portions indicate the optical black output timing of CCD.
62
60
140
140
140
149
150
160
170
180
CXD1265R
– 17 –
0
7
14
10
(GM = L, D2 = L, TEST2 = L)
BFG
ID
PBLK
CLP4
CLP3
CLP2
CLP1
XSUB
XV4
XV3
XV2
XV1
XDL2
XDL1
XSH2
XSH1
XSP2
XSP1
XSHD
XSHP
RG
H1
CL
BLK/HD
20
31
31
Timing Chart (7)
PAL horizontal direction, analog color
30
35
38
35
40
46
51
50
57
68
70
75
81
79
80
86
90
90
90
96
101
100
112
110
117
128
126
120
130
Black painted portions indicate the optical black output timing of CCD.
60
140
149
154
154
154
150
160
170
180
CXD1265R
– 18 –
0
7
10
(GM = H, D2 = L, TEST2 = L)
BFG
ID
PBLK
CLP4
CLP3
CLP2
CLP1
XSUB
XV4
XV3
XV2
INPUT PIN
L
XDL2
XV1
L
H
L
XSH1
XDL1
H
XSP2
XSH2
H
XSP1
XSHD
XSHP
RG
H1
CL
BLK/HD
20
31
31
30
Timing Chart (8)
PAL horizontal direction, digital color 1
35
35
40
46
50
57
68
70
81
79
80
86
90
90
90
96
101
100
112
110
117
128
126
120
130
Black painted portions indicate the optical black output timing of CCD.
60
140
149
154
154
154
150
160
170
180
CXD1265R
– 19 –
0
7
10
(GM = H, D2 = L, TEST2 = H)
BFG
ID
PBLK
CLP4
CLP3
CLP2
CLP1
XSUB
XV4
XV3
XV2
INPUT PIN
L
XDL2
XV1
H
XDL1
XSH2
XSH1
XSP2
XSP1
XSHD
XSHP
RG
H1
CL
BLK/HD
20
31
31
30
Timing Chart (9)
PAL horizontal direction, digital color 2
35
35
40
46
50
57
68
70
81
79
80
86
90
90
90
96
101
100
112
110
117
128
126
120
130
Black painted portions indicate the optical black output timing of CCD.
60
140
149
154
154
154
150
160
170
180
CXD1265R
H
XSP2
L
XDL2
– 20 –
L
BFG
–6
0
7
7
14
10
(GM = L, D2 = H, TEST2 = L)
L
ID
PBLK
CLP4
CLP3
CLP2
CLP1
XSUB
XV4
XV3
XV2
XV1
H
XDL1
XSH2
XSH1
H
XSP1
XSHD
XSHP
RG
H1
CL
BLK/HD
20
31
31
31
30
35
38
35
40
46
Timing Chart (10)
CCIR horizontal direction, analog black-and-white
50
57
68
70
79
80
90
90
90
101
100
112
110
117
128
126
120
130
Black painted portions indicate the optical black output timing of CCD.
60
140
149
154
154
150
164
160
170
180
CXD1265R
– 21 –
EVEN
ODD
HD
XSG2
XSG1
XV4
XV3
XV2
XV1
XV4
XV3
XV2
XV1
XV4
XV3
XV2
XV1
XV4
XV3
XV2
XV1
Frame readout
EVEN
ODD
Field readout
4-1. Timing Chart of Readout (NTSC/EIA)
578
22
3
3
36
36
33
36
3
36
36
Unit: Number of clocks (1ck = 69.84ns)
36
CXD1265R
– 22 –
EVEN
ODD
HD
XV4
XV3
XV2
XV1
XV4
XV3
XV2
XV1
XV4
XV3
XV2
XV1
XV4
XV3
XV2
XV1
XSG2
XSG1
Frame readout
EVEN
ODD
Field readout
4-2. Timing Chart of Readout (PAL/CCIR)
589
22
3
3
36
36
33
36
3
36
36
Unit: Number of clocks (1ck = 70.48ns)
36
CXD1265R
CXD1265R
5. High-speed Clock Timing Chart
CK
CL
H1
H2
RG
XSHP
XSHD
XSP1
XSP2
XSH1
XSH2
For color mode
XSH1
(SHP)
XSH2
For
black-and-white
mode
(SHD)
XDL1
XDL2
MCK
∗ For black and white mode, XSP1, XSP2, XDL1, and XDL2 are halted.
– 23 –
CXD1265R
Package Outline
Unit: mm
64PIN LQFP (PLASTIC)
12.0 ± 0.2
∗
10.0 ± 0.1
48
33
32
64
17
(0.22)
0.5 ± 0.2
(11.0)
49
A
1
0.5 ± 0.08
+ 0.08
0.18 – 0.03
16
+ 0.2
1.5 – 0.1
+ 0.05
0.127 – 0.02
0.1
0° to 10°
0.5 ± 0.2
0.1 ± 0.1
NOTE: Dimension “∗” does not include mold protrusion.
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY / PHENOL RESIN
SONY CODE
LQFP-64P-L01
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
∗QFP064-P-1010-A
LEAD MATERIAL
42 ALLOY
PACKAGE WEIGHT
0.3g
JEDEC CODE
– 24 –
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