Revised April 2000 DM74LS161A • DM74LS163A Synchronous 4-Bit Binary Counters General Description These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting designs. The DM74LS161A and DM74LS163A are 4-bit binary counters. The carry output is decoded by means of a NOR gate, thus preventing spikes during the normal counting mode of operation. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enable inputs and internal gating. This mode of operation eliminates the output counting spikes which are normally associated with asynchronous (ripple clock) counters. A buffered clock input triggers the four flip-flops on the rising (positive-going) edge of the clock input waveform. These counters are fully programmable; that is, the outputs may be preset to either level. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable input. The clear function for the DM74LS161A is asynchronous; and a low level at the clear input sets all four of the flip-flop outputs LOW, regardless of the levels of clock, load, or enable inputs. The clear function for the DM74LS163A is synchronous; and a low level at the clear inputs sets all four of the flip-flop outputs LOW after the next clock pulse, regardless of the levels of the enable inputs. This synchronous clear allows the count length to be modified easily, as decoding the maximum count desired can be accomplished with one external NAND gate. The gate output is connected to the clear input to synchronously clear the counter to all low outputs. The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. Instrumental in accomplishing this function are two count-enable inputs and a ripple carry output. Both count-enable inputs (P and T) must be HIGH to count, and input T is fed forward to enable the ripple carry output. The ripple carry output thus enabled will produce a highlevel output pulse with a duration approximately equal to the high-level portion of the QA output. This high-level overflow ripple carry pulse can be used to enable successive cascaded stages. HIGH-to-LOW level transitions at the enable P or T inputs may occur, regardless of the logic level of the clock. These counters feature a fully independent clock circuit. Changes made to control inputs (enable P or T or load) that will modify the operating mode have no effect until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) will be dictated solely by the conditions meeting the stable set-up and hold times. Features ■ Synchronously programmable ■ Internal look-ahead for fast counting ■ Carry output for n-bit cascading ■ Synchronous counting ■ Load control line ■ Diode-clamped inputs ■ Typical propagation time, clock to Q output 14 ns ■ Typical clock frequency 32 MHz ■ Typical power dissipation 93 mW Ordering Code: Order Number DM74LS161AM Package Number Package Description M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow DM74LS161AN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide DM74LS163AM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow DM74LS163AN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. © 2000 Fairchild Semiconductor Corporation DS006397 www.fairchildsemi.com DM74LS161A • DM74LS163A Synchronous 4-Bit Binary Counters August 1986 DM74LS161A • DM74LS163A Connection Diagram Logic Diagram DM74LS163A The DM74LS161A is similar, however, the clear buffer is connected directly to the flip-flops. www.fairchildsemi.com 2 DM74LS161A • DM74LS163A Parameter Measurement Information Switching Time Waveforms The input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, duty cycle ≤ 50%, ZOUT ≈ 50Ω, tR ≤ 10 ns, tF ≤ 10 ns. Vary PRR to measure fMAX. Outputs QD and carry are tested at tN+16 where tN is the bit time when all outputs are LOW. VREF = 1.5V. Switching Time Waveforms The input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, duty cycle ≤ 50%, ZOUT ≈ 50Ω, tR ≤ 6 ns, tF ≤ 6 ns. Vary PRR to measure fMAX. Enable P and enable T setup times are measured at tN+0. VREF = 1.3V. 3 www.fairchildsemi.com DM74LS161A • DM74LS163A Timing Diagram LS161A, LS163A Synchronous Binary Counters Typical Clear, Preset, Count and Inhibit Sequences Sequence: (1) Clear outputs to zero (2) Preset to binary twelve (3) Count to thirteen, fourteen, fifteen, zero, one, and two (4) Inhibit www.fairchildsemi.com 4 Supply Voltage Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. 7V Input Voltage 7V 0°C to +70°C Operating Free Air Temperature Range −65°C to +150°C Storage Temperature Range DM74LS161A Recommended Operating Conditions Symbol Parameter Min Nom Max Units 4.75 5 5.25 V LOW Level Input Voltage 0.8 V mA VCC Supply Voltage VIH HIGH Level Input Voltage VIL 2 V IOH HIGH Level Output Current −0.4 IOL LOW Level Output Current 8 mA fCLK Clock Frequency (Note 2) 25 MHz 20 MHz tW tSU tH tREL TA 0 Clock Frequency (Note 3) 0 Pulse Width Clock 20 6 (Note 2) Clear 20 9 Pulse Width Clock 25 (Note 3) Clear 25 ns ns Setup Time Data 20 8 (Note 2) Enable P 25 17 Load 25 15 Setup Time Data 20 (Note 3) Enable P 30 Load 30 Hold Time Data 0 −3 (Note 2) Others 0 −3 Hold Time Data 5 (Note 3) Others 5 Clear Release Time (Note 2) 20 Clear Release Time (Note 3) 25 Free Air Operating Temperature 0 ns ns ns ns ns ns 70 °C Note 2: CL = 15 pF, RL = 2 kΩ, TA = 25°C and VCC = 5.5V. Note 3: CL = 50 pF, RL = 2 kΩ, TA = 25°C and VCC = 5.5V. 5 www.fairchildsemi.com DM74LS161A • DM74LS163A Absolute Maximum Ratings(Note 1) DM74LS161A • DM74LS163A DM74LS161A Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter Conditions VI Input Clamp Voltage VCC = Min, II = −18 mA VOH HIGH Level VCC = Min, IOH = Max Output Voltage VIL = Max, VIH = Min VOL LOW Level VCC = Min, IOL = Max Output Voltage VIL = Max, VIH = Min Typ Min (Note 4) 2.7 IIH −1.5 V V 0.35 0.5 0.25 0.4 Input Current @ Max VCC = Max Enable T 0.2 Input Voltage VI = 7V Clock 0.2 Load 0.2 Others 0.1 HIGH Level VCC = Max Enable T 40 Input Current VI = 2.7V Clock 40 Load 40 Others IIL Units 3.4 IOL = 4 mA, VCC = Min II Max VCC = Max Enable T Input Current VI = 0.4V Clock −0.8 Load −0.8 Supply Current with Outputs HIGH VCC = Max (Note 6) ICCL Supply Current with Outputs LOW VCC = Max (Note 7) mA −0.4 Others ICCH µA −0.8 VCC = Max (Note 5) Short Circuit Output Current mA 20 LOW Level IOS V −20 −100 mA 18 31 mA 19 32 mA Note 4: All typicals are at VCC = 5V, TA = 25°C. Note 5: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 6: ICCH is measured with the load HIGH, then again with the load LOW, with all other inputs HIGH and all outputs OPEN. Note 7: ICCL is measured with the clock input HIGH, then again with the clock input LOW, with all other inputs LOW and all outputs OPEN. DM74LS161A Switching Characteristics at VCC = 5V and TA = 25°C RL = 2 kΩ From (Input) Symbol Parameter CL = 15 pF To (Output) Min fMAX Maximum Clock Frequency tPLH Propagation Delay Time LOW-to-HIGH Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output tPLH Propagation Delay Time LOW-to-HIGH Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output tPLH Propagation Delay Time LOW-to-HIGH Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output tPLH tPHL tPHL 25 Clock to Ripple Carry Clock to Ripple Carry Clock to Any Q (Load HIGH) Clock to Any Q (Load HIGH) Clock to Any Q (Load LOW) Clock to Any Q (Load LOW) Propagation Delay Time Enable T to LOW-to-HIGH Level Output Ripple Carry Propagation Delay Time Enable T to HIGH-to-LOW Level Output Ripple Carry Propagation Delay Time HIGH-to-LOW Level Output www.fairchildsemi.com Max Clear to Any Q 6 CL = 50 pF Min Units Max 20 MHz 25 30 ns 30 38 ns 22 27 ns 27 38 ns 24 30 ns 27 38 ns 14 27 ns 15 27 ns 28 45 ns Symbol Parameter Min Nom Max Units 4.75 5 5.25 V LOW Level Input Voltage 0.8 V mA VCC Supply Voltage VIH HIGH Level Input Voltage VIL 2 V IOH HIGH Level Output Current −0.4 IOL LOW Level Output Current 8 mA fCLK Clock Frequency (Note 8) 25 MHz 20 MHz 0 Clock Frequency (Note 9) tW tSU tH tREL TA 0 Pulse Width Clock 20 6 (Note 8) Clear 20 9 Pulse Width Clock 25 (Note 9) Clear 25 Setup Time Data 20 8 (Note 8) Enable P 25 17 Load 25 15 ns Setup Time Data 20 (Note 9) Enable P 30 Load 30 Hold Time Data 0 −3 (Note 8) Others 0 −3 Hold Time Data 5 (Note 9) Others 5 Clear Release Time (Note 8) 20 Clear Release Time (Note 9) 25 Free Air Operating Temperature 0 ns ns ns ns ns ns ns °C 70 Note 8: CL = 15 pF, RL = 2 kΩ, TA = 25°C and VCC = 5V. Note 9: CL = 50 pF, RL = 2 kΩ, TA = 25°C and VCC = 5V. DM74LS163A Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter Conditions VI Input Clamp Voltage VCC = Min, II = −18 mA VOH HIGH Level VCC = Min, IOH = Max Output Voltage VIL = Max, VIH = Min VOL LOW Level VCC = Min, IOL = Max Output Voltage VIL = Max, VIH = Min Min Typ (Note 10) 2.7 3.4 IOL = 4 mA, VCC = Min II IIH Units −1.5 V V 0.35 0.5 0.25 0.4 Input Current @ Max VCC = Max Enable T 0.2 Input Voltage VI = 7V Clock, Clear 0.2 Load 0.2 Others 0.1 HIGH Level VCC = Max Enable T 40 Input Current VI = 2.7V Load 40 Clock, Clear 40 Others IIL Max LOW Level VCC = Max Input Current VI = 0.4V Short Circuit Output Current ICCH Supply Current with Outputs HIGH VCC = Max (Note 12) ICCL Supply Current with Outputs LOW VCC = Max (Note 13) mA µA 20 Enable T −0.8 Clock, Clear −0.8 Load −0.8 mA −0.4 Others VCC = Max (Note 11) IOS V −20 −100 mA 18 31 mA 18 32 mA Note 10: All typicals are at VCC = 5V, TA = 25°C. Note 11: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 12: ICCH is measured with the load HIGH, then again with the load LOW, with all other inputs HIGH and all outputs OPEN. Note 13: ICCL is measured with the clock input HIGH, then again with the clock input LOW, with all other inputs LOW and all outputs OPEN. 7 www.fairchildsemi.com DM74LS161A • DM74LS163A DM74LS163A Recommended Operating Conditions DM74LS161A • DM74LS163A DM74LS163A Switching Characteristics at VCC = 5V and TA = 25°C RL = 2 kΩ From (Input) Symbol Parameter CL = 15 pF To (Output) Min fMAX Maximum Clock Frequency tPLH Propagation Delay Time LOW-to-HIGH Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output tPLH Propagation Delay Time LOW-to-HIGH Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output tPLH Propagation Delay Time LOW-to-HIGH Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output tPLH tPHL tPHL 25 Clock to Ripple Carry Clock to Ripple Carry Clock to Any Q (Load HIGH) Clock to Any Q (Load HIGH) Clock to Any Q (Load LOW) Clock to Any Q (Load LOW) Propagation Delay Time Enable T to LOW-to-HIGH Level Output Ripple Carry Propagation Delay Time Enable T to HIGH-to-LOW Level Output Ripple Carry Propagation Delay Time HIGH-to-LOW Level Output Clear to Any Q (Note 14) Note 14: The propagation delay clear to output is measured from the clock input transition. www.fairchildsemi.com Max 8 CL = 50 pF Min Units Max 20 MHz 25 30 ns 30 38 ns 22 27 ns 27 38 ns 24 30 ns 27 38 ns 14 27 ns 15 27 ns 28 45 ns DM74LS161A • DM74LS163A Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A 9 www.fairchildsemi.com DM74LS161A • DM74LS163A Synchronous 4-Bit Binary Counters Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com www.fairchildsemi.com 10