Errata Sheet V1.0 This Errata Sheet refers to: • The following datasheets: AT91M40800 Summary, Rev. 1348CS–05/00 AT91X40 Series, Rev. 1354C–08/01 AT91M40800 Electrical Characteristics, Rev. 1393A–08/00 • 100-lead TQFP devices with the following markings AT91 ARM® Thumb® Microcontrollers Internal Product Reference 56510C or 56510E AT91M40800-33AI AT91M40800 Errata Sheet V1.0 1. Warning: Additional NWAIT Constraints When the NWAIT signal is asserted during an external memory access, the following EBI behavior is correct: – NWAIT is asserted before the first rising edge of the master clock and respects the NWAIT to MCKI rising setup timing as defined in the Electrical Characteristics datasheet. – NWAIT is sampled inactive and at least one standard wait state remains to be executed, even if NWAIT does not meet the NWAIT to first MCKI rising setup timing (i.e., NWAIT is asserted only on the second rising edge of MCKI). In these cases, the access is delayed as required by NWAIT and the access operations are correctly performed. In other cases, the following erroneous behavior occurs: – 32-bit read accesses are not managed correctly and the first 16-bit data sampling takes into account only the standard wait states. 16- and 8-bit accesses are not affected. – During write accesses of any type, the NWE rises on the rising edge of the last cycle as defined by the programmed number of wait states. However, NWAIT assertion does affect the length of the total access. Only the NWE pulse length is inaccurate. At maximum speed, asserting the NWAIT in the first access cycle is not possible, as the sum of the timings “MCKI Falling to Chip Selec” and “NWAIT setup to MCKI rising” are generally higher than one half of a clock period. This leads to using at least one standard wait state. However, this is not sufficient except to perform byte or half-word read accesses. Word and write accesses require at least two standard wait states. Rev. 1747A–01/02 1 The following waveforms further explain the issue: If the NWAIT setup time is satisfied on the first rising edge of MCKI, the behavior is accurate. The EBI operations are not affected when the NWAIT rises. Figure 1. NWAIT Rising MCKI NWAIT NWAIT Setup before MCKI Rising (EB16) If the NWAIT setup time is satisfied on the following edges of MCKI and if at least one standard wait state remains to be executed, the behavior is accurate. In the following example, the number of standard wait states is two. The NWAIT setup time on the second rising edge of MCKI must be met. Figure 2. Number of Standard Wait States is Two MCKI NWAIT EB16 NCS 1(1) 2(1) 3(1) Standard Access Length with Two Wait States Note: 2 1. These numbers refer to the standard access cycles. AT91M40800 Erata Sheet 1747A–01/02 AT91M40800 Erata Sheet If the first two conditions are not met during a 32-bit read access, the first 16-bit data is read at the end of the standard 16-bit read access. In the following example, the number of standard waits is one. NWAIT assertions do affect both NRD pulse lengths, but first data sampling is not delayed. The second data sampling is correct. Figure 3. Number of Standard Wait States is One MCKI Second Data Sampling (Correct) NWAIT First Data Sampling (Erroneous) EB16 NRD 1(1) 2(1) 2(1) 1(1) 2(1) 2(1) 32-bit Access = Two 16-bit Accesses Each Access Length = One Wait State + Assertion for One More Cycle Note: 1. These numbers refer to the standard access cycles. If the first two conditions are not met during write accesses, the NWE signal is not affected by the NWAIT assertion. The following example illustrates the number of standard wait states. NWAIT is not asserted during the first cycle, but is asserted at the second and last cycle of the standard access. The access is correctly delayed as the NCS line rises accordingly to the NWAIT assertion. However, the NWE signal waveform is unchanged, and rises too early. Figure 4. Description of the Number of Standard Wait States MCKI NWAIT EB16 Erroneous NWE Rising NWE NCS Access Length = One Wait State + Assertion of the NWAIT for One More Cycle 3 1747A–01/02 Atmel Headquarters Atmel Operations Corporate Headquarters Memory 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 487-2600 Europe Atmel SarL Route des Arsenaux 41 Casa Postale 80 CH-1705 Fribourg Switzerland TEL (41) 26-426-5555 FAX (41) 26-426-5500 Asia Atmel Asia, Ltd. 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