FCDN608-UBM 1-Channel ESD Protector Product Description The FCDN608-UBM provides robust ESD protection for sensitive parts that may be subjected to electrostatic discharge (ESD). The tiny form factor and single pad allows it to be used in very confined spaces. The electrical ‘back-to-back zener’ configuration provides symmetrical ESD protection in cases where nodes with AC signals are present. This device is designed and characterized to safely dissipate ESD strikes of at least 15 kV, according to the MIL-STD-883 (Method 3015) specification for Human Body Model (HBM) ESD. http://onsemi.com Features Compact Die Protects from ESD Discharges Almost No Conduction at Signal Amplitudes Less than 5 V ESD Protection to over 15 kV (Human Body Model HBM) per MIL_STD_883 International ESD Standard Applications LED Lighting Modules Interface Circuits Signal Node Signal Node Reference Node 1 2 3 Top View 1 Wirebond Pad 2 DAP 3 4 Test Point (Green Pad) Reference Node (Backside is the Bare Silicon) Figure 1. Electrical Schematic and Top View ORDERING INFORMATION For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Semiconductor Components Industries, LLC, 2011 May, 2011 − Rev. 3 1 Publication Order Number: FCDN608−UBM/D FCDN608−UBM Table 1. PIN DESCRIPTIONS FCDN608−UBM (Schematic and Top View) Designation Schematic Top View Metal Composition 1 Signal Node Wirebond Pad Al 2 Signal Node DAP Cu 3 Reference Node Test Point − 4 Reference Node N/A Bare Silicon Table 2. ORDERING INFORMATION Ordering Part Number DAP (Die Attach Pad) Backside Metal BG Thickness Shipping Method FCDN608−UBM Cu (Copper) Bare Silicon 10 mils Wafer Form SPECIFICATIONS Table 3. ABSOLUTE MAXIMUM RATINGS Parameter Rating Units Operating Junction Temperature Range −40 to +150 C Storage Junction Temperature Range −65 to +150 C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Table 4. STANDARD OPERATING CONDITIONS Parameter Operating Junction Temperature Range Rating Units −40 to +150 C Table 5. ELECTRICAL OPERATING CHARACTERISTICS (Note 1) Symbol ILEAK VCL VESD VCL_ESD RDYN CIN Parameter Test Conditions Min Typ Leakage Current V = 5 V, 25C V = −10 V, 25C V = 5 V, 150C Clamp Voltage on Signal Node Positive Polarity Negative Polarity TA = 25C at 10 mA at −10 mA ESD Protection − Withstand Voltage: Human Body Model (MIL−STD−883, Method 3015) TA = 25C Clamping Voltage on Signal Node for Transients Positive Polarity Negative Polarity IPP = 1 A, tP = 8/20 ms Positive Transients Negative Transients +7 −12 Dynamic Resistance RDYN+ RDYN− IPP = 1 A, tP = 8/20 ms Positive Transients Negative Transients 0.2 0.4 Input Capacitance At 1 MHz, 30 mV osc. Level, 0 VDC Bias (Note 2) At 1 MHz, 30 mV osc. Level, 3 VDC Bias +5 −14 +7 −11.5 Max Units +0.35 −0.35 4.0 mA mA mA +9 −10 V kV 15 1. Operating characteristics are over standard operating conditions unless otherwise specified. http://onsemi.com 2 175 120 V W pF FCDN608−UBM MECHANICAL DETAILS Table 6. MECHANICAL SPECIFICATIONS Parameter Condition Units Composition Silicon Wafer, n+ Doped Die Shape Rectangular Length (Stepping Size) 1560 mm Width (Stepping Size) 1160 mm BG Thickness 10 mils Saw Street Widths (Space between Devices on Wafer) (Note 1) 40 (X−Direction) 40 (Y−Direction) mm Die Attach Pad Length 1000 mm Die Attach Pad Width 1000 mm Die Attach Pad (DAP) Cu (Copper) Backside Metal Bare Silicon Reflective Surface 1100 mm x 1.500 mm + 250 mm Submount Pitch (Solid Line Area) 1560 mm x 1160 mm Stepping Size 50 mm 50 mm Soldable DAP 1000 mm x 1000 mm 250 mm Test Pad Opening 90 mm x 90 mm Figure 2. Die Dimensions 1. The saw street is defined as the passivation−free area between devices. Passivation−Free Saw Street: 40 mm + + + + Passivation−Free Saw Street: 40 mm Figure 3. Die−Array on Wafer ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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