AD AD9226ARS Adc converter Datasheet

a
FEATURES
Signal-to-Noise Ratio: 69 dB @ f IN = 31 MHz
Spurious-Free Dynamic Range: 85 dB @ fIN = 31 MHz
Intermodulation Distortion of –75 dBFS @ fIN = 140 MHz
ENOB = 11.1 @ fIN = 10 MHz
Low-Power Dissipation: 475 mW
No Missing Codes Guaranteed
Differential Nonlinearity Error: ⴞ0.6 LSB
Integral Nonlinearity Error: ⴞ0.6 LSB
Clock Duty Cycle Stabilizer
Patented On-Chip Sample-and-Hold with
Full Power Bandwidth of 750 MHz
Straight Binary or Two’s Complement Output Data
28-Lead SSOP, 48-Lead LQFP
Single 5 V Analog Supply, 3 V/5 V Driver Supply
Pin-Compatible to AD9220, AD9221, AD9223,
AD9224, AD9225
PRODUCT DESCRIPTION
The AD9226 is a monolithic, single-supply, 12-bit, 65 MSPS
analog-to-digital converter with an on-chip, high-performance
sample-and-hold amplifier and voltage reference. The AD9226
uses a multistage differential pipelined architecture with a patented input stage and output error correction logic to provide
12-bit accuracy at 65 MSPS data rates. There are no missing
codes over the full operating temperature range (guaranteed).
The input of the AD9226 allows for easy interfacing to both
imaging and communications systems. With a truly differential
input structure, the user can select a variety of input ranges and
offsets including single-ended applications.
The sample-and-hold amplifier (SHA) is well suited for IF
undersampling schemes such as in single-channel communication applications with input frequencies up to and well
beyond Nyquist frequencies.
The AD9226 has an on-board programmable reference. For system design flexibility, an external reference can also be chosen.
A single clock input is used to control all internal conversion
cycles. An out-of-range signal indicates an overflow condition
that can be used with the most significant bit to determine low
or high overflow.
Complete 12-Bit, 65 MSPS
ADC Converter
AD9226
FUNCTIONAL BLOCK DIAGRAM
DRVDD
AVDD
CLK
DUTY CYCLE STABILIZER
SHA
VINA
8-STAGE
1-1/2-BIT PIPELINE
MDAC1
VINB
A/D
CAPT
CAPB
A/D
4
CALIBRATION
ROM
VREF
3
16
CORRECTION LOGIC
12
OUTPUT BUFFERS
SENSE
REF
SELECT
1V
REFCOM
MODE
SELECT
MODE
AD9226
AVSS
OTR
BIT 1
(MSB)
BIT 12
(LSB)
DRVSS
The AD9226 has two important mode functions. One will set
the data format to binary or two’s complement. The second will
make the ADC immune to clock duty cycle variations.
PRODUCT HIGHLIGHTS
IF Sampling—The patented SHA input can be configured for
either single-ended or differential inputs. It will maintain outstanding AC performance up to input frequencies of 300 MHz.
Low Power—The AD9226 at 475 mW consumes a fraction of
the power presently available in existing, high-speed monolithic
solutions.
Out of Range (OTR)—The OTR output bit indicates when
the input signal is beyond the AD9226’s input range.
Single Supply—The AD9226 uses a single 5 V power supply
simplifying system power supply design. It also features a separate digital output driver supply line to accommodate 3 V and
5 V logic families.
Pin Compatibility—The AD9226 is similar to the AD9220,
AD9221, AD9223, AD9224, and AD9225 ADCs.
Clock Duty Cycle Stabilizer—Makes conversion immune to
varying clock pulsewidths.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
AD9226* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
TOOLS AND SIMULATIONS
View a parametric search of comparable parts.
• Visual Analog
DOCUMENTATION
REFERENCE MATERIALS
Application Notes
Technical Articles
• AN-1142: Techniques for High Speed ADC PCB Layout
• AN-282: Fundamentals of Sampled Data Systems
• Correlating High-Speed ADC Performance to Multicarrier
3G Requirements
• AN-302: Exploit Digital Advantages in an SSB Receiver
• DNL and Some of its Effects on Converter Performance
• AN-345: Grounding for Low-and-High-Frequency Circuits
• MS-2210: Designing Power Supplies for High Speed ADC
• AN-348: Avoiding Passive-Component Pitfalls
• AN-501: Aperture Uncertainty and ADC System
Performance
DESIGN RESOURCES
• AD9226 Material Declaration
• AN-715: A First Approach to IBIS Models: What They Are
and How They Are Generated
• PCN-PDN Information
• AN-737: How ADIsimADC Models an ADC
• Symbols and Footprints
• Quality And Reliability
• AN-741: Little Known Characteristics of Phase Noise
• AN-742: Frequency Domain Response of SwitchedCapacitor ADCs
• AN-756: Sampled Systems and the Effects of Clock Phase
Noise and Jitter
• AN-807: Multicarrier WCDMA Feasibility
• AN-808: Multicarrier CDMA2000 Feasibility
• AN-827: A Resonant Approach to Interfacing Amplifiers to
Switched-Capacitor ADCs
• AN-835: Understanding High Speed ADC Testing and
Evaluation
• AN-905: Visual Analog Converter Evaluation Tool Version
1.0 User Manual
• AN-935: Designing an ADC Transformer-Coupled Front
End
DISCUSSIONS
View all AD9226 EngineerZone Discussions.
SAMPLE AND BUY
Visit the product page to see pricing options.
TECHNICAL SUPPORT
Submit a technical question or find your regional support
number.
DOCUMENT FEEDBACK
Submit feedback for this data sheet.
Data Sheet
• AD9226: Complete 12-Bit, 65 MSPS ADC Converter Data
Sheet
User Guides
• UG-173: High Speed ADC USB FIFO Evaluation Kit (HSCADC-EVALB-DCZ)
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AD9226–SPECIFICATIONS
(AVDD = 5 V, DRVDD = 3 V, fSAMPLE = 65 MSPS, VREF = 2.0 V, Differential inputs, TMIN to TMAX unless otherwise
DC SPECIFICATIONS noted.)
Parameter
Temp
Test Level
RESOLUTION
Min
Typ
Max
12
ACCURACY
Integral Nonlinearity (INL)
Unit
Bits
± 0.6
Full
25°C
Full
25°C
Full
Full
25°C
25°C
Full
V
I
V
I
I
V
I
I
V
Full
Full
Full
V
V
V
±2
± 26
± 0.4
Full
25°C
V
I
± 0.05
INPUT REFERRED NOISE
VREF = 1.0 V
VREF = 2.0 V
Full
Full
V
V
0.5
0.25
LSB rms
LSB rms
ANALOG INPUT
Input Span (VREF = 1 V)
(VREF = 2 V)
Input (VINA or VINB) Range
Input Capacitance
Full
Full
Full
Full
V
V
IV
V
1
2
V p-p
V p-p
V
pF
Full
25°C
Full
25°C
Full
Full
25°C
V
I
V
I
V
V
I
REFERENCE INPUT RESISTANCE
Full
V
POWER SUPPLIES
Supply Voltages
AVDD
DRVDD
Supply Current
IAVDD4
Full
Full
V
V
Full
25°C
Full
25°C
V
I
V
I
Full
25°C
V
I
Differential Nonlinearity (DNL)
No Missing Codes Guaranteed
Zero Error
Gain Error
TEMPERATURE DRIFT
Zero Error
Gain Error1
Gain Error2
POWER SUPPLY REJECTION
AVDD (5 V ± 0.25 V)
INTERNAL VOLTAGE REFERENCE
Output Voltage (1 V Mode)
Output Voltage Tolerance (1 V Mode)
Output Voltage (2.0 V Mode)
Output Voltage Tolerance (2.0 V Mode)
Output Current (Available for External Loads)
Load Regulation3
IDRVDD5
POWER CONSUMPTION
4, 5
± 0.6
± 1.6
± 1.0
12
± 0.3
± 0.6
0
± 1.4
± 2.0
ppm/°C
ppm/°C
ppm/°C
± 0.4
AVDD
7
1.0
± 15
2.0
± 29
1.0
0.7
1.5
5
4.75
2.85
5
LSB
LSB
LSB
LSB
Bits
% FSR
% FSR
% FSR
% FSR
% FSR
% FSR
V
mV
V
mV
mA
mV
mV
kΩ
5.25
5.25
86
V (± 5% AVDD Operating)
V (± 5% DRVDD Operating)
16.5
mA (2 V External VREF)
mA (2 V External VREF)
mA (2 V External VREF)
mA (2 V External VREF)
500
mW (2 V External VREF)
90.5
14.6
475
NOTES
1
Includes internal voltage reference error.
2
Excludes internal voltage reference error.
3
Load regulation with 1 mA load current (in addition to that required by the AD9226).
4
AVDD = 5 V
5
DRVDD = 3 V
Specifications subject to change without notice.
–2–
REV. B
AD9226
DIGITAL SPECIFICATIONS (AVDD = 5 V, DRVDD = 3 V, f
SAMPLE
Parameters
= 65 MSPS, VREF = 2.0 V, TMIN to TMAX, unless otherwise noted.)
Temp
Test Level
Min
Full
Full
Full
Full
Full
Full
IV
IV
IV
IV
V
IV
2.4
LOGIC OUTPUTS (With DRVDD = 5 V)
High-Level Output Voltage (IOH = 50 µA)
High-Level Output Voltage (IOH = 0.5 mA)
Low-Level Output Voltage (IOL = 1.6 mA)
Low-Level Output Voltage (IOL = 50 µA)
Output Capacitance
Full
Full
Full
Full
IV
IV
IV
IV
LOGIC OUTPUTS (With DRVDD = 3 V)
High-Level Output Voltage (IOH = 50 µA)
High-Level Output Voltage (IOH = 0.5 mA)
Low-Level Output Voltage (IOL = 1.6 mA)
Low-Level Output Voltage (IOL = 50 µA)
Full
Full
Full
Full
1
Typ
Max
Unit
1
LOGIC INPUTS (Clock, DFS , Duty Cycle , and
Output Enable1)
High-Level Input Voltage
Low-Level Input Voltage
High-Level Input Current (VIN = AVDD)
Low-Level Input Current (VIN = 0 V)
Input Capacitance
Output Enable1
0.8
+10
+10
–10
–10
5
DRVDD
+ 0.5
2
DRVDD
– 0.5
2
4.5
2.4
V
V
V
V
pF
0.4
0.1
5
IV
IV
IV
IV
V
V
µA
µA
pF
V
2.95
2.80
V
V
V
V
0.4
0.05
NOTES
1
LQFP package.
Specifications subject to change without notice.
SWITCHING SPECIFICATIONS
(TMIN to TMAX with AVDD = 5 V, DRVDD = 3 V, CL = 20 pF)
Parameters
Temp
Test Level
Min
Typ
Max Conversion Rate
Clock Period1
CLOCK Pulsewidth High2
CLOCK Pulsewidth Low2
Output Delay
Pipeline Delay (Latency)
Output Enable Delay3
Full
Full
Full
Full
Full
Full
Full
VI
V
V
V
V
V
V
65
15.38
3
3
3.5
7
7
15
NOTES
1
The clock period may be extended to 10 µs without degradation in specified performance @ 25°C.
2
When MODE pin is tied to AVDD or grounded, the AD9226 SSOP is not affected by clock duty cycle.
3
LQFP package.
Specifications subject to change without notice.
n+1
ANALOG
INPUT
n+2
n+3
n
n+8
n+4
n+5
n+7
n+6
CLOCK
DATA
OUT
n–8
n–7
n–6
n–5
n–4
n–3
n–2
n–1
n
n+1
TOD = 7.0 MAX
3.5 MIN
Figure 1. Timing Diagram
REV. B
–3–
Max
Unit
MHz
ns
ns
ns
ns
Clock Cycles
ns
AD9226–SPECIFICATIONS
AC SPECIFICATIONS
(AVDD = 5 V, DRVDD = 3 V, fSAMPLE = 65 MSPS, VREF = 2.0 V, TMIN to TMAX, Differential Input unless otherwise noted.)
Parameter
SIGNAL-TO-NOISE RATIO
fIN = 2.5 MHz
Temp
Test Level
Full
V
I
V
I
V
V
V
25°C
fIN = 15 MHz
Full
25°C
fIN = 31 MHz
fIN = 60 MHz
fIN = 200 MHz1
SIGNAL-TO-NOISE RATIO AND DISTORTION
fIN = 2.5 MHz
Full
Full
Full
Full
25°C
fIN = 15 MHz
Full
25°C
fIN = 31 MHz
fIN = 60 MHz
fIN = 200 MHz1
TOTAL HARMONIC DISTORTION
fIN = 2.5 MHz
Full
Full
Full
Full
25°C
fIN = 15 MHz
Full
25°C
fIN = 31 MHz
fIN = 60 MHz
fIN = 200 MHz1
SECOND AND THIRD HARMONIC DISTORTION
fIN = 2.5 MHz
Full
Full
Full
Full
25°C
fIN = 15 MHz
Full
25°C
fIN = 31 MHz
fIN = 60 MHz
fIN = 200 MHz1
SPURIOUS FREE DYNAMIC RANGE
fIN = 2.5 MHz
Full
Full
Full
Full
fIN = 31 MHz
fIN = 60 MHz
fIN = 200 MHz1
ANALOG INPUT BANDWIDTH
25°C
V
Max
68.9
68.4
68
68
65
68.8
dBc
dBc
dBc
dBc
dBc
dBc
dBc
67.9
68.3
67.3
67
67
60
–84
–77.0
–82.3
–76.0
–68
–68
–61
–86.5
–78
–86.7
–76
–83
–82
–75
86.4
Unit
dBc
dBc
dBc
dBc
dBc
dBc
dBc
67.4
V
I
V
I
V
V
V
Full
Full
Full
Full
25°C
Typ
68
V
I
V
I
V
V
V
V
I
V
I
V
V
V
25°C
fIN = 15 MHz
V
I
V
I
V
V
V
Min
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
82
81
60
dBc
dBc
dBc
dBc
dBc
dBc
dBc
750
MHz
78
85.5
76
NOTES
1
1.0 V Reference and Input Span
Specifications subject to change without notice.
–4–
REV. B
AD9226
EXPLANATION OF TEST LEVELS
Test Level
ABSOLUTE MAXIMUM RATINGS 1
I.
Pin Name
100% production tested.
II. 100% production tested at 25°C and sample tested at
specified temperatures. AC testing done on sample basis.
III. Sample tested only.
IV. Parameter is guaranteed by design and characterization
testing.
V. Parameter is a typical value only.
VI. All devices are 100% production tested at 25°C; sample tested
at temperature extremes.
THERMAL RESISTANCE
θJC SSOP
θJA SSOP
θJC LQFP
θJA LQFP
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23°C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63.3°C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17°C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76.2°C/W
With
Respect to
AVDD
AVSS
DRVDD
DRVSS
AVSS
DRVSS
AVDD
DRVDD
REFCOM
AVSS
CLK, MODE
AVSS
Digital Outputs DRVSS
VINA, VINB
AVSS
VREF
AVSS
SENSE
AVSS
CAPB, CAPT
AVSS
OEB2
DRVSS
CM LEVEL2
AVSS
AVSS
VR2
Junction Temperature
Storage Temperature
Lead Temperature (10 sec)
Min
Max
Unit
–0.3
–0.3
–0.3
–6.5
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
+6.5
+6.5
+0.3
+6.5
+0.3
AVDD + 0.3
DRVDD + 0.3
AVDD + 0.3
AVDD + 0.3
AVDD + 0.3
AVDD + 0.3
DRVDD + 0.3
AVDD + 0.3
AVDD + 0.3
150
+150
300
V
V
V
V
V
V
V
V
V
V
V
V
V
V
°C
°C
°C
–65
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may affect device reliability.
2
LQFP package.
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
AD9226ARS
AD9226AST
AD9226-EB
AD9226-LQFP-EB
–40°C to +85°C
–40°C to +85°C
28-Lead Shrink Small Outline (SSOP)
48-Lead Thin Plastic Quad Flatpack (LQFP)
Evaluation Board (SSOP)
Evaluation Board (LQFP)
RS-28
ST-48
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9226 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
REV. B
–5–
WARNING!
ESD SENSITIVE DEVICE
AD9226
PIN CONNECTION
28-Lead SSOP
28
DRVDD
2
27
DRVSS
BIT 11
3
26
AVDD
BIT 10
4
25
AVSS
48 47 46 45 44 43 42 41 40 39 38 37
BIT 9
5
24
VINB
SENSE
BIT 8
6
23
VINA
MODE2
34 AVDD
33 AVSS
32 AVSS
BIT 7
7
VINB
VINA
CM LEVEL
NC
1
VR
CLK
(LSB) BIT 12
VREF
MODE1
CAPT
CAPT
CAPB
CAPB
REF COM (AVSS)
PIN CONNECTION
48-Lead LQFP
1
AVSS
AVSS 2
AVDD 3
AVDD 4
36
PIN 1
IDENTIFIER
NC
NC 6
35
5
AD9226
31
TOP VIEW
(Not to Scale)
CLK 7
NC 8
30
NC 11
(LSB) BIT 12 12
16–21,
24–26
27
28
35
36
37
38
39, 40
41, 42
43
45
46
47
48
REFCOM (AVSS)
BIT 3 11
18
VREF
BIT 2 12
17
SENSE
(MSB) BIT 1 13
16
AVSS
OTR 14
15
AVDD
DRVSS
DRVDD
BIT 4
BIT 8
BIT 7
BIT 6
BIT 5
13 14 15 16 17 18 19 20 21 22 23 24
BIT 11
1, 2, 32, 33
3, 4, 31, 34
5, 6, 8, 10,
11, 44
7
9
12
13
14, 22, 30
15, 23, 29
CAPB
19
BIT 2
25 BIT 3
28-PIN FUNCTION DESCRIPTIONS
48-PIN FUNCTION DESCRIPTIONS
Pin
Number
20
26
DRVSS
DRVDD
BIT 10
BIT 9
NC = NO CONNECT
BIT 5
9
29
OEB 9
NC 10
BIT 6
BIT 4 10
AVDD
DRVSS
DRVDD
28 OTR
27 BIT 1 (MSB)
AD9226
TOP VIEW 22 MODE
8 (Not to Scale) 21 CAPT
Name
Description
AVSS
AVDD
NC
Analog Ground
5 V Analog Supply
No Connect
CLK
OEB
BIT 12
BIT 11
DRVSS
DRVDD
Clock Input Pin
Output Enable (Active Low)
Least Significant Data Bit (LSB)
Data Output Bit
Digital Output Driver Ground
3 V to 5 V Digital Output
Driver Supply
Data Output Bits
BITS 10–5,
BITS 4–2
BIT 1
OTR
MODE2
SENSE
VREF
REFCOM
(AVSS)
CAPB
CAPT
MODE1
CM LEVEL
VINA
VINB
VR
Pin
Number
1
2
3–12
13
14
15, 26
16, 25
17
18
19
20
21
22
23
24
27
28
Most Significant Data Bit (MSB)
Out of Range
Data Format Select
Reference Select
Reference In/Out
Reference Common
Name
Description
CLK
BIT 12
BITS 11–2
BIT 1
OTR
AVDD
AVSS
SENSE
VREF
REFCOM
(AVSS)
CAPB
CAPT
MODE
VINA
VINB
DRVSS
DRVDD
Clock Input Pin
Least Significant Data Bit (LSB)
Data Output Bits
Most Significant Data Bit (MSB)
Out of Range
5 V Analog Supply
Analog Ground
Reference Select
Input Span Select (Reference I/O)
Reference Common
Noise Reduction Pin
Noise Reduction Pin
Data Format Select /Clock Stabilizer
Analog Input Pin (+)
Analog Input Pin (–)
Digital Output Driver Ground
3 V to 5 V Digital Output
Driver Supply
Noise Reduction Pin
Noise Reduction Pin
Clock Stabilizer
Midsupply Reference
Analog Input Pin (+)
Analog Input Pin (–)
Noise Reduction Pin
–6–
REV. B
AD9226
DEFINITIONS OF SPECIFICATIONS
INTEGRAL NONLINEARITY (INL)
INL refers to the deviation of each individual code from a line
drawn from “negative full scale” through “positive full scale.”
The point used as “negative full scale” occurs 1/2 LSB before
the first code transition. “Positive full scale” is defined as a level
1 1/2 LSB beyond the last code transition. The deviation is
measured from the middle of each particular code to the true
straight line.
DIFFERENTIAL NONLINEARITY (DNL, NO MISSING
CODES)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Guaranteed
no missing codes to 12-bit resolution indicates that all 4096
codes, respectively, must be present over all operating ranges.
EFFECTIVE NUMBER OF BITS (ENOB)
For a sine wave, SINAD can be expressed in terms of the number of bits. Using the following formula,
N = (SINAD – 1.76)/6.02
it is possible to obtain a measure of performance expressed as
N, the effective number of bits.
Thus, effective number of bits for a device for sine wave inputs
at a given input frequency can be calculated directly from its
measured SINAD.
TOTAL HARMONIC DISTORTION (THD)
THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal and is
expressed as a percentage or in decibels.
SIGNAL-TO-NOISE RATIO (SNR)
ZERO ERROR
The major carry transition should occur for an analog value
1/2 LSB below VINA = VINB. Zero error is defined as the
deviation of the actual transition from that point.
SNR is the ratio of the rms value of the measured input signal to
the rms sum of all other spectral components below the Nyquist
frequency, excluding the first six harmonics and dc. The value
for SNR is expressed in decibels.
GAIN ERROR
SPURIOUS FREE DYNAMIC RANGE (SFDR)
The first code transition should occur at an analog value
1/2 LSB above negative full scale. The last transition should
occur at an analog value 1 1/2 LSB below the positive full scale.
Gain error is the deviation of the actual difference between first
and last code transitions and the ideal difference between first
and last code transitions.
SFDR is the difference in dB between the rms amplitude of the
input signal and the peak spurious signal.
TEMPERATURE DRIFT
The temperature drift for zero error and gain error specifies the
maximum change from the initial (25°C) value to the value at
TMIN or TMAX.
ENCODE PULSEWIDTH DUTY CYCLE
Pulsewidth high is the minimum amount of time that the clock
pulse should be left in the logic “1” state to achieve rated performance; pulsewidth low is the minimum time the clock pulse
should be left in the low state. At a given clock rate, these specs
define an acceptable clock duty cycle.
MINIMUM CONVERSION RATE
POWER SUPPLY REJECTION
The clock rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed limit.
The specification shows the maximum change in full scale from
the value with the supply at the minimum limit to the value with
the supply at its maximum limit.
MAXIMUM CONVERSION RATE
APERTURE JITTER
OUTPUT PROPAGATION DELAY
Aperture jitter is the variation in aperture delay for successive
samples and can be manifested as noise on the input to the ADC.
The delay between the clock logic threshold and the time when
all bits are within valid logic levels.
APERTURE DELAY
TWO TONE SFDR
Aperture delay is a measure of the sample-and-hold amplifier
(SHA) performance and is measured from the rising edge of the
clock input to when the input signal is held for conversion.
The ratio of the rms value of either input tone to the rms value
of the peak spurious component. The peak spurious component
may or may not be an IMD product. May be reported in dBc
(i.e., degrades as signal levels are lowered) or in dBFS (always
related back to converter full scale).
SIGNAL-TO-NOISE AND DISTORTION (S/N+D, SINAD)
RATIO
The encode rate at which parametric testing is performed.
S/N+D is the ratio of the rms value of the measured input
signal to the rms sum of all other spectral components below
the Nyquist frequency, including harmonics but excluding dc.
The value for S/N+D is expressed in decibels.
REV. B
–7–
AD9226
DRVDD
DRVDD
DRVDD
AVDD
DRVSS
AVSS
DRVSS
a. D0–D11, OTR
b. Three-State (OEB)
c. CLK
AVDD
AVDD
AVSS
AVSS
d. AIN
e. CAPT, CAPB, MODE, SENSE, VREF
Figure 2. Equivalent Circuits
–8–
REV. B
Typical Performance Characteristics–AD9226
(AVDD = 5.0 V, DRVDD = 3.0 V, fSAMPLE = 65 MSPS with CLK Stabilizer Enabled, TA = 25ⴗC, 2 V Differential Input Span, VCM = 2.5 V, AIN = –0.5 dBFS,
VREF = 2.0 V, unless otherwise noted.)
0
100
–10
SNR = 69.9dBc
SINAD = 69.8dBc
ENOB = 11.4BITS
THD = –86.4dBc
SFDR = 88.7dBc
–20
–30
SFDR – dBFS
90
–50
dBFS
80
dBFS AND dBc
–40
–60
–70
SFDR – dBc
SNR – dBFS
70
–80
60
SNR – dBc
–90
–100
50
–110
–120
0
6.5
13
19.5
26
40
–30
32.5
–25
–20
FREQUENCY – MHz
–15
–10
–5
0
AIN – dBFS
TPC 1. Single-Tone 8K FFT with fIN = 5 MHz
TPC 4. Single-Tone SNR/SFDR vs. AIN with fIN = 5 MHz
0
100
SNR = 70.4dBFS
SFDR = 87.5dBFS
–10
SFDR – dBFS
90
–20
SFDR – dBc
–30
dBFS AND dBc
–40
dBFS
–50
–60
–70
–80
80
SNR – dBFS
70
60
–90
SNR – dBc
–100
50
–110
–120
0
6.5
13
19.5
26
40
–30
32.5
–25
–20
TPC 2. Dual-Tone 8K FFT with fIN–1 = 18 MHz and
fIN–2 = 20 MHz (AIN–1 = AIN–2 = –6.5 dBFS)
–10
–5
0
TPC 5. Dual-Tone SNR/SFDR vs. AIN with fIN–1 = 18 MHz
and fIN–2 = 20 MHz
0
100
–10
SNR = 69.5dBc
SINAD = 69.4dBc
ENOB = 11.3BITS
THD = –85dBc
SFDR = 87.6dBc
–20
–30
SFDR – dBFS
90
dBFS AND dBc
–40
dBFS
–15
AIN – dBFS
FREQUENCY – MHz
–50
–60
–70
–80
80
SNR – dBFS
70
60
–90
SNR – dBc
SFDR – dBc
–100
50
–110
–120
0
6.5
13
19.5
26
40
–30
32.5
TPC 3. Single-Tone 8K FFT with fIN = 31 MHz
REV. B
–25
–20
–15
–10
–5
0
AIN – dBFS
FREQUENCY – MHz
TPC 6. Single-Tone SNR/SFDR vs. AIN with fIN = 31 MHz
–9–
AD9226
12.2
75
71
70
2V SPAN, DIFFERENTIAL
11.4
70
1V SPAN,
DIFFERENTIAL
1V SPAN,
SINGLE-ENDED
55
8.9
50
8.1
SNR – dBc
9.8
60
ENOB – Bits
SINAD – dBc
68
10.6
65
2V SPAN, DIFFERENTIAL
69
2V SPAN, SINGLE-ENDED
1V SPAN,
DIFFERENTIAL
67
66
65
1V SPAN,
SINGLE-ENDED
64
63
62
2V SPAN, SINGLE-ENDED
45
1
7.3
1000
100
10
FREQUENCY – MHz
61
1
TPC 7. SINAD/ENOB vs. Frequency
TPC 10. SNR vs. Frequency
95
–45
2V SPAN, SINGLE-ENDED
–50
90
1V SPAN,
DIFFERENTIAL
85
–55
1V SPAN,
SINGLE-ENDED
80
SFDR – dBc
–60
THD – dBc
1000
10
100
FREQUENCY – MHz
–65
–70
2V SPAN,
DIFFERENTIAL
–75
2V SPAN,
DIFFERENTIAL
75
70
65
1V SPAN,
SINGLE-ENDED
60
–80
2V SPAN, SINGLE-ENDED
55
1V SPAN,
DIFFERENTIAL
–85
50
45
–90
1
100
10
FREQUENCY – MHz
1000
100
10
FREQUENCY – MHz
1
TPC 8. THD vs. Frequency
1000
TPC 11. SFDR vs. Frequency
72
–70
–40ⴗC
–72
+25ⴗC
70
–74
THD – dBc
SNR – dBc
–76
68
+85ⴗC
66
–78
+85ⴗC
–80
+25ⴗC
–82
–84
64
–86
–88
62
1
100
10
FREQUENCY – MHz
–40ⴗC
–90
1000
1
TPC 9. SNR vs. Temperature and Frequency
10
FREQUENCY – MHz
100
TPC 12. THD vs. Temperature and Frequency
–10–
REV. B
AD9226
70.5
105
4th HARMONIC
70.25
fIN = 2MHz
70
SINAD – dBc
HARMONICS – dBc
95
85
3RD HARMONIC
75
fIN = 12MHz
69.75
69.5
fIN = 20MHz
65
69.25
2ND HARMONIC
55
100
10
FREQUENCY – MHz
1
69
10
1000
TPC 13. Harmonics vs. Frequency
20
30
40
50
SAMPLE RATE – MSPS
60
70
TPC 16. SINAD vs. Sample Rate
100
90
SFDR – CLOCK STABILIZER ON
85
80
95
SINAD/SFDR – dBc
SFDR – dBc
fIN = 2MHz
fIN = 12MHz
90
85
SFDR – CLOCK STABILIZER OFF
75
SINAD – CLOCK STABILIZER ON
70
65
60
SINAD – CLOCK STABILIZER OFF
55
fIN = 20MHz
50
80
10
20
30
40
50
SAMPLE RATE – MSPS
60
45
30
70
1.0
1
0.8
0.8
0.6
0.6
0.4
0.4
0.2
0.2
0.0
–0.2
–0.6
–0.6
–0.8
–0.8
1000
1500
2000
CODE
2500
3000
3500
–1
4000
TPC 15. Typical INL
REV. B
65
70
–0.2
–0.4
500
50
55
45
60
% POSITIVE DUTY CYCLE
0
–0.4
–1.0
0
40
TPC 17. SINAD/SFDR vs. Duty Cycle @ fIN = 20 MHz
DNL – LSB
INL – LSB
TPC 14. SFDR vs. Sample Rate
35
0
500
1k
1500
2k
2500
CODE
TPC 18. Typical DNL
–11–
3k
3500
4k
AD9226
AD9226–Typical
IF Sampling Performance Characteristics
(AVDD = 5.0 V, DRVDD = 3.0 V, fSAMPLE = 65 MSPS with CLK Stabilizer Enabled, TA = 25ⴗC, 2 V Differential Input Span, VCM = 2.5 V, AIN = –6.5 dBFS,
VREF = 2.0 V, unless otherwise noted.)
170.1
95
SNR = 70.2dBFS
SFDR = 89dBFS
NOISE FLOOR = 145.33dBFS/Hz
–20
90
165.1
SFDR – 2V SPAN
SNR/SFDR – dBFS
–30
–40
dBFS
–50
–60
–70
–80
85
160.1
80
155.1
75
150.1
SNR/NOISE FLOOR – 2V SPAN
–90
–100
NOISE FLOOR – dBFS/Hz
0
–10
145.1
70
–110
4
8
12
16
20
24
28
65
–24
32
–21
–15
–18
–12
–9
AIN – dBFS
FREQUENCY – MHz
TPC 19. Dual-Tone 8K FFT with fIN–1 = 44.2 MHz and
fIN–2 = 45.6 MHz
TPC 22. Dual-Tone SNR and SFDR with fIN–1 = 44.2 MHz
and fIN–2 = 45.6 MHz
0
165.1
90
SNR = 68.5dBFS
SFDR = 75dBFS
NOISE FLOOR = 143.6dBFS/Hz
–10
–20
140.1
–6
SFDR – 2V SPAN
160.1
85
SNR/SFDR – dBFS
–30
dBFS
–40
–50
–60
–70
–80
155.1
80
SFDR – 1V SPAN
150.1
75
SNR/NOISE FLOOR – 2V SPAN
70
145.1
65
140.1
–90
–100
–110
–120
SNR/NOISE FLOOR – 1V SPAN
0
4
8
12
16
20
24
28
60
–24
32
–21
–18
–15
–12
–9
TPC 20. Dual-Tone 8K FFT with fIN–1 = 69.2 MHz and
fIN–2 = 70.6 MHz
TPC 23. Dual-Tone SNR and SFDR with fIN–1 = 69.2 MHz
and fIN–2 = 70.6 MHz
0
165.1
90
SNR = 67.5dBFS
SFDR = 75dBFS
NOISE FLOOR = 142.6dBFS/Hz
–10
–20
135.1
–6
AIN – dBFS
FREQUENCY – MHz
SFDR – 2V SPAN
160.1
85
–30
SNR/SFDR – dBFS
–40
dBFS
NOISE FLOOR – dBFS/Hz
0
–50
–60
–70
–80
80
155.1
SFDR – 1V SPAN
150.1
75
SNR/NOISE FLOOR – 2V SPAN
145.1
70
–90
NOISE FLOOR – dBFS/Hz
–120
SNR/NOISE FLOOR – 1V SPAN
–100
140.1
65
–110
–120
0
4
8
12
16
20
24
28
60
–24
32
–21
–18
–15
–12
–9
135.1
–6
AIN – dBFS
FREQUENCY – MHz
TPC 21. Dual-Tone 8K FFT with fIN–1 = 139.2 MHz and
fIN–2 = 140.7 MHz
TPC 24. Dual-Tone SNR and SFDR with fIN–1 = 139.2 MHz
and fIN–2 = 140.7 MHz
–12–
REV. B
AD9226
0
165.1
90
SFDR – 2V SPAN
fIN = 190.82MHz
fSAMPLE = 61.44MSPS
–20
160.1
85
SNR/SFDR – dBFS
–30
–40
–60
–70
–80
155.1
80
SFDR – 1V SPAN
150.1
75
SNR/NOISE FLOOR – 2V SPAN
145.1
70
–90
–100
140.1
65
SNR/NOISE FLOOR – 1V SPAN
–110
–120
0
5
10
25
15
20
FREQUENCY – MHz
60
–24
30
–21
–15
–18
–12
–9
135.1
–6
AIN – dBFS
TPC 25. Single-Tone 8K FFT at IF = 190 MHz–WCDMA
(fIN = 190.82 MHz, fSAMPLE = 61.44 MSPS)
TPC 28. Single-Tone SNR and SFDR vs. AIN at IF = 190 MHz
–WCDMA (fIN–1 = 190.8 MHz, fSAMPLE = 61.44 MSPS)
0
85
SNR = 65.1dBFS
SFDR = 59dBFS
NOISE FLOOR = 140.2dBFS/Hz
–10
–20
160.1
SFDR – 2V SPAN
155.1
80
–30
SNR/SFDR – dBFS
–40
dBFS
–50
–60
–70
–80
75
150.1
SFDR – 1V SPAN
SNR/NOISE FLOOR – 2V SPAN
70
145.1
65
140.1
–90
–100
60
SNR/NOISE FLOOR – 1V SPAN
NOISE FLOOR – dBFS/Hz
dBFS
–50
NOISE FLOOR – dBFS/Hz
–10
135.1
–110
–120
0
4
8
12
16
20
24
28
55
–24
32
FREQUENCY – MHz
TPC 26. Dual-Tone 8K FFT with fIN–1 = 239.1 MHz and
fIN–2 = 240.7 MHz
–45
CMRR – dBc
–55
INPUT SPAN = 2V p–p
–75
INPUT SPAN = 1V p–p
–85
–95
1
10
100
FREQUENCY – MHz
1000
TPC 27. CMRR vs. Frequency (AIN = –0 dBFS and
CML = 2.5 V)
REV. B
–18
–15
AIN – dBFS
–12
–9
–6
130.1
TPC 29. Dual-Tone SNR and SFDR with fIN–1 = 239.1 MHz
and fIN–2 = 240.7 MHz
–35
–65
–21
–13–
AD9226
and/or shunt capacitor can help limit the wideband noise at the
ADC’s input by forming a low-pass filter. The source impedance driving VINA and VINB should be matched. Failure to
provide matching will result in degradation of the AD9226’s
SNR, THD, and SFDR.
THEORY OF OPERATION
The AD9226 is a high-performance, single-supply 12-bit ADC.
The analog input of the AD9226 is very flexible allowing for both
single-ended or differential inputs of varying amplitudes that can
be ac- or dc-coupled.
It utilizes a nine-stage pipeline architecture with a wideband,
sample-and-hold amplifier (SHA) implemented on a costeffective CMOS process. A patented structure is used in the
SHA to greatly improve high frequency SFDR/distortion. This
also improves performance in IF undersampling applications.
Each stage of the pipeline, excluding the last stage, consists of a
low resolution flash ADC connected to a switched capacitor
DAC and interstage residue amplifier (MDAC). The residue
amplifier amplifies the difference between the reconstructed DAC
output and the flash input for the next stage in the pipeline. One
bit of redundancy is used in each of the stages to facilitate digital
correction of flash errors. The last stage simply consists of a
flash ADC.
CH
QS2
CPIN
QS1
VINB
CS
QS1
CPAR
VINA
QH1
CS
CPIN
QS2
CPAR
CH
Figure 3. Equivalent Input Circuit
VCC
Factory calibration ensures high linearity and low distortion.
RS
33⍀
AD9226
VINA
ANALOG INPUT OPERATION
Figure 3 shows the equivalent analog input of the AD9226 which
consists of a 750 MHz differential SHA. The differential input
structure of the SHA is highly flexible, allowing the device to be
easily configured for either a differential or single-ended input.
The analog inputs, VINA and VINB, are interchangeable with
the exception that reversing the inputs to the VINA and VINB
pins results in a data inversion (complementing the output word).
RS
33⍀
VEE
15pF
VINB
VREF
10␮F
0.1␮F
SENSE
REFCOM
The optimum noise and dc linearity performance for either
differential or single-ended inputs is achieved with the largest input
signal voltage span (i.e., 2 V input span) and matched input
impedance for VINA and VINB. Only a slight degradation in
dc linearity performance exists between the 2 V and 1 V input
spans.
High frequency inputs may find the 1 V span better suited to
achieve superior SFDR performance. (See Typical Performance Characteristics.)
Figure 4. Series Resistor Isolates Switched-Capacitor
SHA Input from Op Amp; Matching Resistors Improve
SNR Performance
OVERVIEW OF INPUT AND REFERENCE
CONNECTIONS
The overall input span of the AD9226 is equal to the potential
at the VREF pin. The VREF potential may be obtained from
the internal AD9226 reference or an external source (see
Reference Operation section).
The ADC samples the analog input on the rising edge of the clock
input. During the clock low time (between the falling edge and
rising edge of the clock), the input SHA is in the sample mode;
during the clock high time it is in hold. System disturbances just
prior to the rising edge of the clock and/or excessive clock jitter
on the rising edge may cause the input SHA to acquire the wrong
value and should be minimized.
In differential applications, the center point of the span is
obtained by the common-mode level of the signals. In singleended applications, the center point is the dc potential applied
to one input pin while the signal is applied to the opposite input
pin. Figures 5a–5f show various system configurations.
When the ADC is driven by an op amp and a capacitive load is
switched onto the output of the op amp, the output will momentarily drop due to its effective output impedance. As the output
recovers, ringing may occur. To remedy the situation, a series
resistor can be inserted between the op amp and the SHA
input as shown in Figure 4. A shunt capacitance also acts like
a charge reservoir, sinking or sourcing the additional charge
required by the hold capacitor, CH, further reducing current
transients seen at the op amp’s output.
The AD9226 has a very flexible input structure allowing it to
interface with single-ended or differential input interface circuitry.
DRIVING THE ANALOG INPUTS
The optimum mode of operation, analog input range, and associated interface circuitry will be determined by the particular
applications performance requirements as well as power supply options.
DIFFERENTIAL DRIVER CIRCUITS
Differential operation requires that VINA and VINB be simultaneously driven with two equal signals that are 180ⴗ out of phase
with each other.
The optimum size of this resistor is dependent on several factors,
including the ADC sampling rate, the selected op amp, and the
particular application. In most applications, a 30 Ω to 100 Ω
resistor is sufficient.
For noise-sensitive applications, the very high bandwidth of the
AD9226 may be detrimental and the addition of a series resistor
Differential modes of operation (ac- or dc-coupled input) provide
the best THD and SFDR performance over a wide frequency
range. They should be considered for the most demanding
spectral-based applications (e.g., direct IF conversion to digital).
–14–
REV. B
AD9226
1.5V
0.5V
2.5V
AD9226
33⍀
CMLEVEL
3.0V
2.5V
2.0V
VINA
15pF
0.1␮F
VINB
33⍀
AD9226
(LQFP)
33⍀
VINA
CAPT
49.9⍀
1V
VREF
10␮F
0.1␮F
0.1␮F
0.1␮F
10␮F
VINB
33⍀
CAPB
SENSE
0.1␮F
15pF
0.1␮F
2V
0.1␮F
REFCOM
CAPT
10␮F
VREF
3.0V
2.5V
2.0V
10␮F
CAPB
0.1␮F
0.1␮F
Figure 5a. 1 V Single-Ended Input, Common-Mode
Voltage = 1 V
SENSE
Figure 5e. 2 V Differential Input, Common-Mode
Voltage = 2.5 V
1.25V
0.75V
AD9226
33⍀
10k⍀
VINA
49.9⍀
0.1␮F
1V
VREF
1.25V
10␮F
0.75V
AVDD
0.1␮F
CAPT
VINB
33⍀
10k⍀
0.1␮F
15pF
CAPB
0.1␮F
2.5V
2.75V
2.5V
2.0V
10␮F
AD9226
33⍀
VINA
0.1␮F
49.9⍀
0.1␮F
15pF
SENSE
VINB
33⍀
CAPT
0.1␮F
1V
Figure 5b. 1 V Differential Input, Common-Mode
Voltage = 1 V
2.75V
2.5V
2.25V
10␮F
VREF
10␮F
CAPB
0.1␮F
0.1␮F
SENSE
Figure 5f. 1 V Differential Input, Common-Mode
Voltage = 2.5 V (Recommended for IF Undersampling)
2.5V
1.5V
AD9226
33⍀
VINA
49.9⍀
0.1␮F
15pF
VINB
33⍀
The differential input characterization for this data sheet was
performed using the configuration shown in Figure 7.
CAPT
0.1␮F
2V
10␮F
VREF
2.5V
CAPB
10␮F
1.5V
0.1␮F
0.1␮F
SENSE
Figure 5c. 2 V Differential Input, Common-Mode
Voltage = 2 V
3.0V
1.0V
AD9226
33⍀
VINA
15pF
0.1␮F
VINB
33⍀
CAPT
2V
VREF
10␮F
0.1␮F
SENSE
REFCOM
0.1␮F
10␮F
CAPB
0.1␮F
Figure 5d. 2 V Single-Ended Input, Common-Mode
Voltage = 2 V
REV. B
Since not all applications have a signal preconditioned for
differential operation, there is often a need to perform a singleended-to-differential conversion. In systems that do not need to
be dc-coupled, an RF transformer with a center tap is the best
method to generate differential inputs for the AD9226. It provides all the benefits of operating the ADC in the differential
mode without contributing additional noise or distortion. An RF
transformer also has the added benefit of providing electrical
isolation between the signal source and the ADC. An improvement
in THD and SFDR performance can be realized by operating
the AD9226 in the differential mode. The performance enhancement between the differential and single-ended mode is most
noteworthy as the input frequency approaches and goes beyond
the Nyquist frequency (i.e., fIN > FS /2).
The circuit shown in Figure 6a is an ideal method of applying
a differential dc drive to the AD9226. It uses an AD8138 to
derive a differential signal from a single-ended one. Figure 6b
illustrates its performance.
Figure 7 presents the schematic of the suggested transformer
circuit. The circuit uses a Minicircuits RF transformer, model
T1-1T, which has an impedance ratio of four (turns ratio of 2).
The schematic assumes that the signal source has a 50 Ω source
impedance. The center tap of the transformer provides a convenient means of level-shifting the input signal to a desired
common-mode voltage. In Figure 7 the transformer centertap
is connected to a resistor divider at the midsupply voltage.
–15–
AD9226
SINGLE-ENDED DRIVER CIRCUITS
10␮F
5V
0.1␮F
1k⍀
0.1␮F
0.1␮F
1k⍀
0.1␮F
AVDD
499⍀
1V p-p
0V
The AD9226 can be configured for single-ended operation using
dc- or ac-coupling. In either case, the input of the ADC must be
driven from an operational amplifier that will not degrade the
ADC’s performance. Because the ADC operates from a single
supply, it will be necessary to level-shift ground-based bipolar
signals to comply with its input requirements. Both dc- and
ac-coupling provide this necessary function, but each method
results in different interface issues which may influence the
system design and performance.
10␮F
VINA
450⍀
CAPT
AD8138
49.9⍀
0.1␮F
AD9226
10␮F
CAPB
499⍀
0.1␮F
VINB
499⍀
Single-ended operation requires that VINA be ac- or dc-coupled
to the input signal source, while VINB of the AD9226 be biased
to the appropriate voltage corresponding to the middle of the input
span. The single-ended specifications for the AD9226 are characterized using Figure 9a circuitry with input spans of 1 V and
2 V. The common-mode level is 2.5 V.
Figure 6a. Direct-Coupled Drive Circuit with AD8138
Differential Op Amp
0
SNR = 66.9dBc
SFDR = 70.0dBc
If the analog inputs exceed the supply limits, internal parasitic
diodes will turn on. This will result in transient currents within
the device. Figure 8 shows a simple means of clamping an input.
It uses a series resistor and two diodes. An optional capacitor is
shown for ac-coupled applications. A larger series resistor can
be used to limit the fault current through D1 and D2. This
can cause a degradation in overall performance. A similar
clamping circuit can also be used for each input if a differential input signal is being applied. A better method to ensure
the input is not overdriven is to use amplifiers powered by a single
5 V supply such as the AD8138.
–20
dBc
–40
–60
–80
–100
–120
0
4
8
12
16
MHz
20
24
28
32
VCC
OPTIONAL
AC-COUPLING
CAPACITOR
RS1
30⍀
Figure 6b. FS = 65 MSPS, fIN = 30 MHz, Input Span = 1 V p-p
The same midsupply potential may be obtained from the
CMLEVEL pin of the AD9226 in the LQFP package.
Referring to Figure 7, a series resistor, RS, is inserted between the
AD9226 and the secondary of the transformer. The value of
33 ohm was selected to specifically optimize both the THD and
SNR performance of the ADC. RS and the internal capacitance
help provide a low-pass filter to block high-frequency noise.
Transformers with other turns ratios may also be selected to
optimize the performance of a given application. For example, a
given input signal source or amplifier may realize an improvement in distortion performance at reduced output power levels
and signal swings. By selecting a transformer with a higher
impedance ratio (e.g., Minicircuits T16-6T with a 1:16 impedance ratio), the signal level is effectively “stepped up” thus
further reducing the driving requirements of signal source.
1k⍀
0.1␮F
VINA
CAPT
49.9⍀
0.1␮F
1k⍀
15pF
AD9226
0.1␮F
10␮F
CAPB
MINICIRCUITS
T1-1T
RS
33⍀
D2
RS2
20⍀
AD9226
D1
VEE
Figure 8. Simple Clamping Circuit
AC-COUPLING AND INTERFACE ISSUES
For applications where ac-coupling is appropriate, the op amp
output can be easily level-shifted by means of a coupling
capacitor. This has the advantage of allowing the op amp’s common-mode level to be symmetrically biased to its midsupply
level (i.e., (AVDD/2). Op amps that operate symmetrically with
respect to their power supplies typically provide the best ac
performance as well as greatest input/output span. Various highspeed performance amplifiers that are restricted to +5 V/–5 V
operation and/or specified for 5 V single-supply operation can be
easily configured for the 2 V or 1 V input span of the AD9226.
Simple AC Interface
AVDD
RS
33⍀
AVDD
VINB
Figure 7. Transformer-Coupled Input
0.1␮F
Figure 9a shows a typical example of an ac-coupled, singleended configuration of the SSOP package. The bias voltage
shifts the bipolar, ground-referenced input signal to approximately AVDD/2. The capacitors, C1 and C2, are 0.1 µF ceramic
and 10 µF tantalum capacitors in parallel to achieve a low
cutoff frequency while maintaining a low impedance over a
wide frequency range. The combination of the capacitor and the
resistor form a high-pass network with a high-pass –3 dB frequency determined by the equation,
f–3 dB = 1/(2 × π × R × (C1 + C2))
–16–
REV. B
AD9226
The low-impedance VREF output can be used to provide dc
bias levels to the fixed VINB pin and the signal on VINA. Figure 9b shows the VREF configured for 2.0 V, thus the input
range of the ADC is 1.0 V to 3.0 V. Other input ranges could
be selected by changing VREF.
Figure 10 illustrates the relation between common-mode voltage
and THD. Note that optimal performance occurs when the
reference voltage is set to 2.0 V (input span = 2.0 V).
When the inputs are biased from the reference (Figure 9b),
there may be a slight degeneration of dynamic performance. A
midsupply output level is available at the CM LEVEL pin of the
LQFP package.
Many applications require the analog input signal to be dc-coupled
to the AD9226. An operational amplifier can be configured to
rescale and level-shift the input signal to make it compatible
with the selected input range of the ADC.
+1V
0V
–1V
C1
10␮F
V
V
R
R
+5V
VIN
RS
0.1␮F
VINA
–5V
C2
0.1␮F
CAPT
15pF
AD9226
0.1␮F
CAPB
RS
VINB
0.1␮F
R
10␮F
10␮F
0.1␮F
R
VREF
3.5
2.5
1.5
10␮F
In the simplest case, the input signal to the AD9226 will already
be biased at levels in accordance with the selected input range. It
is necessary to provide an adequately low source impedance for
the VINA and VINB analog pins of the ADC.
0.1␮F
REFERENCE OPERATION
0.1␮F
10␮F
AD9226
RS
VINA
0.1␮F
1k⍀
CAPT
15pF
0.1␮F
10␮F
1k⍀
CAPB
RS
0.1␮F
VINB
10␮F
The selected input range of the AD9226 should be considered
with the headroom requirements of the particular op amp to
prevent clipping of the signal. Many of the new high-performance
op amps are specified for only ± 5 V operation and have limited
input/output swing capabilities. Also, since the output of a dual
supply amplifier can swing below absolute minimum (–0.3 V),
clamping its output should be considered in some applications
(see Figure 8). When single-ended, dc-coupling is needed, the
use of the AD8138 in a differential configuration (Figure 9a) is
highly recommended.
Simple Op Amp Buffer
Figure 9a. AC-Coupled Input Configuration
VIN
DC-COUPLING AND INTERFACE ISSUES
Figure 11a shows a simplified model of the internal voltage reference of the AD9226. A reference amplifier buffers a 1 V fixed
reference. The output from the reference amplifier, A1, appears
on the VREF pin. The voltage on the VREF pin determines
the full-scale input span of the ADC. This input span equals,
0.1␮F
VREF
10␮F
The AD9226 contains an on-board bandgap reference that
provides a pin-strappable option to generate either a 1 V or
2 V output. With the addition of two external resistors, the user
can generate reference voltages between 1 V and 2 V. See
Figures 5a-5f for a summary of the pin-strapping options for the
AD9226 reference configurations. Another alternative is to use
an external reference for designs requiring enhanced accuracy
and/or drift performance described later in this section.
0.1␮F
Full-Scale Input Span = VREF
Figure 9b. Alternate AC-Coupled Input Configuration
The voltage appearing at the VREF pin, and the state of the
internal reference amplifier, A1, are determined by the voltage
appearing at the SENSE pin. The logic circuitry contains comparators that monitor the voltage at the SENSE pin. If the
SENSE pin is tied to AVSS, the switch is connected to the
internal resistor network thus providing a VREF of 2.0 V. If the
SENSE pin is tied to the VREF pin via a short or resistor, the
switch will connect to the SENSE pin. This connection will provide a VREF of 1.0 V. An external resistor network will provide
an alternative VREF between 1.0 V and 2.0 V (see Figure 12).
Another comparator controls internal circuitry that will disable
the reference amplifier if the SENSE pin is tied to AVDD.
Disabling the reference amplifier allows the VREF pin to be
driven by an external voltage reference.
–84
–83
–82
dBc
–81
–80
–79
–78
–77
–76
0
0.5
1.0
1.5
2.0
2.5
Volts
3.0
3.5
4.0
4.5
5.0
Figure 10. THD vs. Common-Mode Voltage
(2 V Differential Input Span, fIN = 10 MHz)
REV. B
–17–
AD9226
to determine appropriate values for R1 and R2. These resistors
should be in the 2 kΩ to 10 kΩ range. For the example shown,
R1 equals 2.5 kΩ and R2 equals 5 kΩ. From the equation above,
the resultant reference voltage on the VREF pin is 1.5 V. This
sets the input span to be 1.5 V p-p. The midscale voltage can
also be set to VREF by connecting VINB to VREF. Alternatively, the midscale voltage can be set to 2.5 V by connecting
VINB to a low-impedance 2.5 V source as shown in Figure 12.
AD9226
TO
A/D
CAPT
2.5V
A2
CAPB
VREF
AD9226
33⍀
3.25V
A1
1V
VINA
1.75V
15pF
2.5V
33⍀
SENSE
DISABLE
A1
LOGIC
10␮F
REFCOM
0.1␮F
0.1␮F
VINB
CAPT
1.5V
VREF
R1
2.5k⍀
0.1␮F
SENSE
R2
5k⍀
10␮F
CAPB
0.1␮F
REFCOM
Figure 11a. Equivalent Reference Circuit
Figure 12. Resistor Programmable Reference (1.5 V p-p
Input Span, Differential Input VCM = 2.5 V)
0.1␮F
VREF
10␮F
0.1␮F
CAPT
AD9226
0.1␮F
10␮F
USING AN EXTERNAL REFERENCE
CAPB
0.1␮F
Figure 11b. CAPT and CAPB DC-Coupling
The actual reference voltages used by the internal circuitry of the
AD9226 appear on the CAPT and CAPB pins. The voltages
on these pins are symmetrical about the analog supply. For
proper operation when using an internal or external reference, it
is necessary to add a capacitor network to decouple these pins.
Figure 11b shows the recommended decoupling network. The
turn-on time of the reference voltage appearing between CAPT
and CAPB is approximately 10 ms and should be evaluated in
any power-down mode of operation.
USING THE INTERNAL REFERENCE
The AD9226 can be easily configured for either a 1 V p-p input
span or 2 V p-p input span by setting the internal reference.
Other input spans can be realized with two external gainsetting resistors as shown in Figure 12 of this data sheet, or
using an external reference.
The AD9226 contains an internal reference buffer, A2 (see
Figure 11b), that simplifies the drive requirements of an external
reference. The external reference must be able to drive about
5 kΩ (± 20%) load. Note that the bandwidth of the reference
buffer is deliberately left small to minimize the reference noise
contribution. As a result, it is not possible to rapidly change the
reference voltage in this mode.
Figure 13 shows an example of an external reference driving
both VINB and VREF. In this case, both the common-mode
voltage and input span are directly dependent on the value of
VREF. Both the input span and the center of the input span are
equal to the external VREF. Thus the valid input range extends
from (VREF + VREF/2) to (VREF – VREF/2). For example,
if the REF191, a 2.048 V external reference, is selected, the
input span extends to 2.048 V. In this case, 1 LSB of the AD9226
corresponds to 0.5 mV. It is essential that a minimum of a 10 µF
capacitor, in parallel with a 0.1 µF low-inductance ceramic
capacitor, decouple the reference output to ground.
To use an external reference, the SENSE pin must be connected
to AVDD. This connection will disable the internal reference.
Pin Programmable Reference
By shorting the VREF pin directly to the SENSE pin, the internal reference amplifier is placed in a unity-gain mode and the
resultant VREF output is 1 V. By shorting the SENSE pin
directly to the REFCOM pin, the internal reference amplifier is
configured for a gain of 2.0 and the resultant VREF output is
2.0 V. The VREF pin should be bypassed to the REFCOM pin
with a 10 µF tantalum capacitor in parallel with a low-inductance
0.1 µF ceramic capacitor as shown in Figure 11b.
VINA+VREF/2
5V
0.1␮F
AD9226
33⍀
VINA
VINB–VREF/2
15pF
VREF
10␮F
33⍀
0.1␮F
VINB
CAPT
0.1␮F
VREF
0.1␮F
CAPB
5V
Resistor Programmable Reference
Figure 12 shows an example of how to generate a reference
voltage other than 1.0 V or 2.0 V with the addition of two external resistors. Use the equation,
10␮F
SENSE
0.1␮F
Figure 13. Using an External Reference
VREF = 1 V × (1 + R1/R2)
–18–
REV. B
AD9226
MODE CONTROLS
Clock Stabilizer
DIGITAL INPUTS AND OUTPUTS
Digital Outputs
The clock stabilizer is a circuit that desensitizes the ADC from
clock duty cycle variations. The AD9226 eases system clock
constraints by incorporating a circuit that restores the internal duty
cycle to 50%, independent of the input duty cycle. Low jitter on
the rising edge (sampling edge) of the clock is preserved while
the noncritical falling edge is generated on-chip.
Table IV details the relationship among the ADC input, OTR, and
straight binary output.
It may be desirable to disable the clock stabilizer, and may be
necessary when the clock frequency speed is varied or completely
stopped. Once the clock frequency is changed, over 100 clock
cycles may be required for the clock stabilizer to settle to a different speed. When the stabilizer is disabled, the internal switching
will be directly affected by the clock state. If the external clock is
high, the SHA will be in hold. If the clock pulse is low, the SHA
will be in track. TPC 16 shows the benefits of using the clock
stabilizer. See Tables I and III.
Data Format Select (DFS)
The AD9226 may be set for binary or two’s complement data
output formats. See Tables I and II.
SSOP Package
The SSOP mode control (Pin 22) has two functions. It enables/
disables the clock stabilizer and determines the output data format.
The exact functions of the mode pin are outlined in Table I.
Table I. Mode Select (SSOP)
Mode
DFS
Clock Duty Cycle Shaping
DNC
AVDD
GND
10 kΩ
Resistor
Binary
Binary
Two’s Complement
Two’s Complement
To GND
Clock Stabilizer Disabled
Clock Stabilizer Enabled
Clock Stabilizer Enabled
Clock Stabilizer Disabled
Table IV. Output Data Format
Input (V)
Condition (V)
Binary
Output Mode
VINA–VINB
VINA–VINB
VINA–VINB
VINA–VINB
VINA–VINB
< – VREF
= – VREF
=0
= + VREF – 1 LSB
≥ + VREF
0000 0000 0000
0000 0000 0000
1000 0000 0000
1111 1111 1111
1111 1111 1111
Two’s
Complement
Mode
OTR
1000 0000 0000
1000 0000 0000
0000 0000 0000
0111 1111 1111
0111 1111 1111
1
0
0
0
1
Out of Range (OTR)
An out-of-range condition exists when the analog input voltage
is beyond the input range of the converter. OTR is a digital
output that is updated along with the data output corresponding
to the particular sampled analog input voltage. Hence, OTR has
the same pipeline delay (latency) as the digital data. It is LOW
when the analog input voltage is within the analog input range.
It is HIGH when the analog input voltage exceeds the input
range as shown in Figure 14. OTR will remain HIGH until the
analog input returns within the input range and another conversion
is completed. By logical ANDing OTR with the MSB and its
complement, overrange high or underrange low conditions can be
detected. Table V is a truth table for the over/underrange
circuit in Figure 15, which uses NAND gates. Systems requiring
programmable gain conditioning of the AD9226 input signal
can immediately detect an out-of-range condition, thus eliminating gain selection iterations. Also, OTR can be used for
digital offset and gain calibration.
Table V. Out-of-Range Truth Table
LQFP Package
Pin 35 of the LQFP package determines the output data format
(DFS). If it is connected to AVSS, the output word will be straight
binary. If it is connected to AVDD, the output data format will
be two’s complement. See Table II.
Pin 43 of the LQFP package controls the clock stabilizer function
of the AD9226. If the pin is connected to AVSS, both clock
edges will be used in the conversion architecture. When Pin 43
is connected to AVDD, the internal duty cycle will be determined
by the clock stabilizer function within the ADC. See Table III.
OTR
MSB
Analog Input Is
0
0
1
1
0
1
0
1
In Range
In Range
Underrange
Overrange
+FS – 1 1/2 LSB
OTR DATA OUTPUTS
1
1111 1111 1111
0
1111 1111 1111
0
1111 1111 1110
OTR
–FS +1/2 LSB
Table II. DFS Pin Controls
DFS Function
Pin 35 Connection
Straight Binary
Two’s Complement
AVSS
AVDD
0
0
1
0000 0000 0001
0000 0000 0000
0000 0000 0000
–FS
–FS – 1/2 LSB
+FS
+FS – 1/2 LSB
Figure 14. OTR Relation to Input Voltage and Output Data
Table III. Clock Stabilizer Pin
MSB
Clock Restore Function
Pin 43 Connection
Clock Stabilizer Enabled
Clock Stabilizer Disabled
AVDD
AVSS
OVER = 1
OTR
MSB
UNDER = 1
Figure 15. Overrange or Underrange Logic
REV. B
–19–
AD9226
Digital Output Driver Considerations
The AD9226 output drivers can be configured to interface with
5 V or 3.3 V logic families by setting DRVDD to 5 V or 3.3 V
respectively. The output drivers are sized to provide sufficient
output current to drive a wide variety of logic families. However,
large drive currents tend to cause glitches on the supplies and may
affect converter performance. Applications requiring the ADC to
drive large capacitive loads or large fan outs may require external
buffers or latches.
OEB Function (Three-State)
The LQFP-packaged AD9226 has Three-State (OEB) ability. If
the OEB pin is held low, the output data drivers are enabled. If
the OEB pin is high, the output data drivers are placed in a high
impedance state. It is not intended for rapid access to buss.
3. The inherent distributed capacitor formed by the power
plane, PCB insulation, and ground plane.
It is important to design a layout that prevents noise from coupling onto the input signal. Digital signals should not be run in
parallel with input signal traces and should be routed away from
the input circuitry. While the AD9226 features separate analog
and driver ground pins, it should be treated as an analog component. The AVSS and DRVSS pins must be joined together
directly under the AD9226. A solid ground plane under the
ADC is acceptable if the power and ground return currents are
carefully managed.
AVDD
10␮F
AD9226
0.1␮F
Clock Input Considerations
AVSS
High-speed, high-resolution ADCs are sensitive to the quality of
the clock input. The clock input should be treated as an analog
signal in cases where aperture jitter may affect the dynamic
performance of the AD9226. Power supplies for clock drivers
should be separated from the ADC output driver supplies to
avoid modulating the clock signal with digital noise. Low-jitter
crystal controlled oscillators make the best clock sources.
The quality of the clock input, particularly the rising edge, is
critical in realizing the best possible jitter performance of the
part. Faster rising edges often have less jitter.
Clock Input and Power Dissipation
Most of the power dissipated by the AD9226 is from the analog
power supplies. However, lower clock speeds will reduce digital
current. Figure 16 shows the relationship between power and
clock rate.
Figure 17. Analog Supply Decoupling
Analog and Digital Driver Supply Decoupling
The AD9226 features separate analog and digital supply and
ground pins, helping to minimize digital corruption of sensitive
analog signals. In general, AVDD (analog power) should be
decoupled to AVSS (analog ground). The AVDD and AVSS
pins are adjacent to one another. Also, DRVDD (digital power)
should be decoupled to DRVDD (digital ground). The decoupling
capacitors (especially 0.1 µF) should be located as close to the
pins as possible. Figure 17 shows the recommended decoupling
for the pair of analog supplies; 0.1 µF ceramic chip and 10 µF
tantalum capacitors should provide adequately low impedance
over a wide frequency range.
600
CML
VR
AD9226
0.1␮F
0.1␮F
POWER DISSIPATION – mW
550
500
Figure 18. CML Decoupling (LQFP)
DRVDD = 5V
450
Bias Decoupling
The CML and VR are analog bias points used internally by the
AD9226. These pins must be decoupled with at least a 0.1 µF
capacitor as shown in Figure 18. The dc level of CML is approximately AVDD/2. This voltage should be buffered if it is to be
used for any external biasing. CML and VR outputs are only
available in the LQFP package.
400
DRVDD = 3V
350
300
250
200
5
15
25
35
45
55
65
75
DRVDD
SAMPLE RATE – Msps
10␮F
AD9226
DRVSS
Figure 16. Power Consumption vs. Sample Rate
GROUNDING AND DECOUPLING
Analog and Digital Grounding
Figure 19. Digital Supply Decoupling
Proper grounding is essential in any high-speed, high-resolution
system. Multilayer printed circuit boards (PCBs) are recommended to provide optimal grounding and power schemes. The
use of ground and power planes offers distinct advantages:
1. The minimization of the loop area encompassed by a signal
and its return path.
0.1␮F
CML
The LQFP-packaged AD9226 has a midsupply reference point.
This midsupply point is used within the internal architecture of
the AD9226 and must be decoupled with a 0.1 µF capacitor. It
will source or sink a load of up to 300 µA. If more current is
required, it should be buffered with a high impedance amplifier.
2. The minimization of the impedance associated with ground
and power paths.
–20–
REV. B
AD9226
VR
The clock input signal to the AD9226 evaluation board can be
applied to one of two inputs, CLOCK and AUXCLK. The
CLOCK input should be selected if the frequency of the input
clock signal is at the target sample rate of the AD9226. The
input clock signal is ac-coupled and level-shifted to the switching threshold of a 74VHC02 clock driver. The AUXCLK input
should be selected in applications requiring the lowest jitter and
SNR performance (i.e., IF Undersampling characterization). It
allows the user to apply a clock input signal that is 4× the target
sample rate of the AD9226. A low-jitter, differential divide-by-4
counter, the MC100EL33D, provides a 1× clock output that is
subsequently returned back to the CLOCK input via JP7. For
example, a 260 MHz signal (sinusoid) will be divided down to
a 65 MHz signal for clocking the ADC. Note, R1 must be
removed with the AUXCLK interface. Lower jitter is often
achieved with this interface since many RF signal generators
display improved phase noise at higher output frequencies and
the slew rate of the sinusoidal output signal is 4× that of a 1×
signal of equal amplitude.
VR is an internal bias point on the LQFP package. It must be
decoupled to ground with a 0.1 µF capacitor.
The digital activity on the AD9226 chip falls into two general
categories: correction logic and output drivers. The internal
correction logic draws relatively small surges of current, mainly
during the clock transitions. The output drivers draw large
current impulses while the output bits are changing. The size
and duration of these currents are a function of the load on the
output bits: large capacitive loads are to be avoided.
For the digital decoupling shown in Figure 19, 0.1 µF ceramic
chip and 10 µF tantalum capacitors are appropriate. Reasonable capacitive loads on the data pins are less than 20 pF per
bit. Applications involving greater digital loads should consider
increasing the digital decoupling proportionally and/or using
external buffers/latches.
A complete decoupling scheme will also include large tantalum
or electrolytic capacitors on the power supply connector to
reduce low-frequency ripple to negligible levels.
EVALUATION BOARD AND TYPICAL BENCH
CHARACTERIZATION TEST SETUP
The AD9226 evaluation board is configured to operate upon
applying both power and the analog and clock input signals. It
provides three possible analog input interfaces to characterize
the AD9226’s ac and dc performance. For ac characterization, it
provides a transformer coupled input with the common-mode
input voltage (CMV) set to AVDD/2. Note, the evaluation
board is shipped with a transformer coupled interface and a 2 V
input span. For differential dc coupled applications, the evaluation board has provisions to be driven by the AD8138 amplifier.
If a single-ended input is desired, it may be driven through the
S3 connector. The various input signal options are accessible by
the jumper connections. Refer to the Evaluation Board schematic.
Figure 20 shows the bench characterization setup used to evaluate the AD9226’s ac performance for many of the data sheet
characterization curves. Signal and Clock RF generators A and
B are high-frequency, “very” low-phase noise frequency sources.
These generators should be phase locked by sharing the same
10 MHz REF signal (located on the instruments back panel) to
allow for nonwindowed, coherent FFTs. Also, the AUXCLK
option on the AD9226 evaluation board should be used to
achieve the best SNR performance. Since the distortion and
broadband noise of an RF generator can often be a limiting
factor in measuring the true performance of an ADC, a high Q
passive bandpass filter should be inserted between the generator
and AD9226 evaluation board.
5V
AVDD
REFIN
SIGNAL SYNTHESIZER
65(OR 260MHz), 4V p-p
HP8644
1MHz
BANDPASS FILTER
S4
INPUT
xFMR
5V
GND
3V
DUT GND
AVDD
3V
DUT
DVDD
AD9226
EVALUATION BOARD
10MHz
REFOUT
CLK SYNTHESIZER
65(OR 260MHz), 4V p-p
HP8644
S1
INPUT
CLOCK
S4
AUX CLOCK
(ⴜ4)
Figure 20. Evaluation Board Connections
REV. B
–21–
DVDD
OUTPUT
WORD
(P1)
DSP
EQUIPMENT
AD9226
DUTAVDD
TP5
WHT
JP23
JP22
C1
10␮F
10V
JP25
R3
10k⍀
C36
0.1␮F
C39
0.001␮F
4
JP24
R4
10k⍀
C21
10␮F
10V
AD9226LQFP
3
1
C35
0.1␮F
2
36
37
38
C34
0.1␮F
39
C20
10␮F
10V
40
C33
0.1␮F
41
42
C32
0.1␮F
45
C50
0.1␮F
DUTAVDDIN TB1 2
FBEAD
2
C58
22␮F
25V
L1
1
TP2
RED
VINA
SHEET 3
VINB
47
5
DUTAVDD
6
C59
0.1␮F
32
AGND TB1 3
33
DUTAVDD
AVDDIN TB1 1
46
FBEAD
2
C47
22␮F
25V
L2
1
TP1
RED
AVDD
C23
10␮F
10V
31
C38
0.1␮F
C41
0.001␮F
C52
0.1␮F
34
30
29
23
22
DRVDDIN TB1 5
FBEAD
2
C48
22␮F
25V
L3
1
AVDD1
OTR
AVDD2
MSB-B1
AVSS1
B2
AVSS2
B3
SENSE
B4
VREF
B5
REFCOM
B6
CAPB1
B7
CAPB2
B8
CAPT1
B9
CAPT2
B10
CML
U1
B11
VINA
B12
VINB
B13
NC1
LSB-B14
NC2
NC3
AVSS3
OEB
AVSS4
VR
AVDD3
DFS
AVDD4
DUTY
CLK
DRVSS3
DRVDD3
NC4
DRVDD1
DRVDD2
DRVSS1
DRVSS2
28
OTR0
27
D130
26
D120
25
D110
24
D100
21
D90
20
D80
19
D70
18
D60
17
D50
16
D40
13
D20
11
DUTDRVDD
DUTDRVDD
AGND TB1 4
JP6
D10
10
JP1
D00
8
JP2
9
48
35
R42
1k⍀
43
C2
0.1␮F
R6
1k⍀
7
44
R10
1k⍀
15
14
DUTCLK
TP3
RED
C53
0.1␮F
AVDD
D30
12
WHT
TP6
C3
10␮F
10V
C37
0.1␮F
C40
0.001␮F
NC = NO CONNECT
FBEAD
2
DVDDIN TB1 6
C6
22␮F
25V
L4
1
C14
0.1␮F
TP4
RED
DVDD
TP11
TP12
TP13
TP14
BLK
BLK
BLK
BLK
Figure 21. AD9226 Evaluation Board
–22–
REV. B
AD9226
C12
0.1␮F
DVDD
10V C4 10␮F
1
2
1 74VHC541 20
G1
AUXCLK
S5
1
2
1N5712
T1–1T
6
5
R11
49.9⍀
4
G2
1
T2
2
D2
3
2
2
D13
2
D1
D12
1N5712
D11
3
4
5
D10
6
D9
8
AVDD
7
6
5
AVDD
R12
113⍀
MC100EL33D
VCC
OUT
VEE
INA
INB
INCOM
7
D8
1
8
D7
2
9
D6
3
Y1
A2
Y2
Y4
A5
Y5
A6
Y6
A7
Y7
A8
Y8
C19
0.1␮F
C26
10␮F
10V
2
U3
DECOUPLING
2
AVDD
74VHC04
8
8f
5
D2
6
D1
11
8b
R7
DUTCLK
10 22⍀
74VHC04 JP4
8c
2
7
D0
8
R9 OTR
22⍀
13
RP1
6 22⍀ 11
12
RP1
7 22⍀ 10
11
RP1
8 22⍀ 9
RP2
1 22⍀ 16
G1
VCC
G2
GND
A1
Y1
A2
Y2
9
A3
U7
Y3
A4
Y4
A5
Y5
A6
Y6
A7
Y7
A8
Y8
10
18
17
16
15
RP2
3 22⍀ 14
RP2
4 22⍀ 13
RP2
5 22⍀ 12
RP2
6 22⍀ 11
13
3 P1
P1 4
5 P1
P1 6
7 P1
P1 8
9 P1
P1 10
11 P1
P1 12
13 P1
P1 14
15 P1
P1 16
17 P1
P1 18
19 P1
P1 20
21 P1
P1 22
23 P1
P1 24
25 P1
P1 26
27 P1
P1 28
29 P1
P1 30
31 P1
P1 32
33 P1
P1 34
35 P1
P1 36
37 P1
P1 38
39 P1
P1 40
12
11
RP2
8 22⍀ 9
AVDD
C10
0.1␮F
C3
10␮F
10V
U8
DECOUPLING
RP2
7 22⍀ 10
NC = NO CONNECT
4
74VHC04
Figure 22. AD9226 Evaluation Board
REV. B
RP2
2 22⍀ 15
P1 2
14
JP3
6
74VHC04
3
RP1
5 22⍀ 12
1 P1
74VHC04
74VHC04
8e
4
D3
1
5
3
D4
1
A
2 TP7
C13
WHT 8a
0.10␮F
13
12
9
14
19
B
8d
RP1
4 22⍀ 13
1 74VHC541 20
JP17
R1
49.9⍀
15
10V C5 10␮F
1
2
D5
CLOCK
S1
1
16
C11
0.1␮F
JP7
R19 R2 R18
4k⍀ 5k⍀ 4k⍀
RP1
3 22⍀ 14
17
Y3
A4
RP1
2 22⍀ 15
18
4
C18
0.1␮F
R15
90⍀
3
U6
AVDD
R13
113⍀
R14
90⍀
U3
REF
AVDD
C17
0.1␮F
NC
10
GND
A1
A3
RP1
1 22⍀ 16
VCC
19
–23–
AD9226
OTRO
D130
D120
D110
D100
D90
D80
D70
RP3
1 22⍀ 8
RP3
2 22⍀ 7
RP3
3 22⍀ 6
RP3
4 22⍀ 5
2
RP4
22⍀ 8
RP4
22⍀ 7
3
RP4
22⍀ 6
4
RP4
22⍀ 5
1
R34
523⍀
AMP INPUT
S2
1
2
R35
499⍀
R31
49.9⍀
OTR
D13
JP5
AVDD
SINGLE
INPUT
S3
1
D12
D11
2
AVDD
D10
D9
C15
10␮F
10V
1
2
C7
0.1␮F
JP42
R5
49.9⍀
R41
1k⍀
JP40
R32
10k⍀
R33
10k⍀
R37
499⍀
D7
R40
1k⍀
AVDD
C69
0.1␮F
D8
C9
0.33␮F
JP45
R21
22⍀
JP46
R22
22⍀
C8
0.1␮F
C44
TBD
VINA
C24
SHEET 1
50pF
VINB
C43
TBD
JP41
3
1
JP43
VCC
–W
4
U2
8
ⴙW
VEE
6
VOⴙ
VDC
VO–
2
D60
D50
5
AD8138
R36
499⍀
XFMR INPUT
S4
1
2
R24
49.9⍀
DUTAVDD
6
T1–1T
4
1
D40
R38
1k⍀
T2
3
R8
1k⍀
RP5
3 22⍀ 6
D6
D5
D4
RP5
4 22⍀ 5
2
5
RP5
1 22⍀ 8
RP5
2 22⍀ 7
C25
0.33␮F
C16
0.1␮F
D30
D20
D10
D00
RP6
1 22⍀ 8
RP6
2 22⍀ 7
RP6
3 22⍀ 6
RP6
4 22⍀ 5
D3
D2
D1
D0
Figure 23. AD9226 Evaluation Board
Figure 24. Evaluation Board Component Side Layout (Not to Scale)
–24–
REV. B
AD9226
Figure 25. Evaluation Board Solder Side Layout (Not to Scale)
Figure 26. Evaluation Board Power Plane
REV. B
–25–
AD9226
Figure 27. Evaluation Board Ground Plane
Figure 28. Evaluation Board Component Side (Not to Scale)
–26–
REV. B
AD9226
Figure 29. Evaluation Board Solder Side (Not to Scale)
REV. B
–27–
AD9226
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
48-Lead Thin Plastic Quad Flatpack
(ST-48)
0.063 (1.60)
MAX
0.030 (0.75)
0.018 (0.45)
0.407 (10.34)
0.397 (10.08)
0.354 (9.00) BSC SQ
36
1
15
0.311 (7.9)
0.301 (7.64)
0.078 (1.98) PIN 1
0.068 (1.73)
0.008 (0.203) 0.0256
(0.65)
0.002 (0.050) BSC
14
COPLANARITY
0.003 (0.08)
0ⴗ
MIN
12
25
13
0.019 (0.5)
BSC
0.008 (0.2)
0.004 (0.09)
0.07 (1.79)
0.066 (1.67)
8°
0.015 (0.38)
0°
SEATING 0.009 (0.229)
0.010 (0.25)
PLANE
0.005 (0.127)
0.276
(7.00)
BSC
SQ
TOP VIEW
(PINS DOWN)
24
0.011 (0.27)
0.006 (0.17)
0.057 (1.45)
0.053 (1.35)
7ⴗ
0ⴗ
0.03 (0.762)
0.022 (0.558)
0.006 (0.15) SEATING
0.002 (0.05) PLANE
PRINTED IN U.S.A.
1
37
48
0.212 (5.38)
0.205 (5.21)
28
C01027–0–3/01(B)
28-Lead Shrink Small Outline
(RS-28)
–28–
REV. B