TI1 AAV0144A 6.4-gsps single channel or 3.2-gsps dual channel, 12-bit, rf-sampling analog-to-digital converter (adc) Datasheet

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ADC12DJ3200
SLVSD97 – MAY 2017
1 Features
3 Description
•
ADC12DJ3200 is an RF-sampling giga-sample ADC
that can directly sample input frequencies from DC to
above 10 GHz. In dual channel mode, ADC12DJ3200
can sample up to 3200-MSPS and in single channel
mode up to 6400-MSPS. Programmable tradeoffs in
channel count (dual channel mode) and Nyquist
bandwidth (single channel mode) allow development
of flexible hardware that meets the needs of both high
channel count or wide instantaneous signal
bandwidth applications. Full power input bandwidth (3 dB) of 8.0 GHz, with usable frequencies exceeding
the -3 dB point in both dual and single channel
modes, allows direct RF sampling of L-band, S-band,
C-band and X-band for frequency agile systems.
1
•
•
•
•
•
•
•
•
ADC Core:
– 12-bit Resolution
– Up to 6.4 GSPS in single channel mode
– Up to 3.2 GSPS in dual channel mode
Buffered Analog Inputs with VCMI of 0 V
– Analog input bandwidth (-3 dB): 8.0 GHz
– Usable input frequency range: >10 GHz
– Full-scale input voltage (VFS, default): 0.8 VPP
Noise Floor (No signal, VFS = 1.0 VPP):
– Dual channel mode: -151.8 dBFS/Hz
– Single channel mode: -154.6 dBFS/Hz
Noiseless Aperture Delay (TAD) Adjustment
– Precise sampling control: 19-fs step
– Temperature and voltage invariant delays
Easy-to-use Synchronization Features
– Automatic SYSREF timing calibration
– Timestamp for sample marking
JESD204B Serial Data Interface
– Supports subclass 0 and 1
– Maximum lane rate: 12.8 Gbps
– Up to 16 lanes allows reduced lane rate
Digital Down-Converters in Dual Channel Mode
– Real output: DDC bypass or 2x decimation
– Complex output: 4x, 8x or 16x decimation
– Four independent 32-bit NCOs per DDC
Power consumption: 3.0 W
Power Supplies: 1.1 V, 1.9 V
ADC12DJ3200 uses a high speed JESD204B output
interface with up to 16 serialized lanes and subclass1 compliance for deterministic latency and multidevice synchronization. The serial output lanes
support up to 12.8 Gbps and can be configured to
trade-off bit rate and number of lanes. Innovative
synchronization features including noiseless aperture
delay (TAD) adjustment and SYSREF windowing
simplify system design for phased array radar and
MIMO communications. Optional digital down
converters (DDCs) in dual channel mode allow for
reduction in interface rate (real and complex
decimation modes) and digital mixing of the signal
(complex decimation modes only).
Device Information(1)
PART NUMBER
ADC12DJ3200
FCBGA (144) 10.00 mm x 10.00 mm
ADC12DJ3200 Measured Input Bandwidth
3
Normalized Gain Response (dB)
Communications testers (802.11ad, 5G)
Satellite communications (SATCOM)
Phased array radar, SIGINT and ELINT
Synthetic aperture radar (SAR)
Time-of-flight and LIDAR distance measurement
Oscilloscopes and wideband digitizers
RF sampling software defined radio (SDR)
BODY SIZE (NOM)
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
•
•
•
•
•
•
•
PACKAGE
0
-3
-6
-9
Single Channel Mode
Dual Channel Mode
-12
-15
0
2
4
6
8
Input Frequency (GHz)
10
12
D_BW
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to
change without notice.
ADVANCE INFORMATION
ADC12DJ3200 6.4-GSPS Single Channel or 3.2-GSPS Dual Channel,
12-bit, RF-Sampling Analog-to-Digital Converter (ADC)
ADC12DJ3200
SLVSD97 – MAY 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
1
1
1
2
3
8
7
Detailed Description ............................................ 25
7.1
7.2
7.3
7.4
7.5
7.6
Absolute Maximum Ratings ...................................... 8
ESD Ratings.............................................................. 8
Recommended Operating Conditions....................... 9
Thermal Information ................................................ 10
Electrical Characteristics - DC Specifications ......... 11
Electrical Characteristics - Power Consumption ..... 12
Electrical Characteristics - AC Specifications ......... 14
Timing Requirements .............................................. 21
Switching Characteristics ........................................ 21
8
25
26
26
42
57
58
Device and Documentation Support................ 105
8.1
8.2
8.3
8.4
8.5
8.6
9
Overview .................................................................
Functional Block Diagrams .....................................
Feature Description.................................................
Device Functional Modes........................................
Programming...........................................................
Register Maps .........................................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
105
105
105
105
105
105
Mechanical, Packaging, and Orderable
Information ......................................................... 106
ADVANCE INFORMATION
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
2
DATE
REVISION
NOTES
May 2017
*
Initial release
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SLVSD97 – MAY 2017
5 Pin Configuration and Functions
A
AGND
AGND
AGND
INA+
INA-
AGND
AGND
DA3+
DA3-
DA2+
DA2-
DGND
B
TMSTP+
AGND
AGND
AGND
AGND
AGND
AGND
DA7+
DA7-
DA6+
DA6-
DGND
C
TMSTP-
SYNCSE
BG
VA19
VA11
AGND
NCOA0
ORA0
VD11
VD11
DA5+
DA1+
D
AGND
VA11
VA11
VA19
VA11
AGND
NCOA1
ORA1
DGND
DGND
DA5-
DA1-
E
AGND
VA19
VA19
VA19
VA11
AGND
CALTRIG
SCS
VD11
VD11
DA4+
DA0+
F
CLK+
AGND
AGND
VA19
VA11
AGND
CALSTAT
SCLK
DGND
DGND
DA4-
DA0-
G
CLK-
AGND
AGND
VA19
VA11
AGND
VD11
SDI
DGND
DGND
DB4-
DB0-
H
AGND
VA19
VA19
VA19
VA11
AGND
VD11
SDO
VD11
VD11
DB4+
DB0+
J
AGND
VA11
VA11
VA19
VA11
AGND
NCOB1
ORB1
DGND
DGND
DB5-
DB1-
K
SYSREF+
TDIODE+
TDIODE-
VA19
VA11
PD
NCOB0
ORB0
VD11
VD11
DB5+
DB1+
L
SYSREF-
AGND
AGND
AGND
AGND
AGND
AGND
DB7+
DB7-
DB6+
DB6-
DGND
M
AGND
AGND
AGND
INB+
INB-
AGND
AGND
DB3+
DB3-
DB2+
DB2-
DGND
1
2
3
4
5
6
7
8
9
10
11
12
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ADVANCE INFORMATION
AAV Package
144-Ball Flip Chip BGA
Top View
3
ADC12DJ3200
SLVSD97 – MAY 2017
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Pin Functions
PIN
I/O
DESCRIPTION
ADVANCE INFORMATION
NAME
NO.
AGND
A1, A2, A3,
A6, A7, B2,
B3, B4, B5,
B6, B7, C6,
D1, D6, E1,
E6, F2, F3,
F6, G2, G3,
G6, H1, H6,
J1, J6, L2,
L3, L4, L5,
L6, L7, M1,
M2, M3, M6,
M7
—
Analog supply ground. AGND and DGND should be tied to a common ground plane (GND)
on circuit board.
DGND
A12, B12,
D9, D10, F9,
F10, G9,
G10, J9, J10,
L12, M12
—
Digital supply ground. AGND and DGND should be tied to a common ground plane (GND)
on circuit board.
BG
C3
O
Bandgap voltage output. This pin is capable of sourcing only small currents and driving
limited capacitive loads as specified in Recommended Operating Conditions. This pin can be
left disconnected if not used.
CALSTAT
F7
O
Foreground calibration status output or device alarm output. Functionality is programmed
through CAL_STATUS_SEL. This pin can be left disconnected if not used.
CALTRIG
E7
I
Foreground calibration trigger input. This pin is only used if hardware calibration triggering is
selected in CAL_TRIG_EN, otherwise software triggering is performed using
CAL_SOFT_TRIG. This pin should be tied to GND if not used.
CLK+
F1
I
Device (sampling) clock positive input. The clock signal is strongly recommended to be AC
coupled to this input for best performance. In single channel mode, the analog input signal is
sampled on both rising and falling edges. In dual channel mode, the analog signal is
sampled on the rising edge. This differential input has an internal 100-Ω differential
termination and is self-biased to the optimal input common mode voltage as long as
DEVCLK_LVPECL_EN is set to 0.
CLK-
G1
I
Device (sampling) clock negative input. Must be AC coupled.
DA0+
E12
O
High-speed serialized-data output for channel A, lane 0, positive connection. This differential
output must be AC-coupled and must always be terminated with a 100-Ω differential
termination at the receiver. This pin can be left disconnected if not used.
DA0-
F12
O
High-speed serialized-data output for channel A, lane 0, negative connection. This pin can
be left disconnected if not used.
DA1+
C12
O
High-speed serialized-data output for channel A, lane 1, positive connection. This differential
output must be AC-coupled and must always be terminated with a 100-Ω differential
termination at the receiver. This pin can be left disconnected if not used.
DA1-
D12
O
High-speed serialized-data output for channel A, lane 1, negative connection. This pin can
be left disconnected if not used.
DA2+
A10
O
High-speed serialized-data output for channel A, lane 2, positive connection. This differential
output must be AC-coupled and must always be terminated with a 100-Ω differential
termination at the receiver. This pin can be left disconnected if not used.
DA2-
A11
O
High-speed serialized-data output for channel A, lane 2, negative connection. This pin can
be left disconnected if not used.
DA3+
A8
O
High-speed serialized-data output for channel A, lane 3, positive connection. This differential
output must be AC-coupled and must always be terminated with a 100-Ω differential
termination at the receiver. This pin can be left disconnected if not used.
DA3-
A9
O
High-speed serialized-data output for channel A, lane 3, negative connection. This pin can
be left disconnected if not used.
DA4+
E11
O
High-speed serialized-data output for channel A, lane 4, positive connection. This differential
output must be AC-coupled and must always be terminated with a 100-Ω differential
termination at the receiver. This pin can be left disconnected if not used.
DA4-
F11
O
High-speed serialized-data output for channel A, lane 4, negative connection. This pin can
be left disconnected if not used.
4
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PIN
I/O
DESCRIPTION
C11
O
High-speed serialized-data output for channel A, lane 5, positive connection. This differential
output must be AC-coupled and must always be terminated with a 100-Ω differential
termination at the receiver. This pin can be left disconnected if not used.
DA5-
D11
O
High-speed serialized-data output for channel A, lane 5, negative connection. This pin can
be left disconnected if not used.
DA6+
B10
O
High-speed serialized-data output for channel A, lane 6, positive connection. This differential
output must be AC-coupled and must always be terminated with a 100-Ω differential
termination at the receiver. This pin can be left disconnected if not used.
DA6-
B11
O
High-speed serialized-data output for channel A, lane 6, negative connection. This pin can
be left disconnected if not used.
DA7+
B8
O
High-speed serialized-data output for channel A, lane 7, positive connection. This differential
output must be AC-coupled and must always be terminated with a 100-Ω differential
termination at the receiver. This pin can be left disconnected if not used.
DA7-
B9
O
High-speed serialized-data output for channel A, lane 7, negative connection. This pin can
be left disconnected if not used.
DB0+
H12
O
High-speed serialized-data output for channel B, lane 0, positive connection. This differential
output must be AC-coupled and must always be terminated with a 100-Ω differential
termination at the receiver. This pin can be left disconnected if not used.
DB0-
G12
O
High-speed serialized-data output for channel B, lane 0, negative connection. This pin can
be left disconnected if not used.
DB1+
K12
O
High-speed serialized-data output for channel B, lane 1, positive connection. This differential
output must be AC-coupled and must always be terminated with a 100-Ω differential
termination at the receiver. This pin can be left disconnected if not used.
DB1-
J12
O
High-speed serialized-data output for channel B, lane 1, negative connection. This pin can
be left disconnected if not used.
DB2+
M10
O
High-speed serialized-data output for channel B, lane 2, positive connection. This differential
output must be AC-coupled and must always be terminated with a 100-Ω differential
termination at the receiver. This pin can be left disconnected if not used.
DB2-
M11
O
High-speed serialized-data output for channel B, lane 2, negative connection. This pin can
be left disconnected if not used.
DB3+
M8
O
High-speed serialized-data output for channel B, lane 3, positive connection. This differential
output must be AC-coupled and must always be terminated with a 100-Ω differential
termination at the receiver. This pin can be left disconnected if not used.
DB3-
M9
O
High-speed serialized-data output for channel B, lane 3, negative connection. This pin can
be left disconnected if not used.
DB4+
H11
O
High-speed serialized-data output for channel B, lane 4, positive connection. This differential
output must be AC-coupled and must always be terminated with a 100-Ω differential
termination at the receiver. This pin can be left disconnected if not used.
DB4-
G11
O
High-speed serialized-data output for channel B, lane 4, negative connection. This pin can
be left disconnected if not used.
DB5+
K11
O
High-speed serialized-data output for channel B, lane 5, positive connection. This differential
output must be AC-coupled and must always be terminated with a 100-Ω differential
termination at the receiver. This pin can be left disconnected if not used.
DB5-
J11
O
High-speed serialized-data output for channel B, lane 5, negative connection. This pin can
be left disconnected if not used.
DB6+
L10
O
High-speed serialized-data output for channel B, lane 6, positive connection. This differential
output must be AC-coupled and must always be terminated with a 100-Ω differential
termination at the receiver. This pin can be left disconnected if not used.
DB6-
L11
O
High-speed serialized-data output for channel B, lane 6, negative connection. This pin can
be left disconnected if not used.
DB7+
L8
O
High-speed serialized-data output for channel B, lane 7, positive connection. This differential
output must be AC-coupled and must always be terminated with a 100-Ω differential
termination at the receiver. This pin can be left disconnected if not used.
DB7-
L9
O
High-speed serialized-data output for channel B, lane 7, negative connection. This pin can
be left disconnected if not used.
NAME
NO.
DA5+
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Pin Functions (continued)
5
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Pin Functions (continued)
PIN
NAME
NO.
I/O
DESCRIPTION
Channel A analog input positive connection. The differential full-scale input range is
determined by the full-scale voltage adjust register. The input common mode voltage should
be set to AGND. This input is terminated to ground through a 50-Ω termination resistor. This
pin can be left disconnected if not used.
INA+
A4
I
NOTE
Use of INA+/– is recommended for single channel
mode for optimized performance.
ADVANCE INFORMATION
INA-
A5
I
Channel A analog input negative connection. This input is terminated to ground through a
50-Ω termination resistor. This pin can be left disconnected if not used.
INB+
M4
I
Channel B analog input positive connection. The differential full-scale input range is
determined by the full-scale voltage adjust register. The input common mode voltage should
be set to AGND. This input is terminated to ground through a 50-Ω termination resistor. This
pin can be left disconnected if not used.
INB-
M5
I
Channel B analog input negative connection. This input is terminated to ground through a
50-Ω termination resistor. This pin can be left disconnected if not used.
NCOA0
C7
I
NCO accumulator selection control LSB for DDC A. NCOA0 and NCOA1 select which NCO,
of a possible four NCOs, is used for digital mixing. The remaining unselected NCOs continue
to run to maintain phase coherency and can be swapped in by changing the values of
NCOA0 and NCOA1. This is an asynchronous input. This pin should be tied to GND if not
used.
NCOA1
D7
I
NCO accumulator selection control MSB for DDC A. This pin should be tied to GND if not
used.
NCOB0
K7
I
NCO accumulator selection control LSB for DDC B. NCOB0 and NCOB1 select which NCO,
of a possible four NCOs, is used for digital mixing. The remaining unselected NCOs continue
to run to maintain phase coherency and can be swapped in by changing the values of
NCOB0 and NCOB1. This is an asynchronous input. This pin should be tied to GND if not
used.
NCOB1
J7
I
NCO accumulator selection control MSB for DDC B. This pin should be tied to GND if not
used.
ORA0
C8
O
Fast over-range detection status for channel A for T0 threshold. When the analog input
exceeds the threshold programmed into OVR_T0, this status will go high. The minimum
pulse duration is set by OVR_N. This pin can be left disconnected if not used.
ORA1
D8
O
Fast over-range detection status for channel A for T1 threshold. When the analog input
exceeds the threshold programmed into OVR_T1, this status will go high. The minimum
pulse duration is set by OVR_N. This pin can be left disconnected if not used.
ORB0
K8
O
Fast over-range detection status for channel B for T0 threshold. When the analog input
exceeds the threshold programmed into OVR_T0, this status will go high. The minimum
pulse duration is set by OVR_N. This pin can be left disconnected if not used.
ORB1
J8
O
Fast over-range detection status for channel B for T1 threshold. When the analog input
exceeds the threshold programmed into OVR_T1, this status will go high. The minimum
pulse duration is set by OVR_N. This pin can be left disconnected if not used.
PD
K6
I
This pin disables all analog circuits and serializer outputs when set high for temperature
diode calibration only. This pin should not be used to power down the device for power
savings. This pin should be tied to GND during normal operation. Please see note beneath
Recommended Operating Conditions for more information.
SCLK
F8
I
Serial interface clock. This pin functions as the serial-interface clock input which clocks the
serial programming data in and out. Using the Serial Interface describes the serial interface
in more detail. Supports 1.1 V and 1.8 V CMOS levels.
SCS
E8
I
Serial interface chip select active low input. Using the Serial Interface describes the serial
interface in more detail. Supports 1.1 V and 1.8 V CMOS levels. This pin has a 82-kΩ pull-up
resistor to VD11.
SDI
G8
I
Serial interface data input. Using the Serial Interface describes the serial interface in more
detail. Supports 1.1 V and 1.8 V CMOS levels.
O
Serial interface data output. Using the Serial Interface describes the serial interface in more
detail. This pin is high impedance during normal device operation. This pin outputs 1.9-V
CMOS levels during serial interface read operations. This pin can be left disconnected if not
used.
SDO
6
H8
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Pin Functions (continued)
SYNCSE
NO.
C2
I/O
DESCRIPTION
I
JESD204B SYNC signal single-ended active low input. This pin provides the JESD204Brequired synchronization request input. A logic low applied to this input initiates code group
synchronization and the initial lane alignment sequence. The choice of single-ended or
differential SYNC (using TMSTP+ and TMSTP- pins) is selected by programming
SYNC_SEL. This pin should be tied to GND if differential SYNC (TMSTP+/-) is used as the
JESD204B SYNC signal.
SYSREF+
K1
I
SYSREF positive input used to achieve synchronization and deterministic latency across the
JESD204B interface. This differential input (SYSREF+ to SYSREF–) has an internal 100-Ω
differential termination. It is self-biased when AC coupled (SYSREF_LVPECL_EN must be
set to 0), but can be DC coupled by setting SYSREF_LVPECL_EN to 1 which changes the
internal termination to 50-Ω single-ended termination to ground on each SYSREF+ and
SYSREF– input. The common mode voltage must be within the recommended range when
DC coupled.
SYSREF-
L1
I
SYSREF negative input.
TDIODE+
K2
I
Temperature diode positive (anode) connection. An external temperature sensor can be
connected to TDIODE+ and TDIODE- to monitor the junction temperature of the device. This
pin can be left disconnected if not used.
TDIODE-
K3
I
Temperature diode negative (cathode) connection. This pin can be left disconnected if not
used.
TMSTP+
B1
I
Timestamp input positive connection or differential JESD204B SYNC positive connection.
This input is used as the timestamp input when SYNC_SEL is set 0 to use SYNCSE as the
JESD204B SYNC signal. This input is used as the JESD204B SYNC signal when
SYNC_SEL is set to use TMSTP+ and TMSTP- as the JESD204B SYNC signal, in which
case TMSTP+/– uses active low signaling. For additional usage information as timestamp
input, see Timestamp. This differential input (TMSTP+ to TMSTP–) has an internal 100-Ω
differential termination. This pin is never self-biased and therefore it must be externally
biased for both AC and DC coupled configurations. AC coupling can be used when
TMSTP_LVPECL_EN is set to 0. TMSTP+/– can be DC coupled by setting
TMSTP_LVPECL_EN to 1 which changes the internal termination to 50-Ω single-ended
termination to ground on each TMSTP+ and TMSTP– input. The common mode voltage
must be within the recommended range when both AC and DC coupled. This pin can be left
disconnected if SYNCSE is used for JESD204B SYNC and timestamp is not required.
TMSTP-
C1
I
Timestamp input positive connection or differential JESD204B SYNC negative connection.
This pin can be left disconnected if SYNCSE is used for JESD204B SYNC and timestamp is
not required.
VA11
C5, D2, D3,
D5, E5, F5,
G5, H5, J2,
J3, J5, K5
I
1.1-V analog supply.
VA19
C4, D4, E2,
E3, E4, F4,
G4, H2, H3,
H4, J4, K4
I
1.9-V analog supply.
VD11
C9, C10, E9,
E10, G7, H7,
H9, H10, K9,
K10
I
1.1-V digital supply.
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PIN
NAME
7
ADC12DJ3200
SLVSD97 – MAY 2017
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6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
VA19 (2)
-0.3
2.35
V
(2)
-0.3
1.32
V
VD11 (3)
-0.3
1.32
V
Voltage between VD11 and VA11
-1.32
1.32
V
VA11
Supply Voltage Range
Voltage between AGND and DGND
-0.1
0.1
V
DA0...7+, DA0...7-, DB0...7+, DB0...7-,
TMSTP+, TMSTP– (3)
-0.5
min(1.32,
VD11+0.5)
V
CLK+, CLK–, SYSREF+, SYSREF– (2)
-0.5
min(1.32,
VA11+0.5)
V
BG, TDIODE+, TDIODE– (2)
-0.5
min(2.35,
VA19+0.5)
V
-1
1
V
-0.5
VA19+0.5
V
Peak input current (any input except INA+, INA–, INB+, INB–)
-25
25
mA
Peak input current (INA+, INA–, INB+, INB–)
-50
50
mA
16.4
dBm
100
mA
150
°C
150
°C
Terminal Voltage Range
INA+, INA–, INB+, INB– (2)
ADVANCE INFORMATION
CALSTAT, CALTRIG, NCOA0, NCOA1,
NCOB0, NCOB1, ORA0, ORA1, ORB0,
ORB1, PD, SCLK, SCS, SDI, SDO,
SYNCSE (2)
Peak RF input power (INA+, INA–, INB+, INB–)
Single-ended with ZS-SE = 50 Ω or differential
with ZS-DIFF = 100 Ω
Peak total input current (sum of absolute value of all currents forced in or out, not including
power supply current)
Operating junction temperature, Tj
Storage temperature, Tstg
(1)
(2)
(3)
-65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Measured to AGND.
Measured to DGND.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
8
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
± 2500
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
± 1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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6.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)
Supply Voltage Range
VCMI
Input common mode voltage
Input voltage, peak-to-peak
differential
NOM
1.8
1.9
2.0
V
1.1
1.15
V
VD11, Digital 1.1V supply (2)
1.05
1.1
1.15
V
INA+, INA–, INB+, INB– (1)
-50
0
100
mV
CLK+, CLK–, SYSREF+,
SYSREF– (1) (3)
0.0
0.3
0.55
V
0.0
0.3
0.55
V
0.4
1.0
2.0
VPP-DIFF
(1) (4)
CLK+ to CLK–, SYSREF+ to
SYSREF–, TMSTP+ to TMSTP–
INA+ to INA–, INB+ to INB–
1.0
VIH
High level input voltage
VIL
Low level input voltage
CALTRIG, NCOA0, NCOA1, NCOB0,
NCOB1, PD, SCLK, SCS, SDI,
SYNCSE (1)
IC_TD
Temperature diode input current
TDIODE+ to TDIODE–
CL
BG max load capacitance
IO
BG max output current
DC
Input clock duty cycle
30
TA
Operating free-air temperature
-40
Tj
Operating junction temperature
(4)
(5)
(6)
(7)
UNIT
1.05
CALTRIG, NCOA0, NCOA1, NCOB0,
NCOB1, PD, SCLK, SCS, SDI,
SYNCSE (1)
(1)
(2)
(3)
MAX
VA11, Analog 1.1V supply (1)
TMSTP+, TMSTP–
VID
MIN
(5)
VPP-DIFF
0.7
V
0.45
100
50
V
µA
50
pF
100
µA
70
%
85
ºC
105 (6) (7)
ºC
Measured to AGND.
Measured to DGND.
It is strongly recommended that CLK+/– be AC coupled with DEVCLK_LVPECL_EN set to 0 to allow CLK+/– to self bias to the optimal
input common mode voltage for best performnace. TI recommends AC coupling for SYSREF+/– unless DC coupling is required, in
which case LVPECL input mode must be used (SYSREF_LVPECL_EN = 1).
TMSTP+/– does not have internal biasing which requires TMSTP+/– to be biased externally whether AC coupled with
TMSTP_LVPECL_EN = 0 or DC coupled with TMSTP_LVPECL_EN = 1.
ADC output code will saturate when VID for INA+/– or INB+/– exceeds the programmed full-scale voltage (VFS) set by FS_RANGE_A for
INA+/– or FS_RANGE_B for INB+/–.
Prolonged use above this junction temperature may increase the device failure-in-time (FIT) rate.
Tested up to 1000 hours continuous operation at Tj = 125°C. See Absolute Maximum Ratings for absolute maximum operational
temperature.
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ADVANCE INFORMATION
VA19, Analog 1.9V supply
VDD
(1)
ADC12DJ3200
SLVSD97 – MAY 2017
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ADVANCE INFORMATION
NOTE
Power down of the high speed data outputs (DA0+/– ... DA7+/–, DB0+/– ... DB7+/–) for
extended times may reduce performance of the output serializers, especially at high data
rates. Power down of the serializers occurs when the PD pin is held high, the MODE
register is programmed to a value other than 0x00 or 0x01, PD_ACH or PD_BCH registers
settings are programmed to 1 or when the JMODE register setting is programmed to a
mode that uses less than the 16 total lanes the device allows. For instance, JMODE 0
uses eight total lanes and therefore the four highest indexed lanes for each JESD204B
link (DA4+/– ... DA7+/–, DB4+/– ... DB7+/–) are powered down in this mode. When the PD
pin is held high or the MODE register is programmed to a value other than 0x00 or 0x01
then all of the output serializers are powered down. When PD_ACH or PD_BCH register
settings are programmed to 1 the associated ADC channel and lanes are powered down.
To prevent unreliable operation the PD pin and MODE register should only be used for
brief periods of time to measure temperature diode offsets and not used for long-term
power savings. Further, use of a JMODE that uses fewer than 16 lanes will result in
unreliable operation of the unused lanes. If the system will never use the unused lanes
during the lifetime of the device then the unused lanes will not cause issues and can be
powered down. If the system may make use of the unused lanes at a later time, the
reliable operation of the serializer outputs can be maintained by enabling JEXTRA_A and
JEXTRA_B which results in VD11 power consumption to increase and the output
serializers to toggle.
6.4 Thermal Information
ADC12DJ3200
THERMAL METRIC (1)
AAV (FCBGA)
UNIT
144 PINS
RθJA
Junction-to-ambient thermal resistance
25.3
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
1.1
°C/W
RθJB
Junction-to-board thermal resistance
8.2
°C/W
ψJT
Junction-to-top characterization parameter
0.1
°C/W
ψJB
Junction-to-board characterization parameter
8.2
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
n/a
°C/W
(1)
10
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics - DC Specifications
Typical values at TA = +25°C, VA19 = 1.9V, VA11 = 1.1V, VD11 = 1.1V, default full-scale voltage (FS_RANGE_A =
FS_RANGE_B = 0xA000), input signal applied to INA+/– in single channel modes, fIN = 248 MHz, fCLK = maximum rated clock
frequency, filtered 1-Vpp sine-wave clock, background calibration, unless otherwise noted. Minimum and maximum values are
at nominal supply voltages and over operating free-air temperature range provided in Recommended Operating Conditions.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DC ACCURACY
Resolution
12
bits
DNL
Differential nonlinearity
Resolution with no missing codes
±0.3
LSB
INL
Integral nonlinearity
±2.5
LSB
VOFF
Offset Error
Default full-scale voltage, OS_CAL disabled
±0.6
mV
VOFF_ADJ
Input offset voltage
adjustment range
Available offset correction range (see OS_CAL or
OADJ_x_INx)
±55
mV
VOFF_DRI
Offset Drift
Foreground calibration at nominal temperature only
23
µV/°C
Foreground calibration at each temperature
0
µV/°C
FT
VIN_FSR
Analog differential input full
scale range
Default full-scale voltage (FS_RANGE_A =
FS_RANGE_B = 0xA000)
750
800
Maximum full-scale voltage (FS_RANGE_A =
FS_RANGE_B = 0xFFFF)
1000
1040
Minimum full-scale voltage (FS_RANGE_A =
FS_RANGE_B = 0x2000)
VIN_FSR_
DRIFT
VIN_FSR_
MATCH
Analog differential input full
scale range drift
Analog differential input full
scale range matching
480
850
mVPP
mVPP
500
mVPP
Default FS_RANGE_A and FS_RANGE_B setting,
foreground calibration at nominal temperature only,
inputs driven by 50-Ω source, includes effect of RIN
drift
-0.01
%/°C
Default FS_RANGE_A and FS_RANGE_B setting,
foreground calibration at each temperature, inputs
driven by 50-Ω source, includes effect of RIN drift
0.03
%/°C
Matching between INA+/INA– and INB+/INB–,
default setting, dual channel mode
0.625
%
RIN
Single-ended input resistance
Each input terminal is terminated to AGND
to AGND
RIN_TEMP
Input termination linear temperature coefficient
48
50
52
Ω
17.6
mΩ/°C
Single channel mode at DC
0.4
pF
Dual channel mode at DC
0.4
pF
Forced forward current of 100 µA. Offset voltage
(approx. 0.792 V at 0°C) varies with process and
must be measured for each part. Offset
measurement should be done with the device
unpowered or with the PD pin asserted to minimize
device self-heating. PD pin should be asserted only
long enough to take the offset measurement.
-1.6
mV/°C
IL ≤ 100 µA
1.1
V
IL ≤ 100 µA
-64
µV/°C
Differential termination with DEVCLK_LVPECL_EN =
0, SYSREF_LVPECL_EN = 0 and
TMSTP_LVPECL_EN = 0
110
Ω
Single ended termination to GND (per pin) with
DEVCLK_LVPECL_EN = 0, SYSREF_LVPECL_EN
= 0 and TMSTP_LVPECL_EN = 0
55
Ω
CO
CIN
Single-ended input
capacitance
TEMPERATURE DIODE CHARACTERISTICS (TDIODE+, TDIODE–)
ΔVBE
Temperature diode voltage
slope
BANDGAP VOLTAGE OUTPUT (BG)
VBG
Reference output voltage
VBG_DRIF Reference output
temperature drift
T
CLOCK INPUTS (CLK+, CLK–, SYSREF+, SYSREF–, TMSTP+, TMSTP–)
ZT
Internal termination
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ADVANCE INFORMATION
ANALOG INPUTS (INA+, INA–, INB+, INB–)
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SLVSD97 – MAY 2017
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Electrical Characteristics - DC Specifications (continued)
Typical values at TA = +25°C, VA19 = 1.9V, VA11 = 1.1V, VD11 = 1.1V, default full-scale voltage (FS_RANGE_A =
FS_RANGE_B = 0xA000), input signal applied to INA+/– in single channel modes, fIN = 248 MHz, fCLK = maximum rated clock
frequency, filtered 1-Vpp sine-wave clock, background calibration, unless otherwise noted. Minimum and maximum values are
at nominal supply voltages and over operating free-air temperature range provided in Recommended Operating Conditions.
PARAMETER
VCM
Input common mode voltage,
self-biased
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Self-biasing common mode voltage for CLK+/– when
AC coupled (DEVCLK_LVPECL_EN must be set to
0)
0.26
V
Self-biasing common mode voltage for SYSREF+/–
when AC coupled (SYSREF_LVPECL_EN must be
set to 0) and with receiver enabled
(SYSREF_RECV_EN = 1).
0.29
V
Self-biasing common mode voltage for SYSREF+/–
when AC coupled (SYSREF_LVPECL_EN must be
set to 0) and with receiver disabled
(SYSREF_RECV_EN = 0).
VA11
V
ADVANCE INFORMATION
CL_DIFF
Differential input capacitance
Between positive and negative differential input pins
0.1
pF
CL_SE
Single-ended input
capacitance
Each input to ground
0.5
pF
SERDES OUTPUTS (DA0+/DA0–...DA7+/DA7–, DB0+/DB0–...DB7+/DB7–)
VOD
Differential output voltage,
peak-to-peak
100-Ω load
VCM
Output common mode
voltage
AC coupled
ZDIFF
Differential output impedance
580
600
620
mVPPDIFF
VD11/2
V
100
Ω
CMOS INTERFACE: SCLK, SDI, SDO, SCS, PD, NCOA0, NCOA1, NCOB0, NCOB1, CALSTAT, CALTRIG, ORA0, ORA1, ORB0, ORB1,
SYNCSE
IIH
High level input current
–40
40
µA
IIL
Low level input current
–40
40
µA
CI
Input capacitance
VOH
High level output voltage
ILOAD = –400 µA
VOL
Low level output voltage
ILOAD = 400 µA
2
pF
1.65
V
150
mV
6.6 Electrical Characteristics - Power Consumption
Typical values at TA = +25°C, VA19 = 1.9V, VA11 = 1.1V, VD11 = 1.1V, default full-scale voltage (FS_RANGE_A =
FS_RANGE_B = 0xA000), input signal applied to INA+/– in single channel modes, fIN = 248 MHz, fCLK = maximum rated clock
frequency, filtered 1-Vpp sine-wave clock, background calibration, unless otherwise noted. Minimum and maximum values are
at nominal supply voltages and over operating free-air temperature range provided in Recommended Operating Conditions.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IVA19
1.9-V analog supply current
IVA11
1.1-V analog supply current
IVD11
1.1-V digital supply current
PDIS
Power dissipation
3.0
IVA19
1.9-V analog supply current
875
950
mA
IVA11
1.1-V analog supply current
515
600
mA
IVD11
1.1-V digital supply current
615
750
mA
PDIS
Power dissipation
2.9
3.5
W
IVA19
1.9-V analog supply current
IVA11
1.1-V analog supply current
IVD11
1.1-V digital supply current
PDIS
Power dissipation
12
Power mode 1: Single channel
mode, JMODE 1 (16 lanes, DDC
bypassed), foreground calibration
Power mode 2: Single channel
mode, JMODE 0 (8 lanes, DDC
bypassed), foreground calibration
Power mode 3: Single channel
mode, JMODE 1 (16 lanes, DDC
bypassed), background calibration
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897
mA
491
mA
640
mA
W
1181
mA
595
mA
653
mA
3.6
W
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Electrical Characteristics - Power Consumption (continued)
Typical values at TA = +25°C, VA19 = 1.9V, VA11 = 1.1V, VD11 = 1.1V, default full-scale voltage (FS_RANGE_A =
FS_RANGE_B = 0xA000), input signal applied to INA+/– in single channel modes, fIN = 248 MHz, fCLK = maximum rated clock
frequency, filtered 1-Vpp sine-wave clock, background calibration, unless otherwise noted. Minimum and maximum values are
at nominal supply voltages and over operating free-air temperature range provided in Recommended Operating Conditions.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
IVA19
1.9-V analog supply current
IVA11
1.1-V analog supply current
IVD11
1.1-V digital supply current
PDIS
Power dissipation
3.8
W
IVA19
1.9-V analog supply current
964
mA
IVA11
1.1-V analog supply current
493
mA
IVD11
1.1-V digital supply current
802
mA
PDIS
Power dissipation
3.3
W
Power mode 4: Dual channel mode,
JMODE 3 (16 lanes, DDC
bypassed), background calibration
mA
594
mA
636
mA
ADVANCE INFORMATION
Power mode 5: Dual channel mode,
JMODE 11 (8 lanes, 4x decimation),
foreground calibration
1260
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6.7 Electrical Characteristics - AC Specifications
Typical values at TA = +25°C, VA19 = 1.9V, VA11 = 1.1V, VD11 = 1.1V, default full-scale voltage (FS_RANGE_A =
FS_RANGE_B = 0xA000), input signal applied to INA+/– in single channel modes, fIN = 248 MHz, fCLK = maximum rated clock
frequency, filtered 1-Vpp sine-wave clock, background calibration, unless otherwise noted. Minimum and maximum values are
at nominal supply voltages and over operating free-air temperature range provided in Recommended Operating Conditions.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ANALOG INPUTS (INA+, INA–, INB+, INB–)
Analog full-power input bandwidth
(–3 dB) (1)
BW
XTALK
Channel-to-channel Crosstalk
ADVANCE INFORMATION
Dual channel mode, foreground
calibration
8.1
Single channel mode, foreground
calibration
7.9
Dual channel mode, background
calibration
8.1
Single channel mode, background
calibration
7.9
Dual channel mode, aggressor =
400 MHz, – 1 dBFS
–93
Dual channel mode, aggressor = 3
GHz, – 1 dBFS
–70
Dual channel mode, aggressor = 6
GHz, – 1 dBFS
–63
GHz
dB
DYNAMIC AC CHARACTERISTICS - DUAL CHANNEL MODE
CER
Code error rate
NOISEDC
DC input noise standard deviation
NSD
NF
Noise spectral density, no input
signal, excludes fixed interleaving
spur (Fs/2 spur)
Noise figure, no input, ZS = 100 Ω
10–18
errors/sam
ple
No input, foreground calibration,
excludes DC offset, includes fixed
interleaving spur (Fs/2 spur)
2
LSB
Maximum full-scale voltage
(FS_RANGE_A = FS_RANGE_B =
0xFFFF) setting, foreground
calibration
-151.8
Default full-scale voltage
(FS_RANGE_A = FS_RANGE_B =
0xA000) setting, foreground
calibration
-150.2
Maximum full-scale voltage
(FS_RANGE_A = 0xFFFF) setting,
foreground calibration
23.5
Default full-scale voltage
(FS_RANGE_A = 0xA000) setting,
foreground calibration
22.8
fIN = 347 MHz, AIN = –1 dBFS
56.6
fIN = 347 MHz, AIN = –1 dBFS,
maximum FS_RANGE_A and
FS_RANGE_B setting, foreground
calibration
57.6
dBFS/Hz
dB
fIN = 997 MHz, AIN = –1 dBFS
SNR
(1)
14
Signal to noise ratio, large signal,
excluding DC, HD2, HD3 and
interleaving spurs
fIN = 2482 MHz, AIN = –1 dBFS
56.3
52
55.2
fIN = 2482 MHz, AIN = –1 dBFS,
maximum FS_RANGE_A and
FS_RANGE_B setting, foreground
calibration
56.1
fIN = 4997 MHz, AIN = –1 dBFS
52.6
fIN = 6397 MHz, AIN = –1 dBFS
51.3
fIN = 8197 MHz, AIN = –1 dBFS
49.8
dBFS
Useable bandwidth may exceed the -3-dB analog bandwidth.
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Electrical Characteristics - AC Specifications (continued)
Typical values at TA = +25°C, VA19 = 1.9V, VA11 = 1.1V, VD11 = 1.1V, default full-scale voltage (FS_RANGE_A =
FS_RANGE_B = 0xA000), input signal applied to INA+/– in single channel modes, fIN = 248 MHz, fCLK = maximum rated clock
frequency, filtered 1-Vpp sine-wave clock, background calibration, unless otherwise noted. Minimum and maximum values are
at nominal supply voltages and over operating free-air temperature range provided in Recommended Operating Conditions.
SNR
Signal to noise ratio, small signal,
excluding DC, HD2, HD3 and
interleaving spurs
TEST CONDITIONS
MIN
57.4
fIN = 997 MHz, AIN = –16 dBFS
57.5
fIN = 2482 MHz, AIN = –16 dBFS
57.4
fIN = 4997 MHz, AIN = –16 dBFS
57.1
fIN = 6397 MHz, AIN = –16 dBFS
57.3
fIN = 8197 MHz, AIN = –16 dBFS
56.9
fIN = 347 MHz, AIN = –1 dBFS
56.0
fIN = 997 MHz, AIN = –1 dBFS
SINAD
Signal to noise and distortion ratio,
large signal, excluding DC and FS/2
fixed spurs
fIN = 2482 MHz, AIN = –1 dBFS
ENOB
SFDR
SFDR
FS/2
Spurious free dynamic range, large
signal, excluding DC and FS/2 fixed
spurs
Spurious free dynamic range, small
signal, excluding DC and FS/2 fixed
spurs
FS/2 fixed interleaving spur,
independent of input signal
UNIT
dBFS
54.6
fIN = 4997 MHz, AIN = –1 dBFS
50.3
fIN = 6397 MHz, AIN = –1 dBFS
48.9
fIN = 8197 MHz, AIN = –1 dBFS
47.4
fIN = 347 MHz, AIN = –1 dBFS
9.0
fIN = 2482 MHz, AIN = –1 dBFS
MAX
55.7
51
fIN = 997 MHz, AIN = –1 dBFS
Effective number of bits, large
signal, excluding DC and FS/2 fixed
spurs
TYP
fIN = 347 MHz, AIN = –16 dBFS
dBFS
9.0
8.2
8.8
fIN = 4997 MHz, AIN = –1 dBFS
8.1
fIN = 6397 MHz, AIN = –1 dBFS
7.8
fIN = 8197 MHz, AIN = –1 dBFS
7.6
fIN = 347 MHz, AIN = –1 dBFS
–67
fIN = 347 MHz, AIN = –1 dBFS,
maximum FS_RANGE_A and
FS_RANGE_B setting, foreground
calibration
–67
fIN = 997 MHz, AIN = –1 dBFS
–69
fIN = 2482 MHz, AIN = –1 dBFS
–66
fIN = 2482 MHz, AIN = –1 dBFS,
maximum FS_RANGE_A and
FS_RANGE_B setting, foreground
calibration
–63
fIN = 4997 MHz, AIN = –1 dBFS
–56
fIN = 6397 MHz, AIN = –1 dBFS
–55
fIN = 8197 MHz, AIN = –1 dBFS
–52
fIN = 347 MHz, AIN = –16 dBFS
–73
fIN = 997 MHz, AIN = –16 dBFS
–72
fIN = 2482 MHz, AIN = –16 dBFS
–72
fIN = 4997 MHz, AIN = –16 dBFS
–72
fIN = 6397 MHz, AIN = –16 dBFS
–72
fIN = 8197 MHz, AIN = –16 dBFS
–72
No input
–75
bits
–60
dBFS
dBFS
–55
dBFS
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PARAMETER
15
ADC12DJ3200
SLVSD97 – MAY 2017
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Electrical Characteristics - AC Specifications (continued)
Typical values at TA = +25°C, VA19 = 1.9V, VA11 = 1.1V, VD11 = 1.1V, default full-scale voltage (FS_RANGE_A =
FS_RANGE_B = 0xA000), input signal applied to INA+/– in single channel modes, fIN = 248 MHz, fCLK = maximum rated clock
frequency, filtered 1-Vpp sine-wave clock, background calibration, unless otherwise noted. Minimum and maximum values are
at nominal supply voltages and over operating free-air temperature range provided in Recommended Operating Conditions.
PARAMETER
2nd order harmonic
HD2
ADVANCE INFORMATION
3rd order harmonic
HD3
FS/2-FIN
SPUR
16
FS/2-FIN interleaving spur, signal
dependent
Worst harmonic 4th order or higher
TEST CONDITIONS
MIN
TYP
fIN = 347 MHz, AIN = –1 dBFS
–73
fIN = 347 MHz, AIN = –1 dBFS,
maximum FS_RANGE_A and
FS_RANGE_B setting, foreground
calibration
–72
fIN = 997 MHz, AIN = –1 dBFS
–72
fIN = 2482 MHz, AIN = –1 dBFS
–67
fIN = 2482 MHz, AIN = –1 dBFS,
maximum FS_RANGE_A and
FS_RANGE_B setting, foreground
calibration
–66
fIN = 4997 MHz, AIN = –1 dBFS
–58
fIN = 6397 MHz, AIN = –1 dBFS
–57
fIN = 8197 MHz, AIN = –1 dBFS
–58
fIN = 347 MHz, AIN = –1 dBFS
–70
fIN = 347 MHz, AIN = –1 dBFS,
maximum FS_RANGE_A and
FS_RANGE_B setting, foreground
calibration
–68
fIN = 997 MHz, AIN = –1 dBFS
–72
fIN = 2482 MHz, AIN = –1 dBFS
–69
fIN = 2482 MHz, AIN = –1 dBFS,
maximum FS_RANGE_A and
FS_RANGE_B setting, foreground
calibration
–63
fIN = 4997 MHz, AIN = –1 dBFS
–57
fIN = 6397 MHz, AIN = –1 dBFS
–55
fIN = 8197 MHz, AIN = –1 dBFS
–52
fIN = 347 MHz, AIN = –1 dBFS
–69
fIN = 997 MHz, AIN = –1 dBFS
–70
fIN = 2482 MHz, AIN = –1 dBFS
–70
fIN = 4997 MHz, AIN = –1 dBFS
–67
fIN = 6397 MHz, AIN = –1 dBFS
–63
fIN = 8197 MHz, AIN = –1 dBFS
–63
fIN = 347 MHz, AIN = –1 dBFS
–72
fIN = 997 MHz, AIN = –1 dBFS
–72
fIN = 2482 MHz, AIN = –1 dBFS
–73
fIN = 4997 MHz, AIN = –1 dBFS
–70
fIN = 6397 MHz, AIN = –1 dBFS
–69
fIN = 8197 MHz, AIN = –1 dBFS
–67
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MAX
–60
–60
–60
–65
UNIT
dBFS
dBFS
dBFS
dBFS
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Electrical Characteristics - AC Specifications (continued)
Typical values at TA = +25°C, VA19 = 1.9V, VA11 = 1.1V, VD11 = 1.1V, default full-scale voltage (FS_RANGE_A =
FS_RANGE_B = 0xA000), input signal applied to INA+/– in single channel modes, fIN = 248 MHz, fCLK = maximum rated clock
frequency, filtered 1-Vpp sine-wave clock, background calibration, unless otherwise noted. Minimum and maximum values are
at nominal supply voltages and over operating free-air temperature range provided in Recommended Operating Conditions.
PARAMETER
3 order intermodulation
MIN
TYP
–81
fIN = 997 MHz ± 5 MHz,
AIN = –7 dBFS per tone
–78
fIN = 2482 MHz ± 5 MHz,
AIN = –7 dBFS per tone
–73
fIN = 4997 MHz ± 5 MHz,
AIN = –7 dBFS per tone
–65
fIN = 6397 MHz ± 5 MHz,
AIN = –7 dBFS per tone
–56
fIN = 8197 MHz ± 5 MHz,
AIN = –7 dBFS per tone
–46
MAX
UNIT
dBFS
ADVANCE INFORMATION
IMD3
rd
TEST CONDITIONS
fIN = 347 MHz ± 5 MHz,
AIN = –7 dBFS per tone
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Electrical Characteristics - AC Specifications (continued)
Typical values at TA = +25°C, VA19 = 1.9V, VA11 = 1.1V, VD11 = 1.1V, default full-scale voltage (FS_RANGE_A =
FS_RANGE_B = 0xA000), input signal applied to INA+/– in single channel modes, fIN = 248 MHz, fCLK = maximum rated clock
frequency, filtered 1-Vpp sine-wave clock, background calibration, unless otherwise noted. Minimum and maximum values are
at nominal supply voltages and over operating free-air temperature range provided in Recommended Operating Conditions.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DYNAMIC AC CHARACTERISTICS - SINGLE CHANNEL MODE
CER
Code error rate
NOISEDC
DC input noise standard deviation
NSD
ADVANCE INFORMATION
NF
Noise spectral density, no input
signal, excludes fixed interleaving
spurs (Fs/2 and Fs/4 spur)
Noise figure, no input, ZS = 100 Ω
10–18
errors/sam
ple
No input, foreground calibration,
excludes DC offset, includes fixed
interleaving spurs (Fs/2 and Fs/4
spurs)
3.5
LSB
Maximum full-scale voltage
(FS_RANGE_A = 0xFFFF) setting,
foreground calibration
-154.6
Default full-scale voltage
(FS_RANGE_A = 0xA000) setting,
foreground calibration
-153.1
Maximum full-scale voltage
(FS_RANGE_A = 0xFFFF) setting,
foreground calibration
20.7
Default full-scale voltage
(FS_RANGE_A = 0xA000) setting,
foreground calibration
19.9
fIN = 347 MHz, AIN = –1 dBFS
56.6
fIN = 347 MHz, AIN = –1 dBFS,
maximum FS_RANGE_A setting,
foreground calibration
57.5
dBFS/Hz
dB
fIN = 997 MHz, AIN = –1 dBFS
SNR
SNR
SINAD
ENOB
18
Signal to noise ratio, large signal,
excluding DC, HD2, HD3 and
interleaving spurs
Signal to noise ratio, small signal,
excluding DC, HD2, HD3 and
interleaving spurs
Signal to noise and distortion ratio,
large signal, excluding DC and FS/2
fixed spurs
Effective number of bits, large
signal, excluding DC and FS/2 fixed
spurs
fIN = 2482 MHz, AIN = –1 dBFS
56.3
52
55.3
fIN = 2482 MHz, AIN = –1 dBFS,
maximum FS_RANGE_A setting,
foreground calibration
56.1
fIN = 4997 MHz, AIN = –1 dBFS
53.0
fIN = 6397 MHz, AIN = –1 dBFS
51.6
fIN = 8197 MHz, AIN = –1 dBFS
50.0
fIN = 347 MHz, AIN = –16 dBFS
57.4
fIN = 997 MHz, AIN = –16 dBFS
57.6
fIN = 2482 MHz, AIN = –16 dBFS
57.4
fIN = 4997 MHz, AIN = –16 dBFS
57.3
fIN = 6397 MHz, AIN = –16 dBFS
57.4
fIN = 8197 MHz, AIN = –16 dBFS
57.0
fIN = 347 MHz, AIN = –1 dBFS
52.7
fIN = 997 MHz, AIN = –1 dBFS
52.4
fIN = 2482 MHz, AIN = –1 dBFS
48
52.1
fIN = 4997 MHz, AIN = –1 dBFS
47.5
fIN = 6397 MHz, AIN = –1 dBFS
46.6
fIN = 8197 MHz, AIN = –1 dBFS
47.7
fIN = 347 MHz, AIN = –1 dBFS
8.6
fIN = 997 MHz, AIN = –1 dBFS
8.5
fIN = 2482 MHz, AIN = –1 dBFS
7.7
8.4
fIN = 4997 MHz, AIN = –1 dBFS
7.7
fIN = 6397 MHz, AIN = –1 dBFS
7.5
fIN = 8197 MHz, AIN = –1 dBFS
7.6
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dBFS
dBFS
dBFS
dBFS
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Electrical Characteristics - AC Specifications (continued)
Typical values at TA = +25°C, VA19 = 1.9V, VA11 = 1.1V, VD11 = 1.1V, default full-scale voltage (FS_RANGE_A =
FS_RANGE_B = 0xA000), input signal applied to INA+/– in single channel modes, fIN = 248 MHz, fCLK = maximum rated clock
frequency, filtered 1-Vpp sine-wave clock, background calibration, unless otherwise noted. Minimum and maximum values are
at nominal supply voltages and over operating free-air temperature range provided in Recommended Operating Conditions.
SFDR
SFDR
Spurious free dynamic range, large
signal, excluding DC, FS/4 and FS/2
fixed spurs
Spurious free dynamic range, large
signal, excluding DC, FS/4 and FS/2
fixed spurs
TEST CONDITIONS
MIN
TYP
fIN = 347 MHz, AIN = –1 dBFS
–67
fIN = 347 MHz, AIN = –1 dBFS,
maximum FS_RANGE_A setting,
foreground calibration
–64
fIN = 997 MHz, AIN = –1 dBFS
–63
fIN = 2482 MHz, AIN = –1 dBFS
–58
fIN = 2482 MHz, AIN = –1 dBFS,
maximum FS_RANGE_A setting,
foreground calibration
–55
fIN = 4997 MHz, AIN = –1 dBFS
–51
fIN = 6397 MHz, AIN = –1 dBFS
–50
fIN = 8197 MHz, AIN = –1 dBFS
–48
fIN = 347 MHz, AIN = –16 dBFS
–75
fIN = 997 MHz, AIN = –16 dBFS
–73
fIN = 2482 MHz, AIN = –16 dBFS
–72
fIN = 4997 MHz, AIN = –16 dBFS
–66
fIN = 6397 MHz, AIN = –16 dBFS
–65
fIN = 8197 MHz, AIN = –16 dBFS
–63
–56
FS/2
FS/2 fixed interleaving spur,
independent of input signal
No input, OS_CAL disabled. Spur
can be improved by running
OS_CAL.
FS/4
FS/4 fixed interleaving spur,
independent of input signal
No input
–65
fIN = 347 MHz, AIN = –1 dBFS
–73
fIN = 347 MHz, AIN = –1 dBFS,
maximum FS_RANGE_A setting,
foreground calibration
–76
fIN = 997 MHz, AIN = –1 dBFS
–74
fIN = 2482 MHz, AIN = –1 dBFS
–68
fIN = 2482 MHz, AIN = –1 dBFS,
maximum FS_RANGE_A setting,
foreground calibration
–72
fIN = 4997 MHz, AIN = –1 dBFS
–62
fIN = 6397 MHz, AIN = –1 dBFS
–62
fIN = 8197 MHz, AIN = –1 dBFS
–61
fIN = 347 MHz, AIN = –1 dBFS
–70
fIN = 347 MHz, AIN = –1 dBFS,
maximum FS_RANGE_A setting,
foreground calibration
–68
fIN = 997 MHz, AIN = –1 dBFS
–68
fIN = 2482 MHz, AIN = –1 dBFS
–69
fIN = 2482 MHz, AIN = –1 dBFS,
maximum FS_RANGE_A setting,
foreground calibration
–64
fIN = 4997 MHz, AIN = –1 dBFS
–59
fIN = 6397 MHz, AIN = –1 dBFS
–58
fIN = 8197 MHz, AIN = –1 dBFS
–55
HD2
HD3
2nd order harmonic
3rd order harmonic
MAX
–50
UNIT
dBFS
dBFS
dBFS
–55
–60
–60
dBFS
dBFS
dBFS
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ADVANCE INFORMATION
PARAMETER
19
ADC12DJ3200
SLVSD97 – MAY 2017
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Electrical Characteristics - AC Specifications (continued)
Typical values at TA = +25°C, VA19 = 1.9V, VA11 = 1.1V, VD11 = 1.1V, default full-scale voltage (FS_RANGE_A =
FS_RANGE_B = 0xA000), input signal applied to INA+/– in single channel modes, fIN = 248 MHz, fCLK = maximum rated clock
frequency, filtered 1-Vpp sine-wave clock, background calibration, unless otherwise noted. Minimum and maximum values are
at nominal supply voltages and over operating free-air temperature range provided in Recommended Operating Conditions.
PARAMETER
FS/2-FIN
FS/4±FIN
ADVANCE INFORMATION
SPUR
IMD3
20
FS/2-FIN interleaving spur, signal
dependent
FS/4±FIN interleaving spurs, signal
dependent
Worst harmonic 4th order or higher
rd
3 order intermodulation
TEST CONDITIONS
MIN
TYP
fIN = 347 MHz, AIN = –1 dBFS
–68
fIN = 997 MHz, AIN = –1 dBFS
–63
fIN = 2482 MHz, AIN = –1 dBFS
–58
fIN = 4997 MHz, AIN = –1 dBFS
–51
fIN = 6397 MHz, AIN = –1 dBFS
–50
fIN = 8197 MHz, AIN = –1 dBFS
–48
fIN = 347 MHz, AIN = –1 dBFS
–74
fIN = 997 MHz, AIN = –1 dBFS
–69
fIN = 2482 MHz, AIN = –1 dBFS
–70
fIN = 4997 MHz, AIN = –1 dBFS
–66
fIN = 6397 MHz, AIN = –1 dBFS
–63
fIN = 8197 MHz, AIN = –1 dBFS
–61
fIN = 347 MHz, AIN = –1 dBFS
–73
fIN = 997 MHz, AIN = –1 dBFS
–73
fIN = 2482 MHz, AIN = –1 dBFS
–75
fIN = 4997 MHz, AIN = –1 dBFS
–69
fIN = 6397 MHz, AIN = –1 dBFS
–69
fIN = 8197 MHz, AIN = –1 dBFS
–63
fIN = 347 MHz ± 5 MHz,
AIN = –7 dBFS per tone
–80
fIN = 997 MHz ± 5 MHz,
AIN = –7 dBFS per tone
–75
fIN = 2482 MHz ± 5 MHz,
AIN = –7 dBFS per tone
–72
fIN = 4997 MHz ± 5 MHz,
AIN = –7 dBFS per tone
–63
fIN = 6397 MHz ± 5 MHz,
AIN = –7 dBFS per tone
–65
fIN = 8197 MHz ± 5 MHz,
AIN = –7 dBFS per tone
–50
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MAX
–50
–60
–65
UNIT
dBFS
dBFS
dBFS
dBFS
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6.8 Timing Requirements
MIN
NOM
MAX
UNIT
3200
MHz
DEVICE (SAMPLING) CLOCK (CLK+, CLK–)
Input clock frequency (CLK+, CLK–), both single channel and dual channel
modes (1)
fCLK
800
SYSREF (SYSREF+, SYSREF–)
t(PH_SYS)
SYSREF+/– assertion duration after SYSREF+/– rising edge event
4
ns
t(PL_SYS)
SYSREF+/– deassertion duration after SYSREF+/– falling edge event
1
ns
JESD204B SYNC TIMING (SYNCSE OR TMSTP+/–)
)
21
9
JMODE = 0, 2, 4, 6,
10, 13 or 15
tSU(SYNCS
E)
t(SYNCSE)
tCLK
cycles
17
–2
Minimum setup time from de-assertion of JESD204B
SYNC signal (SYNCSE if SYNC_SEL = 0 or TMSTP+/– if
JMODE = 1, 3, 5, 7, 9,
SYNC_SEL = 1) to multi-frame boundary (SYSREF rising
11, 14 or 16
edge captured high) for NCO synchronization
JMODE = 12, 17 or 18
tCLK
cycles
2
10
SYNCSE minimum assertion time to trigger link resynchronization
4
Frames
15.625
MHz
SERIAL PROGRAMMING INTERFACE (SCLK, SDI, SCS)
fCLK(SCLK) Maximum serial clock frequency
t(PH)
Minimum serial clock high value pulse width
32
ns
t(PL)
Minimum serial clock low value pulse width
32
ns
tSU(SCS)
Minimum setup time from SCS to rising edge of SCLK
30
ns
tH(SCS)
Minimum hold time from rising edge of SCLK to SCS
3
ns
tSU(SDI)
Minimum setup time from SDI to rising edge of SCLK
30
ns
tH(SDI)
Minimum hold time from rising edge of SCLK to SDI
3
ns
(1)
Unless functionally limited to a smaller range in Table 16 based on programmed JMODE.
6.9 Switching Characteristics
Typical values at TA = +25°C, VA19 = 1.9V, VA11 = 1.1V, VD11 = 1.1V, default full-scale voltage (FS_RANGE_A =
FS_RANGE_B = 0xA000), input signal applied to INA+/– in single channel modes, fIN = 248 MHz, fCLK = maximum rated clock
frequency, filtered 1-Vpp sine-wave clock, background calibration, unless otherwise noted. Minimum and maximum values are
at nominal supply voltages and over operating free-air temperature range provided in Recommended Operating Conditions.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DEVICE (SAMPLING) CLOCK (CLK+, CLK–)
From CLK+/- rising edge (dual
channel mode) or rising and falling
edge (single channel mode) to
sampling instant with
TAD_COARSE = 0x00, TAD_FINE
= 0x00 and TAD_INV = 0
tAD
Sampling (aperture) delay
tTAD(MAX)
Maximum TAD (aperture delay) adjustment range, not including clock
inversion (TAD_INV = 0, TAD_COARSE = 0xFF, TAD_FINE = 0xFF)
tTAD(STEP)
TAD (aperture delay) adjustment step
size
tAJ
Aperture jitter, rms
TAD_COARSE delay step size
360
ps
293
ps
1.13
ps
TAD_FINE delay step size
19
fs
Minimum TAD (aperture delay)
setting (TAD_COARSE = 0x00,
TAD_INV = 0)
50
fs
70 (1)
fs
Maximum TAD (aperture delay)
setting (TAD_COARSE = 0xFF)
excluding TAD_INV (TAD_INV = 0)
SERIAL DATA OUTPUTS (DA0+...DA7+, DA0–...DA7–, DB0+...DB7+, DB0–...DB7–)
(1)
tAJ increases due to additional attenuation on internal clock path.
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ADVANCE INFORMATION
tH(SYNCSE
JMODE = 0, 2, 4, 6,
Minimum hold time from multi-frame boundary (SYSREF 10, 13 or 15
rising edge captured high) to de-assertion of JESD204B
JMODE = 1, 3, 5, 7, 9,
SYNC signal (SYNCSE if SYNC_SEL = 0 or TMSTP+/– if
11, 14 or 16
SYNC_SEL = 1) for NCO synchronization
JMODE = 12, 17 or 18
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Switching Characteristics (continued)
Typical values at TA = +25°C, VA19 = 1.9V, VA11 = 1.1V, VD11 = 1.1V, default full-scale voltage (FS_RANGE_A =
FS_RANGE_B = 0xA000), input signal applied to INA+/– in single channel modes, fIN = 248 MHz, fCLK = maximum rated clock
frequency, filtered 1-Vpp sine-wave clock, background calibration, unless otherwise noted. Minimum and maximum values are
at nominal supply voltages and over operating free-air temperature range provided in Recommended Operating Conditions.
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
1
TYP
12.8
Gbps
78.125
1000
ps
ADVANCE INFORMATION
fSERDES
Serialized output bit rate
UI
Serialized output unit interval
tTLH
Low-to-high transition time
(differential)
10% to 90%, 12.8 Gbps, SER_PE
= 0x04
37
ps
tTHL
High-to-low transition time
(differential)
10% to 90%, 12.8 Gbps, SER_PE
= 0x04
37
ps
DDJ
Data dependent jitter, peak-to-peak
12.8 Gbps serial rate using PRBS7 test pattern, SER_PE = 0x04
8
ps
RJ
Random jitter, RMS
12.8 Gbps serial rate using PRBS7 test pattern, SER_PE = 0x04
1.9
ps
Total jitter, peak-to-peak
12.8 Gbps serial rate using PRBS7 test pattern, with gaussian
portion defined with respect to a
BER=1e-15 (Q=7.94), SER_PE =
0x04
37
ps
JMODE = 0
-8.5
JMODE = 1
-20.5
TJ
ADC CORE LATENCY
tADC
Deterministic delay from the CLK+/–
edge that samples the reference
sample to the CLK+/– edge that
samples SYSREF going high (2)
JMODE = 2
-9
JMODE = 3
-21
JMODE = 4
-4.5
JMODE = 5
-24.5
JMODE = 6
-5
JMODE = 7
-25
JMODE = 9
60
JMODE = 10
140
JMODE = 11
136
JMODE = 12
120
JMODE = 13
232
JMODE = 14
232
JMODE = 15
446
JMODE = 16
430
JMODE = 17
-48.5
JMODE = 18
-49
tCLK cycles
JESD204B AND SERIALIZER LATENCY
(2)
22
tADC is an exact, unrounded, deterministic delay. The delay can be negative if the reference sample is sampled after the SYSREF high
capture point, in which case the total latency is smaller than the delay given by tTX.
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Switching Characteristics (continued)
Typical values at TA = +25°C, VA19 = 1.9V, VA11 = 1.1V, VD11 = 1.1V, default full-scale voltage (FS_RANGE_A =
FS_RANGE_B = 0xA000), input signal applied to INA+/– in single channel modes, fIN = 248 MHz, fCLK = maximum rated clock
frequency, filtered 1-Vpp sine-wave clock, background calibration, unless otherwise noted. Minimum and maximum values are
at nominal supply voltages and over operating free-air temperature range provided in Recommended Operating Conditions.
TEST CONDITIONS
Delay from the CLK+/– rising edge
that samples SYSREF high to the first
bit of the multi-frame on the
JESD204B serial output lane
corresponding to the reference
sample of tADC (3)
tTX
MIN
TYP
MAX
JMODE = 0
72
84
JMODE = 1
119
132
JMODE = 2
72
84
JMODE = 3
119
132
JMODE = 4
67
80
JMODE = 5
106
119
JMODE = 6
67
80
JMODE = 7
106
119
JMODE = 9
106
119
JMODE = 10
67
80
JMODE = 11
106
119
JMODE = 12
213
225
JMODE = 13
67
80
JMODE = 14
106
119
JMODE = 15
67
80
JMODE = 16
106
119
JMODE = 17
195
208
JMODE = 18
195
208
UNIT
tCLK cycles
SERIAL PROGRAMMING INTERFACE (SDO)
t(OZD)
Maximum delay from falling edge of 16th SCLK cycle during read operation
for SDO transition from tri-state to valid data
7
ns
t(ODZ)
Maximum delay from SCS rising edge for SDO transition from valid data to
tri-state
7
ns
t(OD)
Maximum delay from falling edge of 16th SCLK cycle during read operation
to SDO valid
12
ns
(3)
The values given for tTX include deterministic and non-deterministic delays. Over process, temperature, and voltage, the delay will vary.
JESD204B accounts for these variations when operating in subclass-1 mode in order to achieve deterministic latency. Proper receiver
RBD value must be chosen such that the elastic buffer release point does not occur within the invalid region of the local multi-frame
clock (LMFC) cycle.
S1
S0
tAD
S2
tADC
tCLK
CLK+
CLK±
SYSREF+
SYSREF±
tSU(SYSREF)
tH(SYSREF)
tTX
Start of Multi-Frame
S0
DA0+/±*
S1
S2
* Only serdes lane DA0+/- is shown, but it is representative of all lanes. The number of output lanes used and bit-packing format is dependent on the
programmed JMODE value.
Figure 1. ADC Timing Diagram
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PARAMETER
ADC12DJ3200
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CLK+
CLK±
SYSREF+
SYSREF±
LMFC(1)
(Internal)
One multi-frame
One multi-frame
tH(SYNCSE)
tSU(SYNCSE)
SYNCSE
(SYNC_SEL=0)
TMSTP+/±
(SYNC_SEL=1)
tTX
DA0+/±
Start of ILAS
(2)
/R
(1)
It is assumed that the internal LMFC is aligned with the rising edge of CLK+/- that captures SYSREF+/- high value.
Only serdes lane DA0+/- is shown, but it is representative of all lanes. All lanes will output /R at approximately the same point in time. Number of lanes is
dependent on the programmed JMODE value.
(2)
ADVANCE INFORMATION
Figure 2. SYNCSE and TMSTP+/– Timing Diagram for NCO Synchronization
st
th
1 clock
16
th
clock
24
clock
SCLK
tH(SCS)
t(PH)
tSU(SCS)
t(PL)
tH(SCS)
tSU(SCS)
t(PH) + t(PL) = t(P) = 1 / ¦CLK(SCLK)
SCS
tSU(SDI)
tSU(SDI)
tH(SDI)
SDI
D7
D1
tH(SDI)
D0
Write Command
COMMAND FIELD
t(OD)
SDO
Hi-Z
D7
t(OZD)
D1
Hi-Z
D0
Read Command
t(ODZ)
Figure 3. Serial Interface Timing
24
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7 Detailed Description
7.1 Overview
ADC12DJ3200 is an RF-sampling giga-sample ADC that can directly sample input frequencies from DC to above
10 GHz. In dual channel mode, ADC12DJ3200 can sample up to 3200-MSPS and in single channel mode up to
6400-MSPS. Programmable tradeoffs in channel count (dual channel mode) and Nyquist bandwidth (single
channel mode) allow development of flexible hardware that meets the needs of both high channel count or wide
instantaneous signal bandwidth applications. Full power input bandwidth (-3 dB) of 8.0 GHz, with usable
frequencies exceeding the -3 dB point in both dual and single channel modes, allows direct RF sampling of Lband, S-band, C-band and X-band for frequency agile systems.
ADC12DJ3200 uses a high speed JESD204B output interface with up to 16 serialized lanes and subclass-1
compliance for deterministic latency and multi-device synchronization. The serial output lanes support up to 12.8
Gbps and can be configured to trade-off bit rate and number of lanes. Innovative synchronization features
including noiseless aperture delay (TAD) adjustment and SYSREF windowing simplify system design for phased
array radar and MIMO communications. Optional digital down converters (DDCs) in dual channel mode allow for
reduction in interface rate (real and complex decimation modes) and digital mixing of the signal (complex
decimation modes only).
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Time interleaving is achieved internally through 4 active cores. In dual channel mode, two cores are interleaved
per channel to increase the sample rate to 2x the core sample rate. In single channel mode, all 4 cores are time
interleaved to increase the sample rate to 4x the core sample rate. Either input can be used in single channel
mode, however performance has been optimized for INA+/–. The user provides a clock at 2x the ADC core
sample rate and the generation of the clocks for the interleaved cores is done internally for both single channel
mode and dual channel mode. ADC12DJ3200 also provides foreground and background calibration options to
match the gain and offset between cores to minimize spurious artifacts due to the interleaving.
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7.2 Functional Block Diagrams
NCOA0 NCOA1 NCOB0 NCOB1 CALTRG PD
SCLK
SDI
SDO
SCS\
SPI Registers and
Device Control
DDC Bypass / Single Channel Mode
DDC A
TMSTP+
DA0+
DA0-
NCO Bank A
TMSTPInput
MUX
INA+
ADC A
JESD204B
Link A
N
Mixer
INA-
DA7+
DA7-
Filter
JMODE
DDC Bypass / Single Channel Mode
Overrange
SYNCSE\
DDC B
ADVANCE INFORMATION
DB0+
DB0-
NCO Bank B
INB+
INBInput
MUX
ADC B
JESD204B
Link B
N
Mixer
DB7+
DB7-
Filter
DIGBIND
Aperture
Delay Adjust
JMODE
CLK+
Clock Distribution
and Synchronization
CLK-
SYSREF+
Status
Indicators
SYSREF
Windowing
SYSREF-
TDIODE+
ORA0
ORA1
ORB0
ORB1
CALSTAT
TDIODECopyright © 2016, Texas Instruments Incorporated
Figure 4. ADC12DJ3200 Functional Block Diagram
7.3 Feature Description
7.3.1 Analog Inputs
The analog inputs of ADC12DJ3200 have internal buffers to enable high input bandwidth and isolate sampling
capacitor glitch noise from the input circuit. Analog inputs must be driven differentially since operation with a
single-ended signal results in degraded performance. Both AC coupling and DC coupling of the analog inputs is
supported. The analog inputs are designed for an input common mode voltage (VCMI) of 0 V which is terminated
internally through single-ended 50-Ω resistors to ground (GND) on each input pin. DC-coupled input signals must
have a common mode voltage that meets the device input common mode requirements specified as VCMI in
Recommended Operating Conditions. The 0-V input common mode voltage simplifies the interface to split-supply
fully differential amplifiers and to a variety of transformers and baluns. ADC12DJ3200 includes internal analog
input protection to protect the ADC inputs during over-ranged input conditions (see Analog Input Protection). A
simplified analog input model is shown in Figure 5.
26
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Feature Description (continued)
AGND
50
Analog input
protection
diodes
INA/B+
ADC
50
INA/BInput buffer
Copyright © 2016, Texas Instruments Incorporated
There is no degradation in analog input bandwidth when using single channel mode versus dual channel mode.
In single channel mode it is strongly recommended that INA+/– be used as the input to the ADC since ADC
performance has been optimized for INA+/–. However, either analog input (INA+ and INA– or INB+ and INB–)
can be used. The use of INB+/– will result in degraded performance unless custom trim routines are used to
optimize performance for INB+/– for each part. The desired input can be chosen using SINGLE_INPUT in Input
Mux Control Register (address = 0x060) [reset = 0x01].
NOTE
In single channel mode it is strongly recommended that INA+/– be used as the input to the
ADC for optimized performance.
7.3.1.1 Analog Input Protection
The analog inputs are protected against over-drive conditions by internal clamping diodes that are capable of
sourcing or sinking input currents during over-range conditions, see voltage and current limits in Absolute
Maximum Ratings. The over-range protection is also defined for a peak RF input power in Absolute Maximum
Ratings, which is frequency independent. Operation above the maximum conditions listed in Recommended
Operating Conditions will result in an increase in failure-in-time (FIT) rate, so the system should correct the overdrive condition as quickly as possible. The analog input protection diodes are shown in Figure 5.
7.3.1.2 Full-Scale Voltage (VFS) Adjustment
Input full-scale voltage (VFS) adjustment is available, in fine increments, for each analog input through the
FS_RANGE_A (INA Full Scale Range Adjust Register (address = 0x030-0x031) [reset = 0xA4C4]) register
setting and FS_RANGE_B (INB Full Scale Range Adjust Register (address = 0x032-0x033) [reset = 0xA4C4])
register setting for INA+/– and INB+/–, respectively. The available adjustment range is specified in Electrical
Characteristics - DC Specifications. Larger full-scale voltages improve SNR and noise floor (in dBFS/Hz)
performance, but may degrade harmonic distortion. The full-scale voltage adjustment is useful for matching the
full-scale range of multiple ADCs when developing a multi-converter system or for external interleaving of
multiple ADC12DJ3200 to achieve higher sampling rates.
7.3.1.3 Analog Input Offset Adjust
The input offset voltage for each input can be adjusted through the OADJ_x_INy registers (registers 0x08A and
0x095), where x represents the ADC core (A, B, or C) and y represents the analog input (A or B). The
adjustment range is approximately 28 mV to –28 mV differential.
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Figure 5. ADC12DJ3200 Analog Input Internal Termination
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Feature Description (continued)
7.3.2 ADC Core
ADC12DJ3200 consists of a total of six ADC cores. The cores are interleaved for higher sampling rates and
swapped on-the-fly for calibration as required by the operating mode. This section highlights the theory and key
features of the ADC cores.
7.3.2.1 ADC Theory of Operation
ADVANCE INFORMATION
The differential voltages at the analog inputs are captured by the rising edge of CLK+/– in dual channel mode or
by the rising and falling edges of CLK+/– in single channel mode. After capturing the input signal, the ADC
converts the analog voltage to a digital value by comparing the voltage to the internal reference voltage. If the
voltage on INA– or INB– is higher than the voltage on INA+ or INB+, respectively, then the digital output will be a
negative 2's complement value. If the voltage on INA+ or INB+ is higher than the voltage on INA– or INB–,
respectively, then the digital output will be a positive 2's complement value. The differential voltage at the input
pins can be calculated from the digital output by Equation 1, where Code is the output code in 2's complement
format in decimal (e.g. –2048 to +2047) and VFS is the full-scale input voltage of the ADC as specified in
Recommended Operating Conditions, including any adjustment performed by programming FS_RANGE_A or
FS_RANGE_B.
Code
V IN
V FS
2N
(1)
7.3.2.2 ADC Core Calibration
ADC core calibration is required to optimize analog performance of the ADC cores. Calibration must be repeated
as operating conditions change, namely temperature, in order to maintain optimal performance. The
ADC12DJ3200 family has a built in calibration routine that can be run as a foreground operation or a background
operation. Foreground operation requires ADC downtime, where the ADC is no longer sampling the input signal,
to complete the process. Background calibration can be used to overcome this limitation and allow constant
operation of the ADC. See Calibration Modes for detailed information on each mode.
7.3.2.3 ADC Over-Range Detection
To ensure that system gain management has the quickest-possible response time, a low-latency configurable
over-range function is included. The over-range function works by monitoring the converted 12-bit samples at the
ADC to quickly detect if the ADC is near saturation or already in an over-range condition. The absolute value of
the upper 8 bits of the ADC data are checked against two programmable thresholds, OVR_T0 and OVR_T1.
These thresholds apply to both channel A and channel B in dual channel mode. The following table lists how an
ADC sample is converted to an absolute value for a comparison of the thresholds.
Table 1. Conversion of ADC Sample for Over-Range Comparison
ADC SAMPLE
(OFFSET BINARY)
ADC SAMPLE
(2's COMPLEMENT)
ABSOLUTE VALUE
UPPER 8 BITS USED FOR
COMPARISON
1111 1111 1111 (4095)
0111 1111 1111 (+2047)
111 1111 1111 (2047)
1111 1111 (255)
1111 1111 0000 (4080)
0111 1111 0000 (+2032)
111 1111 0000 (2032)
1111 1110 (254)
1000 0000 0000 (2048)
0000 0000 0000 (0)
000 0000 0000 (0)
0000 0000 (0)
0000 0001 0000 (16)
1000 0001 0000 (–2032)
111 1111 0000 (2032)
1111 1110 (254)
0000 0000 0000 (0)
1000 0000 0000 (–2048)
111 1111 1111 (2047)
1111 1111 (255)
If the upper 8 bits of the absolute value equal or exceed the OVR_T0 or OVR_T1 thresholds during the
monitoring period, then the over-range bit associated with the threshold is set to 1, otherwise the over-range bit
is 0. In decimation bypass modes, the over-range status can be monitored on the ORA0 and ORA1 pins for
channel A and ORB0 and ORB1 pins for channel B, where ORx0 corresponds to the OVR_T0 threshold and
ORx1 corresponds to the OVR_T1 threshold. In decimation modes, (JMODE 9 through JMODE 16) the overrange status is output on the ORx0 and ORx1 pins as well as embedded into the output data samples. For
complex decimation modes the OVR_T0 threshold status is embedded as the LSB along with the upper 15 bits
of every complex I sample and OVR_T1 threshold status is embedded as the LSB along with the upper 15 bits of
every complex Q sample. For real decimation modes the OVR_T0 threshold status is embedded as the LSB of
every even numbered sample and OVR_T1 threshold status is embedded as the LSB of every odd numbered
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sample. Table 2 lists the outputs, related data samples, threshold settings and the monitoring period equation. In
single channel mode, both ORA0 and ORB0 indicators and ORA1 and ORB1 indicators must be monitored to
correctly detect an over-range condition for OVR_T0 and OVR_T1, respectively. The monitoring period and
reporting length of an over-range event can be adjusted by using the OVR_N setting. Table 3 lists the over-range
pulse lengths for the various OVR_N settings (Over-range Configuration Register (address = 0x213) [reset =
0x07]).
Table 2. Threshold and Monitoring Period for Over-Range Indicators in Dual Channel Decimation Modes
ORA0
ORA1
ORB0
ORB1
(1)
ASSOCIATED
THRESHOLD
OVR_T0
OVR_T1
OVR_T0
OVR_T1
DECIMATION TYPE
OVER-RANGE STATUS
EMBEDDED IN
Real Decimation (2x)
Channel A even
numbered samples
Complex Down-Conversion (4x, 8x,
16x)
Channel A In-Phase (I)
samples
Real Decimation (2x)
Channel A odd
numbered samples
Complex Down-Conversion (4x, 8x,
16x)
Channel A Quadrature
(Q) samples
Real Decimation (2x)
Channel B even
numbered samples
Complex Down-Conversion (4x, 8x,
16x)
Channel B In-Phase (I)
samples
Real Decimation (2x)
Channel B odd
numbered samples
Complex Down-Conversion (4x, 8x,
16x)
Channel B Quadrature
(Q) samples
MONITORING PERIOD
(ADC SAMPLES)
2OVR_N (1)
ADVANCE INFORMATION
OVER-RANGE
INDICATOR
OVR_N is the monitoring period register setting.
Table 3. Over-Range Monitoring Period
OVR_N
Over-range Pulse Length (DEVCLK cycles)
0
8
1
16
2
32
3
64
4
128
5
256
6
512
7
1024
Typically, the OVR_T0 threshold can be set near the full-scale value (228 for example). When the threshold is
triggered, a typical system can turn down the system gain to avoid clipping. The OVR_T1 threshold can be set
much lower. For example, the OVR_T1 threshold can be set to 64 (peak input voltage of −12 dBFS). If the input
signal is strong, the OVR_T1 threshold is tripped occasionally. If the input is quite weak, the threshold is never
tripped. The downstream logic device monitors the OVR_T1 bit. If OVR_T1 stays low for an extended period of
time, then the system gain can be increased until the threshold is occasionally tripped (meaning the peak level of
the signal is above −12 dBFS).
7.3.2.4 Code Error Rate (CER)
ADC cores can generate bit errors within a sample, often called code errors (CER) or referred to as sparkle
codes, due to metastability caused by non-ideal comparator limitations. The ADC12DJ3200 uses a unique ADC
architecture that inherently allows significant code error rate improvements from traditional pipelined flash or
successive approximation register (SAR) ADCs. The code error rate of the ADC12DJ3200 is multiple orders of
magnitude better than what can be achieved in alternative architectures at equivalent sampling rates providing
significant signal reliability improvements.
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7.3.3 Timestamp
TMSTP+ and TMSTP– differential input can be used as a time-stamp input to mark a specific sample based on
the timing of an external trigger event relative to the sampled signal. TIMESTAMP_EN (LSB Control Bit Output
Register (address = 0x160) [reset = 0x00]) must be set in order to use the timestamp feature and output the
timestamp data. When enabled, the LSB of the 12-bit ADC digital output reports the status of the TMSTP+/–
input. In effect, the 12-bit output sample consists of the upper 11-bits of the 12-bit converter and the LSB of the
12-bit output sample is the output of a parallel 1-bit converter (TMSTP+/–)with the same latency as the ADC
core. In the 8-bit operating modes, the LSB of the 8-bit output sample is used to output the timestamp status.
The trigger must be applied to the differential TMSTP+ and TMSTP– inputs. The trigger can be asynchronous to
the ADC sampling clock and is sampled at approximately the same time as the analog input. Timestamp cannot
be used when a JMODE with decimation is selected and instead SYSREF should be used to achieve
synchronization through JESD204B's subclass-1 method for achieving deterministic latency.
7.3.4 Clocking
The clocking subsystem of ADC12DJ3200 has two input signals, device clock (CLK+, CLK–) and SYSREF
(SYSREF+, SYSREF–). Within the clocking subsystem there is a noiseless aperture delay adjustment (tAD
Adjust), a clock duty cycle corrector and a SYSREF capture block. The clocking subsystem is shown in Figure 6.
CLK+
Clock Distribution
and Synchronization
(ADC cores, digital,
JESD204B, etc.)
IN
E
D_
F
TA
TA
D_
C
D_
IN
V
OA
RS
E
CLK-
TA
ADVANCE INFORMATION
Duty Cycle
Correction
tAD Adjust
SYSREF Capture
SYSREF+
SYSREF Windowing
SYSREF-
SYSREF_POS
SYSREF_SEL
Automatic
SYSREF
Calibration
SRC_EN
Copyright © 2016, Texas Instruments Incorporated
Figure 6. ADC12DJ3200 Clocking Subsystem
The device clock is used as the sampling clock for the ADC core as well as the clocking for the digital processing
and serializer outputs. A low noise (low jitter) device clock should be used to maintain high signal-to-noise ratio
(SNR) within the ADC. In dual channel mode the analog input signal for each input is sampled on the rising edge
of the device clock. In single channel mode both the rising and falling edge of the device clock are used to
capture the analog signal to reduce the max clock rate required by the ADC. Duty cycle correction is
implemented in ADC12DJ3200 to ease the requirements on the external device clock while maintaining high
performance. Table 4 summarizes the device clock interface in dual channel mode and single channel mode.
Table 4. Device Clock vs. Mode of Operation
30
Mode of Operation
Sampling Rate vs. FCLK
Dual channel mode
1 x FCLK
Rising edge
Single channel mode
2 x FCLK
Rising and falling edge
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SYSREF is a system timing reference used for JESD204B subclass-1 implementations of deterministic latency.
SYSREF is used to achieve deterministic latency and for multi-device synchronization. SYSREF must be
captured by the correct device clock edge in order to achieve repeatable latency and synchronization.
ADC12DJ3200 includes SYSREF Windowing and Automatic SYSREF Calibration to ease the requirements on
the external clocking circuits and simplify the synchronization process. SYSREF can be implemented as a single
pulse or as a periodic clock. In periodic implementations, SYSREF must be equal to, or an integer division of, the
local multi-frame clock frequency.
ADC12DJ3200 contains a delay adjustment on the device clock (sampling clock) input path, called tAD Adjust,
that can be used to shift the sampling instance within the device to align sampling instances among multiple
devices or for external interleaving of multiple ADC12DJ3200. Further, tAD Adjust can be used for automatic
SYSREF calibration for easy synchronization (Automatic SYSREF Calibration). tAD Adjust delays all clocks within
the device by the chosen amount, which will also shift the timing of the JESD204B serialized outputs. tAD Adjust
is implemented in a way that adds no additional noise (noiseless) to the clock path, however small reduction in
clock jitter is possible over the full adjustment range due to internal clock path attenuation resulting in minor SNR
degradations at high input frequencies (see TAJ in Switching Characteristics). tAD Adjust can be set using
TAD_INV, TAD_COARSE and TAD_FINE in DEVCLK Aperture Delay Adjustment Register (address = 0x2B5 to
0x2B7) [reset = 0x000000]. Setting TAD_INV inverts the input clock resulting in a delay equal to half the clock
period. TAD_COARSE and TAD_FINE are variable analog delays with step sizes and ranges summarized in
Table 5. All three delay options are independent and can be used in conjunction.
Table 5. tAD Adjust Adjustment Ranges
ADJUSTMENT PARAMETER
ADJUSTMENT STEP
DELAY SETTINGS
MAXIMUM DELAY
TAD_INV
1/(FCLK * 2)
1
1/(FCLK * 2)
TAD_COARSE
See tTAD(STEP) in Switching
Characteristics
256
See tTAD(MAX) in Switching
Characteristics
TAD_FINE
See tTAD(STEP) in Switching
Characteristics
256
~5 ps
tAD Adjust can be changed on-the-fly during normal operation. It is recommended to use TAD_RAMP to reduce
the probability of the JESD204B link losing synchronization. See Aperture Delay Ramp Control (TAD_RAMP).
7.3.4.2 Aperture Delay Ramp Control (TAD_RAMP)
ADC12DJ3200 contains a function to smoothly adjust the tAD Adjust value towards the newly set TAD_COARSE
value. This will allow the tAD Adjust value to be adjusted without glitching the internal clock circuitry. The
TAD_RAMP_RATE parameter allows either a slower or faster ramp to be selected. The TAD_RAMP_EN
parameter enables the ramp feature.
7.3.4.3 Automatic SYSREF Calibration
JESD204B interface ADCs require capture of SYSREF within a clock period to guarantee multi-device
synchronization or deterministic latency. ADC12DJ3200 can automatically make use of its tAD Adjust feature to
drastically simplify the synchronization process. At system startup, the device clock (CLK+/-) and SYSREF (+/-)
should be applied to the ADC12DJ3200 and ADC12DJ3200 should be programmed for normal operation.
SYSREF should be a continuous signal for this procedure to work. Once programmed, SRC_EN can be set in
Figure 91 to start the calibration process. The ADC12DJ3200 will then search for the optimal tAD Adjust setting
until the device clock falling edge is internally aligned to the SYSREF rising edge. SYSREF calibration maximizes
the internal SYSREF setup and hold times relative to the device clock while also aligning the sampling instant to
the SYSREF rising edge. Other than matching trace lengths to each ADC12DJ3200 device no other design
requirements are needed in order to achieve multi-device synchronization. A timing diagram of the SYSREF
calibration procedure is shown in Figure 7. The optimized setup and hold times are shown as tSU(OPT) and tH(OPT),
respectively.
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7.3.4.1 Noiseless Aperture Delay Adjustment (tAD Adjust)
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Sampled Input
Signal
Internal Unadjusted
Device Clock
Internal Calibrated
Device Clock
tTAD(SRC)
Internal SYSREF
tCAL(SRC)
ADVANCE INFORMATION
SRC_EN
(SPI register bit)
tH(OPT) tSU(OPT)
Before calibration, device clock falling edge
does not align with SYSREF rising edge
After calibration, device clock falling
edge aligns with SYSREF rising edge
Calibration
enabled
Figure 7. SYSREF Calibration Timing Diagram
After triggering SYSREF calibration, the bit TAD_DONE in Figure 93 can be monitored to ensure that SYSREF
calibration has finished. Once finished, the optimal tAD Adjust setting that SYSREF calibration has determined
can be read from SRC_TAD in Figure 93. After calibration, the system will automatically use the calibrated tAD
Adjust setting for operation until the system is powered down. The user also has the ability to disable SYSREF
calibration and then fine-tune the tAD Adjust setting according to the systems needs. Alternatively, the use of
SYSREF calibration and manual delay adjustment allows for calibration at product test (or periodical recalibration) of the optimal tAD Adjust setting for each system. SYSREF calibration should not be run while ADC
calibration (foreground or background) is running. If background calibration is the desired use case, it should be
disabled while SYSREF calibration is used, then enabled once TAD_DONE goes high for normal operation.
SYSREF_SEL in Clock Control Register 0 (address = 0x029) [reset = 0x00] must be set to 0 when using
SYSREF calibration.
SYSREF calibration will search the analog delay line delays using both non-inverted and inverted clock polarity
to minimize the required analog delay required in order to reduce clock additive jitter.
7.3.4.4 SYSREF Windowing
In order to guarantee multi-device synchronization or deterministic latency the SYSREF signal must be captured
by a deterministic device clock (CLK+/-) edge. The requirement imposes setup and hold constraints on SYSREF
relative to the device clock. At giga-sample clock rates external timing can be difficult. ADC12DJ3200 includes a
SYSREF window detection scheme and delay adjustment to aid the user in meeting optimal setup and hold
times.
First, the device clock and SYSREF should be applied to the device. The location of SYSREF relative to the
device clock cycle is determined and stored in SYSREF_POS in Figure 24. SYSREF_POS can be read through
SPI to find timing violations. Each bit of SYSREF_POS represents a delay in a delay chain. If a bit in
SYSREF_POS is set to '1', then that delay setting has a setup or hold violation. Upon determining the valid
SYSREF window (the positions of SYSREF_POS that are set to '0'), the midpoint should be chosen as the
SYSREF capture point by setting SYSREF_SEL in Clock Control Register 0 (address = 0x029) [reset = 0x00] to
the value corresponding to that SYSREF_POS position. Ideally, SYSREF_POS and SYSREF_SEL should be
performed at the middle of the system's operating temperature range to provide maximum margin for
temperature variations. This process can be performed at final test and the optimal SYSREF_SEL setting can be
stored for use at every system power up. Further, SYSREF_POS can be used to characterize SYSREF timing
over operating conditions for a specific system by sweeping the system temperature, for instance.
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NOTE
SYSREF_SEL should be set to '0' when using SYSREF calibration.
The delay steps for each SYSREF_POS bits can be adjusted using SYSREF_ZOOM. When SYSREF_ZOOM is
set to '0', the delay steps are roughly 77 ps. When SYSREF_ZOOM is set to '1', the delay steps are roughly 24
ps. SYSREF_ZOOM should always be used (SYSREF_ZOOM = 1) unless a transition region (defined by 1's in
SYSREF_POS) is not seen which could be the case for low clock rates (less than 1.6 GHz). Bits 0 and 23 of
SYSREF_POS will always be set to '1' since it cannot be determined if these settings are close to a timing
violation. The value programmed into SYSREF_SEL is the decimal number representing the desired bit location
in SYSREF_POS. Table 6 shows some example SYSREF_POS readings and the optimal SYSREF_SEL
settings.
SYSREF_POS (LSB->MSB)
OPTIMAL SYSREF_SEL SETTING
b100110000000011000000001
8 or 9
b100011000000000000011001
12
b100000000000011000000001
6 or 7
b100000001100000000000001
16
b100110001100011000110001
6
7.3.5 Digital Down Converters (Dual Channel Mode Only)
After converting the analog voltage to a digital value, the digitized sample can either be sent directly to the
JESD204B interface block (DDC bypass) or it can be sent to the digital down conversion (DDC) block for
frequency conversion and decimation (in dual channel mode only). Frequency conversion and decimation allow a
specific frequency band to be selected and output in the digital data stream while reducing the effective data rate
and interface speed or width. The DDC is designed such that the digital processing does not degrade the noise
spectral density (NSD) performance of the ADC. The digital down converter for channel A of the ADC12DJ3200
is shown in Figure 8. Channel B has the same structure with the input data selected by DIG_BIND_B and the
NCO selection mux controlled by pins NCOB[1:0] or through CSELB[1:0].
NCO Bank A
NCOA[1:0]
or
CSELA[1:0]
MUX
Complex
15-bit
@ Fs/N
Real
15-bit
@ Fs/2
2
Low Pass
MUX
DIG_BIND_A
High Pass
JESD204B
JMODE
JMODE
(DDC Bypass)
Spectral
Inversion
2
ADC
Channel B
2
Decimate-by-N
(based on JMODE)
MUX
Complex
Mixer
MUX
Real
12-bit
@ Fs
MUX
ADC
Channel A
MUX
N
D2_HIGH_PASS
INVERT_SPECTRUM
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Figure 8. Channel A Digital Down Conversion Block (Dual Channel Mode Only)
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ADVANCE INFORMATION
Table 6. Examples of SYSREF_POS Readings and SYSREF_SEL Selections
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7.3.5.1 Numerically Controlled Oscillator and Complex Mixer
The DDC contains a complex numerically-controlled oscillator (NCO) and a complex mixer. The oscillator
generates a complex exponential sequence as shown in Equation 2.
x[n] = ejωn
(2)
The frequency (ω) is specified by a 32-bit register setting. The complex exponential sequence is multiplied by the
real input from the ADC to mix the desired carrier to a frequency equal to fIN+fNCO, where fIN is the analog input
frequency after aliasing (in undersampling systems) and fNCO is the programmed NCO frequency.
7.3.5.1.1 NCO Fast Frequency Hopping (FFH)
Fast frequency hopping (FFH) is made possible by each DDC having four independent NCOs that can be
controlled by the NCOA0 and NCOA1 pins for DDC A and NCOB0 and NCOB1 pins for DDC B. Each NCO has
independent frequency settings (Basic NCO Frequency Setting Mode) and initial phase settings (NCO Phase
Offset Setting (Eight Total)) that can be set independently. Further, all NCOs have independent phase
accumulators that continue to run when the specific NCO is not selected, allowing the NCOs to maintain their
phase between selection so that downstream processing does not need to perform carrier recovery after each
hop.
ADVANCE INFORMATION
DDC Block
NCO Bank A
tGPIO-MIXER
tMIXER-TX
NCOx[1:0]
MUX
Dx0+/Dx1+/-
INx+
N
ADC
Dx2+/-
JESD204B
INxComplex
Mixer
Decimate-by-N
(based on JMODE)
Dx7+/-
tADC-MIXER
Copyright © 2016, Texas Instruments Incorporated
Figure 9. NCO Fast Frequency Hopping Latency Diagram
NCO hopping occurs when the NCO GPIO pins change state. The pins are controlled asynchronously and
therefore synchronous switching is not possible. Associated latencies are demonstrated in Figure 9, where tTX
and tADC are provided in Switching Characteristics. All latencies are approximations only and are not guaranteed
to be accurate.
Table 7. NCO Fast Frequency Hopping Latency Definitions
Latency Parameter
Value or Calculation
Units
tGPIO-MIXER
~36 to ~40
tCLK cycles
tADC-MIXER
~36
tCLK cycles
tMIXER-TX
(tTX + tADC) – tADC-MIXER
tCLK cycles
7.3.5.1.2 NCO Selection
Within each channel's DDC, four different frequency and phase settings are available for use. Each of the four
settings uses a different phase accumulator within the NCO. Since all four phase accumulators are independent
and continuously running, rapid switching between different NCO frequencies is possible allowing for phase
coherent frequency hopping.
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The specific frequency-phase pair used for each channel is selected through the NCOA[1:0] or NCOB[1:0] input
pins when CMODE () is set to 1. Alternatively, the selected NCO can be chosen through SPI by CSELA for DDC
A and CSELB for DDC B by setting CMODE to 0 (default). The logic table for NCO selection is provided in
Table 8 for both GPIO and SPI selection options.
NCO Selection
CMODE
NCOx1
NCOx0
CSELx[1]
CSELx[0]
NCO 0 using GPIO
1
0
0
X
X
NCO 1 using GPIO
1
0
1
X
X
NCO 2 using GPIO
1
1
0
X
X
NCO 3 using GPIO
1
1
1
X
X
NCO 0 using SPI
0
X
X
0
0
NCO 1 using SPI
0
X
X
0
1
NCO 2 using SPI
0
X
X
1
0
NCO 3 using SPI
0
X
X
1
1
The frequency for each phase accumulator is programmed independently through the FREQAn, FREQBn (n=0 to
3, see ) and, optionally, NCO_RDIV () settings. The phase offset for each accumulator is programmed
independently through the PHASEAn and PHASEBn (n=0 to 3, see ) register settings.
7.3.5.1.3 Basic NCO Frequency Setting Mode
In basic NCO frequency-setting mode (NCO_RDIV = 0x0000), the NCO frequency setting is set by the 32-bit
register value, FREQAn and FREQBn (n = 0 to 3, see ). The NCO frequency can be calculated using Equation 3.
ƒ(NCO) = FREQA/Bn × 2–32 × ƒ(DEVCLK) (n = 0 – 3)
(3)
NOTE
Changing the register setting after the JESD204B interface is running results in nondeterministic NCO phase. If deterministic phase is required, the JESD204B link must be
re-initialized after changing the register setting.
7.3.5.1.4 Rational NCO Frequency Setting Mode
In basic NCO frequency mode, the frequency step size is very small and many frequencies can be synthesized,
but sometimes an application requires very specific frequencies that fall between two frequency steps. For
example with ƒS equal to 2457.6 MHz and a desired ƒ(NCO) equal to 5.02 MHz the value for NCO_FREQ is
8773085.867. Truncating the fractional portion results in an ƒ(NCO) equal to 5.0199995 MHz, which is not the
desired frequency.
To produce the desired frequency, the NCO_RDIV parameter is used to force the phase accumulator to arrive at
specific frequencies without error. First, select a frequency step size (ƒ(STEP)) that is appropriate for the NCO
frequency steps required. The typical value of ƒ(STEP) is 10 kHz. Next, program the NCO_RDIV value according
to Equation 4.
NCO _ RDIV
§ ¦(DEVCLK) ·
¨
¸
¨ ¦(STEP) ¸
©
¹
128
(4)
The result of Equation 4 must be an integer value. If the value is not an integer, adjust either of the parameters
until the result in an integer value.
For example, select a value of 1920 for NCO_RDIV.
NOTE
NCO_RDIV values larger than 8192 can degrade the NCO SFDR performance and are
not recommended.
Now use Equation 5 to calculate the NCO_FREQ register value.
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Table 8. Logic Table for NCO Selection using GPIO or SPI
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NCO _ FREQ
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§ 225 u N ·
round u ¨
¨ NCO _ RDIV ¸¸
©
¹
(5)
Alternatively, the following equations can be used:
¦(NCO)
N
¦(STEP)
(6)
§ 2 u N ·
round u ¨
¨ NCO _ RDIV ¸¸
©
¹
25
NCO _ FREQ
(7)
Table 9. Common NCO_RDIV Values (For 10-kHz Frequency Steps)
ƒ(DEVCLK) (MHz)
NCO_RDIV
3200
2500
ADVANCE INFORMATION
3072
2400
2949.12
2304
2457.6
1920
1966.08
1536
1600
1250
1474.56
1152
1228.8
960
7.3.5.1.5 NCO Phase Offset Setting (Eight Total)
The NCO phase-offset setting is set by the 16-bit register value PHASEAn and PHASEBn (n = 0 to 3, see ). The
value is left-justified into a 32-bit field and then added to the phase accumulator.
Use Equation 8 to calculate the phase offset in radians.
Φ(rad) = PHASEA/Bn × 2–16 × 2 × π (n=0 to 3)
(8)
NOTE
Changing the register setting after the JESD204B interface is running results in nondeterministic NCO phase. If deterministic phase is required, the JESD204B link must be
re-initialized after changing the register setting.
7.3.5.1.6 NCO Phase Synchronization (Eight Total)
The NCOs must be synchronized after setting or changing the value of FREQAn, FREQBn, PHASEAn or
PHASEBn. NCO synchronization is performed when the JESD204B link is initialized or by SYSREF, based on
the settings of NCO_SYNC_ILA and NCO_SYNC_NEXT (). The procedures are given below for the JESD204B
initialization procedure and the SYSREF procedure for both DC coupled and AC coupled SYSREF signals.
NCO synchronization using JESD204B SYNC signal (SYNCSE or TMSTP+/–):
1. Device must be programmed for normal operation
2. Set NCO_SYNC_ILA to 1
3. Set JESD_EN to 0
4. Program FREQAn, FREQBn, PHASEAn and PHASEBn to the desired settings
5. In JESD204B receiver (logic device) deassert SYNC signal by setting it high
6. Set JESD_EN to 1
7. Assert SYNC signal by setting it low in JESD204B receiver to start CGS process
8. After achieving CGS, deassert SYNC signal by setting it high at the same time for all ADCs that are to be
synchronized and verify that SYNC setup and hold times are met (specified in Timing Requirements)
NCO synchronization using SYSREF (DC coupled):
1. Device must be programmed for normal operation
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2.
3.
4.
5.
6.
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Set JESD_EN to 1 to start JESD204B link (SYNC signal can respond as normal during CGS process)
Program FREQAn, FREQBn, PHASEAn and PHASEBn to the desired settings
Verify that SYSREF is disabled (held low)
Arm NCO synchronization by setting NCO_SYNC_NEXT to 1
Issue a single SYSREF pulse to all ADCs to synchronize NCOs within all devices
7.3.5.2 Decimation Filters
The decimation filters are arranged to provide a programmable overall decimation of 2, 4, 8 or 16. All filter
outputs have a resolution of 15 bits. The decimate-by-2 filter has a real output, while the decimate-by-4,
decimate-by-8, and decimate-by-16 filters have complex outputs. Table 10 lists the effective output sample rates,
available signal bandwidths, output formats and stopband attenuation for each decimation mode.
Table 10. Output Sample Rates and Signal Bandwidths
ƒ(DEVCLK)
DECIMATION SETTING
OUTPUT RATE
(MSPS)
MAX ALIAS PROTECTED
SIGNAL BANDWIDTH
(MHz)
STOP-BAND
ATTENUATION
Output Format
No decimation
ƒ(DEVCLK)
ƒ(DEVCLK) / 2
n/a
Real signal, 12-bit data
Decimate-by-2
ƒ(DEVCLK) / 2
0.4 x ƒ(DEVCLK) / 2
> 80 dB
Real signal, 15-bit data
Decimate-by-4 (D4_AP87 = 0)
ƒ(DEVCLK) / 4
0.8 x ƒ(DEVCLK) / 4
> 80 dB
Complex signal, 15-bit
data
Decimate-by-4 (D4_AP87 = 1)
ƒ(DEVCLK) / 4
0.875 x ƒ(DEVCLK) / 4
> 60 dB
Complex signal, 15-bit
data
Decimate-by-8
ƒ(DEVCLK) / 8
0.8 x ƒ(DEVCLK) / 8
> 80 dB
Complex signal, 15-bit
data
Decimate-by-16
ƒ(DEVCLK) / 16
0.8 x ƒ(DEVCLK) / 16
> 80 dB
Complex signal, 15-bit
data
For maximum efficiency a group of high speed filter blocks are implemented with specific blocks used for each
decimation setting. The first table below describes the combination of filter blocks used for each decimation
setting. The next table lists the coefficient details and decimation factor of each filter block.
Table 11. Decimation Mode Filter Usage
Decimation Setting
Filter Blocks Used
2
CS80
4 (D4_AP87 = 0)
CS45, CS80
4 (D4_AP87 = 1)
CS45, CS87
8
CS20, CS40, CS80
16
CS10, CS20, CS40, CS80
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NCO synchronization using SYSREF (AC coupled):
1. Device must be programmed for normal operation
2. Set JESD_EN to 1 to start JESD204B link (SYNC signal can respond as normal during CGS process)
3. Program FREQAn, FREQBn, PHASEAn and PHASEBn to the desired settings
4. Run SYSREF continuously
5. Arm NCO synchronization by setting NCO_SYNC_NEXT to 1 at the same time at all ADCs by timing the
rising edge of SCLK for the last data bit (LSB) at the end of the SPI write so that it occurs after a SYSREF
rising edge and early enough before the next SYSREF rising edge so that the trigger is armed before the
next SYSREF rising edge (long SYSREF period is recommended)
6. NCOs in all ADCs will be synchronized by the next SYSREF rising edge
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Table 12. Filter Coefficient Details
Filter Coefficient Set (Decimation Factor of Filter)
CS10 (2)
CS20 (2)
CS40 (2)
CS45 (2)
CS80 (2)
CS87 (2)
–65
–65
109
109
–327
–327
56
56
–37
–37
–15
0
0
0
0
0
0
0
0
0
0
0
0
577
577
–837
–837
2231
2231
–401
–401
118
118
23
23
1024
–15
0
0
0
0
0
0
0
0
0
0
4824
4824
–8881
–8881
1596
1596
–291
–291
–40
–40
8192
0
0
0
0
0
0
0
0
39742
39742
–4979
–4979
612
612
64
64
65536
0
0
0
0
0
0
20113
20113
–1159
–1159
–97
–97
32768
0
0
0
0
2031
2031
142
142
0
0
0
0
–3356
–3356
–201
–201
0
0
0
0
5308
5308
279
279
ADVANCE INFORMATION
0
0
0
0
–8140
–8140
–380
–380
0
0
0
0
12284
12284
513
513
0
0
0
0
–18628
–18628
–690
–690
0
0
0
0
29455
29455
939
939
0
0
0
0
–53191
–53191
–1313
–1313
0
0
0
0
166059
166059
1956
1956
262144
0
0
–3398
–3398
0
0
10404
10404
16384
7.3.5.3 Output Data Format
The DDC output data consist of 15–bit complex data plus the two over-range threshold-detection control bits.
The following table lists the data format:
16-BIT OUTPUT WORD
CHANNEL
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
I
DDC Output In-Phase (I) 15 bit
OR_T0
Q
DDC Output Quadrature (Q) 15 bit
OR_T1
7.3.5.4 Decimation Settings
7.3.5.4.1 Decimation Factor
The decimation setting is adjustable over the following settings and is set by the JMODE parameter.
• DDC Bypass: No decimation, real output
• Decimate-by-2: Real output
• Decimate-by-4: Complex output
• Decimate-by-8: Complex output
• Decimate-by-16: Complex output
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7.3.5.4.2 DDC Gain Boost
The DDC gain boost () provides additional gain through the DDC block. Setting BOOST to 1 sets the total
decimation filter chain gain to 6.02-dB. With a setting of 0, the total decimation filter chain has a 0-dB gain. This
setting should only be used when the negative image of the input signal is filtered out by the decimation filters,
otherwise clipping may occur. There is no reduction in analog performance when gain boost is enabled or
disabled, but care should be taken to understand the reference output power for proper performance
calculations.
7.3.6 JESD204B Interface
ADC12DJ3200 uses the JESD204B high-speed serial interface for data converters to transfer data from the ADC
to the receiving logic device. ADC12DJ3200 serialized lanes are capable of operating up to 12.8 Gbps, slightly
above the JESD204B max lane rate. A maximum of sixteen lanes can be used to allow lower lane rates for
interfacing with speed limited logic devices. Figure 10 shows a simplified block diagram of the JESD204B
interface protocol.
ADC
JESD204B
TRANSPORT
LAYER
SCRAMBLER
(Optional)
JESD204B
LINK LAYER
8b/10b
ENCODER
JESD204B
TX
ANALOG
CHANNEL
Logic Device
JESD204B Block
APPLICATION
LAYER
JESD204B
TRANSPORT
LAYER
DESCRAMBLE
(Optional)
JESD204B
LINK LAYER
8b/10b
DECODER
JESD204B
RX
Copyright © 2016, Texas Instruments Incorporated
Figure 10. Simplified JESD204B Interface Diagram
The various signals used in the JESD204B interface and the associated ADC12DJ3200 pin names are
summarized briefly in Table 13 for reference.
Table 13. Summary of JESD204B Signals
Signal Name
Data
SYNC
Device Clock
SYSREF
ADC12DJ3200 Pin Names
Description
DA0+...DA7+, DA0–...DA7–, DB0+...DB7+, DB0–...DB7–
High-speed serialized data after
8b/10b encoding
SYNCSE, TMSTP+, TMSTP–
Link initialization signal (handshake),
toggles low to start code group
synchronization (CGS) process
CLK+, CLK–
ADC sampling clock, also used for
clocking digital logic and output
serializers
SYSREF+, SYSREF–
System timing reference used to
deterministically reset the internal local
multiframe counters in each
JESD204B device
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7.3.6.1 Transport Layer
The transport layer takes samples from the ADC output (in decimation bypass mode) or from the DDC output
and maps the samples into octets, frames, multiframes and lanes. Sample mapping is defined by the JESD204B
mode that is used, defined by parameters such as L, M, F, S, N, N', CF, etc. There are a number of predefined
transport layer modes in the ADC12DJ3200 which are defined in Table 16. The high level configuration
parameters for the transport layer in ADC12DJ3200 are described in Table 14. For simplicity, the transport layer
mode is chosen by simply setting the JMODE parameter and the desired K value. For reference, the various
configuration parameters for JESD204B are defined in Table 15.
7.3.6.2 Scrambler
An optional data scrambler can be used to scramble the octets before transmission across the channel.
Scrambling is recommended in order to remove the possibility of spectral peaks in the transmitted data. The
JESD204B receiver automatically synchronizes its descrambler to the incoming scrambled data stream. The
initial lane alignment sequence (ILA) is never scrambled. Scrambling can be enabled by setting SCR (JESD204B
Control Register (address = 0x204) [reset = 0x02]).
7.3.6.3 Data Layer
ADVANCE INFORMATION
The data layer serves multiple purposes in JESD204B, including establishing the code boundaries (Code Group
Synchronization (CGS)), initializing the link (Initial Lane Alignment Sequence (ILAS)), encoding the data (8b/10b
Encoding) and monitoring the health of the link (Frame and Multiframe Monitoring).
7.3.6.3.1 Code Group Synchronization (CGS)
The first step in initializing the JESD204B link, after SYSREF is processed, is to achieve code group
synchronization. The receiver first asserts the SYNC signal when ready to initialize the link. The transmitter
responds to the request by sending a stream of K28.5 characters. The receiver then aligns its character clock to
the K28.5 character sequence. Code group synchronization is achieved after receiving four K28.5 characters
successfully. The receiver deasserts SYNC on the next LMFC edge after CGS is achieved and waits for the
transmitter to start the initial lane alignment sequence.
7.3.6.3.2 Initial Lane Alignment Sequence (ILAS)
After the transmitter sees the SYNC signal deassert it waits until its next LMFC edge to start sending the initial
lane alignment sequence. The ILAS consists of four multiframes each containing a predetermined sequence. The
receiver looks for the start of the ILAS to determine the frame and multiframe boundaries. As the ILAS reaches
the receiver for each lane, the lane starts to buffer its data until all receivers have received the ILAS and
subsequently release the ILAS from all lanes at the same time in order to align the lanes. The second multiframe
of the ILAS contains configuration parameters for the JESD204B that can be used by the receiver to verify that
the transmitter and receiver configurations match.
7.3.6.3.3 8b/10b Encoding
The data link layer converts the 8-bit octets from the transport layer into 10-bit characters for transmission across
the link using 8b/10b encoding. 8b/10b encoding provides DC balance for AC coupling of the serdes links and a
sufficient number of edge transitions for the receiver to reliably recover the data clock. 8b/10b also provides
some amount of error detection where a single bit error in a character will likely result in either not being able to
find the 10-bit character in the 8b/10b decoder lookup table or incorrect character disparity.
7.3.6.3.4 Frame and Multiframe Monitoring
ADC12DJ3200 supports frame and multiframe monitoring for verifying the health of the JESD204B link. If the last
octet of a frame matches the last octet of the previous frame, then the second frame's last octet is replaced with
a /F/ (/K28.7/) character. If the second frame is the last frame of a multiframe then a /A/ (/K28.3/) character is
used instead. When scrambling is enabled, if the last octet of a frame is 0xFC then the transmitter replaces it
with a /F/ (/K28.7/) character. With scrambling, if the last octet of a multiframe is 0x7C then the transmitter
replaces it with a /A/ (/K28.3/) character. When the receiver sees a /F/ or /A/ character, it checks to see if it
occurs at the end of a frame or multiframe, and replaces it with the appropriate data character. The receiver can
report an error if the alignment characters occur in the incorrect place and trigger a link realignment.
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7.3.6.4 Physical Layer
The JESD204B physical layer consists of a current mode logic (CML) output driver and receiver. The receiver
consists of a clock detection and recovery (CDR) unit to extract the data clock from the serialized data stream
and may contain an equalizer to correct for the low pass response of the physical transmission channel.
Likewise, the transmitter may contain pre-equalization to account for frequency dependent losses across the
channel. The total reach of the serdes links depends on the data rate, board material, connectors, equalization,
noise and jitter, and required bit-error performance. The serdes lanes do not have to be matched in length as the
receiver will align the lanes during the initial lane alignment sequence.
7.3.6.4.1 Serdes Pre-Emphasis
7.3.6.5 JESD204B Enable
The JESD204B interface must be disabled through JESD_EN (JESD204B Enable Register (address = 0x200)
[reset = 0x01]) while any of the other JESD204B parameters are being changed. While JESD_EN is set to 0 the
block is held in reset and the serializers are powered down. The clocks for this section are also gated off to
further save power. When the parameters have been set as desired the JESD204B block can be enabled
(JESD_EN is set to 1).
7.3.6.6 Multi-Device Synchronization and Deterministic Latency
7.3.6.7 Operation in Subclass 0 Systems
7.3.7 Alarm Monitoring
A number of built in alarms are available to monitor internal events. Several types of alarms/upsets are detected
by this feature:
1. Serializer PLL not locked
2. JESD204B link not transmitting data (not in the data transmission state)
3. SYSREF caused internal clocks to be realigned
4. An upset that impacts the NCO
5. An upset that impacts the internal clocks
When an alarm occurs, a bit for each specific alarm is set in ALM_STATUS. Each alarm bit remains set until the
host system writes a 1 to clear it. If the alarm type is not masked (see ALM_MASK), then the alarm is also
indicated by the ALARM register. The CALSTAT output pin can be configured as an alarm output that will go
high when an alarm occurs. See CAL_STATUS_SEL.
7.3.7.1 NCO Upset Detection
The NCO_ALM register bit indicates if the NCO in channel A or B may have been upset. The NCO phase
accumulators in channel A are continuously compared to channel B. If they differ for even one clock cycle, the
NCO_ALM register bit is set and remains set until cleared by the host system by writing a 1. This feature
requires the phase and frequency words for each NCO accumulator in DDC A (PHASEAx, FREQAx) to be set to
the same values as the NCO accumulators in DDC B (PHASEBx, FREQBx). For example, PHASEA0 must be
the same as PHASEB0 and FREQA0 must be the same as FREQB0, however PHASEA1 can be set to a
different value than PHASEA0. This ultimate reduces the number of NCO frequencies available for phase
coherent frequency hopping from four to two for each DDC. Note that DDC B can use a different NCO frequency
than DDC A by setting the NCOB[1:0] pins to a different value than NCOA[1:0]. This detection is only valid after
the NCOs have been synchronized by either SYSREF or the start of the ILA sequence (as determined by
NCO_SYNC). For NCO upset detection to work properly, follow this usage model:
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ADC12DJ3200 high-speed output drivers can pre-equalize the transmitted data stream by using pre-emphasis in
order to compensate for the low pass response of the transmission channel. Configurable pre-emphasis settings
allow the output drive waveform to be optimized for different PCB materials and signal transmission distances.
The pre-emphasis setting is adjusted through the serializer pre-emphasis setting SER_PE (Serializer PreEmphasis Control Register (address = 0x048) [reset = 0x00]). Higher values will increase the pre-emphasis to
compensate for more lossy PCB materials. This adjustment is best used in conjunction with an eye-diagram
analysis capability in the receiver. The pre-emphasis setting should be adjusted to optimize the eye-opening for
the specific hardware configuration and line rates needed.
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1.
2.
3.
4.
Program JESD_EN=0
Ensure the part is configured to utilize both channels (PD_ACH=0, PD_BCH=0)
Select a JMODE that utilizes the NCO
Program all NCO frequencies and phases the same for channel A and B, for example FREQA0=FREQB0,
FREQA1=FREQB1, FREQA2=FREQB2, FREQA3=FREQB3).
5. If desired, utilize the CMODE and CSEL registers or the NCOA[1:0] and NCOB[1:0] pins to choose a unique
frequency for channel A and channel B
6. Program JESD_EN=1
7. Synchronize the NCOs (using the ILA or using SYSREF). See NCO_SYNC register.
8. Write a ‘1’ to the NCO_ALM register bit to clear it
9. Monitor the NCO_ALM status bit or the CALSTAT output pin if CAL_STATUS_SEL is properly configured
10. If the frequency or phase registers are changed while the NCO is enabled, the NCOs can get out of
synchronization. Repeat steps 7-9.
11. If the device enters and exits global power down, repeat steps 7-9.
7.3.7.2 Clock Upset Detection
ADVANCE INFORMATION
The CLK_ALM register bit indicates if the internal clocks may have been upset. The clocks in channel A are
continuously compared to channel B. If they differ for even one DEVCLK/2 cycle, the CLK_ALM register bit is set
and remains set until cleared by the host system by writing a ‘1’. For the CLK_ALM register bit to function
properly, follow this usage model:
1.
2.
3.
4.
5.
6.
Program JESD_EN=0
Ensure the part is configured to utilize both channels (PD_ACH=0, PD_BCH=0)
Program JESD_EN=1
Write CLK_ALM=1 to clear CLK_ALM
Monitor the CLK_ALM status bit or the CALSTAT output pin if CAL_STATUS_SEL is properly configured
When exiting global power-down (via MODE or the PD pin), the CLK_ALM status bit may be set and should
be cleared by writing a '1' to CLK_ALM
7.3.8 Temperature Monitoring Diode
A built-in thermal monitoring diode is made available on the TDIODE+ and TDIODE– pins. This diode facilitates
temperature monitoring and characterization of the device in higher ambient temperature environments. While
the on-chip diode is not highly characterized, the diode can be used effectively by performing a baseline
measurement (offset) at a known ambient or board temperature and creating a linear equation with the diode
voltage slope provided in Electrical Characteristics - DC Specifications. Offset measurement should be done with
the device unpowered or with the PD pin asserted to minimize device self-heating. PD pin should be asserted
only long enough to take the offset measurement. Recommended monitoring ICs include the LM95233 device
and similar remote-diode temperature monitoring products from Texas Instruments.
7.3.9 Analog Reference Voltage
The reference voltage for ADC12DJ3200 is derived from an internal bandgap reference. A buffered version of the
reference voltage is available at the BG pin for user convenience. This output has an output-current capability of
±100 μA. The BG output must be buffered if more current is required. No provision exists for the use of an
external reference voltage, but the full-scale input voltage can be adjusted through the full-scale-range register
settings. In unique cases, the VA11 supply voltage can act as the reference voltage by setting BG_BYPASS
(Internal Reference Bypass Register (address = 0x038) [reset = 0x00]).
7.4 Device Functional Modes
ADC12DJ3200 can be configured to operate in a number of functional modes. These modes are described in this
section.
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Device Functional Modes (continued)
7.4.1 Dual Channel Mode
ADC12DJ3200 can be used as a dual channel ADC where the sampling rate is equal to the clock frequency (FS
= FCLK) provided at the CLK+ and CLK- pins. The two inputs, AIN+/- and BIN+/-, serve as the respective inputs
for each channel in this mode. This mode is chosen simply by setting JMODE to the appropriate setting for the
desired configuration as described in Table 16. The analog inputs can be swapped by setting DUAL_INPUT
(Input Mux Control Register (address = 0x060) [reset = 0x01])
7.4.2 Single Channel Mode (DES Mode)
NOTE
In single channel mode it is strongly recommended that INA+/– be used as the input to the
ADC for optimized performance.
7.4.3 JESD204B Modes
ADC12DJ3200 can be programmed as a single channel or dual channel ADC, with or without decimation, and a
number JESD204B output formats. Table 14 summarizes the basic operating mode configuration parameters
and whether they are user configured or derived.
NOTE
Power down of the high speed data outputs (DA0+/– ... DA7+/–, DB0+/– ... DB7+/–) for
extended times may reduce performance of the output serializers, especially at high data
rates. Please see note beneath Recommended Operating Conditions for more information.
Table 14. ADC12DJ3200 Operating Mode Configuration Parameters
Parameter
Description
User configured or Derived
Value
JMODE
JESD204B operating mode,
automatically derives the rest of
the JESD204B parameters,
single channel or dual channel
mode and the decimation factor
User
Set by JMODE (JESD204B Mode
Register (address = 0x201) [reset
= 0x02])
D
Decimation factor
Derived
See Table 16
DES
1 = single channel mode, 0 =
dual channel mode
Derived
See Table 16
R
Number of bits transmitted per
Derived
lane per DEVCLK cycle. The
JESD204B linerate is the
DEVCLK frequency times R. This
parameter sets the SERDES PLL
multiplication factor or controls
bypassing of the SERDES PLL.
See Table 16
Links
Number of JESD204B links used
Derived
See Table 16
K
Number of frames per multiframe
User Configured
Set by KM1 (JESD204B K
Parameter Register (address =
0x202) [reset = 0x1F]), see
allowed values in Table 16
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ADVANCE INFORMATION
ADC12DJ3200 can also be used as a single channel ADC where the sampling rate is equal to two times the
clock frequency (FS = 2xFCLK) provided at the CLK+ and CLK– pins. This mode effectively interleaves the two
ADC channels together to form a single channel ADC at twice the sampling rate. This mode is chosen simply by
setting JMODE to the appropriate setting for the desired configuration as described in Table 16. Either analog
input, INA+/– or INB+/–, can serve as the input to the ADC, however INA+/– is recommended for best
performance. The analog input can be selected using SINGLE_INPUT (Input Mux Control Register (address =
0x060) [reset = 0x01]). The digital down-converters cannot be used in single channel mode.
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There are a number of parameters required to define the JESD204B format, all of which are sent across the link
during the initial lane alignment sequence. In the ADC12DJ3200, most of the parameters are automatically
derived based on the selected JMODE; however, a few are configured by the user. These parameters are
described in Table 15.
Table 15. JESD204B Initial Lane Alignment Sequence Parameters
ADVANCE INFORMATION
Parameter
Description
User configured or Derived
Value
ADJCNT
LMFC adjustment amount (not
applicable)
Derived
Always 0
ADJDIR
LMFC adjustment direction (not
applicable)
Derived
Always 0
BID
Bank ID
Derived
Always 0
CF
Number of control words per
frame
Derived
Always 0
CS
Control bits per sample
Derived
Always set to 0 in ILAS, see
Table 16 for actual usage
DID
Device identifier, used to identify
the link
User
Set by DID (JESD204B DID
Parameter Register (address =
0x206) [reset = 0x00]), see
Table 17
F
Number of octets (bytes) per
frame (per lane)
Derived
See Table 16
HD
High density format (samples
split between lanes)
Derived
Always 0
JESDV
JESD204 standard revision
Derived
Always 1
K
Number of frames per multiframe
User
Set by KM1 register, JESD204B
K Parameter Register (address =
0x202) [reset = 0x1F]
L
Number of serial output lanes per Derived
link
See Table 16
LID
Lane identifier for each lane
Derived
See Table 17
M
Number of converters used to
determine lane bit packing; may
not match number of ADC
channels in the device
Derived
See Table 16
N
Sample resolution (before adding Derived
control and tail bits)
See Table 16
N'
Bits per sample after adding
control and tail bits
Derived
See Table 16
S
Number of samples per converter Derived
(M) per frame
See Table 16
SCR
Scrambler enabled
User
Set by SCR register
SUBCLASSV
Device subclass version
Derived
Always 1
RES1
Reserved field 1
Derived
Always 0
RES2
Reserved field 2
Derived
Always 0
CHKSUM
Checksum for ILAS checking
(sum of all above parameters
modulo 256)
Derived
Computed based on above
parameters
Configuring the ADC12DJ3200 is made easy by use of a single configuration parameter called JMODE
(JESD204B Mode Register (address = 0x201) [reset = 0x02]). Using Table 16, the correct JMODE value can be
found for the desired operating mode. The modes shown in Table 16 are the only available operating modes.
The table also gives a range and allowable step size for the K parameter (set by KM1, see JESD204B K
Parameter Register (address = 0x202) [reset = 0x1F]), which sets the multi-frame length in number of frames.
44
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Table 16. ADC12DJ3200 Operating Modes
User Specified Parameter
Derived Parameters
JMODE
K
[Min:Step:Max]
D
DES
Links
N
CS
N’
L
M
F
(per link) (per link)
12-bit, Single Channel, 8 lanes
0
3:1:32
1
1
2
12
0
12
4
4 (1)
12-bit, Single Channel, 16 lanes
1
3:1:32
1
1
2
12
0
12
8
8 (1)
Input Clock
Range (MHz)
S
R
(Fbit/Fclk)
8
5
4
800-3200
8
5
2
800-3200
(1)
12-bit, Dual Channel, 8 lanes
2
3:1:32
1
0
2
12
0
12
4
4
8
5
4
800-3200
12-bit, Dual Channel, 16 lanes
3
3:1:32
1
0
2
12
0
12
8
8 (1)
8
5
2
800-3200
8-bit, Single Channel, 4 lanes
4
18:2:32
1
1
2
8
0
8
2
1
1
2
5
800-2560
8-bit, Single Channel, 8 lanes
5
18:2:32
1
1
2
8
0
8
4
1
1
4
2.5
800-3200
8-bit, Dual Channel, 4 lanes
6
18:2:32
1
0
2
8
0
8
2
1
1
2
5
800-2560
8-bit, Dual Channel, 8 lanes
7
18:2:32
1
0
2
8
0
8
4
1
1
4
2.5
800-3200
RESERVED
8
-
-
-
-
-
-
-
-
-
-
-
-
-
(2)
15-bit, Real Data, Decimate-by-2, 8 lanes
9
9:1:32
2
0
2
15
1
16
4
1
2
4
2.5
800-3200
15-bit, Decimate-by-4, 4 lanes
10
9:1:32
4
0
2
15
1 (2)
16
2
2
2
1
5
800-2560
15-bit, Decimate-by-4, 8 lanes
11
9:1:32
4
0
2
15
1 (2)
16
4
2
2
2
2.5
800-3200
(1)
12-bit, Decimate-by-4, 16 lanes
12
3:1:32
4
0
2
12
0
12
8
8
8
5
1
1000-3200
15-bit, Decimate-by-8, 2 lanes
13
5:1:32
8
0
2
15
1 (2)
16
1
2
4
1
5
800-2560
15-bit, Decimate-by-8, 4 lanes
14
9:1:32
8
0
2
15
1 (2)
16
2
2
2
1
2.5
800-3200
(2)
15-bit, Decimate-by-16, 1 lane
15
3:1:32
16
0
1
15
1
16
1
4
8
1
5
800-2560
15-bit, Decimate-by-16, 2 lanes
16
5:1:32
16
0
2
15
1 (2)
16
1
2
4
1
2.5
800-3200
8-bit, Single Channel, 16 lanes
17
18:2:32
1
1
2
8
0
8
8
1
1
8
1.25
800-3200
8-bit, Dual Channel, 16 lanes
18
18:2:32
1
0
2
8
0
8
8
1
1
8
1.25
800-3200
(1)
(2)
M equals L in these modes to allow the samples to be sent in time-order over L lanes. The M parameter does not represent the actual number of converters. The M sample streams from
each link should be interleaved in the receiver to produce the correct sample data. See mode diagrams for more details.
CS is always reported as 0 in the initial lane alignment sequence (ILAS) for ADC12DJ3200.
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ADC12DJ3200 Operating Mode
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ADC12DJ3200 has a total of sixteen high-speed output drivers which are grouped into two eight lane JESD204B
links. Most of the operating modes use two links with up to eight lanes per link. The lanes and their derived
configuration parameters are described in Table 17. For a specified JMODE, the lowest indexed lanes for each
link are used while the higher indexed lanes for each link are automatically powered down. Always route the
lowest indexed lanes to the logic device.
Table 17. ADC12DJ3200 Lane Assignment and Parameters
Device Pin
Designation
Link
DID (User Configured)
LID (Derived)
DA0+/–
0
DA1+/–
1
DA2+/–
DA5+/–
2
Set by DID (JESD204B DID
Parameter Register (address = 0x206) 3
[reset = 0x00]), the effective DID is
4
equal to the DID register setting (DID)
5
DA6+/–
6
DA7+/–
7
DB0+/–
0
DB1+/–
1
DA3+/–
DA4+/–
A
ADVANCE INFORMATION
DB2+/–
DB3+/–
DB4+/–
Set by DID (JESD204B DID
Parameter Register (address = 0x206)
[reset = 0x00]), the effective DID is
equal to the DID register setting plus 1
(DID+1)
B
DB5+/–
2
3
4
5
DB6+/–
6
DB7+/–
7
7.4.3.1 JESD204B Output Data Formats
Output data is formatted in a specific optimized fashion for each JMODE setting. When the DDC is not used
(Decimation = 1) the 12-bit offset binary values are mapped into octets. For the DDC mode the 16-bit values (15bit complex data plus 1 over-range bit) are mapped into octets. The following tables show the specific mapping
formats for a single frame. In all mappings the tail bits (T) are 0 (zero). In the tables below, the single channel
format samples are defined as Sn, where n is the sample number within the frame. In the dual channel real
output formats (DDC bypass and Dec-by-2), the samples are defined as An and Bn, where An are samples from
channel A and Bn are samples from channel B. In the complex output formats (Dec-by-4, Dec-by-8, Dec-by-16),
the samples are defined as AIn, AQn, BIn and BQn, where AIn and AQn are the in-phase and quadrature-phase
samples of channel A and BIn and BQn are the in-phase and quadrature-phase samples of channel B. All
samples are formatted as MSB first, LSB last.
46
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Table 18. JMODE 0 (12-bit, Dec-by-1, Single Channel, 8 lanes)
Octet
Nibbl
e
0
0
1
1
2
2
3
4
3
5
6
4
7
8
5
9
10
6
11
12
7
13
14
15
DA0
S0
S8
S16
S24
S32
T
DA1
S2
S10
S18
S26
S34
T
DA2
S4
S12
S20
S28
S36
T
DA3
S6
S14
S22
S30
S38
T
DB0
S1
S9
S17
S25
S33
T
DB1
S3
S11
S19
S27
S35
T
DB2
S5
S13
S21
S29
S37
T
DB3
S7
S15
S23
S31
S39
T
Table 19. JMODE 1 (12-bit, Dec-by-1, Single Channel, 16 lanes)
Nibbl
e
0
0
1
1
2
2
3
4
3
5
6
4
7
8
5
9
10
6
11
12
7
13
14
15
DA0
S0
S16
S32
S48
S64
T
DA1
S2
S18
S34
S50
S66
T
DA2
S4
S20
S36
S52
S68
T
DA3
S6
S22
S38
S54
S70
T
DA4
S8
S24
S40
S56
S72
T
DA5
S10
S26
S42
S58
S74
T
DA6
S12
S28
S44
S60
S76
T
DA7
S14
S30
S46
S62
S78
T
DB0
S1
S17
S33
S49
S65
T
DB1
S3
S19
S35
S51
S67
T
DB2
S5
S21
S37
S53
S69
T
DB3
S7
S23
S39
S55
S71
T
DB4
S9
S25
S41
S57
S73
T
DB5
S11
S27
S43
S59
S75
T
DB6
S13
S29
S45
S61
S77
T
DB7
S15
S31
S47
S63
S79
T
ADVANCE INFORMATION
Octet
Table 20. JMODE 2 (12-bit, Dec-by-1, Dual Channel, 8 lanes)
Octet
Nibbl
e
0
0
1
1
2
2
3
4
3
5
6
4
7
8
5
9
10
6
11
12
7
13
14
15
DA0
A0
A4
A8
A12
A16
T
DA1
A1
A5
A9
A13
A17
T
DA2
A2
A6
A10
A14
A18
T
DA3
A3
A7
A11
A15
A19
T
DB0
B0
B4
B8
B12
B16
T
DB1
B1
B5
B9
B13
B17
T
DB2
B2
B6
B10
B14
B18
T
DB3
B3
B7
B11
B15
B19
T
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Table 21. JMODE 3 (12-bit, Dec-by-1, Dual Channel, 16 lanes)
Octet
Nibbl
e
0
0
1
1
2
2
3
4
3
5
6
4
7
8
5
9
10
6
11
7
12
13
14
15
ADVANCE INFORMATION
DA0
A0
A8
A16
A24
A32
T
DA1
A1
A9
A17
A25
A33
T
DA2
A2
A10
A18
A26
A34
T
DA3
A3
A11
A19
A27
A35
T
DA4
A4
A12
A20
A28
A36
T
DA5
A5
A13
A21
A29
A37
T
DA6
A6
A14
A22
A30
A38
T
DA7
A7
A15
A23
A31
A39
T
DB0
B0
B8
B16
B24
B32
T
DB1
B1
B9
B17
B25
B33
T
DB2
B2
B10
B18
B26
B34
T
DB3
B3
B11
B19
B27
B35
T
DB4
B4
B12
B20
B28
B36
T
DB5
B5
B13
B21
B29
B37
T
DB6
B6
B14
B22
B30
B38
T
DB7
B7
B15
B23
B31
B39
T
Table 22. JMODE 4 (8-bit, Dec-by-1, Single Channel, 4 lanes)
Octet
0
Nibble
0
1
DA0
S0
DA1
S2
DB0
S1
DB1
S3
Table 23. JMODE 5 (8-bit, Dec-by-1, Single Channel, 8 lanes)
Octet
0
Nibble
0
1
DA0
S0
DA1
S2
DA2
S4
DA3
S6
DB0
S1
DB1
S3
DB2
S5
DB3
S7
Table 24. JMODE 6 (8-bit, Dec-by-1, Dual Channel, 4 lanes)
Octet
Nibble
48
0
0
1
DA0
A0
DA1
A1
DB0
B0
DB1
B1
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Table 25. JMODE 7 (8-bit, Dec-by-1, Dual Channel, 8 lanes)
Octet
0
Nibble
0
1
DA0
A0
DA1
A1
DA2
A2
DA3
A3
DB0
B0
DB1
B1
DB2
B2
DB3
B3
Table 26. JMODE 9 (15-bit, Dec-by-2, Dual Channel, 8 lanes)
0
0
1
1
2
DA0
A0
DA1
A1
DA2
A2
DA3
A3
DB0
B0
DB1
B1
DB2
B2
DB3
B3
3
ADVANCE INFORMATION
Octet
Nibble
Table 27. JMODE 10 (15-bit, Dec-by-4, Dual Channel, 4 lanes)
Octet
Nibble
0
0
1
1
2
DA0
AI0
DA1
AQ1
DB0
BI0
DB1
BQ1
3
Table 28. JMODE 11 (15-bit, Dec-by-4, Dual Channel, 8 lanes)
Octet
Nibble
0
0
DA0
1
1
2
3
AI0
DA1
AI1
DA2
AQ0
DA3
AQ1
DB0
BI0
DB1
BI1
DB2
BQ0
DB3
BQ1
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Table 29. JMODE 12 (12-bit, Dec-by-4, Dual Channel, 16 lanes)
Octet
0
Nibbl
e
0
1
1
2
2
3
4
3
5
6
4
7
5
8
9
10
6
11
7
12
13
14
15
DA0
AI0
AI4
AI8
AI12
AI16
T
DA1
AQ0
AQ4
AQ8
AQ12
AQ16
T
DA2
AI1
AI5
AI9
AI13
AI17
T
DA3
AQ1
AQ5
AQ9
AQ13
AQ17
T
DA4
AI2
AI6
AI10
AI14
AI18
T
DA5
AQ2
AQ6
AQ10
AQ14
AQ218
T
DA6
AI3
AI7
AI11
AI15
AI19
T
DA7
AQ3
AQ7
AQ11
AQ15
AQ19
T
DB0
BI0
BI4
BI8
BI12
BI16
T
DB1
BQ0
BQ4
BQ8
BQ12
BQ16
T
ADVANCE INFORMATION
DB2
BI1
BI5
BI9
BI13
BI17
T
DB3
BQ1
BQ5
BQ9
BQ13
BQ17
T
DB4
BI2
BI6
BI10
BI14
BI18
T
DB5
BQ2
BQ6
BQ10
BQ14
BQ218
T
DB6
BI3
BI7
BI11
BI15
BI19
T
DB7
BQ3
BQ7
BQ11
BQ15
BQ19
T
Table 30. JMODE 13 (15-bit, Dec-by-8, Dual Channel, 2 lanes)
Octet
0
Nibble
1
0
1
2
2
3
3
4
5
6
DA0
AI0
AQ0
DB0
BI0
BQ0
7
Table 31. JMODE 14 (15-bit, Dec-by-8, Dual Channel, 4 lanes)
Octet
0
Nibble
1
0
1
2
DA0
AI0
DA1
AQ0
DB0
BI0
DB1
BQ0
3
Table 32. JMODE 15 (15-bit, Dec-by-16, Dual Channel, 1 lane)
Octet
0
Nibbl
e
0
DA0
1
1
2
2
3
4
3
5
AI0
6
4
7
8
5
9
AQ0
10
6
11
7
12
13
BI0
14
15
BQ0
Table 33. JMODE 16 (15-bit, Dec-by-16, Dual Channel, 2 lanes)
Octet
Nibble
50
0
0
1
1
2
2
3
4
3
5
6
DA0
AI0
AQ0
DB0
BI0
BQ0
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Table 34. JMODE 17 (8-bit, Dec-by-1, Single Channel, 16 lanes)
0
0
1
DA0
S0
DA1
S2
DA2
S4
DA3
S6
DA4
S8
DA5
S10
DA6
S12
DA7
S14
DB0
S1
DB1
S3
DB2
S5
DB3
S7
DB4
S9
DB5
S11
DB6
S13
DB7
S15
ADVANCE INFORMATION
Octet
Nibble
Table 35. JMODE 18 (8-bit, Dec-by-1, Dual Channel, 16 lanes)
Octet
0
Nibble
0
1
DA0
A0
DA1
A1
DA2
A2
DA3
A3
DA4
A4
DA5
A5
DA6
A6
DA7
A7
DB0
B0
DB1
B1
DB2
B2
DB3
B3
DB4
B4
DB5
B5
DB6
B6
DB7
B7
7.4.3.2 Dual DDC and Redundant Data Mode
When operating in dual channel mode the data from one channel can be routed to both digital down-converter
blocks by using DIG_BIND_A or DIG_BIND_B (). This enables down-conversion of two separate captured bands
from a single ADC channel. The second ADC can be powered down in this mode by setting PD_ACH or
PD_BCH (Device Configuration Register (address = 0x002) [reset = 0x00]).
Additionally, DIG_BIND_A or DIG_BIND_B can be used to provide redundant data to separate digital processors
by routing data from one ADC channel to both JESD204B links. Redundant data mode is available for all JMODE
modes except for the single channel modes. Both dual DDC mode and redundant data mode are demonstrated
in Figure 11 where the data for ADC channel A is routed to both DDCs and then transmitted to a single
processor or two processors (for redundancy).
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DDC A
DIG_BIND_A = 0
DDC Bypass
JESD204B
LINK A
(DA0-DA7)
MUX
ADC
Channel A
MUX
DDC Bypass
ADC
Channel B
DDC B
JESD204B
LINK B
(DB0-DB7)
MUX
MUX
JMODE
JMODE
DIG_BIND_B = 0
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Figure 11. Dual DDC Mode or Redundant Data Mode for Channel A
ADVANCE INFORMATION
7.4.4 Power Down Modes
NOTE
Power down of the high speed data outputs (DA0+/– ... DA7+/–, DB0+/– ... DB7+/–) for
extended times may reduce performance of the output serializers, especially at high data
rates. Please see note beneath Recommended Operating Conditions for more information.
The PD input pin allows the ADC12DJ3200 devices to be entirely powered down. Power down can also be
controlled by MODE (Device Configuration Register (address = 0x002) [reset = 0x00]). The serial data output
drivers are disabled when PD is high. When the device returns to normal operation, the JESD204 link must be
re-established, and the ADC pipeline contain meaningless information so the system must wait a sufficient time
for the data to be flushed. If power down for power savings is desired the system should power down the supply
voltages regulators for VA19, VA11 and VD11 rather than make use of the PD input or MODE settings.
7.4.5 Test Modes
A number of device test modes are available. These modes insert known patterns of information into the device
data path for assistance with system debug, development, or characterization.
7.4.5.1 Serializer Test-Mode Details
Test modes are enabled by setting JTEST (JESD204B Test Pattern Control Register (address = 0x205) [reset =
0x00]) to the desired test mode. Each test mode is described in detail in the following sections. Regardless of the
test mode, the serializer outputs are powered up based on JMODE. The test modes should only be enabled
while the JESD204B link is disabled.
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ADC
JESD204B Block
JESD204B
TRANSPORT
LAYER
ADC
SCRAMBLER
(Optional)
Long/Short Transport
Octet Ramp
Test Mode Enable
JESD204B
LINK LAYER
8b/10b
ENCODER
Repeated ILA
Modified RPAT
Test Mode Enable
Active Lanes and
Serial Rates
Set by JMODE
JESD204B
TX
PRBS
D21.5
K28.5
Serial Outputs High/Low
Test Mode Enable
Copyright © 2016, Texas Instruments Incorporated
Figure 12. Test-Mode Insertion Points
The PRBS test modes bypass the 8b/10b encoder. These test modes produce pseudo-random bit streams that
comply with the ITU-T O.150 specification. These bit streams are used with lab test equipment that can selfsynchronize to the bit pattern and therefore the initial phase of the pattern is not defined.
The sequences are defined by a recursive equation. For example, the PRBS7 sequence is defined as shown in
Equation 9.
y[n] = y[n – 6]y[n – 7]
where bit n is the XOR of bit [n – 6] and bit [n – 7] which are previously transmitted bits
(9)
Table 36. PBRS Mode Equations
PRBS TEST MODE
SEQUENCE
PRBS7
y[n] = y[n – 6]y[n – 7]
SEQUENCE LENGTH (bits)
y[n – 15]
127
PRBS15
y[n] = y[n – 14]
32767
PRBS23
y[n] = y[n – 18]y[n – 23]
8388607
The initial phase of the pattern is unique for each lane.
7.4.5.3 Ramp Test Mode
In the ramp test mode, the JESD204B link layer operates normally, but the transport layer is disabled and the
input from the formatter is ignored. After the ILA sequence, each lane transmits an identical octet stream that
increments from 0x00 to 0xFF and repeats.
7.4.5.4 Short and Long Transport Test Mode
JESD204B defines both short and long transport test modes to verify that the transport layers in the transmitter
and receiver are operating correctly. ADC12DJ3200 has three different transport layer test patterns depending on
the N' value of the specified JMODE (Table 16).
7.4.5.4.1 Short Transport Test Pattern
Short transport test patterns send a predefined octet format that repeats every frame. In the ADC12DJ32000, all
of the JMODE configurations that have an N' value of 8 or 12 use the short transport test pattern. Table 37 and
Table 38 define the short transport test patterns for N' values of 8 and 12. All applicable lanes are shown,
however only the enabled lanes (lowest indexed) for the configured JMODE are used.
Table 37. Short Transport Test Pattern for N' = 8 Modes (Length = 2 Frames)
Frame:
0
1
DA0
0x00
0xFF
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7.4.5.2 PRBS Test Modes
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Table 37. Short Transport Test Pattern for N' = 8 Modes (Length = 2 Frames) (continued)
Frame:
0
1
DA1
0x01
0xFE
DA2
0x02
0xFD
DA3
0x03
0xFC
DB0
0x00
0xFF
DB1
0x01
0xFE
DB2
0x02
0xFD
DB3
0x03
0xFC
Table 38. Short Transport Test Pattern for N' = 12 Modes (Length = 1 Frame)
Octet
Nibbl
e
DA0
0
0
1
1
2
2
3
0xF01
4
3
5
6
0xF02
4
7
8
5
9
0xF03
10
6
11
0xF04
12
7
13
14
15
0xF05
T
ADVANCE INFORMATION
DA1
0xE11
0xE12
0xE13
0xE14
0xE15
T
DA2
0xD21
0xD22
0xD23
0xD24
0xD25
T
DA3
0xC31
0xC32
0xC33
0xC34
0xC35
T
DA4
0xB41
0xB42
0xB43
0xB44
0xB45
T
DA5
0xA51
0xA52
0xA53
0xA54
0xA55
T
DA6
0x961
0x962
0x963
0x964
0x965
T
DA7
0x871
0x872
0x873
0x874
0x875
T
DB0
0xF01
0xF02
0xF03
0xF04
0xF05
T
DB1
0xE11
0xE12
0xE13
0xE14
0xE15
T
DB2
0xD21
0xD22
0xD23
0xD24
0xD25
T
DB3
0xC31
0xC32
0xC33
0xC34
0xC35
T
DB4
0xB41
0xB42
0xB43
0xB44
0xB45
T
DB5
0xA51
0xA52
0xA53
0xA54
0xA55
T
DB6
0x961
0x962
0x963
0x964
0x965
T
DB7
0x871
0x872
0x873
0x874
0x875
T
7.4.5.4.2 Long Transport Test Pattern
The long-transport test mode is used in all of the JMODE modes where N' equals 16. Patterns are generated in
accordance with the JESD204B standard and are different for each output format as defined in Table 16. The
rules for the pattern are defined below. The length of the test pattern is given by Equation 10. The long transport
test pattern is the same for link A and link B, where DAx lanes belong to link A and DBx lanes belong to link B.
Long Test Pattern Length (Frames) = K * ceil(/ (M*S+2) / K)
•
•
54
(10)
Sample Data:
– Frame 0: Each sample contains N bits, with all samples set to the converter id (CID) plus 1 (CID + 1). CID
is defined based on the converter number within the link; note that two links are used in all modes except
JMODE 15. Within a link, the converters are numbered by channel (A or B) and in-phase (I) and
quadrature-phase (Q) and reset between links. For instance, in JMODE 10, two links are used so channel
A and B data is separated into separate links and the in-phase component for each channel has CID = 0
and the quadrature-phase component has CID = 1. In JMODE 15, one link is used, so channel A and B
are within the same link and AI has CID = 0, AQ has CID = 1, BI has CID = 2, and BQ has CID = 3.
– Frame 1: Each sample contains N bits, with each sample (for each converter) set as its individual sample
ID (SID) within the frame plus 1 (SID + 1)
– Frame 2 +: Each sample contains N bits, with the data set to 2N–1 for all samples, for example if N is 15,
then 2N–1 = 16384
Control Bits (if CS > 0):
– Frame 0 to M*S–1: The control bit belonging to sample mod(i,S) of converter floor(i,S) set to "1" and all
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others set to "0". Essentially, the control bit "walks" from the lowest indexed sample to the highest indexed
sample and from the lowest indexed converter to highest indexed converter, changing position every
sample (not every frame).
– Frame M*S +: All control bits set to 0
Table 39. Example Long Transport Test Pattern - JMODE = 10, K = 10
TIME →
OCTET
#
0
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
DA0
0x0003
0x0002
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x0003
DA1
0x0004
0x0003
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x0004
DB0
0x0003
0x0002
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x0003
DB1
0x0004
0x0003
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x8000
0x0004
Frame
n
Frame
n+1
Frame
n+2
Frame
n+3
Frame
n+4
Frame
n+5
Frame
n+6
Frame
n+7
Frame
n+8
Frame
n+9
Frame
n + 10
If multiple devices are all programmed to the transport layer test mode (while JESD_EN = 0), then JESD_EN is
set to 1, and then SYSREF is used to align the LMFC of the devices, the patterns will be aligned to the SYSREF
event. For more details see JESD204B, section 5.1.6.3.
7.4.5.5 D21.5 Test Mode
In this test mode, the controller transmits a continuous stream of D21.5 characters (alternating 0s and 1s).
7.4.5.6 K28.5 Test Mode
In this test mode, the controller transmits a continuous stream of K28.5 characters.
7.4.5.7 Repeated ILA Test Mode
In this test mode, the JESD204B link layer operates normally with one exception: when the ILA sequence
completes, the sequence repeats indefinitely. Whenever the receiver issues a synchronization request, the
transmitter will initiate code group synchronization. Upon completion of code group synchronization, the
transmitter will repeatedly transmit the ILA sequence. If there is no active code group synchronization request at
the moment the transmitter enters the test mode, the transmitter will behave as if it received one.
7.4.5.8 Modified RPAT Test Mode
A 12-octet repeating pattern is defined in INCITS TR-35-2004. The purpose of this pattern is to generate white
spectral content for JESD204B compliance and jitter testing. Table 40 lists the pattern before and after 8b10b
encoding.
Table 40. Modified RPAT Pattern Values
OCTET NUMBER
Dx.y NOTATION
8-BIT INPUT TO 8b10b ENCODER
0
D30.5
0xBE
1
D23.6
0xD7
2
D3.1
0x23
3
D7.2
0x47
4
D11.3
0x6B
5
D15.4
0x8F
6
D19.5
0xB3
7
D20.0
0x14
8
D30.2
0x5E
9
D27.7
0xFB
10
D21.1
0x35
11
D25.2
0x59
20b OUTPUT OF 8b10b ENCODER
(2 CHARACTERS)
0x86BA6
0xC6475
0xD0E8D
0xCA8B4
0x7949E
0xAA665
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1
Pattern
Repeats →
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7.4.6 Calibration Modes
ADC12DJ3200 has two calibration modes available, foreground calibration and background calibration.
Foreground calibration requires the ADC to stop operating during calibration. Background calibration allows the
ADC to continue to operate while the ADC core is calibrated in the background by swapping in a different ADC
core to take its place. Additional Offset calibration features are available in both Foreground and Background
calibration modes.
7.4.6.1 Foreground Calibration Mode
Foreground calibration requires the ADC to stop converting the analog input signals during the procedure.
Foreground calibration always runs on power up and the user must wait a sufficient time before programming the
device to guarantee that the calibration is finished. Foreground calibration can be initiated by triggering the
calibration engine. The trigger source can be either the CAL_TRIG pin or CAL_SOFT_TRIG (Calibration
Software Trigger Register (address = 0x06C) [reset = 0x01]) and is chosen by setting CAL_TRIG_EN
(Calibration Pin Configuration Register (address = 0x06B) [reset = 0x00]). Foreground Offset calibration is
enabled separately via CAL_OS.
7.4.6.2 Background Calibration Mode
ADVANCE INFORMATION
Background calibration mode allows the ADC to continuously operate, with no interruption of data. This is
accomplished by activating an extra ADC core which is calibrated and then takes over operation for one of the
other previously active ADC corea. Once that ADC is taken off-line it is then calibrated and can in turn take over
to allow the next ADC to be calibrated. This process operates continuously, ensuring the ADC cores are always
providing the optimum performance regardless of system temperature changes. Due to the additional active ADC
core, Background calibration mode has increased power consumption in comparison to Foreground calibration
mode. The Low-Power Background Calibration mode discussed next provides reduced average power
consumption in comparison with the standard Background calibration mode. Background calibration can be
enabled by setting CAL_BG (Calibration Configuration 0 Register (address = 0x062) [reset = 0x01]).
CAL_TRIG_EN should be set to 0 and CAL_SOFT_TRIG should be set to 1. Background Offset calibration is
enabled separately via CAL_BGOS.
7.4.6.3 Low-Power Background Calibration Mode
A Low-Power Background calibration mode reduces the power-overhead of enabling additional ADC cores. Offline cores are powered down until ready to be calibrated and put on-line. Set LP_EN=1 to enable the Low-Power
Background calibration feature. LP_SLEEP_DLY is used to adjust the amount of time an ADC sleeps before
waking up for calibration (if LP_EN=1 and LP_TRIG=0). LP_WAKE_DLY sets how long the core is allowed to
stabilize before calibration and being put on-line. LP_TRIG is use to select between an automatic switching
process or one that is controlled by the user via CAL_SOFT_TRIG or CAL_TRIG.
7.4.7 Offset Filtering
The ADC12DJ3200 has an additional feature which can be enabled to reduce offset related interleaving spurs at
Fs/2 and Fs/4(single input mode only). Offset filtering is enabled via CAL_OSFILT. The OSFILT_BW and
OSFILT_SOAK parameters can be adjusted to tradeoff offset spur reduction with potential impact on information
in the mission mode signal being processed. These two parameters should be set to the same value under most
situations. The DC_RESTORE setting is used to either retain or filter out all DC related content in the signal.
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7.5 Programming
7.5.1 Using the Serial Interface
The serial interface is accessed using the following four pins: serial clock (SCLK), serial-data in (SDI), serial-data
out (SDO), and serial-interface chip-select (SCS). Registers access is enabled through the SCS pin.
7.5.1.1 SCS
This signal must be asserted low to access a register through the serial interface. Setup and hold times with
respect to the SCLK must be observed.
7.5.1.2 SCLK
Serial data input is accepted at the rising edge of this signal. SCLK has no minimum frequency requirement.
7.5.1.3 SDI
7.5.1.4 SDO
The SDO signal provides the output data requested by a read command. This output is high impedance during
write bus cycles and during the read bit and register address portion of read bus cycles.
Each register access consists of 24 bits, as shown in Figure 13. The first bit is high for a read and low for a write.
The next 15 bits are the address of the register that is to be written to. During write operations, the last 8 bits are
the data written to the addressed register. During read operations, the last 8 bits on SDI are ignored, and, during
this time, the SDO outputs the data from the addressed register. The serial protocol details are illustrated in
Figure 13.
Single Register Access
SCS
1
8
16
17
A0
D7
24
SCLK
Command Field
SDI
R/W A14
A13
A12
A11 A10
A9
A8
A7
A6
Data Field
A5
A4
A3
A2
A1
D6
D5
D4
D3
D2
D1
D0
Data Field
SDO
(read mode)
High Z
D7
D6
D5
D4
D3
D2
D1
D0
High Z
Figure 13. Serial Interface Protocol - Single Read / Write
7.5.1.5 Streaming Mode
The serial interface supports streaming reads and writes. In this mode, the initial 24 bits of the transaction
specifics the access type, register address, and data value as normal. Additional clock cycles of write or read
data are immediately transferred, as long as the SCS input is maintained in the asserted (logic low) state. The
register address auto increments (default) or decrements for each subsequent 8 bit transfer of the streaming
transaction. The ADDR_ASC bit (register 000h, bits 5 and 2) controls whether the address value ascends
(increments) or descends (decrements). Streaming mode can be disabled by setting the ADDR_HOLD bit (User
SPI Configuration Register (address = 0x010) [reset = 0x00]). The streaming mode transaction details are shown
in Figure 14.
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Each register access requires a specific 24-bit pattern at this input. This pattern consists of a read-and-write
(R/W) bit, register address, and register value. The data is shifted in MSB first. Setup and hold times with respect
to the SCLK must be observed (see Timing Requirements).
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Programming (continued)
Multiple Register Access
SCS
8
1
16
24
17
32
25
SCLK
Command Field
SDI
R/W A14
A13
A12
A11
A10
A9
A8
A7
Data Field (write mode)
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
Data Field (write mode)
D1
D0
D7
D6
D5
D4
D3
Data Field
High Z
SDO
(read mode)
D7
D6
D5
D4
D3
D2
D2
D1
D0
Data Field
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
High Z
Figure 14. Serial Interface Protocol - Streaming Read / Write
See the Register Maps section for detailed information regarding the registers.
ADVANCE INFORMATION
NOTE
The serial interface must not be accessed during calibration of the ADC. Accessing the
serial interface during this time impairs the performance of the device until the device is
calibrated correctly. Writing or reading the serial registers also reduces dynamic
performance of the ADC for the duration of the register access time.
7.6 Register Maps
Memory Map
Address
Reset
Acronym
Type
Register Name
0x000
0x30
CONFIG_A
R/W
0x001
Undefined
RESERVED
R
0x002
0x00
DEVICE_CONFIG
R/W
0x003
0x03
CHIP_TYPE
R
Chip Type Register
0x004-0x005
0x0020
CHIP_ID
R
Chip ID Registers
0x006
0x0A
CHIP_VERSION
R
Chip Version Register
Standard SPI-3.0 (0x000 to 0x00F)
Configuration A Register
RESERVED
Device Configuration Register
0x007-0x00B
Undefined
RESERVED
R
RESERVED
0x00C-0x00D
0x0451
VENDOR_ID
R
Vendor Identification Register
0x00E-0x00F
Undefined
RESERVED
R
RESERVED
0x010
0x00
USR0
R/W
0x011-0x01F
Undefined
RESERVED
R
0x020-0x028
Undefined
RESERVED
R
0x029
0x00
CLK_CTRL0
R/W
Clock Control Register 0
0x02A
0x20
CLK_CTRL1
R/W
Clock Control Register 1
User SPI Configuration (0x010 to 0x01F)
User SPI Configuration Register
RESERVED
Miscellaneous Analog Registers (0x020 to 0x047)
RESERVED
0x02B
Undefined
RESERVED
R
RESERVED
0x02C-0x02E
Undefined
SYSREF_POS
R
SYSREF Capture Position Register
0x02F
Undefined
RESERVED
R
RESERVED
0x030-0x031
0xA000
FS_RANGE_A
R/W
INA Full Scale Range Adjust Register
0x032-0x033
0xA000
FS_RANGE_B
R/W
INB Full Scale Range Adjust Register
0x034-0x037
Undefined
RESERVED
R
0x038
0x00
BG_BYPASS
R/W
58
RESERVED
Internal Reference Bypass Register
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Register Maps (continued)
Memory Map (continued)
Address
Reset
Acronym
Type
0x039-0x03A
Undefined
RESERVED
R
0x03B
0x00
TMSTP_CTRL
R/W
0x03C-0x047
Undefined
RESERVED
R
Register Name
RESERVED
TMSTP+/- Control Register
RESERVED
Serializer Registers (0x048 to 0x05F)
0x048
0x00
SER_PE
R/W
0x049-0x05F
Undefined
RESERVED
R
Serializer Pre-Emphasis Control Register
RESERVED
0x060
0x01
INPUT_MUX
R/W
Input Mux Control Register
0x061
0x062
0x01
CAL_EN
R/W
Calibration Enable Register
0x01
CAL_CFG0
R/W
Calibration Configuration 0 Register
0x063-0x069
Undefined
RESERVED
R
RESERVED
0x06A
Undefined
CAL_STATUS
R
Calibration Status Register
0x06B
0x00
CAL_PIN_CFG
R/W
Calibration Pin Configuration Register
0x06C
0x01
CAL_SOFT_TRIG
R/W
Calibration Software Trigger Register
0x06D
Undefined
RESERVED
R
ADVANCE INFORMATION
Calibration Registers (0x060 to 0x0FF)
RESERVED
0x06E
0x88
CAL_LP
R/W
0x06F
Undefined
RESERVED
R
Low-Power Background Calibration Register
0x070
0x00
CAL_DATA_EN
R/W
Calibration Data Enable Register
Calibration Data Register
RESERVED
0x071
Undefined
CAL_DATA
R/W
0x072-0x079
Undefined
RESERVED
R
0x07A
Undefined
GAIN_TRIM_A
R/W
Channel A Gain Trim Register
RESERVED
0x07B
Undefined
GAIN_TRIM_B
R/W
Channel B Gain Trim Register
0x07C
Undefined
BG_TRIM
R/W
Band-Gap Reference Trim Register
0x07D
Undefined
RESERVED
R
0x07E
Undefined
RTRIM_A
R/W
VINA Input Resistor Trim Register
0x07F
Undefined
RTRIM_B
R/W
VINB Input Resistor Trim Register
0x080
Undefined
TADJ_A_FG90
R/W
Timing Adjustment for A-ADC, Single Channel Mode,
Foreground Calibration Register
0x081
Undefined
TADJ_B_FG0
R/W
Timing Adjustment for B-ADC, Single Channel Mode,
Foreground Calibration Register
0x082
Undefined
TADJ_A_BG90
R/W
Timing Adjustment for A-ADC, Single Channel Mode,
Background Calibration Register
0x083
Undefined
TADJ_C_BG0
R/W
Timing Adjustment for C-ADC, Single Channel Mode,
Background Calibration Register
0x084
Undefined
TADJ_C_BG90
R/W
Timing Adjustment for C-ADC, Single Channel Mode,
Background Calibration Register
0x085
Undefined
TADJ_B_BG0
R/W
Timing Adjustment for B-ADC, Single Channel Mode,
Background Calibration Register
0x086
Undefined
TADJ_A
R/W
Timing Adjustment for A-ADC, Dual Channel Mode Register
0x087
Undefined
TADJ_CA
R/W
Timing Adjustment for C-ADC acting for A-ADC, Dual
Channel Mode Register
0x088
Undefined
TADJ_CB
R/W
Timing Adjustment for C-ADC acting for B-ADC, Dual
Channel Mode Register
RESERVED
0x089
Undefined
TADJ_B
R/W
Timing Adjustment for B-ADC, Dual Channel Mode Register
0x08A-0x08B
Undefined
OADJ_A_INA
R/W
Offset Adjustment for A-ADC and INA Register
0x08C-0x08D
Undefined
OADJ_A_INB
R/W
Offset Adjustment for A-ADC and INB Register
0x08E-0x08F
Undefined
OADJ_C_INA
R/W
Offset Adjustment for C-ADC and INA Register
0x090-0x091
Undefined
OADJ_C_INB
R/W
Offset Adjustment for C-ADC and INB Register
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Register Maps (continued)
Memory Map (continued)
Address
Reset
Acronym
Type
0x092-0x093
Undefined
OADJ_B_INA
R/W
Offset Adjustment for B-ADC and INA Register
0x094-0x095
Undefined
OADJ_B_INB
R/W
Offset Adjustment for B-ADC and INB Register
0x096
Undefined
RESERVED
R
0x097
0x00
OSFILT0
R/W
Offset Filtering Control 0
0x098
0x33
OSFILT1
R/W
Offset Filtering Control 1
0x099-0x0FF
Undefined
RESERVED
R
Register Name
RESERVED
RESERVED
ADC Bank Registers (0x100 to 0x15F)
0x100-0x101
Undefined
ADVANCE INFORMATION
RESERVED
R
0x102
0x103
RESERVED
Undefined
B0_TIME_0
R/W
Timing Adjustment for Bank 0 (0° Clock) Register
Undefined
B0_TIME_90
R/W
Timing Adjustment for Bank 0 (-90° Clock) Register
0x104-0x111
Undefined
RESERVED
R
0x112
Undefined
B1_TIME_0
R/W
Timing Adjustment for Bank 1 (0° Clock) Register
0x113
Undefined
B1_TIME_90
R/W
Timing Adjustment for Bank 1 (-90° Clock) Register
0x114-0x121
Undefined
RESERVED
R
0x122
Undefined
B2_TIME_0
R/W
Timing Adjustment for Bank 2 (0° Clock) Register
Timing Adjustment for Bank 2 (-90° Clock) Register
RESERVED
RESERVED
0x123
Undefined
B2_TIME_90
R/W
0x124-0x131
Undefined
RESERVED
R
0x132
Undefined
B3_TIME_0
R/W
Timing Adjustment for Bank 3 (0° Clock) Register
Timing Adjustment for Bank 3 (-90° Clock) Register
RESERVED
0x133
Undefined
B3_TIME_90
R/W
0x134-0x141
Undefined
RESERVED
R
0x142
Undefined
B4_TIME_0
R/W
Timing Adjustment for Bank 4 (0° Clock) Register
Timing Adjustment for Bank 4 (-90° Clock) Register
RESERVED
0x143
Undefined
B4_TIME_90
R/W
0x144-0x151
Undefined
RESERVED
R
0x152
Undefined
B5_TIME_0
R/W
Timing Adjustment for Bank 5 (0° Clock) Register
0x153
Undefined
B5_TIME_90
R/W
Timing Adjustment for Bank 5 (-90° Clock) Register
0x154-0x15F
Undefined
RESERVED
R
RESERVED
RESERVED
LSB Control Registers (0x160 to 0x1FF)
0x160
0x00
ENC_LSB
R/W
0x161-0x1FF
Undefined
RESERVED
R
LSB Control Bit Output Register
RESERVED
JESD204B Registers (0x200 to 0x20F)
0x200
0x01
JESD_EN
R/W
JESD204B Enable Register
0x201
0x02
JMODE
R/W
JESD204B Mode (JMODE) Register
0x202
0x1F
KM1
R/W
JESD204B K Parameter Register
0x203
0x01
JSYNC_N
R/W
JESD204B Manual SYNC Request Register
0x204
0x02
JCTRL
R/W
JESD204B Control Register
0x205
0x00
JTEST
R/W
JESD204B Test Pattern Control Register
0x206
0x00
DID
R/W
JESD204B DID Parameter Register
0x207
0x00
FCHAR
R/W
JESD204B Frame Character Register
0x208
Undefined
JESD_STATUS
R/W
JESD204B / System Status Register
0x209
0x00
PD_CH
R/W
JESD204B Channel Power Down
0x20A
0x00
JEXTRA_A
R/W
JESD204B Extra Lane Enable (Link A)
0x00
JEXTRA_B
R/W
JESD204B Extra Lane Enable (Link B)
Undefined
RESERVED
R
0x20B
RESERVED
Digital Down Converter Registers (0x210-0x2AF)
60
0x211
0xF2
OVR_T0
R/W
Over-range Threshold 0 Register
0x212
0xAB
OVR_T1
R/W
Over-range Threshold 1 Register
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Register Maps (continued)
Memory Map (continued)
Address
Reset
Acronym
Type
0x213
0x07
OVR_CFG
R/W
Register Name
Over-range Configuration Register
Undefined
RESERVED
R
RESERVED
0x297
Undefined
SPIN_ID
R
Spin Identification Value
0x298-0x2AF
Undefined
RESERVED
R
RESERVED
SYSREF Calibration Registers (0x2B0 to 0x2BF)
0x2B0
0x00
SRC_EN
R/W
SYSREF Calibration Enable Register
0x2B1
0x05
SRC_CFG
R/W
SYSREF Calibration Configuration Register
0x2B2-0x2B4
Undefined
SRC_STATUS
R
0x2B5-0x2B7
0x00
TAD
R/W
DEVCLK Aperture Delay Adjustment Register
0x2B8
0x00
TAD_RAMP
R/W
DEVCLK Timing Adjust Ramp Control Register
0x2B9-0x2BF
Undefined
RESERVED
R
0x2C0
Undefined
ALARM
R
0x2C1
0x1F
ALM_STATUS
R/W
Alarm Status Register
0x2C2
0x1F
ALM_MASK
R/W
Alarm Mask Register
SYSREF Calibration Status
RESERVED
Alarm Registers (0x2C0 to 0x2C2)
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Alarm Interrupt Status Register
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7.6.1 Register Descriptions
7.6.1.1 Standard SPI-3.0 (0x000 to 0x00F)
Table 41. Standard SPI-3.0 Registers
Address
Reset
Acronym
0x000
0x30
CONFIG_A
Register Name
Configuration A Register
Section
0x001
Undefined
RESERVED
RESERVED
0x002
0x00
DEVICE_CONFIG
0x003
0x03
CHIP_TYPE
0x004-0x005
0x0020
CHIP_ID
0x006
0x0A
CHIP_VERSION
0x007-0x00B
Undefined
RESERVED
RESERVED
0x00C-0x00D
0x0451
VENDOR_ID
Vendor Identification Register
0x00E-0x00F
Undefined
RESERVED
RESERVED
Device Configuration Register
Chip Type Register
Chip ID Registers
Chip Version Register
7.6.1.1.1 Configuration A Register (address = 0x000) [reset = 0x30]
ADVANCE INFORMATION
Figure 15. Configuration A Register (CONFIG_A)
7
SOFT_RESET
R/W-0
6
RESERVED
R-0
5
ADDR_ASC
R/W-1
4
SDO_ACTIVE
R-1
3
2
1
0
RESERVED
R-0000
Table 42. CONFIG_A Field Descriptions
Bit
Field
Type
Reset
Description
7
SOFT_RESET
R/W
0
Setting this bit results in full reset of the device. This bit is selfclearing. After writing this bit, the device may take up to 750 ns
to reset. During this time, do not perform any SPI transactions.
6
RESERVED
R
0
RESERVED
5
ADDR_ASC
R/W
1
0: descend – decrement address while streaming reads/writes
1: ascend – increment address while streaming reads/writes
(default)
4
SDO_ACTIVE
R
1
Always returns 1 indicating that device always uses 4-wire SPI
mode
RESERVED
R
0000
RESERVED
3-0
7.6.1.1.2 Device Configuration Register (address = 0x002) [reset = 0x00]
Figure 16. Device Configuration Register (DEVICE_CONFIG)
7
6
5
4
3
RESERVED
R-0000 00
62
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2
1
0
MODE
R/W-00
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Table 43. DEVICE_CONFIG Field Descriptions
Field
Type
Reset
Description
RESERVED
R
0000 00
RESERVED
1-0
MODE
R/W
00
SPI 3.0 specification has 1 as low power functional mode, 2 as
low power fast resume and 3 as power-down. This chip does not
support these modes.
0: Normal Operation – full power and full performance (default)
1: Normal Operation – full power and full performance (default)
2: Power Down - Everything powered down. Only use for brief
periods of time to calibrate on-chip Temperature Diode
measurement. Please see note beneath Recommended
Operating Conditions for more information.
3: Power Down - Everything powered down. Only use for brief
periods of time to calibrate on-chip Temperature Diode
measurement. Please see note beneath Recommended
Operating Conditions for more information.
ADVANCE INFORMATION
Bit
7-2
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7.6.1.1.3 Chip Type Register (address = 0x003) [reset = 0x03]
Figure 17. Chip Type Register (CHIP_TYPE)
7
6
5
4
3
2
RESERVED
R-0000
1
0
CHIP_TYPE
R-0011
Table 44. CHIP_TYPE Field Descriptions
Bit
Field
Type
Reset
Description
7-4
RESERVED
R
0000
RESERVED
3-0
CHIP_TYPE
R
0011
Always returns 0x3, indicating that the part is a high speed ADC.
7.6.1.1.4 Chip ID Register (address = 0x004 to 0x005) [reset = 0x0020]
Figure 18. Chip ID Register (CHIP_ID)
15
14
13
12
ADVANCE INFORMATION
11
10
9
8
3
2
1
0
CHIP_ID[15:8]
R-0x00h
7
6
5
4
CHIP_ID[7:0]
R-0x20h
Table 45. CHIP_ID Field Descriptions
Bit
15-0
Field
Type
Reset
Description
CHIP_ID
R
0x0020h
Always returns 0x0020 to indicate that this chip is part of the
family
7.6.1.1.5 Chip Version Register (address = 0x006) [reset = 0x01]
Figure 19. Chip Version Register (CHIP_VERSION)
7
6
5
4
3
CHIP_VERSION
R-0000 1010
2
1
0
Table 46. CHIP_VERSION Field Descriptions
64
Bit
Field
Type
Reset
7-0
CHIP_VERSION
R
0000 1010 Chip version, returns 0x0A
Description
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7.6.1.1.6 Vendor Identification Register (address = 0x00C to 0x00D) [reset = 0x0451]
Figure 20. Vendor Identification Register (VENDOR_ID)
15
14
13
12
11
VENDOR_ID[15:8]
R-0x04h
10
9
8
7
6
5
4
3
VENDOR_ID[7:0]
R-0x51h
2
1
0
Table 47. VENDOR_ID Field Descriptions
Bit
15-0
Field
Type
Reset
Description
VENDOR_ID
R
0x0451h
Always returns 0x0451 (TI Vendor ID)
7.6.1.2 User SPI Configuration (0x010 to 0x01F)
Address
Reset
Acronym
0x010
0x00
USR0
0x011-0x01F
Undefined
RESERVED
Register Name
Section
User SPI Configuration Register
RESERVED
7.6.1.2.1 User SPI Configuration Register (address = 0x010) [reset = 0x00]
Figure 21. User SPI Configuration Register (USR0)
7
6
5
4
RESERVED
R-0000 000
3
2
1
0
ADDR_HOLD
R/W-0
Table 49. USR0 Field Descriptions
Bit
Field
Type
Reset
7-1
RESERVED
R/W
0000 000
ADDR_HOLD
R/W
0
0
Description
0: Use ADDR_ASC bit to define what happens to address during
streaming (default).
1: Address stays static throughout streaming operation. Useful
for reading/writing calibration vector information at CAL_DATA
register.
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ADVANCE INFORMATION
Table 48. User SPI Configuration Registers
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7.6.1.3 Miscellaneous Analog Registers (0x020 to 0x047)
Table 50. Miscellaneous Analog Registers
Address
Reset
Acronym
0x020-0x028
Undefined
RESERVED
Register Name
RESERVED
Section
0x029
0x00
CLK_CTRL0
Clock Control Register 0
0x02A
0x20
CLK_CTRL1
Clock Control Register 1
0x02B
Undefined
RESERVED
RESERVED
0x02C-0x02E
Undefined
SYSREF_POS
0x02F
Undefined
RESERVED
0x030-0x031
0xA000
FS_RANGE_A
INA Full Scale Range Adjust Register
0x032-0x033
0xA000
FS_RANGE_B
INB Full Scale Range Adjust Register
0x034-0x037
Undefined
RESERVED
RESERVED
0x038
0x00
BG_BYPASS
Internal Reference Bypass Register
0x039-0x03A
Undefined
RESERVED
RESERVED
0x03B
0x00
SYNC_CTRL
TMSTP+/- Control Register
0x03C-0x047
Undefined
RESERVED
RESERVED
SYSREF Capture Position Register
RESERVED
ADVANCE INFORMATION
7.6.1.3.1 Clock Control Register 0 (address = 0x029) [reset = 0x00]
Figure 22. Clock Control Register 0 (CLK_CTRL0)
7
RESERVED
R/W-0
6
SYSREF_PRO
C_EN
R/W-0
5
SYSREF_REC
V_EN
R/W-0
4
SYSREF_ZOO
M
R/W-0
3
2
1
0
SYSREF_SEL
R/W-0000
Table 51. CLK_CTRL0 Field Descriptions
Bit
Field
Type
Reset
Description
7
RESERVED
R/W
0
RESERVED
6
SYSREF_PROC_EN
R/W
0
Enable the SYSREF processor. This must be set to allow the
part to process SYSREF events. SYSREF_RECV_EN must be
set before setting SYSREF_PROC_EN.
5
SYSREF_RECV_EN
R/W
0
Set this bit to enable the SYSREF receiver circuit
4
SYSREF_ZOOM
R/W
0
Set this bit to “zoom” in the SYSREF strobe status (impacts
SYSREF_POS)
SYSREF_SEL
R/W
0000
Set this field to select which SYSREF delay to use. Set this
based on the results returned by SYSREF_POS. You must set
this to 0 to use SYSREF Calibration.
3-0
7.6.1.3.2 Clock Control Register 1 (address = 0x02A) [reset = 0x00]
Figure 23. Clock Control Register 1 (CLK_CTRL1)
7
6
5
RESERVED
4
3
R/W-0010 0
2
1
0
DEVCLK_LVPE SYSREF_LVPE SYSREF_INVE
CL_EN
CL_EN
RTED
R/W-0
R/W-0
R/W-0
Table 52. CLK_CTRL1 Field Descriptions
66
Bit
Field
Type
Reset
Description
7-3
RESERVED
R/W
0010 0
RESERVED
2
DEVCLK_LVPECL_EN
R/W
0
Activate low voltage PECL mode for DEVCLK
1
SYSREF_LVPECL_EN
R/W
0
Activate low voltage PECL mode for SYSREF
0
SYSREF_INVERTED
R/W
0
Inverts the SYSREF signal used for alignment
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7.6.1.3.3 SYSREF Capture Position Register (address = 0x02C-0x02E) [reset = Undefined]
Figure 24. SYSREF Capture Position Register (SYSREF_POS)
23
22
21
15
14
13
7
6
5
20
19
SYSREF_POS[23:16]
R-Undefined
12
11
SYSREF_POS[15:8]
R-Undefined
4
3
SYSREF_POS[7:0]
R-Undefined
18
17
16
10
9
8
2
1
0
Bit
23-0
Field
Type
Reset
Description
SYSREF_POS
R
Undefined
Returns a 24-bit status value that indicates the position of the
SYSREF edge with respect to DEVCLK. Use this to program
SYSREF_SEL.
ADVANCE INFORMATION
Table 53. SYSREF_POS Field Descriptions
7.6.1.3.4 INA Full Scale Range Adjust Register (address = 0x030-0x031) [reset = 0xA4C4]
Figure 25. INA Full Scale Range Adjust Register (FS_RANGE_A)
15
14
13
7
6
5
12
11
FS_RANGE_A[15:8]
R/W-0xA0h
4
3
FS_RANGE_A[7:0]
R/W-0x00h
10
9
8
2
1
0
Table 54. FS_RANGE_A Field Descriptions
Bit
15-0
Field
Type
Reset
Description
FS_RANGE_A
R/W
0xA000h
Enables adjustment of the analog full scale range for INA
0x0000: Settings below 0x2000 may result in degraded device
performance.
0x2000: 500 mVpp - Recommended minimum setting.
0xA000: 800 mVpp (default)
0xFFFF: 1000 mVpp
7.6.1.3.5 INB Full Scale Range Adjust Register (address = 0x032-0x033) [reset = 0xA4C4]
Figure 26. INB Full Scale Range Adjust Register (FS_RANGE_B)
15
14
13
7
6
5
12
11
FS_RANGE_B[15:8]
R/W-0xA0
4
3
FS_RANGE_B[7:0]
R/W-0x00
10
9
8
2
1
0
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Table 55. FS_RANGE_B Field Descriptions
Bit
15-0
Field
Type
Reset
Description
FS_RANGE_B
R/W
0xA000h
Enables adjustment of the analog full scale range for INB
0x0000: Settings below 0x2000 may result in degraded device
performance.
0x2000: 500 mVpp - Recommended minimum setting.
0xA000: 800 mVpp (default)
0xFFFF: 1000 mVpp
ADVANCE INFORMATION
68
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7.6.1.3.6 Internal Reference Bypass Register (address = 0x038) [reset = 0x00]
Figure 27. Internal Reference Bypass Register (BG_BYPASS)
7
6
5
4
RESERVED
R/W-0000 000
3
2
1
0
BG_BYPASS
R/W-0
Table 56. BG_BYPASS Field Descriptions
Bit
Field
Type
Reset
Description
7-1
RESERVED
R/W
0000 000
RESERVED
0
BG_BYPASS
R/W
0
When set, VA11 is used as the voltage reference instead of the
internal reference
7.6.1.3.7 TMSTP+/- Control Register (address = 0x03B) [reset = 0x00]
7
6
5
4
3
2
1
TMSTP_LVPE
CL_EN
R/W-0
RESERVED
R/W-0000 00
0
TMSTP_RECV
_EN
R/W-0
Table 57. TMSTP_CTRL Field Descriptions
Bit
Field
Type
Reset
Description
7-2
RESERVED
R/W
0000 00
RESERVED
1
TMSTP_LVPECL_EN
R/W
0
When set, activates the low voltage PECL mode for the
differential TMSTP+/- input
0
TMSTP_RECV_EN
R/W
0
Enables the differential TMSTP+/- input
7.6.1.4 Serializer Registers (0x048 to 0x05F)
Table 58. Serializer Registers
Address
Reset
Acronym
Register Name
0x048
0x00
SER_PE
Serializer Pre-Emphasis Control Register
Section
0x049-0x05F
Undefined
RESERVED
RESERVED
7.6.1.4.1 Serializer Pre-Emphasis Control Register (address = 0x048) [reset = 0x00]
Figure 29. Serializer Pre-Emphasis Control Register (SER_PE)
7
6
5
4
3
RESERVED
R/W-0000
2
1
0
SER_PE
R/W-0000
Table 59. SER_PE Field Descriptions
Bit
Field
Type
Reset
Description
7-4
RESERVED
R/W
0000
RESERVED
3-0
SER_PE
R/W
0000
Sets the pre-emphasis for the serial lanes to compensate for the
low-pass response of the PCB trace. This is a global setting that
affects all 16 lanes.
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Figure 28. TMSTP+/- Control Register (TMSTP_CTRL)
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7.6.1.5 Calibration Registers (0x060 to 0x0FF)
Table 60. Calibration Registers
Reset
Acronym
0x060
0x01
INPUT_MUX
Input Mux Control Register
0x061
0x01
CAL_EN
Calibration Enable Register
0x062
0x01
CAL_CFG0
Calibration Configuration 0 Register
0x063-0x069
Undefined
RESERVED
RESERVED
0x06A
Undefined
CAL_STATUS
Calibration Status Register
0x06B
0x00
CAL_PIN_CFG
Calibration Pin Configuration Register
0x06C
0x01
CAL_SOFT_TRIG
Calibration Software Trigger Register
0x06D-0x06D
Undefined
RESERVED
0x06E
0x88
CAL_LP
0x06F
Undefined
RESERVED
0x070
0x00
CAL_DATA_EN
0x071
Undefined
CAL_DATA
Calibration Data Register
0x072-0x079
Undefined
RESERVED
RESERVED
0x07A
Undefined
GAIN_TRIM_A
Channel A Gain Trim Register
0x07B
Undefined
GAIN_TRIM_B
Channel B Gain Trim Register
0x07C
Undefined
BG_TRIM
0x07D
Undefined
RESERVED
0x07E
Undefined
RTRIM_A
VINA Input Resistor Trim Register
0x07F
Undefined
RTRIM_B
VINB Input Resistor Trim Register
0x080
Undefined
TADJ_A_FG90
Timing Adjustment for A-ADC, Single Channel
Mode, Foreground Calibration Register
0x081
Undefined
TADJ_B_FG0
Timing Adjustment for B-ADC, Single Channel
Mode, Foreground Calibration Register
0x082
Undefined
TADJ_A_BG90
Timing Adjustment for A-ADC, Single Channel
Mode, Background Calibration Register
0x083
Undefined
TADJ_C_BG0
Timing Adjustment for C-ADC, Single Channel
Mode, Background Calibration Register
0x084
Undefined
TADJ_C_BG90
Timing Adjustment for C-ADC, Single Channel
Mode, Background Calibration Register
0x085
Undefined
TADJ_B_BG0
Timing Adjustment for B-ADC, Single Channel
Mode, Background Calibration Register
0x086
Undefined
TADJ_A
0x087
Undefined
TADJ_CA
Timing Adjustment for C-ADC acting for AADC, Dual Channel Mode Register
0x088
Undefined
TADJ_CB
Timing Adjustment for C-ADC acting for BADC, Dual Channel Mode Register
0x089
Undefined
TADJ_B
0x08A-0x08B
Undefined
OADJ_A_INA
Offset Adjustment for A-ADC and INA
Register
0x08C-0x08D
Undefined
OADJ_A_INB
Offset Adjustment for A-ADC and INB
Register
0x08E-0x08F
Undefined
OADJ_C_INA
Offset Adjustment for C-ADC and INA
Register
0x090-0x091
Undefined
OADJ_C_INB
Offset Adjustment for C-ADC and INB
Register
0x092-0x093
Undefined
OADJ_B_INA
Offset Adjustment for B-ADC and INA
Register
0x094-0x095
Undefined
OADJ_B_INB
Offset Adjustment for B-ADC and INB
Register
0x096
Undefined
RESERVED
RESERVED
0x097
0x00
0SFILT0
Offset Filtering Control 0
0x098
0x33
OSFILT1
Offset Filtering Control 1
0x099-0x0FF
Undefined
RESERVED
ADVANCE INFORMATION
Address
70
Register Name
Section
RESERVED
Low-Power Background Calibration Register
RESERVED
Calibration Data Enable Register
Band-Gap Reference Trim Register
RESERVED
Timing Adjustment for A-ADC, Dual Channel
Mode Register
Timing Adjustment for B-ADC, Dual Channel
Mode Register
RESERVED
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7.6.1.5.1 Input Mux Control Register (address = 0x060) [reset = 0x01]
Figure 30. Input Mux Control Register (INPUT_MUX)
7
6
RESERVED
R/W-000
5
4
DUAL_INPUT
R/W-0
3
2
1
RESERVED
R/W-00
0
SINGLE_INPUT
R/W-01
Bit
Field
Type
Reset
Description
7-5
RESERVED
R/W
000
RESERVED
DUAL_INPUT
R/W
0
Select inputs for dual channel modes. If JMODE is selecting a
single channel mode, this register has no effect.
0: A channel samples INA, B channel samples INB (no swap)
(default)
1: A channel samples INB, B channel samples INA (swap)
3-2
RESERVED
R/W
00
RESERVED
1-0
SINGLE_INPUT
R/W
01
Defines which input is sampled in single channel mode. If
JMODE is not selecting a single channel mode, this register has
no effect.
0: RESERVED
1: INA is used (default)
2: INB is used
3: RESERVED
4
7.6.1.5.2 Calibration Enable Register (address = 0x061) [reset = 0x01]
Figure 31. Calibration Enable Register (CAL_EN)
7
6
5
4
RESERVED
R/W-0000 000
3
2
1
0
CAL_EN
R/W-1
Table 62. CAL_EN Field Descriptions
Bit
Field
Type
Reset
Description
7-1
RESERVED
R/W
0000 000
RESERVED
CAL_EN
R/W
1
Calibration Enable. Set high to run calibration. Set low to hold
calibration in reset to program new calibration settings. Clearing
CAL_EN also resets the clock dividers that clock the digital block
and JESD204B interface.
Some calibration registers require clearing CAL_EN before
making any changes. All registers with this requirement contain
a note in their descriptions. After changing the registers, set
CAL_EN to re-run calibration with the new settings.
Always set CAL_EN before setting JESD_EN. Always clear
JESD_EN before clearing CAL_EN.
0
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Table 61. INPUT_MUX Field Descriptions
ADC12DJ3200
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7.6.1.5.3 Calibration Configuration 0 Register (address = 0x062) [reset = 0x01]
Only change this register while CAL_EN is 0.
Figure 32. Calibration Configuration 0 Register (CAL_CFG0)
7
6
RESERVED
R/W-000
5
4
CAL_OSFILT
R/W-0
3
CAL_BGOS
R/W-0
2
CAL_OS
R/W-0
1
CAL_BG
R/W-0
0
CAL_FG
R/W-1
Table 63. CAL_CFG0 Field Descriptions
ADVANCE INFORMATION
Bit
Field
Type
Reset
Description
7-5
RESERVED
R/W
0000
RESERVED
4
CAL_OSFILT
R/W
0
Enable offset filtering by setting this bit high.
3
CAL_BGOS
R/W
0
0 : Disable background offset calibration (default)
1: Enable background offset calibration (requires CAL_BG to be
set).
2
CAL_OS
R/W
0
0 : Disable foreground offset calibration (default)
1: Enable foreground offset calibration (requires CAL_FG to be
set)
1
CAL_BG
R/W
0
0 : Disable background calibration (default)
1: Enable background calibration
0
CAL_FG
R/W
1
0 : Reset calibration values, skip foreground calibration
1: Reset calibration values, then run foreground calibration
(default)
7.6.1.5.4 Calibration Status Register (address = 0x06A) [reset = Undefined]
Figure 33. Calibration Status Register (CAL_STATUS)
7
6
5
4
3
2
RESERVED
CAL_ERROR
R
R
1
CAL_STOPPE
D
R
0
FG_DONE
R
Table 64. CAL_STATUS Field Descriptions
72
Bit
Field
Type
Reset
Description
7-4
RESERVED
R
RESERVED
3-2
CAL_ERROR
R
If CAL_ERROR is any value that is not 11, then an error has
occurred during calibration
1
CAL_STOPPED
R
This bit will return a 1 when background calibration has
successfully stopped at the requested phase. This bit will return
a 0 once calibration has started operating again. If background
calibration is disabled, this bit will be set once foreground
calibration is completed or skipped.
0
FG_DONE
R
This bit is set high when foreground calibration has completed
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7.6.1.5.5 Calibration Pin Configuration Register (address = 0x06B) [reset = 0x00]
Figure 34. Calibration Pin Configuration Register (CAL_PIN_CFG)
7
6
5
RESERVED
R/W-0000 0
4
3
2
1
CAL_STATUS_SEL
R/W-00
0
CAL_TRIG_EN
R/W-0
Bit
Field
Type
Reset
Description
7-3
RESERVED
R/W
0000 0
RESERVED
2-1
CAL_STATUS_SEL
R/W
00
0: CALSTAT output pin matches FG_DONE
1: RESERVED
2: CALSTAT output pin matches ALARM
3: CALSTAT output pin is always low.
CAL_TRIG_EN
R/W
0
Choose hardware or software trigger source
0: Use the CAL_SOFT_TRIG register for the calibration trigger.
The CAL_TRIG input is disabled (ignored).
1: Use the CAL_TRIG input for the calibration trigger. The
CAL_SOFT_TRIG register is ignored.
0
7.6.1.5.6 Calibration Software Trigger Register (address = 0x06C) [reset = 0x01]
Figure 35. Calibration Software Trigger Register (CAL_SOFT_TRIG)
7
6
5
4
RESERVED
3
2
1
R/W-0000 000
0
CAL_SOFT_TR
IG
R/W-1
Table 66. CAL_SOFT_TRIG Field Descriptions
Bit
Field
Type
Reset
Description
7-1
RESERVED
R/W
0000 000
RESERVED
CAL_SOFT_TRIG
R/W
1
CAL_SOFT_TRIG is a software bit to provide the functionality of
the CAL_TRIG input. Program CAL_TRIG_EN=0 to use
CAL_SOFT_TRIG for the calibration trigger. Note: If no
calibration trigger is needed, leave CAL_TRIG_EN=0 and
CAL_SOFT_TRIG=1 (trigger set high).
0
7.6.1.5.7 Low-Power Background Calibration Register (address = 0x06E) [reset = 0x88]
Figure 36. Low-Power Background Calibration Register (CAL_LP)
7
6
LP_SLEEP_DLY
R/W-010
5
4
3
LP_WAKE_DLY
R/W-01
2
RESERVED
R/W-0
1
LP_TRIG
R/W-0
0
LP_EN
R/W-0
Table 67. CAL_LP Field Descriptions
Bit
Field
Type
Reset
Description
7-5
LP_SLEEP_DLY
R/W
010
Adjust how long an ADC sleeps before waking up for calibration
(only applys when LP_EN=1 and LP_TRIG=0).
4-3
LP_WAKE_DLY
R/W
01
Adjust how much time is given up for settling before calibrating
an ADC after it wakes up (only applies when LP_EN=1)
2
RESERVED
R/W
0
RESERVED
1
LP_TRIG
R/W
0
0: ADC sleep duration is set by LP_SLEEP_DLY (autonomous
mode).
1: ADCs sleep until woken by a trigger. An ADC is awoken when
the calibration trigger (CAL_SOFT_TRIG bit or CAL_TRIG input)
is low.
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Table 65. CAL_PIN_CFG Field Descriptions
ADC12DJ3200
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Table 67. CAL_LP Field Descriptions (continued)
Bit
0
Field
Type
Reset
Description
LP_EN
R/W
0
0: Disable low-power background calibration (default)
1: Enable low-power background calibration (only applies when
CAL_BG=1).
7.6.1.5.8 Calibration Data Enable Register (address = 0x070) [reset = 0x00]
Figure 37. Register (CAL_DATA_EN)
7
6
5
4
RESERVED
R/W-0000 000
3
2
1
0
CAL_DATA_EN
R/W-0
Table 68. CAL_DATA_EN Field Descriptions
Bit
Field
Type
Reset
Description
7-1
RESERVED
R/W
0000 000
RESERVED
CAL_DATA_EN
R/W
0
Set this bit to enable the CAL_DATA register to enable reading
and writing of calibration data. See Calibration Data Read/Write
for more information.
0
ADVANCE INFORMATION
74
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7.6.1.5.9 Calibration Data Register (address = 0x071) [reset = Undefined]
Figure 38. Calibration Data Register (CAL_DATA)
7
6
5
4
3
2
1
0
CAL_DATA
R/W
Bit
Field
Type
Reset
Description
7-0
CAL_DATA
R/W
Undefined
After setting CAL_DATA_EN, repeated reads of this register will
return all the calibration values for the ADCs. Repeated writes of
this register will input all the calibration values for the ADCs. To
read the calibration data, read the register 673 times. To write
the vector, write the register 673 times with previously stored
calibration data.
To speed up the read/write operation, set ADDR_HOLD=1 and
use streaming read or write process.
IMPORTANT: Accessing the CAL_DATA register while
CAL_STOPPED=0 will corrupt the calibration. Also, stopping the
process before reading or writing 673 times will leave the
calibration data in an invalid state.
7.6.1.5.10 Channel A Gain Trim Register (address = 0x07A) [reset = Undefined]
Figure 39. Channel A Gain Trim Register (GAIN_TRIM_A)
7
6
5
4
3
2
1
0
GAIN_TRIM_A
R/W
Table 70. GAIN_TRIM_A Field Descriptions
Bit
Field
Type
Reset
Description
7-0
GAIN_TRIM_A
R/W
Undefined
This register enables gain trim of channel A. After reset, the
factory trimmed value can be read and adjusted as required.
7.6.1.5.11 Channel B Gain Trim Register (address = 0x07B) [reset = Undefined]
Figure 40. Channel B Gain Trim Register (GAIN_TRIM_B)
7
6
5
4
3
2
1
0
GAIN_TRIM_B
R/W
Table 71. GAIN_TRIM_B Field Descriptions
Bit
Field
Type
Reset
Description
7-0
GAIN_TRIM_B
R/W
Undefined
This register enables gain trim of channel B. After reset, the
factory trimmed value can be read and adjusted as required.
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Table 69. CAL_DATA Field Descriptions
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7.6.1.5.12 Band-Gap Reference Trim Register (address = 0x07C) [reset = Undefined]
Figure 41. Band-Gap Reference Trim Register (BG_TRIM)
7
6
5
4
3
2
RESERVED
R/W-0000
1
0
BG_TRIM
R/W
Table 72. BG_TRIM Field Descriptions
Bit
Field
Type
Reset
Description
7-4
RESERVED
R/W
0000
RESERVED
3-0
BG_TRIM
R/W
Undefined
This register enables trim of the internal band-gap reference.
After reset, the factory trimmed value can be read and adjusted
as required.
7.6.1.5.13 VINA Input Resistor Trim Register (address = 0x07E) [reset = Undefined]
Figure 42. VINA Input Resistor Trim Register (RTRIM_A)
ADVANCE INFORMATION
7
6
5
4
3
2
1
0
RTRIM
R/W
Table 73. RTRIM_A Field Descriptions
Bit
Field
Type
Reset
Description
7-0
RTRIM_A
R/W
Undefined
This register controls VINA ADC input termination trim. After
reset, the factory trimmed value can be read and adjusted as
required.
7.6.1.5.14 VINB Input Resistor Trim Register (address = 0x07F) [reset = Undefined]
Figure 43. VINB Input Resistor Trim Register (RTRIM_B)
7
6
5
4
3
2
1
0
RTRIM
R/W
Table 74. RTRIM_B Field Descriptions
Bit
Field
Type
Reset
Description
7-0
RTRIM_B
R/W
Undefined
This register controls VINB ADC input termination trim. After
reset, the factory trimmed value can be read and adjusted as
required.
7.6.1.5.15 Timing Adjust for A-ADC, Single Channel Mode, Foreground Calibration Register (address = 0x080) [reset
= Undefined]
Figure 44. Register (TADJ_A_FG90)
7
6
5
4
3
2
1
0
TADJ_A_FG90
R/W
76
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Table 75. TADJ_A_FG90 Field Descriptions
Bit
Field
Type
Reset
Description
7-0
TADJ_A_FG90
R/W
Undefined
This register (and other TADJ* registers that follow it) are used
to adjust the sampling instant of each ADC core. Different TADJ
registers apply to different ADCs under different modes or
phases of background calibration. After reset, the factory
trimmed value can be read and adjusted as required.
7.6.1.5.16 Timing Adjust for B-ADC, Single Channel Mode, Foreground Calibration Register (address = 0x081) [reset
= Undefined]
Figure 45. Register (TADJ_B_FG0)
7
6
5
4
3
2
1
0
TADJ_B_FG0
R/W
Bit
Field
Type
Reset
Description
7-0
TADJ_B_FG0
R/W
Undefined
This register (and other TADJ* registers that follow it) are used
to adjust the sampling instant of each ADC core. Different TADJ
registers apply to different ADCs under different modes or
phases of background calibration. After reset, the factory
trimmed value can be read and adjusted as required.
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Table 76. TADJ_B_FG0 Field Descriptions
ADC12DJ3200
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7.6.1.5.17 Timing Adjust for A-ADC, Single Channel Mode, Background Calibration Register (address = 0x082)
[reset = Undefined]
Figure 46. Register (TADJ_A_BG90)
7
6
5
4
3
2
1
0
TADJ_A_BG90
R/W
Table 77. TADJ_B_FG0 Field Descriptions
Bit
Field
Type
Reset
Description
7-0
TADJ_A_BG90
R/W
Undefined
This register (and other TADJ* registers that follow it) are used
to adjust the sampling instant of each ADC core. Different TADJ
registers apply to different ADCs under different modes or
phases of background calibration. After reset, the factory
trimmed value can be read and adjusted as required.
7.6.1.5.18 Timing Adjust for C-ADC, Single Channel Mode, Background Calibration Register (address = 0x083)
[reset = Undefined]
ADVANCE INFORMATION
Figure 47. Register (TADJ_C_BG0)
7
6
5
4
3
2
1
0
TADJ_C_BG0
R/W
Table 78. TADJ_B_FG0 Field Descriptions
Bit
Field
Type
Reset
Description
7-0
TADJ_C_BG0
R/W
Undefined
This register (and other TADJ* registers that follow it) are used
to adjust the sampling instant of each ADC core. Different TADJ
registers apply to different ADCs under different modes or
phases of background calibration. After reset, the factory
trimmed value can be read and adjusted as required.
7.6.1.5.19 Timing Adjust for C-ADC, Single Channel Mode, Background Calibration Register (address = 0x084)
[reset = Undefined]
Figure 48. Register (TADJ_C_BG90)
7
6
5
4
3
2
1
0
TADJ_C_BG90
R/W
Table 79. TADJ_B_FG0 Field Descriptions
78
Bit
Field
Type
Reset
Description
7-0
TADJ_C_BG90
R/W
Undefined
This register (and other TADJ* registers that follow it) are used
to adjust the sampling instant of each ADC core. Different TADJ
registers apply to different ADCs under different modes or
phases of background calibration. After reset, the factory
trimmed value can be read and adjusted as required.
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7.6.1.5.20 Timing Adjust for B-ADC, Single Channel Mode, Background Calibration Register (address = 0x085)
[reset = Undefined]
Figure 49. Register (TADJ_B_BG0)
7
6
5
4
3
2
1
0
TADJ_B_BG0
R/W
Table 80. TADJ_B_FG0 Field Descriptions
Bit
Field
Type
Reset
Description
7-0
TADJ_B_BG0
R/W
Undefined
This register (and other TADJ* registers that follow it) are used
to adjust the sampling instant of each ADC core. Different TADJ
registers apply to different ADCs under different modes or
phases of background calibration. After reset, the factory
trimmed value can be read and adjusted as required.
7.6.1.5.21 Timing Adjust for A-ADC, Dual Channel Mode Register (address = 0x086) [reset = Undefined]
7
6
5
4
3
2
1
0
TADJ_A
R/W
Table 81. TADJ_A Field Descriptions
Bit
Field
Type
Reset
Description
7-0
TADJ_A
R/W
Undefined
This register (and other TADJ* registers that follow it) are used
to adjust the sampling instant of each ADC core. Different TADJ
registers apply to different ADCs under different modes or
phases of background calibration. After reset, the factory
trimmed value can be read and adjusted as required.
7.6.1.5.22 Timing Adjust for C-ADC acting for A-ADC, Dual Channel Mode Register (address = 0x087) [reset =
Undefined]
Figure 51. Register (TADJ_CA)
7
6
5
4
3
2
1
0
TADJ_CA
R/W
Table 82. TADJ_CA Field Descriptions
Bit
Field
Type
Reset
Description
7-0
TADJ_CA
R/W
Undefined
This register (and other TADJ* registers that follow it) are used
to adjust the sampling instant of each ADC core. Different TADJ
registers apply to different ADCs under different modes or
phases of background calibration. After reset, the factory
trimmed value can be read and adjusted as required.
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Figure 50. Register (TADJ_A)
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7.6.1.5.23 Timing Adjust for C-ADC acting for B-ADC, Dual Channel Mode Register (address = 0x088) [reset =
Undefined]
Figure 52. Register (TADJ_CB)
7
6
5
4
3
2
1
0
TADJ_CB
R/W
Table 83. TADJ_CB Field Descriptions
Bit
Field
Type
Reset
Description
7-0
TADJ_CB
R/W
Undefined
This register (and other TADJ* registers that follow it) are used
to adjust the sampling instant of each ADC core. Different TADJ
registers apply to different ADCs under different modes or
phases of background calibration. After reset, the factory
trimmed value can be read and adjusted as required.
7.6.1.5.24 Timing Adjust for B-ADC, Dual Channel Mode Register (address = 0x089) [reset = Undefined]
Figure 53. Register (TADJ_B)
ADVANCE INFORMATION
7
6
5
4
3
2
1
0
TADJ_B
R/W
Table 84. TADJ_B Field Descriptions
Bit
Field
Type
Reset
Description
7-0
TADJ_B
R/W
Undefined
This register (and other TADJ* registers that follow it) are used
to adjust the sampling instant of each ADC core. Different TADJ
registers apply to different ADCs under different modes or
phases of background calibration. After reset, the factory
trimmed value can be read and adjusted as required.
7.6.1.5.25 Offset Adjustment for A-ADC and INA Register (address = 0x08A-0x08B) [reset = Undefined]
Figure 54. Register (OADJ_A_INA)
15
14
13
12
11
5
4
3
OADJ_A_INA[7:0]
R/W
RESERVED
R/W-0000
7
6
10
9
OADJ_A_INA[11:8]
R/W
2
1
8
0
Table 85. OADJ_A_INA Field Descriptions
Bit
80
Field
Type
Reset
Description
15-12
RESERVED
R/W
0000
RESERVED
11-0
OADJ_A_INA
R/W
Undefined
Offset adjustment value for ADC0 (A-ADC) applied when ADC0
samples INA. The format is unsigned. After reset, the factory
trimmed value can be read and adjusted as required.
Important notes:
•
Never write OADJ* registers while foreground calibration is
underway
•
Never write OADJ* registers if CAL_BG and CAL_BGOS
are set
•
If CAL_OS=1 and CAL_BGOS=0, only read OADJ* registers
if FG_DONE=1
•
If CAL_BG=1 and CAL_BGOS=1, only read OADJ* register
if CAL_STOPPED=1
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7.6.1.5.26 Offset Adjustment for A-ADC and INB Register (address = 0x08C-0x08D) [reset = Undefined]
Figure 55. Register (OADJ_A_INB)
15
14
13
12
11
5
4
3
OADJ_A_INB[7:0]
R/W
RESERVED
R/W-0000
7
6
10
9
OADJ_A_INB[11:8]
R/W
2
1
8
0
Field
Type
Reset
Description
15-12
Bit
RESERVED
R/W
0000
RESERVED
11-0
OADJ_A_INB
R/W
Undefined
Offset adjustment value for ADC0 (A-ADC) applied when ADC0
samples INB. The format is unsigned. After reset, the factory
trimmed value can be read and adjusted as required.
Important notes:
•
Never write OADJ* registers while foreground calibration is
underway
•
Never write OADJ* registers if CAL_BG and CAL_BGOS
are set
•
If CAL_OS=1 and CAL_BGOS=0, only read OADJ* registers
if FG_DONE=1
•
If CAL_BG=1 and CAL_BGOS=1, only read OADJ* register
if CAL_STOPPED=1
7.6.1.5.27 Offset Adjustment for C-ADC and INA Register (address = 0x08E-0x08F) [reset = Undefined]
Figure 56. Register (OADJ_C_INA)
15
14
13
12
11
5
4
3
OADJ_C_INA[7:0]
R/W
RESERVED
R/W-0000
7
6
10
9
OADJ_C_INA[11:8]
R/W
2
1
8
0
Table 87. OADJ_C_INA Field Descriptions
Bit
Field
Type
Reset
Description
15-12
RESERVED
R/W
0000
RESERVED
11-0
OADJ_C_INA
R/W
Undefined
Offset adjustment value for ADC1 (A-ADC) applied when ADC1
samples INA. The format is unsigned. After reset, the factory
trimmed value can be read and adjusted as required.
Important notes:
•
Never write OADJ* registers while foreground calibration is
underway
•
Never write OADJ* registers if CAL_BG and CAL_BGOS
are set
•
If CAL_OS=1 and CAL_BGOS=0, only read OADJ* registers
if FG_DONE=1
•
If CAL_BG=1 and CAL_BGOS=1, only read OADJ* register
if CAL_STOPPED=1
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Table 86. OADJ_A_INB Field Descriptions
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7.6.1.5.28 Offset Adjustment for C-ADC and INB Register (address = 0x090-0x091) [reset = Undefined]
Figure 57. Register (OADJ_C_INB)
15
14
13
12
11
5
4
3
OADJ_C_INB[7:0]
R/W
RESERVED
R/W-0000
7
6
10
9
OADJ_C_INB[11:8]
R/W
2
1
8
0
Table 88. OADJ_C_INB Field Descriptions
Bit
ADVANCE INFORMATION
Field
Type
Reset
Description
15-12
RESERVED
R/W
0000
RESERVED
11-0
OADJ_C_INB
R/W
Undefined
Offset adjustment value for ADC1 (A-ADC) applied when ADC1
samples INB. The format is unsigned. After reset, the factory
trimmed value can be read and adjusted as required.
Important notes:
•
Never write OADJ* registers while foreground calibration is
underway
•
Never write OADJ* registers if CAL_BG and CAL_BGOS
are set
•
If CAL_OS=1 and CAL_BGOS=0, only read OADJ* registers
if FG_DONE=1
•
If CAL_BG=1 and CAL_BGOS=1, only read OADJ* register
if CAL_STOPPED=1
7.6.1.5.29 Offset Adjustment for B-ADC and INA Register (address = 0x092-0x093) [reset = Undefined]
Figure 58. Register (OADJ_B_INA)
15
14
13
12
11
5
4
3
OADJ_B_INA[7:0]
R/W
RESERVED
R/W-0000
7
6
10
9
OADJ_B_INA[11:8]
R/W
2
1
8
0
Table 89. OADJ_B_INA Field Descriptions
Bit
82
Field
Type
Reset
Description
15-12
RESERVED
R/W
0000
RESERVED
11-0
OADJ_B_INA
R/W
Undefined
Offset adjustment value for ADC2 (B-ADC) applied when ADC2
samples INA. The format is unsigned. After reset, the factory
trimmed value can be read and adjusted as required.
Important notes:
•
Never write OADJ* registers while foreground calibration is
underway
•
Never write OADJ* registers if CAL_BG and CAL_BGOS
are set
•
If CAL_OS=1 and CAL_BGOS=0, only read OADJ* registers
if FG_DONE=1
•
If CAL_BG=1 and CAL_BGOS=1, only read OADJ* register
if CAL_STOPPED=1
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7.6.1.5.30 Offset Adjustment for B-ADC and INB Register (address = 0x094-0x095) [reset = Undefined]
Figure 59. Register (OADJ_B_INB)
15
14
13
12
11
5
4
3
OADJ_B_INB[7:0]
R/W
RESERVED
R/W-0000
7
6
10
9
OADJ_B_INB[11:8]
R/W
2
1
8
0
Field
Type
Reset
Description
15-12
Bit
RESERVED
R/W
0000
RESERVED
11-0
OADJ_B_INB
R/W
Undefined
Offset adjustment value for ADC2 (B-ADC) applied when ADC2
samples INB. The format is unsigned. After reset, the factory
trimmed value can be read and adjusted as required.
Important notes:
•
Never write OADJ* registers while foreground calibration is
underway
•
Never write OADJ* registers if CAL_BG and CAL_BGOS
are set
•
If CAL_OS=1 and CAL_BGOS=0, only read OADJ* registers
if FG_DONE=1
•
If CAL_BG=1 and CAL_BGOS=1, only read OADJ* register
if CAL_STOPPED=1
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Table 90. OADJ_B_INB Field Descriptions
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7.6.1.5.31 Offset Filtering Control 0 Register (address = 0x097) [reset = 0x00]
Figure 60. Register (OSFILT0)
7
6
5
4
RESERVED
R/W-0000 000
3
2
1
0
DC_RESTORE
R/W
Table 91. OSFILT0 Field Descriptions
Bit
Field
Type
Reset
Description
7-1
RESERVED
R/W
0000 000
RESERVED
DC_RESTORE
R/W
0
When set the offset filtering feature (enabled by CAL_OSFILT)
will filter only the offset mismatch across ADC banks and will not
remove the frequency content near DC. When cleared, the
feature filters all offsets from all banks, thus filtering all DC
content in the signal. See Offset Filtering feature description.
0
ADVANCE INFORMATION
84
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7.6.1.5.32 Offset Filtering Control 1 Register (address = 0x098) [reset = 0x33]
Figure 61. Register (OSFILT1)
7
6
5
4
3
OSFILT_BW
R/W-0011
2
1
0
OSFILT_SOAK
R/W-0011
Bit
Field
Type
Reset
Description
7-4
OSFILT_BW
R/W
0011
This adjusts the IIR filter bandwidth for the offset filtering feature
(enabled by CAL_OSFILT). More bandwidth will suppress more
flicker noise from the ADCs and reduce the offset spurs. Less
bandwidth will minimize the impact of the filters on the mission
mode signal.
OSFILT_BW: IIR Coefficient: -3dB Bandwidth (single sided)
0: RESERVED: RESERVED
1: 2-10 : 609e-9*FDEVCLK
2: 2-11 : 305e-9*FDEVCLK
3: 2-12 : 152e-9*FDEVCLK
4: 2-13 : 76e-9*FDEVCLK
5: 2-14 : 38e-9*FDEVCLK
6-15: RESERVED
3-0
OSFILT_SOAK
R/W
0011
This adjusts the IIR soak time for the offset filtering feature. This
applies when offset filtering and background calibration are both
enabled. This field determines how long the IIR filter is allowed
to settle when it is first connected to an ADC after the ADC is
calibrated. After the soak time completes, the ADC is placed
online using the IIR filter. It is recommended to set
OSFILT_SOAK = OSFILT_BW.
7.6.1.6 ADC Bank Registers (0x100 to 0x15F)
Table 93. ADC Bank Registers
Address
Reset
Acronym
Register Name
Section
0x100-0x101
Undefined
RESERVED
RESERVED
0x102
Undefined
B0_TIME_0
Timing Adjustment for Bank 0 (0° Clock) Register
0x103
Undefined
B0_TIME_90
Timing Adjustment for Bank 0 (-90° Clock) Register
0x104-0x111
Undefined
RESERVED
RESERVED
0x112
Undefined
B1_TIME_0
Timing Adjustment for Bank 1 (0° Clock) Register
0x113
Undefined
B1_TIME_90
Timing Adjustment for Bank 1 (-90° Clock) Register
0x114-0x121
Undefined
RESERVED
RESERVED
0x122
Undefined
B2_TIME_0
Timing Adjustment for Bank 2 (0° Clock) Register
0x123
Undefined
B2_TIME_90
Timing Adjustment for Bank 2 (-90° Clock) Register
0x124-0x131
Undefined
RESERVED
RESERVED
0x132
Undefined
B3_TIME_0
Timing Adjustment for Bank 3 (0° Clock) Register
0x133
Undefined
B3_TIME_90
Timing Adjustment for Bank 3 (-90° Clock) Register
0x134-0x141
Undefined
RESERVED
RESERVED
0x142
Undefined
B4_TIME_0
Timing Adjustment for Bank 4 (0° Clock) Register
0x143
Undefined
B4_TIME_90
Timing Adjustment for Bank 4 (-90° Clock) Register
0x144-0x151
Undefined
RESERVED
RESERVED
0x152
Undefined
B5_TIME_0
Timing Adjustment for Bank 5 (0° Clock) Register
0x153
Undefined
B5_TIME_90
Timing Adjustment for Bank 5 (-90° Clock) Register
0x154-0x15F
Undefined
RESERVED
RESERVED
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Table 92. OSFILT1 Field Descriptions
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7.6.1.6.1 Timing Adjustment for Bank 0 (0° Clock) Register (address = 0x102) [reset = Undefined]
Figure 62. Timing Adjustment for Bank 0 (0° Clock) Register (B0_TIME_0)
7
6
5
4
3
2
1
0
B0_TIME_0
R/W
Table 94. B0_TIME_0 Field Descriptions
Bit
Field
Type
Reset
Description
7-0
B0_TIME_0
R/W
Undefined
Time adjustment for bank 0 (applied when ADC is configured for
0° clock phase). After reset, the factory trimmed value can be
read and adjusted as required.
7.6.1.6.2 Timing Adjustment for Bank 0 (-90° Clock) Register (address = 0x103) [reset = Undefined]
Figure 63. Timing Adjustment for Bank 0 (-90° Clock) Register (B0_TIME_90)
7
6
5
4
3
2
1
0
ADVANCE INFORMATION
B0_TIME_90
R/W
Table 95. B0_TIME_90 Field Descriptions
Bit
Field
Type
Reset
Description
7-0
B0_TIME_90
R/W
Undefined
Time adjustment for bank 0 (applied when ADC is configured for
-90° clock phase). After reset, the factory trimmed value can be
read and adjusted as required.
7.6.1.6.3 Timing Adjustment for Bank 1 (0° Clock) Register (address = 0x112) [reset = Undefined]
Figure 64. Timing Adjustment for Bank 1 (0° Clock) Register (B1_TIME_0)
7
6
5
4
3
2
1
0
B1_TIME_0
R/W
Table 96. B1_TIME_0 Field Descriptions
Bit
Field
Type
Reset
Description
7-0
B1_TIME_0
R/W
Undefined
Time adjustment for bank 1 (applied when ADC is configured for
0° clock phase). After reset, the factory trimmed value can be
read and adjusted as required.
7.6.1.6.4 Timing Adjustment for Bank 1 (-90° Clock) Register (address = 0x113) [reset = Undefined]
Figure 65. Timing Adjustment for Bank 1 (-90° Clock) Register (B1_TIME_90)
7
6
5
4
3
2
1
0
B1_TIME_90
R/W
Table 97. B1_TIME_90 Field Descriptions
86
Bit
Field
Type
Reset
Description
7-0
B1_TIME_90
R/W
Undefined
Time adjustment for bank 1 (applied when ADC is configured for
-90° clock phase). After reset, the factory trimmed value can be
read and adjusted as required.
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7.6.1.6.5 Timing Adjustment for Bank 2 (0° Clock) Register (address = 0x122) [reset = Undefined]
Figure 66. Timing Adjustment for Bank 2 (0° Clock) Register (B2_TIME_0)
7
6
5
4
3
2
1
0
B2_TIME_0
R/W
Table 98. B2_TIME_0 Field Descriptions
Bit
Field
Type
Reset
Description
7-0
B2_TIME_0
R/W
Undefined
Time adjustment for bank 2 (applied when ADC is configured for
0° clock phase). After reset, the factory trimmed value can be
read and adjusted as required.
7.6.1.6.6 Timing Adjustment for Bank 2 (-90° Clock) Register (address = 0x123) [reset = Undefined]
Figure 67. Timing Adjustment for Bank 2 (-90° Clock) Register (B2_TIME_90)
6
5
4
3
2
1
0
B2_TIME_90
R/W
Table 99. B2_TIME_90 Field Descriptions
Bit
Field
Type
Reset
Description
7-0
B2_TIME_90
R/W
Undefined
Time adjustment for bank 2 (applied when ADC is configured for
-90° clock phase). After reset, the factory trimmed value can be
read and adjusted as required.
7.6.1.6.7 Timing Adjustment for Bank 3 (0° Clock) Register (address = 0x132) [reset = Undefined]
Figure 68. Timing Adjustment for Bank 3 (0° Clock) Register (B3_TIME_0)
7
6
5
4
3
2
1
0
B3_TIME_0
R/W
Table 100. B3_TIME_0 Field Descriptions
Bit
Field
Type
Reset
Description
7-0
B3_TIME_0
R/W
Undefined
Time adjustment for bank 3 (applied when ADC is configured for
0° clock phase). After reset, the factory trimmed value can be
read and adjusted as required.
7.6.1.6.8 Timing Adjustment for Bank 3 (-90° Clock) Register (address = 0x133) [reset = Undefined]
Figure 69. Timing Adjustment for Bank 3 (-90° Clock) Register (B3_TIME_90)
7
6
5
4
3
2
1
0
B3_TIME_90
R/W
Table 101. B3_TIME_90 Field Descriptions
Bit
Field
Type
Reset
Description
7-0
B3_TIME_90
R/W
Undefined
Time adjustment for bank 3 (applied when ADC is configured for
-90° clock phase). After reset, the factory trimmed value can be
read and adjusted as required.
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7.6.1.6.9 Timing Adjustment for Bank 4 (0° Clock) Register (address = 0x142) [reset = Undefined]
Figure 70. Timing Adjustment for Bank 4 (0° Clock) Register (B4_TIME_0)
7
6
5
4
3
2
1
0
B4_TIME_0
R/W
Table 102. B4_TIME_0 Field Descriptions
Bit
Field
Type
Reset
Description
7-0
B4_TIME_0
R/W
Undefined
Time adjustment for bank 4 (applied when ADC is configured for
0° clock phase). After reset, the factory trimmed value can be
read and adjusted as required.
7.6.1.6.10 Timing Adjustment for Bank 4 (-90° Clock) Register (address = 0x143) [reset = Undefined]
Figure 71. Timing Adjustment for Bank 4 (-90° Clock) Register (B4_TIME_90)
7
6
5
4
3
2
1
0
ADVANCE INFORMATION
B4_TIME_90
R/W
Table 103. B4_TIME_90 Field Descriptions
Bit
Field
Type
Reset
Description
7-0
B4_TIME_90
R/W
Undefined
Time adjustment for bank 4 (applied when ADC is configured for
-90° clock phase). After reset, the factory trimmed value can be
read and adjusted as required.
7.6.1.6.11 Timing Adjustment for Bank 5 (0° Clock) Register (address = 0x152) [reset = Undefined]
Figure 72. Timing Adjustment for Bank 5 (0° Clock) Register (B5_TIME_0)
7
6
5
4
3
2
1
0
B5_TIME_0
R/W
Table 104. B5_TIME_0 Field Descriptions
Bit
Field
Type
Reset
Description
7-0
B5_TIME_0
R/W
Undefined
Time adjustment for bank 5 (applied when ADC is configured for
0° clock phase). After reset, the factory trimmed value can be
read and adjusted as required.
7.6.1.6.12 Timing Adjustment for Bank 5 (-90° Clock) Register (address = 0x153) [reset = Undefined]
Figure 73. Timing Adjustment for Bank 5 (-90° Clock) Register (B5_TIME_90)
7
6
5
4
3
2
1
0
B5_TIME_90
R/W
Table 105. B5_TIME_90 Field Descriptions
88
Bit
Field
Type
Reset
Description
7-0
B5_TIME_90
R/W
Undefined
Time adjustment for bank 5 (applied when ADC is configured for
-90° clock phase). After reset, the factory trimmed value can be
read and adjusted as required.
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7.6.1.7 LSB Control Registers (0x160 to 0x1FF)
Table 106. LSB Control Registers
Address
Reset
Acronym
Register Name
0x160
0x00
ENC_LSB
LSB Control Bit Output Register
Section
0x161-0x1FF
Undefined
RESERVED
RESERVED
7.6.1.7.1 LSB Control Bit Output Register (address = 0x160) [reset = 0x00]
Figure 74. LSB Control Bit Output Register (ENC_LSB)
7
6
5
4
3
2
1
0
CAL_STATE_E TIMESTAMP_E
N
N
R/W-0
R/W-0
RESERVED
R/W-0000 00
Bit
Field
Type
Reset
Description
7-2
RESERVED
R/W
0000 00
RESERVED
1
CAL_STATE_EN
R/W
0
When set, the transport layer transmits calibration state
information on the LSB of the output samples.
0
TIMESTAMP_EN
R/W
0
When set, the transport layer transmits the timestamp signal on
the LSB of the output samples. TIMESTAMP_EN has priority
over CAL_STATE_EN. SYNC_RECV_EN must also be set high
when using timestamp. The latency of the timestamp signal
(through the entire chip) matches the latency of the analog ADC
inputs.
Note: The control bit that is enabled by this register is never
advertised in the ILA (the CS field is 0 in the ILA).
7.6.1.8 JESD204B Registers (0x200 to 0x20F)
Table 108. JESD204B Registers
Address
Reset
Acronym
Register Name
0x200
0x01
JESD_EN
JESD204B Enable Register
0x201
0x02
JMODE
0x202
0x1F
KM1
0x203
0x01
JSYNC_N
0x204
0x02
JCTRL
JESD204B Control Register
0x205
0x00
JTEST
JESD204B Test Pattern Control Register
0x206
0x00
DID
0x207
0x00
FCHAR
JESD204B Frame Character Register
0x208
Undefined
JESD_STATUS
JESD204B / System Status Register
0x209
0x00
PD_CH
0x20A
0x00
JEXTRA_A
JESD204B Extra Lane Enable (Link A)
0x20B
0x00
JEXTRA_B
JESD204B Extra Lane Enable (Link B)
Undefined
RESERVED
RESERVED
Section
JESD204B Mode Register
JESD204B K Parameter Register
JESD204B Manual SYNC Request Register
JESD204B DID Parameter Register
JESD204B Channel Power Down
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Table 107. ENC_LSB Field Descriptions
ADC12DJ3200
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7.6.1.8.1 JESD204B Enable Register (address = 0x200) [reset = 0x01]
Figure 75. JESD204B Enable Register (JESD_EN)
7
6
5
4
RESERVED
R/W-0000 000
3
2
1
0
JESD_EN
R/W-1
Table 109. JESD_EN Field Descriptions
Bit
Field
Type
Reset
Description
7-1
RESERVED
R/W
0000 000
RESERVED
JESD_EN
R/W
1
0 : Disable JESD204B interface
1 : Enable JESD204B interface
Note 1: Before altering other JESD204B registers, you must
clear JESD_EN. When JESD_EN is 0, the block is held in reset
and the serializers are powered down. The clocks are gated off
to save power. The LMFC counter is also held in reset, so
SYSREF will not align the LMFC.
Note 2: Always set CAL_EN before setting JESD_EN
Note 3: Always clear JESD_EN before clearing CAL_EN
0
ADVANCE INFORMATION
7.6.1.8.2 JESD204B Mode Register (address = 0x201) [reset = 0x02]
Figure 76. JESD204B Mode Register (JMODE)
7
6
RESERVED
R/W-000
5
4
3
2
JMODE
R/W-0001 0
1
0
Table 110. JMODE Field Descriptions
Bit
Field
Type
Reset
Description
7-5
RESERVED
R/W
000
RESERVED
4-0
JMODE
R/W
0001 0
Specify the JESD204B output mode
Note: This register should only be changed when JESD_EN=0
and CAL_EN=0
7.6.1.8.3 JESD204B K Parameter Register (address = 0x202) [reset = 0x1F]
Figure 77. JESD204B K Parameter Register (KM1)
7
6
RESERVED
R/W-000
5
4
3
2
KM1
R/W-1111 1
1
0
Table 111. KM1 Field Descriptions
90
Bit
Field
Type
Reset
Description
7-5
RESERVED
R/W
000
RESERVED
4-0
KM1
R/W
1111 1
K is the number of frames per multiframe and this register must
be programmed as K-1. Depending on the JMODE setting, there
are constraints on the legal values of K. (default: KM1=31,
K=32)
Note: This register should only be changed when JESD_EN is 0.
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7.6.1.8.4 JESD204B Manual SYNC Request Register (address = 0x203) [reset = 0x01]
Figure 78. JESD204B Manual SYNC Request Register (JSYNC_N)
7
6
5
4
RESERVED
R/W-0000 000
3
2
1
0
JSYNC_N
R/W-1
Bit
Field
Type
Reset
Description
7-1
RESERVED
R/W
0000 000
RESERVED
JSYNC_N
R/W
1
Set this bit to 0 to request JESD204B synchronization
(equivalent to the SYNCSE pin being asserted). For normal
operation, leave this bit set to 1.
Note: The JSYNC_N register can always generate a
synchronization request, regardless of the SYNC_SEL register.
However, if the selected sync pin is stuck low, you cannot deassert the synchronization request unless you program
SYNC_SEL=2.
0
7.6.1.8.5 JESD204B Control Register (address = 0x204) [reset = 0x02]
Figure 79. JESD204B Control Register (JCTRL)
7
6
5
4
3
RESERVED
R/W-0000
2
SYNC_SEL
R/W-00
1
SFORMAT
R/W-1
0
SCR
R/W-0
Table 113. JCTRL Field Descriptions
Bit
Field
Type
Reset
Description
7-4
RESERVED
R/W
0000
RESERVED
3-2
SYNC_SEL
R/W
00
0: Use the SYNCSE input for SYNC~ function (default)
1: Use the TMSTP+/- differential input for SYNC~ function.
SYNC_RECV_EN must also be set.
2: Do not use any sync input signal (use software SYNC~
through JSYNC_N)
1
SFORMAT
R/W
1
Output sample format for JESD204B samples
0: Offset binary
1: Signed 2’s complement (default)
0
SCR
R/W
0
0: Scrambler disabled (default)
1: Scrambler enabled
Note: This register should only be changed when JESD_EN is 0.
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Table 112. JSYNC_N Field Descriptions
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7.6.1.8.6 JESD204B Test Pattern Control Register (address = 0x205) [reset = 0x00]
Figure 80. JESD204B Test Pattern Control Register (JTEST)
7
6
5
4
3
2
RESERVED
R/W-0000
1
0
JTEST
R/W-0000
Table 114. JTEST Field Descriptions
ADVANCE INFORMATION
Bit
Field
Type
Reset
Description
7-4
RESERVED
R/W
0000
RESERVED
3-0
JTEST
R/W
0000
0: Test mode disabled. Normal operation (default)
1: PRBS7 test mode
2: PRBS15 test mode
3: PRBS23 test mode
4: Ramp test mode
5: Transport Layer test mode
6: D21.5 test mode
7: K28.5 test mode
8: Repeated ILA test mode
9: Modified RPAT test mode
10: Serial outputs held low
11: Serial outputs held high
12: P21_BIST test mode (for serializer BIST)
13 thru 15: RESERVED
Note: This register should only be changed when JESD_EN is 0.
7.6.1.8.7 JESD204B DID Parameter Register (address = 0x206) [reset = 0x00]
Figure 81. JESD204B DID Parameter Register (DID)
7
6
5
4
3
2
1
0
DID
R/W-0000 0000
Table 115. DID Field Descriptions
92
Bit
Field
Type
Reset
7-0
DID
R/W
0000 0000 Specifies the DID (Device ID) value that is transmitted during the
second multiframe of the JESD204B ILA. Link A will transmit
DID, and link B will transmit DID+1. Bit 0 is ignored and always
returns 0 (if you program an odd number, it will be decremented
to an even number).
Note: This register should only be changed when JESD_EN is 0.
Description
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7.6.1.8.8 JESD204B Frame Character Register (address = 0x207) [reset = 0x00]
Figure 82. JESD204B Frame Character Register (FCHAR)
7
6
5
4
3
2
1
0
RESERVED
R/W-0000 00
FCHAR
R/W-00
Bit
Field
Type
Reset
Description
7-2
RESERVED
R/W
0000 00
RESERVED
1-0
FCHAR
R/W
00
Specify which comma character is used to denote end-of-frame.
This character is transmitted opportunistically (see section
12.8.5)
0: Use K28.7 (default) (JESD204B compliant)
1: Use K28.1 (not JESD204B compliant)
2: Use K28.5 (not JESD204B compliant)
3: RESERVED
When using a JESD204B receiver, always use FCHAR=0. When
using a general purpose 8b/10b receiver, the K28.7 character
may cause issues. When K28.7 is combined with certain data
characters, a false, misaligned comma character can result, and
some receivers will re-align to the false comma. To avoid this,
program FCHAR to 1 or 2.
Note: This register should only be changed when JESD_EN is 0.
7.6.1.8.9 JESD204B / System Status Register (address = 0x208) [reset = Undefined]
Figure 83. JESD204B / System Status Register (JESD_STATUS)
7
RESERVED
6
LINK_UP
R
R
5
SYNC_STATU
S
R
4
REALIGNED
3
ALIGNED
2
PLL_LOCKED
R/W
R/W
R
1
0
RESERVED
R
Table 117. JESD_STATUS Field Descriptions
Bit
Field
Type
Reset
Description
7
RESERVED
R
Undefined
RESERVED
6
LINK_UP
R
Undefined
When set, indicates that the JESD204B link is up
5
SYNC_STATUS
R
Undefined
Returns the state of the JESD204B SYNC~ signal.
0: SYNC~ asserted
1: SYNC~ de-asserted
4
REALIGNED
R/W
Undefined
When high, indicates that an internal digital clock, frame clock,
or multiframe (LMFC) clock phase was realigned by SYSREF.
Writing a 1 to this bit will clear it.
3
ALIGNED
R/W
Undefined
When high, indicates that the multiframe (LMFC) clock phase
has been established by SYSREF. The first SYSREF event after
enabling the JESD204B encoder will set this bit. Writing a 1 to
this bit will clear it.
2
PLL_LOCKED
R
Undefined
When high, indicates that the PLL is locked
RESERVED
R
Undefined
RESERVED
1-0
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Table 116. FCHAR Field Descriptions
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7.6.1.8.10 JESD204B Channel Power Down Register (address = 0x209) [reset = 0x00]
Figure 84. JESD204B Channel Power Down Register (PD_CH)
7
6
5
4
3
RESERVED
R/W-0000 00
2
1
PD_BCH
R/W-0
0
PD_ACH
R/W-0
Table 118. PD_CH Field Descriptions
ADVANCE INFORMATION
94
Bit
Field
Type
Reset
Description
7-2
RESERVED
R/W
0000 00
RESERVED
1
PD_BCH
R/W
0
When set, the “B” ADC channel is powered down. The digital
channels that are bound to the “B” ADC channel are also
powered down (see DIG_BIND).
Important notes:
1. You must set JESD_EN=0 before changing PD_CH
2. To power down both ADC channels, use MODE
3. If both channels are powered down, then the entire
JESD204B subsystem (including the PLL and LMFC) are
powered down
4. If the selected JESD204B mode transmits A and B data on
link A, and the B digital channel is disabled, link A remains
operational, but the B-channel samples are undefined.
0
PD_ACH
R/W
0
When set, the “A” ADC channel is powered down. The digital
channels that are bound to the “A” ADC channel are also
powered down (see DIG_BIND).
Important notes:
1. You must set JESD_EN=0 before changing PD_CH
2. To power down both ADC channels, use MODE
3. If both channels are powered down, then the entire
JESD204B subsystem (including the PLL and LMFC) are
powered down
4. If the selected JESD204B mode transmits A and B data on
link A, and the B digital channel is disabled, link A remains
operational, but the B-channel samples are undefined.
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7.6.1.8.11 JESD204B Extra Lane Enable (Link A) Register (address = 0x20A) [reset = 0x00]
Figure 85. JESD204B Extra Lane Enable (Link A) Register (JEXTRA_A)
7
6
5
4
EXTRA_LANE_A
3
2
1
R/W-0000 000
0
EXTRA_SER_
A
R/W-0
Bit
Field
Type
Reset
Description
7-1
EXTRA_LANE_A
R/W
0000 000
Program these register bits to enable extra lanes (even if the
selected JMODE does not require the lanes to be enabled).
EXTRA_LANE_A(n) enables An (n=1 to 7). This register enables
the link layer clocks for the affected lanes. To also enable the
extra serializes set EXTRA_SER_A=1.
0
EXTRA_SER_A
R/W
0
0: Only the link layer clocks for extra lanes are enabled.
1: Serializers for extra lanes are also enabled. Use this mode to
transmit data from the extra lanes.
Important notes:
This register should only be changed when JESD_EN=0.
The bit-rate and mode of the extra lanes are set by the JMODE
and JTEST parameters.
This register does not override the PD_CH register, so ensure
that the link is enabled to use this feature.
To enable serializer 'n', the lower number lanes 0 to n-1 must
also be enabled, otherwise serializer 'n' will not receive a clock.
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Table 119. JESD204B Extra Lane Enable (Link A) Field Descriptions
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7.6.1.8.12 JESD204B Extra Lane Enable (Link B) Register (address = 0x20B) [reset = 0x00]
Figure 86. JESD204B Extra Lane Enable (Link B) Register (JEXTRA_B)
7
6
5
4
EXTRA_LANE_B
3
2
1
R/W-0000 000
0
EXTRA_SER_
B
R/W-0
Table 120. JESD204B Extra Lane Enable (Link B) Field Descriptions
Field
Type
Reset
Description
EXTRA_LANE_B
R/W
0000 000
Program these register bits to enable extra lanes (even if the
selected JMODE does not require the lanes to be enabled).
EXTRA_LANE_B(n) enables Bn (n=1 to 7). This register enables
the link layer clocks for the affected lanes. To also enable the
extra serializes set EXTRA_SER_B=1.
0
EXTRA_SER_B
R/W
0
0: Only the link layer clocks for extra lanes are enabled.
1: Serializers for extra lanes are also enabled. Use this mode to
transmit data from the extra lanes.
Important notes:
This register should only be changed when JESD_EN=0.
The bit-rate and mode of the extra lanes are set by the JMODE
and JTEST parameters.
This register does not override the PD_CH register, so ensure
that the link is enabled to use this feature.
To enable serializer 'n', the lower number lanes 0 to n-1 must
also be enabled, otherwise serializer 'n' will not receive a clock.
ADVANCE INFORMATION
Bit
7-1
96
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7.6.1.9 Digital Down Converter Registers (0x210-0x2AF)
Table 121. Over-range Registers
Address
Reset
Acronym
Register Name
0x211
0xF2
OVR_T0
Over-range Threshold 0 Register
Section
0x212
0xAB
OVR_T1
Over-range Threshold 1 Register
0x213
0x07
OVR_CFG
Undefined
RESERVED
0x297
Undefined
SPIN_ID
0x298-0x2AF
Undefined
RESERVED
Over-range Configuration Register
RESERVED
Spin Identification Value
RESERVED
7.6.1.9.1 Over-range Threshold 0 Register (address = 0x211) [reset = 0xF2]
Figure 87. Over-range Threshold 0 Register (OVR_T0)
7
6
5
4
3
2
1
0
ADVANCE INFORMATION
OVR_T0
R/W-1111 0010
Table 122. OVR_T0 Field Descriptions
Bit
Field
Type
Reset
7-0
OVR_T0
R/W
1111 0010 Over-range threshold 0. This parameter defines the absolute
sample level that causes control bit 0 to be set. The detection
level in dBFS (peak) is
20log10(OVR_T0 / 256)
Default: 0xF2 = 242 → –0.5 dBFS
Description
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7.6.1.9.2 Over-range Threshold 1 Register (address = 0x212) [reset = 0xAB]
Figure 88. Over-range Threshold 1 Register (OVR_T1)
7
6
5
4
3
2
1
0
OVR_T1
R/W-1010 1011
Table 123. OVR_T1 Field Descriptions
Bit
Field
Type
Reset
7-0
OVR_T1
R/W
1010 1011 Over-range threshold 1. This parameter defines the absolute
sample level that causes control bit 1 to be set. The detection
level in dBFS (peak) is
20log10(OVR_T1 / 256)
Default: 0xAB = 171 → –3.5 dBFS
Description
7.6.1.9.3 Over-range Configuration Register (address = 0x213) [reset = 0x07]
Figure 89. Over-range Configuration Register (OVR_CFG)
ADVANCE INFORMATION
7
6
5
4
3
OVR_EN
R/W-0
RESERVED
R/W-0000
2
1
OVR_N
R/W-111
0
Table 124. OVR_CFG Field Descriptions
(1)
98
Bit
Field
Type
Reset
Description
7-4
RESERVED
R/W
0000 0
RESERVED
3
OVR_EN
R/W
0
Enables over-range status output pins when set high. The
ORA0, ORA1, ORB0 and ORB1 outputs are held low when
OVR_EN is set low. This register only effects the over-range
output pins (ORxx) and not the over-range status embedded in
the data samples.
2-0
OVR_N (1)
R/W
111
Program this register to adjust the pulse extension for the
ORA0/1 and ORB0/1 outputs. The minimum pulse duration of
the over-range outputs is 8 * 2OVR_N DEVCLK cycles.
Incrementing this field doubles the monitoring period.
Changing the OVR_N setting while JESD_EN=1 may cause the phase of the monitoring period to change.
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7.6.1.10 Spin Identification Register (address = 0x297) [reset = Undefined]
Figure 90. Spin Identification Register (SPIN_ID)
7
6
RESERVED
R-000
5
4
3
2
SPIN_ID
R
1
0
Table 125. SPIN_ID Field Descriptions
Bit
Field
Type
Reset
Description
7-5
RESERVED
R
000
RESERVED
4-0
SPIN_ID
R
See
Spin identification value:
description 0 : ADC12DJ3200
7.6.2 SYSREF Calibration Registers (0x2B0 to 0x2BF)
Table 126. SYSREF Calibration Registers
Reset
Acronym
Register Name
SYSREF Calibration Enable Register
0x2B0
0x00
SRC_EN
0x2B1
0x05
SRC_CFG
Section
SYSREF Calibration Configuration Register
0x2B2-0x2B4
Undefined
0x2B5-0x2B7
0x00
TAD
0x2B8
0x00
TAD_RAMP
DEVCLK Timing Adjust Ramp Control
Register
Undefined
RESERVED
RESERVED
0x2B9-0x2BF
ADVANCE INFORMATION
Address
SRC_STATUS
SYSREF Calibration Status
DEVCLK Aperture Delay Adjustment Register
7.6.2.1 SYSREF Calibration Enable Register (address = 0x2B0) [reset = 0x00]
Figure 91. SYSREF Calibration Enable Register (SRC_EN)
7
6
5
4
RESERVED
R/W-0000 000
3
2
1
0
SRC_EN
R/W-0
Table 127. SRC_EN Field Descriptions
Bit
Field
Type
Reset
Description
7-1
RESERVED
R/W
0000 000
RESERVED
SRC_EN
R/W
0
0: SYSREF Calibration Disabled. Use the TAD register to
manually control the tad[16:0] output and adjust the DEVCLK
delay. (default)
1: SYSREF Calibration Enabled. The DEVCLK delay is
automatically calibrated. The TAD register is ignored.
A 0-to-1 transition on SRC_EN starts the SYSREF calibration
sequence. Program SRC_CFG before setting SRC_EN. Ensure
that ADC calibration is not currently running before setting
SRC_EN.
0
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7.6.2.2 SYSREF Calibration Configuration Register (address = 0x2B1) [reset = 0x05]
Figure 92. SYSREF Calibration Configuration Register (SRC_CFG)
7
6
5
4
3
RESERVED
R/W-0000
2
SRC_AVG
R/W-01
1
0
SRC_HDUR
R/W-01
Table 128. SRC_CFG Field Descriptions
Field
Type
Reset
Description
RESERVED
R/W
0000 00
RESERVED
3-2
SRC_AVG
R/W
01
Specifies the amount of averaging used for SYSREF Calibration.
Larger values will increase calibration time and reduce the
variance of the calibrated value.
0: 4 averages
1: 16 averages
2: 64 averages
3: 256 averages
1-0
SRC_HDUR
R/W
01
Specifies the duration of each high-speed accumulation for
SYSREF Calibration. If the SYSREF period exceeds the
supported value, calibration will fail. Larger values will increase
calibration time and support longer SYSREF periods. For a
given SYSREF period, larger values will also reduce the
variance of the calibrated value.
0: 4 cycles per accumulation, max SYSREF period of 85
DEVCLK cycles
1: 16 cycles per accumulation, max SYSREF period of 1100
DEVCLK cycles
2: 64 cycles per accumulation, max SYSREF period of 5200
DEVCLK cycles
3: 256 cycles per accumulation, max SYSREF period of 21580
DEVCLK cycles
Max duration of SYSREF calibration is bounded by:
TSYSREFCAL (in DEVCLK cycles) = 256 * 19 * 4(SRC_AVG +
ADVANCE INFORMATION
Bit
7-4
SRC_HDUR + 2)
100
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7.6.2.3 SYSREF Calibration Status Register (address = 0x2B2 to 0x2B4) [reset = Undefined]
Figure 93. SYSREF Calibration Status Register (SRC_STATUS)
23
22
21
20
19
18
17
SRC_DONE
R
16
SRC_TAD[16]
R
RESERVED
R
15
14
13
12
11
SRC_TAD[15:8]
R
10
9
8
7
6
5
4
2
1
0
3
SRC_TAD[7:0]
R
Bit
Field
Type
Reset
Description
23-18
RESERVED
R
Undefined
RESERVED
17
SRC_DONE
R
Undefined
This bit returns ‘1’ when SRC_EN=1 and SYSREF Calibration
has been completed
SRC_TAD
R
Undefined
This field returns the value for tad[16:0] computed by SYSREF
Calibration. It is only valid if SRC_DONE=1.
16-0
7.6.2.4 DEVCLK Aperture Delay Adjustment Register (address = 0x2B5 to 0x2B7) [reset = 0x000000]
Figure 94. DEVCLK Aperture Delay Adjustment Register (TAD)
23
22
21
15
14
7
6
20
RESERVED
R/W-0000 000
19
18
17
16
TAD_INV
R/W-0
13
12
11
TAD_COARSE
R/W-0000 0000
10
9
8
5
4
2
1
0
3
TAD_FINE
R/W-0000 0000
Table 130. TAD Field Descriptions
Bit
Field
Type
Reset
Description
RESERVED
R/W
0000 000
RESERVED
TAD_INV
R/W
0
Invert DEVCLK by setting this bit equal to 1
15-8
TAD_COARSE
R/W
0000 0000 This register controls the DEVCLK aperture delay adjustment
when SRC_EN=0. Use this register to manually control the
DEVCLK aperture delay when SYSREF Calibration is disabled.
If ADC calibration or JESD204B is running, it is recommended
that you gradually increase or decrease this value (1 code at a
time) to avoid clock glitches. TAD_COARSE has a resolution of
approximately 1 ps per LSB.
7-0
TAD_FINE
R/W
0000 0000 TAD_FINE has a resolution of approximately 25 fs.
23-17
16
7.6.2.5 DEVCLK Timing Adjust Ramp Control Register (address = 0x2B8) [reset = 0x00]
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Table 129. SRC_STATUS Field Descriptions
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Figure 95. DEVCLK Timing Adjust Ramp Control Register (TAD_RAMP)
7
6
5
4
3
2
RESERVED
R/W-0000 00
1
TAD_RAMP_R
ATE
R/W-0
0
TAD_RAMP_E
N
R/W-0
Table 131. TAD_RAMP Field Descriptions
Bit
Field
Type
Reset
Description
7-2
RESERVED
R/W
0000 00
RESERVED
1
TAD_RAMP_RATE
R/W
0
Specifies the ramp rate for the tad[15:8] output when the
TAD[15:8] register is written while TAD_RAMP_EN=1.
0: tad[15:8] ramps up or down one code per 256 DEVCLK
cycles.
1: tad[15:8] ramps up or down 4 codes per 256 DEVCLK cycles.
0
TAD_RAMP_EN
R/W
0
TAD Ramp enable. Set this bit if you want the coarse TAD
adjustments to ramp up or down instead of changing abruptly.
0: After writing the TAD[15:8] register the tad[15:7] output port is
updated within 1024 DEVCLK cycles.
1: After writing the TAD[15:8] register the tad[15:7] output port
ramps up or down until it matches the TAD[15:8] register.
ADVANCE INFORMATION
102
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7.6.3 Alarm Registers (0x2C0 to 0x2C2)
Table 132. Alarm Registers
Address
Reset
Acronym
Register Name
ALARM
Section
0x2C0
Undefined
Alarm Interrupt Status Register
0x2C1
0x1F
ALM_STATUS
Alarm Status Register
0x2C2
0x1F
ALM_MASK
Alarm Mask Register
7.6.3.1 Alarm Interrupt Register (address = 0x2C0) [reset = Undefined]
Figure 96. Alarm Interrupt Register (ALARM)
7
6
5
4
RESERVED
R
3
2
1
0
ALARM
R
Bit
Field
Type
Reset
Description
7-1
RESERVED
R
Undefined
RESERVED
ALARM
R
Undefined
This bit returns a ‘1’ whenever any alarm occurs that is
unmasked in the ALM_STATUS register. Use ALM_MASK to
mask (disable) individual alarms. CAL_STATUS_SEL can be
used to drive the ALARM bit onto the CALSTAT output pin to
provide a hardware alarm interrupt signal.
0
7.6.3.2 Alarm Status Register (address = 0x2C1) [reset = 0x1F]
Figure 97. Alarm Status Register (ALM_STATUS)
7
6
RESERVED
5
4
PLL_ALM
3
LINK_ALM
R/W-1
R/W-1
R/W-000
2
REALIGNED_A
LM
R/W-1
1
NCO_ALM
0
CLK_ALM
R/W-1
R/W-1
Table 134. ALM_STATUS Field Descriptions
Bit
Field
Type
Reset
Description
7-5
RESERVED
R/W
000
RESERVED
4
PLL_ALM
R/W
1
PLL Lock Lost Alarm: This bit is set whenever the PLL is not
locked. Write a ‘1’ to clear this bit.
3
LINK_ALM
R/W
1
Link Alarm: This bit is set whenever the JESD204B link is
enabled, but is not in the DATA_ENC state. Write a ‘1’ to clear
this bit.
2
REALIGNED_ALM
R/W
1
Realigned Alarm: This bit is set whenever SYSREF causes the
internal clocks (including the LMFC) to be realigned. Write a ‘1’
to clear this bit.
0
CLK_ALM
R/W
1
Clock Alarm: This bit can be used to detect an upset to the
digital block and JESD204B clocks. This bit is set whenever the
internal clock dividers for the A and B channels do not match.
Write a ‘1’ to clear this bit.
7.6.3.3 Alarm Mask Register (address = 0x2C2) [reset = 0x1F]
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Table 133. ALARM Field Descriptions
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Figure 98. Alarm Mask Register (ALM_MASK)
7
6
RESERVED
R/W-000
5
4
3
2
1
0
MASK_PLL_AL MASK_LINK_A MASK_REALIG MASK_NCO_A MASK_CLK_AL
M
LM
NED_ALM
LM
M
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
Table 135. ALM_MASK Field Descriptions
Bit
Field
Type
Reset
Description
7-5
RESERVED
R/W
000
RESERVED
4
MASK_PLL_ALM
R/W
1
When set, PLL_ALM is masked and will not impact the ALARM
register bit
3
MASK_LINK_ALM
R/W
1
When set, LINK_ALM is masked and will not impact the ALARM
register bit
2
MASK_REALIGNED_ALM
R/W
1
When set, REALIGNED_ALM is masked and will not impact the
ALARM register bit
1
MASK_NCO_ALM
R/W
1
When set, NCO_ALM is masked and will not impact the ALARM
register bit
0
MASK_CLK_ALM
R/W
1
When set, CLK_ALM is masked and will not impact the ALARM
register bit
ADVANCE INFORMATION
104
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8 Device and Documentation Support
8.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 136. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
ADC12DJ3200
Click here
Click here
Click here
Click here
Click here
8.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
8.4 Trademarks
E2E is a trademark of Texas Instruments.
8.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
8.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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8.3 Community Resources
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9 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
ADVANCE INFORMATION
106
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PACKAGE OPTION ADDENDUM
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27-May-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ADC12DJ3200AAV
PREVIEW
FCBGA
AAV
144
168
TBD
Call TI
Call TI
-40 to 85
ADC12DJ32
ADC12DJ3200AAVT
PREVIEW
FCBGA
AAV
144
250
TBD
Call TI
Call TI
-40 to 85
ADC12DJ32
PADC12DJ3200AAV
PREVIEW
FCBGA
AAV
144
168
TBD
Call TI
Call TI
-40 to 85
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OUTLINE
AAV0144A
FCBGA - 1.94 mm max height
SCALE 1.400
BALL GRID ARRAY
10.15
9.85
A
B
BALL A1 CORNER
10.15
9.85
( 8)
(0.68)
(0.5)
1.94 MAX
C
SEATING PLANE
NOTE 4
BALL TYP
0.405
TYP
0.325
0.2 C
8.8 TYP
(0.6) TYP
SYMM
0.8 TYP
(0.6) TYP
M
L
K
J
H
SYMM
8.8
TYP
G
F
E
D
0.51
144X
0.41
0.15
C A B
0.08
C NOTE 3
C
B
A
1
2
3
4
5
6
7
8
9
10
11 12
0.8 TYP
4219578/A 04/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Dimension is measured at the maximum solder ball diameter, parallel to primary datum C.
4. Primary datum C and seating plane are defined by the spherical crowns of the solder balls.
www.ti.com
EXAMPLE BOARD LAYOUT
AAV0144A
FCBGA - 1.94 mm max height
BALL GRID ARRAY
(0.8) TYP
A
1
2
3
4
5
6
7
8
10
9
11
12
B
(0.8) TYP
C
D
144X ( 0.4)
E
F
SYMM
G
H
J
K
L
M
SYMM
LAND PATTERN EXAMPLE
SCALE:8X
( 0.4)
METAL
0.05 MAX
METAL UNDER
SOLDER MASK
0.05 MIN
( 0.4)
SOLDER MASK
OPENING
SOLDER MASK
OPENING
NON-SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4219578/A 04/2016
NOTES: (continued)
5. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SPRU811 (www.ti.com/lit/spru811).
www.ti.com
EXAMPLE STENCIL DESIGN
AAV0144A
FCBGA - 1.94 mm max height
BALL GRID ARRAY
144X ( 0.4)
(0.8) TYP
A
1
2
3
4
5
6
7
8
9
10
11
12
B
(0.8)
TYP
C
D
E
F
SYMM
G
H
J
K
L
M
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.15 mm THICK STENCIL
SCALE:8X
4219578/A 04/2016
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.
www.ti.com
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