CD40174BMS CMOS Hex ‘D’-Type Flip-Flop December 1992 Features Pinout • High Voltage Type (20V Rating) CD40174BMS TOP VIEW • 5V, 10V and 15V Parametric Ratings • Standardized, Symmetrical Output Characteristics CLEAR 1 • 100% Tested for Quiescent Current at 20V 16 VDD Q1 2 15 Q6 • Maximum Input Current of 1µA at 18V Over Full Package Temperature Range, 100nA at 18V and +25oC D1 3 14 D6 D2 4 13 D5 • Noise Margin (Over full Package Temperature Range): - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V Q2 5 12 Q5 D3 6 11 D4 Q3 7 10 Q4 9 CLOCK VSS 8 • Meets All Requirements of JEDEC Tentative Standard No. 13A, “Standard Specifications for Description of ‘B’ Series CMOS Devices” Applications Functional Diagram • Shift Registers D1 • Buffer/Storage Registers 3 2 Q1 F/F1 • Pattern Generators D2 Description CD40174BMS consists of six identical ‘D’-Type flip-flops having independent DATA inputs. The CLOCK and CLEAR inputs are common to all six units. Data is transferred to the Q outputs on the positive going transition of the clock pulse. All six flip-flops are simultaneously reset by a low level on the CLEAR input. D3 D4 4 5 F/F2 6 7 F/F3 11 10 F/F4 Q2 Q3 Q4 The CD40174BMS is supplied in these 16 lead outline packages: Braze Seal DIP H4T Frit Seal DIP H1E Ceramic Flatpack H6W D5 D5 CLOCK CLEAR 13 12 F/F5 14 9 15 F/F6 Q5 Q6 1 VSS = 8 VDD = 16 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 7-1384 File Number 3359 Specifications CD40174BMS Absolute Maximum Ratings Reliability Information DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum Thermal Resistance . . . . . . . . . . . . . . . . θja θjc Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W o Maximum Package Power Dissipation (PD) at +125 C For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Supply Current SYMBOL IDD CONDITIONS (NOTE 1) VDD = 20V, VIN = VDD or GND VDD = 18V, VIN = VDD or GND Input Leakage Current IIL VIN = VDD or GND VDD = 20 VDD = 18V Input Leakage Current IIH VIN = VDD or GND VDD = 20 VDD = 18V Output Voltage Output Voltage VOL15 VOH15 VDD = 15V, No Load VDD = 15V, No Load (Note 3) GROUP A SUBGROUPS LIMITS TEMPERATURE o 1 +25 C oC 2 +125 3 -55o o C MIN MAX UNITS - 2 µA - 200 µA - 2 µA 1 +25 C -100 - nA 2 +125oC -1000 - nA 3 -55oC -100 - nA 1 +25oC - 100 nA 2 +125oC - 1000 nA 3 -55oC - 100 nA 1, 2, 3 +25oC, +125oC, -55oC - 50 mV 1, 2, 3 +25oC, +125oC, -55oC 14.95 - V Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1 +25oC 0.53 - mA Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1 +25oC 1.4 - mA Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1 +25oC 3.5 - mA 1 +25oC - -0.53 mA 1 +25oC - -1.8 mA 1 +25oC - -1.4 mA 1 +25oC - -3.5 mA 1 +25oC -2.8 -0.7 V 0.7 2.8 V Output Current (Source) Output Current (Source) Output Current (Source) Output Current (Source) N Threshold Voltage P Threshold Voltage Functional IOH5A IOH5B IOH10 IOH15 VNTH VPTH F VDD = 5V, VOUT = 4.6V VDD = 5V, VOUT = 2.5V VDD = 10V, VOUT = 9.5V VDD = 15V, VOUT = 13.5V VDD = 10V, ISS = -10µA VSS = 0V, IDD = 10µA 1 +25oC VDD = 2.8V, VIN = VDD or GND 7 +25oC VDD = 20V, VIN = VDD or GND 7 +25oC VDD = 18V, VIN = VDD or GND 8A +125oC VDD = 3V, VIN = VDD or GND 8B -55oC VOH > VOL < VDD/2 VDD/2 V Input Voltage Low (Note 2) VIL5 VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC - 1.5 V Input Voltage High (Note 2) VIH5 VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 3.5 - V Input Voltage Low (Note 2) VIL15 VDD = 15V, VOH > 13.5V, VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC - 4 V Input Voltage High (Note 2) VIH15 VDD = 15V, VOH > 13.5V, VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC 11 - V NOTES: 1. All voltages referenced to device GND, 100% testing being implemented. 2. Go/No Go test with limits applied to inputs. 7-1385 3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max. Specifications CD40174BMS TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Propagation Delay Clock to Output Propagation Delay CLEAR to Output Transition Time Maximum Clock Input Frequency SYMBOL TPHL1 TPLH1 TPHL2 CONDITIONS (Note 1, 2) GROUP A SUBGROUPS TEMPERATURE VDD = 5V, VIN = VDD or GND 9 10, 11 VDD = 5V, VIN = VDD or GND 9 10, 11 TTHL TTLH VDD = 5V, VIN = VDD or GND 9 10, 11 FCL VDD = 5V, VIN = VDD or GND 9 10, 11 +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC +25oC +125oC, -55oC LIMITS MIN MAX UNITS - 300 ns - 405 ns - 200 ns - 270 ns - 200 ns - 270 ns 3.5 - MHz 3.5/1.35 - MHz MIN MAX UNITS - 1 µA - 30 µA - 2 µA - 60 µA NOTES: 1. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 2. -55oC and +125oC limits guaranteed, 100% testing being implemented. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL IDD CONDITIONS NOTES VDD = 5V, VIN = VDD or GND 1, 2 TEMPERATURE -55oC, +25oC +125oC VDD = 10V, VIN = VDD or GND 1, 2 -55oC, +25oC +125oC VDD = 15V, VIN = VDD or GND Output Voltage VOL VDD = 5V, No Load 1, 2 1, 2 - 2 µA +125oC - 120 µA +25oC, +125oC, - 50 mV -55oC, +25oC -55oC Output Voltage VOL VDD = 10V, No Load 1, 2 +25oC, +125oC, -55oC - 50 mV Output Voltage VOH VDD = 5V, No Load 1, 2 +25oC, +125oC, -55oC 4.95 - V Output Voltage VOH VDD = 10V, No Load 1, 2 +25oC, +125oC, -55oC 9.95 - V VDD = 5V, VOUT = 0.4V 1, 2 +125oC 0.36 - mA -55oC 0.64 - mA +125oC 0.9 - mA -55oC 1.6 - mA +125oC 2.4 - mA -55oC 4.2 - mA +125oC - -0.36 mA -55oC - -0.64 mA +125oC - -1.15 mA -55oC - -2.0 mA +125oC - -0.9 mA -55oC - -1.6 mA Output Current (Sink) Output Current (Sink) Output Current (Sink) Output Current (Source) Output Current (Source) Output Current (Source) IOL5B IOL10 IOL15 IOH5A IOH5B IOH10 VDD = 10V, VOUT = 0.5V VDD = 15V, VOUT = 1.5V VDD = 5V, VOUT = 4.6V 1, 2 1, 2 1, 2 VDD = 5V, VOUT = 2.5V 1, 2 VDD = 10V, VOUT = 9.5V 7-1386 1, 2 Specifications CD40174BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER Output Current (Source) Input Voltage Low SYMBOL IOH15 VIL Input Voltage High VIH Propagation Delay Clock to Output TPHL1 TPLH1 Propagation Delay CLEAR to Output Transition Time Maximum Clock Input Frequency Minimum Data Setup Time TPHL2 CONDITIONS VDD =15V, VOUT = 13.5V FCL TREM 3 V - 140 ns 1, 2, 3 - 100 ns 1, 2, 3 +25oC - 100 ns VDD = 15V VDD = 10V VDD = 10V VDD = 15V VDD = 10V VDD = 5V VDD = 5V VDD = 5V VDD = 5V VDD = 10V VDD = 5V VDD = 5V VDD = 10V CIN - +25oC VDD = 15V Input Capacitance mA +25oC VDD = 10V TW -4.2 1, 2, 3 VDD = 10V VDD = 15V Minimum CLEAR Pulse Width - +25oC, +125oC, V VDD = 15V Minimum CLEAR Removal Time mA - VDD = 10V TRCL TFCL -2.4 +7 VDD = 15V Maximum Clock Rise and Fall Time - -55oC +25oC, +125oC, -55oC VDD = 15V TW 1, 2 1, 2 VDD = 10V Minimum Clock Pulse Width UNITS VDD = 10V, VOH > 9V, VOL < 1V VDD = 10V TH MAX -55oC VDD = 15V Minimum Data Hold Time MIN +125oC 1, 2 VDD = 15V TS TEMPERATURE VDD = 10V, VOH > 9V, VOL < 1V VDD = 15V TTHL TTLH NOTES CLEAR All others o 1, 2, 3 +25 C - 80 ns 1, 2, 3 +25oC - 100 ns 1, 2, 3 +25oC - 80 ns 1, 2, 3 +25oC 6 - MHz 1, 2, 3 +25oC 8 - MHz 1, 2, 3 +25oC - 40 ns 1, 2, 3 +25oC - 20 ns 1, 2, 3 +25oC - 10 ns 1, 2, 3 +25oC - 80 ns 1, 2, 3 +25oC - 40 ns 1, 2, 3 +25oC - 30 ns 1, 2, 3 +25oC - 130 ns 1, 2, 3 +25oC - 60 ns 1, 2, 3 +25oC - 40 ns 1, 2, 3, 4 +25oC 15 - µs 1, 2, 3, 4 +25oC 15 - µs 1, 2, 3, 4 +25oC 15 - µs 1, 2, 3 +25oC - 0 ns 1, 2, 3 +25oC - 0 ns 1, 2, 3 +25oC - 0 ns 1, 2, 3 +25oC - 100 ns 1, 2, 3 +25oC - 50 ns 1, 2, 3 +25oC - 40 ns 1, 2 +25oC - 40 pF 1, 2 +25oC - 7.5 pF NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. If more than one unit is cascaded, TRCL should be made less than or equal to the sumof the transition time and the fixed propagation delay of the output of the driving stage for the estimated capacitive load. 7-1387 Specifications CD40174BMS TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER SYMBOL Supply Current IDD CONDITIONS NOTES TEMPERATURE MIN MAX UNITS 1, 4 +25oC - 7.5 µA 1, 4 +25oC -2.8 -0.2 V VDD = 10V, ISS = -10µA 1, 4 +25oC - ±1 V VDD = 20V, VIN = VDD or GND N Threshold Voltage VNTH N Threshold Voltage Delta ∆VTN P Threshold Voltage VTP VSS = 0V, IDD = 10µA 1, 4 +25oC 0.2 2.8 V P Threshold Voltage Delta ∆VTP VSS = 0V, IDD = 10µA 1, 4 +25oC - ±1 V 1 +25oC VOH > VDD/2 VOL < VDD/2 V 1, 2, 3, 4 +25oC - 1.35 x +25oC Limit ns Functional F VDD = 10V, ISS = -10µA VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Propagation Delay Time TPHL TPLH VDD = 5V 3. See Table 2 for +25oC limit. NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. Read and Record TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC PARAMETER SYMBOL DELTA LIMIT Supply Current - MSI-1 IDD ± 0.2µA Output Current (Sink) IOL5 ± 20% x Pre-Test Reading IOH5A ± 20% x Pre-Test Reading Output Current (Source) TABLE 6. APPLICABLE SUBGROUPS MIL-STD-883 METHOD GROUP A SUBGROUPS Initial Test (Pre Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A 100% 5004 1, 7, 9, Deltas 100% 5004 1, 7, 9 100% 5004 1, 7, 9, Deltas 100% 5004 2, 3, 8A, 8B, 10, 11 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroup B-6 Sample 5005 1, 7, 9 Sample 5005 1, 2, 3, 8A, 8B, 9 CONFORMANCE GROUP PDA (Note 1) Interim Test 3 (Post Burn-In) PDA (Note 1) Final Test Group A Group B Group D READ AND RECORD IDD, IOL5, IOH5A Subgroups 1, 2, 3, 9, 10, 11 Subgroups 1, 2 3 NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2. TABLE 7. TOTAL DOSE IRRADIATION CONFORMANCE GROUPS Group E Subgroup 2 TEST READ AND RECORD MIL-STD-883 METHOD PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD 5005 1, 7, 9 Table 4 1, 9 Table 4 7-1388 Specifications CD40174BMS TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION OPEN GROUND Static Burn-In 1 (Note 1) 2, 5, 7, 10, 12, 15 1, 3, 4, 6, 8, 9, 11, 13, 14 Static Burn-In 2 (Note 1) 2, 5, 7, 10, 12, 15 8 1, 3, 4, 6, 9, 11, 13, 14, 16 Dynamic Burn-In (Note 1) - 8 1, 16 2, 5, 7, 10, 12, 15 8 1, 3, 4, 6, 9, 11, 13, 14, 16 Irradiation (Note 2) 9V ± -0.5V 50kHz 25kHz 2, 5, 7, 10, 12, 15 9 3, 4, 6, 11, 13, 14 VDD 16 NOTE: 1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V ± 0.5V Logic Diagram CL CL p p n n Q VDD D 3 (4, 6, 11, 13, 14) CL CL CL CL p p n n CL CL 2 (5, 7, 10, 12, 15) VSS CLR* 1 CL CLK* CL 9 * All inputs (terms 1, 3, 4, 6, 9, 11, 13, 14) protected by COS/MOS protection network FIGURE 1. 1 OF 6 FLIP-FLOPS TRUTH TABLE FOR 1 OF 6 FLIP-FLOPS INPUTS CLOCK X OUTPUT DATA CLEAR Q 0 1 0 1 1 1 X 1 NC X 0 0 1 = High Level X = Don’t Care 2 = Low Level NC = No Change All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 1389 CD40174BMS Typical Performance Curves OUTPUT LOW (SINK) CURRENT (IOL) (mA) 200 SUPPLY VOLTAGE (VDD) = 5V 150 100 10V 15V 50 0 0 20 30 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 25 20 15 10V 10 5 5V 0 40 60 80 100 LOAD CAPACITANCE (CL) (pF) 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE 2. TYPICAL TRANSITION TIME AS A FUNCTION OF LOAD CAPACITANCE FIGURE 3. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 AMBIENT TEMPERATURE (TA) = +25oC 0 AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V 15.0 0 -5 GATE-TO-SOURCE VOLTAGE (VGS) = 15V -10 12.5 -15 10.0 -10V 10V 7.5 -20 -25 5.0 -15V 2.5 -30 5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE 4. MINIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS AMBIENT TEMPERATURE (TA) = +25oC 0 0 GATE-TO-SOURCE VOLTAGE (VGS) = -5V -5 -10V -15V -10 -15 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 FIGURE 5. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS POWER DISSIPATION PER FLIP-FLOP (PD) (µW) OUTPUT LOW (SINK) CURRENT (IOL) (mA) AMBIENT TEMPERATURE (TA) = +25oC OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) TRANSITION TIME (fTHL, fTLH) (ns) AMBIENT TEMPERATURE (TA) = +25oC FIGURE 6. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS 105 AMBIENT TEMPERATURE (TA) = +25oC 8 6 4 2 SUPPLY VOLTAGE (VDD) = 15V 104 8 6 4 10V 10V 2 103 8 6 4 5V 2 CL = 50pF CL = 15pF 102 8 6 4 2 10 2 1 4 6 8 2 4 6 8 2 4 6 8 2 10 103 102 CLOCK INPUT FREQUENCY (fCL) (kHz) 4 6 8 104 FIGURE 7. TYPICAL DYNAMIC POWER DISSIPATION AS A FUNCTION OF CLOCK FREQUENCY 7-1390 CD40174BMS PROPAGATION DELAY TIME (tPHL, tPLH) (ns) Typical Performance Curves (Continued) 200 AMBIENT TEMPERATURE (TA) = +25oC 175 SUPPLY VOLTAGE (VDD) = 5V 150 125 100 10V 75 15V 50 25 0 0 10 20 30 40 50 60 70 80 90 100 LOAD CAPACITANCE (CL) (pF) FIGURE 8. TYPICAL PROPAGATION DELAY TIME (CLOCK TO OUTPUT) AS A FUNCTION OF LOAD CAPACITANCE Waveform Pad Layout tr CL CLOCK INPUT VDD tf CL 90% 50% 10% tH(HL)* DATA INPUT tSU(HL)* tSU(LH)* tTLH tTHL OUTPUT tPLH tREM VDD CLEAR 0 0 tH(LH)* VDD 50% 0 VDD 90% 50% 10% 0 tPHL *(LH) OR (HL) OPTIONAL 50% FIGURE 9. DEFINITION OF SETUP, HOLD, PROPAGATION DELAY, AND REMOVAL TIMES DIMENSIONS AND PAD LAYOUT FOR CD40174BMSH The photographs and dimensions of each CMOS chip represent a chip when it is part of the wafer. When the wafer is separated into individual chips, the angle of cleavage may vary with respect to the chip face for different chips. The actual dimensions of the isolated chip, therefore, may differ slightly from the nominal dimensions shown. The user should consider a tolerance of -3 mils to +16 mils applicable to the nominal dimensions shown. Dimension in parenthesis are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch). METALLIZATION: PASSIVATION: BOND PADS: Thickness: 11kÅ − 14kÅ, AL. 10.4kÅ - 15.6kÅ, Silane 0.004 inches X 0.004 inches MIN DIE THICKNESS: 0.0198 inches - 0.0218 inches 7-1391