FDM3300NZ
Monolithic Common Drain N-Channel 2.5V Specified PowerTrench
MOSFET
General Description
Features
This dual N-Channel MOSFET has been designed
using Fairchild Semiconductor’s advanced Power
Trench process to optimize the RDS(ON) @ VGS = 2.5v on
special MicroFET lead frame with all the drains on one
side of the package.
• 10 A, 20 V
RDS(ON) = 23 mΩ @ VGS = 4.5 V
RDS(ON) = 28 mΩ @ VGS = 2.5 V
• > 2000v ESD Protection
Applications
• Low Profile – 1mm maximum – in the new package
MicroFET 3.3x3.3 mm
• Li-Ion Battery Pack
D1
D1
D2
D2
D2
S1
G1
S2
G2
1
8
2
7
3
6
4
5
MicroFET
Absolute Maximum Ratings
Symbol
VDSS
VGSS
ID
TA=25oC unless otherwise noted
Parameter
Ratings
PD
Drain-Source Voltage
Gate-Source Voltage
Drain Current – Continuous
– Pulsed
Power Dissipation (Steady State)
TJ, TSTG
Operating and Storage Junction Temperature Range
(Note 1a)
(Note 1a)
(Note 1b)
Thermal Characteristics
RθJA
RθJA
RθJC
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1b)
(Note 1)
Package Marking and Ordering Information
Device Marking
3300N
2003 Fairchild Semiconductor Corporation
Device
FDM3300NZ
Reel Size
7’’
20
±12
10
40
2.5
1.2
–55 to +150
52
108
5
Tape width
12mm
Units
V
V
A
W
°C
°C/W
Quantity
3000 units
FDM3300NZ Rev. E3 (W)
FDM3300NZ
February 2003
Symbol
Parameter
Off Characteristics
BVDSS
∆BVDSS
∆TJ
IDSS
IGSS
TA = 25°C unless otherwise noted
Drain–Source Breakdown
Voltage
Breakdown Voltage Temperature
Coefficient
Zero Gate Voltage Drain Current
Gate–Body Leakage,
On Characteristics
Test Conditions
VGS = 0 V,
ID = 250 µA
Min
20
ID = 250 µA, Referenced to 25°C
VDS = 16 V,
VGS = ±12 V,
Typ Max
Units
V
10.7
mV/°C
1
±10
µA
µA
0.9
–3
1.5
V
mV/°C
16
20
22
23
28
31
mΩ
VGS = 0 V
VDS = 0 V
(Note 2)
VGS(th)
∆VGS(th)
∆TJ
RDS(on)
Gate Threshold Voltage
Gate Threshold Voltage
Temperature Coefficient
Static Drain–Source
On–Resistance
ID(on)
gFS
On–State Drain Current
Forward Transconductance
VDS = VGS,
ID = 250 µA
ID = 250 µA, Referenced to 25°C
VGS = 4.5 V,
ID = 10A
VGS = 2.5 V,
ID = 9 A
VGS = 4.5 V, ID = 10A, TJ=125°C
VGS = 2.5 V,
VDS = 5 V
VDS = 5 V,
ID =10 A
0.6
10
35
A
S
1210
pF
330
pF
180
2.3
pF
Ω
Dynamic Characteristics
Ciss
Input Capacitance
Output Capacitance
VDS = 10 V,
f = 1.0 MHz
V GS = 0 V,
Coss
Crss
RG
Reverse Transfer Capacitance
Gate Resistance
V GS = 0 V,
f = 1.0 MHz
VDD = 10 V,
VGS = 4.5 V,
ID = 1 A,
RGEN = 6 Ω
Switching Characteristics
td(on)
Turn–On Delay Time
tr
Turn–On Rise Time
td(off)
Turn–Off Delay Time
tf
Turn–Off Fall Time
Qg
Total Gate Charge
Qgs
Gate–Source Charge
Qgd
Gate–Drain Charge
(Note 2)
VDS = 10 V,
VGS = 4.5 V
ID = 10 A,
10
20
ns
14
25
ns
26
42
ns
13
23
ns
12
17
nC
2
nC
4
nC
Drain–Source Diode Characteristics and Maximum Ratings
IS
VSD
trr
Qrr
Maximum Continuous Drain–Source Diode Forward Current
Drain–Source Diode Forward
VGS = 0 V, IS = 2 A
Voltage
IF = 10 A,
Diode Reverse Recovery Time
Diode Reverse Recovery Charge diF/dt = 100 A/µs
(Note 2)
0.7
2
1.2
A
V
20
nS
6
nC
Notes:
1. RθJA is determined with the device mounted on a 1 in² 2 oz. copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJC are guaranteed by design while RθJA is
determined by the user'
s board design.
(a). RθJA = 52°C/W when mounted on a 1in2 pad of 2 oz copper, 1.5” x 1.5” x 0.062” thick PCB
(b). RθJA = 108°C/W when mounted on a minimum pad of 2 oz copper
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%
FDM3300NZ Rev E3 (W)
FDM3300NZ
Electrical Characteristics
FDM3300NZ
Typical Characteristics
VGS = 4.5V
2
3.0V
RDS(ON), NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
40
ID, DRAIN CURRENT (A)
3.5V
30
2.5V
20
2.0V
10
1.8
VGS = 2.0V
1.6
1.4
2.5V
1.2
3.0V
0
0.5
1
1.5
0
2
4
8
12
16
20
ID, DRAIN CURRENT (A)
VDS, DRAIN-SOURCE VOLTAGE (V)
Figure 1. On-Region Characteristics.
Figure 2. On-Resistance Variation with
Drain Current and Gate Voltage.
0.047
1.6
ID = 5A
ID = 10A
VGS = 4.5V
RDS(ON), ON-RESISTANCE (OHM)
RDS(ON), NORMALIZED
DRAIN-SOURCE ON-RESISTANCE
4.5V
0.8
0
1.4
1.2
1
0.8
0.6
-50
-25
0
25
50
75
100
125
0.042
0.037
0.032
TA = 125oC
0.027
0.022
TA = 25oC
0.017
0.012
150
1
o
2
TJ, JUNCTION TEMPERATURE ( C)
3
4
5
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 3. On-Resistance Variation with
Temperature.
Figure 4. On-Resistance Variation with
Gate-to-Source Voltage.
100
TA = -55oC
VDS = 5V
IS, REVERSE DRAIN CURRENT (A)
40
ID, DRAIN CURRENT (A)
3.5V
1
25oC
30
125oC
20
10
0
VGS = 0V
10
TA = 125oC
1
25oC
0.1
0.01
-55oC
0.001
0.0001
0.5
1
1.5
2
2.5
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 5. Transfer Characteristics.
3
0
0.2
0.4
0.6
0.8
1
1.2
VSD, BODY DIODE FORWARD VOLTAGE (V)
Figure 6. Body Diode Forward Voltage Variation
with Source Current and Temperature.
FDM3300NZ Rev E3 (W)
FDM3300NZ
Typical Characteristics
1800
ID = 10A
VDS = 5V
4
1500
10V
CAPACITANCE (pF)
VGS, GATE-SOURCE VOLTAGE (V)
5
15V
3
2
1200
1
900
Coss
600
300
Crss
0
0
0
3
6
9
12
15
0
4
Qg, GATE CHARGE (nC)
8
16
20
Figure 8. Capacitance Characteristics.
50
RDS(ON) LIMIT
P(pk), PEAK TRANSIENT POWER (W)
100
100us
1ms
10
10ms
100ms
1s
10s
1
DC
VGS = 4.5V
SINGLE PULSE
RθJA = 108oC/W
0.1
TA = 25oC
0.01
0.1
1
10
100
SINGLE PULSE
RθJA = 108°C/W
TA = 25°C
40
30
20
10
0
0.001
0.01
0.1
1
10
100
1000
t1, TIME (sec)
VDS, DRAIN-SOURCE VOLTAGE (V)
Figure 9. Maximum Safe Operating Area.
r(t), NORMALIZED EFFECTIVE TRANSIENT
THERMAL RESISTANCE
12
VDS, DRAIN TO SOURCE VOLTAGE (V)
Figure 7. Gate Charge Characteristics.
ID, DRAIN CURRENT (A)
f = 1MHz
VGS = 0 V
Ciss
Figure 10. Single Pulse Maximum
Power Dissipation.
1
D = 0.5
RθJA(t) = r(t) * RθJA
RθJA =108 °C/W
0.2
0.1
0.1
0.05
0.01
P(pk)
0.02
0.01
t1
SINGLE PULSE
0.001
0.0001
0.001
t2
TJ - TA = P * RθJA(t)
Duty Cycle, D = t1 / t2
0.01
0.1
1
10
100
1000
t1, TIME (sec)
Figure 11. Transient Thermal Response Curve.
Thermal characterization performed using the conditions described in Note 1b.
Transient thermal response will change depending on the circuit board design.
FDM3300NZ Rev E3 (W)
.SUBCKT FDM3300NZ 2 1 3
*NOM TEMP=25 DEG C
*FEB 26, 2003
CA 12 8 1E-9
CB 15 14 1.2E-9
CIN 6 8 10.8E-10
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
DRAIN
2
RSLC2
5
51
GATE
1
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 8.3E-3
RGATE 9 20 4.2
RSLC1 5 51 RSLCMOD 1E-6
RSLC2 5 50 1E3
RSOURCE 8 7 RSOURCEMOD 3.9E-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
11
+
RDRAIN
6
8
EVTHRES
+ 19 8
EVTEMP
RGATE +
18 9
20 22
21
EBREAK
16
17
18
-
DBODY
MWEAK
6
MMED
MSTRO
RLGATE
LSOURCE
CIN
RLGATE 1 9 38.4
RLDRAIN 2 5 10
RLSOURCE 3 7 40
ESLC
-
+
LGATE
DBREAK
50
ESG
RLDRAIN
RSLC1
51
+
LGATE 1 9 3.84E-9
LDRAIN 2 5 1.00E-9
LSOURCE 3 7 4E-9
5
10
EBREAK 11 7 17 18 23.3
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
IT 8 17 1
LDRAIN
DPLCAP
8
7
RSOURCE
S1A
12
13
S2A
S1B
CA
17
18
S2B
13
RVTEMP
CB
6
8
-
19
VBAT
+
IT
14
+
+
EGS
RLSOURCE
RBREAK
15
14
13
8
SOURC E
3
5
8
EDS
-
8
22
RVTHRES
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1E-6*115),3))}
.MODEL DBODYMOD D (IS=2E-12 RS=9.9E-3 N=0.90 TRS1=2.1E-3 TRS2=1.0E-6 CJO=4.5E-10 TT=1E-9 M=0.45 IKF=0.3 XTI=2.0)
.MODEL DBREAKMOD D (RS=1E-1 TRS1=1.12E-3 TRS2=1.25E-6)
.MODEL DPLCAPMOD D (CJO=45E-11 IS=1E-30 N=10 M=0.4)
.MODEL MMEDMOD NMOS (VTO=1.05 KP=8 IS=1E-30 N=10 TOX=1 L=1U W=1U RG=4.2)
.MODEL MSTROMOD NMOS (VTO=1.31 KP=82 IS=1E-30 N=10 TOX=1 L=1U W=1U)
.MODEL MWEAKMOD NMOS (VTO=0.81 KP=0.05 IS=1E-30 N=10 TOX=1 L=1U W=1U RG=42 RS=.1)
.MODEL RBREAKMOD RES (TC1=0.56E-3 TC2=1.00E-7)
.MODEL RDRAINMOD RES (TC1=4.6E-3 TC2=10E-6)
.MODEL RSLCMOD RES (TC1=2.5E-3 TC2=8E-6)
.MODEL RSOURCEMOD RES (TC1=1.0E-3 TC2=1E-6)
.MODEL RVTHRESMOD RES (TC1=-1.85E-3 TC2=-7E-6)
.MODEL RVTEMPMOD RES (TC1=-0.7E-3 TC2=0.50E-6)
.MODEL S1AMOD VSWITCH (RON=1E-5 ROFF=0.1 VON=-4 VOFF=-3)
.MODEL S1BMOD VSWITCH (RON=1E-5 ROFF=0.1 VON=-3 VOFF=-4)
.MODEL S2AMOD VSWITCH (RON=1E-5 ROFF=0.1 VON=-1.0 VOFF=0.6)
.MODEL S2BMOD VSWITCH (RON=1E-5 ROFF=0.1 VON=0.6 VOFF=-1.0)
.ENDS
Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET
Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by
William J. Hepp and C. Frank Wheatley.
FDM3300NZ Rev E3 (W)
FDM3300NZ
PSPICE Electrical Model N-Channel
FDM3300NZ
SPICE Thermal Model
.SUBCKT FDM3300NZ_THERM TH TL
*Thermal Model Subcircuit
*Feb 26, 2003
th
JUNCTION
CTHERM1 TH 8 3
CTHERM2 8 7 5
RTHERM1
CTHERM3 7 6 7
CTHERM4 6 5 13.2
CTHERM1
8
RTHERM2
CTHERM2
CTHERM5 5 4 25.4
7
CTHERM6 4 3 36.21
CTHERM7 3 2 47.54
RTHERM3
CTHERM3
6
CTHERM8 2 TL 208.21
RTHERM4
RTHERM1 TH 8 0.04
CTHERM4
5
RTHERM2 8 7 0.05
RTHERM3 7 6 0.06
RTHERM5
4
RTHERM4 6 5 0.07
RTHERM5 5 4 0.085
RTHERM6
RTHERM7
RTHERM8 2 TL 0.35
.ENDS
CTHERM6
3
RTHERM6 4 3 0.095
RTHERM7 3 2 0.25
CTHERM5
CTHERM7
2
RTHERM8
CTHERM8
tl
AMBIENT
FDM3300NZ Rev E3 (W)
FDM3300NZ
Dimensional Outline and Pad Layout
FDM3300NZ Rev E3 (W)
TRADEMARKS
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NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
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OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
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FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
2. A critical component is any component of a life
1. Life support devices or systems are devices or
support device or system whose failure to perform can
systems which, (a) are intended for surgical implant into
be reasonably expected to cause the failure of the life
the body, or (b) support or sustain life, or (c) whose
support device or system, or to affect its safety or
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
effectiveness.
reasonably expected to result in significant injury to the
user.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or
In Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
No Identification Needed
Full Production
This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.
Obsolete
Not In Production
This datasheet contains specifications on a product
that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Rev. I2