Intel® EP80579 Integrated Processor
Product Line
Datasheet
Order Number: 320066-003US
August 2009
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Intel® EP80579 Integrated Processor Product Line Datasheet
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Order Number: 320066-003US
Product Features
System on a Chip (SoC)
— Integrated Intel® Architecture (IA) processor
and chipset (MCH/ICH) technology
— Extensive integration of standard Intel
architecture communications interfaces
provide cost, power and board area savings
(Gigabit Ethernet (GbE), Time Division
Multiplexing (TDM)‡ processing, Security
Services Unit (SSU),‡ and Acceleration
Services Units (ASU)‡)
Intel Architecture Processor
— Low-power and high-performance architecture
based on Intel Architecture (IA-32) processor
— Three operating frequency SKUs:
- 600 MHz, 1066 MHz, or 1200 MHz
— 256 KB L2 data coherent cache (2 way)
Integrated Memory Control Hub (IMCH) and
Integrated I/O Control Hub (IICH) Compatible
—
—
—
—
—
—
—
—
—
—
Enhanced DMA (EDMA) controller
Two SATA Gen1 or Gen2 interfaces
Two USB 1.1 or USB 2.0 ports
Two integrated, 16550-compatible UARTs
LPC 1.1 interface
Serial Peripheral Interface (SPI)†
Two SMBus 2.0 compliant interfaces
GPIOs
Watchdog Timer
One 32/64-bit and two 32-bit high-precision
event timers
Acceleration Services Unit
(ASU)‡
— High performance accelerator on-chip engines
for packet processing
— Support capabilities for commonly used
protocol implementations such as TCP/IP, UDP,
IPSec, SSL, NAT, and SRTP
Security Services Unit (SSU)‡
— High-performance on-chip Crypto Accelerator
— Support capabilities for commonly used
cryptographic protocol implementations
†
‡
Single-Channel Double-Data-Rate (DDR)
SDRAM Memory
— Supports DDR2 at 400/533/667/800 MT/s
— Supports 32 or 64-bit interfaces
— Error correction code (ECC); single-bit correct/
double-bit detect (SEC/DED) coverage
— Addressable from Intel architecture processor
and PCI Express
Three Gigabit Ethernet MACs
— Three 10/100/1000 ports with RGMII/RMII
interfaces
— MDIO interface for external PHY configuration
— Serial EEPROM interface supports network
boot and wake-on LAN
SKU Support1
— Embedded: Intel architecture compatibility
and high-speed interfaces (GbEs, PCI
Express*)
— Application Services: Security — Packet
security compatibility and IP Telephony packet
security, TDM, and High-Level Data Link
Control (HDLC)
Industry Standard PCI Express Interface
— Supports 1x8, 2x4, or 2x1 configurations as a
root complex
Integrated Serial ATA (SATA) Host Controllers
— Independent DMA operation on two ports
— Data transfer rates up to 3.0 Gb/s
— Alternate Device ID
Integrated High-speed Serial Interface (TDM)‡
— Supports up to 12 external T1/E1 and codecs
— Supports up to 128 HDLC channels
Local Expansion Bus (LEB)
— Supports up to eight chip selects
— 25-bit address and 16-bit data
— Supports HPI-8 and HPI-16
Dual Controller Area Network (CAN)
— Supports two CAN 2.0b interfaces
Single Synchronous Serial Port (SSP)
Compatible
IEEE 1588-2008 Hardware Assistance
— Supports two GbE and two CAN interfaces
— Time master/target support
1088-Ball FCBGA package
— Dimensions of 37.5 mm x 37.5 mm
— 1.092-mm solder ball pitch
— Lead-free only — RoHS 5/6 compliant
Typical Applications
— Embedded, Security and/or IP Telephony
applications
Intel recommends using the SPI for Pre-boot firmware
due to the reduced availability of LPC FWH.
Feature must be enabled with EP80579 software. Refer
to the EP80579 software documentation for more
information.
1. For complete information about product features and SKUs, please refer to Chapter 47.0, “SKUs, Power Savings and Pre-Boot
Firmware”.
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Contents
Contents
Introduction and Overview, Volume 1 of 6 ................................... 91
1.0
Introduction ............................................................................................................93
1.1
Introduction ......................................................................................................93
1.2
Document Organization ......................................................................................93
1.3
Referenced Documents and Related Websites ........................................................94
1.4
Acronyms .........................................................................................................95
1.5
Glossary ...........................................................................................................98
2.0
Architectural Overview .......................................................................................... 103
2.1
Overview ........................................................................................................ 103
2.1.1
Block Summary ...................................................................................... 103
2.1.2
External Interfaces ................................................................................. 106
2.1.3
Frequencies and Gear Ratios .................................................................... 107
2.2
Signaling Architecture ...................................................................................... 107
2.3
DMA and Peer-to-Peer Data Transfers................................................................. 109
3.0
Platform Memory and Device Configuration ........................................................... 111
3.1
Overview ........................................................................................................ 111
3.1.1
Configuration Objectives.......................................................................... 111
3.1.2
Terminology and Conventions .................................................................. 112
3.2
IA Platform Infrastructure ................................................................................. 113
3.2.1
IA Platform View of Endianness ................................................................ 113
3.2.2
IA Platform View of Configuration ............................................................. 114
3.3
High-Level Views ............................................................................................. 116
3.3.1
Characteristics of External System Memory (DRAM) .................................... 116
3.3.2
Characteristics of Internal and External Memories ....................................... 117
3.3.3
Characteristics of Device Configuration ...................................................... 118
3.4
Memory Map for IA-Attached Agents .................................................................. 119
3.5
Memory Map for AIOC-Attached Devices ............................................................. 119
3.6
Endianness ..................................................................................................... 119
3.7
PCI Configuration............................................................................................. 119
3.7.1
Overview............................................................................................... 120
3.7.2
Device Tree ........................................................................................... 121
3.7.3
Materializing Device Structures................................................................. 124
3.7.4
PCI Configuration Headers ....................................................................... 124
4.0
Signaling................................................................................................................ 131
4.1
Overview ........................................................................................................ 131
4.1.1
Terminology and Conventions .................................................................. 132
4.2
Existing Signaling Capabilities............................................................................ 132
4.2.1
IA-32 core/Platform ................................................................................ 133
4.2.1.1
MSI and INTx Signaling.................................................................... 133
4.2.1.2
GPIO Signaling ............................................................................... 133
4.2.2
Other Agents ......................................................................................... 133
4.3
Inter-Agent Signaling ....................................................................................... 134
4.3.1
Signaling that Travels Around the Signal Bridge .......................................... 135
4.3.2
Signaling that is Bridged from a Side-Band Source Signal ............................ 135
4.3.2.1
Targeting the IA-32 core with a Bridged Signal.................................... 136
5.0
Error Handling ....................................................................................................... 139
5.1
Overview ........................................................................................................ 139
5.2
EP80579 View of Error Reporting ....................................................................... 139
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Contents
5.2.1
5.2.2
5.3
Error
5.3.1
5.3.2
5.3.3
5.3.4
5.3.5
5.3.6
5.3.7
5.3.8
5.4
Error
5.4.1
5.4.2
5.4.3
5.4.4
5.4.5
5.4.6
5.5
Error
5.5.1
5.5.2
5.6
Error
5.6.1
5.6.2
5.6.3
5.6.4
5.6.5
Hardware Capabilities ............................................................................. 139
Software Usage Model ............................................................................ 141
Reporting by the IMCH ............................................................................. 141
Overview of the First and Next Error Architecture ....................................... 141
Global Error Events ................................................................................ 142
Unit-Level Errors from the Buffer Unit ....................................................... 143
Unit-Level Errors from the DRAM Interface ................................................ 143
Unit-Level Errors from the FSB Interface ................................................... 144
Unit-Level Errors from the NSI ................................................................. 145
Unit-Level Errors from the EDMA Engine.................................................... 146
Unit-Level Errors from PCI Express* Ports A0 and A1 .................................. 147
Reporting by the IICH .............................................................................. 149
SMBus Interface .................................................................................... 149
LPC Interface......................................................................................... 150
USB 1.1 Interface .................................................................................. 151
USB 2.0 Interface .................................................................................. 151
SATA Interface ...................................................................................... 152
Serial I/O Interface ................................................................................ 153
Reporting by the System Memory Controller ............................................... 153
Handling Out-of-Bounds Addresses........................................................... 154
IMCH - Memory Controller ....................................................................... 154
Reporting by AIOC Devices ....................................................................... 155
Gigabit Ethernet MAC ............................................................................. 155
CAN Interface ........................................................................................ 156
SSP Interface ........................................................................................ 157
Local Expansion Bus ............................................................................... 158
IEEE 1588, and GCU............................................................................... 159
6.0
Reset and Power Management............................................................................... 161
6.1
Reset and Powergood Distribution ..................................................................... 161
6.1.1
Types of Reset....................................................................................... 161
6.1.1.1
Powergood Implementation.............................................................. 161
6.1.1.2
Hard Reset Implementation.............................................................. 162
6.1.1.3
Software Controlled Reset................................................................ 162
6.1.1.4
CPU Only Reset Implementation ....................................................... 162
6.1.1.5
S-state Wake Events ....................................................................... 163
6.1.1.6
Targeted Reset Implementation ........................................................ 163
6.1.2
Platform Reset and Powergood................................................................. 163
6.1.2.1
Platform Powergood ........................................................................ 163
6.1.2.2
Platform Reset................................................................................ 163
6.1.2.3
Reset and Powergood Distribution ..................................................... 164
6.1.3
EP80579 Power Sequencing and Reset Sequence........................................ 167
6.2
BIOS Boot Flow (Initialization) .......................................................................... 175
6.2.1
Memory Configuration............................................................................. 176
6.2.2
Memory Initialization .............................................................................. 176
6.2.3
Boot from Network ................................................................................. 176
6.3
Power Management ......................................................................................... 177
6.3.1
Power Management States ...................................................................... 177
6.3.2
Power Management Support .................................................................... 179
6.3.2.1
Transitioning Between Power States .................................................. 181
6.3.2.2
Power State Transition Timing Diagrams ............................................ 181
6.3.3
Thermal Sensor ..................................................................................... 182
6.3.4
ACPI Implementation.............................................................................. 182
7.0
Register Summary ................................................................................................. 183
7.1
Overview of Register Descriptions and Summaries ............................................... 183
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Contents
7.1.1
Register Description Tables ...................................................................... 183
7.1.2
Register Field Access Attributes ................................................................ 189
7.1.3
Register Nomenclature and Values ............................................................ 189
7.1.4
“Sticky” Register Fields............................................................................ 190
7.2
IA-32 core Registers ........................................................................................ 190
7.3
IMCH and IICH Registers .................................................................................. 191
7.3.1
IMCH Registers: Bus 0, Device 0, Function 0 ............................................. 191
7.3.2
IMCH Error Reporting Registers: Bus 0, Device 0, Function 1 ........................ 195
7.3.3
EDMA Engine Registers: Bus 0, Device 1, Function 0 ................................... 197
7.3.4
PCI Express* Port A Registers: Bus 0, Device 2, Function 0 ......................... 200
7.3.5
PCI Express* Port A1 Registers: Bus 0, Device 3, Function 0 ........................ 203
7.3.6
USB (1.1) Controller: Bus 0, Device 29, Functions 0 ................................... 206
7.3.7
USB (2.0) Controller: Bus 0, Device 29, Function 7 .................................... 207
7.3.8
Root Complex: Bus 0, Device 31, Function 0 ............................................. 209
7.3.9
LPC Interface: Bus 0, Device 31, Function 0 .............................................. 210
7.3.10
SATA Controller: Bus 0, Device 31, Function 2............................................ 213
7.3.11
SMBus Controller: Bus 0, Device 31, Function 3.......................................... 216
7.3.12
IA-32 Core Interface I/O-Mapped Register ................................................. 217
7.3.13
IMCH PCI Configuration ........................................................................... 217
7.3.14
APIC ..................................................................................................... 217
7.3.15
8259 Interrupt Controller (PIC) ................................................................ 219
7.3.16
APM Power Management.......................................................................... 219
7.3.17
LPC DMA ............................................................................................... 220
7.3.18
8254 Timers .......................................................................................... 221
7.3.19
High Precision Event Timers ..................................................................... 222
7.3.20
Watchdog Timer and Serial I/O................................................................. 222
7.3.21
Real Time Clock...................................................................................... 223
7.4
AIOC Registers ................................................................................................ 224
7.4.1
PCI-to-PCI Bridge: Bus 0, Device 4, Function 0........................................... 224
7.4.2
Gigabit Ethernet MAC: Bus M, Devices 0, 1, and 2, Function 0 ..................... 226
7.4.3
GCU: Bus M, Device 3, Function 0............................................................. 240
7.4.4
CAN Interface: Bus M, Device 4 and 5, Function 0 ...................................... 242
7.4.5
SSP Interface: Bus M, Device 6, Function 0 ............................................... 245
7.4.6
IEEE 1588 Timestamp Unit: Bus M, Device 7, Function 0 ............................. 247
7.4.7
Local Expansion Bus Interface: Bus M, Device 8, Function 0: ....................... 249
IA-32 Core and Integrated Memory Controller Hub,
Volume 2 of 6.............................................................................. 251
8.0
IA-32 Core ............................................................................................................. 253
8.1
Overview ........................................................................................................ 253
8.2
Theory of Operation ......................................................................................... 253
8.2.1
L2 Cache Size ........................................................................................ 253
8.2.2
Platform and JTAG Identifiers ................................................................... 253
8.2.3
FSB Physical Interface ............................................................................. 254
8.2.4
IA-32 Core and FSB Frequency ................................................................. 254
9.0
CMI Introduction ................................................................................................... 255
9.1
System Architecture......................................................................................... 256
9.2
PCI Express*................................................................................................... 256
9.2.1
Supported PCI Express Configurations ....................................................... 257
9.2.1.1
Low power SKU with PCI Express ports removed ................................. 257
9.3
Supported Debug and Management Interfaces ..................................................... 257
9.4
Supported IMCH Integrated Features.................................................................. 257
9.4.1
EDMA Controller ..................................................................................... 257
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Contents
9.4.2
Integrated Memory Init/Test Engine ......................................................... 258
9.4.3
Coherent Memory Write Buffer ................................................................. 258
9.4.4
RASUM Features .................................................................................... 258
9.4.4.1
SEC-DED ECC................................................................................. 259
9.4.4.2
Integrated Memory Scrub Engine ...................................................... 259
9.5
IMCH Feature List........................................................................................... 259
9.5.1
Memory Interface................................................................................... 259
9.5.2
PCI Express Interface in IMCH ................................................................. 259
9.5.3
EDMA Controller..................................................................................... 261
9.5.4
Coherent Memory Write Buffer ................................................................. 262
9.5.5
Integrated Memory Scrub Engine ............................................................. 262
9.5.6
Hardware Memory Initialization Engine...................................................... 262
9.5.7
System Management Functions ................................................................ 263
9.5.8
RASUM ................................................................................................. 263
9.6
IICH Feature List............................................................................................. 264
9.6.1
Low-Pin count (LPC) Interface and Firmware Hub (FWH) Interface ................ 264
9.6.2
Serial Peripheral Interface (SPI) ............................................................... 264
9.6.3
Integrated Serial ATA Host Controllers ...................................................... 264
9.6.4
USB .................................................................................................... 264
9.6.5
Interrupt Controller ................................................................................ 264
9.6.6
Power Management Logic ....................................................................... 265
9.6.7
DMA Controller ...................................................................................... 265
9.6.8
Timers Based on 82C54 .......................................................................... 265
9.6.9
High Precision Event Timers (HPET) .......................................................... 265
9.6.10
Real-Time Clock with 256-byte Battery-backed CMOS RAM .......................... 265
9.6.11
System TCO Reduction Circuits ............................................................... 265
9.6.12
SMBus .................................................................................................. 265
9.6.13
Watchdog Timer..................................................................................... 266
9.6.14
Serial Port............................................................................................. 266
9.6.15
GPIO .................................................................................................... 266
10.0 System Address Map ............................................................................................. 267
10.1 Overview ....................................................................................................... 267
10.1.1
System Memory Spaces .......................................................................... 268
10.1.2
VGA and MDA Memory Spaces ................................................................. 268
10.1.3
PAM Memory Spaces............................................................................... 270
10.1.4
TSEG SMM Memory Space ....................................................................... 274
10.1.5
PCI Express Enhanced Configuration Aperture ............................................ 274
10.1.6
IOAPIC Memory Space ............................................................................ 275
10.1.7
FSB Interrupt Memory Space ................................................................... 275
10.1.8
High SMM Memory Space ........................................................................ 276
10.1.9
PCI Device Memory (MMIO) ..................................................................... 276
10.1.9.1
Device 2 Memory and Prefetchable Memory........................................ 277
10.1.9.2
Device 3 Memory and Prefetchable Memory........................................ 277
10.1.9.3
Device 4 Memory and Prefetchable Memory........................................ 277
10.2 IMCH Responses to EDMA Transactions .............................................................. 278
10.2.1
Fixed Address Spaces (EDMA).................................................................. 278
10.2.2
Relocatable Address Spaces (EDMA) ......................................................... 278
10.3 I/O Address Space........................................................................................... 279
10.3.1
Configuration Window ............................................................................. 279
10.3.2
VGA and MDA Regions ............................................................................ 280
10.4 Main Memory Addressing.................................................................................. 281
10.5 System Management Mode (SMM) Space............................................................ 281
10.5.1
SMM Addressing Ranges ......................................................................... 281
10.5.1.1
SMM Space Restrictions ................................................................... 281
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Contents
10.5.1.2
SMM Space Definition ...................................................................... 282
10.6 Memory Reclaim Background............................................................................. 283
10.6.1
Memory Remapping Algorithm.................................................................. 283
10.7 IICH Register and Memory Mappings .................................................................. 284
10.7.1
I/O Map ................................................................................................ 284
10.7.1.1
Fixed I/O Address Ranges ................................................................ 284
10.7.1.2
Variable I/O Decode Ranges ............................................................. 286
10.7.2
Memory Map .......................................................................................... 287
10.7.3
Boot-Block Update Scheme ...................................................................... 288
11.0 System Memory Controller ..................................................................................... 289
11.1 Overview ........................................................................................................ 289
11.2 Memory Controller Feature List .......................................................................... 289
11.3 Configurations ................................................................................................. 291
11.3.1
Rules for Populating DIMM Slots ............................................................... 293
11.3.2
DRAM Addressing ................................................................................... 294
11.3.3
Memory Address Translation Tables .......................................................... 295
11.3.3.1
DDR2 Address Translation Tables ...................................................... 295
11.3.4
DRAM Timings........................................................................................ 296
11.3.4.1
2T Timing Mode .............................................................................. 297
11.3.5
DQ/DQS Mapping ................................................................................... 298
11.3.6
32-Bit Mode ........................................................................................... 298
11.4 DDR2 Features ................................................................................................ 298
11.4.1
Interface Signalling Voltage ..................................................................... 298
11.4.2
On-DIMM Die Termination (ODT) .............................................................. 299
11.4.2.1
ODT Control of Reads ...................................................................... 300
11.4.2.2
ODT Control of Writes ...................................................................... 300
11.4.3
On-Die Termination (ODTZ) on the EP80579 ............................................. 301
11.4.4
Refresh ................................................................................................. 302
11.4.5
Self-Refresh........................................................................................... 302
11.4.6
RCOMP.................................................................................................. 303
11.4.7
DDR2 MR and EMR settings...................................................................... 303
11.4.8
Scrubbing Support .................................................................................. 304
11.4.8.1
Demand Scrubbing .......................................................................... 304
11.4.8.2
Background Scrubbing ..................................................................... 304
11.5 Error Handling................................................................................................. 304
12.0 Enhanced Direct Memory Access Controller (EDMA) ............................................... 307
12.1 Overview ........................................................................................................ 307
12.1.1
Features................................................................................................ 308
12.1.2
Logical Block Diagram ............................................................................. 309
12.2 Channel Programming Interface......................................................................... 310
12.3 Chaining Operation .......................................................................................... 311
12.3.1
Chain Descriptor Definition ...................................................................... 311
12.3.2
DMA Chain Descriptor in Memory .............................................................. 312
12.3.3
Chain Descriptor Usage ........................................................................... 312
12.3.4
Scatter/Gather Transfer........................................................................... 314
12.3.5
Appending to a Descriptor Chain ............................................................... 314
12.3.6
Splicing a Descriptor Chain into a Linked List.............................................. 315
12.4 Transfer Types ................................................................................................ 316
12.4.1
Local Memory to Local Memory................................................................. 316
12.4.2
Local Memory to I/O Subsystem Memory ................................................... 316
12.4.3
I/O Memory to Local Memory ................................................................... 317
12.4.4
I/O Memory to I/O Memory...................................................................... 317
12.5 Addressing...................................................................................................... 317
12.5.1
Address Coherence ................................................................................. 317
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Contents
12.5.2
Addressing Modes .................................................................................. 318
12.5.2.1
Standard Byte Movement Mode ........................................................ 318
12.5.2.2
Decrement/Byte Reversal Mode ....................................................... 319
12.5.2.3
Constant Address Modes .................................................................. 320
12.5.2.4
Buffer and Memory Initialization Modes.............................................. 326
12.5.3
PCI Express Traffic Class ......................................................................... 329
12.6 Channel Data Queuing ..................................................................................... 329
12.7 Error Conditions .............................................................................................. 329
12.7.1
Controller Interface Error ........................................................................ 330
12.7.2
Memory Interface Error........................................................................... 330
12.7.3
I/O Interface Error ................................................................................. 331
12.8 Channel Arbitration.......................................................................................... 331
12.8.1
Normal Arbitration Scheme...................................................................... 331
12.8.2
Prioritized Arbitration Scheme.................................................................. 332
12.9 Configuration .................................................................................................. 332
12.9.1
Power Up/Default Status ......................................................................... 333
12.9.2
Channel-Specific Register Definitions ........................................................ 333
12.9.2.1
Channel Control Register – CCR ........................................................ 333
12.9.2.2
Channel Status Register – CSR ......................................................... 334
12.9.2.3
Current Descriptor Address Register – CDAR ...................................... 334
12.9.2.4
Current Descriptor Upper Address Register – CDUAR ........................... 334
12.9.2.5
Source Address Register – SAR......................................................... 335
12.9.2.6
Source Upper Address Register – SUAR ............................................. 335
12.9.2.7
Destination Address Register – DAR .................................................. 335
12.9.2.8
Destination Upper Address Register – DUAR ....................................... 335
12.9.2.9
Next Descriptor Address Register – NDAR .......................................... 335
12.9.2.10 Next Descriptor Upper Address Register – NDUAR ............................... 336
12.9.2.11 Transfer Count Register – TCR.......................................................... 336
12.9.2.12 Descriptor Control Register – DCR..................................................... 336
12.10 Interrupts ...................................................................................................... 337
12.10.1 Interrupt Routing Mechanisms ................................................................. 338
12.10.2 Message Signaled Interrupt (MSI) ............................................................ 339
12.10.2.1 MSI Control Register – MSICR .......................................................... 339
12.10.2.2 MSI Address Register – MSIAR ......................................................... 339
12.10.2.3 MSI Data Register – MSIDR.............................................................. 340
12.10.3 Interrupt Ordering.................................................................................. 340
12.10.3.1 Interrupt Ordering for Memory Destination ......................................... 340
12.10.3.2 Interrupt Ordering for Outbound Destination ...................................... 340
12.11 Initiating an EDMA Transfer .............................................................................. 341
12.11.1 Setup and Initiation................................................................................ 341
12.11.2 Suspend Function................................................................................... 342
12.11.3 Stop Function ........................................................................................ 342
12.11.4 EDMA Process Flow ................................................................................ 343
13.0 Platform Configuration .......................................................................................... 345
13.1 RASUM Features - SMBus Access ....................................................................... 345
13.2 Platform Configuration Structure Conceptual Overview ......................................... 345
13.2.1
IMCH PCI Devices .................................................................................. 346
13.2.2
IICH PCI Devices.................................................................................... 347
13.3 Routing Configuration Accesses ......................................................................... 349
13.3.1
Standard PCI Bus Configuration Mechanism ............................................... 349
13.3.2
PCI Bus #0 Configuration Mechanism........................................................ 350
13.3.3
Primary PCI and Downstream Configuration Mechanism .............................. 350
13.3.4
IMCH PCI Express Bus Configuration Mechanism ........................................ 351
13.3.5
IMCH Configuration Cycle Flow Chart ....................................................... 352
13.4 IMCH Register Introduction............................................................................... 353
13.5 IMCH Sticky Registers...................................................................................... 353
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Intel® EP80579 Integrated Processor Product Line Datasheet
9
Contents
13.6
IMCH I/O Mapped Registers .............................................................................. 354
13.6.0.1
Offset 0CF8h: CONFIG_ADDRESS - Configuration Address Register ........ 354
13.6.0.2
Offset 0CFCh: CONFIG_DATA - Configuration Data Register .................. 355
13.7 IMCH Memory Mapped Registers ........................................................................ 355
13.8 PCI Express Enhanced Configuration Mechanisms................................................. 356
13.8.1
PCI Express Configuration Transaction Header ............................................ 356
13.8.2
Enhanced Configuration Hardware Implications........................................... 356
13.8.3
Enhanced Configuration Memory Address Map ............................................ 357
13.8.4
Enhanced Configuration FSB Address Format.............................................. 357
14.0 RAS Features and Exception Handling .................................................................... 359
14.1 RAS Features .................................................................................................. 359
14.1.1
Data Protection ...................................................................................... 359
14.1.1.1
DRAM ECC ..................................................................................... 359
14.1.1.2
PCI Express Interface ...................................................................... 359
14.1.1.3
Data Error Propagation Between Interfaces/Units ................................ 359
14.1.2
DRAM Data Integrity ............................................................................... 360
14.1.2.1
Periodic Memory Scrubbing............................................................... 360
14.1.2.2
DRAM Hardware Initialization ............................................................ 360
14.1.2.3
Uncorrectable Retries....................................................................... 360
14.1.2.4
DRAM Refresh................................................................................. 361
14.1.2.5
DDR I/O Hardware Assisted Calibration .............................................. 361
14.1.3
PCI Express Data Integrity ....................................................................... 361
14.1.3.1
PCI Express Training........................................................................ 361
14.1.3.2
PCI Express Retry ........................................................................... 361
14.1.3.3
PCI Express Recovery ...................................................................... 361
14.1.3.4
PCI Express Retrain ......................................................................... 361
14.1.4
Test/Support Major Buses........................................................................ 362
14.1.4.1
IICH XOR ....................................................................................... 362
14.1.4.2
SMB (IMCH) ................................................................................... 362
14.1.4.3
SMB (IICH) .................................................................................... 362
14.1.4.4
I2C ............................................................................................... 362
14.2 Exception Handling .......................................................................................... 362
14.2.1
FERR/NERR Global Register Scheme ......................................................... 362
14.2.1.1
FERR/NERR Unit Registers ................................................................ 363
14.2.1.2
Clearing FERR/NERR Registers .......................................................... 363
14.2.1.3
FERR/NERR Unit Specific .................................................................. 364
14.2.1.4
SERR/SMI/SCI Enabling Registers...................................................... 364
14.2.1.5
MCERR Enabling Registers ................................................................ 365
14.2.1.6
Error Escalation Register .................................................................. 365
14.2.1.7
Error Masking ................................................................................. 365
14.2.1.8
PCI Express Errors and Errors on Behalf of PCI Express ........................ 366
14.2.1.9
Configurable Error Containment at the Legacy Interface ....................... 367
14.3 Error Conditions Signaled.................................................................................. 368
15.0 Platform Management (IMCH) ............................................................................... 371
15.1 Integrated SMBus Interface............................................................................... 371
15.2 SMBus Target Architecture ................................................................................ 371
15.2.1
High Level Operation............................................................................... 371
15.2.1.1
SMBus Register Summary ................................................................ 371
15.2.1.2
Internal Register Access Mechanism .................................................. 373
15.2.1.3
SMBus Register Definitions ............................................................... 373
15.2.1.4
Unsupported Access Addresses ......................................................... 376
15.2.1.5
SMBus Transaction Pictograms ......................................................... 376
15.2.2
Suggested SMBus Usage Models ............................................................... 380
15.2.2.1
Remote Error Handling..................................................................... 380
15.2.2.2
Remote Platform Monitoring ............................................................. 380
15.3 Platform Power Management Support ................................................................. 380
Intel® EP80579 Integrated Processor Product Line Datasheet
10
August 2009
Order Number: 320066-003US
Contents
15.3.1
Supported System Power States .............................................................. 380
15.3.1.1
Supported CPU Power States ............................................................ 381
15.3.1.2
Supported Device Power States ........................................................ 381
15.3.1.3
Supported Bus Power States ............................................................ 381
15.3.2
DDR2 Interface Power Management.......................................................... 381
15.3.3
PCI Express Interface Power Management ................................................. 382
15.3.3.1
PCI Express Link Power State Definitions ........................................... 382
15.3.3.2
Software Controlled PCI Express Link States....................................... 382
15.3.3.3
Hardware Controlled PCI Express Link States...................................... 383
15.3.3.4
System Clocking Solution Dependencies............................................. 384
15.3.3.5
Device and Link PM Initialization ....................................................... 384
15.3.4
Device and Slot Power Limits ................................................................... 385
15.3.5
PME Support.......................................................................................... 385
15.3.5.1
PME Wake Signaling ........................................................................ 385
15.3.5.2
PME Messaging............................................................................... 386
15.3.6
BIOS Support for PCI Express PM Messaging.............................................. 386
15.3.6.1
PCI Express PME_TURN_OFF Semantic .............................................. 386
16.0 IMCH Registers...................................................................................................... 389
16.1 IMCH Registers: Bus 0, Device 0, Function 0 ...................................................... 389
16.1.1
Register Details ..................................................................................... 391
16.1.1.1
Offset 00h: VID – Vendor Identification Register ................................. 391
16.1.1.2
Offset 02h: DID – Device Identification Register ................................. 391
16.1.1.3
Offset 04h: PCICMD: PCI Command Register ...................................... 392
16.1.1.4
Offset 06h: PCISTS: PCI Status Register ............................................ 393
16.1.1.5
Offset 08h: RID - Revision Identification Register ................................ 394
16.1.1.6
Offset 0Ah: SUBC - Sub-Class Code Register ...................................... 394
16.1.1.7
Offset 0Bh: BCC – Base Class Code Register....................................... 394
16.1.1.8
Offset 0Eh: HDR - Header Type Register ............................................ 395
16.1.1.9
Offset 14h: SMRBASE - System Memory RCOMP Base
Address Register............................................................................. 395
16.1.1.10 Offset 2Ch: SVID - Subsystem Vendor Identification Register ............... 396
16.1.1.11 Offset 2Eh: SID - Subsystem Identification Register ............................ 397
16.1.1.12 Offset 4Ch: NSIBAR - Root Complex Block Address Register ................. 397
16.1.1.13 Offset 50h: CFG0 - IMCH Configuration 0 Register............................... 398
16.1.1.14 Offset 51h: IMCH_CFG1 – IMCH Configuration 1 Register ..................... 399
16.1.1.15 Offset 53h: CFGNS1 - Configuration 1 Register ................................... 399
16.1.1.16 Offset 58h: FDHC - Fixed DRAM Hole Control Register ......................... 400
16.1.1.17 Offset 59h: PAM0 - Programmable Attribute Map 0 Register ................. 401
16.1.1.18 Offset 5Ah: PAM1 - Programmable Attribute Map 1 Register ................. 402
16.1.1.19 Offset 5Bh: PAM2 - Programmable Attribute Map 2 Register ................. 403
16.1.1.20 Offset 5Ch: PAM3 - Programmable Attribute Map 3 Register ................. 404
16.1.1.21 Offset 5Dh: PAM4 - Programmable Attribute Map 4 Register ................. 405
16.1.1.22 Offset 5Eh: PAM5 - Programmable Attribute Map 5 Register ................. 406
16.1.1.23 Offset 5Fh: PAM6 - Programmable Attribute Map 6 Register.................. 407
16.1.1.24 Offset 9Ch: DEVPRES - Device Present Register .................................. 407
16.1.1.25 Offset 9Dh: EXSMRC - Extended System Management RAM Control Register.
409
16.1.1.26 Offset 9Eh: SMRAM - System Management RAM Control Register .......... 411
16.1.1.27 Offset 9Fh: EXSMRAMC - Expansion System Management RAM Control
Register ........................................................................................ 413
16.1.1.28 Offset B8h: IMCH_MENCBASE - IA/ASU Shared Non-Coherent (AIOC-Direct)
Memory Base Address Register ......................................................... 413
16.1.1.29 Offset BCh: IMCH_MENCLIMIT - IA/ASU Shared Non-Coherent (AIOC-Direct)
Memory Limit Address Register......................................................... 414
16.1.1.30 Offset C4h: TOLM - Top of Low Memory Register................................. 414
16.1.1.31 Offset C6h: REMAPBASE - Remap Base Address Register...................... 416
16.1.1.32 Offset C8h: REMAPLIMIT – Remap Limit Address Register .................... 416
16.1.1.33 Offset CAh: REMAPOFFSET - Remap Offset Register ............................ 417
August 2009
Order Number: 320066-003US
Intel® EP80579 Integrated Processor Product Line Datasheet
11
Contents
16.1.1.34
16.1.1.35
Offset CCh: TOM - Top Of Memory Register ........................................ 417
Offset CEh: HECBASE - PCI Express Port A (PEA) Enhanced Configuration
Base Address Register ..................................................................... 418
16.1.1.36 Offset D8h: CACHECTL0 - Write Cache Control 0 Register ..................... 418
16.1.1.37 Offset DEh: SKPD - Scratchpad Data Register ..................................... 419
16.1.1.38 Offset F6h: IMCH_TST2 - IMCH Test Byte 2 Register ............................ 419
16.1.1.39 Offset 60h: DRB[0-3] – DRAM Row [3:0] Boundary Register ................. 420
16.1.1.40 Offset 70h: DRA[0-1] – DRAM Row [0:1] Attribute Register .................. 421
16.1.1.41 Offset 78h: DRT0 - DRAM Timing Register 0 ....................................... 424
16.1.1.42 Offset 64h: DRT1 – DRAM Timing Register 1 ....................................... 431
16.1.1.43 Offset 7Ch: DRC – DRAM Controller Mode Register .............................. 435
16.1.1.44 Offset 84h: ECCDIAG – ECC Detection/Correction
Diagnostic Register.......................................................................... 437
16.1.1.45 Offset 88h: SDRC – DDR SDRAM Secondary Control Register ................ 439
16.1.1.46 Offset 8Ch: CKDIS – CK/CK# Clock Disable Register ............................ 441
16.1.1.47 Offset 8Dh: CKEDIS - CKE Clock Disable Register ................................ 442
16.1.1.48 Offset 90h: SPARECTL - SPARE Control Register .................................. 443
16.1.1.49 Offset B0h: DDR2ODTC - DDR2 ODT Control Register .......................... 443
16.2 DRAM Controller Error Reporting Registers: Bus 0, Device 0, Function 1 ................. 445
16.2.1
Register Details ...................................................................................... 447
16.2.1.1
Offset 00h: VID - Vendor Identification Register .................................. 447
16.2.1.2
Offset 02h: DID - Device Identification Register .................................. 447
16.2.1.3
Offset 04h: PCICMD - PCI Command Register ..................................... 448
16.2.1.4
Offset 06h: PCISTS - PCI Status Register ........................................... 448
16.2.1.5
Offset 08h: RID - Revision Identification Register ................................ 449
16.2.1.6
Offset 0Ah: SUBC - Sub-Class Code Register....................................... 449
16.2.1.7
Offset 0Bh: BCC - Base Class Code Register........................................ 449
16.2.1.8
Offset 0Dh: MLT - Master Latency Timer Register ................................ 450
16.2.1.9
Offset 0Eh: HDR - Header Type Register............................................. 450
16.2.1.10 Offset 2Ch: SVID - Subsystem Vendor Identification Register ................ 450
16.2.1.11 Offset 2Eh: SID - Subsystem Identification Register............................. 451
16.2.1.12 Offset 40h: GLOBAL_FERR - Global First Error Register......................... 451
16.2.1.13 Offset 44h: GLOBAL_NERR - Global Next Error Register........................ 453
16.2.1.14 Offset 48h: NSI_FERR - NSI First Error Register .................................. 454
16.2.1.15 Offset 4Ch: NSI_NERR - NSI Next Error Register ................................. 457
16.2.1.16 Offset 50h: NSI_SCICMD - NSI SCI Command Register ........................ 459
16.2.1.17 Offset 54h: NSI_SMICMD - NSI SMI Command Register ....................... 461
16.2.1.18 Offset 58h: NSI_SERRCMD - NSI SERR Command Register ................... 464
16.2.1.19 Offset 5Ch: NSI_MCERRCMD - NSI MCERR Command Register .............. 466
16.2.1.20 Offset 60h: FSB_FERR - FSB First Error Register.................................. 468
16.2.1.21 Offset 62h: FSB_NERR - FSB Next Error Register ................................. 469
16.2.1.22 Offset 64h: FSB_EMASK - FSB Error Mask Register .............................. 470
16.2.1.23 Offset 68h: FSB_SCICMD - FSB SCI Command Register ....................... 471
16.2.1.24 Offset 6Ah: FSB_SMICMD - FSB SMI Command Register....................... 472
16.2.1.25 Offset 6Ch: FSB_SERRCMD - FSB SERR Command Register .................. 473
16.2.1.26 Offset 6Eh: FSB_MCERRCMD - FSB MCERR Command Register .............. 474
16.2.1.27 Offset 70h: BUF_FERR - Memory Buffer First Error Register .................. 475
16.2.1.28 Offset 72h: BUF_NERR - Memory Buffer Next Error Register.................. 475
16.2.1.29 Offset 74h: BUF_EMASK - Memory Buffer Error Mask Register ............... 476
16.2.1.30 Offset 78h: BUF_SCICMD - Memory Buffer SCI Command Register ........ 477
16.2.1.31 Offset 7Ah: BUF_SMICMD - Memory Buffer SMI Command Register ....... 478
16.2.1.32 Offset 7Ch: BUF_SERRCMD - Memory Buffer SERR
Command Register .......................................................................... 479
16.2.1.33 Offset 7Eh: BUF_MCERRCMD - Memory Buffer MCERR
Command Register .......................................................................... 480
16.2.1.34 Offset E4h: NSIERRINJCTL - NSI Error Injection Control Register ........... 481
16.2.1.35 Offset E8h: BERRINJCTL - Buffer Error Injection Control Register........... 481
16.2.1.36 Offset 80h: DRAM_FERR - DRAM First Error Register ............................ 482
16.2.1.37 Offset 82h: DRAM_NERR - DRAM Next Error Register ........................... 484
16.2.1.38 Offset 84h: DRAM_EMASK - DRAM Error Mask Register ........................ 485
Intel® EP80579 Integrated Processor Product Line Datasheet
12
August 2009
Order Number: 320066-003US
Contents
16.2.1.39
16.2.1.40
16.2.1.41
16.2.1.42
16.2.1.43
Offset 88h: DRAM_SCICMD - DRAM SCI Command Register ................. 486
Offset 8Ah: DRAM_SMICMD - DRAM SMI Command Register ................ 487
Offset 8Ch: DRAM_SERRCMD - DRAM SERR Command Register ............ 488
Offset 8Eh: DRAM_MCERRCMD - DRAM MCERR Command Register........ 490
Offset 98h: THRESH_SEC0 - Rank 0 SEC Error
Threshold Register .......................................................................... 491
16.2.1.44 Offset 9Ah: THRESH_SEC1 - Rank 1 SEC Error
Threshold Register .......................................................................... 491
16.2.1.45 Offset A0h: DRAM_SECF_ADD - DRAM First Single Bit Error Correct Address
Register ........................................................................................ 492
16.2.1.46 Offset A4h: DRAM_DED_ADD - DRAM Double Bit Error
Address Register............................................................................. 492
16.2.1.47 Offset A8h: DRAM_SCRB_ADD - DRAM Scrub Error
Address Register............................................................................. 493
16.2.1.48 Offset B0h: DRAM_SEC_R0 - DRAM Rank 0 SEC Error
Counter Register............................................................................. 493
16.2.1.49 Offset B2h: DRAM_DED_R0 - DRAM Rank 0 DED Error
Counter Register............................................................................. 494
16.2.1.50 Offset B4h: DRAM_SEC_R1 - DRAM Rank 1 SEC Error
Counter Register............................................................................. 494
16.2.1.51 Offset B6h: DRAM_DED_R1 - DRAM Rank 1 DED Error
Counter Register............................................................................. 495
16.2.1.52 Offset C2h: THRESH_DED - DED Error Threshold Register .................... 495
16.2.1.53 Offset C4h: DRAM_SECF_SYNDROME - DRAM First Single Error Correct
Syndrome Register ......................................................................... 496
16.2.1.54 Offset C6h: DRAM_SECN_SYNDROME - DRAM Next Single Error Correct
Syndrome Register ......................................................................... 496
16.2.1.55 Offset C8h: DRAM_SECN_ADD - DRAM Next Single Bit Error Correct Address
Register ........................................................................................ 497
16.2.1.56 Offset DCh: RANKTHREX - Rank Error Threshold Exceeded Register....... 497
16.2.1.57 Offset ECh: DERRINJCTL - DRAM Error Injection Control Register .......... 499
16.3 EDMA Registers: Bus 0, Device 1, Function 0 ..................................................... 501
16.3.1
Register Details ..................................................................................... 502
16.3.1.1
Offset 00h: VID - Vendor Identification Register.................................. 502
16.3.1.2
Offset 02h: DID - Device Identification Register .................................. 502
16.3.1.3
Offset 04h: PCICMD - PCI Command Register ..................................... 503
16.3.1.4
Offset 06h: PCISTS - PCI Status Register ........................................... 504
16.3.1.5
Offset 08h: RID - Revision Identification Register ................................ 504
16.3.1.6
Offset 0Ah: SUBC - Sub-Class Code Register ...................................... 505
16.3.1.7
Offset 0Bh: BCC - Base Class Code Register ....................................... 505
16.3.1.8
Offset 0Eh: HDR - Header Type Register ............................................ 505
16.3.1.9
Offset 10h: EDMALBAR - EDMA Low Base Address Register .................. 506
16.3.1.10 Offset 2Ch: SVID - Subsystem Vendor Identification Register ............... 506
16.3.1.11 Offset 2Eh: SID - Subsystem Identification Register ............................ 506
16.3.1.12 Offset 34h: CAPPTR - Capabilities Pointer Register .............................. 507
16.3.1.13 Offset 3Ch: INTRLINE - Interrupt Line Register ................................... 507
16.3.1.14 Offset 3Dh: INTRPIN - Interrupt Pin Register ...................................... 508
16.3.1.15 Offset 40h: EDMACTL - EDMA Control Register ................................... 508
16.3.1.16 Offset 80h: EDMA_FERR - EDMA First Error Register ............................ 508
16.3.1.17 Offset 84h: EDMA_NERR - EDMA Next Error Register ........................... 510
16.3.1.18 Offset 88h: EDMA_EMASK - EDMA Error Mask Register ........................ 512
16.3.1.19 Offset A0h: EDMA_SCICMD - EDMA SCI Command Register ................. 514
16.3.1.20 Offset A4h: EDMA_SMICMD - EDMA SMI Command Register................. 515
16.3.1.21 Offset A8h: EDMA_SERRCMD - EDMA SERR Command Register ............ 516
16.3.1.22 Offset ACh: EDMA_MCERRCMD - EDMA MCERR Command Register........ 517
16.3.1.23 Offset B0h: MSICR - MSI Control Register .......................................... 518
16.3.1.24 Offset B4h: MSIAR - MSI Address Register ......................................... 519
16.3.1.25 Offset B8h: MSIDR - MSI Data Register ............................................. 520
16.4 PCI Express* Port A Standard and Enhanced Registers: Bus 0,
Devices 2 and 3, Function 0 ............................................................................. 521
August 2009
Order Number: 320066-003US
Intel® EP80579 Integrated Processor Product Line Datasheet
13
Contents
16.4.1
Register Details ...................................................................................... 527
16.4.1.1
Offset 00h: VID - Vendor Identification Register .................................. 527
16.4.1.2
Offset 02h: DID - Device Identification Register .................................. 527
16.4.1.3
Offset 02h: DID - Device Identification Register .................................. 528
16.4.1.4
Offset 04h: PCICMD - PCI Command Register ..................................... 528
16.4.1.5
Offset 06h: PCISTS - PCI Status Register ........................................... 530
16.4.1.6
Offset 08h: RID - Revision Identification Register ................................ 531
16.4.1.7
Offset 0Ah: SUBC - Sub-Class Code Register....................................... 532
16.4.1.8
Offset 0Bh: BCC - Base Class Code Register........................................ 532
16.4.1.9
Offset 0Ch: CLS - Cache Line Size Register ......................................... 533
16.4.1.10 Offset 0Eh: HDR - Header Type Register............................................. 533
16.4.1.11 Offset 18h: PBUSN - Primary Bus Number Register .............................. 534
16.4.1.12 Offset 19h: SBUSN - Secondary Bus Number Register .......................... 534
16.4.1.13 Offset 1Ah: SUBUSN - Subordinate Bus Number Register...................... 535
16.4.1.14 Offset 1Ch: IOBASE - I/O Base Address Register ................................. 535
16.4.1.15 Offset 1Dh: IOLIMIT - I/O Limit Address Register ................................ 536
16.4.1.16 Offset 1Eh: SECSTS - Secondary Status Register ................................. 536
16.4.1.17 Offset 20h: MBASE - Memory Base Address Register ............................ 538
16.4.1.18 Offset 22h: MLIMIT - Memory Limit Address Register ........................... 538
16.4.1.19 Offset 24h: PMBASE - Prefetchable Memory Base Address Register ........ 539
16.4.1.20 Offset 26h: PMLIMIT - Prefetchable Memory Limit Address Register ....... 540
16.4.1.21 Offset 28h: PMBASU - Prefetchable Memory Base
Upper Address Register.................................................................... 541
16.4.1.22 Offset 2Ch: PMLMTU - Prefetchable Memory Limit Upper
Address Register ............................................................................. 541
16.4.1.23 Offset 34h: CAPPTR - Capabilities Pointer Register ............................... 542
16.4.1.24 Offset 3Ch: INTRLINE - Interrupt Line Register.................................... 542
16.4.1.25 Offset 3Dh: INTRPIN - Interrupt Pin Register ...................................... 543
16.4.1.26 Offset 3Eh: BCTRL - Bridge Control Register ....................................... 543
16.4.1.27 Offset 44h: VSCMD0 - Vendor Specific Command Byte 0 Register .......... 544
16.4.1.28 Offset 45h: VSCMD1 - Vendor Specific Command Byte 1 Register .......... 546
16.4.1.29 Offset 46h: VSSTS0 - Vendor Specific Status Byte 0 Register ................ 547
16.4.1.30 Offset 47h: VSSTS1 - Vendor Specific Status Byte 1 Register ................ 547
16.4.1.31 Offset 48h: VSCMD2 - Vendor Specific Command Byte 2 Register .......... 548
16.4.1.32 Offset 50h: PMCAPID - Power Management Capabilities
Structure Register ........................................................................... 548
16.4.1.33 Offset 51h: PMNPTR - Power Management Next Capabilities Pointer Register
549
16.4.1.34 Offset 52h: PMCAPA - Power Management Capabilities
Register ......................................................................................... 549
16.4.1.35 Offset 54h: PMCSR - Power Management Status and Control
Register ......................................................................................... 550
16.4.1.36 Offset 56h: PMCSRBSE - Power Management Status and Control Bridge
Extensions Register ......................................................................... 551
16.4.1.37 Offset 58h: MSICAPID - MSI Capabilities Structure Register .................. 551
16.4.1.38 Offset 59h: MSINPTR - MSI Next Capabilities Pointer Register ............... 552
16.4.1.39 Offset 5Ah: MSICAPA - MSI Capabilities Register ................................. 552
16.4.1.40 Offset 5Ch: MSIAR - MSI Address for PCI Express* Register.................. 553
16.4.1.41 Offset 60h: MSIDR - MSI Data Register .............................................. 554
16.4.1.42 Offset 64h: PEACAPID - PCI Express* Features Capabilities ID
Register ......................................................................................... 555
16.4.1.43 Offset 65h: PEANPTR - PCI Express* Next Capabilities Pointer
Register ......................................................................................... 556
16.4.1.44 Offset 66h: PEACAPA - PCI Express* Features Capabilities Register........ 556
16.4.1.45 Offset 68h: PEADEVCAP - PCI Express* Device Capabilities
Register ......................................................................................... 557
16.4.1.46 Offset 6Ch: PEADEVCTL - PCI Express* Device Control Register ............ 558
16.4.1.47 Offset 6Eh: PEADEVSTS - PCI Express* Device Status Register ............. 560
16.4.1.48 Offset 70h: PEALNKCAP - PCI Express* Link Capabilities Register .......... 561
16.4.1.49 Offset 70h: PEA1LNKCAP - PCI Express* Link Capabilities Register......... 561
Intel® EP80579 Integrated Processor Product Line Datasheet
14
August 2009
Order Number: 320066-003US
Contents
16.4.1.50
16.4.1.51
16.4.1.52
16.4.1.53
16.4.1.54
16.4.1.55
16.4.1.56
16.4.1.57
16.4.1.58
16.4.1.59
16.4.1.60
16.4.1.61
16.4.1.62
16.4.1.63
16.4.1.64
Offset 74h: PEALNKCTL - PCI Express* Link Control Register ................ 562
Offset 76h: PEALNKSTS - PCI Express* Link Status Register ................. 564
Offset 78h: PEASLTCAP - PCI Express* Slot Capabilities Register........... 565
Offset 78h: PEA1SLTCAP - PCI Express* Slot Capabilities Register......... 566
Offset 7Ch: PEASLTCTL - PCI Express* Slot Control Register ................ 568
Offset 7Eh: PEASLTSTS - PCI Express* Slot Status Register ................. 569
Offset 80h: PEARPCTL - PCI Express* Root Port Control Register........... 570
Offset 84h: PEARPSTS - PCI Express* Root Port Status Register............ 571
Offset 100h: ENHCAPST - Enhanced Capability Structure Register ......... 571
Offset 104h: UNCERRSTS - Uncorrectable Error Status Register ............ 572
Offset 108h: UNCERRMSK - Uncorrectable Error Mask Register ............. 574
Offset 10Ch: UNCERRSEV - Uncorrectable Error Severity Register ......... 575
Offset 110h: CORERRSTS - Correctable Error Status Register ............... 576
Offset 114h: CORERRMSK - Correctable Error Mask Register................. 578
Offset 118h: AERCACR - Advanced Error Capabilities and
Control Register.............................................................................. 579
16.4.1.65 Offset 11Ch: HDRLOG0 - Header Log DW 0 (1st 32 bits) Register.......... 580
16.4.1.66 Offset 120h: HDRLOG1 - Header Log DW 1 (2nd 32 bits) Register ......... 580
16.4.1.67 Offset 124h: HDRLOG2 - Header Log DW 2 (3rd 32 bits) Register ......... 581
16.4.1.68 Offset 128h: HDRLOG3 - Header Log DW 3 (4th 32 bits) Register.......... 581
16.4.1.69 Offset 12Ch: RPERRCMD - Root (Port) Error Command Register ............ 582
16.4.1.70 Offset 130h: RPERRMSTS - Root (Port) Error Message Status
Register ........................................................................................ 583
16.4.1.71 Offset 134h: ERRSID - Error Source ID Register.................................. 585
16.4.1.72 Offset 140h: PEAUNITERR - PCI Express* Unit Error Register................ 585
16.4.1.73 Offset 144h: PEAMASKERR - PCI Express* Unit Mask Error
Register ........................................................................................ 588
16.4.1.74 Offset 148h: PEAERRDOCMD - PCI Express* Error Do
Command Register ......................................................................... 589
16.4.1.75 Offset 14Ch: UNCEDMASK - Uncorrectable Error Detect Mask
Register ........................................................................................ 591
16.4.1.76 Offset 150h: COREDMASK - Correctable Error Detect Mask
Register ........................................................................................ 592
16.4.1.77 Offset 158h: PEAUNITEDMASK - PCI Express* Unit Error Detect Mask Register
594
16.4.1.78 Offset 160h: PEAFERR - PCI Express* First Error Register .................... 595
16.4.1.79 Offset 164h: PEANERR - PCI Express* Next Error Register.................... 597
16.4.1.80 Offset 168h: PEAERRINJCTL - Error Injection Control Register .............. 597
16.5 Memory Mapped I/O Registers for DRAM Controller.............................................. 599
16.5.1
Detailed Register Description ................................................................... 601
16.5.1.1
Offset 00h: NOTESPAD - Note (Sticky) Pad for BIOS Support
Register ........................................................................................ 601
16.5.1.2
Offset 02h: NOTEPAD - Note Pad for BIOS Support Register ................. 601
16.5.1.3
Offset 40h: DCALCSR – DDR Calibration Control and Status
Register ........................................................................................ 602
16.5.1.4
Offset 44h: DCALADDR - DDR Calibration Address Register .................. 606
16.5.1.5
Offset 48h: DCALDATA[0-71] - DRAM Calibration Data Registers........... 607
16.5.1.6
Offset 94h: RCVENAC - Receiver Enable Algorithm Control
Register ........................................................................................ 611
16.5.1.7
Offset 98h: DSRETC - DRAM Self-Refresh (SR) Extended Timing and Control
611
16.5.1.8
Offset 9Ch: DQSFAIL1 - DQSFAIL1 Configuration Register .................... 612
16.5.1.9
Offset A0h: DQSFAIL0 - DQSFAIL0 Configuration Register .................... 613
16.5.1.10 DRRTC: Receive Enable Reference Output Timing Control Registers ....... 614
16.5.1.11 Offset A4h: DRRTC00 - Receive Enable Reference Output Timing Control
Register ........................................................................................ 615
16.5.1.12 Offset A8h: DRRTC01 - Receive Enable Reference Output Timing Control
Register ........................................................................................ 616
16.5.1.13 Offset C4h: DRRTC02 - Receive Enable Reference Output Timing Control
Register ........................................................................................ 616
August 2009
Order Number: 320066-003US
Intel® EP80579 Integrated Processor Product Line Datasheet
15
Contents
16.5.1.14
16.5.1.15
16.5.1.16
16.5.1.17
16.5.1.18
16.5.1.19
16.5.1.20
16.5.1.21
16.5.1.22
16.5.1.23
16.5.1.24
16.5.1.25
16.5.1.26
16.5.1.27
16.5.1.28
16.5.1.29
16.5.1.30
16.5.1.31
16.5.1.32
16.5.1.33
16.5.1.34
16.5.1.35
16.5.1.36
16.5.1.37
16.5.1.38
16.5.1.39
16.5.1.40
16.5.1.41
16.5.1.42
16.5.1.43
16.5.1.44
16.5.1.45
16.5.1.46
16.5.1.47
16.5.1.48
16.5.1.49
16.5.1.50
16.5.1.51
16.5.1.52
16.5.1.53
16.5.1.54
16.5.1.55
16.5.1.56
16.5.1.57
16.5.1.58
16.5.1.59
16.5.1.60
16.5.1.61
16.5.1.62
16.5.1.63
16.5.1.64
16.5.1.65
DQS Calibration Registers................................................................. 616
Offset B4h: DQSOFCS00 - DQS Calibration Register ............................. 617
Offset B8h: DQSOFCS01 - DQS Calibration Register ............................. 617
Offset C6h: DQSOFCS02 - DQS Calibration Register ............................. 618
Offset BCh: DQSOFCS10 - DQS Calibration Register............................. 618
Offset C0h: DQSOFCS11 - DQS Calibration Register ............................. 619
Offset C7h: DQSOFCS12 - DQS Calibration Register ............................. 619
WPTRTC DDR I/O Write Pointer Timing............................................... 620
Offset CCh: WPTRTC0 - Write Pointer Timing Control 0 Register ........... 620
Offset D0h: WPTRTC1 - Write Pointer Timing Control 1 Register ............ 621
DDQSCVDP and DDQSCADP.............................................................. 621
Offset D4h: DDQSCVDP0 - DQS DELAY CALIBRATION VICTIM PATTERN 0
Register ......................................................................................... 621
Offset D8h: DDQSCVDP1 - DQS DELAY CALIBRATION VICTIM PATTERN 1
Register ......................................................................................... 622
Offset DCh: DDQSCADP0 - DQS DELAY CALIBRATION AGGRESSOR PATTERN
0 Register ...................................................................................... 622
Offset E0h: DDQSCADP1 - DQS DELAY CALIBRATION AGGRESSOR PATTERN
1 Register ...................................................................................... 622
Offset F0h: DIOMON - DDR I/O Monitor Register ................................. 623
Offset F8h: DRAMISCTL - Miscellaneous DRAM DDR Cluster Control Register
624
Offset C8h: DRAMDLLC - DDR I/O DLL Control Register ........................ 625
Offset E8h: FIVESREG - Fixed 5s Pattern Register................................ 625
Offset ECh: AAAAREG - Fixed As Pattern Register ............................... 626
Memory BIST Registers .................................................................... 626
Offset 140h: MBCSR - MemBIST Control Register ............................... 626
Offset 144h: MBADDR - Memory Test Address Register ........................ 629
Offset 148h: MBDATA[0:9] - Memory Test Data Register ...................... 629
Offset 19Ch: MB_START_ADDR - Memory Test Start Address
Register ......................................................................................... 631
Offset 1A0h: MB_END_ADDR - Memory Test End Address Register......... 632
Offset 1A4h: MBLFSRSED - Memory Test Circular Shift and LFSR Seed
Register ......................................................................................... 633
Offset 1A8h: MBFADDRPTR - Memory Test Failure Address Pointer Register .
633
Offset 1B0h: MB_ERR_DATA00 - Memory Test Error Data 0 ................. 634
Offset 1B4h: MB_ERR_DATA01 - Memory Test Error Data 0 ................. 634
Offset 1B8h: MB_ERR_DATA02 - Memory Test Error Data 0 ................. 634
Offset 1BCh: MB_ERR_DATA03 - Memory Test Error Data 0 ................. 635
Offset 1C0h: MB_ERR_DATA04 - Memory Test Error Data 0 ................. 635
Offset 1C4h: MB_ERR_DATA10 - Memory Test Error Data 1 ................. 635
Offset 1C8h: MB_ERR_DATA11 - Memory Test Error Data 1 ................. 636
Offset 1CCh: MB_ERR_DATA12 - Memory Test Error Data 1 ................. 636
Offset 1D0h: MB_ERR_DATA13 - Memory Test Error Data 1 ................. 636
Offset 1D4h: MB_ERR_DATA14 - Memory Test Error Data 1 ................. 637
Offset 1D8h: MB_ERR_DATA20 - Memory Test Error Data 2 ................. 637
Offset 1DCh: MB_ERR_DATA21 - Memory Test Error Data 2 ................. 637
Offset 1E0h: MB_ERR_DATA22 - Memory Test Error Data 2 ................. 638
Offset 1E4h: MB_ERR_DATA23 - Memory Test Error Data 2 ................. 638
Offset 1E8h: MB_ERR_DATA24 - Memory Test Error Data 2 ................. 638
Offset 1ECh: MB_ERR_DATA30 - Memory Test Error Data 3 ................. 639
Offset 1F0h: MB_ERR_DATA31 - Memory Test Error Data 3 .................. 639
Offset 1F4h: MB_ERR_DATA32 - Memory Test Error Data 3 .................. 639
Offset 1F8h: MB_ERR_DATA33 - Memory Test Error Data 3 .................. 640
Offset 1FCh: MB_ERR_DATA34 - Memory Test Error Data 3 ................. 640
Offset 260h: DDRIOMC0 - DDR IO Mode Control Register 0................... 640
Offset 264h: DDRIOMC1 - DDR IO Mode Control Register 1................... 641
Offset 268h: DDRIOMC2 - DDR IO Mode Control Register 2................... 644
Offset 284h: WL_CNTL[4:0] - Write Levelization[4:0] Control
Intel® EP80579 Integrated Processor Product Line Datasheet
16
August 2009
Order Number: 320066-003US
Contents
Register ........................................................................................ 646
16.5.1.66 Offset 298h: WDLL_MISC - DLL Miscellaneous Control ......................... 648
16.6 Memory Mapped I/O for EDMA Registers ............................................................ 651
16.6.1
Register Details ..................................................................................... 653
16.6.1.1
Offset 00h: CCR0 - Channel 0 Channel Control Register ...................... 653
16.6.1.2
Offset 04h: CSR0 - Channel 0 Channel Status Register ....................... 656
16.6.1.3
Offset 08h: CDAR0 - Channel 0 Current Descriptor Address
Register ........................................................................................ 657
16.6.1.4
Offset 0Ch: CDUAR0 - Channel 0 Current Descriptor Upper Address Register
658
16.6.1.5
Offset 10h: SAR0 - Channel 0 Source Address Register ....................... 658
16.6.1.6
Offset 14h: SUAR0 - Channel 0 Source Upper Address Register............. 659
16.6.1.7
Offset 18h: DAR0 - Channel 0 Destination Address Register.................. 659
16.6.1.8
Offset 1Ch: DUAR0 - Channel 0 Destination Upper Address
Register ........................................................................................ 660
16.6.1.9
Offset 20h: NDAR0 - Channel 0 Next Descriptor Address Register ......... 661
16.6.1.10 Offset 24h: NDUAR0 - Channel 0 Next Descriptor Upper
Address Register ............................................................................ 661
16.6.1.11 Offset 28h: TCR0 - Channel 0 Transfer Count Register ......................... 662
16.6.1.12 Offset 2Ch: DCR0 - Channel 0 Descriptor Control Register .................... 663
16.6.1.13 Offset 40h: CCR1 - Channel 1 Channel Control Register ....................... 665
16.6.1.14 Offset 44h: CSR1 - Channel 1 Channel Status Register ........................ 665
16.6.1.15 Offset 48h: CDAR1 - Channel 1 Current Descriptor Address
Register ........................................................................................ 665
16.6.1.16 Offset 4Ch: CDUAR1 - Channel 1 Current Descriptor Upper Address Register
666
16.6.1.17 Offset 50h: SAR1 - Channel 1 Source Address Register ....................... 666
16.6.1.18 Offset 54h: SUAR1 - Channel 1 Source Upper Address Register............. 666
16.6.1.19 Offset 58h: DAR1 - Channel 1 Destination Address Register.................. 667
16.6.1.20 Offset 5Ch: DUAR1 - Channel 1 Destination Upper Address
Register ........................................................................................ 667
16.6.1.21 Offset 60h: NDAR1 - Channel 1 Next Descriptor Address Register.......... 667
16.6.1.22 Offset 64h: NDUAR1 - Channel 1 Next Descriptor Upper
Address Register............................................................................. 668
16.6.1.23 Offset 68h: TCR1 - Channel 1 Transfer Count Register ......................... 668
16.6.1.24 Offset 6Ch: DCR1 - Channel 1 Descriptor Control Register ................... 668
16.6.1.25 Offset 80h: CCR2 - Channel 2 Channel Control Register ....................... 669
16.6.1.26 Offset 84h: CSR2 - Channel 2 Channel Status Register ........................ 669
16.6.1.27 Offset 88h: CDAR2 - Channel 2 Current Descriptor Address
Register ........................................................................................ 669
16.6.1.28 Offset 8Ch: CDUAR2 - Channel 2 Current Descriptor Upper Address Register
670
16.6.1.29 Offset 90h: SAR2 - Channel 2 Source Address Register ....................... 670
16.6.1.30 Offset 94h: SUAR2 - Channel 2 Source Upper Address Register............. 670
16.6.1.31 Offset 98h: DAR2 - Channel 2 Destination Address Register.................. 671
16.6.1.32 Offset 9Ch: DUAR2 - Channel 2 Destination Upper Address
Register ........................................................................................ 671
16.6.1.33 Offset A0h: NDAR2 - Channel 2 Next Descriptor Address Register ......... 671
16.6.1.34 Offset A4h: NDUAR2 - Channel 2 Next Descriptor Upper
Address Register ............................................................................ 672
16.6.1.35 Offset A8h: TCR2 - Channel 2 Transfer Count Register ......................... 672
16.6.1.36 Offset ACh: DCR2 - Channel 2 Descriptor Control Register.................... 672
16.6.1.37 Offset C0h: CCR3 - Channel 3 Channel Control Register ...................... 673
16.6.1.38 Offset C4h: CSR3 - Channel 3 Channel Status Register ........................ 673
16.6.1.39 Offset C8h: CDAR3 - Channel 3 Current Descriptor Address
Register ........................................................................................ 673
16.6.1.40 Offset CCh: CDUAR3 - Channel 3 Current Descriptor Upper Address Register
674
16.6.1.41 Offset D0h: SAR3 - Channel 3 Source Address Register........................ 674
16.6.1.42 Offset D4h: SUAR3 - Channel 3 Source Upper Address Register ............ 674
August 2009
Order Number: 320066-003US
Intel® EP80579 Integrated Processor Product Line Datasheet
17
Contents
16.6.1.43
16.6.1.44
Offset D8h: DAR3 - Channel 3 Destination Address Register.................. 675
Offset DCh: DUAR3 - Channel 3 Destination Upper Address
Register ......................................................................................... 675
16.6.1.45 Offset E0h: NDAR3 - Channel 3 Next Descriptor Address Register .......... 675
16.6.1.46 Offset E4h: NDUAR3 - Channel 3 Next Descriptor Upper
Address Register ............................................................................. 676
16.6.1.47 Offset E8h: TCR3 - Channel 3 Transfer Count Register ......................... 676
16.6.1.48 Offset ECh: DCR3 - Channel 3 Descriptor Control Register .................... 677
16.6.1.49 Offset 100h: DCGC - EDMA Controller Global Command ....................... 677
16.6.1.50 Offset 104h: DCGS - EDMA Controller Global Status............................. 678
16.7 Memory Mapped I/O for NSI Registers ................................................................ 679
16.7.1
Register Details ...................................................................................... 680
16.7.1.1
Offset 00h: NSIVCECH - NSI Virtual Channel Enhanced Capability Header
Register ......................................................................................... 680
16.7.1.2
Offset 04h: NSIPVCCAP1 - NSI Port VC Capability Register 1................. 680
16.7.1.3
Offset 08h: NSIPVCCAP2 - Port VC Capability Register 2....................... 681
16.7.1.4
Offset 0Ch: NSIPVCCTL - NSI Port VC Control Register ......................... 682
16.7.1.5
Offset 10h: NSIVC0RCAP - NSI VC0 Resource Capability Register .......... 682
16.7.1.6
Offset 14h: NSIVC0RCTL - NSI VC0 Resource Control Register .............. 683
16.7.1.7
Offset 1Ah: NSIVC0RSTS - NSI VC0 Resource Status Register ............... 684
16.7.1.8
Offset 80h: NSIRCILCECH - NSI Root Complex Internal Link Control Enhanced
Capability Header Register................................................................ 684
16.7.1.9
Offset 84h: NSILCAP - NSI Link Capabilities Register............................ 685
Integrated I/O Controller Hub, Volume 3 of 6 ............................. 687
17.0 Bridging and Configuration .................................................................................... 689
17.1 Root Complex Memory-Mapped Configuration Register Details ............................... 689
17.1.1
VC Configuration Registers....................................................................... 691
17.1.1.1
Offset 0000h: VCH - Virtual Channel Capability Header Register ............ 691
17.1.1.2
Offset 0004h: VCAP1 - Virtual Channel Capability 1 Register ................. 691
17.1.1.3
Offset 0008h: VCAP2 - Virtual Channel Capability 2 Register ................. 692
17.1.1.4
Offset 000Ch: PVC - Port Virtual Channel Control Register .................... 692
17.1.1.5
Offset 000Eh: PVS - Port Virtual Channel Status Register...................... 693
17.1.1.6
Offset 0010h: V0CAP - Virtual Channel 0 Resource Capability
Register ......................................................................................... 693
17.1.1.7
Offset 0014h: V0CTL - Virtual Channel 0 Resource Control Register ....... 694
17.1.1.8
Offset 001Ah: V0STS - Virtual Channel 0 Resource Status Register ........ 695
17.1.2
Root Complex Topology Capability Structure Registers................................. 696
17.1.2.1
Offset 0100h: RCTCL- - Root Complex Topology Capabilities List Register ....
696
17.1.2.2
Offset 0104h: ES - Element Self Description Register ........................... 696
17.1.2.3
Offset 0110h: ULD - Upstream Link Description Register....................... 697
17.1.2.4
Offset 0118h: ULBA - Upstream Link Base Address Register .................. 697
17.1.3
Internal Link Configuration Registers ......................................................... 698
17.1.3.1
Offset 01A0h: ILCL - Internal Link Capabilities List Register .................. 698
17.1.3.2
Offset 01A4h: LCAP - Link Capabilities Register ................................... 698
17.1.3.3
Offset 01A8h: LCTL - Link Control Register ......................................... 699
17.1.3.4
Offset 01AAh: LSTS - Link Status Register .......................................... 700
17.1.4
TCO Configuration .................................................................................. 700
17.1.4.1
Offset 3000h: TCTL - TCO Control Register ......................................... 700
17.1.5
Interrupt Configuration Registers .............................................................. 701
17.1.5.1
Offset 3100h: D31IP - Device 31 Interrupt Pin Register ........................ 701
17.1.5.2
Offset 3108h: D29IP - Device 29 Interrupt Pin Register ........................ 702
17.1.5.3
Offset 3140h: D31IR - Device 31 Interrupt Route Register .................... 702
17.1.5.4
Offset 3144h: D29IR - Device 29 Interrupt Route Register .................... 703
17.1.5.5
Offset 31FFh: OIC - Other Interrupt Control Register ........................... 704
17.1.6
General Configuration Registers................................................................ 704
Intel® EP80579 Integrated Processor Product Line Datasheet
18
August 2009
Order Number: 320066-003US
Contents
17.1.6.1
17.1.6.2
17.1.6.3
17.1.6.4
17.1.6.5
17.1.6.6
Offset 3400h: RC - RTC Configuration Register ................................... 704
Offset 3404h: HPTC - High Performance Precision Timer Configuration
Register ........................................................................................ 705
Offset 3410h: GCS: General Control and Status Register...................... 706
Offset 3414h: BUC - Backed Up Control Register................................. 708
Offset 3418h: FD - Function Disable Register...................................... 709
Offset 341Ch: PRC - Power Reduction Control Register Clock
Gating........................................................................................... 711
18.0 System Management ............................................................................................. 713
18.1 Overview ....................................................................................................... 713
18.2 TCO I/O-Mapped Configuration Register Details ................................................... 714
18.2.1
TCO PCI Configuration Registers .............................................................. 715
18.2.2
Bus 0, Device 31, Function 0: TCO Configuration Register (I/O-Mapped via ABASE
BAR) Summary Table ............................................................................. 715
18.2.2.1
Offset 00h: TRLD - TCO Timer Reload and Current Value Register ......... 715
18.2.2.2
Offset 02h: TDI - TCO Data In Register.............................................. 715
18.2.2.3
Offset 03h: TDO - TCO Data Out Register .......................................... 716
18.2.2.4
Offset 04h: TSTS1 - TCO 1 Status Register ........................................ 716
18.2.2.5
Offset 06h: TSTS2 - TCO 2 STS Register ............................................ 718
18.2.2.6
Offset 08h: TCTL1 - TCO 1 Control Register........................................ 720
18.2.2.7
Offset 0Ah: TCTL2 - TCO 2 Control Register ....................................... 721
18.2.2.8
Offset 0Ch: TMSG[1-2] - TCO MESSAGE Register ................................ 721
18.2.2.9
Offset 0Eh: TWDS - TCO Watchdog Status Register ............................. 722
18.2.2.10 Offset 10h: LE - Legacy Elimination Register....................................... 722
18.2.2.11 Offset 12h: TTMR - TCO Timer Initial Value Register ............................ 723
18.3 TCO Signal Usage............................................................................................ 723
18.3.1
INTRUDER# Signal ................................................................................. 723
18.3.2
Pin Straps ............................................................................................. 723
18.3.3
SMLINK Signals ..................................................................................... 723
18.4 TCO Theory of Operation .................................................................................. 723
18.4.1
Overview .............................................................................................. 723
18.4.2
Detecting a DOA CPU or System............................................................... 724
18.4.3
Handling an Operating System Lockup ...................................................... 724
18.4.4
Handling a CPU or Other Hardware Lockup ................................................ 725
18.4.5
Handling an Intruder .............................................................................. 725
18.4.6
Handling a Potentially Failing Power Supply ............................................... 725
18.4.7
Handling an ECC Error or Other Memory Error............................................ 726
18.4.8
SMM to Operating System and Operating System to SMM Calls .................... 726
18.4.9
Detecting an Improper FWH Programming ................................................. 726
18.4.10 IRQ1 and IRQ12 for Legacy Elimination .................................................... 726
18.5 Event Reporting via SMLink/SMBus ................................................................... 727
18.5.1
Overview .............................................................................................. 727
18.5.1.1
TCO Compatible Mode ..................................................................... 727
18.5.2
Message Format..................................................................................... 731
18.5.3
Connecting an External LAN Controller ...................................................... 732
19.0 LPC Interface: Bus 0, Device 31, Function 0........................................................... 733
19.1 Overview ....................................................................................................... 733
19.2 LPC Interface Configuration Register Details........................................................ 733
19.2.1
PCI Configuration Registers ..................................................................... 734
19.2.1.1
Offset 00h: ID: Vendor Identification Register .................................... 734
19.2.1.2
Offset 04h: CMD: Device Command Register ...................................... 735
19.2.1.3
Offset 06h: STS: Status Register ...................................................... 736
19.2.1.4
Offset 08h: RID - Revision ID Register............................................... 736
19.2.1.5
Offset 09h: CC: Class Code Register.................................................. 737
19.2.1.6
Offset 0Dh: MLT: Master Latency Timer Register ................................. 737
19.2.1.7
Offset 0Eh: HTYPE: Header Type Register .......................................... 738
August 2009
Order Number: 320066-003US
Intel® EP80579 Integrated Processor Product Line Datasheet
19
Contents
19.2.1.8
Offset 2Ch: SID: Subsystem Identifiers Register.................................. 738
19.2.2
ACPI/GPIO Configuration Registers ........................................................... 738
19.2.2.1
Offset 40h: ABASE: ACPI Base Address Register.................................. 738
19.2.2.2
Offset 44h: ACT: ACPI Control Register .............................................. 739
19.2.2.3
Offset 48h: GBA: GPIO Base Address Register..................................... 740
19.2.2.4
Offset 4Ch: GC: GPIO Control Register ............................................... 741
19.2.3
Interrupt Configuration Registers .............................................................. 741
19.2.3.1
Offset 60h: PARC: PIRQA Routing Control Register .............................. 741
19.2.3.2
Offset 61h: PBRC: PIRQB Routing Control Register .............................. 742
19.2.3.3
Offset 62h: PCRC: PIRQC Routing Control Register .............................. 742
19.2.3.4
Offset 63h: PDRC: PIRQD Routing Control Register .............................. 743
19.2.3.5
Offset 64h: SCNT: Serial IRQ Control Register..................................... 744
19.2.3.6
Offset 68h: PERC: PIRQE Routing Control Register............................... 745
19.2.3.7
Offset 69h: PFRC: PIRQF Routing Control Register ............................... 745
19.2.3.8
Offset 6Ah: PGRC: PIRQG Routing Control Register .............................. 746
19.2.3.9
Offset 6Bh: PHRC: PIRQH Routing Control Register .............................. 747
19.2.4
LPC I/O Configuration Registers................................................................ 747
19.2.4.1
Offset 80h: iOD: i/O Decode Ranges Register...................................... 747
19.2.4.2
Offset 82h: IOE: I/O Enables Register ................................................ 749
19.2.4.3
Offset 84h: LG1: LPC Generic Decode Range 1 Register........................ 750
19.2.4.4
Offset 88h: LG2: LPC Generic Decode Range 2 Register........................ 751
19.2.5
Power Management Configuration Registers ............................................... 751
19.2.6
FWH Configuration Registers .................................................................... 751
19.2.6.1
Offset D0h: FS1: FWH ID Select 1 Register ......................................... 751
19.2.6.2
Offset D4h: FS2: FWH ID Select 2 Register ......................................... 753
19.2.6.3
Offset D8h: FDE: FWH Decode Enable Register.................................... 754
19.2.6.4
Offset DCh: BC: BIOS Control Register............................................... 756
19.2.7
Root Complex Register Block Configuration Register .................................... 756
19.2.7.1
Offset F0h: RCBA: Root Complex Base Address Register ....................... 756
19.2.8
Manufacturing Information Register .......................................................... 757
19.2.8.1
Offset F8h: MANID: Manufacturer ID Register ..................................... 757
19.3 Interface ........................................................................................................ 757
19.3.1
Overview............................................................................................... 758
19.3.2
Cycle Types ........................................................................................... 758
19.3.3
Aborting a Cycle ..................................................................................... 759
19.3.4
Memory Cycle Notes ............................................................................... 759
19.3.5
I/O Cycle Notes ...................................................................................... 760
19.3.6
DMA Cycle Notes .................................................................................... 760
19.3.7
Bus Master Cycle Notes ........................................................................... 760
19.3.8
FWH Cycle Notes .................................................................................... 760
19.3.9
LPC PD# Protocol ................................................................................... 760
19.3.10 Cycle Posting Policies .............................................................................. 760
19.3.11 Configuration ......................................................................................... 761
19.3.11.1 LPC Interface Decoders .................................................................... 761
19.3.11.2 Bus Master Device Mapping and START Fields ..................................... 761
19.3.11.3 Firmware Memory IDSEL fields.......................................................... 761
19.3.12 SERR# Generation ................................................................................. 761
20.0 LPC DMA ................................................................................................................ 763
20.1 Overview ........................................................................................................ 763
20.2 LPC DMA I/O-Mapped Register Details ................................................................ 764
20.2.1
Register Descriptions .............................................................................. 766
20.2.1.1
Offset 00h: DMA_BCA[0-3] - DMA Base and Current Address Registers for
Channels 0-3 .................................................................................. 766
20.2.1.2
Offset C4h: DMA_BCA[5-7] - DMA Base and Current Address Registers for
Channels 5-7 .................................................................................. 767
Intel® EP80579 Integrated Processor Product Line Datasheet
20
August 2009
Order Number: 320066-003US
Contents
20.2.1.3
Offset 01h: DMA_BCC[0-3] - DMA Base and Current Count Registers for
Channels 0-3 ................................................................................. 768
20.2.1.4
Offset C6h: DMA_BCC[5-7] - DMA Base and Current Count Registers for
Channels 5-7 ................................................................................. 769
20.2.1.5
Offset 08h: DMA_COMMAND - DMA Command Register........................ 770
20.2.1.6
Offset 87h: DMA_MPL[0-3] - DMA Memory Low Page Registers for Channels
0-3 ............................................................................................... 771
20.2.1.7
Offset 8Bh: DMA_MPL[5-7] - DMA Memory Low Page Registers for Channels
5-7 ............................................................................................... 771
20.2.1.8
Offset 08h: DMA_STATUS - DMA Status Register ................................ 772
20.2.1.9
Offset 0Ah: DMA_WSM - DMA Write Single Mask Register .................... 773
20.2.1.10 Offset 0Bh: DMA_CHM - DMA Channel Mode Register .......................... 774
20.2.1.11 Offset 0Ch: DMA_CBP - DMA Clear Byte Pointer Register...................... 775
20.2.1.12 Offset 0Dh: DMA_MC - DMA Master Clear Register .............................. 775
20.2.1.13 Offset 0Eh: DMA_CM - DMA Clear Mask Register ................................. 776
20.2.1.14 Offset 0Fh: DMA_WAM - DMA Write All Mask Register .......................... 777
20.3 DMA Channel Arbitration .................................................................................. 778
20.4 Special Cases in Address/Count......................................................................... 779
20.4.1
Address Overrun/Underrun ...................................................................... 779
20.4.2
16-Bit Channels ..................................................................................... 779
20.4.3
Autoinitialize ......................................................................................... 779
20.4.4
Software Commands .............................................................................. 779
20.5 Theory of Operation for LPC DMA....................................................................... 780
20.5.1
Asserting DMA Requests ......................................................................... 780
20.5.2
Abandoning DMA Requests ...................................................................... 780
20.5.3
General Flow of DMA Transfers ................................................................ 781
20.5.4
Terminal Count ...................................................................................... 781
20.5.5
Verify Mode ........................................................................................... 782
20.5.6
DMA Request Deassertion ....................................................................... 782
20.5.7
SYNC Field/LDRQ# Rules......................................................................... 783
21.0 Serial Peripheral Interface .................................................................................... 785
21.1 Overview ....................................................................................................... 785
21.1.1
Features ............................................................................................... 785
21.2 External Interface ........................................................................................... 785
21.3 SPI Protocol.................................................................................................... 786
21.3.1
SPI Pin-Level Protocol ............................................................................. 786
21.3.1.1
Addressing..................................................................................... 787
21.3.1.2
Data Transaction ............................................................................ 787
21.3.1.3
Bus Errors .................................................................................... 788
21.3.1.4
Instructions ................................................................................... 788
21.3.1.5
SPI Timings ................................................................................... 789
21.4 Host Side Interface.......................................................................................... 789
21.4.1
SPI Host Interface Registers .................................................................... 789
21.4.2
Register Overview .................................................................................. 789
21.4.2.1
Offset 3020h: SPIS – SPI Status ....................................................... 790
21.4.2.2
Offset 3022h: SPIC – SPI Control...................................................... 791
21.4.2.3
Offset 3024h: SPIA – SPI Address ..................................................... 792
21.4.2.4
Offset 3028h: SPID0 – SPI Data 0..................................................... 792
21.4.2.5
SPID[0-6] – SPI Data N ................................................................... 793
21.4.2.6
Offset 3070h: BBAR – BIOS Base Address .......................................... 793
21.4.2.7
Offset 3074h: PREOP – Prefix Opcode Configuration ............................ 794
21.4.2.8
Offset 3076h: OPTYPE – Opcode Type Configuration ............................ 794
21.4.2.9
Offset 3078h: OPMENU – Opcode Menu Configuration .......................... 795
21.4.2.10 Offset 3080h: PBR0 – Protected BIOS Range [0-2] .............................. 796
21.4.3
Running SPI Cycles from the Host ............................................................ 797
21.4.3.1
Memory Reads ............................................................................... 797
21.4.3.2
Generic Programmed Commands ...................................................... 799
August 2009
Order Number: 320066-003US
Intel® EP80579 Integrated Processor Product Line Datasheet
21
Contents
21.4.3.3
Flash Protection .............................................................................. 800
21.4.3.4
Decoding Memory Ranges for SPI ...................................................... 801
21.5 BIOS Programming Considerations ..................................................................... 801
21.5.1
SPI Initialization ..................................................................................... 801
22.0 General Purpose I/O: Bus 0, Device 31, Function 0 ................................................ 803
22.1 Overview ........................................................................................................ 803
22.1.1
GPIO Summary Table.............................................................................. 805
22.2 General Purpose I/O-Mapped Configuration Register Details .................................. 806
22.2.1
Register Descriptions .............................................................................. 807
22.2.1.1
Offset 00h: GPIO_USE_SEL1 -GPIO Use Select 1 {31:0}
Register ......................................................................................... 807
22.2.1.2
Offset 04h: GP_IO_SEL1 - GPIO Input/Output Select 1 {31:0}
Register ......................................................................................... 808
22.2.1.3
Offset 0Ch: GP_LVL1 - GPIO Level 1 for Input or Output {31:0}
Register ......................................................................................... 809
22.2.1.4
Offset 18h: GPO_BLINK - GPIO Blink Enable Register ........................... 810
22.2.1.5
Offset 2Ch: GPI_INV - GPIO Signal Invert Register .............................. 812
22.2.1.6
Offset 30h: GPIO_USE_SEL2 - GPIO Use Select 2 {63:32}
Register ......................................................................................... 813
22.2.1.7
Offset 34h: GP_IO_SEL2 - GPIO Input/Output Select 2 {63:32} Register 813
22.2.1.8
Offset 38h: GP_LVL2 - GPIO Level for Input or
Output 2 {63:32} Register ............................................................... 814
22.3 Additional GPIO Theory of Operation .................................................................. 815
22.3.1
SMI# and SCI Routing ............................................................................ 815
22.3.2
Triggering.............................................................................................. 815
23.0 SATA: Bus 0, Device 31, Function 2 ........................................................................ 817
23.1 SATA PCI Configuration Registers ...................................................................... 817
23.1.1
PCI Header ............................................................................................ 819
23.1.1.1
Offset 00h: ID - Identifiers Register ................................................... 819
23.1.1.2
Offset 04h: CMD - Command Register................................................ 819
23.1.1.3
Offset 06h: STS - Device Status Register............................................ 820
23.1.1.4
Offset 08h: RID - Revision ID Register ............................................... 821
23.1.1.5
PI - Programming Interface Register .................................................. 822
23.1.1.6
Offset 0Ah: CC - Class Code Register ................................................. 823
23.1.1.7
Offset 0Dh: MLT – Master Latency Timer Register ................................ 823
23.1.1.8
Offset 10h: PCMDBA – Primary Command Block Base Address
Register ......................................................................................... 823
23.1.1.9
Offset 14h: PCTLBA – Primary Control Block Base Address Register........ 824
23.1.1.10 Offset 18h: SCMDBA – Secondary Command Block Base
Address Register ............................................................................. 824
23.1.1.11 Offset 1Ch: SCTLBA – Secondary Control Block Base Address
Register ......................................................................................... 825
23.1.1.12 Offset 20h: LBAR – Legacy Bus Master Base Address Register ............... 825
23.1.1.13 Offset 24h: ABAR – AHCI Base Address Register.................................. 826
23.1.1.14 Offset 2Ch: SS - Sub System Identifiers Register................................. 827
23.1.1.15 Offset 34h: CAP – Capabilities Pointer Register.................................... 827
23.1.1.16 Offset 3Ch: INTR - Interrupt Information Register ............................... 828
23.1.2
Additional SFF-8038i Configuration Registers.............................................. 828
23.1.2.1
Offset 40h: PTIM – Primary Timing Register ........................................ 829
23.1.2.2
STIM – Secondary Timing Register .................................................... 830
23.1.2.3
Offset 44h: D1TIM – Device 1 IDE Timing Register .............................. 830
23.1.2.4
Offset 48h: SYNCC – Synchronous DMA Control Register ...................... 831
23.1.2.5
Offset 4Ah: SYNCTIM – Synchronous DMA Timing Register ................... 832
23.1.2.6
Offset 54h: IIOC – IDE I/O Configuration Register ............................... 833
23.1.3
PCI Power Management Capabilities .......................................................... 834
23.1.3.1
Offset 70h: Offset 70h: PID – PCI Power Management Capability ID Register
834
Intel® EP80579 Integrated Processor Product Line Datasheet
22
August 2009
Order Number: 320066-003US
Contents
23.1.3.2
23.1.3.3
Offset 72h: PC – PCI Power Management Capabilities Register .............. 834
Offset 74h: PMCS – PCI Power Management Control And
Status Register............................................................................... 835
23.1.4
Message Signaled Interrupt Capability ...................................................... 836
23.1.4.1
Offset 80h: MID – Message Signaled Interrupt Identifiers Register ........ 836
23.1.4.2
Offset 82h: MC – Message Signaled Interrupt Message
Control Register.............................................................................. 837
23.1.4.3
Offset 84h: MA – Message Signaled Interrupt Message
Address Register............................................................................. 838
23.1.4.4
Offset 88h: MD – Message Signaled Interrupt Message
Data Register ................................................................................. 838
23.1.5
Additional Configuration Registers ............................................................ 838
23.1.5.1
Offset 90h: MAP – Port Mapping Register ........................................... 839
23.1.5.2
Offset 92h: PCS – Port Control and Status Register ............................. 839
23.1.6
Serial ATA Capability Registers................................................................. 841
23.1.6.1
Offset A8h: SATACR0 – Serial ATA Capability Register 0....................... 841
23.1.6.2
Offset ACh: SATACR1 – Serial ATA Capability Register 1 ...................... 841
23.1.7
Additional Configuration Registers ............................................................ 842
23.1.7.1
Offset C0h: ATC – APM Trapping Control Register................................ 842
23.1.7.2
Offset C4h: ATS – ATM Trapping Status Register................................. 843
23.1.7.3
Offset D0h: SP – Scratch Pad Register ............................................... 844
23.1.7.4
Offset E0h: BFCS – BIST FIS Control/Status Register........................... 844
23.1.7.5
Offset E4h: BFTD1 – BIST FIS Transmit Data 1 Register....................... 846
23.1.7.6
Offset E8h: BFTD2 – BIST FIS Transmit Data 2 Register....................... 846
23.1.7.7
Offset F8h: MANID – Manufacturing ID Register .................................. 847
23.2 SATA I/O Mapped Registers .............................................................................. 847
23.2.1
Primary Devices ..................................................................................... 848
23.2.1.1
Offset 00h: PCMD – Primary Command Register ................................. 848
23.2.1.2
Offset 02h: PSTS – Primary Status Register........................................ 849
23.2.1.3
Offset 04h: PDTP – Primary Descriptor Table Pointer Register ............... 849
23.2.2
Secondary Devices ................................................................................. 850
23.2.2.1
Offset 08h: SCMD – Secondary Command Register ............................. 850
23.2.2.2
Offset 0Ah: SSTS – Secondary Status Register ................................... 850
23.2.2.3
Offset 0Ch: SDTP – Secondary Descriptor Table Pointer Register ........... 850
23.2.3
AHCI Index and Data Registers ................................................................ 850
23.2.3.1
Offset 10h: INDEX – AHCI Index Register .......................................... 850
23.2.3.2
Offset 14h: DATA – AHCI Data Register ............................................. 851
23.3 SATA Memory Mapped Registers ....................................................................... 851
23.3.1
Generic Host Controller ........................................................................... 852
23.3.1.1
Offset 00h: HCAP – HBA Capabilities Register ..................................... 853
23.3.1.2
Offset 04h: GHC – Global HBA Control Register................................... 855
23.3.1.3
Offset 08h: IS – Interrupt Status Register .......................................... 856
23.3.1.4
Offset 0Ch: PI – Ports Implemented Register ...................................... 856
23.3.1.5
Offset 10h: VS – AHCI Version Register ............................................. 857
23.3.2
Vendor Specific Registers ........................................................................ 857
23.3.2.1
Offset A0h: SGPO - SPGIO Control Register........................................ 857
23.3.3
Port DMA Registers................................................................................. 858
23.3.3.1
Offset 100h: PxCLB[0-1] – Port [0-1] Command List Base Address Register..
858
23.3.3.2
Offset 104h: PxCLBU[0-1] – Port [0-1] Command List Base Address Upper 32bits Register................................................................................... 858
23.3.3.3
Offset 108h: PxFB[0-1] – Port [0-1] FIS Base Address Register............. 859
23.3.3.4
Offset 10Ch: PxFBU[0-1] – Port [0-1] FIS Base Address Upper 32-bits
Register ........................................................................................ 859
23.3.3.5
Offset 110h: PxIS[0-1] – Port [0-1] Interrupt Status Register ............... 860
23.3.3.6
Offset 114h: PxIE[0-1] – Port [0-1] Interrupt Enable Register............... 861
23.3.3.7
Offset 118h: PxCMD[0-1] – Port [0-1] Command Register.................... 863
23.3.4
Port Interface Registers (One Set Per Port) ................................................ 866
August 2009
Order Number: 320066-003US
Intel® EP80579 Integrated Processor Product Line Datasheet
23
Contents
23.3.4.1
Offset 120h: PxTFD[0-1] – Port [0-1] Task File Data Register................ 866
23.3.4.2
Offset 124h: PxSIG[0-1] – Port [0-1] Signature Register ...................... 867
23.3.4.3
Offset 128h: PxSSTS[0-1] – Port [0-1] Serial ATA Status Register ......... 868
23.3.4.4
Offset 12Ch: PxSCTL[0-1] – Port [0-1] Serial ATA Control Register ........ 869
23.3.4.5
Offset 130h: PxSERR[0-1] – Port [0-1] Serial ATA Error Register ........... 870
23.3.4.6
Offset 134h: PxSACT[0-1] – Port [0-1] Serial ATA Active Register.......... 872
23.3.4.7
Offset 138h: PxCI[0-1] – Port [0-1] Command Issue Register ............... 872
23.3.4.8
Offset 13Ch: PxSNTF[0-1] – Port [0-1] SNotification Register................ 873
23.4 Overview ........................................................................................................ 873
23.5 Legacy Operation............................................................................................. 873
23.5.1
Transfer Examples .................................................................................. 873
23.5.1.1
Register FIS Only ............................................................................ 873
23.5.1.2
Non-Queued DMA Data Transfers ...................................................... 874
23.5.1.3
SW Assisted Queued DMA Transfer .................................................... 875
23.5.2
Error Handling........................................................................................ 876
23.5.2.1
Errors on DMI ................................................................................. 876
23.5.2.2
Errors on SATA Interface .................................................................. 876
23.5.3
Hot Plug Operation ................................................................................. 878
23.5.4
48-Bit (“Large”) LBA Operation Requirements............................................. 878
23.5.5
Power Management Operation .................................................................. 879
23.5.5.1
Introduction ................................................................................... 879
23.5.5.2
Power State Mappings...................................................................... 879
23.5.5.3
Power State Transitions ................................................................... 880
23.5.5.4
SMI Trapping (APM) ........................................................................ 881
23.5.6
Interrupt Architecture ............................................................................. 882
23.5.7
Staggered Spin-up.................................................................................. 882
23.5.8
HW/SW Operation for Detecting an SATA Device Presence ........................... 882
23.5.8.1
Introduction ................................................................................... 882
23.5.8.2
Hardware Flow................................................................................ 882
23.5.8.3
Software Flow................................................................................. 883
23.5.9
SMI Generation ...................................................................................... 883
23.5.10 LED ...................................................................................................... 884
23.6 AHCI Operation ............................................................................................... 884
23.6.1
System Memory Structures ...................................................................... 884
23.6.2
Error Reporting and Recovery................................................................... 885
23.6.2.1
Error Types .................................................................................... 885
23.6.2.2
Error Recovery................................................................................ 888
23.6.3
Hot Plug Operation ................................................................................. 888
23.6.4
Power Management Operation .................................................................. 889
23.6.4.1
Introduction ................................................................................... 889
23.6.4.2
Power State Mappings...................................................................... 889
23.6.4.3
Power State Transitions ................................................................... 890
23.6.4.4
PME............................................................................................... 892
23.7 Additional Information ...................................................................................... 892
23.7.1
Mode Switching ...................................................................................... 892
23.7.1.1
AHCI Mode ..................................................................................... 893
23.7.1.2
IDE Mode ....................................................................................... 893
24.0 SMBus Controller Functional Description: Bus 0, Device 31, Function 3 ................. 895
24.1 Overview ........................................................................................................ 895
24.1.1
Host Controller ....................................................................................... 895
24.1.2
Slave Interface....................................................................................... 896
24.2 SMBus Controller PCI Configuration Register Details ............................................. 896
24.2.1
SMBus Controller PCI Configuration Register Descriptions ............................ 897
24.2.1.1
Offset 00h: VID: Vendor ID Register .................................................. 897
24.2.1.2
Offset 02h: DID: Device ID Register .................................................. 897
24.2.1.3
Offset 04h: CMD: Command Register................................................. 897
Intel® EP80579 Integrated Processor Product Line Datasheet
24
August 2009
Order Number: 320066-003US
Contents
24.2.1.4
Offset 06h: DS – Device Status Register ............................................ 898
24.2.1.5
Offset 08h: RID: Revision ID Register................................................ 899
24.2.1.6
Offset 09h: PI: Programming Interface Register .................................. 900
24.2.1.7
Offset 0Ah: SCC: Sub Class Code Register ......................................... 900
24.2.1.8
Offset 0Bh: BCC: Base Class Code Register ........................................ 900
24.2.1.9
Offset 20h: SM_BASE: SMB Base Address Register.............................. 901
24.2.1.10 Offset 2Ch: SVID: SVID Register ...................................................... 901
24.2.1.11 Offset 2Eh: SID: Subsystem Identification Register ............................. 902
24.2.1.12 Offset 3Ch: INTLN: Interrupt Line Register ......................................... 902
24.2.1.13 Offset 3Dh: NTPN: Interrupt Pin Register ........................................... 903
24.2.1.14 Offset 40h: HCFG: Host Configuration Register ................................... 903
24.2.1.15 Offset F8h: MANID: Manufacturer ID Register..................................... 904
24.3 SMBus Controller I/O-Mapped Configuration Register Details ................................. 905
24.3.1
SMBus Controller I/O-Mapped Configuration Register Descriptions ................ 906
24.3.1.1
Offset 00h: HSTS: Host Status Register ............................................. 906
24.3.1.2
Offset 02h: HCTL: Host Control Register ............................................ 908
24.3.1.3
Offset 03h: HCMD: Host Command Register ....................................... 912
24.3.1.4
Offset 04h: TSA: Transmit Slave Address Register............................... 912
24.3.1.5
Offset 05h: HD0: Data 0 Register ..................................................... 913
24.3.1.6
Offset 06h: HD1: Data 1 Register ..................................................... 913
24.3.1.7
Offset 07h: HBD: Host Block Data Register......................................... 914
24.3.1.8
Offset 08h: PEC: Packet Error Check Data Register.............................. 915
24.3.1.9
Offset 0Ch: AUXS: Auxiliary Status Register ....................................... 915
24.3.1.10 Offset 0Dh: AUXC: Auxiliary Control Register...................................... 916
24.3.1.11 Offset 0Eh: SMLC: SMLINK_PIN_CTL Register..................................... 916
24.3.1.12 Offset 0Fh: SMBC: SMBUS_PIN_CTL Register ..................................... 917
24.4 Host Controller................................................................................................ 918
24.4.1
Overview .............................................................................................. 918
24.4.2
Command Protocols................................................................................ 918
24.4.2.1
Quick Command ............................................................................. 918
24.4.2.2
Send Byte/Receive Byte................................................................... 919
24.4.2.3
Write Byte/Word............................................................................. 920
24.4.2.4
Read Byte/Word ............................................................................. 921
24.4.2.5
Process Call ................................................................................... 922
24.4.2.6
Block Read/Write ............................................................................ 923
24.4.2.7
I2C Read ...................................................................................... 925
24.4.2.8
Block Write-Block Read Process Call .................................................. 926
24.4.3
I2C Behavior ......................................................................................... 928
24.4.4
Heartbeat for Use with External LAN ......................................................... 928
24.5 Bus Arbitration................................................................................................ 928
24.6 Bus Timings.................................................................................................... 928
24.6.1
Clock Stretching..................................................................................... 928
24.6.2
Bus Time Out (CMI as SMB Master) ......................................................... 929
24.7 Interrupts/SMI#.............................................................................................. 929
24.8 CRC Generation and Checking ........................................................................... 930
24.8.1
Slave Interface I/O Space ....................................................................... 930
24.8.2
Register Details ..................................................................................... 931
24.8.2.1
Offset 09h: RSA: Receive Slave Address Register ................................ 931
24.8.2.2
Offset 0Ah: SD: Slave Data Register ................................................. 931
24.8.2.3
Offset 10h: SSTS: Slave Status Register ............................................ 932
24.8.2.4
Offset 11h: SCMD: Slave Command Register ...................................... 932
24.8.2.5
Offset 14h: NDA: Notify Device Address Register ................................ 933
24.8.2.6
Offset 16h: NDLB: Notify Data Low Byte Register ................................ 934
24.8.2.7
Offset 17h: NDHB: Notify Data High Byte Register .............................. 934
24.9 Slave Interface Behavioral Description ............................................................... 935
24.9.1
Format of Slave Write Cycle..................................................................... 935
24.9.2
Format of Read Command ....................................................................... 936
24.9.3
Format of the Host Notify Command ......................................................... 938
August 2009
Order Number: 320066-003US
Intel® EP80579 Integrated Processor Product Line Datasheet
25
Contents
25.0 USB (1.1) Controller: Bus 0, Device 29, Function 0................................................. 941
25.1 USB (1.1) Controller Configuration Register Details .............................................. 941
25.1.1
Register Details ...................................................................................... 942
25.1.1.1
ID - Identifiers Register ................................................................... 942
25.1.1.2
PCICMD - Command Register............................................................ 942
25.1.1.3
PCISTS - Device Status Register........................................................ 943
25.1.1.4
RID - Revision ID Register ................................................................ 944
25.1.1.5
SUBC - Sub Class Code Register........................................................ 945
25.1.1.6
BCC - Base Class Code Register ........................................................ 945
25.1.1.7
MLT - Master Latency Timer Register ................................................. 945
25.1.1.8
HDR - Header Type Register ............................................................. 946
25.1.1.9
USBIOBAR - Base Address Register ................................................... 946
25.1.1.10 USBx_SVID - USB Subsystem Vendor ID Register................................ 947
25.1.1.11 USBx_SID - USB Subsystem ID Register ............................................ 947
25.1.1.12 INTL - Interrupt Line Register ........................................................... 948
25.1.1.13 INTP - Interrupt Pin Register............................................................. 948
25.1.1.14 SBRN - Serial Bus Release Number Register........................................ 948
25.1.1.15 USBLKMCR - USB Legacy Keyboard/Mouse Control Register .................. 949
25.1.1.16 USBREN - USB Resume Enable Register ............................................. 951
25.1.1.17 USBCWP - USB Core Well Policy Register ............................................ 951
25.1.1.18 MANID - Manufacturer ID Register..................................................... 952
25.2 USB (1.1) Controller I/O-Mapped Register Details ................................................ 953
25.2.1
Register Details ...................................................................................... 953
25.2.1.1
USBCMD: USB Command Register ..................................................... 953
25.2.1.2
USBSTS: USB Status Register ........................................................... 957
25.2.1.3
USBINTR: USB Interrupt Enable Register............................................ 958
25.2.1.4
FRNUM: Frame Number Register ....................................................... 959
25.2.1.5
FRBASEADD: Frame List Base Address Register................................... 960
25.2.1.6
SOFMOD: Start of Frame Modify Register ........................................... 960
25.2.1.7
PSCR - Port Status and Control Register ............................................. 962
25.3 Data Transfers to/from Main Memory ................................................................. 964
25.4 Data Structures in Main Memory ........................................................................ 964
25.5 Data Transfers To/From Main Memory ................................................................ 964
25.5.1
Executing the Schedule ........................................................................... 965
25.5.2
Processing Transfer Descriptors ................................................................ 965
25.5.3
Command Register, Status Register, and TD Status Bit Interaction................ 966
25.5.4
Transfer Queuing.................................................................................... 966
25.6 USB Buffer Management ................................................................................... 969
25.7 Data Encoding and Bit Stuffing .......................................................................... 970
25.8 Bus Protocol.................................................................................................... 970
25.8.1
Bit Ordering ........................................................................................... 970
25.8.2
SYNC Field............................................................................................. 970
25.8.3
Packet Field Formats ............................................................................... 970
25.8.3.1
Packet Identifier Field ...................................................................... 971
25.8.4
Address Fields ........................................................................................ 971
25.8.4.1
Address Field .................................................................................. 971
25.8.4.2
Endpoint Field................................................................................. 971
25.8.5
Frame Number Field................................................................................ 971
25.8.6
Data Field.............................................................................................. 971
25.8.7
Cyclic Redundancy Check (CRC) ............................................................... 972
25.9 Packet Formats ............................................................................................... 972
25.10 USB Interrupts ................................................................................................ 972
25.10.1 Overview............................................................................................... 972
25.10.2 Transaction-Based Interrupts ................................................................... 972
25.10.2.1 CRC Error/Time-out ......................................................................... 972
25.10.2.2 Interrupt on Completion ................................................................... 973
25.10.2.3 Short Packet Detect......................................................................... 973
Intel® EP80579 Integrated Processor Product Line Datasheet
26
August 2009
Order Number: 320066-003US
Contents
25.10.2.4 Serial Bus Babble............................................................................ 973
25.10.2.5 Stalled .......................................................................................... 973
25.10.2.6 Data Buffer Error ............................................................................ 973
25.10.2.7 Bit Stuff Error................................................................................. 974
25.10.3 Non-Transaction Based Interrupts ............................................................ 974
25.10.3.1 Resume Received ........................................................................... 974
25.10.3.2 Process Error ................................................................................. 974
25.10.3.3 Host System Error .......................................................................... 974
25.10.3.4 Implementation Notes ..................................................................... 974
25.11 USB Power Management .................................................................................. 974
25.12 USB Legacy Keyboard Operation ....................................................................... 975
26.0 USB 2.0 Host Controller: Bus 0, Device 29, Function 7 .......................................... 977
26.1 Overview ....................................................................................................... 977
26.2 USB 2.0 PCI Configuration Registers .................................................................. 978
26.2.1
Register Details ..................................................................................... 979
26.2.1.1
Offset 00h: VID - Vendor ID Register ................................................ 979
26.2.1.2
Offset 02h: DID - Device Identification Register .................................. 979
26.2.1.3
Offset 04h: CMD - Command Register ............................................... 980
26.2.1.4
Offset 06h: DSR - Device Status Register........................................... 981
26.2.1.5
Offset 08h: RID - Revision ID Register............................................... 983
26.2.1.6
Offset 09h: PI - Programming Interface Register ................................. 983
26.2.1.7
Offset 0Ah: SCC - Sub Class Code Register ........................................ 983
26.2.1.8
Offset 0Bh: BCC - Base Class Code Register ....................................... 984
26.2.1.9
Offset 0Dh: MLT - Master Latency Timer Register ................................ 984
26.2.1.10 Offset 10h: MBAR - Memory Base Address Register ............................. 985
26.2.1.11 Offset 2Ch: SSVID - USB 2.0 Subsystem Vendor ID Register ................ 985
26.2.1.12 Offset 2Eh: SSID - USB 2.0 Subsystem ID Register ............................ 986
26.2.1.13 Offset 34h: CAP_PTR - Capabilities Pointer Register ............................ 986
26.2.1.14 Offset 3Ch: ILINE - Interrupt Line Register......................................... 987
26.2.1.15 Offset 3Dh: IPIN - Interrupt Pin Register............................................ 987
26.2.1.16 Offset 50h: PM_CID - PCI Power Management Capability ID
Register ........................................................................................ 987
26.2.1.17 Offset 51h: PM_NEXT - Next Item Pointer #1 Register ........................ 988
26.2.1.18 Offset 52h: PM_CAP - Power Management Capabilities Register............. 989
26.2.1.19 Offset 54h: PM_CS - Power Management Control/Status Register .......... 990
26.2.1.20 Offset 58h: DP_CID - Debug Port Capability ID Register ...................... 991
26.2.1.21 Offset 59h: DP_NEXT - Next Item Pointer #2 Register ........................ 991
26.2.1.22 Offset 5Ah: DP_BASE - Debug Port Base Offset Register ...................... 991
26.2.1.23 Offset 60h: SBRN - Serial Bus Release Number Register ...................... 992
26.2.1.24 Offset 61h: FLA - Frame Length Adjustment Register........................... 992
26.2.1.25 Offset 62h: PWC - Port Wake Capability Register................................. 993
26.2.1.26 Offset 64h: CUO - Classic USB Override Register................................. 993
26.2.1.27 Offset 68h: ULSEC - USB 2.0 Legacy Support Extended
Capability Register .......................................................................... 994
26.2.1.28 Offset 6Ch: ULSCS - USB 2.0 Legacy Support Control/Status
Register ........................................................................................ 995
26.2.1.29 Offset 70h: ISU2SMI - Intel Specific USB 2.0 SMI Register ................... 997
26.2.1.30 Offset 80h: AC - Access Control Register............................................ 999
26.2.1.31 Offset F8h: MANID - Manufacturer ID Register...................................1000
26.3 USB 2.0 Memory-Mapped I/O Registers.............................................................1001
26.3.1
Host Controller Capability Register Details ................................................1002
26.3.1.1
Offset 00h: CAPLENGTH - Capability Length Register ..........................1002
26.3.1.2
Offset 02h: HCIVERSION - Host Controller Interface Version Number Register
1003
26.3.1.3
Offset 04h: HCSPARAMS - Host Controller Structural Parameters Register ....
1003
26.3.1.4
Offset 08h: HCCPARAMS - Host Controller Capability Parameters Register ....
1004
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Order Number: 320066-003US
Intel® EP80579 Integrated Processor Product Line Datasheet
27
Contents
26.3.2
Host
26.3.2.1
26.3.2.2
26.3.2.3
26.3.2.4
26.3.2.5
Controller Operational Register Details ............................................. 1005
Offset 20h: USB2CMD - USB 2.0 Command Register .......................... 1007
Offset 24h: USB2STS - USB 2.0 Status Register ................................ 1009
Offset 28h: USB2INTR - USB 2.0 Interrupt Enable Register ................. 1011
Offset 2Ch: FRINDEX - Frame Index Register .................................... 1013
Offset 30h: CTRLDSSEGMENT - Control Data Structure
Segment Register.......................................................................... 1013
26.3.2.6
Offset 34h: PERIODICLISTBASE - Periodic Frame List Base Address Register
1014
26.3.2.7
Offset 38h: ASYNCLISTADDR - Current Asynchronous List Address Register .
1015
26.3.2.8
Offset 60h: CONFIGFLAG - Configure Flag Register ............................ 1015
26.3.2.9
Offset 64h: PORTSC - Port N Status and Control Register ................... 1016
26.4 EHC Initialization ........................................................................................... 1021
26.4.1
Power On ............................................................................................ 1021
26.4.2
Driver Initialization ............................................................................... 1021
26.4.3
EHC Resets .......................................................................................... 1021
26.5 Data Structures in Main Memory ...................................................................... 1022
26.6 USB 2.0 Enhanced Host Controller DMA ............................................................ 1022
26.6.1
Periodic List Execution........................................................................... 1022
26.6.1.1
Read Policies for Periodic DMA ........................................................ 1022
26.6.1.2
Write Policies for Periodic DMA ........................................................ 1024
26.6.2
Asynchronous List Execution .................................................................. 1025
26.6.2.1
Read Policies for Asynchronous DMA ................................................ 1025
26.6.2.2
Write Policies for Asynchronous DMA................................................ 1027
26.7 Data Encoding and Bit Stuffing ........................................................................ 1027
26.8 Packet Formats ............................................................................................. 1027
26.9 USB 2.0 Interrupts and Error Conditions ........................................................... 1027
26.9.1
Aborts on USB 2.0-Initiated Memory Reads .............................................. 1028
26.9.2
Host Interface Parity Errors ................................................................... 1028
26.10 USB 2.0 Power Management ........................................................................... 1030
26.10.1 Pause Feature ...................................................................................... 1030
26.10.2 Suspend Feature .................................................................................. 1031
26.10.3 ACPI Device States ............................................................................... 1031
26.10.4 ACPI System States .............................................................................. 1032
26.11 Interaction with Classic Host Controllers ........................................................... 1032
26.11.1 Port-Routing Logic ................................................................................ 1033
26.11.2 Device Connects ................................................................................... 1033
26.11.3 Device Disconnects ............................................................................... 1034
26.11.4 Effect of Resets on Port-Routing Logic ..................................................... 1034
26.12 USB 2.0 Legacy Keyboard Operation ................................................................ 1035
26.13 USB 2.0 Based Debug Port .............................................................................. 1035
26.13.1 USB 2.0 Based Debug Port Overview ....................................................... 1035
26.13.2 Debug Port Register Details ................................................................... 1036
26.13.2.1 Offset A0h: CNTL_STS - Control/Status Register ............................... 1036
26.13.2.2 Offset A4h: USBPID - USB PIDs Register .......................................... 1039
26.13.2.3 Offset A8h: DATABUF - Data Buffer Bytes 7:0 ................................... 1039
26.13.2.4 Offset B0h: CONFIG - Configuration Register .................................... 1040
26.13.3 USB 2.0 Based Debug Port Theory of Operation ........................................ 1040
26.13.3.1 Behavioral Rules ........................................................................... 1040
26.13.3.2 OUT Transactions .......................................................................... 1041
26.13.3.3 IN Transactions............................................................................. 1042
26.13.3.4 Debug Software ............................................................................ 1043
27.0 Power Management ............................................................................................. 1045
27.1 Features ....................................................................................................... 1045
27.2 IMCH-IICH Messages...................................................................................... 1046
Intel® EP80579 Integrated Processor Product Line Datasheet
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August 2009
Order Number: 320066-003US
Contents
27.3 Power Management Register Details .................................................................1047
27.3.1
Power Management PCI Configuration Registers ........................................1047
27.3.1.1
Offset A0h: GEN_PMCON_1 - General PM Configuration 1
Register .......................................................................................1047
27.3.1.2
Offset A2h: GEN_PMCON_2 - General PM Configuration 2
Register .......................................................................................1049
27.3.1.3
Offset A4h: GEN_PMCON_3 - General PM Configuration 3
Register .......................................................................................1051
27.3.1.4
Offset B8h: GPI_ROUT - GPI Routing Control Register.........................1053
27.3.2
APM Power Management I/O-Mapped Registers .........................................1053
27.3.2.1
Offset B2h: APM_CNT - Advanced Power Management Control .Port Register
1054
27.3.2.2
Offset B3h: APM_STS - Advanced Power Management Status ..Port Register
1054
27.3.3
General Power Management I/O-Mapped Registers ....................................1055
27.3.3.1
Offset 00h: PM1_STS – Power Management 1 Status Register..............1056
27.3.3.2
Offset 02h: PM1_EN - Power Management 1 Enables Register ..............1058
27.3.3.3
Offset 04h: PM1_CNT - Power Management 1 Control Register.............1059
27.3.3.4
Offset 08h: PM1_TMR - Power Management 1 Timer Register ..............1060
27.3.3.5
Offset 10h: PROC_CNT - Processor Control Register ...........................1060
27.3.3.6
Offset 14h: LV2 - Level 2 Register....................................................1063
27.3.3.7
Offset 28h: GPE0_STS - General Purpose Event 0 Status Register ........1063
27.3.3.8
Offset 2Ch: PMBASE_GPE0_EN - General Purpose
Event 0 Enables Register ................................................................1066
27.3.3.9
Offset 30h: SMI_EN - SMI Control and Enable Register .......................1068
27.3.3.10 Offset 34h: SMI_STS - SMI Status Register .......................................1070
27.3.3.11 Offset 38h: ALT_GPI_SMI_EN - Alternate GPI SMI Enable
Register .......................................................................................1073
27.3.3.12 Offset 3Ah: ALT_GPI_SMI_STS - Alternate GPI SMI Status
Register .......................................................................................1074
27.3.3.13 Offset 44h: DEVTRAP_STS - DEVTRAP_STS Register...........................1074
27.4 SMI#/SCI Generation .....................................................................................1076
27.4.0.1
PCI Express* SCI...........................................................................1078
27.5 Dynamic Processor Clock Control......................................................................1079
27.5.1
Overview .............................................................................................1079
27.5.2
Transition Rules Among S0/Cx and Sx States............................................1080
27.5.3
S0/C0, S0/C2, Entry/Exit Timings and Sequences......................................1081
27.5.3.1
C0→C2→C0 Timings and Diagram ....................................................1081
27.5.3.2
C0→C2 Entry Sequence ..................................................................1082
27.5.3.3
C2→C0 Break Sequence .................................................................1083
27.6 Sleep States ..................................................................................................1083
27.6.1
Sleep State Overview ............................................................................1083
27.6.2
Initiating Sleep States ...........................................................................1083
27.6.3
Exiting Sleep States ..............................................................................1084
27.6.4
Sx-G3-Sx, Handling Power Failures..........................................................1085
27.7 Processor Thermal Management .......................................................................1086
27.7.1
PROCHOT# Signal for SMI# or SCI ..........................................................1086
27.7.2
Processor Passive Cooling.......................................................................1087
27.7.3
On-Demand Passive Cooling ...................................................................1087
27.7.4
Active Cooling.......................................................................................1087
27.8 Event Input Signals, Messages and Their Usage..................................................1087
27.8.1
PWRBTN# – Power Button ......................................................................1087
27.8.1.1
Power Button Override Function.......................................................1088
27.8.1.2
Sleep Button .................................................................................1088
27.8.2
RI# – Ring Indicate Signal .....................................................................1089
27.8.3
PME# – PCI Power Management Event .....................................................1089
27.8.4
SYS_RESET# Button..............................................................................1089
August 2009
Order Number: 320066-003US
Intel® EP80579 Integrated Processor Product Line Datasheet
29
Contents
27.8.5
Processor Thermal Trip.......................................................................... 1089
27.8.6
SATA SCI ............................................................................................ 1090
27.8.7
PCI Express* PME Event Message ........................................................... 1090
27.9 Alternate (ALT) Access Mode ........................................................................... 1091
27.9.1
Write Only Registers with Read Paths in Alternate Access Mode .................. 1091
27.9.2
PIC Reserved Bits ................................................................................. 1093
27.9.3
Read-Only Registers with Write Paths in ALT Access Mode.......................... 1094
27.10 System Power Supplies, Planes, and Signals...................................................... 1094
27.10.1 Power Plane Control with SLP_S3#, SLP_S4# and SLP_S5# ....................... 1094
27.10.2 SLP_S4# and Suspend-To-RAM Sequencing ............................................. 1094
27.10.3 PWROK Signal ...................................................................................... 1095
27.10.4 CPUPWRGD Signal ................................................................................ 1095
27.10.5 Controlling Leakage and Power Consumption During Low-Power States........ 1095
27.10.6 VRMPWROK ......................................................................................... 1096
27.11 Legacy Power Management Theory of Operation ................................................ 1096
27.11.1 Overview............................................................................................. 1096
27.11.2 APM Power Management........................................................................ 1096
28.0 IA-32 Core Interface ............................................................................................ 1097
28.1 IA-32 Core Interface I/O-Mapped Register Details .............................................. 1097
28.1.1
Register Descriptions ............................................................................ 1098
28.1.1.1
Offset 61h: NMI_SC - NMI Status and Control Register....................... 1098
28.1.1.2
Offset 70h: NMI_EN - NMI Enable (and Real Time Clock Index)
Register ....................................................................................... 1099
28.1.1.3
Offset 92h: PORT92 - Fast A20 and Init Register ............................... 1100
28.1.1.4
Offset F0h: COPROC_ERR - Coprocessor Error Register ...................... 1100
28.1.1.5
Offset CF9h: RST_CNT - Reset Control Register ................................. 1101
28.2 IA-32 Core Interface Signals .......................................................................... 1102
28.2.1
A20M# (Mask A20) ............................................................................... 1102
28.2.2
INIT# (Initialization) ............................................................................. 1102
28.2.3
INTR# (Interrupt Signals)...................................................................... 1103
28.2.4
STPCLK# and CPUSLP# (Stop Clock Request and Processor Sleep Signals) ... 1103
28.2.5
Enhanced Intel SpeedStep Technology (EIST) Signals................................ 1103
28.2.6
DPSLP# (Deeper Sleep)......................................................................... 1103
29.0 Real Time Clock ................................................................................................... 1105
29.1 Overview ...................................................................................................... 1105
29.2 RTC I/O Registers .......................................................................................... 1105
29.3 Real Time Clock Indexed Register Details .......................................................... 1106
29.3.1
Real Time Clock Register Details ............................................................. 1107
29.3.1.1
Offset 0Ah: RTC_REGA - Register A (General Configuration) ............... 1107
29.3.1.2
Offset 0Bh: RTC_REGB - Register B (General Configuration) ............... 1109
29.3.1.3
Offset 0Ch: RTC_REGC - Register C (Flag Register)............................ 1110
29.3.1.4
Offset 0Dh: RTC_REGD - Register D (Flag Register) ........................... 1111
29.4 Update Cycles ............................................................................................... 1112
29.5 Interrupts ..................................................................................................... 1112
29.6 Lockable RAM Ranges..................................................................................... 1112
29.7 Century Rollover............................................................................................ 1112
29.8 Month and Year Alarms .................................................................................. 1113
30.0 Interrupts ............................................................................................................ 1115
30.1 Overview ...................................................................................................... 1115
30.2 8259 Interrupt Controllers (PIC) ...................................................................... 1117
30.2.1
Overview............................................................................................. 1117
30.2.2
I/O Registers ....................................................................................... 1118
30.2.2.1
ICW1[0-1] - Initialization Command Word 1 Register ......................... 1119
30.2.2.2
ICW2[0-1] - Initialization Command Word 2 Register ......................... 1120
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August 2009
Order Number: 320066-003US
Contents
30.2.2.3
30.2.2.4
30.2.2.5
30.2.2.6
MICW3 - Master Initialization Command Word 3 Register ....................1121
SICW3 - Slave Initialization Command Word 3 Register ......................1121
ICW4[0-1] - Initialization Command Word 4 Register..........................1122
OCW1[0-1] - Operational Control Word 1 (Interrupt Mask)
Register .......................................................................................1122
30.2.2.7
OCW2[0-1] - Operational Control Word 2 Register..............................1123
30.2.2.8
OCW3[0-1] - Operational Control Word 3 Register..............................1124
30.2.2.9
ELCR1 - Master Edge/Level Control Register ......................................1125
30.2.2.10 ELCR2 - Slave Edge/Level Control Register ........................................1126
30.2.3
Interrupt Handling.................................................................................1127
30.2.3.1
Generating Interrupts.....................................................................1127
30.2.3.2
Acknowledging Interrupts ...............................................................1127
30.2.3.3
Hardware/Software Interrupt Sequence ............................................1127
30.2.4
Initialization Command Words (ICW) .......................................................1128
30.2.4.1
ICW1 ...........................................................................................1128
30.2.4.2
ICW2 ...........................................................................................1128
30.2.4.3
ICW3 ...........................................................................................1128
30.2.4.4
ICW4 ...........................................................................................1129
30.2.5
Operation Command Words (OCW)..........................................................1129
30.2.6
Modes of Operation ...............................................................................1129
30.2.6.1
Fully Nested Mode..........................................................................1129
30.2.6.2
Special Fully Nested Mode...............................................................1129
30.2.6.3
Automatic Rotation Mode (Equal Priority Devices)...............................1130
30.2.6.4
Specific Rotation Mode (Specific Priority)...........................................1130
30.2.6.5
Poll Mode......................................................................................1130
30.2.6.6
Edge and Level Triggered Mode .......................................................1130
30.2.7
End of Interrupt (EOI) operations ............................................................1131
30.2.7.1
Normal EOI ...................................................................................1131
30.2.7.2
Automatic EOI Mode.......................................................................1131
30.2.8
Masking Interrupts ................................................................................1131
30.2.8.1
Masking on an Individual Interrupt Request.......................................1131
30.2.8.2
Special Mask Mode.........................................................................1131
30.2.9
Steering of PCI Interrupts ......................................................................1131
30.3 Advanced Interrupt Controller: APIC .................................................................1132
30.3.1
Interrupt Handling.................................................................................1132
30.3.2
PCI/PCI Express* Message-Based Interrupts.............................................1132
30.3.2.1
Front Side Bus Interrupt Delivery .....................................................1133
30.3.2.2
Edge-Triggered Operation ...............................................................1133
30.3.2.3
Level-Triggered Operation...............................................................1133
30.3.2.4
Registers Associated with Front-Side Bus Interrupt Delivery ................1133
30.3.2.5
EOI..............................................................................................1133
30.3.2.6
Interrupt Message Format ..............................................................1133
30.3.3
APIC Memory-Mapped Register Details .....................................................1135
30.3.3.1
APIC_IDX - Index Register ..............................................................1135
30.3.3.2
APIC_DAT – Data Register .............................................................1136
30.3.3.3
APIC_EOI - EOI Register .................................................................1136
30.3.4
Index Registers.....................................................................................1137
30.3.4.1
APIC_ID – Identification Register .....................................................1138
30.3.4.2
APIC_VS - Version Register .............................................................1138
30.3.4.3
APIC_RTE[0-39] - Redirection Table Entry.........................................1139
30.4 PCI Interrupts via /PCI Express* ......................................................................1142
30.5 Serial Interrupt ..............................................................................................1142
30.5.1
Overview .............................................................................................1142
30.5.2
Start Frame..........................................................................................1142
30.5.3
Data Frames.........................................................................................1143
30.5.4
Stop Frame ..........................................................................................1143
30.5.5
Serial Interrupts Not Supported via SERIRQ..............................................1143
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Order Number: 320066-003US
Intel® EP80579 Integrated Processor Product Line Datasheet
31
Contents
30.5.6
30.5.7
Special Notes on IRQ14 and IRQ15 ......................................................... 1144
Data Frame Format............................................................................... 1144
31.0 8254 Timers......................................................................................................... 1145
31.1 Overview ...................................................................................................... 1145
31.2 8254 Timer I/O-Mapped Register Details........................................................... 1145
31.2.1
Timer Registers .................................................................................... 1146
31.2.1.1
Offset 43h: TCW - Timer Control Word Register................................. 1146
31.2.1.2
Offset 40h: TSB[0-2] - Interval Timer Status Byte Format
Register ....................................................................................... 1146
31.2.1.3
Offset 40h: TCAP[0-2] - Interval Timer Counter Access Ports
Register ....................................................................................... 1148
31.3 Counters ...................................................................................................... 1148
31.3.1
Counter 0, System Timer....................................................................... 1148
31.3.2
Counter 1, Refresh Request Signal .......................................................... 1148
31.3.3
Counter 2, Speaker Tone ....................................................................... 1148
31.3.4
Counter Operating Modes ...................................................................... 1149
31.4 Timer Programming ....................................................................................... 1149
31.5 Reading from the Interval Timer ...................................................................... 1150
31.5.1
Simple Read ........................................................................................ 1150
31.5.2
Counter Latch Command ....................................................................... 1150
31.5.3
Read Back Command ............................................................................ 1151
32.0 High Precision Event Timers................................................................................. 1153
32.1 Overview ...................................................................................................... 1153
32.2 Register Details ............................................................................................. 1153
32.2.1
Register Descriptions ............................................................................ 1155
32.2.1.1
Offset 000h: GCAP_ID - General Capabilities and ID Register .............. 1155
32.2.1.2
Offset 010h: GEN_CONF - General Configuration Register................... 1156
32.2.1.3
Offset 020h: GINTR_STA - General Interrupt Status Register .............. 1157
32.2.1.4
Offset 0F0h: MAIN_CNT - Main Counter Value Register....................... 1158
32.2.1.5
Offset 100h: HPTCC[0-2] - Timer n Configuration and
Capabilities Register ...................................................................... 1159
32.2.1.6
Offset 108h: HPTCV[0-2] - Timer n Comparator Value Register ........... 1161
32.3 Theory Of Operation....................................................................................... 1164
32.3.1
Timer Accuracy Rules ............................................................................ 1164
32.3.2
Interrupt Mapping................................................................................. 1164
32.3.3
Periodic vs. Non-Periodic Modes.............................................................. 1165
32.3.3.1
Non-Periodic Mode ........................................................................ 1165
32.3.3.2
Periodic Mode ............................................................................... 1165
32.3.4
Enabling the Timers ............................................................................. 1166
32.3.5
Interrupt Levels.................................................................................... 1166
32.3.6
Handling Interrupts............................................................................... 1166
32.3.7
Unloading Device Driver Issues .............................................................. 1167
33.0 Serial I/O Unit and Watchdog Timer .................................................................... 1169
33.1 Overview ...................................................................................................... 1169
33.2 Features ....................................................................................................... 1169
33.3 Functional Description .................................................................................... 1170
33.3.1
Host Processor Interface (LPC) ............................................................... 1170
33.4 LPC Interface ................................................................................................ 1170
33.4.1
LPC Cycles........................................................................................... 1170
33.4.1.1
I/O Read and Write Cycles.............................................................. 1171
33.4.2
Policy.................................................................................................. 1171
33.4.3
LPC Transfers....................................................................................... 1171
33.4.3.1
I/O Transfers ................................................................................ 1171
33.5 Logical Devices 4 and 5: Serial Ports (UART1 and UART2) ................................... 1171
Intel® EP80579 Integrated Processor Product Line Datasheet
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August 2009
Order Number: 320066-003US
Contents
33.5.1
UART Feature List .................................................................................1172
33.5.2
UART Operational Description .................................................................1173
33.5.2.1
Programmable Baud Rate Generator.................................................1174
33.5.3
UART Register Details ............................................................................1175
33.5.3.1
Offset 00h: RBR - Receive Buffer Register .........................................1176
33.5.3.2
Offset 00h: THR - Transmit Holding Register .....................................1176
33.5.3.3
Offset 01h: IER - Interrupt Enable Register .......................................1177
33.5.3.4
Offset 02h: IIR - Interrupt Identification Register ...............................1178
33.5.3.5
Offset 02h: FCR - FIFO Control Register ............................................1180
33.5.3.6
Offset 03h: LCR - Line Control Register.............................................1182
33.5.3.7
Offset 04h: MCR - Modem Control Register........................................1184
33.5.3.8
Offset 05h: LSR - Line Status Register ..............................................1185
33.5.3.9
Offset 06h: MSR - Modem Status Register.........................................1188
33.5.3.10 Offset 07h: SCR - Scratchpad Register .............................................1190
33.5.3.11 Offset 00h: DLL - Programmable Baud Rate Generator Divisor Latch Register
Low .............................................................................................1190
33.5.3.12 Offset 01h: DLH - Programmable Baud Rate Generator Divisor Latch Register
High.............................................................................................1190
33.5.4
FIFO Operation .....................................................................................1191
33.5.4.1
FIFO Interrupt Mode Operation ........................................................1191
33.5.4.2
FIFO Polled Mode Operation ............................................................1192
33.6 Logical Device 6: Watchdog Timer ....................................................................1192
33.6.1
Overview .............................................................................................1192
33.6.2
Watchdog Timer Register Details .............................................................1194
33.6.2.1
Offset 00h: PV1R0 - Preload Value 1 Register 0 .................................1194
33.6.2.2
Offset 01h: PV1R1 - Preload Value 1 Register 1 .................................1195
33.6.2.3
Offset 02h: PV1R2 - Preload Value 1 Register 2 .................................1195
33.6.2.4
Offset 04h: PV2R0 - Preload Value 2 Register 0 .................................1196
33.6.2.5
Offset 05h: PV2R1 - Preload Value 2 Register 1 .................................1196
33.6.2.6
Offset 06h: PV2R2 - Preload Value 2 Register 2 .................................1197
33.6.2.7
Offset 08h: GISR - General Interrupt Status Register..........................1197
33.6.2.8
Offset 0Ch: RR0 - Reload Register 0 .................................................1198
33.6.2.9
Offset 0Dh: RR1 - Reload Register 1.................................................1199
33.6.2.10 Offset 10h: WDTCR - WDT Configuration Register ..............................1199
33.6.2.11 Offset 18h: WDTLR - WDT Lock Register ...........................................1201
33.6.3
Theory Of Operation ..............................................................................1202
33.6.3.1
RTC Well and WDT_TOUT# Functionality ...........................................1202
33.6.3.2
Register Unlocking Sequence...........................................................1202
33.6.3.3
Reload Sequence ...........................................................................1202
33.6.3.4
Low Power State............................................................................1202
33.7 Serial IRQ .....................................................................................................1203
33.7.1
Timing Diagrams For SIW_SERIRQ Cycle..................................................1203
33.7.1.1
SIW_SERIRQ Cycle Control .............................................................1203
33.7.1.2
SIW_SERIRQ Data Frame ...............................................................1204
33.7.1.3
Stop Cycle Control .........................................................................1205
33.7.1.4
Latency ........................................................................................1205
33.7.1.5
EOI/ISR Read Latency ....................................................................1205
33.7.1.6
Reset and Initialization ...................................................................1205
33.8 Configuration .................................................................................................1206
33.8.1
Configuration Port Address ....................................................................1206
33.8.2
Primary Configuration Address Decoder....................................................1206
33.8.2.1
Entering the Configuration State ......................................................1206
33.8.2.2
Exiting the Configuration State ........................................................1206
33.8.2.3
Configuration Sequence ..................................................................1206
33.8.2.4
Configuration Mode ........................................................................1206
33.8.3
SIW Configuration Register Summary ......................................................1207
33.8.3.1
Global Control/Configuration Registers [00h - 2Fh].............................1208
33.8.3.2
Logical Device Configuration Registers [30h — FFh]............................1209
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Order Number: 320066-003US
Intel® EP80579 Integrated Processor Product Line Datasheet
33
Contents
Acceleration and I/O Complex, Volume 4 of 6 ........................... 1213
34.0 PCI-to-PCI Bridge ................................................................................................ 1215
34.1 Summary ..................................................................................................... 1215
34.2 PCI-to-PCI Bridge Detailed Register Descriptions................................................ 1215
34.2.1
PCI-to-PCI Bridge Header ...................................................................... 1216
34.2.2
PCI-to-PCI Bridge Configuration Space .................................................... 1217
34.2.2.1
Offset 0h: VID – Vendor Identification Register ................................. 1217
34.2.2.2
Offset 2h: DID – Device Identification Register.................................. 1217
34.2.2.3
Offset 4h: PCICMD – Device Command Register ................................ 1217
34.2.2.4
Offset 6h: PCISTS – Device Status Register ...................................... 1218
34.2.2.5
Offset 8h: RID – Revision ID Register .............................................. 1219
34.2.2.6
Offset 9h: CC – Class Code Register ................................................ 1219
34.2.2.7
Offset Ch: CLS – Cacheline Size Register .......................................... 1219
34.2.2.8
Offset Dh: LT – Latency Timer Register ............................................ 1220
34.2.2.9
Offset Eh: HDR – Header Type Register............................................ 1220
34.2.2.10 Offset 10h: CSRBAR0 – Control and Status Registers Base Address Register
1220
34.2.2.11 Offset 14h: CSRBAR1 – Control and Status Registers Base Address Register
1221
34.2.2.12 Offset 18h: PBNUM – Primary Bus Number Register ........................... 1221
34.2.2.13 Offset 19h: SECBNM – Secondary Bus Number Register ..................... 1221
34.2.2.14 Offset 1Ah: SUBBNM – Subordinate Bus Number Register................... 1222
34.2.2.15 Offset 1Bh: SECLT – Secondary Latency Timer Register...................... 1222
34.2.2.16 Offset 1Ch: IOB – I/O Base Register ................................................ 1222
34.2.2.17 Offset 1Dh: IOL – I/O Limit Register ................................................ 1223
34.2.2.18 Offset 1Eh: SECSTA – Secondary Status Register .............................. 1223
34.2.2.19 Offset 20h: MEMB – Memory Base Register....................................... 1224
34.2.2.20 Offset 22h: MEML – Memory Limit Register ....................................... 1224
34.2.2.21 Offset 24h: PMBASE – Prefetchable Memory Base Register.................. 1225
34.2.2.22 Offset 26h: PMLIMIT – Prefetchable Memory Limit Register ................. 1225
34.2.2.23 Offset 28h: PMBASU – Prefetchable Memory Base Upper Register ........ 1226
34.2.2.24 Offset 2Ch: PMLMTU – Prefetchable Memory Limit Upper Register ........ 1226
34.2.2.25 Offset 30h: IOBU – I/O Base Upper Register ..................................... 1227
34.2.2.26 Offset 32h: IOLU – I/O Limit Upper Register ..................................... 1227
34.2.2.27 Offset 34h: CP – Capabilities Pointer Register.................................... 1227
34.2.2.28 Offset 3Ch: IRQL – Interrupt Line Register........................................ 1228
34.2.2.29 Offset 3Dh: IRQP – Interrupt Pin Register......................................... 1228
34.2.2.30 Offset 3Eh: BCTL – Bridge Control Register....................................... 1228
34.2.2.31 Offset DCh: PCID – Power Management Capability ID Register ............ 1229
34.2.2.32 Offset DDh: PCP – Power Management Next Capability Pointer
Register ....................................................................................... 1230
34.2.2.33 Offset DEh: PMCAP – Power Management Capability Register .............. 1230
34.2.2.34 Offset E0h: PMCS – Power Management Control and Status
Register ....................................................................................... 1231
34.2.2.35 Offset E2h: PMCSE – Power Management Control and Status Extension
Register ....................................................................................... 1232
35.0 PCI-to-PCI Bridge: AIOC Configuration ............................................................... 1233
35.1 Overview ...................................................................................................... 1233
35.2 Feature List .................................................................................................. 1233
35.3 PCI Configuration Registers............................................................................. 1233
35.3.1
Description of PCI Configuration Header Space ......................................... 1233
35.4 Interrupt Handling for AIOC Devices................................................................. 1235
35.5 Power Management of AIOC Devices ................................................................ 1236
35.6 Gigabit Ethernet MAC Configuration Spaces: Bus M, Device 0-2, Function 0 ........... 1237
35.6.1
Register Details .................................................................................... 1237
35.6.1.1
Offset 00h: VID – Vendor Identification Register................................ 1240
35.6.1.2
Offset 02h: DID – Device Identification Register ................................ 1241
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August 2009
Order Number: 320066-003US
Contents
35.6.1.3
35.6.1.4
35.6.1.5
35.6.1.6
35.6.1.7
35.6.1.8
35.6.1.9
35.6.1.10
Offset 02h: DID – Device Identification Register ................................1242
Offset 02h: DID – Device Identification Register ................................1242
Offset 04h: PCICMD – Device Command Register ...............................1243
Offset 06h: PCISTS – Device Status Register .....................................1244
Offset 08h: RID – Revision ID Register .............................................1245
Offset 09h: CC – Class Code Register ...............................................1245
Offset 0Eh: HDR – Header Type Register...........................................1246
Offset 10h: CSRBAR – Control and Status Registers Base
Address Register............................................................................1246
35.6.1.11 Offset 14h: IOBAR – CSR I/O Mapped BAR Register............................1247
35.6.1.12 Offset 2Ch: SVID – Subsystem Vendor ID Register.............................1248
35.6.1.13 Offset 2Eh: SID – Subsystem ID Register..........................................1248
35.6.1.14 Offset 34h: CP – Capabilities Pointer Register ....................................1248
35.6.1.15 Offset 3Ch: IRQL – Interrupt Line Register ........................................1249
35.6.1.16 Offset 3Dh: IRQP – Interrupt Pin Register .........................................1250
35.6.1.17 Offset DCh: PCID – Power Management Capability ID Register.............1251
35.6.1.18 Offset DDh: PCP – Power Management Next Capability Pointer
Register .......................................................................................1251
35.6.1.19 Offset DEh: PMCAP – Power Management Capability Register...............1252
35.6.1.20 Offset E0h: PMCS – Power Management Control and Status
Register .......................................................................................1253
35.6.1.21 Offset E4h: SCID – Signal Target Capability ID Register ......................1254
35.6.1.22 Offset E5h: SCP – Signal Target Next Capability Pointer Register..........1254
35.6.1.23 Offset E6h: SBC – Signal Target Byte Count Register ..........................1255
35.6.1.24 Offset E7h: STYP – Signal Target Capability Type Register...................1255
35.6.1.25 Offset E8h: SMIA – Signal Target IA Mask Register.............................1256
35.6.1.26 Offset E9h: Reserved Register .........................................................1256
35.6.1.27 Offset EAh: Reserved Register .........................................................1256
35.6.1.28 Offset ECh: SINT – Signal Target Raw Interrupt Register.....................1257
35.6.1.29 Offset F0h: MCID – Message Signalled Interrupt Capability ID
Register .......................................................................................1258
35.6.1.30 Offset F1h: MCP – Message Signalled Interrupt Next Capability Pointer
Register .......................................................................................1258
35.6.1.31 Offset F2h: MCTL – Message Signalled Interrupt Control Register .........1259
35.6.1.32 Offset F4h: MADR – Message Signalled Interrupt Address
Register .......................................................................................1259
35.6.1.33 Offset F8h: MDATA – Message Signalled Interrupt Data Register ..........1260
35.7 Gigabit Ethernet MAC I/O Spaces: Bus M, Device 0-2, Function 0 .........................1261
35.7.1
Register Details ....................................................................................1262
35.7.1.1
Offset 0000h: IOADDR - IOADDR Register ........................................1262
35.7.1.2
Offset 0004h: IODATA - IODATA Register .........................................1264
35.8 GCU Configuration Space: Bus M, Device 3, Function 0........................................1265
35.8.1
Register Details ....................................................................................1265
35.8.1.1
Offset 00h: VID – Vendor Identification Register ................................1265
35.8.1.2
Offset 02h: DID – Device Identification Register ................................1266
35.8.1.3
Offset 04h: PCICMD – Device Command Register ...............................1266
35.8.1.4
Offset 06h: PCISTS – Device Status Register .....................................1267
35.8.1.5
Offset 08h: RID – Revision ID Register .............................................1267
35.8.1.6
Offset 09h: CC – Class Code Register ...............................................1268
35.8.1.7
Offset 0Eh: HDR – Header Type Register...........................................1268
35.8.1.8
Offset 10h: CSRBAR – Control and Status Registers Base
Address Register............................................................................1269
35.8.1.9
Offset 2Ch: SVID – Subsystem Vendor ID Register.............................1269
35.8.1.10 Offset 2Eh: SID – Subsystem ID Register..........................................1270
35.8.1.11 Offset 34h: CP – Capabilities Pointer Register ....................................1270
35.8.1.12 Offset DCh: PCID – Power Management Capability ID Register.............1270
35.8.1.13 Offset DDh: PCP – Power Management Next Capability Pointer
Register .......................................................................................1271
35.8.1.14 Offset DEh: PMCAP – Power Management Capability Register...............1271
August 2009
Order Number: 320066-003US
Intel® EP80579 Integrated Processor Product Line Datasheet
35
Contents
35.8.1.15
Offset E0h: PMCS – Power Management Control and Status
Register ....................................................................................... 1272
35.9 CAN Controller Configuration Spaces: Bus M, Device 4-5, Function 0 .................... 1273
35.9.1
Register Details .................................................................................... 1273
35.9.1.1
Offset 00h: VID – Vendor Identification Register................................ 1275
35.9.1.2
Offset 02h: DID – Device Identification Register ................................ 1275
35.9.1.3
Offset 02h: DID – Device Identification Register ................................ 1276
35.9.1.4
Offset 04h: PCICMD – Device Command Register .............................. 1276
35.9.1.5
Offset 06h: PCISTS – Device Status Register .................................... 1277
35.9.1.6
Offset 08h: RID – Revision ID Register............................................. 1278
35.9.1.7
Offset 09h: CC – Class Code Register............................................... 1278
35.9.1.8
Offset 0Eh: HDR – Header Type Register .......................................... 1279
35.9.1.9
Offset 10h: CSRBAR – Control and Status Registers Base
Address Register ........................................................................... 1279
35.9.1.10 Offset 2Ch: SVID – Subsystem Vendor ID Register ............................ 1280
35.9.1.11 Offset 2Eh: SID – Subsystem ID Register ......................................... 1280
35.9.1.12 Offset 34h: CP – Capabilities Pointer Register.................................... 1281
35.9.1.13 Offset 3Ch: IRQL – Interrupt Line Register........................................ 1281
35.9.1.14 Offset 3Dh: IRQP – Interrupt Pin Register......................................... 1282
35.9.1.15 Offset 40h: CANCTL – CAN Control Register ...................................... 1282
35.9.1.16 Offset DCh: PCID – Power Management Capability ID Register ............ 1283
35.9.1.17 Offset DDh: PCP – Power Management Next Capability Pointer
Register ....................................................................................... 1283
35.9.1.18 Offset DEh: PMCAP – Power Management Capability Register .............. 1284
35.9.1.19 Offset E0h: PMCS – Power Management Control and Status
Register ....................................................................................... 1284
35.9.1.20 Offset E4h: SCID – Signal Target Capability ID Register ..................... 1285
35.9.1.21 Offset E5h: SCP – Signal Target Next Capability Pointer Register ......... 1285
35.9.1.22 Offset E6h: SBC – Signal Target Byte Count Register ......................... 1286
35.9.1.23 Offset E7h: STYP – Signal Target Capability Type Register .................. 1286
35.9.1.24 Offset E8h: SMIA – Signal Target IA Mask Register ............................ 1287
35.9.1.25 Offset E9h: Reserved Register......................................................... 1287
35.9.1.26 Offset EAh: Reserved Register ........................................................ 1287
35.9.1.27 Offset ECh: SINT – Signal Target Raw Interrupt Register .................... 1287
35.9.1.28 Offset F0h: MCID – Message Signalled Interrupt Capability ID
Register ....................................................................................... 1288
35.9.1.29 Offset F1h: MCP – Message Signalled Interrupt Next Capability Pointer
Register ....................................................................................... 1288
35.9.1.30 Offset F2h: MCTL – Message Signalled Interrupt Control Register......... 1289
35.9.1.31 Offset F4h: MADR – Message Signalled Interrupt Address
Register ....................................................................................... 1289
35.9.1.32 Offset F8h: MDATA – Message Signalled Interrupt Data Register.......... 1290
35.10 SSP Controller Configuration Space: Bus M, Device 6, Function 0 ........................ 1291
35.10.1 Register Details .................................................................................... 1291
35.10.1.1 Offset 00h: VID – Vendor Identification Register................................ 1292
35.10.1.2 Offset 02h: DID – Device Identification Register ................................ 1292
35.10.1.3 Offset 04h: PCICMD – Device Command Register .............................. 1292
35.10.1.4 Offset 06h: PCISTS – Device Status Register .................................... 1293
35.10.1.5 Offset 08h: RID – Revision ID Register............................................. 1294
35.10.1.6 Offset 09h: CC – Class Code Register............................................... 1295
35.10.1.7 Offset 0Eh: HDR – Header Type Register .......................................... 1295
35.10.1.8 Offset 10h: CSRBAR – Control and Status Registers Base
Address Register ........................................................................... 1295
35.10.1.9 Offset 2Ch: SVID – Subsystem Vendor ID Register ............................ 1296
35.10.1.10 Offset 2Eh: SID – Subsystem ID Register ......................................... 1296
35.10.1.11 Offset 34h: CP – Capabilities Pointer Register.................................... 1297
35.10.1.12 Offset 3Ch: IRQL – Interrupt Line Register........................................ 1297
35.10.1.13 Offset 3Dh: IRQP – Interrupt Pin Register......................................... 1298
35.10.1.14 Offset DCh: PCID – Power Management Capability ID Register ............ 1298
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August 2009
Order Number: 320066-003US
Contents
35.10.1.15 Offset DDh: PCP – Power Management Next Capability Pointer
Register .......................................................................................1299
35.10.1.16 Offset DEh: PMCAP - Power Management Capability ...........................1299
35.10.1.17 Offset E0h: PMCS – Power Management Control and Status
Register .......................................................................................1300
35.10.1.18 Offset E4h: SCID – Signal Target Capability ID Register ......................1300
35.10.1.19 Offset E5h: SCP – Signal Target Next Capability Pointer Register..........1301
35.10.1.20 Offset E6h: SBC – Signal Target Byte Count Register ..........................1301
35.10.1.21 Offset E7h: STYP – Signal Target Capability Type Register...................1301
35.10.1.22 Offset E8h: SMIA – Signal Target IA Mask Register.............................1302
35.10.1.23 Offset E9h: Reserved Register .........................................................1302
35.10.1.24 Offset EAh: Reserved Register .........................................................1302
35.10.1.25 Offset ECh: SINT – Signal Target Raw Interrupt Register.....................1302
35.10.1.26 Offset F0h: MCID – Message Signalled Interrupt Capability ID
Register .......................................................................................1302
35.10.1.27 Offset F1h: MCP – Message Signalled Interrupt Next Capability Pointer
Register .......................................................................................1303
35.10.1.28 Offset F2h: MCTL – Message Signalled Interrupt Control
Register .......................................................................................1303
35.10.1.29 Offset F4h: MADR – Message Signalled Interrupt Address
Register .......................................................................................1304
35.10.1.30 Offset F8h: MDATA – Message Signalled Interrupt Data Register ..........1304
35.11 IEEE 1588 Hardware Assist Unit Configuration Space: Bus M, Device 7, Function 0 1305
35.11.1 Register Details ....................................................................................1305
35.11.1.1 Offset 00h: VID – Vendor Identification Register ................................1306
35.11.1.2 Offset 02h: DID – Device Identification Register ................................1306
35.11.1.3 Offset 04h: PCICMD – Device Command Register ...............................1306
35.11.1.4 Offset 06h: PCISTS – Device Status Register .....................................1307
35.11.1.5 Offset 08h: RID – Revision ID Register .............................................1308
35.11.1.6 Offset 09h: CC – Class Code Register ...............................................1308
35.11.1.7 Offset 0Eh: HDR – Header Type Register ..........................................1309
35.11.1.8 Offset 10h: CSRBAR – Control and Status Registers Base
Address Register............................................................................1309
35.11.1.9 Offset 2Ch: SVID – Subsystem Vendor ID Register.............................1310
35.11.1.10 Offset 2Eh: SID – Subsystem ID Register..........................................1310
35.11.1.11 Offset 34h: CP – Capabilities Pointer Register ....................................1310
35.11.1.12 Offset 3Ch: IRQL – Interrupt Line Register ........................................1311
35.11.1.13 Offset 3Dh: IRQP – Interrupt Pin Register .........................................1311
35.11.1.14 Offset DCh: PCID – Power Management Capability ID Register.............1312
35.11.1.15 Offset DDh: PCP – Power Management Next Capability Pointer
Register .......................................................................................1312
35.11.1.16 Offset DEh: PMCAP – Power Management Capability Register...............1313
35.11.1.17 Offset E0h: PMCS – Power Management Control and Status
Register .......................................................................................1313
35.11.1.18 Offset E4h: SCID – Signal Target Capability ID Register ......................1314
35.11.1.19 Offset E5h: SCP – Signal Target Next Capability Pointer Register..........1314
35.11.1.20 Offset E6h: SBC – Signal Target Byte Count Register ..........................1314
35.11.1.21 Offset E7h: STYP – Signal Target Capability Type Register...................1315
35.11.1.22 Offset E8h: SMIA – Signal Target IA Mask Register.............................1315
35.11.1.23 Offset E9h: Reserved Register .........................................................1315
35.11.1.24 Offset EAh: Reserved Register .........................................................1315
35.11.1.25 Offset ECh: SINT – Signal Target Raw Interrupt Register.....................1316
35.11.1.26 Offset F0h: MCID – Message Signalled Interrupt Capability ID
Register .......................................................................................1316
35.11.1.27 Offset F1h: MCP – Message Signalled Interrupt Next Capability Pointer
Register .......................................................................................1317
35.11.1.28 Offset F2h: MCTL – Message Signalled Interrupt Control
Register .......................................................................................1317
35.11.1.29 Offset F4h: MADR – Message Signalled Interrupt Address
Register .......................................................................................1318
August 2009
Order Number: 320066-003US
Intel® EP80579 Integrated Processor Product Line Datasheet
37
Contents
35.11.1.30 Offset F8h: MDATA – Message Signalled Interrupt Data Register.......... 1318
35.12 Expansion Bus Configuration Space: Bus M, Device 8, Function 0 ........................ 1319
35.12.1 Register Details .................................................................................... 1319
35.12.1.1 Offset 00h: VID – Vendor Identification Register................................ 1320
35.12.1.2 Offset 02h: DID – Device Identification Register ................................ 1320
35.12.1.3 Offset 04h: PCICMD – Device Command Register .............................. 1321
35.12.1.4 Offset 06h: PCISTS – Device Status Register .................................... 1321
35.12.1.5 Offset 08h: RID – Revision ID Register............................................. 1322
35.12.1.6 Offset 09h: CC – Class Code Register............................................... 1323
35.12.1.7 Offset 0Eh: HDR – Header Type Register .......................................... 1323
35.12.1.8 Offset 10h: CSRBAR – Control and Status Registers Base
Address Register ........................................................................... 1323
35.12.1.9 Offset 14h: MMBAR – Expansion Bus Base Address Register................ 1324
35.12.1.10 Offset 2Ch: SVID – Subsystem Vendor ID Register ............................ 1325
35.12.1.11 Offset 2Eh: SID – Subsystem ID Register ......................................... 1325
35.12.1.12 Offset 34h: CP – Capabilities Pointer Register.................................... 1326
35.12.1.13 Offset 3Ch: IRQL – Interrupt Line Register........................................ 1326
35.12.1.14 Offset 3Dh: IRQP – Interrupt Pin Register......................................... 1327
35.12.1.15 Offset 40h: LEBCTL – LEB Control Register ....................................... 1327
35.12.1.16 Offset DCh: PCID – Power Management Capability ID Register ............ 1327
35.12.1.17 Offset DDh: PCP – Power Management Next Capability Pointer
Register ....................................................................................... 1328
35.12.1.18 Offset DEh: PMCAP – Power Management Capability Register .............. 1328
35.12.1.19 Offset E0h: PMCS – Power Management Control and Status
Register ....................................................................................... 1329
35.12.1.20 Offset E4h: SCID – Signal Target Capability ID Register ..................... 1329
35.12.1.21 Offset E5h: SCP – Signal Target Next Capability Pointer Register ......... 1330
35.12.1.22 Offset E6h: SBC – Signal Target Byte Count Register ......................... 1330
35.12.1.23 Offset E7h: STYP – Signal Target Capability Type Register .................. 1330
35.12.1.24 Offset E8h: SMIA – Signal Target IA Mask Register ............................ 1331
35.12.1.25 Offset E9h: Reserved Register......................................................... 1331
35.12.1.26 Offset EAh: Reserved Register ........................................................ 1331
35.12.1.27 Offset ECh: SINT – Signal Target Raw Interrupt Register .................... 1331
35.12.1.28 Offset F0h: MCID – Message Signalled Interrupt Capability ID
Register ....................................................................................... 1332
35.12.1.29 Offset F1h: MCP – Message Signalled Interrupt Next Capability Pointer
Register ....................................................................................... 1332
35.12.1.30 Offset F2h: MCTL – Message Signalled Interrupt Control
Register ....................................................................................... 1333
35.12.1.31 Offset F4h: MADR – Message Signalled Interrupt Address
Register ....................................................................................... 1333
35.12.1.32 Offset F8h: MDATA – Message Signalled Interrupt Data Register.......... 1334
36.0 AIOC Interfaces ................................................................................................... 1335
36.1 Overview ...................................................................................................... 1335
36.2 Gigabit Ethernet (GbE) ................................................................................... 1335
36.2.1
Integrated DMA Features ....................................................................... 1336
36.2.2
MAC Features....................................................................................... 1336
36.2.3
Host Off-Loading Features ..................................................................... 1337
36.2.4
Interfaces............................................................................................ 1337
36.2.5
Power Management .............................................................................. 1337
36.2.6
Serial EEPROM Interface ........................................................................ 1338
36.3 Local Expansion Bus Interface (LEB)................................................................. 1338
36.4 Serial Synchronous Port (SSP)......................................................................... 1339
36.5 Controller Area Network (CAN) ........................................................................ 1339
36.6 IEEE 1588 Time Synchronization Hardware Assist ............................................. 1340
37.0 Gigabit Ethernet Controller .................................................................................. 1341
37.1 Overview ...................................................................................................... 1341
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August 2009
Order Number: 320066-003US
Contents
37.1.1
Terminology and Conventions .................................................................1341
37.1.1.1
Register and Bit References.............................................................1341
37.1.1.2
Byte and Bit Designations ...............................................................1341
37.1.1.3
Numbering....................................................................................1341
37.1.1.4
Memory Alignment Terminology.......................................................1342
37.1.1.5
Alignment and Byte Ordering...........................................................1342
37.1.1.6
Packet Buffer ................................................................................1342
37.1.2
Wake On LAN .......................................................................................1343
37.2 Feature List ...................................................................................................1343
37.3 Functional Block Diagram ................................................................................1344
37.4 Usage Model ..................................................................................................1345
37.4.1
Protocol Translation ...............................................................................1346
37.4.2
Power Management ...............................................................................1346
37.4.3
Software Initialization and Diagnostics .....................................................1346
37.4.3.1
Power Up State .............................................................................1346
37.4.3.2
Memory Initialization ......................................................................1347
37.4.3.3
General Configuration.....................................................................1348
37.4.3.4
Link Setup Mechanisms and Control/Status Bit Summary ....................1348
37.4.3.5
Receive Initialization ......................................................................1348
37.4.3.6
Transmit Initialization.....................................................................1349
37.4.3.7
Initialization of Statistics.................................................................1350
37.4.3.8
GbE Line Rate Configuration Change ................................................1350
37.4.3.9
Network Boot ................................................................................1350
37.4.3.10 Diagnostics ...................................................................................1351
37.5 Functional Description.....................................................................................1351
37.5.1
Ethernet Addressing ..............................................................................1351
37.5.2
Interrupt Control & Tuning .....................................................................1352
37.5.2.1
Interrupt Cause Set/Read Registers..................................................1353
37.5.2.2
Interrupt Mask Set (Read)/Clear Registers ........................................1353
37.5.2.3
Interrupt Throttling Register............................................................1353
37.5.3
Hardware Acceleration Capability ............................................................1353
37.5.3.1
Checksum Off-Loading....................................................................1353
37.5.3.2
TCP Segmentation .........................................................................1354
37.5.4
Buffer and Descriptor Structure...............................................................1354
37.5.5
Packet Reception...................................................................................1354
37.5.5.1
Packet Address Filtering..................................................................1354
37.5.5.2
Receive Data Storage .....................................................................1355
37.5.5.3
Receive Descriptor Format ..............................................................1355
37.5.5.4
Receive Descriptor Fetching ............................................................1358
37.5.5.5
Receive Descriptor Write-Back .........................................................1358
37.5.5.6
Receive Descriptor Queue Structure .................................................1359
37.5.5.7
Receive Interrupts .........................................................................1360
37.5.5.8
Receive Packet Checksum Off loading ...............................................1363
37.5.6
Packet Transmission ..............................................................................1365
37.5.6.1
Transmit Data Storage ...................................................................1365
37.5.6.2
Transmit Descriptor Formats ...........................................................1365
37.5.6.3
Legacy Transmit Descriptor Format ..................................................1366
37.5.6.4
TCP/IP Context Transmit Descriptor Format.......................................1369
37.5.6.5
TCP/IP Data Descriptor Format ........................................................1373
37.5.6.6
Transmit Descriptor Structure..........................................................1375
37.5.6.7
Transmit Descriptor Fetching ...........................................................1377
37.5.6.8
Transmit Descriptor Write-back .......................................................1377
37.5.6.9
Transmit Interrupts........................................................................1378
37.5.6.10 Transmit Checksum Off loading .......................................................1379
37.5.7
TCP Segmentation.................................................................................1380
37.5.7.1
Assumptions .................................................................................1381
37.5.7.2
Transmission Process .....................................................................1381
37.5.7.3
TCP Segmentation Performance .......................................................1382
August 2009
Order Number: 320066-003US
Intel® EP80579 Integrated Processor Product Line Datasheet
39
Contents
37.5.7.4
Packet Format .............................................................................. 1382
37.5.7.5
TCP Segmentation Indication .......................................................... 1383
37.5.7.6
TCP Segmentation Data Descriptors................................................. 1383
37.5.7.7
IP and TCP/UDP Headers ................................................................ 1384
37.5.7.8
Transmit Checksum Off loading with TCP Segmentation...................... 1388
37.5.7.9
IP/TCP/UDP Header Updating.......................................................... 1389
37.5.7.10 Data Flow..................................................................................... 1391
37.5.8
Ethernet Interfaces ............................................................................... 1391
37.5.8.1
MAC/PHY GMII/MII Interface .......................................................... 1392
37.5.8.2
Duplex Operation .......................................................................... 1393
37.5.8.3
Physical Layer Auto-Negotiation & Link Setup Features....................... 1394
37.5.8.4
10/100Mbps Specific Performance Enhancements .............................. 1396
37.5.8.5
Flow Control ................................................................................. 1397
37.5.9
802.1q VLAN Support............................................................................ 1400
37.5.9.1
Transmitting and Receiving 802.1q Packets ...................................... 1401
37.5.9.2
802.1q VLAN Packet Filtering .......................................................... 1401
37.5.10 Wake on LAN ....................................................................................... 1402
37.5.10.1 Advanced Power Management Wakeup............................................. 1402
37.5.10.2 ACPI Power Management Wakeup ................................................... 1403
37.5.10.3 Wake-up Packets: Pre-defined Filters ............................................... 1404
37.5.10.4 Wake-up Packets: Flexible Filters .................................................... 1409
37.5.11 Serial EEPROM ..................................................................................... 1412
37.5.11.1 EEPROM Device............................................................................. 1412
37.5.11.2 Software Accesses......................................................................... 1412
37.5.11.3 Signature Field ............................................................................. 1413
37.5.11.4 EEPROM Map ................................................................................ 1413
37.5.11.5 Hardware Accessed Words.............................................................. 1415
37.5.11.6 Software Accessed Words............................................................... 1417
37.5.12 Error Handling...................................................................................... 1418
37.5.12.1 CSR (Target) Accesses ................................................................... 1418
37.5.12.2 DMA Host (Master) Accesses........................................................... 1418
37.5.12.3 Internal Memories ......................................................................... 1419
37.5.13 Reset Operation ................................................................................... 1420
37.5.13.1 Soft Reset .................................................................................... 1422
37.5.13.2 MAC Disable ................................................................................. 1422
37.5.14 Endianness .......................................................................................... 1422
37.6 GbE Controller Register Summary .................................................................... 1425
37.6.1
Registers Overview ............................................................................... 1425
37.6.1.1
Memory-Mapped Access to Internal Registers and Memories ............... 1436
37.6.1.2
I/O-Mapped Access to Internal Registers and Memories ...................... 1436
37.6.1.3
Register Conventions ..................................................................... 1437
37.6.2
General Registers: Detailed Descriptions.................................................. 1438
37.6.2.1
CTRL – Device Control Register ....................................................... 1438
37.6.2.2
STATUS – Device Status Register .................................................... 1441
37.6.2.3
CTRL_EXT – Extended Device Control Register .................................. 1442
37.6.2.4
CTRL_AUX – Auxiliary Device Control/Status Register ........................ 1444
37.6.2.5
EEPROM_CTRL – EEPROM Control Register ....................................... 1446
37.6.2.6
EEPROM_RR – EEPROM Read Register .............................................. 1448
37.6.2.7
FCAL – Flow Control Address Low Register ........................................ 1449
37.6.2.8
FCAH – Flow Control Address High Register ...................................... 1450
37.6.2.9
FCT – Flow Control Type Register .................................................... 1451
37.6.2.10 VET – VLAN EtherType Register....................................................... 1452
37.6.2.11 FCTTV – Flow Control Transmit Timer Value Register.......................... 1452
37.6.2.12 PBA – Packet Buffer Allocation Register ............................................ 1453
37.6.3
Interrupt Registers: Detailed Descriptions ................................................ 1454
37.6.3.1
ICR0 – Interrupt 0 Cause Read Register ........................................... 1454
37.6.3.2
ITR0 – Interrupt 0 Throttling Register .............................................. 1457
37.6.3.3
ICS0 – Interrupt 0 Cause Set Register ............................................ 1458
Intel® EP80579 Integrated Processor Product Line Datasheet
40
August 2009
Order Number: 320066-003US
Contents
37.6.3.4
IMS0 – Interrupt 0 Mask Set/Read Register .......................................1459
37.6.3.5
IMC0 – Interrupt 0 Mask Clear Register ...........................................1460
37.6.3.6
ICR1 – Interrupt 1 Cause Read Register............................................1462
37.6.3.7
ICS1 – Interrupt 1 Cause Set Register .............................................1464
37.6.3.8
IMS1 – Interrupt 1 Mask Set/Read Register .......................................1466
37.6.3.9
IMC1 – Interrupt 1 Mask Clear Register ...........................................1467
37.6.3.10 ICR2 – Error Interrupt Cause Read Register ......................................1469
37.6.3.11 ICS2 – Error Interrupt Cause Set Register ........................................1471
37.6.3.12 IMS2 – Error Interrupt Mask Set/Read Register..................................1472
37.6.3.13 IMC2 – Error Interrupt Mask Clear Register ......................................1473
37.6.4
Receive Registers: Detailed Descriptions ..................................................1474
37.6.4.1
RCTL – Receive Control Register ......................................................1474
37.6.4.2
FCRTL: Flow Control Receive Threshold Low Register .........................1478
37.6.4.3
FCRTH – Flow Control Receive Threshold High Register ......................1479
37.6.4.4
RDBAL – Receive Descriptor Base Address Low Register ......................1480
37.6.4.5
RDBAH – Receive Descriptor Base Address High Register ...................1480
37.6.4.6
RDLEN – Receive Descriptor Length Register ....................................1481
37.6.4.7
RDH – Receive Descriptor Head Register ..........................................1481
37.6.4.8
RDT – Receive Descriptor Tail Register .............................................1482
37.6.4.9
RDTR – RX Interrupt Delay Timer (Packet Timer) Register ..................1482
37.6.4.10 RXDCTL – Receive Descriptor Control Register ..................................1483
37.6.4.11 RADV – Receive Interrupt Absolute Delay Timer Register ...................1485
37.6.4.12 RSRPD – Receive Small Packet Detect Interrupt Register.....................1486
37.6.4.13 RXCSUM – Receive Checksum Control Register ..................................1487
37.6.4.14 MTA[0-127] – 128 Multicast Table Array Registers .............................1488
37.6.4.15 RAL[0-15] – Receive Address Low Register........................................1488
37.6.4.16 RAH[0-15] – Receive Address High Register ......................................1489
37.6.4.17 VFTA[0-127] – 128 VLAN Filter Table Array Registers .........................1490
37.6.5
Transmit Registers: Detailed Descriptions .................................................1491
37.6.5.1
TCTL – Transmit Control Register .....................................................1491
37.6.5.2
TIPG – Transmit IPG Register .........................................................1493
37.6.5.3
AIT – Adaptive IFS Throttle Register.................................................1495
37.6.5.4
TDBAL – Transmit Descriptor Base Address Low Register ....................1496
37.6.5.5
TDBAH – Transmit Descriptor Base Address High Register ...................1496
37.6.5.6
TDLEN – Transmit Descriptor Length Register ...................................1497
37.6.5.7
TDH – Transmit Descriptor Head Register..........................................1497
37.6.5.8
TDT – Transmit Descriptor Tail Register ............................................1498
37.6.5.9
TIDV – Transmit Interrupt Delay Value Register .................................1499
37.6.5.10 TXDCTL – Transmit Descriptor Control Register .................................1500
37.6.5.11 TADV – Transmit Absolute Interrupt Delay Value Register ...................1502
37.6.5.12 TSPMT – TCP Segmentation Pad and Minimum Threshold Register ........1503
37.6.6
Statistical Registers: Detailed Descriptions ...............................................1505
37.6.6.1
CRCERRS – CRC Error Count Register ...............................................1505
37.6.6.2
ALGNERRC – Alignment Error Count Register .....................................1506
37.6.6.3
RXERRC – Receive Error Count Register ............................................1506
37.6.6.4
MPC – Missed Packet Count Register ................................................1507
37.6.6.5
SCC – Single Collision Count Register ...............................................1507
37.6.6.6
ECOL – Excessive Collisions Count Register .......................................1508
37.6.6.7
MCC – Multiple Collision Count Register ............................................1508
37.6.6.8
LATECOL – Late Collisions Count Register..........................................1509
37.6.6.9
COLC – Collision Count Register.......................................................1509
37.6.6.10 DC – Defer Count Register ..............................................................1510
37.6.6.11 TNCRS – Transmit with No CRS Count Register ..................................1510
37.6.6.12 CEXTERR – Carrier Extension Error Count Register .............................1511
37.6.6.13 RLEC – Receive Length Error Count Register......................................1511
37.6.6.14 XONRXC – XON Received Count Register ..........................................1512
37.6.6.15 XONTXC – XON Transmitted Count Register ......................................1512
37.6.6.16 XOFFRXC – XOFF Received Count Register ........................................1513
37.6.6.17 XOFFTXC – XOFF Transmitted Count Register ....................................1513
August 2009
Order Number: 320066-003US
Intel® EP80579 Integrated Processor Product Line Datasheet
41
Contents
37.6.6.18
37.6.6.19
37.6.6.20
37.6.6.21
FCRUC – FC Received Unsupported Count Register ............................ 1514
PRC64 – Good Packets Received Count (64 Bytes) Register................. 1514
PRC127 – Good Packets Received Count (65-127 Bytes) Register ........ 1515
PRC255 – Good Packets Received Count (128-255 Bytes)
Register ....................................................................................... 1515
37.6.6.22 PRC511 – Good Packets Received Count (256-511 Bytes)
Register ....................................................................................... 1516
37.6.6.23 PRC1023 – Good Packets Received Count (512-1023 Bytes)
Register ...................................................................................... 1516
37.6.6.24 PRC1522 – Good Packets Received Count (1024 to Max Bytes)
Register ...................................................................................... 1517
37.6.6.25 GPRC – Good Packets Received Count (Total) Register ....................... 1518
37.6.6.26 BPRC – Broadcast Packets Received Count Register ........................... 1518
37.6.6.27 MPRC – Multicast Packets Received Count Register ........................... 1519
37.6.6.28 GPTC – Good Packets Transmitted Count Register.............................. 1519
37.6.6.29 GORCL – Good Octets Received Count Low Register ........................... 1520
37.6.6.30 GORCH – Good Octets Received Count High Register ......................... 1521
37.6.6.31 GOTCL – Good Octets Transmitted Count Low Register....................... 1521
37.6.6.32 GOTCH – Good Octets Transmitted Count High Register ..................... 1522
37.6.6.33 RNBC – Receive No Buffers Count Register ....................................... 1523
37.6.6.34 RUC – Receive Undersize Count Register ......................................... 1523
37.6.6.35 RFC – Receive Fragment Count Register ........................................... 1524
37.6.6.36 ROC – Receive Oversize Count Register............................................ 1524
37.6.6.37 RJC – Receive Jabber Count Register ............................................... 1525
37.6.6.38 TORL – Total Octets Received Low Register....................................... 1525
37.6.6.39 TORH – Total Octets Received High Register ..................................... 1526
37.6.6.40 TOTL – Total Octets Transmitted Low Register................................... 1527
37.6.6.41 TOTH – Total Octets Transmitted High Register ................................. 1527
37.6.6.42 TPR – Total Packets Received Register ............................................. 1528
37.6.6.43 TPT – Total Packets Transmitted Register ......................................... 1529
37.6.6.44 PTC64 – Packets Transmitted Count (64 Bytes) Register..................... 1529
37.6.6.45 PTC127 – Packets Transmitted Count (65-127 Bytes) Register ............ 1530
37.6.6.46 PTC255 – Packets Transmitted Count (128-255 Bytes) Register........... 1530
37.6.6.47 PTC511 – Packets Transmitted Count (256-511 Bytes) Register........... 1530
37.6.6.48 PTC1023 – Packets Transmitted Count (512-1023 Bytes) Register ....... 1531
37.6.6.49 PTC1522: Packets Transmitted Count (1024-1522 Bytes) Register ....... 1531
37.6.6.50 MPTC – Multicast Packets Transmitted Count Register ........................ 1532
37.6.6.51 BPTC – Broadcast Packets Transmitted Count Register ....................... 1532
37.6.6.52 TSCTC – TCP Segmentation Context Transmitted Count Register ......... 1533
37.6.6.53 TSCTFC – TCP Segmentation Context Transmit Fail Count
Register ...................................................................................... 1533
37.6.7
Management Register Descriptions.......................................................... 1534
37.6.7.1
WUC – Wake Up Control Register (0x05800; RW) .............................. 1534
37.6.7.2
WUFC – Wake Up Filter Control Register (0x05808; RW) .................... 1535
37.6.7.3
WUS – Wake Up Status Register (0x05810; RW) ............................... 1536
37.6.7.4
IPAV – IP Address Valid Register (0x05838; RW) ............................... 1537
37.6.7.5
IP4AT[0-3] - (0x5840 - 0x5858; RW) – IPv4 Address Table
Registers ..................................................................................... 1538
37.6.7.6
IPV6_ADDR0BYTES_1_4 – IPv6 Address Table Register (0x5880),
Bytes 1 - 4 .................................................................................. 1538
37.6.7.7
IPV6_ADDR0BYTES_5_8 – IPv6 Address Table Register,
Bytes 5 - 8 .................................................................................. 1539
37.6.7.8
IPV6_ADDR0BYTES_9_12 – IPv6 Address Table Register,
Bytes 9 - 12 ................................................................................. 1540
37.6.7.9
IPV6_ADDR0BYTES_13_16 – IPv6 Address Table Register,
Bytes 13 - 16 ............................................................................... 1540
37.6.7.10 FFLT[0-3] – Flexible Filter Length Table Registers
(0x5F00 - 0x5F18; RW) ................................................................. 1541
37.6.7.11 FFMT[0-127] – Flexible Filter Mask Table Registers
(0x9000 - 0x93F8; RW) ................................................................. 1542
Intel® EP80579 Integrated Processor Product Line Datasheet
42
August 2009
Order Number: 320066-003US
Contents
37.6.7.12 FFVT[0-127] – Flexible Filter Value Table Registers ............................1543
37.6.8
Error Register Descriptions .....................................................................1544
37.6.8.1
INTBUS_ERR_STAT – Internal Bus Error Status Register .....................1544
37.6.8.2
MEM_TST – Memory Error Test Register............................................1545
37.6.8.3
MEM_STS – Memory Error Status Register ........................................1546
37.7 Power Management ........................................................................................1549
37.7.1
Assumptions.........................................................................................1549
37.7.2
D3cold support .....................................................................................1549
37.7.3
Power States ........................................................................................1550
37.7.3.1
Dr................................................................................................1550
37.7.3.2
D0u State .....................................................................................1551
37.7.3.3
D0a .............................................................................................1551
37.7.3.4
D3 ...............................................................................................1551
37.7.4
Timing of Power-State Transitions ...........................................................1551
37.7.4.1
Power up (off to Dr to D0u to D0a) ..................................................1552
37.7.4.2
Transition from D0a to D3 and Back without Reset .............................1554
37.7.4.3
Transition from D0a to D3 and Back with Reset..................................1555
37.7.4.4
Reset without Transition to D3.........................................................1556
37.7.4.5
Timing Requirements .....................................................................1556
37.7.4.6
Timing Guarantees.........................................................................1557
37.7.5
Power Management Extended Capabilities Registers...................................1557
38.0 Global Configuration Unit ....................................................................................1559
38.1 Overview ......................................................................................................1559
38.2 Feature List ...................................................................................................1559
38.3 Usage Model ..................................................................................................1559
38.3.1
RCOMP ...............................................................................................1559
38.3.1.1
GbE ............................................................................................1560
38.3.1.2
LEB..............................................................................................1560
38.4 Register Summary..........................................................................................1561
38.4.1
Detailed Register Descriptions.................................................................1562
38.4.1.1
Offset 0x00000010h: MDIO_STATUS - MDIO Status Register...............1562
38.4.1.2
Offset 0x00000014h: MDIO_COMMAND - MDIO Command
Register .......................................................................................1562
38.4.1.3
Offset 0x00000018h: MDIO_DRIVE - MDIO Drive Register ..................1563
38.4.1.4
Offset 0x00000020h: MDC_DRIVE - MDC Drive Register ....................1563
38.4.1.5
Offset 0x00000024h: GCU_GBE_RC_CTRL - GCU GbE RCOMP
Control Register.............................................................................1564
38.4.1.6
Offset 0x00000044h: GCU_GBE_RC_STAT - GCU GbE RCOMP
Status Register .............................................................................1564
38.4.1.7
Offset 0x00000050h: GCU_LEB_RC_STAT - GCU Local
Expansion Bus RCOMP Status Register .............................................1565
38.4.1.8
Offset 0x00000054h: GCU_LEB_RC_CTRL - GCU Local
Expansion Bus RCOMP Control Register.............................................1566
38.4.1.9
Offset 0x00000060h: SSP_DRIVE - SSP Drive Register ......................1566
38.4.1.10 Offset 0x00000064h: TDM_DRIVE_3 - TDM Drive Register for
TDM Port 3 ..................................................................................1567
38.4.1.11 Offset 0x00000068h: TDM_DRIVE_12 - TDM Drive Register
for TDM Ports 1 & 2........................................................................1567
38.4.1.12 Offset 0x00000028h: CAN_DRIVE - CAN Drive Register .....................1568
39.0 Controller Area Network - CAN .............................................................................1569
39.1 Overview ......................................................................................................1569
39.2 Feature List ...................................................................................................1569
39.3 Functional Block Diagram ................................................................................1570
39.4 Usage Model ..................................................................................................1571
39.4.1
CAN Basics...........................................................................................1571
39.4.2
Addressing and Bus Arbitration ...............................................................1571
August 2009
Order Number: 320066-003US
Intel® EP80579 Integrated Processor Product Line Datasheet
43
Contents
39.4.3
Frame Types ........................................................................................ 1572
39.4.3.1
Data Frame .................................................................................. 1572
39.4.3.2
Remote Frame .............................................................................. 1575
39.4.3.3
Error Frames ................................................................................ 1576
39.4.3.4
Overload Frames........................................................................... 1577
39.4.4
CAN Bit Timing..................................................................................... 1577
39.4.4.1
Introduction ................................................................................. 1577
39.4.4.2
Setting Proper Bit Rate, tseg1 and tseg2 .......................................... 1579
39.5 Theory of Operation ....................................................................................... 1580
39.5.1
Modes of Operation............................................................................... 1580
39.5.2
Error Handling...................................................................................... 1580
39.5.3
Send/Receive Procedure ........................................................................ 1581
39.5.3.1
Send Procedure ............................................................................ 1581
39.5.3.2
Receive Procedures ....................................................................... 1581
39.5.3.3
Rx Message Processing .................................................................. 1582
39.5.3.4
Acceptance Filter........................................................................... 1582
39.5.3.5
RTR Auto-Reply............................................................................. 1583
39.5.3.6
RxBuffer Linking............................................................................ 1583
39.5.4
TxMessage Registers............................................................................. 1584
39.6 Register Summary ......................................................................................... 1585
39.6.1
Detailed Register Descriptions ................................................................ 1587
39.6.1.1
Offset 00000000h: Int_status - Interrupt Status Register .................. 1587
39.6.1.2
Offset 00000004h: Int_Ebl - Interrupt Enable Register ...................... 1588
39.6.1.3
Offset 00000008h: Buffer Status - Buffer Status Indicators................. 1589
39.6.1.4
Offset 0000000Ch: ErrorStatus - Error Status Indicators .................... 1590
39.6.1.5
Offset 00000010h: Command - Operating Modes............................... 1591
39.6.1.6
Offset 00000014h: Config - CAN Configuration Register ..................... 1592
39.6.1.7
Offset 00000020h: TxMessageControl[0-7] - Transmit Message Control and
Command .................................................................................... 1593
39.6.1.8
Offset 00000024h: TxMessageID[0-7] - Transmit Message ID ............. 1595
39.6.1.9
Offset 00000028h: TxMessageDataHigh[0-7] - Transmit Message Data High
1596
39.6.1.10 Offset 0000002Ch: TxMessageDataLow[0-7] - Transmit Message Data Low..
1597
39.6.1.11 Offset 000000A0h: RxMessageControl[0-15] - Receive Message Command
and Control .................................................................................. 1598
39.6.1.12 Offset 000000A4h: RxMessageID[0-15] - Receive Message ID............. 1600
39.6.1.13 Offset 000000A8h: RxMessageDataHigh[0-15] - Receive Message Data High
1600
39.6.1.14 Offset 000000ACh: RxMessageDataLow[0-15] - Receive Message Data Low .
1601
39.6.1.15 Offset 000000B0h: RxMessageAMR[0-15] - Receive Message AMR ....... 1601
39.6.1.16 Offset 000000B4h: RxMessageACR[0-15] - Receive Message ACR........ 1602
39.6.1.17 Offset 000000B8h: RxMessageAMR_Data[0-15] - Receive Message AMR Data
1603
39.6.1.18 Offset 000000BCh: RxMessageACR_Data[0-15] - Receive Message ACR Data
1603
40.0 SSP Serial Port..................................................................................................... 1605
40.1 Overview ...................................................................................................... 1605
40.2 Feature List .................................................................................................. 1605
40.3 Theory of Operation ....................................................................................... 1605
40.3.1
Endianness .......................................................................................... 1605
40.3.2
Error Handling...................................................................................... 1605
40.4 Register Summary ......................................................................................... 1606
40.4.1
SSP Control Register 0 .......................................................................... 1607
40.4.1.1
Offset 00h: SSCR0 - SSP Control Register 0 Details ........................... 1607
40.4.1.2
Data Size Select (DSS) .................................................................. 1609
Intel® EP80579 Integrated Processor Product Line Datasheet
44
August 2009
Order Number: 320066-003US
Contents
40.4.1.3
40.4.1.4
40.4.1.5
40.4.1.6
40.4.2
SSP
40.4.2.1
40.4.2.2
40.4.2.3
40.4.2.4
40.4.2.5
40.4.2.6
40.4.2.7
40.4.2.8
40.4.2.9
40.4.2.10
40.4.2.11
40.4.3
SSP
40.4.3.1
40.4.3.2
Frame Format (FRF) .......................................................................1609
External Clock Select (ECS).............................................................1609
Synchronous Serial Port Enable (SSE) ..............................................1609
Serial Clock Rate (SCR) ..................................................................1609
Control Register 1...........................................................................1610
Offset 04h: SSCR1 - SSP Control Register 1 Details ............................1610
Receive FIFO Interrupt Enable (RIE) .................................................1611
Transmit FIFO Interrupt Enable (TIE) ...............................................1611
Loop Back Mode (LBM) ...................................................................1611
Serial Clock Polarity (SPO) ..............................................................1612
Serial Clock Phase (SPH) ................................................................1612
National Microwire* Data Size (MWDS) .............................................1613
Transmit FIFO Interrupt Threshold (TFT)...........................................1613
Receive FIFO Interrupt Threshold (RFT) ............................................1613
Enable FIFO Write/Read Function (EFWR)..........................................1613
Select FIFO for Enable FIFO Write/Read (STRF)..................................1614
Status Register...............................................................................1614
Offset 08h: SSSR - SSP Status Register Details .................................1614
Transmit FIFO Not Full Flag (TNF) (Read-Only,
Non-Interruptible)..........................................................................1615
40.4.3.3
Receive FIFO Not Empty Flag (RNE)
(Read-Only, Non-Interruptible) ........................................................1615
40.4.3.4
SSP Busy Flag (BSY) (Read-Only, Non-Interruptible) ..........................1615
40.4.3.5
Transmit FIFO Service Request Flag (TFS) (Read-Only,
Maskable Interrupt) .......................................................................1616
40.4.3.6
Receive FIFO Service Request Flag (RFS) (Read-Only,
Maskable Interrupt) .......................................................................1616
40.4.3.7
Receiver Overrun Status (ROR) (Read/Write,
Non-Maskable Interrupt).................................................................1616
40.4.3.8
Transmit FIFO Level .......................................................................1616
40.4.3.9
Receive FIFO Level.........................................................................1616
40.4.4
SSP Interrupt Test Register ....................................................................1616
40.4.4.1
Offset 0Ch: SSITR - SSP Interrupt Test Register Details ......................1616
40.4.5
SSP Data Register .................................................................................1617
40.4.5.1
Offset 10h: SSDR - SSP Data Register Details....................................1617
41.0 IEEE 1588 Time Synchronization Hardware Assist ................................................1619
41.1 Overview ......................................................................................................1619
41.2 Feature List ...................................................................................................1619
41.2.1
Signal Descriptions................................................................................1620
41.3 Functional Block Diagram ................................................................................1620
41.4 Usage Model ..................................................................................................1622
41.4.1
Channel Mapping ..................................................................................1622
41.5 Functional Description.....................................................................................1622
41.5.1
IEEE 1588 Overview ..............................................................................1622
41.5.1.1
Initialization ..................................................................................1623
41.5.1.2
Time Synchronization .....................................................................1623
41.5.1.3
PTP Message Formats .....................................................................1628
41.5.2
Time Stamping Operation.......................................................................1629
41.5.2.1
Sync Messages ..............................................................................1630
41.5.2.2
Follow-up Messages .......................................................................1630
41.5.2.3
Delay_Req Message .......................................................................1630
41.5.2.4
Delay_Response Messages ..............................................................1631
41.5.2.5
Error Handling ...............................................................................1631
41.5.3
IEEE1588 over Ethernet .........................................................................1631
41.5.3.1
Timestamping Mechanism ...............................................................1631
41.5.3.2
PTP Message Detection in Ethernet Frames........................................1632
41.5.3.3
Modes of Operation ........................................................................1633
August 2009
Order Number: 320066-003US
Intel® EP80579 Integrated Processor Product Line Datasheet
45
Contents
41.5.4
IEEE1588 over CAN .............................................................................. 1634
41.5.5
Auxiliary Snapshots .............................................................................. 1635
41.5.6
Target Time Expiration .......................................................................... 1636
41.5.7
System Time........................................................................................ 1636
41.5.8
Interrupts............................................................................................ 1637
41.5.9
Reset ................................................................................................. 1637
41.6 Register Summary ......................................................................................... 1637
41.6.1
Detailed Register Descriptions ................................................................ 1639
41.6.1.1
Offset 0000h: TS_Control - Time Sync Control Register ...................... 1639
41.6.1.2
Offset 0004h: TS_Event - Time Sync Event Register .......................... 1641
41.6.1.3
Offset 0008h: TS_Addend - Addend Register..................................... 1643
41.6.1.4
Offset 000Ch: TS_Accum - Accumulator Register ............................... 1643
41.6.1.5
Offset 0010h: TS_Test - Time Sync Test Register .............................. 1644
41.6.1.6
Offset 0014h: TS_PPS - PPS Compare Register.................................. 1646
41.6.1.7
Offset 0018h: TS_TSysTimeLo - Raw System Time Low Register ......... 1647
41.6.1.8
Offset 001Ch: TS_RSysTimeHI - Raw System Time High Register ........ 1648
41.6.1.9
Offset 0020h: TS_SysTimeLo - System Time Low Register .................. 1649
41.6.1.10 Offset 0024h: TS_SysTimeHi - System Time High Register.................. 1650
41.6.1.11 Offset 0028h: TS_TrgtLo - Target Time Low Register ......................... 1650
41.6.1.12 Offset 002Ch: TS_TrgtHi - Target Time High Register......................... 1651
41.6.1.13 Offset 0030h: TS_ASMLo - Auxiliary Slave Mode Snapshot
Low Register................................................................................. 1652
41.6.1.14 Offset 0034h: TS_ASMHi - Auxiliary Slave Mode Snapshot
High Register............................................................................... 1653
41.6.1.15 Offset 0038h: TS_AMMSLo - Auxiliary Master Mode Snapshot
Low Register................................................................................. 1654
41.6.1.16 Offset 003Ch: TS_AMMSHi - Auxiliary Master Mode Snapshot High Register .
1655
41.6.1.17 Offset 0040h: TS_Ch_Control[0-7] - Time Synchronization Channel Control
Register (Per Ethernet Channel) ...................................................... 1656
41.6.1.18 Offset 0044h: TS_CH_EVENT[0-7] - Time Synchronization Channel Event
Register (Per Ethernet Channel) ...................................................... 1658
41.6.1.19 Offset 0048h: TS_TxSnapLo[0-7] - Transmit Snapshot Low Register (Per
Ethernet Channel) ......................................................................... 1659
41.6.1.20 Offset 004Ch: TS_TxSnapHi[0-7] - Transmit Snapshot High Register (Per
Ethernet Channel) ......................................................................... 1660
41.6.1.21 Offset 0050h: TS_RxSnapLo[0-7] - Receive Snapshot Low Register (Per
Ethernet Channel) ......................................................................... 1661
41.6.1.22 Offset 0054h: TS_RxSnapHi[0-7] - Receive Snapshot High Register (Per
Ethernet Channel) ......................................................................... 1662
41.6.1.23 Offset 0058h: TS_SrcUUIDLo[0-7] - Source UUID0 Low Register (Per
Ethernet Channel) ......................................................................... 1663
41.6.1.24 Offset 005Ch: TS_SrcUUIDHI[0-7] - SequenceID/SourceUUID High Register
(Per Ethernet Channel) .................................................................. 1664
41.6.1.25 Offset 0140h: TS_CANx_Status[0-1] - Time Synchronization Channel Event
Register (Per CAN Channel) ............................................................ 1665
41.6.1.26 Offset 0144h: TS_CANSnapLo[0-1] - Transmit Snapshot Low Register (Per
CAN Channel) ............................................................................... 1666
41.6.1.27 Offset 0148h: TS_CANSnapHi[0-1] - Transmit Snapshot High Register (Per
CAN Channel) ............................................................................... 1667
41.6.1.28 Offset 01F0h: TS_Aux_TrgtLo - Auxiliary Target Time Low
Register ....................................................................................... 1668
41.6.1.29 Offset 01F4h: TS_Aux_TrgtHi -Auxiliary Target Time High
Register ....................................................................................... 1668
41.6.1.30 Offset 0200h: L2_EtherType - L2 EtherType Register ......................... 1669
41.6.1.31 Offset 0204h: UD_EtherType - User Defined EtherType Register .......... 1669
41.6.1.32 Offset 0208h: UD_Header_Offset - User Defined Header Offset
Register ....................................................................................... 1670
41.6.1.33 Offset 020Ch: UD_Header - User Defined Header Register .................. 1670
Intel® EP80579 Integrated Processor Product Line Datasheet
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August 2009
Order Number: 320066-003US
Contents
42.0 Local Expansion Bus Controller.............................................................................1671
42.1 Overview ......................................................................................................1671
42.2 Feature List ...................................................................................................1671
42.3 Block Diagram ...............................................................................................1672
42.4 Theory of Operation........................................................................................1672
42.4.1
Outbound Transfers...............................................................................1672
42.4.1.1
Chip Select Address Allocation .........................................................1673
42.4.1.2
Address and Data Byte Steering ......................................................1675
42.4.1.3
Expansion Bus Interface Configuration..............................................1676
42.4.1.4
Using I/O Wait ..............................................................................1680
42.4.1.5
Parity ...........................................................................................1681
42.4.1.6
Special Design Knowledge for Using HPI mode...................................1681
42.4.1.7
Expansion Bus Outbound Timing Diagrams ........................................1682
42.5 Register Summary..........................................................................................1696
42.5.1
Timing and Control Registers ..................................................................1698
42.5.1.1
EXP_TIMING_CS0 - Expansion Bus Timing Register ............................1698
42.5.1.2
EXP_TIMING_CS[1-7] - Expansion Bus Timing Registers .....................1700
42.5.2
Configuration and Status Registers ..........................................................1702
42.5.2.1
EXP_CNFG0 - Configuration Register 0..............................................1702
42.5.2.2
EXP_PARITY_STATUS - Expansion Bus Parity Status Register...............1703
42.6 Performance Estimation ..................................................................................1703
Test and Debug, Volume 5 of 6 .................................................. 1707
43.0 Global Design for Test Features ............................................................................1709
43.1 JTAG ...........................................................................................................1709
43.1.1
JTAG Functions Overview ......................................................................1709
43.1.2
EP80579 TAP Controllers ........................................................................1709
43.1.2.1
IA-32 Core....................................................................................1709
43.1.2.2
MCH TAP Extension ........................................................................1709
43.1.3
EP80579 JTAG ID Codes.........................................................................1710
43.1.4
Special Requirements and Limitations ......................................................1710
43.1.5
JTAG Instructions Summary: MCH ...........................................................1710
43.2 I/O Testing ...................................................................................................1713
43.2.1
JTAG Boundary Scan .............................................................................1713
43.2.1.1
Pins Excluded from Boundary Scan Chain ..........................................1713
44.0 IA-32 Core............................................................................................................1715
44.1 JTAG ............................................................................................................1715
44.1.1
Usage..................................................................................................1715
44.1.1.1
Description ...................................................................................1716
45.0 IMCH Design for Test............................................................................................1717
45.1 IMCH Design for Test Features .......................................................................1717
45.1.1
Features .............................................................................................1717
45.2 JTAG ............................................................................................................1717
45.2.1
IMCH JTAG Instructions .........................................................................1717
45.2.1.1
JTAG Chain Details.........................................................................1717
45.3 High Speed I/O Testing ...................................................................................1719
46.0 ICH Design for Test ..............................................................................................1721
46.1 JTAG ............................................................................................................1721
46.2 I/O Test Mode................................................................................................1721
46.2.1
Test Mode Entry Methods .......................................................................1721
46.2.1.1
Non-Functional Test Mode Entry.......................................................1721
46.2.2
Test Mode Registers ..............................................................................1723
46.2.2.1
TEST0 - Test Control Register 0 .......................................................1723
August 2009
Order Number: 320066-003US
Intel® EP80579 Integrated Processor Product Line Datasheet
47
Contents
46.2.3
XOR Chains ........................................................................................ 1725
Technical Specifications, Volume 6 of 6..................................... 1727
47.0 SKUs, Power Savings and Pre-Boot Firmware ...................................................... 1729
47.1 Overview ...................................................................................................... 1729
47.2 SKUs, Strap Options and Pre-Boot Firmware Programmable Configuration Modes ... 1729
47.2.1
SKU Features ....................................................................................... 1729
47.2.2
DDR2 Frequencies Supported by the EP80579 .......................................... 1731
47.2.3
Strap Options (Platform-based Configuration)........................................... 1731
47.2.4
Pre-Boot Firmware Programmable SKU Options ........................................ 1732
48.0 Package Specifications......................................................................................... 1733
48.1 Package Introduction ..................................................................................... 1733
48.2 Functional Signal Definitions............................................................................ 1733
48.3 JTAG Boundary Scan Chain (BSC) and XOR Chain .............................................. 1733
48.4 Signal Pin Descriptions ................................................................................... 1734
48.4.1
IA-32 Core .......................................................................................... 1736
48.4.1.1
Thermal Diode .............................................................................. 1736
48.4.1.2
Global Clock CRU .......................................................................... 1736
48.4.1.3
Sideband Miscellaneous Signals....................................................... 1737
48.4.2
Integrated Memory Controller Hub (IMCH) ............................................... 1739
48.4.2.1
IMCH Reset .................................................................................. 1739
48.4.2.2
DDR2 SDRAM ............................................................................... 1739
48.4.2.3
PCI Express* ................................................................................ 1741
48.4.3
Integrated I/O Controller Hub (IICH)....................................................... 1744
48.4.3.1
Real Time Clock ............................................................................ 1744
48.4.3.2
General Purpose I/O (GPIO) and Interrupts ...................................... 1744
48.4.3.3
Serial Peripheral Interface (SPI) ...................................................... 1749
48.4.3.4
Low Pin Count (LPC) Interface......................................................... 1749
48.4.3.5
SMBus ......................................................................................... 1750
48.4.3.6
UART Interface ............................................................................. 1751
48.4.3.7
Serial ATA (SATA) Interface............................................................ 1753
48.4.3.8
Universal Serial Bus (USB) Interface ................................................ 1755
48.4.3.9
Power Management Interface.......................................................... 1756
48.4.3.10 IICH Miscellaneous Signals ............................................................. 1758
48.4.4
Acceleration and I/O Complex (AIOC)...................................................... 1759
48.4.4.1
Controller Area Network (CAN) Bus.................................................. 1759
48.4.4.2
Gigabit Ethernet (GbE) Interface ..................................................... 1760
48.4.4.3
Time Division Multiplexing (TDM) Interface ....................................... 1764
48.4.4.4
Local Expansion Bus (LEB) Interface ................................................ 1765
48.4.4.5
Synchronous Serial Port (SSP) Interface........................................... 1768
48.4.4.6
IEEE 1588-2008 Hardware Assist Interface ....................................... 1768
48.4.5
Miscellaneous....................................................................................... 1769
48.4.5.1
JTAG ........................................................................................... 1769
48.4.5.2
Miscellaneous Signals .................................................................... 1770
48.4.5.3
Reserved ..................................................................................... 1770
48.4.5.4
No Connect .................................................................................. 1771
48.4.6
Power ................................................................................................. 1772
48.5 Flip-Chip Ball Grid Array (FCBGA) Package Dimensions ....................................... 1773
48.6 Ball Map Information ...................................................................................... 1778
49.0 Electrical Specifications ....................................................................................... 1819
49.1 Absolute Maximum Ratings ............................................................................. 1820
49.1.1
Input and I/O Pin Undershoot and Overshoot Specifications........................ 1820
49.2 Power Characteristics ..................................................................................... 1823
49.2.1
Power Supply Requirements................................................................... 1823
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Order Number: 320066-003US
Contents
49.3 Clocks ..........................................................................................................1829
49.3.1
External Clock Requirements ..................................................................1829
49.4 Power and Reset Sequencing ...........................................................................1830
49.5 AC/DC Characteristics .....................................................................................1831
49.5.1
Power Management ...............................................................................1831
49.5.1.1
Power Management Signal List ........................................................1831
49.5.1.2
Power Management AC Characteristics..............................................1832
49.5.2
DDR2 ..................................................................................................1836
49.5.2.1
DDR2 Signal List............................................................................1836
49.5.2.2
DDR2 DC Characteristics.................................................................1836
49.5.2.3
DDR2 AC Characteristics .................................................................1838
49.5.3
PCI Express* ........................................................................................1846
49.5.3.1
PCI Express* Signal List .................................................................1846
49.5.3.2
PCI Express* Differential Transmitter and Receiver Specifications.........1846
49.5.3.3
PCI Express* Clock Specifications ....................................................1850
49.5.4
Serial ATA (SATA) .................................................................................1854
49.5.4.1
SATA Signal List ............................................................................1854
49.5.4.2
SATA DC Characteristics .................................................................1854
49.5.4.3
SATA DC Output Characteristics.......................................................1855
49.5.4.4
SATA LED .....................................................................................1855
49.5.4.5
SATA AC Characteristics .................................................................1856
49.5.5
Universal Serial Bus (USB) .....................................................................1856
49.5.5.1
USB Signal List ..............................................................................1856
49.5.5.2
USB DC Characteristics...................................................................1857
49.5.5.3
USB AC Characteristics ...................................................................1859
49.5.5.4
USB AC Specifications ....................................................................1859
49.5.6
System Management Bus (SMBus) ..........................................................1863
49.5.6.1
SMBus Signal List ..........................................................................1863
49.5.6.2
SMBus DC Characteristics ...............................................................1863
49.5.6.3
SMBus AC Characteristics ...............................................................1864
49.5.7
UART...................................................................................................1867
49.5.7.1
UART Signal List ............................................................................1867
49.5.7.2
UART DC Characteristics .................................................................1867
49.5.7.3
UART AC Characteristics .................................................................1868
49.5.7.4
UART Receiver AC Specifications ......................................................1868
49.5.8
Serial Peripheral Interface (SPI) ..............................................................1869
49.5.8.1
SPI Signal List ...............................................................................1869
49.5.8.2
SPI DC Characteristics ....................................................................1869
49.5.8.3
SPI AC Characteristics ....................................................................1869
49.5.9
Low Pin Count (LPC) ..............................................................................1870
49.5.9.1
LPC Signal List ..............................................................................1870
49.5.9.2
LPC DC Characteristics ...................................................................1871
49.5.9.3
LPC AC Characteristics....................................................................1872
49.5.10 General Purpose I/O (GPIO) ...................................................................1874
49.5.10.1 GPIO Signal List ............................................................................1874
49.5.10.2 GPIO DC Characteristics .................................................................1874
49.5.10.3 GPIO AC Specifications ...................................................................1875
49.5.11 IICH Interrupt Signal .............................................................................1875
49.5.11.1 IICH Interrupt Signal List ................................................................1875
49.5.11.2 IICH Interrupt Signal DC Characteristics ...........................................1875
49.5.11.3 IICH Interrupt Signal AC Input, Output Characteristics........................1876
49.5.11.4 IICH Interrupt Signal Timing Specification .........................................1876
49.5.11.5 IICH Clock AC Specifications............................................................1876
49.5.12 Real Time Clock (RTC) ...........................................................................1877
49.5.12.1 RTC Signal List ..............................................................................1877
49.5.12.2 RTC DC Characteristics ...................................................................1877
49.5.12.3 RTC AC Characteristics ...................................................................1878
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Intel® EP80579 Integrated Processor Product Line Datasheet
49
Contents
49.5.13 Gigabit Ethernet (GbE: RMII, RGMII, MDIO, EEPROM) ............................... 1879
49.5.13.1 Gigabit Ethernet Signal List ............................................................ 1879
49.5.13.2 Gigabit Ethernet DC Characteristics ................................................. 1879
49.5.13.3 Gigabit Ethernet AC Characteristics.................................................. 1882
49.5.13.4 GbE Reset Conditions .................................................................... 1890
49.5.13.5 RComp ........................................................................................ 1890
49.5.13.6 Voltage Domains ........................................................................... 1891
49.5.14 Time Division Multiplex (TDM) ................................................................ 1891
49.5.14.1 TDM Signal List ............................................................................. 1891
49.5.14.2 TDM DC Characteristics .................................................................. 1891
49.5.14.3 TDM DC Clock Specification ............................................................ 1892
49.5.14.4 TDM AC Characteristics .................................................................. 1893
49.5.15 Local Expansion Bus (LEB) ..................................................................... 1894
49.5.15.1 LEB Signal List .............................................................................. 1894
49.5.15.2 LEB DC Characteristics ................................................................... 1895
49.5.15.3 LEB AC Characteristics ................................................................... 1896
49.5.16 Controller Area Network (CAN) ............................................................... 1897
49.5.16.1 CAN Signal List ............................................................................. 1897
49.5.16.2 CAN DC Characteristics .................................................................. 1897
49.5.17 Synchronous Serial Port (SSP)................................................................ 1897
49.5.17.1 SSP Signal List.............................................................................. 1897
49.5.17.2 SSP DC Characteristics................................................................... 1898
49.5.17.3 SSP AC Characteristics ................................................................... 1900
49.5.18 IEEE 1588-2008 Hardware Assist Interface .............................................. 1901
49.5.18.1 IEEE 1588-2008 Hardware Assist Signal List ..................................... 1901
49.5.18.2 IEEE 1588-2008 Hardware Assist DC Characteristics .......................... 1901
49.5.18.3 IEEE 1588-2008 Hardware Assist AC Characteristics ......................... 1901
49.5.19 IICH Miscellaneous Signals (PME#, PCIRST#, SPKR) ................................. 1901
49.5.19.1 IICH Miscellaneous Signal List ......................................................... 1901
49.5.19.2 IICH Miscellaneous Signals DC Characteristics ................................... 1902
49.5.19.3 IICH Miscellaneous Signals AC Characteristics ................................... 1902
49.5.20 Clock Resource Unit (CRU)..................................................................... 1902
49.5.20.1 CRU Signal List ............................................................................. 1902
49.5.20.2 CRU DC Characteristics .................................................................. 1903
49.5.20.3 CRU AC Specifications .................................................................... 1904
49.5.21 Sideband Miscellaneous Signals .............................................................. 1905
49.5.21.1 Sideband Miscellaneous Signals Signal List ....................................... 1905
49.5.21.2 Sideband Miscellaneous Signals DC Characteristics ............................ 1905
49.5.21.3 Sideband Miscellaneous Signals AC Characteristics............................. 1906
49.5.22 IMCH Reset ......................................................................................... 1906
49.5.22.1 IMCH Reset Signal List ................................................................... 1906
49.5.22.2 IMCH Reset Signals DC Characteristics ............................................. 1906
49.5.22.3 IMCH Reset Signals AC Characteristics ............................................. 1906
49.5.23 JTAG................................................................................................... 1907
49.5.23.1 JTAG Signal List ............................................................................ 1907
49.5.23.2 JTAG DC Characteristics ................................................................ 1907
49.5.23.3 JTAG AC Characteristics ................................................................. 1907
50.0 Thermal Specifications and Design Considerations............................................... 1911
50.1 Thermal Characteristics .................................................................................. 1911
50.1.1
Specifications....................................................................................... 1912
50.1.2
Thermal Design Power (TDP) Dissipation.................................................. 1912
50.2 Thermal Sensor ............................................................................................. 1912
50.2.1
Catastrophic Thermal Protection ............................................................. 1913
50.2.1.1
THRMTRIP# Control Sequence ........................................................ 1913
50.2.2
Thermal Sensor Features ....................................................................... 1914
50.2.2.1
PROCHOT# Control Sequence ......................................................... 1914
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Order Number: 320066-003US
Contents
50.2.2.2
50.2.2.3
Figures
2-1
2-2
3-1
3-2
3-3
3-4
4-1
4-2
4-3
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
9-1
10-1
10-2
10-3
10-4
11-1
11-2
11-3
11-4
11-5
12-1
12-2
12-3
12-4
12-5
12-6
12-7
12-8
12-9
12-10
12-11
12-12
12-13
12-14
12-15
12-16
12-17
12-18
Processor Passive Cooling ...............................................................1915
On-Demand Passive Cooling ............................................................1915
Intel® EP80579 Integrated Processor Block Diagram ............................................. 104
Intel® EP80579 Integrated Processor with Intel® QuickAssist
Technology Block Diagram................................................................................. 105
Device-Centric Logical View of EP80579 Devices ................................................... 112
Logical Overview of the CMI PCI Infrastructure..................................................... 115
Attaching the AIOC to the CMI PCI Fabric (Logical Perspective) .............................. 120
Overview of PCI infrastructure for On-die Devices................................................. 121
Logical Overview of Signaling Architecture ........................................................... 131
Logical View of Signaling Flow ............................................................................ 134
Signal Bridging ................................................................................................ 135
Powergood and Reset Interface .......................................................................... 164
Reset Sequence ............................................................................................... 167
EP80579 Rail Power On Sequence ...................................................................... 169
Power Rail Sequence Timings (Sustain Well Power Management) ............................ 170
Power Rail Sequence Timing (No Sustain Well Power Management)......................... 171
Powergood Reset Sequence ............................................................................... 172
Hard Reset Sequence........................................................................................ 173
BIOS Boot Flow (Cold Boot, S3/S4->S0) ............................................................. 175
Global System Power States and Transitions ........................................................ 177
CMI Block Diagram ........................................................................................... 255
Basic Memory Regions ...................................................................................... 267
DOS Legacy Region .......................................................................................... 269
Memory Region from 1 MByte through 4 GBytes ................................................... 271
PAM Associated Attribute Bits............................................................................. 273
Memory Address Tables for 64 Bit, Burst Size 4 and x8 DDR2 Devices ..................... 296
Memory Address Tables for 32 Bit, Burst Size 8 and x8 DDR2 Devices ..................... 296
2T and 1T Timing Mode..................................................................................... 297
ODT Timing on Back-to-Back Reads to Different Slots ........................................... 300
ODT Timing on Back-to-Back Writes to Different Slots ........................................... 301
Concept Diagram of EDMA Data Path .................................................................. 308
Conceptual Diagram of Four Channel EDMA Engine ............................................... 310
Chain Descriptor in Memory ............................................................................... 312
Chaining Mechanism ......................................................................................... 313
Source and Destination in Increment Mode Transfer.............................................. 319
Source in Decrement and Destination in Increment Mode Transfer (Byte Reversal).... 320
Source in Increment and Destination in 1-Byte Granularity Constant Mode Transfer .. 321
Source in Increment and Destination in 2-Byte Granularity Constant Mode Transfer .. 322
Source in Increment and Destination in 4-Byte Granularity Constant Mode Transfer .. 323
Source in Decrement and Destination in 1-Byte Granularity Constant Mode Transfer . 324
Source in Decrement and Destination in 2-Byte Granularity Constant Mode Transfer . 325
Source in Decrement and Destination in 4-Byte Granularity Constant Mode Transfer . 326
Source in Memory Initialization and Destination in Increment Mode Transfer ............ 327
Source in Buffer Initialization and Destination in 1-Byte Granularity Constant Mode
Transfer .......................................................................................................... 328
Source in Buffer Initialization and Destination in 2-Byte Granularity Constant Mode
Transfer .......................................................................................................... 328
Source in Buffer Initialization and Destination in 4-Byte Granularity Constant Mode
Transfer .......................................................................................................... 329
Initiation Flow Chart ......................................................................................... 343
Completion Flow Chart ...................................................................................... 344
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Contents
13-1
13-2
13-3
13-4
13-5
13-6
13-7
14-1
14-2
14-3
15-1
15-2
15-3
15-4
15-5
15-6
15-7
15-8
19-1
19-2
20-1
20-2
21-1
23-1
23-2
23-3
23-4
25-1
25-2
26-1
27-1
28-1
33-1
33-2
33-3
33-4
35-1
35-2
35-3
37-1
37-2
37-3
37-4
37-5
37-6
37-7
37-8
37-9
37-10
37-11
37-12
37-13
37-14
37-15
Bus 0 Device Map ............................................................................................. 348
NSI Type 0 Configuration Address Translation ...................................................... 350
NSI Type 1 Configuration Address Translation ...................................................... 351
Mechanism #1 Type 1 Configuration Address to PCI Address Mapping...................... 351
IMCH Configuration Flow Chart ........................................................................... 352
PCI Express Configuration Transaction Header ...................................................... 356
Enhanced Configuration Memory Address Map ...................................................... 357
Global FERR/NERR Register Representation .......................................................... 362
FERR/NERR Service Routine ............................................................................... 364
PCI Express Error Handling ................................................................................ 368
Dword Configuration Read Protocol ..................................................................... 377
Dword Configuration Write Protocol ..................................................................... 377
Dword Memory Read Protocol............................................................................. 377
Dword Memory Write Protocol ............................................................................ 377
Dword Configuration Read Protocol ..................................................................... 378
Dword Configuration Write Protocol ..................................................................... 378
Dword Memory Read Protocol............................................................................. 379
Dword Configuration Write Protocol ..................................................................... 379
LPC Interface Diagram ...................................................................................... 758
LPC Bridge SERR# ........................................................................................... 762
IICH DMA Controller.......................................................................................... 763
DMA Request Assertion through LDRQ#............................................................... 780
Basic SPI Protocol ............................................................................................. 787
Legacy Mode Host Controller Power State Hierarchy .............................................. 880
Hardware Flow for Port Enable/Device Present Bits................................................ 883
Port System Memory Structure ........................................................................... 884
Power State Hierarchy ....................................................................................... 890
Example Queue Conditions................................................................................. 967
USB Data Encoding ........................................................................................... 970
USB Port Connections...................................................................................... 1033
C0→C2→C0 Entry/Exit Timings......................................................................... 1081
Coprocessor Error Timing Diagram .................................................................... 1103
Example UART Data Frame .............................................................................. 1173
WDT Block Diagram ........................................................................................ 1193
Start Frame Timing with Source Sampled a Low Pulse on IRQ1 ............................. 1203
Stop Frame Timing with Host Using Quiet Mode Sampling Period........................... 1203
PCI Configuration Command Register Layout ...................................................... 1234
PCI Configuration Status Register Layout ........................................................... 1234
PCI Power Management Register Block .............................................................. 1236
GbE Controller Block Diagram........................................................................... 1344
GbE Ethernet Complex .................................................................................... 1345
Multicast Table Array Algorithm ........................................................................ 1349
Example Address Byte Ordering........................................................................ 1352
DA Byte Ordering ........................................................................................... 1352
Receive Descriptor (RDESC) Layout................................................................... 1355
Receive Status (RDESC.Status) Layout .............................................................. 1356
Receive Errors (RDESC.ERRORS) Layout ............................................................ 1357
Special Descriptor Field Layout ......................................................................... 1358
Receive Descriptor Ring Structure ..................................................................... 1359
Packet Delay Timer operation illustrated with a state diagram............................... 1361
Case A: Using only an Absolute Timer ............................................................... 1361
Case B: Using an Absolute Timer in conjunction with the Packet Timer................... 1362
Case C: Packet Timer Expires Even Though A Packet Was Being Transferred
to the Host Memory. ....................................................................................... 1362
IPv6 Extension Header Structure ...................................................................... 1364
Intel® EP80579 Integrated Processor Product Line Datasheet
52
August 2009
Order Number: 320066-003US
Contents
37-16
37-17
37-18
37-19
37-20
37-21
37-22
37-23
37-24
37-25
37-26
37-27
37-28
37-29
37-30
37-31
37-32
37-33
37-34
37-35
37-36
37-37
37-38
37-39
37-40
37-41
37-42
37-43
37-44
37-45
37-46
37-47
37-48
37-49
37-50
37-51
37-52
37-53
37-54
37-55
39-1
39-2
39-3
39-4
39-5
39-6
39-7
39-8
39-9
41-1
41-2
41-3
41-4
41-5
42-1
Transmit Descriptor (TDESC) Layout ..................................................................1366
Legacy Transmit Descriptor (TDESC) Layout .......................................................1366
Transmit Command (TDESC.CMD) Layout...........................................................1367
Transmit Status Layout (TDESC.STATUS) ...........................................................1368
Transmit Special Field Layout (TDESC.SPECIAL) ..................................................1369
TCP/IP Context Transmit Descriptor (TDESC) - (Type = 0000)...............................1370
TCP/IP Context Transmit Descriptor Command Field (TDESC.TUCMD).....................1371
TCP/IP Context Transmit Descriptor Status (TDESC.TUSTATUS).............................1372
TCP/IP Data Transmit Descriptor Layout (TDESC) - (Type = 0001).........................1373
TCP/IP Data Transmit Descriptor Command Field (TDESC.DCMD) ..........................1373
TCP/IP Data Transmit Descriptor Status (TDESC.DSTATUS) ..................................1375
TCP/IP Data Transmit Descriptor Packet Options Field (TDESC.POPTS) ...................1375
TCP/IP Data Transmit Descriptor Special Field (TDESC.VLAN) ................................1375
Transmit Descriptor Ring Structure ....................................................................1376
Transmit Descriptor and TUCMD Field (TDESC) Layouts - (Type = 0000) ................1380
TCP/IP Packet Format ......................................................................................1382
TCP/IP Context Transmit Descriptor & Command Layout.......................................1383
TCP Partial Pseudo-Header Checksum for IPv4 ....................................................1384
TCP Partial Pseudo-Header Checksum for IPv6 ....................................................1384
IPv4 Header (Traditional Representation) ...........................................................1385
IPv4 Header (Little-Endian Order)......................................................................1385
IPv6 Header (Traditional Representation) ...........................................................1385
TCP Header (Traditional Representation) ............................................................1386
TCP Header (Little-Endian Order) ......................................................................1386
TCP Pseudo Header Content (Traditional Representation)......................................1387
TCP Pseudo-Header Content for IPv6 .................................................................1387
UDP Header (Traditional Representation)............................................................1387
UDP Header (Little-Endian Order) ......................................................................1387
UDP Pseudo Header Diagram for IPv4 ................................................................1388
UDP Pseudo-Header Diagram for IPv6 ................................................................1388
Data Flow.......................................................................................................1391
802.3x MAC Control Frame Format ....................................................................1398
TCI Bit Ordering..............................................................................................1401
Memory Protection in the GbE ...........................................................................1419
Power State Transitions ...................................................................................1550
Reset Deasserted after 1st EEPROM Read Completes............................................1552
Reset Deasserted after before EEPROM Read Completes .......................................1553
Transition from D0a to D3 and Back without Reset...............................................1554
Transition from D0a to D3 and Back with Reset ...................................................1555
Reset without Transition to D3 ..........................................................................1556
CAN Block Diagram .........................................................................................1570
Standard CAN Data Frame................................................................................1572
Extended CAN Data Frame ...............................................................................1574
Standard CAN Remote Frame............................................................................1575
Extended CAN Remote Frame ...........................................................................1576
CAN Timing Parameters ...................................................................................1578
Bit Rate and Time Settings ...............................................................................1579
Receive Message Handler .................................................................................1581
Message Arbitration .........................................................................................1584
Programming Model.........................................................................................1621
Example Network Topology...............................................................................1623
Clock Synchronization ......................................................................................1625
Transparent Clock Switch Protocol Flow ..............................................................1627
Time Stamp Reference Point .............................................................................1632
Expansion Bus Controller..................................................................................1672
August 2009
Order Number: 320066-003US
Intel® EP80579 Integrated Processor Product Line Datasheet
53
Contents
42-2
42-3
42-4
42-5
42-6
42-7
42-8
42-9
42-10
42-11
42-12
42-13
42-14
42-15
42-16
42-17
42-18
42-19
42-20
42-21
42-22
46-1
46-2
48-1
48-2
48-3
49-1
49-2
49-3
49-4
49-5
49-6
49-7
49-8
49-9
49-10
49-11
49-12
49-13
49-14
49-15
49-16
49-17
49-18
49-19
49-20
49-21
49-22
49-23
49-24
49-25
49-26
49-27
49-28
49-29
Chip Select Address Allocation When There Are no 32-MByte Devices Programmed.. 1674
Expansion Bus Memory Sizing .......................................................................... 1674
Chip Select Address Allocation when a 32 Mbyte device is programmed ................. 1675
Expansion Bus I/O Wait Operation .................................................................... 1681
Expansion-Bus Write (Intel, Multiplexed Mode) ................................................... 1683
Expansion-Bus Read (Intel, Multiplexed Mode).................................................... 1683
Expansion-Bus Write (Intel-Simplex Mode, Synchronous Intel) ............................. 1684
Expansion-Bus Read (Intel, Simplex Mode) ........................................................ 1684
Intel Synchronous 8-word Read ........................................................................ 1685
Intel Synchronous One-Word Read.................................................................... 1686
Micron* ZBT Write/Read/Write ......................................................................... 1687
Expansion-Bus Write (Motorola*, Multiplexed Mode) ............................................ 1688
Expansion-Bus Read (Motorola*, Multiplexed Mode) ............................................ 1689
Expansion-Bus Write (Motorola*, Simplex Mode)................................................. 1690
Expansion-Bus Read (Motorola*, Simplex Mode) ................................................. 1690
Expansion-Bus Write (TI* HPI-8 Mode) .............................................................. 1691
Expansion-Bus Read (TI* HPI-8 Mode) .............................................................. 1692
Expansion-Bus Write (TI* HPI-16, Multiplexed Mode) .......................................... 1693
Expansion-Bus Read (TI* HPI-16, Multiplexed Mode) ........................................... 1694
Expansion-Bus Write (TI* HPI-16, Simplex Mode) ............................................... 1695
Expansion-Bus Read (TI* HPI-16, Simplex Mode)................................................ 1696
Serial Test Mode Entry for Write ....................................................................... 1722
Serial Test Mode Entry for Read........................................................................ 1722
FCBGA Package — Top and Side Views .............................................................. 1775
FCBGA Package — Front and Detail Views .......................................................... 1776
FCBGA Package — Bottom View........................................................................ 1777
G3 (Mechanical Off) to S0 Timings .................................................................... 1834
S0 to S1 to S0 Timing ..................................................................................... 1834
S0 to S5 to S0 Timings, S3COLD ........................................................................ 1835
DQ and CB (ECC) Setup/Hold Relationship to/from DQS (Read Operation) .............. 1843
DQ and CB (ECC) Valid Before and After DQS (Write Operation)............................ 1843
Write Preamble Duration.................................................................................. 1844
Write Postamble Duration ................................................................................ 1844
Control Signals Valid before and after DDR_CK Rising Edge .................................. 1844
Clock Cycle Time ............................................................................................ 1844
Skew Between any System Memory Differential Clock Pair (DDR_CK/DDR_CK#) ..... 1845
DDR2 Command Clock High Time ..................................................................... 1845
DDR2 Command Clock Low Time ...................................................................... 1845
DDR2 Command Clock to DQS skew.................................................................. 1846
PCI Express* Transmitter Test Load .................................................................. 1851
PCI Express* Receiver Compliance Eye Diagram ................................................. 1851
PCI Express* Transmitter Compliance Eye Diagram ............................................. 1852
Differential Clock Waveform ............................................................................. 1853
Differential Clock Cross-Point Specification ......................................................... 1853
Clock Timing .................................................................................................. 1860
USB Rise and Fall Times .................................................................................. 1861
USB Jitter ...................................................................................................... 1862
USB EOP Width .............................................................................................. 1862
SMBus Transaction ......................................................................................... 1865
SMBus Timeout .............................................................................................. 1866
SPI Timing Diagram ........................................................................................ 1870
LPC Clock (PCICLK) Timing Diagram.................................................................. 1872
LPC Input Setup and Hold Timing Diagram ......................................................... 1873
LPC Valid Delay from Rising Clock Edge Diagram................................................. 1873
LPC Output Enable Delay Diagram .................................................................... 1873
Intel® EP80579 Integrated Processor Product Line Datasheet
54
August 2009
Order Number: 320066-003US
Contents
49-30
49-31
49-32
49-33
49-34
49-35
49-36
49-37
49-38
49-39
49-40
49-41
49-42
49-43
49-44
49-45
49-46
49-47
49-48
49-49
49-50
LPC Float Delay Diagram ..................................................................................1874
IICH Interrupt Signal Timing Diagram ................................................................1876
IICH Clock (CLK14) Timing Diagram ..................................................................1877
RTC Clock Output (SUSCLK) Timing Diagram ......................................................1878
GbE RGMII Mode Signal Connection Block Diagram ..............................................1883
RGMII 125 MHz Reference Clock Timing Diagram ................................................1884
GbE Transmit Waveform — RGMII Mode.............................................................1885
GbE Receive Waveform — RGMII Mode ..............................................................1886
GbE RMII Mode Signal Connection Block Diagram — External Clock Source .............1887
GbE RMII Transmit and Receive Waveforms — RMII Mode ....................................1887
MDIO Output Timing Diagram (EP80579 is Sourcing MDIO) ..................................1888
MDIO Input Timing Diagram (PHY is Sourcing MDIO) ...........................................1888
EEPROM Interface Timing Diagram ....................................................................1889
TDM, Serial Timings.........................................................................................1894
Local Expansion Bus Synchronous Timing ...........................................................1896
SSP Signal Connection Block Diagram - Multi-Drop Connections ............................1899
SSP Interface Timing Diagram ..........................................................................1900
CRU Differential Clock Waveform.......................................................................1903
CRU Differential Clock Cross-Point Specification...................................................1904
JTAG Output Timing Measurement Waveforms ....................................................1908
JTAG Input Timing Measurement Waveforms ......................................................1909
Tables
1-1
1-2
1-3
1-4
2-1
2-2
2-3
2-4
2-5
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
4-1
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
Referenced Documents ...................................................................................... 94
Related Websites ............................................................................................... 95
Acronym Table................................................................................................... 95
Glossary Table .................................................................................................. 98
EP80579 External Interface Summary ................................................................ 106
IA-32 core / FSB Frequency Ratios (depends on SKU and configuration) .................. 107
Memory Controller Frequencies .......................................................................... 107
Summary of Communication .............................................................................. 107
DMA and Peer-to-Peer Data Transfer Options ....................................................... 109
Main Memory DRAM Organization ..................................................................... 112
Basic CMI Platform Address Space Requirements for IMCH and IICH Devices............ 115
Memory Regions .............................................................................................. 116
Supported Operations by Memory Type ............................................................... 117
Supported Operations by Memory Type ............................................................... 118
Device Exposure from an IA-attached Memory Map Perspective .............................. 119
Address Space Sizes of AIOC-attached Devices .................................................... 119
Expansion Bus Byte Ordering for Inbound Transactions using LEBCTL register .......... 119
IMCH and IICH PCI Device Summary .................................................................. 122
AIOC PCI Device Summary ................................................................................ 123
PCI Configuration Header Support for Type 0 Headers in AIOC Devices ................... 125
PCI Configuration Header Support for Type 1 Headers in AIOC Devices ................... 127
Supported Inter-Agent Signaling ........................................................................ 134
Summary of IMCH Global Error Conditions ........................................................... 142
Summary of IMCH Buffer Unit Error Conditions..................................................... 143
Summary of IMCH Buffer Unit Error Reporting Capabilities ..................................... 143
Summary of IMCH FSB Error Conditions .............................................................. 144
Summary of IMCH FSB Error Reporting Capabilities .............................................. 144
Summary of IMCH NSI Error Conditions .............................................................. 145
Summary of IMCH NSI Error Reporting Capabilities............................................... 146
Summary of IMCH EDMA Error Conditions ........................................................... 146
August 2009
Order Number: 320066-003US
Intel® EP80579 Integrated Processor Product Line Datasheet
55
Contents
5-9
5-10
5-11
5-12
5-13
5-14
5-15
5-16
5-17
5-18
5-19
5-20
5-21
5-22
5-23
5-24
5-25
5-26
5-27
5-28
5-29
5-30
5-31
5-32
5-33
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
6-12
7-1
7-2
7-3
7-4
7-5
7-6
7-7
7-8
7-9
7-10
7-11
7-12
7-13
Summary of IMCH EDMA Error Reporting Capabilities ............................................ 147
Summary of IMCH PCI-Express Error Conditions ................................................... 148
Summary of IMCH PCI-Express Error Reporting Capabilities.................................... 149
Summary of SMBus Interface Error Conditions...................................................... 150
Summary of SMBus Controller Error Reporting Capabilities ..................................... 150
Summary of LPC Interface Error Conditions .......................................................... 150
Summary of LPC Interface Error Reporting Capabilities .......................................... 150
Summary of USB 1.1 Interface Error Conditions.................................................... 151
Summary of USB 1.1 Interface Error Reporting Capabilities .................................... 151
Summary of USB 2.0 Interface Error Conditions.................................................... 152
Summary of USB 2.0 Interface Error Reporting Capabilities .................................... 152
Summary of SATA Interface Error Conditions........................................................ 152
Summary of SATA Interface Error Reporting Capabilities ........................................ 153
Summary of Serial I/O Interface Error Conditions.................................................. 153
Summary of Serial I/O Interface Error Reporting Capabilities .................................. 153
Summary of Memory Controller Error Conditions................................................... 154
Summary of Memory Controller Error Reporting Capabilities ................................... 155
Summary of Gigabit Ethernet MAC Error Conditions............................................... 156
Summary of Gigabit Ethernet MAC Error Reporting Capabilities ............................... 156
Summary of CAN Error Conditions....................................................................... 157
Summary of CAN Error Reporting Capabilities ....................................................... 157
Summary of SSP Error Conditions ....................................................................... 158
Summary of SSP Error Reporting Capabilities ....................................................... 158
Summary of Local Expansion Bus Error Conditions ................................................ 158
Summary of Local Expansion Bus Error Reporting Capabilities................................. 159
Types of Reset and Wake-up from Power Saving States ......................................... 161
Power Wells and External Voltages ...................................................................... 162
EP80579 Power Supply Pins ............................................................................... 168
Power Rail Sequence Signal Timings.................................................................... 171
Powergood Reset Timings .................................................................................. 173
Hard Reset Timings........................................................................................... 174
Global Power States .......................................................................................... 178
Device States................................................................................................... 178
Sleeping States ................................................................................................ 179
CPU States ...................................................................................................... 179
ACPI States ..................................................................................................... 180
Power Wells Status for Supported ACPI States* .................................................... 180
Definition of the Views Used in Register Description Tables..................................... 184
View Convention to Describe Single Versus Multiple Physical Registers ..................... 185
Offset Convention to Describe Multiple Physical Registers in the Same Device ........... 186
EG_SINGLE: Example Single Register with Different Views ..................................... 187
EG_MULTI_DIFF: Example Multiple Registers in Different Devices with Different
Views.............................................................................................................. 187
EG_MULTI_SAME[1-2]: Example Multiple Registers in Same Device with Different
Views.............................................................................................................. 188
EG_INDEX: Example Single Indexed Register ....................................................... 188
Register Field Access Attributes .......................................................................... 189
Bus 0, Device 0, Function 0: Summary of IMCH PCI Configuration Registers ............. 191
Bus 0, Device 0, Function 0: Summary of IMCH Configuration Registers Mapped Through
NSIBAR Memory BAR ........................................................................................ 192
Bus 0, Device 0, Function 0: Summary of IMCH SMRBASE Registers ........................ 193
Bus 0, Device 0, Function 1: Summary of IMCH Error Reporting PCI Configuration
Registers ......................................................................................................... 195
Bus 0, Device 1, Function 0: Summary of EDMA PCI Configuration Registers ............ 197
Intel® EP80579 Integrated Processor Product Line Datasheet
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August 2009
Order Number: 320066-003US
Contents
7-14
7-15
7-16
7-17
7-18
7-19
7-20
7-21
7-22
7-23
7-24
7-25
7-26
7-27
7-28
7-29
7-30
7-31
7-32
7-33
7-34
7-35
7-36
7-37
7-38
7-39
7-40
7-41
7-42
7-43
7-44
7-45
7-46
7-47
7-48
Bus 0, Device 1, Function 0: Summary of EDMA Configuration Registers Mapped Through
EDMALBAR Memory BAR ................................................................................... 197
Bus 0, Device 2, Function 0: Summary of PCI Express Port A Standard and Enhanced PCI
Configuration Registers ..................................................................................... 200
Bus 0, Device 3, Function 0: Summary of PCI Express Port A1 Standard and Enhanced PCI
Configuration Registers ..................................................................................... 203
Bus 0, Device 29, Functions 0, Summary of USB (1.1) Controller PCI Configuration
Registers ........................................................................................................ 206
Summary of USB (1.1) Controller Configuration Registers Mapped Through USBIOBAR
I/O BAR .......................................................................................................... 206
Bus 0, Device 29, Function 7: Summary of USB (2.0) Controller PCI Configuration
Registers ........................................................................................................ 207
Bus 0, Device 29, Function 7: Summary of USB (2.0) Controller Configuration Registers
Mapped Through MBAR Memory BAR .................................................................. 208
Bus 0, Device 31, Function 0: Summary of Root Complex Configuration Registers Mapped
Through RCBA Memory BAR............................................................................... 209
Bus 0, Device 31, Function 0: Summary of LPC Interface PCI Configuration Registers 210
Bus 0, Device 31, Function 0: Summary of LPC Interface Power Management PCI
Configuration Registers ..................................................................................... 211
Bus 0, Device 31, Function 0: Summary of TCO Configuration Registers Mapped Through
TCOBASE I/O BAR“........................................................................................... 211
Bus 0, Device 31, Function 0: Summary of LPC Interface Power Management General
Configuration Registers Mapped Through PMBASE I/O BAR .................................... 211
Bus 0, Device 31, Function 0: Summary of General Purpose I/O Configuration Registers
Mapped Through GBA BAR IO BAR...................................................................... 212
Bus 0, Device 31, Function 2: Summary of SATA Controller PCI Configuration
Registers ........................................................................................................ 213
Bus 0, Device 31, Function 2: Summary of SATA Controller Configuration Registers
Mapped Through LBAR I/O BAR.......................................................................... 214
Bus 0, Device 31, Function 2: Summary of SATA Controller Configuration Registers
Mapped Through ABAR Memory BAR ................................................................... 214
Bus 0, Device 31, Function 3: Summary of SMBus Controller PCI Configuration
Registers ........................................................................................................ 216
Bus 0, Device 31, Function 3: Summary of SMBus Controller Configuration Registers
Mapped Through SM_BASE I/O BAR.................................................................... 216
Summary of IA-32 Core Interface Registers Mapped in I/O Space ........................... 217
Summary of IMCH PCI Configuration Registers Mapped in I/O Space ....................... 217
Summary of APIC Registers Mapped in Memory Space“ ......................................... 217
Summary of APIC Indexed Registers................................................................... 218
Summary of 8259 Interrupt Controller (PIC) Registers Mapped in I/O Space ............ 219
Summary of APM Registers Mapped in I/O Space.................................................. 219
Summary of LPC DMA Registers Mapped in I/O Space ........................................... 220
0000h (IO) Base Address Registers in the IA F1 View ............................................ 220
0000h (IO) Base Address Registers in the IA F2 View ............................................ 221
Summary of 8254 Timer Registers Mapped in I/O Space........................................ 221
Summary of HPET Registers Mapped in Memory Space .......................................... 222
Summary of UART Timer registers in I/O space .................................................... 222
Summary of Watchdog Timer Registers in I/O Space............................................. 223
Summary of Real Time Clock Indexed Registers ................................................... 223
Bus 0, Device 4, Function 0: Summary of PCI-to-PCI Bridge PCI Configuration
Registers ........................................................................................................ 224
Bus M, Device 0, Function 0: Summary of Gigabit Ethernet MAC Interface PCI
Configuration Registers ..................................................................................... 226
Bus M, Device 1, Function 0: Summary of Gigabit Ethernet MAC Interface PCI
Configuration Registers ..................................................................................... 227
August 2009
Order Number: 320066-003US
Intel® EP80579 Integrated Processor Product Line Datasheet
57
Contents
7-49
7-50
7-51
7-52
7-53
7-54
7-55
7-56
7-57
7-58
7-59
7-60
7-61
7-62
7-63
7-64
7-65
7-66
7-67
8-1
9-1
10-1
10-2
10-3
10-4
10-5
10-6
10-7
10-8
10-9
10-10
10-11
10-12
10-13
10-14
10-15
10-16
10-17
10-18
10-19
11-1
11-2
11-3
11-4
11-5
Bus M, Device2, Function 0: Summary of Gigabit Ethernet MAC Interface PCI Configuration
Registers ......................................................................................................... 228
Bus M, Device 0, Function 0: Gigabit Ethernet MAC I/O Spaces Registers ................. 229
Bus M, Device 1, Function 0: Gigabit Ethernet MAC I/O Spaces Registers ................. 229
Bus M, Device 2, Function 0: Gigabit Ethernet MAC I/O Spaces Registers ................. 229
Bus M, Device 0, Function 0: Summary of Gigabit Ethernet Interface Registers Mapped
Through CSRBAR Memory BAR ........................................................................... 229
Bus M, Device 1, Function 0: Summary of Gigabit Ethernet Interface Registers Mapped
Through CSRBAR Memory BAR ........................................................................... 233
Bus M, Devices 2, Function 0: Summary of Gigabit Ethernet Interface Registers Mapped
Through CSRBAR Memory BAR ........................................................................... 236
Bus M, Device 3, Function 0: Summary of GCU PCI Configuration Registers .............. 240
Bus M, Device 3, Function 0: Summary of GCU Registers Mapped Through CSRBAR
Memory BAR .................................................................................................... 240
Bus M, Device 4, Function 0: Summary of CAN Interface PCI Configuration Registers. 242
Bus M, Devices 5, Function 0: Summary of CAN Interface PCI Configuration Registers243
Bus M, Device 4, Function 0: Summary of CAN Registers Mapped Through CSRBAR
Memory BAR .................................................................................................... 244
Bus M, Device 5, Function 0: Summary of CAN Registers Mapped Through CSRBAR
Memory BAR .................................................................................................... 244
Bus M, Device 6, Function 0: Summary of SSP Controller PCI Configuration Registers 245
Bus M, Device 6, Function 0: Summary of SSP CSRs ............................................. 246
Bus M, Device 7, Function 0: Summary of IEEE 1588 Timestamp Unit PCI Configuration
Registers ......................................................................................................... 247
Bus M, Device 7, Function 0: Summary of IEEE 1588 TSYNC CSRs .......................... 248
Bus M, Device 8, Function 0: Summary of Local Expansion Bus PCI Configuration
Registers ......................................................................................................... 249
Bus M, Device 8, Function 0: Summary of Local Expansion Bus Registers Mapped Through
CSRBAR PCI Memory BAR"................................................................................. 250
Processor Version Identification Signature (CPUID) ............................................... 254
Supported PCI Express Configurations ................................................................ 257
Regions of Memory Ranges ................................................................................ 267
System Memory Space ...................................................................................... 268
IMCH VGA and MDA Memory Spaces ................................................................... 268
IMCH PAM Memory Address Ranges .................................................................... 270
PAM Associated Attribute Bits ............................................................................ 273
TSEG SMM Memory Space ................................................................................. 274
PCI Express Enhanced Configuration Aperture ...................................................... 274
IOAPIC Memory Space ...................................................................................... 275
FSB Interrupt Memory Space.............................................................................. 275
High SMM Memory Space................................................................................... 276
Device 2 Memory and Prefetchable Memory.......................................................... 277
Device 3 Memory and Prefetchable Memory.......................................................... 277
Device 4 Memory and Prefetchable Memory.......................................................... 277
EDMA Accesses to Fixed Address Spaces ............................................................. 278
EDMA Accesses to Relocatable Address Spaces ..................................................... 279
Supported SMM Ranges ..................................................................................... 282
Fixed I/O Ranges Decoded by IICH .................................................................... 284
Variable I/O Decode Ranges .............................................................................. 286
IICH Memory Decode Ranges (from IA-32 core Perspective) .................................. 287
Supported DDR2 Device Densities and Width........................................................ 291
Supported DRAM Capacity for 64b Mode .............................................................. 291
Supported DRAM Capacity for 32b Mode .............................................................. 292
Raw Cards Supported by the EP80579 ................................................................ 292
Supported DDR2 Data Speeds ............................................................................ 292
Intel® EP80579 Integrated Processor Product Line Datasheet
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August 2009
Order Number: 320066-003US
Contents
11-6
11-7
11-8
11-9
11-10
11-11
11-12
11-13
11-14
11-15
11-16
11-17
12-1
12-2
13-1
13-2
13-3
13-4
13-5
14-1
15-1
15-2
15-3
15-4
15-5
15-6
15-7
15-8
15-9
15-10
15-11
15-12
16-1
16-2
16-3
16-4
16-5
16-6
16-7
16-8
16-9
16-10
16-11
16-12
16-13
16-14
16-15
16-16
16-17
16-18
16-19
16-20
16-21
16-22
16-23
Supported DIMM Populations ............................................................................. 293
Supported Rank Configurations in Single and Dual DIMM mode .............................. 293
256Mb Addressing ............................................................................................ 294
512Mb Addressing ............................................................................................ 294
1Gb Addressing................................................................................................ 294
2Gb Addressing................................................................................................ 295
Supported DRAM Timings .................................................................................. 296
DRA Mapping for DQS ....................................................................................... 298
DQS to DQ Mapping for x8 Devices ..................................................................... 298
ODT Timing Parameters .................................................................................. 299
Supported DDR2 MR and EMR settings ................................................................ 303
Poisoning Granularity........................................................................................ 305
Channel 0 Memory-mapped Register Set ............................................................. 332
Interrupt Summary ........................................................................................ 338
PCI Devices and Functions on Bus 0 ................................................................... 346
Summary of IMCH PCI Configuration Registers Mapped in I/O Space ....................... 354
Offset 0CF8h: CONFIG_ADDRESS: Configuration Address Register ........................ 354
Offset 0CFCh: CONFIG_DATA: Configuration Data Register .................................... 355
Enhanced Configuration FSB Address Format ....................................................... 357
Pseudocode for EDMA Errors ............................................................................ 369
SMBus Register Summary ................................................................................. 372
SMBus Memory-Mapped Register Summary ......................................................... 372
ADDR3 Memory Assignments ............................................................................ 372
Command (CMD) Register ................................................................................ 373
Byte Count Register.......................................................................................... 374
Address Byte 3 Register .................................................................................... 374
ADDR2 – Address Byte 2 Register....................................................................... 375
ADDR1 – Address Byte 1 Register....................................................................... 375
ADDR0 – Address Byte 0 Register....................................................................... 375
Offset 04-07: DATA - Data Register .................................................................... 376
Status Register ................................................................................................ 376
Relationship Between Link and Device PM States .................................................. 383
Bus 0, Device 0, Function 0: Summary of IMCH PCI Configuration Registers............. 389
Offset 00h: VID – Vendor Identification Register .................................................. 391
Offset 02h: DID – Device Identification Register .................................................. 391
Offset 04h: PCICMD: PCI Command Register ...................................................... 392
Offset 06h: PCISTS: PCI Status Register ........................................................... 393
Offset 8h: RID - Revision Identification Register ................................................. 394
Offset 0Ah: SUBC - Sub-Class Code Register ...................................................... 394
Offset 0Bh: BCC – Base Class Code Register ....................................................... 394
Offset 0Eh: HDR - Header Type Register ............................................................ 395
Offset 14h: SMRBASE - System Memory RCOMP Base Address Register ................. 396
Offset 2Ch: SVID - Subsystem Vendor Identification Register ............................... 396
Offset 2Eh: SID - Subsystem Identification Register ............................................ 397
Offset 34h: CAPPTR - Capabilities Pointer Register .............................................. 397
Offset 4Ch: NSIBAR - Root Complex Block Address Register ................................. 397
Offset 50h: CFG0- IMCH Configuration 0 Register ............................................... 398
Offset 51h: IMCH_CFG1 – IMCH Configuration 1 Register .................................... 399
Offset 53h: CFGNS1 - Configuration 1 (Non-Sticky) Register ................................ 399
Offset 58h: FDHC - Fixed DRAM Hole Control Register ......................................... 400
Offset 59h: PAM0 - Programmable Attribute Map 0 Register ................................. 401
Offset 5Ah: PAM1: Programmable Attribute Map 1 Register .................................. 402
Offset 5Bh: PAM2 - Programmable Attribute Map 2 Register ................................. 403
Offset 5Ch: PAM3 - Programmable Attribute Map 3 Register ................................. 404
Offset 5Dh: PAM4 - Programmable Attribute Map 4 Register ................................. 405
August 2009
Order Number: 320066-003US
Intel® EP80579 Integrated Processor Product Line Datasheet
59
Contents
16-24
16-25
16-26
16-27
16-28
16-29
16-30
16-31
16-32
16-33
16-34
16-35
16-36
16-37
16-38
16-39
16-40
16-41
16-42
16-43
16-44
16-45
16-46
16-47
16-48
16-49
16-50
16-51
16-52
16-53
16-54
16-55
16-56
16-57
16-58
16-59
16-60
16-61
16-62
16-63
16-64
16-65
16-66
16-67
16-68
16-69
16-70
16-71
16-72
16-73
16-74
Offset 5Eh: PAM5 - Programmable Attribute Map 5 Register ................................. 406
Offset 5FH: PAM6 - Programmable Attribute Map 6 Register ................................. 407
Offset 9Ch: DEVPRES - Device Present Register .................................................. 408
Offset 9Dh: EXSMRC - Extended System Management RAM Control Register ........... 409
Offset 9Eh: SMRAM - System Management RAM Control Register .......................... 411
Offset 9Fh: EXSMRAMC - Expansion System Management RAM Control Register ...... 413
Offset B8h: IMCH_MENCBASE: IA/ASU Shared Non-Coherent (AIOC-Direct) Memory Base
Address Register ............................................................................................ 413
Offset BCh: IMCH_MENCLIMIT - IA/ASU Shared Non-Coherent (AIOC-Direct) Memory
Limit Address Register ..................................................................................... 414
Offset C4h: TOLM - Top of Low Memory Register ................................................. 415
Offset C6h: REMAPBASE - Remap Base Address Register ..................................... 416
Offset C8h: REMAPLIMIT – Remap Limit Address Register ..................................... 416
Offset CAh: REMAPOFFSET - Remap Offset Register ............................................ 417
Offset CCh: TOM - Top Of Memory Register ........................................................ 417
Offset CEh: HECBASE - PCI Express Port A (PEA) Enhanced Configuration Base Address
Register ......................................................................................................... 418
Offset D8h: CACHECTL0 - Write Cache Control 0 Register .................................... 418
Offset DEh: SKPD - Scratchpad Data Register ..................................................... 419
Offset F6h: IMCH_TST2 - IMCH Test Byte 2 Register ........................................... 419
DRB to DIMM designation .................................................................................. 420
Offset 60h: DRB[0-3] - DRAM Row [3:0] Boundary Register ................................. 421
DRA[1:0] Field Selection.................................................................................... 422
Offset 70h: DRA[0-1] - DRAM Row [0:1] Attribute Register .................................. 422
Offset 78h: DRT0 - DRAM Timing Register 0 ........................................................ 424
Offset 64h: DRT1 - DRAM timing Register 1 ........................................................ 431
Offset 7Ch: DRC - DRAM Controller Mode Register .............................................. 435
Offset 84h: ECCDIAG - ECC Detection/Correction Diagnostic Register ..................... 437
Offset 88h: SDRC - DDR SDRAM Secondary Control Register ................................ 439
Offset 8Ch: CKDIS - CK/CK# Clock Disable Register ............................................ 441
Offset 8Dh: CKEDIS - CKE Clock Enable Register ................................................ 442
Offset 90h: SPARECTL - SPARE Control Register .................................................. 443
Offset B0h: DDR2ODTC - DDR2 ODT Control Register ........................................... 444
Bus 0, Device 0, Function 1: Summary of IMCH Error Reporting PCI Configuration
Registers ......................................................................................................... 445
Offset 00h: VID - Vendor Identification Register .................................................. 447
Offset 02h: DID - Device Identification Register ................................................... 447
Offset 04h: PCICMD - PCI Command Register ..................................................... 448
Offset 06h: PCISTS - PCI Status Register ........................................................... 448
Offset 08h: RID - Revision Identification Register ................................................ 449
Offset 0Ah: SUBC - Sub-Class Code Register ...................................................... 449
Offset 0Bh: BCC - Base Class Code Register ....................................................... 449
Offset 0Dh: MLT - Master Latency Timer Register ................................................ 450
Offset 0Eh: HDR - Header Type Register ............................................................ 450
Offset 2Ch: SVID - Subsystem Vendor Identification Register ............................... 450
Offset 2Eh: SID - Subsystem Identification Register ............................................ 451
Offset 40h: GLOBAL_FERR - Global First Error Register ........................................ 451
Offset 44h: GLOBAL_NERR - Global Next Error Register ....................................... 453
Offset 48h: NSI_FERR - NSI First Error Register .................................................. 454
Offset 4Ch: NSI_NERR - NSI Next Error Register ................................................. 457
Offset 50h: NSI_SCICMD - NSI SCI Command Register ....................................... 459
Offset 54h: NSI_SMICMD: NSI SMI Command Register ........................................ 461
Offset 58h: NSI_SERRCMD - NSI SERR Command Register .................................. 464
Offset 5Ch: NSI_MCERRCMD - NSI MCERR Command Register .............................. 466
Offset 60h: FSB_FERR - FSB First Error Register ................................................. 468
Intel® EP80579 Integrated Processor Product Line Datasheet
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August 2009
Order Number: 320066-003US
Contents
16-75
16-76
16-77
16-78
16-79
16-80
16-81
16-82
16-83
16-84
16-85
16-86
16-87
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16-91
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16-95
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16-102
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16-106
16-107
16-108
16-109
16-110
16-111
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16-113
16-114
16-115
16-116
16-117
16-118
16-119
16-120
16-121
16-122
16-123
16-124
16-125
Offset 62h: FSB_NERR - FSB Next Error Register ................................................ 469
Offset 64h: FSB_EMASK - FSB Error Mask Register ............................................. 470
offset 68h: FSB_SCICMD - FSB SCI Command Register ....................................... 471
Offset 6Ah: FSB_SMICMD - FSB SMI Command Register ...................................... 472
Offset 6Ch: FSB_SERRCMD - FSB SERR Command Register ................................. 473
Offset 6Eh: FSB_MCERRCMD - FSB MCERR Command Register ............................. 474
Offset 70h: BUF_FERR - Memory Buffer First Error Register ................................. 475
Offset 72h: BUF_NERR - Memory Buffer Next Error Register ................................. 475
Offset 74h: BUF_EMASK - Memory Buffer Error Mask Register .............................. 476
Offset 78h: BUF_SCICMD - Memory Buffer SCI Command Register ....................... 477
Offset 7Ah: BUF_SMICMD - Memory Buffer SMI Command Register ...................... 478
Offset 7Ch: BUF_SERRCMD - Memory Buffer SERR Command Register .................. 479
Offset 7Eh: BUF_MCERRCMD - Memory Buffer MCERR Command Register .............. 480
Offset E4h: NSIERRINJCTL - NSI Error Injection Control Register .......................... 481
Offset E8h: BERRINJCTL - Buffer Error Injection Control Register .......................... 482
Offset 80h: DRAM_FERR - DRAM First Error Register ........................................... 483
Offset 82h: DRAM_NERR - DRAM Next Error Register .......................................... 484
Offset 84h: DRAM_EMASK - DRAM Error Mask Register ....................................... 486
Offset 88h: DRAM_SCICMD - DRAM SCI Command Register ................................. 487
Offset 8Ah: DRAM_SMICMD - DRAM SMI Command Register ................................ 488
Offset 8Ch: DRAM_SERRCMD - DRAM SERR Command Register ............................ 489
Offset 8Eh: DRAM_MCERRCMD - DRAM MCERR Command Register ....................... 490
Offset 98h: THRESH_SEC0 - Rank 0 SEC Error Threshold Register ......................... 491
Offset 9Ah: THRESH_SEC1 - Rank 1 SEC Error Threshold Register ........................ 491
Offset A0h: DRAM_SECF_ADD - DRAM First Single Bit Error Correct Address
Register ........................................................................................................ 492
Offset A4h: DRAM_DED_ADD - DRAM Double Bit Error Address Register ................ 492
Offset A8h: DRAM_SCRB_ADD - DRAM Scrub Error Address Register ..................... 493
Offset B0h: DRAM_SEC_R0 - DRAM Rank 0 SEC Error Counter Register ................. 494
Offset B2h: DRAM_DED_R0 - DRAM Rank 0 DED Error Counter Register ................ 494
Offset B4h: DRAM_SEC_R1 - DRAM Rank 1 SEC Error Counter Register ................. 494
Offset B6h: DRAM_DED_R1 - DRAM Rank 1 DED Error Counter Register ................ 495
Offset C2h: THRESH_DED - DED Error Threshold Register .................................... 495
Offset C4h: DRAM_SECF_SYNDROME - DRAM First Single Error Correct
Syndrome Register ......................................................................................... 496
Offset C6h: DRAM_SECN_SYNDROME - DRAM Next Single Error Correct
Syndrome Register .......................................................................................... 496
Offset C8h: DRAM_SECN_ADD - DRAM Next Single Bit Error Correct Address
Register ......................................................................................................... 497
Offset DCh: RANKTHREX - Rank Error Threshold Exceeded Register ...................... 498
Offset ECh: DERRINJCTL - DRAM Error Injection Control Register .......................... 499
Bus 0, Device 1, Function 0: Summary of EDMA PCI Configuration Registers ............ 501
Offset 00h: VID - Vendor Identification Register ................................................. 502
Offset 02h: DID - Device Identification Register ................................................. 502
Offset 04h: PCICMD - PCI Command Register .................................................... 503
Offset 06h: PCISTS - PCI Status Register .......................................................... 504
Offset 08h: RID - Revision Identification Register ............................................... 504
Offset 0Ah: SUBC - Sub-Class Code Register ...................................................... 505
Offset 0Bh: BCC - Base Class Code Register ....................................................... 505
Offset 0Eh: HDR - Header Type Register ............................................................ 505
Offset 10h: EDMALBAR - EDMA Low Base Address Register .................................. 506
Offset 2Ch: SVID - Subsystem Vendor Identification Register ................................ 506
Offset 2Eh: SID - Subsystem Identification Register ............................................. 507
Offset 34h: CAPPTR - Capabilities Pointer Register .............................................. 507
Offset 3Ch: INTRLINE - Interrupt Line Register ................................................... 507
August 2009
Order Number: 320066-003US
Intel® EP80579 Integrated Processor Product Line Datasheet
61
Contents
16-126
16-127
16-128
16-129
16-130
16-131
16-132
16-133
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16-135
16-136
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16-164
16-165
16-166
16-167
16-168
16-169
16-170
16-171
16-172
16-173
16-174
16-175
16-176
16-177
Offset 3Dh: INTRPIN - Interrupt Pin Register ...................................................... 508
Offset 40h: EDMACTL - EDMA Control Register ................................................... 508
Offset 80h: EDMA_FERR - EDMA First Error Register ............................................ 509
Offset 84h: EDMA_NERR - EDMA Next Error Register ........................................... 511
Offset 88h: EDMA_EMASK - EDMA Error Mask Register ........................................ 513
Offset A0h: EDMA_SCICMD - EDMA SCI Command Register ................................. 514
Offset A4h: EDMA_SMICMD - EDMA SMI Command Register .................................. 515
Offset A8h: EDMA_SERRCMD - EDMA SERR Command Register ............................ 516
Offset ACh: EDMA_MCERRCMD - EDMA MCERR Command Register ......................... 517
Offset B0h: MSICR - MSI Control Register .......................................................... 518
Offset B4h: MSIAR - MSI Address Register ......................................................... 519
Offset B8h: MSIDR - MSI Data Register ............................................................. 520
Bus 0, Device 2, Function 0: Summary of PCI Express Port A Standard and
Enhanced PCI Configuration Registers ................................................................. 522
Bus 0, Device 3, Function 0: Summary of PCI Express Port A1 Standard and
Enhanced PCI Configuration Registers ................................................................. 524
Offset 00h: VID - Vendor Identification Register .................................................. 527
Offset 02h: DID - Device Identification Register .................................................. 527
Offset 02h: DID - Device Identification Register ................................................... 528
Offset 04h: PCICMD - PCI Command Register ..................................................... 528
Offset 06h: PCISTS - PCI Status Register ............................................................ 530
Offset 08h: RID - Revision Identification Register ................................................ 531
Offset 0Ah: SUBC - Sub-Class Code Register ...................................................... 532
Offset 0Bh: BCC - Base Class Code Register ....................................................... 532
Offset 0Ch: CLS - Cache Line Size Register ........................................................ 533
Offset 0Eh: HDR - Header Type Register ............................................................ 533
Offset 18h: PBUSN - Primary Bus Number Register ............................................. 534
Offset 19h: SBUSN - Secondary Bus Number Register .......................................... 534
Offset 1Ah: SUBUSN: Subordinate Bus Number Register ...................................... 535
Offset 1Ch: IOBASE - I/O Base Address Register ................................................. 535
Offset 1Dh: IOLIMIT - I/O Limit Address Register ................................................ 536
Offset 1Eh: SECSTS - Secondary Status Register ................................................ 536
Offset 20h: MBASE - Memory Base Address Register ........................................... 538
Offset 22h: MLIMIT - Memory Limit Address Register ........................................... 539
Offset 24h: PMBASE - Prefetchable Memory Base Address Register ........................ 540
Offset 26h: PMLIMIT - Prefetchable Memory Limit Address Register ....................... 540
Offset 28h: PMBASU - Prefetchable Memory Base Upper Address Register .............. 541
Offset 2Ch: PMLMTU - Prefetchable Memory Limit Upper Address Register .............. 541
Offset 34h: CAPPTR - Capabilities Pointer Register .............................................. 542
Offset 3Ch: INTRLINE - Interrupt Line Register ................................................... 542
Offset 3Dh: INTRPIN - Interrupt Pin Register ...................................................... 543
Offset 3Eh: BCTRL - Bridge Control Register ....................................................... 543
Offset 44h: VSCMD0 - Vendor Specific Command Byte 0 Register ......................... 545
Offset 45h: VSCMD1 - Vendor Specific Command Byte 1 Register ......................... 546
Offset 46h: VSSTS0 - Vendor Specific Status Byte 0 Register ................................ 547
Offset 47h: VSSTS1 - Vendor Specific Status Byte 1 Register ................................ 547
Offset 48h: VSCMD2 - Vendor Specific Command Byte 2 Register ......................... 548
Offset 50h: PMCAPID - Power Management Capabilities Structure Register ............. 548
Offset 51h: PMNPTR - Power Management Next Capabilities Pointer Register .......... 549
Offset 52h: PMCAPA - Power Management Capabilities Register ............................ 549
Offset 54h: PMCSR - Power Management Status and Control Register .................... 550
Offset 56h: PMCSRBSE - Power Management Status and Control Bridge Extensions
Register ........................................................................................................ 551
Offset 58h: MSICAPID - MSI Capabilities Structure Register ................................. 551
Offset 59h: MSINPTR - MSI Next Capabilities Pointer Register ............................... 552
Intel® EP80579 Integrated Processor Product Line Datasheet
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August 2009
Order Number: 320066-003US
Contents
16-178
16-179
16-180
16-181
16-182
16-183
16-184
16-185
16-186
16-187
16-188
16-189
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16-221
16-222
16-223
16-224
16-225
16-226
16-227
16-228
16-229
16-230
16-231
16-232
Offset 5Ah: MSICAPA - MSI Capabilities Register ................................................ 553
Offset 5Ch: MSIAR - MSI Address for PCI Express Register .................................. 553
Offset 60h: MSIDR - MSI Data Register ............................................................. 554
Offset 64h: PEACAPID - PCI Express Features Capabilities ID Register ................... 555
Offset 65h: PEANPTR - PCI Express Next Capabilities Pointer Register ................... 556
Offset 66h: PEACAPA - PCI Express Features Capabilities Register ........................ 556
Offset 68h: PEADEVCAP - PCI Express Device Capabilities Register ....................... 557
Offset 6Ch: PEADEVCTL - PCI Express Device Control Register ............................. 558
Offset 6Eh: PEADEVSTS - PCI Express Device Status Register ............................... 560
Offset 70h: PEALNKCAP - PCI Express Link Capabilities Register ........................... 561
Offset 70h: PEA1LNKCAP - PCI Express Link Capabilities Register ......................... 561
Offset 74h: PEALNKCTL - PCI Express Link Control Register ................................. 562
Offset 76h: PEALNKSTS - PCI Express Link Status Register .................................. 564
Offset 78h: PEASLTCAP - PCI Express Slot Capabilities Register ............................ 565
Offset 78h: PEA1SLTCAP - PCI Express Slot Capabilities Register .......................... 566
Offset 7Ch: PEASLTCTL - PCI Express Slot Control Register .................................. 568
Offset 7Eh: PEASLTSTS - PCI Express Slot Status Register ................................... 569
Offset 80h: PEARPCTL - PCI Express Root Port Control Register ............................ 570
Offset 84h: PEARPSTS - PCI Express Root Port Status Register ............................. 571
Offset 100h: ENHCAPST - Enhanced Capability Structure Register ......................... 571
Offset 104h: UNCERRSTS - Uncorrectable Error Status Register ............................ 572
Offset 108h: UNCERRMSK - Uncorrectable Error Mask Register ............................. 574
Offset 10Ch: UNCERRSEV - Uncorrectable Error Severity Register .......................... 575
Offset 110h: CORERRSTS - Correctable Error Status Register ................................ 576
Offset 114h: CORERRMSK - Correctable Error Mask Register ................................ 578
Offset 118h: AERCACR - Advanced Error Capabilities and Control Register ............. 579
Offset 11Ch: HDRLOG0 - Header Log DW 0 (1st 32 bits) Register ......................... 580
Offset 120h: HDRLOG1 - Header Log DW 1 (2nd 32 bits) Register ........................ 580
Offset 124h: HDRLOG2 - Header Log DW 2 (3rd 32 bits) Register .......................... 581
Offset 128h: HDRLOG3 - Header Log DW 3 (4th 32 bits) Register ......................... 581
Offset 12Ch: RPERRCMD - Root (Port) Error Command Register ............................ 582
Offset 130h: RPERRMSTS - Root (Port) Error Message Status Register ................... 583
Offset 134h: ERRSID - Error Source ID Register ................................................. 585
Offset 140h: PEAUNITERR - PCI Express Unit Error Register ................................. 586
Offset 144h: PEAMASKERR - PCI Express Unit Mask Error Register ........................ 588
Offset 148h: PEAERRDOCMD - PCI Express Error Do Command Register ................ 589
Offset 14Ch: UNCEDMASK - Uncorrectable Error Detect Mask Register ................... 591
Offset 150h: COREDMASK - Correctable Error Detect Mask Register ...................... 592
Offset 158h: PEAUNITEDMASK - PCI Express Unit Error Detect Mask Register ......... 594
Offset 160h: PEAFERR - PCI Express First Error Register ....................................... 595
Offset 164h: PEANERR - PCI Express Next Error Register ..................................... 597
Offset 168h: PEAERRINJCTL - Error Injection Control Register .............................. 597
Bus 0, Device 0, Function 0: Summary of IMCH SMRBASE Registers ....................... 599
Offset 00h: NOTESPAD - Note (Sticky) Pad for BIOS Support Register ................... 601
Offset 02h: NOTEPAD - Note Pad for BIOS Support Register ................................. 601
Offset 40h: DCALCSR – DCAL Control and Status Register ................................... 602
DCALCSR.OPMODS in Receive Enable Mode ......................................................... 604
DCALCSR.OPMODS in ZQ Calibration Mode .......................................................... 604
Rules about issuing Self-Refresh and Refresh commands using DCALCSR.OPCODE .... 604
DCALCSR.OPMODS in DQS Cal Mode................................................................... 605
DCALCSR.OPMODS in Error Monitor/Read DDRIO FIFO Mode.................................. 605
Offset 44h: DCALADDR - DCAL Address Register .................................................. 606
Interpretation of DCALADDR based on DCALCSR.OPCODE...................................... 606
Offset 48h: DCALDATA[0-71] - DRAM Calibration Data Register.............................. 607
DCALDATA Based on DCALCSR.OPCODE.............................................................. 608
August 2009
Order Number: 320066-003US
Intel® EP80579 Integrated Processor Product Line Datasheet
63
Contents
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16-275
16-276
16-277
16-278
16-279
16-280
16-281
16-282
16-283
16-284
16-285
16-286
16-287
Offset 94h: RCVENAC - Receiver Enable Algorithm Control Register ......................... 611
Offset 98h: DSRETC - DRAM Self-Refresh (SR) Extended Timing and Control Register 611
Offset 9Ch: DQSFAIL1 - DQS Failure Configuration Register 1................................. 612
Offset A0h: DQSFAIL0 - DQS Failure Configuration Register 0................................. 613
Offset A4h: DRRTC00 - Receive Enable Reference Output Timing Control Register ..... 615
Offset A8h: DRRTC01 - Receive Enable Reference Output Timing Control Register ..... 616
Offset C4h: DRRTC02 - Receive Enable Reference Output Timing Control Register ..... 616
Offset B4h: DQSOFCS00 - DQS Calibration Register .............................................. 617
Offset B8h: DQSOFCS01 - DQS Calibration Register .............................................. 617
Offset C6h: DQSOFCS02 - DQS Calibration Register .............................................. 618
Offset BCh: DQSOFCS10 - DQS Calibration Register .............................................. 618
Offset C0h: DQSOFCS11 - DQS Calibration Register .............................................. 619
Offset C7h: DQSOFCS12 - DQS Calibration Register .............................................. 619
Offset CCh: WPTRTC0 - Write Pointer Timing Control Register................................. 620
Offset D0h: WPTRTC1 - Write Pointer Timing Control 1 Register .............................. 621
Offset D4h: DDQSCVDP0 - DQS Delay Calibration Victim Pattern 0 Register.............. 621
Offset D8h: DDQSCVDP1 - DQS Delay Calibration Victim Pattern 1 Register.............. 622
Offset DCh: DDQSCADP0 - DQS Delay Calibration Aggressor Pattern 0 Register ........ 622
Offset E0h: DDQSCADP1 - DQS Delay Calibration Aggressor Pattern 1 Register......... 623
Offset F0h: DIOMON - DDR I/O Monitor Register .................................................. 623
Offset F8h: DRAMISCTL - Miscellaneous DRAM DDR Cluster Control Register ............ 624
Offset C8h: DRAMDLLC - DDR I/O DLL Control Register ......................................... 625
Offset E8h: FIVESREG - Fixed 5s Pattern Register ................................................. 625
Offset ECh: AAAAREG - Fixed A Pattern Register ................................................... 626
Offset 140h: MBCSR - MemBIST Control Register ................................................ 626
Offset 144h: MBADDR - Memory Test Address Register.......................................... 629
Offset 148h: MBDATA[0:9] - Memory Test Data Register ....................................... 629
MBDATA Failure Address Register Correspondence to DRAM Address ....................... 631
BL4 Column and Chunk Correspondence to DRAM Address ..................................... 631
BL8 Column and Chunk Correspondence to DRAM Address ..................................... 631
Offset 19Ch: MB_START_ADDR - Memory Test Start Address Register .................... 632
Offset 1A0h: MB_END_ADDR - Memory Test End Address Register .......................... 632
Offset 1A4h: MBLFSRSED - Memory Test Circular Shift and LFSR Seed Register ........ 633
Offset 1A8h: MBFADDRPTR - Memory Test Failure Address Pointer Register .............. 633
Offset 1B0h: MB_ERR_DATA00 - Memory Test Error Data 0 ................................... 634
Offset 1B4h: MB_ERR_DATA01 - Memory Test Error Data 0 ................................... 634
Offset 1B8h: MB_ERR_DATA02 - Memory Test Error Data 0 ................................... 634
Offset 1BCh: MB_ERR_DATA03 - Memory Test Error Data 0 ................................... 635
Offset 1C0h: MB_ERR_DATA04 - Memory Test Error Data 0 ................................... 635
Offset 1C4h: MB_ERR_DATA10 - Memory Test Error Data 1 ................................... 635
Offset 1C8h: MB_ERR_DATA11 - Memory Test Error Data 1 ................................... 636
Offset 1CCh: MB_ERR_DATA12 - Memory Test Error Data 1 .................................. 636
Offset 1D0h: MB_ERR_DATA13 - Memory Test Error Data 1 .................................. 636
Offset 1D4h: MB_ERR_DATA14 - Memory Test Error Data 1 .................................. 637
Offset 1D8h: MB_ERR_DATA20 - Memory Test Error Data 2 .................................. 637
Offset 1DCh: MB_ERR_DATA21 - Memory Test Error Data 2 .................................. 637
Offset 1E0h: MB_ERR_DATA22 - Memory Test Error Data 2 ................................... 638
Offset 1E4h: MB_ERR_DATA23 - Memory Test Error Data 2 ................................... 638
Offset 1E8h: MB_ERR_DATA24 - Memory Test Error Data 2 ................................... 638
Offset 1ECh: MB_ERR_DATA30 - Memory Test Error Data 3 ................................... 639
Offset 1F0h: MB_ERR_DATA31 - Memory Test Error Data 3 ................................... 639
Offset 1F4h: MB_ERR_DATA32 - Memory Test Error Data 3 ................................... 639
Offset 1F8h: MB_ERR_DATA33 - Memory Test Error Data 3 ................................... 640
Offset 1FCh: MB_ERR_DATA34 - Memory Test Error Data 3 ................................... 640
Offset 260h: DDRIOMC0 - DDRIO Mode Register Control Register .......................... 641
Intel® EP80579 Integrated Processor Product Line Datasheet
64
August 2009
Order Number: 320066-003US
Contents
16-288
16-289
16-290
16-291
16-292
16-293
16-294
16-295
16-296
16-297
16-298
16-299
16-300
16-301
16-302
16-303
16-304
16-305
16-306
16-307
16-308
16-309
16-310
16-311
16-312
16-313
16-314
16-315
16-316
16-317
16-318
16-319
16-320
16-321
16-322
16-323
16-324
16-325
16-326
16-327
16-328
16-329
16-330
16-331
16-332
16-333
16-334
16-335
16-336
16-337
16-338
16-339
16-340
16-341
Offset 264h: DDRIOMC1 - DDRIO Mode Register Control Register 1 ....................... 642
Legoverride details ........................................................................................... 644
Legoverride - Gray code .................................................................................... 644
Offset 268h: DDRIOMC2 - DDRIO Mode Control Register 2 .................................... 645
Mapping of DQ and DQS/# byte lanes to WL_CNTL[4:0] CSR’s ............................... 646
Offset 284h: WL_CNTL[4:0] - Write Levelization Control Register .......................... 647
Delay of DQ/DQS ............................................................................................ 648
Offset 298h: WDLL_MISC - DLL Miscellaneous Control........................................... 649
Bus 0, Device 1, Function 0: Summary of EDMA Configuration Registers Mapped Through
EDMALBAR Memory BAR ................................................................................... 652
Offset 00h: CCR0 - Channel 0 Channel Control Register ....................................... 653
Offset 04h: CSR0 - Channel 0 Channel Status Register ........................................ 656
Offset 08h: CDAR0 - Channel 0 Current Descriptor Address Register ...................... 657
Offset 0Ch: CDUAR0 - Channel 0 Current Descriptor Upper Address Register .......... 658
Offset 10h: SAR0 - Channel 0 Source Address Register ....................................... 658
Offset 14h: SUAR0 - Channel 0 Source Upper Address Register ............................. 659
Offset 18h: DAR0 - Channel 0 Destination Address Register ................................. 659
Offset 1Ch: DUAR0 - Channel 0 Destination Upper Address Register ....................... 660
Offset 20h: NDAR0 - Channel 0 Next Descriptor Address Register ......................... 661
Offset 24h: NDUAR0 - Channel 0 Next Descriptor Upper Address Register .............. 662
Offset 28h: TCR0 - Channel 0 Transfer Count Register ......................................... 662
Offset 2Ch: DCR0 - Channel 0 Descriptor Control Register ................................... 663
Offset 40h: CCR1 - Channel 1 Channel Control Register ........................................ 665
Offset 44h: CSR1 - Channel 1 Channel Status Register ......................................... 665
Offset 48h: CDAR1 - Channel 1 Current Descriptor Address Register ..................... 665
Offset 4Ch: CDUAR1 - Channel 1 Current Descriptor Upper Address Register ........... 666
Offset 50h: SAR1 - Channel 1 Source Address Register ....................................... 666
Offset 54h: SUAR1 - Channel 1 Source Upper Address Register ............................. 666
Offset 58h: DAR1 - Channel 1 Destination Address Register ................................. 667
Offset 5Ch: DUAR1 - Channel 1 Destination Upper Address Register ....................... 667
Offset 60h: NDAR1 - Channel 1 Next Descriptor Address Register .......................... 667
Offset 64h: NDUAR1 - Channel 1 Next Descriptor Upper Address Register ............... 668
Offset 68h: TCR1 - Channel 1 Transfer Count Register ......................................... 668
Offset 6Ch: DCR1 - Channel 1 Descriptor Control Register ................................... 668
Offset 80h: CCR2 - Channel 2 Channel Control Register ........................................ 669
Offset 84h: CSR2 - Channel 2 Channel Status Register ........................................ 669
Offset 88h: CDAR2: Channel 2 Current Descriptor Address Register ...................... 669
Offset 8Ch: CDUAR2 - Channel 2 Current Descriptor Upper Address Register .......... 670
Offset 90h: SAR2 - Channel 2 Source Address Register ....................................... 670
Offset 94h: SUAR2 - Channel 2 Source Upper Address Register ............................ 670
Offset 98h: DAR2 - Channel 2 Destination Address Register ................................. 671
Offset 9Ch: DUAR2 - Channel 2 Destination Upper Address Register ...................... 671
Offset A0h: NDAR2 - Channel 2 Next Descriptor Address Register ......................... 671
Offset A4h: NDUAR2 - Channel 2 Next Descriptor Upper Address Register .............. 672
Offset A8h: DCR2 - Channel 2Transfer Control Register ....................................... 672
Offset ACh: DCR2 - Channel 2 Descriptor Control Register ................................... 672
Offset C0h: CCR3 - Channel 3 Channel Control Register ...................................... 673
Offset C4h: CSR3 - Channel 3 Channel Status Register ........................................ 673
Offset C8h: CDAR3 - Channel 3 Current Descriptor Address Register ..................... 673
Offset CCh: CDUAR3 - Channel 3 Current Descriptor Upper Address Register .......... 674
Offset D0h: SAR3 - Channel 3 Source Address Register ........................................ 674
Offset D4h: SUAR3 - Channel 3 Source Upper Address Register ............................ 674
Offset D8h: DAR3 - Channel 3 Destination Address Register ................................. 675
Offset DCh: DUAR3 - Channel 3 Destination Upper Address Register ..................... 675
Offset E0h: NDAR3 - Channel 3 Next Descriptor Address Register .......................... 675
August 2009
Order Number: 320066-003US
Intel® EP80579 Integrated Processor Product Line Datasheet
65
Contents
16-342
16-343
16-344
16-345
16-346
16-347
16-348
16-349
16-350
16-351
16-352
16-353
16-354
16-355
16-356
17-1
17-2
17-3
17-4
17-5
17-6
17-7
17-8
17-9
17-10
17-11
17-12
17-13
17-14
17-15
17-16
17-17
17-18
17-19
17-20
17-21
17-22
17-23
17-24
17-25
17-26
17-27
17-28
17-29
17-30
18-1
18-2
18-3
18-4
18-5
18-6
Offset E4h: NDUAR3 - Channel 3 Next Descriptor Upper Address Register ............... 676
Offset E8h: TCR3 - Channel 3 Transfer Count Register .......................................... 676
Offset ECh: DCR3 - Channel 3 Descriptor Control Register .................................... 677
Offset 100h: DCGC - EDMA Controller Global Command ....................................... 677
Offset 104h: DCGS - EDMA Controller Global Status ............................................ 678
Bus 0, Device 0, Function 0: Summary of IMCH Configuration Registers Mapped Through
NSIBAR Memory BAR ........................................................................................ 679
Offset 00h: SNSIVCECH - NSI Virtual Channel Enhanced Capability Header Register . 680
Offset 04h: NSIPVCCAP1 - NSI Port VC Capability Register 1 ................................ 680
Offset 08h: NSIPVCCAP2 - Port VC Capability Register 2 ...................................... 681
Offset 0Ch: NSIPVCCTL - NSI Port VC Control Register ........................................ 682
Offset 10h: NSIVC0RCAP - NSI VC0 Resource Capability Register .......................... 682
Offset 14h: NSIVC0RCTL - NSI VC0 Resource Control Register .............................. 683
Offset 1Ah: NSIVC0RSTS - NSI VC0 Resource Status Register .............................. 684
Offset 80h: NSIRCILCECH - NSI Root Complex Internal Link Control Enhanced Capability
Header Register .............................................................................................. 684
Offset 84h: NSILCAP - NSI Link Capabilities Register ........................................... 685
Bus 0, Device 31, Function 0: Summary of Root Complex Configuration Registers Mapped
Through RCBA Memory BAR ............................................................................... 689
RCBA Base Address Registers in the IA F View ...................................................... 690
Offset 0000h: VCH - Virtual Channel Capability Header Register ............................. 691
Offset 0004h: VCAP1 - Virtual Channel Capability 1 Register .................................. 691
Offset 0008h: VCAP2 - Virtual Channel Capability 2 Register .................................. 692
Offset 000Ch: PVC - Port Virtual Channel Control Register ..................................... 692
Offset 000Eh: PVS -Port Virtual Channel Status Register ........................................ 693
Offset 0010h: V0CAP - Virtual Channel 0 Resource Capability Register ..................... 693
Offset 0014h: V0CTL - Virtual Channel 0 Resource Control Register ......................... 694
Offset 001Ah: V0STS - Virtual Channel 0 Resource Status Register.......................... 695
Offset 0100h: RCTCL - Root Complex Topology Capabilities List Register .................. 696
Offset 0104h: ESD - Element Self Description Register .......................................... 696
Offset 0110h: ULD - Upstream Link Description Register ........................................ 697
Offset 0118h: ULBA - Upstream Link Base Address Register ................................... 697
Offset 01A0h: ILCL - Internal Link Capabilities List Register.................................... 698
Offset 01A4h: LCAP - Link Capabilities Register .................................................... 698
Offset 01A8h: LCTL - Link Control Register .......................................................... 699
Offset 01AAh: LSTS - Link Status Register .......................................................... 700
Offset 3000h: TCTL - TCO Control Register .......................................................... 700
Offset 3100h: D31IP - Device 31 Interrupt Pin Register ........................................ 701
Offset 3108h: D29IP - Device 29 Interrupt Pin Register ........................................ 702
Offset 3140h: D31IR - Device 31 Interrupt Route Register .................................... 702
Offset 3144h: D29IR - Device 29 Interrupt Route Register .................................... 703
Offset 31FFh: OIC - Other Interrupt Control Register ............................................ 704
Offset 3400h: RC - RTC Configuration Register ..................................................... 704
Offset 3404h: HPTC - High Performance Precision Timer Configuration Register ........ 705
Offset 3410h: GCS - General Control and Status Register ...................................... 706
Offset 3414h: BUC - Backed Up Control Register .................................................. 708
Offset 3418h: FD - Function Disable Register ....................................................... 709
Offset 341Ch: PRC - Power Reduction Control Register Clock Gating ....................... 711
Bus 0, Device 31, Function 0: Summary of TCO Configuration Registers Mapped Through
TCOBASE I/O BAR“ ........................................................................................... 714
Offset 00h: TRLD - TCO Timer Reload and Current Value Register ......................... 715
Offset 02h: TDI - TCO Data In Register .............................................................. 715
Offset 03h: TDO - TCO Data Out Register .......................................................... 716
Offset 04h: TSTS1 - TCO 1 Status Register ........................................................ 716
Offset 06h: TSTS2 - TCO 2 STS Register ............................................................. 718
Intel® EP80579 Integrated Processor Product Line Datasheet
66
August 2009
Order Number: 320066-003US
Contents
18-7
18-8
18-9
18-10
18-11
18-12
18-13
18-14
18-15
19-1
19-2
19-3
19-4
19-5
19-6
19-7
19-8
19-9
19-10
19-11
19-12
19-13
19-14
19-15
19-16
19-17
19-18
19-19
19-20
19-21
19-22
19-23
19-24
19-25
19-26
19-27
19-28
19-29
19-30
19-31
19-32
19-33
20-1
20-2
20-3
20-4
20-5
20-6
20-7
20-8
20-9
Offset 08h: TCTL1 - TCO 1 Control Register ....................................................... 720
Offset 0Ah: TCTL2 - TCO 2 Control Register ....................................................... 721
Offset 0Ch: TMSG[1-2] - TCO MESSAGE Register ............................................... 721
Offset 0Eh: TWDS - TCO Watchdog Status Register ............................................ 722
Offset 10h: LE - Legacy Elimination Register ...................................................... 722
Offset 12h: TTMR - TCO Timer Initial Value Register ........................................... 723
Event Transitions that Cause Messages .............................................................. 728
SMBus Message Format .................................................................................... 731
Message Address Byte ...................................................................................... 732
Bus 0, Device 31, Function 0: Summary of LPC Interface PCI Configuration Registers 733
Offset 00h: ID: Vendor Identification Register ...................................................... 734
Offset 04h: CMD: Device Command Register ....................................................... 735
Offset 06h: STS: Status Register ....................................................................... 736
Offset 08h: RID: Revision ID Register ................................................................. 737
Offset 09h: CC: Class Code Register .................................................................. 737
Offset 0Dh: MLT: Master Latency Timer Register ................................................. 737
Offset 0Eh: HTYPE: Header Type Register ........................................................... 738
Offset 2Ch: SID: Subsystem Identifiers Register .................................................. 738
Offset 40h: ABASE: ACPI Base Address Register .................................................. 739
Offset 44h: ACTL: ACPI Control Register ............................................................ 739
Offset 48h: GBA: GPIO Base Address Register ..................................................... 740
Offset 4Ch: GC: GPIO Control Register ............................................................... 741
Offset 60h: PARC: PIRQA Routing Control Register ............................................. 741
Offset 61h: PBRC: PIRQB Routing Control Register .............................................. 742
Offset 62h: PCRC: PIRQC Routing Control Register .............................................. 742
Offset 63h: PDRC: PIRQDQ Routing Control Register ............................................ 743
Offset 64h: SCNT: Serial IRQ Control Register...................................................... 744
Offset 68h: PERC: PIRQEQ Routing Control Register ............................................ 745
Offset 69h: PFRC: PIRQF Routing Control Register .............................................. 745
Offset 6Ah: PGRC: PIRQG Routing Control Register ............................................. 746
Offset 6Bh: PHRC: PIRQH Routing Control Register ............................................. 747
Offset 80h: IOD: I/O Decode Ranges Register ..................................................... 747
Offset 82h: IOE: I/O Enables Register ................................................................ 749
Offset 84h: LG1: LPC Generic Decode Range 1 Register ........................................ 750
Offset 88h: LG2: LPC Generic Decode Range 2 Register ........................................ 751
Offset D0h: FS1: FWH ID Select 1 Register ......................................................... 752
Offset D4h: FS2: FWH ID Select 2 Register ......................................................... 753
Offset D8h: FDE: FWH Decode Enable Register .................................................... 754
Offset DCh: BC: BIOS Control Register ............................................................... 756
Offset F0h: RCBA: Root Complex Base Address Register ....................................... 757
Offset F8h: MANID: Manufacturer ID Register .................................................... 757
LPC Cycle Types Supported .............................................................................. 759
Summary of LPC DMA Registers Mapped in I/O Space ........................................... 764
0000h (IO) Base Address Registers in the IA F1 View ............................................ 764
0000h (IO) Base Address Registers in the IA F2 View ............................................ 765
Offset 00h: DMA_BCA[0-3] - DMA Base and Current Address
Registers for Channels 0-3 .............................................................................. 766
Offset C4h: DMA_BCA[5-7] - DMA Base and Current Address
Registers for Channels 5-7 .............................................................................. 767
Offset 01h: DMA_BCC[0-3] - DMA Base and Current Count
Registers for Channels 0-3 ................................................................................ 768
Offset C6h: DMA_BCC[5-7] - DMA Base and Current Count
Registers for Channels 5-7 ................................................................................ 769
Offset 08h: DMA_COMMAND - DMA Command Register ........................................ 770
Offset 87h: DMA_MPL[0-3] - DMA Memory Low Page Registers for Channels 0-3 ...... 771
August 2009
Order Number: 320066-003US
Intel® EP80579 Integrated Processor Product Line Datasheet
67
Contents
20-10
20-11
20-12
20-13
20-14
20-15
20-16
20-17
20-18
20-19
21-1
21-2
21-3
21-4
21-5
21-6
21-7
21-8
21-9
21-10
21-11
21-12
21-13
21-14
21-15
21-16
22-1
22-2
22-3
22-4
22-5
22-6
22-7
22-8
22-9
22-10
22-11
23-1
23-2
23-3
23-4
23-5
23-6
23-7
23-8
23-9
23-10
23-11
23-12
23-13
23-14
23-15
Offset 8Bh: DMA_MPL[5-7]: DMA Memory Low Page Registers for Channels 5-7 ....... 771
Offset 08h: DMA_STATUS - DMA Status Register ................................................ 772
Offset 0Ah: DMA_WSM - DMA Write Single Mask Register ..................................... 773
Offset 0Bh: DMA_CHM - DMA Channel Mode Register .......................................... 774
Offset 0Ch: DMA_CBP - DMA Clear Byte Pointer Register ....................................... 775
Offset 0Dh: DMA_MC - DMA Master Clear Register ............................................... 775
Offset 0Eh: DMA_CM - DMA Clear Mask Register ................................................. 776
Offset 0Fh: DMA_WAM - DMA Write All Mask Register .......................................... 777
DMA Channel Priority ........................................................................................ 778
Address Shifting in 16-bit DMA Transfers ............................................................. 779
SPI Pin Interface .............................................................................................. 785
GPIO Boot Source Selection ............................................................................... 786
SPI Cycle Timings ............................................................................................. 789
Bus 0, Device 31, Function 0, PCI Registers Mapped Through RCBA Bar ................... 789
Offset 3020h: SPIS - SPI Status ........................................................................ 790
Offset 3022h: SPIC - SPI Control ....................................................................... 791
Offset 3024h: SPIA - SPI Address ..................................................................... 792
Offset 3028h: SPID0 - SPI Data 0 ..................................................................... 792
Offset 3030h, 3038h, 3040h, 3048h, 3050h, 3058h, 3060h: SPI[0-6] SPI Data [0-6] ................................................................................................ 793
Offset 3070h: BBAR - BIOS Base Address .......................................................... 793
Offset 3074h: PREOP - Prefix Opcode Configuration ............................................. 794
Offset 3076h: OPTYPE - Op Code Type .............................................................. 794
Offset 3078h: OPMENU - OPCODE Menu Configuration .......................................... 795
Offset 3080h: PBR0 - Protected BIOS Range #0 .................................................. 796
Byte Enable Handling on Direct Memory Reads ..................................................... 798
Flash Protection Mechanism Summary ................................................................. 800
GPIO Pin’s Alternative Function........................................................................... 804
GPIO Summary Table ....................................................................................... 805
Bus 0, Device 31, Function 0: Summary of General Purpose I/O Configuration Registers
Mapped Through GBA BAR IO BAR ...................................................................... 806
Offset 00h: GPIO_USE_SEL1 - GPIO Use Select 1 {31:0} Register ........................ 807
Offset 04h: GP_IO_SEL1 - GPIO Input/Output Select 1 {31:0} Register ................. 808
Offset 0Ch: GP_LVL1 - GPIO Level 1 for Input or Output {31:0} Register ............... 809
Offset 18h: GPO_BLINK - GPIO Blink Enable Register .......................................... 810
Offset 2Ch: GPI_INV - GPIO Signal Invert Register .............................................. 812
Offset 30h: GPIO_USE_SEL2 - GPIO Use Select 2 {63:32} Register ....................... 813
Offset 34h: GP_IO_SEL2 - GPIO Input/Output Select 2 {63:32} Register ............... 813
Offset 38h: GP_LVL2 - GPIO Level for Input or Output 2 {63:32} Register ............. 814
Bus 0, Device 31, Function 2: Summary of SATA Controller PCI Configuration
Registers ......................................................................................................... 817
Offset 00h: ID – Identifiers Register.................................................................... 819
Offset 04h: CMD - Command Register ................................................................ 819
Offset 06h: STS - Device Status Register ............................................................ 820
Offset 08h: RID - Revision ID Register................................................................. 821
Programming Interface, DID and CC.SCC Register Value Definitions ........................ 822
Programming Interface when CC.SCC = “01h” ...................................................... 822
Programming Interface when CC.SCC = “06h” ...................................................... 823
Offset 0Ah: CC - Class Code Register .................................................................. 823
Offset 0Dh: MLT – Master Latency Timer Register ................................................. 823
Offset 10h: PCMDBA – Primary Command Block Base Address Register.................... 824
Offset 14h: PCTLBA – Primary Control Block Base Address Register ......................... 824
Offset 18h: SCMDBA – Secondary Command Block Base Address Register................ 825
Offset 1Ch: SCTLBA – Secondary Control Block Base Address Register..................... 825
Offset 20h: LBAR – Legacy Bus Master Base Address Register when SCC is SATA
Intel® EP80579 Integrated Processor Product Line Datasheet
68
August 2009
Order Number: 320066-003US
Contents
23-16
23-17
23-18
23-19
23-20
23-21
23-22
23-23
23-24
23-25
23-26
23-27
23-28
23-29
23-30
23-31
23-32
23-33
23-34
23-35
23-36
23-37
23-38
23-39
23-40
23-41
23-42
23-43
23-44
23-45
23-46
23-47
23-48
23-49
23-50
23-51
23-52
23-53
23-54
23-55
23-56
23-57
23-58
23-59
23-60
23-61
23-62
23-63
23-64
23-65
23-66
23-67
with AHCI PI.................................................................................................... 826
Offset 24h: ABAR – AHCI Base Address Register................................................... 826
Offset 2Ch: SS - Sub System Identifiers Register.................................................. 827
Offset 34h: CAP – Capabilities Pointer Register..................................................... 827
Offset 3Ch: INTR - Interrupt Information Register ................................................ 828
Offset 40h: PTIM – Primary Timing Register ......................................................... 829
Offset 44h: D1TIM – Device 1 IDE Timing Register ............................................... 830
Offset 48h: SYNCC – Synchronous DMA Control Register ....................................... 831
Offset 4Ah: SYNCTIM – Synchronous DMA Timing Register .................................... 832
Offset 54h: IIOC – IDE I/O Configuration Register .............................................. 833
Offset 70h: PID – PCI Power Management Capability ID Register ............................ 834
Offset 72h: PC – PCI Power Management Capabilities Register ............................... 834
Offset 74h: PMCS – PCI Power Management Control And Status Register ............... 835
Offset 80h: MID – Message Signaled Interrupt Identifiers Register .......................... 836
Offset 82h: MC – Message Signaled Interrupt Message Control Register................... 837
Offset 84h: MA – Message Signaled Interrupt Message Address Register.................. 838
Offset 88h: MD – Message Signaled Interrupt Message Data Register ...................... 838
Offset 90h: MAP – Port Mapping Register............................................................. 839
Offset 92h: PCS – Port Control and Status Register............................................... 840
Offset A8h: SATACR0 – Serial ATA Capability Register 0 ........................................ 841
Offset ACh: SATACR1 – Serial ATA Capability Register 1 ........................................ 841
Offset C0h: ATC – APM Trapping Control Register ................................................. 842
Offset C4h: ATS – ATM Trapping Status Register .................................................. 843
Offset D0h: SP – Scratch Pad Register ................................................................ 844
Offset E0h: BFCS – BIST FIS Control/Status Register ............................................ 844
Offset E4h: BFTD1 – BIST FIS Transmit Data 1 Register ........................................ 846
Offset E8h: BFTD2 – BIST FIS Transmit Data 2 Register ........................................ 846
Offset F8h: MANID – Manufacturing ID Register ................................................. 847
Bus 0, Device 31, Function 2: Summary of SATA Controller Configuration Registers
Mapped Through LBAR I/O BAR.......................................................................... 848
Offset 00h: PCMD – Primary Command Register ................................................. 848
Offset 02h: PSTS – Primary Status Register ....................................................... 849
Offset 04h: PDTP – Primary Descriptor Table Pointer Register ............................... 849
Offset 10h: INDEX – AHCI Index Register ............................................................ 850
Offset 14h: DATA – AHCI Data Register............................................................... 851
Bus 0, Device 31, Function 2: Summary of SATA Controller Configuration Registers
Mapped Through ABAR Memory BAR ................................................................... 852
Offset 00h: HCAP – HBA Capabilities Register ..................................................... 853
Offset 04h: GHC – Global HBA Control Register .................................................... 855
Offset 08h: IS – Interrupt Status Register .......................................................... 856
Offset 0Ch: PI – Ports Implemented Register ....................................................... 856
Offset 10h: VS – AHCI Version Register............................................................... 857
Offset A0h: SGPO -SPGIO Control Register .......................................................... 857
Offset 100h: PxCLB[0-1] – Port [0-1] Command List Base Address Register .......... 858
Offset 104h: PxCLBU[0-1] – Port [0-1] Command List Base Address Register ......... 858
Offset 108h: PxFB[0-1] – Port [0-1] FIS Base Address Register ............................ 859
Offset 10Ch: PxFBU[0-1] – Port [0-1] FIS Base Address Upper 32-bits Register ...... 859
Offset 110h: PxIS[0-1] – Port [0-1] Interrupt Status Register ............................... 860
Offset 114h: PxIE[0-1] – Port [0-1] Interrupt Enable Register ............................... 861
Offset 118h: PxCMD[0-1] – Port [0-1] Command Register .................................... 863
Port Interface Registers for Ports[1:0] ................................................................ 866
Offset 120h: PxTFD[0-1] – Port [0-1] Task File Data Register .............................. 866
Offset 124h: PxSIG[0-1] – Port [0-1] Signature Register ..................................... 867
Offset 128h: PxSSTS[0-1] – Port [0-1] Serial ATA Status Register ........................ 868
Offset 12Ch: PxSCTL[0-1] – Port [0-1] Serial ATA Control Register ........................ 869
August 2009
Order Number: 320066-003US
Intel® EP80579 Integrated Processor Product Line Datasheet
69
Contents
23-68
23-69
23-70
23-71
23-72
23-73
23-74
23-75
23-76
23-77
24-1
24-2
24-3
24-4
24-5
24-6
24-7
24-8
24-9
24-10
24-11
24-12
24-13
24-14
24-15
24-16
24-17
24-18
24-19
24-20
24-21
24-22
24-23
24-24
24-25
24-26
24-27
24-28
24-29
24-30
24-31
24-32
24-33
24-34
24-35
24-36
24-37
24-38
24-39
24-40
24-41
24-42
24-43
Offset 130h: PxSERR[0-1] – Port [0-1] Serial ATA Error Register ........................... 870
Offset 134h: PxSACT[0-1] – Port [0-1] Serial ATA Active Register ......................... 872
Offset 138h: PxCI[0-1] – Port [0-1] Command Issue Register ................................ 872
Offset 13Ch: PxSNTF[0-1] – Port [0-1] SNotification Register ............................... 873
Errors During Non-DATA FIS Reception................................................................ 877
Errors During PIO Data FIS Reception.................................................................. 877
Errors During DMA Data FIS Reception ................................................................ 877
Errors during unknown FIS type3 reception .......................................................... 878
Errors during FIS transmission ........................................................................... 878
MSI vs. PCI IRQ Actions .................................................................................... 882
SMBus signals .................................................................................................. 895
Bus 0, Device 31, Function 3: Summary of SMBus Controller PCI
Configuration Registers ..................................................................................... 896
Offset 00h: VID: Vendor ID Register .................................................................. 897
Offset 02h: DID: Device ID Register .................................................................. 897
Offset 04h: CMD: Command Register ................................................................ 897
Offset 06h: DS – Device Status Register ............................................................ 898
Offset 08h: RID: Revision ID Register ................................................................ 899
Offset 09h: PI: Programming Interface Register .................................................. 900
Offset 0Ah: SCC: Sub Class Code Register ......................................................... 900
Offset 0Bh: BCC: Base Class Code Register ........................................................ 900
Offset 20h: SM_BASE: SMB Base Address Register .............................................. 901
Offset 2Ch: SVID: SVID Register ...................................................................... 901
Offset 2Eh: SID: Subsystem Identification Register ............................................. 902
Offset 3Ch: INTLN: Interrupt Line Register ......................................................... 902
Offset 3Dh: NTPN: Interrupt Pin Register ............................................................ 903
Offset 40h: HCFG: Host Configuration Register ................................................... 903
Offset F8h: MANID: Manufacturer ID Register ..................................................... 904
Bus 0, Device 31, Function 3: Summary of SMBus Controller Configuration Registers
Mapped Through SM_BASE I/O BAR .................................................................... 905
Offset 00h: HSTS: Host Status Register ............................................................. 906
Offset 02h: HCTL: Host Control Register ............................................................ 908
Offset 03h: HCMD: Host Command Register ........................................................ 912
Offset 04h: TSA: Transmit Slave Address Register .............................................. 912
Offset 05h: HD0: Data 0 Register ..................................................................... 913
Offset 06h: HD1: Data 1 Register ..................................................................... 913
Offset 07h: HBD: Host Block Data Register ......................................................... 914
Offset 08h: PEC: Packet Error Check Data Register ............................................. 915
Offset 0Ch: AUXS: Auxiliary Status Register ....................................................... 915
Offset 0Dh: AUXC: Auxiliary Control Register ...................................................... 916
Offset 0Eh: SMLC: SMLINK_PIN_CTL Register ...................................................... 916
Offset 0Fh: SMBC: SMBUS_PIN_CTL Register ...................................................... 917
Quick Protocol .................................................................................................. 919
Send/Receive Byte Protocol without PEC .............................................................. 919
PEC Send/Receive Order.................................................................................... 919
Write Byte/Word Protocol Without PEC ................................................................ 920
PEC Bit Order .................................................................................................. 920
Read Byte/Word Protocol without PEC ................................................................. 921
Read Byte/Word Protocol with PEC ...................................................................... 921
Process Call Protocol without PEC........................................................................ 922
Process Call Protocol with PEC ........................................................................... 923
Block Read/Write Protocol without PEC ............................................................... 924
Block Read/Write Protocol with PEC .................................................................... 925
Block Write-Block Read Process Call Protocol with/without PEC .............................. 927
Summary of Enables for SMBALERT# .................................................................. 929
Intel® EP80579 Integrated Processor Product Line Datasheet
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August 2009
Order Number: 320066-003US
Contents
24-44
24-45
24-46
24-47
24-48
24-49
24-50
24-51
24-52
24-53
24-54
24-55
24-56
24-57
24-58
24-59
25-1
25-2
25-3
25-4
25-5
25-6
25-7
25-8
25-9
25-10
25-11
25-12
25-13
25-14
25-15
25-16
25-17
25-18
25-19
25-20
25-21
25-22
25-23
25-24
25-25
25-26
25-27
25-28
25-29
25-30
25-31
25-32
25-33
26-1
26-2
26-3
Summary of Enables for SMBus Slave Write, and SMBus Host Events ...................... 929
Summary of Enables for the Host Notify Command ............................................... 930
Bus 0, Device 31, Function 3, Slave PCI Registers Mapped Through SM_Base (IO) .... 930
Offset 09h: RSA: Receive Slave Address Register ............................................... 931
Offset 0Ah: SD: Slave Data Register ................................................................. 931
Offset 10h: SSTS: Slave Status Register ............................................................ 932
Offset 11h: SCMD: Slave Command Register ..................................................... 932
Offset 14h: NDA: Notify Device Address Register ................................................ 933
Offset 16h: NDLB: Notify Data Low Byte Register ............................................... 934
Offset 17h: NDHB: Notify Data High Byte Register .............................................. 934
Slave Write Cycle Format .................................................................................. 935
Slave Write Registers........................................................................................ 936
Command Types ............................................................................................. 936
Slave Read Cycle Format................................................................................... 937
Data Values for Slave Read Registers ................................................................. 937
Host Notify Protocol ......................................................................................... 939
Bus 0, Device 29, Functions 0, Summary of USB (1.1) Controller PCI Configuration
Registers ........................................................................................................ 941
ID - Identifiers Register ................................................................................... 942
PCICMD - Command Register ........................................................................... 942
PCISTS - Device Status Register ....................................................................... 943
RID - Revision ID Register ............................................................................... 944
SUBC - Sub Class Code Register ....................................................................... 945
BCC - Base Class Code Register ....................................................................... 945
MLT - Master Latency Timer Register ................................................................ 945
HDR - Header Type Register ............................................................................ 946
USBIOBAR - Base Address Register ................................................................... 946
USBx_SVID - USB Subsystem Vendor ID Register ............................................... 947
USBx_SID - USB Subsystem ID Register ........................................................... 947
INTL - Interrupt Line Register .......................................................................... 948
INTP - Interrupt Pin Register ............................................................................ 948
SBRN - Serial Bus Release Number Register ....................................................... 948
USBLKMCR - USB Legacy Keyboard/Mouse Control Register ................................. 949
USBREN - USB Resume Enable Register ............................................................ 951
USBCWP - USB Core Well Policy Register ........................................................... 951
MANID - Manufacturer ID Register .................................................................... 952
Summary of USB (1.1) Controller Configuration Registers Mapped Through
USBIOBAR I/O BAR .......................................................................................... 953
USBCMD: USB Command Register .................................................................... 954
Run/Stop, Debug Bit Interaction SWDBG (Bit 5), Run/Stop (Bit 0) Operation............ 956
USBSTS: USB Status Register .......................................................................... 957
USBINTR: USB Interrupt Enable Register ........................................................... 959
FRNUM: Frame Number Register ...................................................................... 959
FRBASEADD: Frame List Base Address Register .................................................. 960
SOFMOD: Start of Frame Modify Register .......................................................... 961
PSCR - Port Status and Control Register ............................................................ 962
Queue Advance Criteria..................................................................................... 968
USB Schedule List Traversal Decision Table ......................................................... 969
Data Field ....................................................................................................... 971
Bits Maintained in Low Power States ................................................................... 975
USB Legacy Keyboard/Mouse Control Register Bit Implementation ......................... 975
USB 1.1 and USB 2.0 Comparison ..................................................................... 977
Bus 0, Device 29, Function 7: Summary of USB (2.0) Controller PCI Configuration
Registers ........................................................................................................ 978
Offset 00h: VID - Vendor ID Register ................................................................ 979
August 2009
Order Number: 320066-003US
Intel® EP80579 Integrated Processor Product Line Datasheet
71
Contents
26-4
26-5
26-6
26-7
26-8
26-9
26-10
26-11
26-12
26-13
26-14
26-15
26-16
26-17
26-18
26-19
26-20
26-21
26-22
26-23
26-24
26-25
26-26
26-27
26-28
26-29
26-30
26-31
26-32
26-33
26-34
26-35
26-36
26-37
26-38
26-39
26-40
26-41
26-42
26-43
26-44
26-45
26-46
26-47
26-48
26-49
26-50
26-51
26-52
26-53
26-54
26-55
26-56
26-57
Offset 02h: DID - Device Identification Register .................................................... 979
Offset 04h: CMD - Command Register ............................................................... 980
Offset 06h: DSR - Device Status Register ........................................................... 981
Offset 08h: RID - Revision ID Register................................................................. 983
Offset 09h: PI - Programming Interface Register................................................... 983
Offset 0Ah: SCC - Sub Class Code Register .......................................................... 983
Offset 0Bh: BCC - Base Class Code Register ......................................................... 984
Offset 0Dh: MLT - Master Latency Timer Register .................................................. 984
Offset 10h: MBAR - Memory Base Address Register ............................................... 985
Offset 2Ch: SSVID - USB 2.0 Subsystem Vendor ID Register .................................. 985
Offset 2Eh: SSID - USB 2.0 Subsystem ID Register ............................................... 986
Offset 34h: CAP_PTR - Capabilities Pointer Register............................................... 986
Offset 3Ch: ILINE - Interrupt Line Register........................................................... 987
Offset 3Dh: IPIN - Interrupt Pin Register.............................................................. 987
Offset 50h: PM_CID - PCI Power Management Capability ID Register ....................... 987
Offset 51h: PM_NEXT - Next Item Pointer #1 Register ........................................... 988
Offset 52h: PM_CAP - Power Management Capabilities Register ............................ 989
Offset 54h: PM_CS - Power Management Control/Status Register .......................... 990
Offset 58h: DP_CID - Debug Port Capability ID Register......................................... 991
Offset 59h: DP_NEXT - Next Item Pointer #2 Register ........................................... 991
Offset 5Ah: DP_BASE - Debug Port Base Offset Register ........................................ 991
Offset 60h: SBRN - Serial Bus Release Number Register ...................................... 992
Offset 61h: FLA - Frame Length Adjustment Register ........................................... 992
Offset 62h: PWC - Port Wake Capability Register ................................................. 993
Offset 64h: CUO - Classic USB Override Register .................................................. 994
Offset 68h: ULSEC - USB 2.0 Legacy Support Extended Capability Register ............ 994
Offset 6Ch: ULSCS - USB 2.0 Legacy Support Control/Status Register ................... 995
Offset 70h: ISU2SMI - Intel Specific USB 2.0 SMI Register ................................... 997
Offset 80h: AC - Access Control Register ............................................................ 999
Offset F8h: MANID - Manufacturer ID Register .................................................. 1000
Bus 0, Device 29, Function 7: Summary of USB (2.0) Controller Configuration Registers
Mapped Through MBAR Memory BAR ................................................................. 1001
Offset 00h: CAPLENGTH - Capability Length Register ........................................... 1002
Offset 02h: HCIVERSION - Host Controller Interface Version Number Register ........ 1003
Offset 04h: HCSPARAMS - Host Controller Structural Parameters Register ............ 1003
Offset 08h: HCCPARAMS - Host Controller Capability Parameters Register ............ 1004
Host Controller Operational Register Details Summary Table ................................ 1006
Offset 20h: USB2CMD - USB 2.0 Command Register ......................................... 1007
Offset 24h: USB2STS - USB 2.0 Status Register ................................................ 1009
Offset 28h: USB2INTR - USB 2.0 Interrupt Enable Register ................................ 1012
Offset 2Ch: FRINDEX - Frame Index Register ................................................... 1013
Offset 30h: CTRLDSSEGMENT - Control Data Structure Segment Register .............. 1014
Offset 34h: PERIODICLISTBASE - Periodic Frame List Base Address Register ........ 1014
Offset 38h: ASYNCLISTADDR - Current Asynchronous List Address Register ......... 1015
Offset 60h: CONFIGFLAG - Configure Flag Register ............................................ 1015
Offset 64h: PORTSC - Port N Status and Control Register .................................... 1016
HCRESET Bit Summary ................................................................................... 1021
Periodic DMA Engine Memory Reads ................................................................. 1022
Asynchronous DMA Engine Reads ..................................................................... 1025
Asynchronous DMA Engine Writes .................................................................... 1027
Host Interface Parity Errors ............................................................................. 1028
Effect of Resets on Port-Routing Logic ............................................................... 1035
Offset A0h: CNTL_STS - Control/Status Register ............................................... 1037
Offset A4h: USBPID - USB PIDs Register .......................................................... 1039
Offset A8h: DATABUF - Data Buffer Bytes 7:0 ................................................... 1039
Intel® EP80579 Integrated Processor Product Line Datasheet
72
August 2009
Order Number: 320066-003US
Contents
26-58
26-59
27-1
27-2
27-3
27-4
27-5
27-6
27-7
27-8
27-9
27-10
27-11
27-12
27-13
27-14
27-15
27-16
27-17
27-18
27-19
27-20
27-21
27-22
27-23
27-24
27-25
27-26
27-27
27-28
27-29
27-30
27-31
27-32
27-33
27-34
27-35
27-36
27-37
27-38
27-39
28-1
28-2
28-3
28-4
28-5
28-6
28-7
28-8
28-9
29-1
29-2
29-3
Offset B0h: CONFIG - Configuration Register ....................................................1040
Debug Port Behavior .......................................................................................1041
IMCH-IICH Messages ......................................................................................1046
Bus 0, Device 31, Function 0: Summary of LPC Interface Power Management PCI
Configuration Registers ....................................................................................1047
Offset A0h: GEN_PMCON_1 - General PM Configuration 1 Register ........................1047
Offset A2h: GEN_PMCON_2 - General PM Configuration 2 Register ........................1049
Offset A4h: GEN_PMCON_3 - General PM Configuration 3 Register .......................1051
Offset B8h: GPI_ROUT - GPI Routing Control Register .........................................1053
Summary of APM Registers Mapped in I/O Space.................................................1053
Offset B2h: APM_CNT - Advanced Power Management Control Port Register ...........1054
Offset B3h: APM_STS - Advanced Power Management Status Port Register .............1054
Bus 0, Device 31, Function 0: Summary of LPC Interface Power Management General
Configuration Registers Mapped Through PMBASE I/O BAR ...................................1055
Offset 00h: PM1_STS – Power Management 1 Status Register .............................1056
Offset 02h: PM1_EN - Power Management 1 Enables Register .............................1058
Offset 04h: PM1_CNT - Power Management 1 Control Register ............................1059
Offset 08h: PM1_TMR - Power Management 1 Timer Register ..............................1060
Offset 10h: PROC_CNT - Processor Control Register ...........................................1060
Offset 14h: LV2 - Level 2 Register ...................................................................1063
Offset 28h: GPE0_STS - General Purpose Event 0 Status Register ........................1063
Offset 2Ch: PMBASE_GPE0_EN - General Purpose Event 0 Enables Register ..........1067
Offset 30h: SMI_EN - SMI Control and Enable Register .......................................1068
Offset 34h: SMI_STS - SMI Status Register ......................................................1071
Offset 38h: ALT_GPI_SMI_EN - Alternate GPI SMI Enable Register .......................1073
Offset 3Ah: ALT_GPI_SMI_STS - Alternate GPI SMI Status Register .....................1074
Offset 44h: DEVTRAP_STS - DEVTRAP_STS Register ...........................................1074
Causes of SCI .................................................................................................1076
Causes of TCO SCI ..........................................................................................1076
Causes of SMI# .............................................................................................1077
Causes of TCO SMI#........................................................................................1078
Break Events .................................................................................................1079
C0→C2→C0 Timings .......................................................................................1082
Sleep State Output Conditions ..........................................................................1083
Sleep Types ...................................................................................................1084
Causes of Wake Events ...................................................................................1085
GPI Wake Events ............................................................................................1085
Transitions Due To Power Failure.......................................................................1086
Transitions Due to Power Button .......................................................................1088
Transitions Due to RI# Signal ...........................................................................1089
Write-Only Registers with Read Paths in Alternate Access Mode ............................1092
PIC Reserved Bits Return Values ......................................................................1093
Register Write Accesses in Alternate Access Mode................................................1094
IA-32 Core Interface Signal State ......................................................................1097
Summary of IA-32 Core Interface Registers Mapped in I/O Space ..........................1097
Offset 61h: NMI_STS_CNT - NMI Status and Control Register ..............................1098
Offset 70h: NMI_EN - NMI Enable (and Real Time Clock Index) Register ...............1099
Offset 92h: PORT92 - Fast A20 and Init Register ...............................................1100
Offset F0h: COPROC_ERR - Coprocessor Error Register ......................................1100
Offset CF9h: RST_CNT - Reset Control Register .................................................1101
INIT# Going Active .........................................................................................1102
NMI Sources...................................................................................................1103
I/O Registers ..................................................................................................1106
RTC (Standard) RAM Bank................................................................................1106
Summary of Real Time Clock Indexed Registers ..................................................1107
August 2009
Order Number: 320066-003US
Intel® EP80579 Integrated Processor Product Line Datasheet
73
Contents
29-4
29-5
29-6
29-7
30-1
30-2
30-3
30-4
30-5
30-6
30-7
30-8
30-9
30-10
30-11
30-12
30-13
30-14
30-15
30-16
30-17
30-18
30-19
30-20
30-21
30-22
30-23
30-24
30-25
30-26
30-27
30-28
30-29
30-30
31-1
31-2
31-3
31-4
31-5
31-6
31-7
31-8
32-1
32-2
32-3
32-4
32-5
32-6
32-7
32-8
33-1
33-2
33-3
33-4
33-5
Offset 0Ah: RTC_REGA - Register A (General Configuration) ............................... 1107
Offset 0Bh: RTC_REGB - Register B (General Configuration) ............................... 1109
Offset 0Ch: RTC_REGC - Register C (Flag Register) ........................................... 1110
Offset 0Dh: RTC_REGD - Register D (Flag Register) .......................................... 1111
Interrupt Options - 8259 Mode ......................................................................... 1115
Interrupt Options - APIC Mode.......................................................................... 1116
Signals Associated with Interrupt Logic .............................................................. 1117
8259 Core Connection .................................................................................... 1117
Summary of 8259 Interrupt Controller (PIC) Registers Mapped in I/O Space ........... 1118
ICW1[0-1] - Initialization Command Word 1 Register .......................................... 1119
ICW2[0-1] - Initialization Command Word 2 Register ......................................... 1120
MICW3 - Master Initialization Command Word 3 Register ................................... 1121
SICW3 - Slave Initialization Command Word 3 Register ..................................... 1121
ICW4[0-1] - Initialization Command Word 4 Register .......................................... 1122
OCW1[0-1]- Operational Control Word 1 (Interrupt Mask) Register ....................... 1122
OCW2[0-1] - Operational Control Word 2 Register .............................................. 1123
OCW3[0-1] - Operational Control Word 3 Register ............................................. 1124
ELCR1 - Master Edge/Level Control Register ..................................................... 1125
ELCR2 - Slave Edge/Level Control Register ....................................................... 1126
Interrupt Handling ......................................................................................... 1127
Content of Interrupt Vector Byte....................................................................... 1127
Interrupt Delivery Address Format ................................................................... 1134
Interrupt Delivery Data Format ........................................................................ 1134
Summary of APIC Registers Mapped in Memory Space“........................................ 1135
APIC_IDX - Index Register .............................................................................. 1135
APIC_DAT – Data Register ............................................................................. 1136
APIC_EOI - EOI Register ................................................................................ 1136
APIC Index Register Space............................................................................... 1137
Summary of APIC Indexed Registers ................................................................. 1137
APIC_ID – Identification Register ..................................................................... 1138
APIC_VS - Version Register ............................................................................ 1138
APIC_RTE[0-39] - Redirection Table Entry ........................................................ 1139
Stop Frame Definition ..................................................................................... 1143
Data Frame Format......................................................................................... 1144
SPKR Signal ................................................................................................... 1145
Summary of 8254 Timer Registers Mapped in I/O Space ...................................... 1145
Offset 43h: TCW - Timer Control Word Register .................................................. 1146
Offset 40h: TSB[0-2] - Interval Timer Status Byte Format Register ..................... 1147
Offset 40h: TCAP[0-2] - Interval Timer Counter Access Ports Register ................... 1148
Counter Operating Modes ............................................................................... 1149
Counter Latch Command ................................................................................ 1150
Read Back Command ..................................................................................... 1151
Summary of HPET Registers Mapped in Memory Space ........................................ 1154
Offset 000h: GCAP_ID - General Capabilities and ID Register ............................. 1155
Offset 010h: GEN_CONF - General Configuration Register ................................... 1156
Offset 020h: GINTR_STA - General Interrupt Status Register ............................... 1157
Offset 0F0h: MAIN_CNT - Main Counter Value Register ....................................... 1158
Offset 100h: HPTCC[0-2] - Timer n Configuration and Capabilities Register .......... 1159
Offset 108h: HPTCV[0-2] - Timer n Comparator Value Register ........................... 1163
Legacy Replacement Routing............................................................................ 1164
Address Map ................................................................................................. 1170
Supported LPC Cycle Types ............................................................................. 1170
I/O Sync Bits Description ................................................................................ 1171
UART Clock Divider Support ............................................................................ 1172
Baud Rate Example ........................................................................................ 1172
Intel® EP80579 Integrated Processor Product Line Datasheet
74
August 2009
Order Number: 320066-003US
Contents
33-6
33-7
33-8
33-9
33-10
33-11
33-12
33-13
33-14
33-15
33-16
33-17
33-18
33-19
33-20
33-21
33-22
33-23
33-24
33-25
33-26
33-27
33-28
33-29
33-30
33-31
33-32
33-33
33-34
33-35
33-36
33-37
33-38
33-39
33-40
33-41
34-1
34-2
34-3
34-4
34-5
34-6
34-7
34-8
34-9
34-10
34-11
34-12
34-13
34-14
34-15
34-16
34-17
34-18
UART Register/Signal Reset States ...................................................................1174
Summary of UART Registers in I/O Space (DLAB=0) ............................................1175
Summary of UART Registers in I/O Space (DLAB=1) ............................................1175
Summary of UART Timer registers in I/O space ...................................................1175
Internal Register Descriptions ..........................................................................1176
Offset 00h: RBR - Receive Buffer Register ........................................................1176
Offset 00h: THR - Transmit Holding Register .....................................................1177
Offset 01h: IER - Interrupt Enable Register .......................................................1177
Interrupt Conditions .......................................................................................1178
Offset 02h: IIR - Interrupt Identification Register ..............................................1179
Interrupt Identification Register Decode ............................................................1179
Offset 02h: FCR - FIFO Control Register ...........................................................1180
Offset 03h: LCR - Line Control Register ............................................................1182
Offset 04h: MCR - Modem Control Register .......................................................1184
Offset 05h: LSR - Line Status Register .............................................................1186
Offset 06h: MSR - Modem Status Register ........................................................1189
Offset 07h: SCR - Scratchpad Register .............................................................1190
Offset 00h: DLL - Programmable Baud Rate Generator Divisor Latch Register Low .1190
Offset 01h: DLH - Programmable Baud Rate Generator Divisor Latch Register High .1190
Summary of Watchdog Timer Registers in I/O Space............................................1194
Offset 00h: PV1R0 - Preload Value 1 Register 0 .................................................1194
Offset 01h: PV1R1 - Preload Value 1 Register 1 .................................................1195
Offset 02h: PV1R2 - Preload Value 1 Register 2 .................................................1195
Offset 04h: PV2R0 - Preload Value 2 Register 0 .................................................1196
Offset 05h: PV2R1 - Preload Value 2 Register 1 .................................................1196
Offset 06h: PV2R2 - Preload Value 2 Register 2 .................................................1197
Offset 08h: GISR - General Interrupt Status Register .........................................1197
Offset 0Ch: RR0 - Reload Register 0 ................................................................1198
Offset 0Dh: RR1 - Reload Register 1 ................................................................1199
Offset 10h: WDTCR - WDT Configuration Register ..............................................1199
Offset 18h: WDTLR - WDT Lock Register ..........................................................1201
SIW_SERIRQ Sampling Periods ........................................................................1204
Configuration Register Summary ......................................................................1207
Logical Device 4 (Serial Port 1) ........................................................................1210
Logical Device 5 (Serial Port 2) ........................................................................1211
Logical Device 6 (Watch Dog Timer) .................................................................1212
Bus 0, Device 4, Function 0: Summary of PCI-to-PCI Bridge PCI
Configuration Registers ....................................................................................1215
PCI-to-PCI Bridge PCI Header .........................................................................1216
Offset 0h: VID: Vendor Identification Register ...................................................1217
Offset 2h: DID: Device Identification Register ...................................................1217
Offset 4h: PCICMD: Device Command Register ..................................................1217
Offset 6h: PCISTS: PCI Device Status Register ..................................................1218
Offset 8h: RID: Revision ID Register ................................................................1219
Offset 9h: CC: Class Code Register ..................................................................1219
Offset Ch: CLS: Cacheline Size Register ...........................................................1219
Offset Dh: LT: Latency Timer Register ..............................................................1220
Offset Eh: HDR: Header Type Register .............................................................1220
Offset 10h: CSRBAR0: Control and Status Registers Base Address Register ...........1220
Offset 14h: CSRBAR1: Control and Status Registers Base Address Register ...........1221
Offset 18h: PBNUM: Primary Bus Number Register .............................................1221
Offset 19h: SECBNM: Secondary Bus Number Register .......................................1221
Offset 1Ah: SUBBNM: Subordinate Bus Number Register ....................................1222
Offset 1Bh: SECLT: Secondary Latency Timer Register .......................................1222
Offset 1Ch: IOB: I/O Base Register ..................................................................1222
August 2009
Order Number: 320066-003US
Intel® EP80579 Integrated Processor Product Line Datasheet
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Contents
34-19
34-20
34-21
34-22
34-23
34-24
34-25
34-26
34-27
34-28
34-29
34-30
34-31
34-32
34-33
34-34
34-35
34-36
34-37
35-1
35-2
35-3
35-4
35-5
35-6
35-7
35-8
35-9
35-10
35-11
35-12
35-13
35-14
35-15
35-16
35-17
35-18
35-19
35-20
35-21
35-22
35-23
35-24
35-25
35-26
35-27
35-28
35-29
35-30
35-31
35-32
35-33
Offset 1Dh: IOL: I/O Limit Register ................................................................. 1223
Offset 1Eh: SECSTA: Secondary Status Register ............................................... 1223
Offset 20h: MEMB: Memory Base Register ........................................................ 1224
Offset 22h: MEML: Memory Limit Register ........................................................ 1224
Offset 24h: PMASE: Prefetchable Memory Base Register .................................... 1225
Offset 26h: PMLIMIT: Prefetchable Memory Limit Register .................................. 1225
Offset 28h: PMBASU: Memory Limit Register .................................................... 1226
Offset 2Ch: PMLMTU: Prefetchable Memory Limit Upper Register ......................... 1226
Offset 30h: IOBU: I/O Base Upper Register ...................................................... 1227
Offset 32h: IOLU: I/O Limit Upper Register ...................................................... 1227
Offset 34h: CP: Capabilities Pointer Register ..................................................... 1227
Offset 3Ch: IRQL: Interrupt Line Register ......................................................... 1228
Offset 3Dh: IRQP: Interrupt Pin Register .......................................................... 1228
Offset 3Eh: BCTL: Bridge Control Register ........................................................ 1228
Offset DCh: PCID: Power Management Capability ID Register ............................. 1229
Offset DDh: PCP: Power Management Next Capability Pointer Register ................. 1230
Offset DEh: PMCAP: Power Management Capability Register ............................... 1230
Offset E0h: PMCS: Power Management Control and Status Register ..................... 1231
Offset E2h: PMCSE: Power Management Control and Status Extension Register ..... 1232
Type 0 PCI Configuration Header .................................................................... 1233
Messaging and Signalling Capability Record per PCI Device ................................ 1235
Bus M, Device 0, Function 0: Summary of Gigabit Ethernet MAC Interface PCI
Configuration Registers ................................................................................... 1237
Bus M, Device 1, Function 0: Summary of Gigabit Ethernet MAC Interface PCI
Configuration Registers ................................................................................... 1238
Bus M, Device2, Function 0: Summary of Gigabit Ethernet MAC Interface PCI Configuration
Registers ....................................................................................................... 1239
Offset 00h: VID: Vendor Identification Register ................................................. 1241
Offset 02h: DID: Device Identification Register ................................................. 1241
Offset 02h: DID: Device Identification Register ................................................. 1242
Offset 02h: DID: Device Identification Register ................................................. 1242
Offset 04h: PCICMD: Device Command Register ............................................... 1243
Offset 06h: PCISTS: PCI Device Status Register ................................................ 1244
Offset 08h: RID: Revision ID Register .............................................................. 1245
Offset 09h: CC: Class Code Register ................................................................ 1245
Offset 0Eh: HDR: Header Type Register ........................................................... 1246
Offset 10h: CSRBAR: Control and Status Registers Base Address Register ............ 1246
Offset 14h: IOBAR: CSR I/O Mapped BAR Register ............................................ 1247
Offset 2Ch: SVID: Subsystem Vendor ID Register ............................................. 1248
Offset 2Eh: SID: Subsystem ID Register .......................................................... 1248
Offset 34h: CP: Capabilities Pointer Register ..................................................... 1249
Offset 3Ch: IRQL: Interrupt Line Register ......................................................... 1249
Offset 3Dh: IRQP: Interrupt Pin Register .......................................................... 1250
Offset DCh: PCID: Power Management Capability ID Register ............................. 1251
Offset DDh: PCP: Power Management Next Capability Pointer Register ................. 1251
Offset DEh: PMCAP: Power Management Capability Register ............................... 1252
Offset E0h: PMCS: Power Management Control and Status Register ..................... 1253
Offset E4h: SCID: Signal Target Capability ID Register ...................................... 1254
Offset E5h: SCP: Signal Target Next Capability Pointer Register .......................... 1254
Offset E6h: SBC: Signal Target Byte Count Register .......................................... 1255
Offset E7h: STYP: Signal Target Capability Type Register ................................... 1255
Offset E8h: SMIA: Signal Target IA Mask Register ............................................. 1256
Offset ECh: SINT: Signal Target Raw Interrupt Register ...................................... 1257
Offset F0h: MCID: Message Signalled Interrupt Capability ID Register .................. 1258
Offset F1h: MCP: Message Signalled Interrupt Next Capability Pointer Register ..... 1258
Intel® EP80579 Integrated Processor Product Line Datasheet
76
August 2009
Order Number: 320066-003US
Contents
35-34
35-35
35-36
35-37
35-38
35-39
35-40
35-41
35-42
35-43
35-44
35-45
35-46
35-47
35-48
35-49
35-50
35-51
35-52
35-53
35-54
35-55
35-56
35-57
35-58
35-59
35-60
35-61
35-62
35-63
35-64
35-65
35-66
35-67
35-68
35-69
35-70
35-71
35-72
35-73
35-74
35-75
35-76
35-77
35-78
35-79
35-80
35-81
35-82
35-83
35-84
35-85
35-86
Offset F2h: MCTL: Message Signalled Interrupt Control Register ..........................1259
Offset F4h: MADR: Message Signalled Interrupt Address Register ........................1259
Offset F8h: MDATA: Message Signalled Interrupt Data Register ...........................1260
Bus M, Device 0, Function 0: Gigabit Ethernet MAC I/O Spaces Registers................1262
Bus M, Device 1, Function 0: Gigabit Ethernet MAC I/O Spaces Registers................1262
Bus M, Device 2, Function 0: Gigabit Ethernet MAC I/O Spaces Registers................1262
Gigabit Ethernet MAC I/O IOBAR Register Summary ............................................1262
Offset 0000h: IOADDR - IOADDR Register ........................................................1263
Offset 0004h: IODATA - IODATA Register .........................................................1264
Bus M, Device 3, Function 0: Summary of GCU PCI Configuration Registers ............1265
Offset 00h: VID: Vendor Identification Register .................................................1265
Offset 02h: DID: Device Identification Register .................................................1266
Offset 04h: PCICMD: Device Command Register ................................................1266
Offset 06h: PCISTS: PCI Device Status Register ................................................1267
Offset 08h: RID: Revision ID Register ..............................................................1268
Offset 09h: CC: Class Code Register ................................................................1268
Offset 0Eh: HDR: Header Type Register ............................................................1268
Offset 10h: CSRBAR: Control and Status Registers Base Address Register .............1269
Offset 2Ch: SVID: Subsystem Vendor ID Register ..............................................1269
Offset 2Eh: SID: Subsystem ID Register ...........................................................1270
Offset 34h: CP: Capabilities Pointer Register .....................................................1270
Offset DCh: PCID: Power Management Capability ID Register ..............................1270
Offset DDh: PCP: Power Management Next Capability Pointer Register .................1271
Offset DEh: PMCAP: Power Management Capability Register ................................1271
Offset E0h: PMCS: Power Management Control and Status Register .....................1272
Bus M, Device 4, Function 0: Summary of CAN Interface PCI
Configuration Registers ....................................................................................1273
Bus M, Devices 5, Function 0: Summary of CAN Interface PCI
Configuration Registers ....................................................................................1274
Offset 00h: VID: Vendor Identification Register .................................................1275
Offset 02h: DID: Device Identification Register .................................................1275
Offset 02h: DID: Device Identification Register .................................................1276
Offset 04h: PCICMD: Device Command Register ................................................1276
Offset 06h: PCISTS: PCI Device Status Register ................................................1277
Offset 08h: RID: Revision ID Register ..............................................................1278
Offset 09h: CC: Class Code Register ................................................................1278
Offset 0Eh: HDR: Header Type Register ............................................................1279
Offset 10h: CSRBAR: Control and Status Registers Base Address Register .............1279
Offset 2Ch: SVID: Subsystem Vendor ID Register ..............................................1280
Offset 2Eh: SID: Subsystem ID Register ...........................................................1280
Offset 34h: CP: Capabilities Pointer Register .....................................................1281
Offset 3Ch: IRQL: Interrupt Line Register .........................................................1281
Offset 3Dh: IRQP: Interrupt Pin Register ..........................................................1282
Offset 40h: CANCTL - CAN Control Register .......................................................1282
Offset DCh: PCID: Power Management Capability ID Register ..............................1283
Offset DDh: PCP: Power Management Next Capability Pointer Register .................1283
Offset DEh: PMCAP: Power Management Capability Register ................................1284
Offset E0h: PMCS: Power Management Control and Status Register .....................1284
Offset E4h: SCID: Signal Target Capability ID Register .......................................1285
Offset E5h: SCP: Signal Target Next Capability Pointer Register ...........................1285
Offset E6h: SBC: Signal Target Byte Count Register ...........................................1286
Offset E7h: STYP: Signal Target Capability Type Register ....................................1286
Offset E8h: SMIA: Signal Target IA Mask Register ..............................................1287
Offset ECh: SINT: Signal Target Raw Interrupt Register .......................................1287
Offset F0h: MCID: Message Signalled Interrupt Capability ID Register ..................1288
August 2009
Order Number: 320066-003US
Intel® EP80579 Integrated Processor Product Line Datasheet
77
Contents
35-87
35-88
35-89
35-90
35-91
35-92
35-93
35-94
35-95
35-96
35-97
35-98
35-99
35-100
35-101
35-102
35-103
35-104
35-105
35-106
35-107
35-108
35-109
35-110
35-111
35-112
35-113
35-114
35-115
35-116
35-117
35-118
35-119
35-120
35-121
35-122
35-123
35-124
35-125
35-126
35-127
35-128
35-129
35-130
35-131
35-132
35-133
35-134
35-135
35-136
35-137
35-138
35-139
Offset F1h: MCP: Message Signalled Interrupt Next Capability Pointer Register ..... 1288
Offset F2h: MCTL: Message Signalled Interrupt Control Register ......................... 1289
Offset F4h: MADR: Message Signalled Interrupt Address Register ........................ 1289
Offset F8h: MDATA: Message Signalled Interrupt Data Register ........................... 1290
Bus M, Device 6, Function 0: Summary of SSP Controller PCI
Configuration Registers ................................................................................... 1291
Offset 00h: VID: Vendor Identification Register ................................................. 1292
Offset 02h: DID: Device Identification Register ................................................. 1292
Offset 04h: PCICMD: Device Command Register ............................................... 1292
Offset 06h: PCISTS: PCI Device Status Register ................................................ 1293
Offset 08h: RID: Revision ID Register .............................................................. 1294
Offset 09h: CC: Class Code Register ................................................................ 1295
Offset 0Eh: HDR: Header Type Register ........................................................... 1295
Offset 10h: CSRBAR: Control and Status Registers Base Address Register ............ 1296
Offset 2Ch: SVID: Subsystem Vendor ID Register ............................................. 1296
Offset 2Eh: SID: Subsystem ID Register .......................................................... 1297
Offset 34h: CP: Capabilities Pointer Register ..................................................... 1297
Offset 3Ch: IRQL: Interrupt Line Register ......................................................... 1297
Offset 3Dh: IRQP: Interrupt Pin Register .......................................................... 1298
Offset DCh: PCID: Power Management Capability ID Register ............................. 1298
Offset DDh: PCP: Power Management Next Capability Pointer Register ................. 1299
Offset DEh: PMCAP: Power Management Capability Register ............................... 1299
Offset E0h: PMCS: Power Management Control and Status Register ..................... 1300
Offset E4h: SCID: Signal Target Capability ID Register ...................................... 1300
Offset E5h: SCP: Signal Target Next Capability Pointer Register .......................... 1301
Offset E6h: SBC: Signal Target Byte Count Register .......................................... 1301
Offset E7h: STYP: Signal Target Capability Type Register ................................... 1301
Offset E8h: SMIA: Signal Target IA Mask Register ............................................. 1302
Offset ECh: SINT: Signal Target Raw Interrupt Register ...................................... 1302
Offset F0h: MCID: Message Signalled Interrupt Capability ID Register .................. 1303
Offset F1h: MCP: Message Signalled Interrupt Next Capability Pointer Register ..... 1303
Offset F2h: MCTL: Message Signalled Interrupt Control Register ......................... 1303
Offset F4h: MADR: Message Signalled Interrupt Address Register ........................ 1304
Offset F8h: MDATA: Message Signalled Interrupt Data Register ........................... 1304
Bus M, Device 7, Function 0: Summary of IEEE 1588 Timestamp Unit PCI Configuration
Registers ....................................................................................................... 1305
Offset 00h: VID: Vendor Identification Register ................................................. 1306
Offset 02h: DID: Device Identification Register ................................................. 1306
Offset 04h: PCICMD: Device Command Register ............................................... 1306
Offset 06h: PCISTS: PCI Device Status Register ................................................ 1307
Offset 08h: RID: Revision ID Register .............................................................. 1308
Offset 09h: CC: Class Code Register ................................................................ 1308
Offset 0Eh: HDR: Header Type Register ........................................................... 1309
Offset 10h: CSRBAR: Control and Status Registers Base Address Register ............ 1309
Offset 2Ch: SVID: Subsystem Vendor ID Register ............................................. 1310
Offset 2Eh: SID: Subsystem ID Register .......................................................... 1310
Offset 34h: CP: Capabilities Pointer Register ..................................................... 1310
Offset 3Ch: IRQL: Interrupt Line Register ......................................................... 1311
Offset 3Dh: IRQP: Interrupt Pin Register .......................................................... 1311
Offset DCh: PCID: Power Management Capability ID Register ............................. 1312
Offset DDh: PCP: Power Management Next Capability Pointer Register ................. 1312
Offset DEh: PMCAP: Power Management Capability Register ............................... 1313
Offset E0h: PMCS: Power Management Control and Status Register ..................... 1313
Offset E4h: SCID: Signal Target Capability ID Register ...................................... 1314
Offset E5h: SCP: Signal Target Next Capability Pointer Register .......................... 1314
Intel® EP80579 Integrated Processor Product Line Datasheet
78
August 2009
Order Number: 320066-003US
Contents
35-140
35-141
35-142
35-143
35-144
35-145
35-146
35-147
35-148
35-149
35-150
35-151
35-152
35-153
35-154
35-155
35-156
35-157
35-158
35-159
35-160
35-161
35-162
35-163
35-164
35-165
35-166
35-167
35-168
35-169
35-170
35-171
35-172
35-173
35-174
35-175
35-176
35-177
35-178
35-179
35-180
37-1
37-2
37-3
37-4
37-5
37-6
37-7
37-8
37-9
37-10
37-11
37-12
37-13
Offset E6h: SBC: Signal Target Byte Count Register ...........................................1314
Offset E7h: STYP: Signal Target Capability Type Register ....................................1315
Offset E8h: SMIA: Signal Target IA Mask Register ..............................................1315
Offset ECh: SINT: Signal Target Raw Interrupt Register .......................................1316
Offset F0h: MCID: Message Signalled Interrupt Capability ID Register ..................1316
Offset F1h: MCP: Message Signalled Interrupt Next Capability Pointer Register ......1317
Offset F2h: MCTL: Message Signalled Interrupt Control Register ..........................1317
Offset F4h: MADR: Message Signalled Interrupt Address Register ........................1318
Offset F8h: MDATA: Message Signalled Interrupt Data Register ...........................1318
Bus M, Device 8, Function 0: Summary of Local Expansion Bus PCI
Configuration Registers ....................................................................................1319
Offset 00h: VID: Vendor Identification Register .................................................1320
Offset 02h: DID: Device Identification Register .................................................1320
Offset 04h: PCICMD: Device Command Register ................................................1321
Offset 06h: PCISTS: PCI Device Status Register ................................................1321
Offset 08h: RID: Revision ID Register ..............................................................1322
Offset 09h: CC: Class Code Register ................................................................1323
Offset 0Eh: HDR: Header Type Register ............................................................1323
Offset 10h: CSRBAR: Control and Status Registers Base Address Register .............1324
Offset 14h: MMBAR: Expansion Bus Base Address Register .................................1324
MMBAR ADDR Field Behavior ............................................................................1325
Offset 2Ch: SVID: Subsystem Vendor ID Register ..............................................1325
Offset 2Eh: SID: Subsystem ID Register ...........................................................1326
Offset 34h: CP: Capabilities Pointer Register .....................................................1326
Offset 3Ch: IRQL: Interrupt Line Register .........................................................1326
Offset 3Dh: IRQP: Interrupt Pin Register ..........................................................1327
Offset 40h: LEBCTL: LEB Control Register ..........................................................1327
Offset DCh: PCID: Power Management Capability ID Register ..............................1327
Offset DDh: PCP: Power Management Next Capability Pointer Register .................1328
Offset DEh: PMCAP: Power Management Capability Register ................................1328
Offset E0h: PMCS: Power Management Control and Status Register .....................1329
Offset E4h: SCID: Signal Target Capability ID Register .......................................1329
Offset E5h: SCP: Signal Target Next Capability Pointer Register ...........................1330
Offset E6h: SBC: Signal Target Byte Count Register ...........................................1330
Offset E7h: STYP: Signal Target Capability Type Register ....................................1330
Offset E8h: SMIA: Signal Target IA Mask Register ..............................................1331
Offset ECh: SINT: Signal Target Raw Interrupt Register .......................................1331
Offset F0h: MCID: Message Signalled Interrupt Capability ID Register ..................1332
Offset F1h: MCP: Message Signalled Interrupt Next Capability Pointer Register ......1332
Offset F2h: MCTL: Message Signalled Interrupt Control Register ..........................1333
Offset F4h: MADR: Message Signalled Interrupt Address Register ........................1333
Offset F8h: MDATA: Message Signalled Interrupt Data Register ...........................1334
Supported Receive Checksum Capabilities ........................................................1363
VLAN Tag Insertion Decision Table when VLAN Mode Enabled (CTRL.VME=1) ..........1368
VLAN Tag Insertion Decision Table.....................................................................1374
Untagged 802.3 Packet vs 802.1q VLAN tagged Packet ........................................1400
Packet Reception Decision Table........................................................................1402
EEPROM Address Map ......................................................................................1413
Initialization Control Word 1 .............................................................................1415
Initialization Control Word 2 .............................................................................1416
Initialization Control Word 3 .............................................................................1416
Management Control Word ...............................................................................1416
IPv4 Address ..................................................................................................1417
IPv6 Address ..................................................................................................1417
Memory protection ..........................................................................................1419
August 2009
Order Number: 320066-003US
Intel® EP80579 Integrated Processor Product Line Datasheet
79
Contents
37-14
37-15
37-16
37-17
37-18
37-19
37-20
37-21
37-22
37-23
37-24
37-25
37-26
37-27
37-28
37-29
37-30
37-31
37-32
37-33
37-34
37-35
37-36
37-37
37-38
37-39
37-40
37-41
37-42
37-43
37-44
37-45
37-46
37-47
37-48
37-49
37-50
37-51
37-52
37-53
37-54
37-55
37-56
37-57
37-58
37-59
37-60
37-61
37-62
37-63
37-64
37-65
GbE Reset Effects ........................................................................................... 1421
Long Word Little Endian, Byte Little Endian Ordering ........................................... 1423
Endianness Control for Gigabit Ethernet MACs .................................................... 1423
Endianness Mode 0: Long Word Little Endian, Byte Big Endian .............................. 1423
Endianness Mode 1: Long Word Little Endian, Byte Little Endian (Default) .............. 1423
Endianness Mode 2: Long Word Big Endian, Byte Big Endian................................. 1424
Endianness Mode 3: Long Word Big Endian, Byte Little Endian .............................. 1424
Bus M, Device 0, Function 0: Summary of Gigabit Ethernet Interface Registers Mapped
Through CSRBAR Memory BAR ......................................................................... 1425
Bus M, Device 1, Function 0: Summary of Gigabit Ethernet Interface Registers Mapped
Through CSRBAR Memory BAR ......................................................................... 1429
Bus M, Devices 2, Function 0: Summary of Gigabit Ethernet Interface Registers Mapped
Through CSRBAR Memory BAR ......................................................................... 1432
I/O Mapped Registers...................................................................................... 1436
CTRL: Device Control Register ........................................................................ 1438
STATUS: Device Status Register ..................................................................... 1441
CTRL_EXT: Extended Device Control Register ................................................... 1442
CTRL_AUX: Auxiliary Device Control Register .................................................... 1444
EEPROM_CTRL - EEPROM Control Register ....................................................... 1446
EEPROM_RR – EEPROM Read Register ............................................................... 1448
FCAL: Flow Control Address Low Register ......................................................... 1449
FCAH: Flow Control Address High Register ....................................................... 1450
FCT: Flow Control Type Register ..................................................................... 1451
VET: VLAN EtherType Register ........................................................................ 1452
FCTTV: Flow Control Transmit Timer Value Register ........................................... 1452
PBA: Packet Buffer Allocation Register ............................................................. 1453
ICR0: Interrupt 0 Cause Read Register ............................................................ 1454
ITR0: Interrupt 0 Throttling Register ............................................................... 1457
ICS0: Interrupt 0 Cause Set Register .............................................................. 1458
IMS0: Interrupt 0 Mask Set/Read Register ....................................................... 1459
IMC0: Interrupt 0 Mask Clear Register ............................................................. 1460
ICR1: Interrupt 1Cause Read Register ............................................................. 1462
ICS1: Interrupt 0 Cause Set Register .............................................................. 1464
IMS1: Interrupt 1 Mask Set/Read Register ....................................................... 1466
IMC1: Interrupt 1 Mask Clear Register ............................................................. 1467
ICR2: Error Interrupt Cause Read Register ....................................................... 1469
ICS2: Error Interrupt Cause Set Register ......................................................... 1471
IMS2: Error Interrupt Mask Set/Read Register ................................................... 1472
IMC2: Error Interrupt Mask Clear Register ......................................................... 1473
RCTL: Receive Control Register ....................................................................... 1474
FCRTL: Flow Control Receive Threshold Low Register .......................................... 1478
FCRTH: Flow Control Receive Threshold High Register ........................................ 1479
RDBAL: Receive Descriptor Base Address Low Register ...................................... 1480
RDBAH: Receive Descriptor Base Address High Register ..................................... 1480
RDLEN: Receive Descriptor Length Register ...................................................... 1481
RDH: Receive Descriptor Head Register ........................................................... 1481
RDT: Receive Descriptor Tail Register .............................................................. 1482
RDTR: RX Interrupt Delay Timer (Packet Timer) Register ................................... 1483
RXDCTL: Receive Descriptor Control Register ................................................... 1483
RADV: Receive Interrupt Absolute Delay Timer Register ..................................... 1485
RSRPD: Receive Small Packet Detect Interrupt Register ..................................... 1486
RXCSUM: Receive Checksum Control Register ................................................... 1487
MTA[0-127] – 128 Multicast Table Array Registers ............................................ 1488
RAL[0-15] - Receive Address Low Register ....................................................... 1488
RAH[0-15] - Receive Address High Register ...................................................... 1489
Intel® EP80579 Integrated Processor Product Line Datasheet
80
August 2009
Order Number: 320066-003US
Contents
37-66
37-67
37-68
37-69
37-70
37-71
37-72
37-73
37-74
37-75
37-76
37-77
37-78
37-79
37-80
37-81
37-82
37-83
37-84
37-85
37-86
37-87
37-88
37-89
37-90
37-91
37-92
37-93
37-94
37-95
37-96
37-97
37-98
37-99
37-100
37-101
37-102
37-103
37-104
37-105
37-106
37-107
37-108
37-109
37-110
37-111
37-112
37-113
37-114
37-115
37-116
37-117
37-118
37-119
37-120
VFTA[0-127] - 128 VLAN Filter Table Array Registers .........................................1490
TCTL: Transmit Control Register ......................................................................1491
TIPG: Transmit IPG Register ...........................................................................1493
AIT: Adaptive IFS Throttle Register ..................................................................1495
TDBAL: Transmit Descriptor Base Address Low Register .....................................1496
TDBAH: Transmit Descriptor Base Address High Register ....................................1496
TDLEN: Transmit Descriptor Length Register .....................................................1497
TDH: Transmit Descriptor Head Register ...........................................................1497
TDT: Transmit Descriptor Tail Register .............................................................1498
TIDV: Transmit Interrupt Delay Value Register ..................................................1499
TXDCTL: Transmit Descriptor Control Register ...................................................1500
TADV: Transmit Absolute Interrupt Delay Value Register ....................................1502
TSPMT: TCP Segmentation Pad And Minimum Threshold Register .........................1504
CRCERRS: CRC Error Count Register ................................................................1505
ALGNERRC: Alignment Error Count Register ......................................................1506
RXERRC: Receive Error Count Register .............................................................1506
MPC: Missed Packet Count Register .................................................................1507
SCC: Single Collision Count Register ................................................................1507
ECOL: Excessive Collisions Count Register ........................................................1508
MCC: Multiple Collision Count Register .............................................................1508
LATECOL: Late Collisions Count Register ..........................................................1509
COLC: Collision Count Register ........................................................................1509
DC: Defer Count Register ...............................................................................1510
TNCRS: Transmit with No CRS Count Register ...................................................1510
CEXTERR: Carrier Extension Error Count Register ..............................................1511
RLEC: Receive Length Error Count Register .......................................................1511
XONRXC: XON Received Count Register ...........................................................1512
XONTXC: XON Transmitted Count Register .......................................................1512
XOFFRXC: XOFF Received Count Register .........................................................1513
XOFFTXC: XOFF Transmitted Count Register .....................................................1513
FCRUC: FC Received Unsupported Count Register ..............................................1514
PRC64: Good Packets Received Count (64 Bytes) Register ..................................1514
PRC127: Good Packets Received Count (65-127 Bytes) Register ..........................1515
PRC255: Good Packets Received Count (128-255 Bytes) Register ........................1515
PRC511 - Good Packets Received Count (256-511 Bytes) Register .......................1516
PRC1023: Good Packets Received Count (512-1023 Bytes) Register .....................1516
PRC1522: Good Packets Received Count (1024 to Max Bytes) Register .................1517
GPRC: Good Packets Received Count (Total) Register .........................................1518
BPRC: Broadcast Packets Received Count Register .............................................1518
MPRC: Multicast Packets Received Count Register ..............................................1519
GPTC: Good Packets Transmitted Count Register ...............................................1519
GORCL: Good Octets Received Count Low Register ............................................1520
GORCH: Good Octets Received Count High Register ...........................................1521
GOTCL: Good Octets Transmitted Count Low Register ........................................1522
GOTCH: Good Octets Transmitted Count High Register .......................................1522
RNBC: Receive No Buffers Count Register .........................................................1523
RUC: Receive Undersize Count Register ............................................................1523
RFC: Receive Fragment Count Register ............................................................1524
ROC: Receive Oversize Count Register .............................................................1524
RJC: Receive Jabber Count Register .................................................................1525
TORL: Total Octets Received Low Register ........................................................1526
TORH: Total Octets Received High Register .......................................................1526
TOTL: Total Octets Transmitted Low Register ....................................................1527
TOTH: Total Octets Transmitted High Register ...................................................1528
TPR: Total Packets Received Register ...............................................................1528
August 2009
Order Number: 320066-003US
Intel® EP80579 Integrated Processor Product Line Datasheet
81
Contents
37-121
37-122
37-123
37-124
37-125
37-126
37-127
37-128
37-129
37-130
37-131
37-132
37-133
37-134
37-135
37-136
37-137
37-138
37-139
37-140
37-141
37-142
37-143
37-144
37-145
37-146
37-147
37-148
37-149
38-1
38-2
38-3
38-4
38-5
38-6
38-7
38-8
38-9
38-10
38-11
38-12
38-13
38-14
39-1
39-2
39-3
39-4
39-5
39-6
39-7
TPT: Total Packets Transmitted Register .......................................................... 1529
PTC64 - Packets Transmitted Count (64 Bytes) Register ..................................... 1529
PTC255: Packets Transmitted Count (128-255 Bytes) Register ............................ 1530
PTC511: Packets Transmitted Count (256-511 Bytes) Register ............................ 1530
PTC1023: Packets Transmitted Count (512-1023 Bytes) Register ........................ 1531
PTC1522: Packets Transmitted Count (1024-1522 Bytes) Register ...................... 1531
MPTC: Multicast Packets Transmitted Count Register ......................................... 1532
BPTC: Broadcast Packets Transmitted Count Register ........................................ 1532
TSCTC: TCP Segmentation Context Transmitted Count Register .......................... 1533
TSCTFC: TCP Segmentation Context Transmit Fail Count Register ....................... 1533
WUC - Wake Up Control Register (0x05800; RW) ................................................ 1534
WUFC - Wake Up Filter Control Register (0x05808; RW) ...................................... 1535
WUS - Wake Up Status Register (0x05810; RW) ................................................ 1536
IPAV - IP Address Valid Register (0x05838; RW)................................................. 1537
IP4AT (0x5840 - 0x5858; RW)[0-3]: IPv4 Address Table Registers ...................... 1538
IPV6_ADDR0BYTES_1_4 – IPv6 Address Table Register (0x5880), Bytes 1 - 4 ...... 1539
IPV6_ADDR0BYTES_5_8 – IPv6 Address Table Register, Bytes 5 - 8 .................... 1539
IPV6_ADDR0BYTES_9_12 – IPv6 Address Table Register, Bytes 9 - 12 ................. 1540
IPV6_ADDR0BYTES_13_16 – IPv6 Address Table Register, Bytes 13 - 16 .............. 1541
FFLT[0-3] - Flexible Filter Length Table Registers (0x5F00 - 0x5F18; RW) .............. 1542
Flexible Filter Mask Table ................................................................................. 1542
FFMT[0-127] - Flexible Filter Mask Table Registers (0x9000 - 0x93F8; RW) ............ 1543
Flexible Filter Mask Table ................................................................................. 1543
FFVT[0-127]: Flexible Filter Value Table Registers ............................................. 1544
INTBUS_ERR_STAT - Internal Bus Error Status Register ..................................... 1544
MEM_TST - Memory Error Test Register ........................................................... 1546
MEM_STS - Memory Error Status Register ........................................................ 1547
MAC Timing ................................................................................................... 1556
GbE Timing Guarantees ................................................................................... 1557
Bus M, Device 3, Function 0: Summary of GCU Registers Mapped Through CSRBAR
Memory BAR .................................................................................................. 1561
Register-Table Legend..................................................................................... 1561
Offset 0x00000010h: MDIO_STATUS - MDIO Status Register................................ 1562
Offset 0x00000014h: MDIO_COMMAND - MDIO Command Register....................... 1562
Offset 0x00000018h: MDIO_DRIVE - MDIO Drive Register ................................... 1563
Offset 0x00000020h: MDC_DRIVE - MDC Drive Register ...................................... 1563
Offset 0x00000024h: GCU_GBE_RC_CTRL - GCU GbE RCOMP Control Register ....... 1564
Offset 0x00000044h: GCU_GBE_RC_STAT - GCU GbE RCOMP Status Register ........ 1564
Offset 0x00000050h: GCU_LEB_RC_STAT - GCU Local Expansion Bus RCOMP Status
Register ........................................................................................................ 1565
Offset 0x00000054h: GCU_LEB_RC_CTRL - GCU Local Expansion Bus RCOMP Control
Register ........................................................................................................ 1566
Offset 0x00000060h: SSP_DRIVE - SSP Drive Register ........................................ 1566
Offset 0x00000064h: TDM_DRIVE_3 - TDM Drive Register for TDM ports 3 ............ 1567
Offset 0x00000068h: TDM_DRIVE_12 - TDM Drive Register for TDM ports 1 & 2 ..... 1567
Offset 0x00000028h: CAN_DRIVE - CAN Drive Register ....................................... 1568
CiA Recommended bit rate and timing Parameters ............................................. 1578
CAN Recommended Bit Rate and Timing Parameters ........................................... 1580
CAN Higher Level Protocol (HLP) Bit Assignment ................................................. 1583
Bus M, Device 4, Function 0: Summary of CAN Registers Mapped Through CSRBAR
Memory BAR .................................................................................................. 1585
Bus M, Device 5, Function 0: Summary of CAN Registers Mapped Through CSRBAR
Memory BAR .................................................................................................. 1586
Offset 00000000h: Int_Status - Interrupt Status Register .................................... 1587
Offset 00000004h: Int_Ebl - Interrupt Enable Register ........................................ 1588
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Order Number: 320066-003US
Contents
39-8
39-9
39-10
39-11
39-12
39-13
39-14
39-15
39-16
39-17
39-18
39-19
39-20
39-21
39-22
39-23
40-1
40-2
40-3
40-4
40-5
40-6
40-7
41-1
41-2
41-3
41-4
41-5
41-6
41-7
41-8
41-9
41-10
41-11
41-12
41-13
41-14
41-15
41-16
41-17
41-18
41-19
41-20
41-21
41-22
41-23
41-24
41-25
41-26
41-27
41-28
Offset 00000008h: Buffer Status Indicators ........................................................1589
Offset 0000000Ch: ErrorStatus - Error Status Indicators ......................................1590
Offset 00000010h: Command - Operating Modes.................................................1591
Offset 00000014h: Config - CAN Configuration Register .......................................1592
Offset 00000020h: TxMessageControl[0-7] - Transmit Message Control and
Command ....................................................................................................1593
Offset 00000024h: TxMessageID[0-7] - Transmit Message ID ...............................1595
Offset 00000028h: TxMessageDataHigh[0-7] - Transmit Message Data High ...........1596
Offset 0000002Ch: TxMessageDataLow[0-7] - Transmit Message Data Low.............1597
Offset 000000A0h: RxMessageControl[0-15] - Receive Message Command and
Control ........................................................................................................1598
Offset 000000A4h: RxMessageID[0-15] - Receive Message ID...............................1600
Offset 000000A8h: RxMessageDataHigh[0-15] - Receive Message Data High...........1600
Offset 000000ACh: RxMessageDataLow[0-15] - Receive Message Data Low ............1601
Offset 000000B0h: RxMessageAMR[0-15] - Receive Message AMR .........................1601
Offset 000000B4h: RxMessageACR[0-15] - Receive Message ACR..........................1602
Offset 000000B8h: RxMessageAMR_Data[0-15] - Receive Message AMR Data .......1603
Offset 000000BCh: RxMessageACR_Data[0-15] - Receive Message ACR Data..........1604
Bus M, Device 6, Function 0: Summary of SSP CSRs ............................................1606
Offset 00h: SSCR0 - SSP Control Register 0 Details ............................................1607
Offset 04h: SSCR1 - SSP Control Register 1 Details ............................................1610
Motorola* SPI Frame Formats for SPO and SPH Programming ..............................1613
Offset 08h: SSSR - SSP Status Register Details ..................................................1614
Offset 0Ch: SSITR - SSP Interrupt Test Register Details ......................................1617
Offset 10h: SSDR - SSP Data Register Details ....................................................1618
Channel Mapping to Interfaces ..........................................................................1622
Clock Synchronization Protocol Flow...................................................................1625
Transparent Clock Synchronization Protocol Flow .................................................1626
IEEE1588 Version 1 and IEEE1588-2008 PTP Message Formats .............................1628
Message Decoding for V1 .................................................................................1629
Message decoding for IEEE1588-2008 ...............................................................1629
PTP Frame Identification ..................................................................................1632
Timestamping Configurations............................................................................1633
Addend Values ................................................................................................1636
Bus M, Device 7, Function 0: Summary of IEEE 1588 TSYNC CSRs .........................1637
Offset 0000h: TS_Control Register ....................................................................1639
Offset 0004h: TS_Event Register .....................................................................1641
Offset 0008h: TS_Addend Register ..................................................................1643
Offset 000Ch: TS_Accum Register ...................................................................1643
Offset 0010h: TS_Test Register .......................................................................1644
Offset 0014h: TS_PPS_Compare Register .........................................................1646
Offset 0018h: TS_RSysTimeLo Register ............................................................1647
Offset 001Ch: TS_RSysTimeHI Register ............................................................1648
Offset 0020h: TS_SysTimeLo Register ..............................................................1649
Offset 0024h: TS_SysTimeHi Register ..............................................................1650
Offset 0028h: TS_TrgtLo Register ....................................................................1650
Offset 002Ch: TS_TrgtHi Register ....................................................................1651
Offset 0030h: TS_ASMSLo Register .................................................................1652
Offset 0034h: TS_ASMSHi Register ...................................................................1653
Offset 0038h: TS_AMMSLo Register ..................................................................1654
Offset 003Ch: TS_AMMSHi Register ..................................................................1655
Offset 0040h: TS_Ch_Control[0-7] - Time Synchronization Channel Control
Register (Per Ethernet Channel) ........................................................................1656
Offset 0044h: TS_CH_EVENT[0-7] - Time Synchronization Channel Event
Register Per Ethernet Channel) .........................................................................1658
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Order Number: 320066-003US
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Contents
41-29
41-30
41-31
41-32
41-33
41-34
41-35
41-36
41-37
41-38
41-39
41-40
41-41
41-42
41-43
42-1
42-2
42-3
42-4
42-5
42-6
42-7
42-8
42-9
42-10
42-11
43-1
43-2
43-3
43-4
44-1
44-2
45-1
45-2
45-3
46-1
46-2
46-3
47-1
47-2
47-3
47-4
48-1
48-2
48-3
Offset 0048h: TS_TxSnapLo[0-7] - Transmit Snapshot Low Register
(Per Ethernet Channel) .................................................................................... 1659
Offset 004Ch: TS_TxSnapHi[0-7] - Transmit Snapshot High Register
(Per Ethernet Channel) .................................................................................... 1660
Offset 0050h: TS_RxSnapLo[0-7] - Receive Snapshot Low Register
(Per Ethernet Channel) .................................................................................... 1661
Offset 0054h: TS_RxSnapHi[0-7] - Receive Snapshot High Register
(Per Ethernet Channel) .................................................................................... 1662
Offset 0058h: TS_SrcUUIDLo[0-7] - Source UUID0 Low Register
(Per Ethernet Channel) .................................................................................... 1663
Offset 005Ch: TS_SrcUUIDHI[0-7] - SequenceID/SourceUUID High Register
(Per Ethernet Channel) ................................................................................... 1664
Offset 0140h: TS_CANx_Status[0-1] - Time Synchronization Channel Event
Register (Per CAN Channel) ............................................................................. 1665
Offset 0144h: TS_CANSnapLo[0-1] - Transmit Snapshot Low Register
(Per CAN Channel).......................................................................................... 1666
Offset 0148h: TS_CANSnapHi[0-1] - Transmit Snapshot High Register
(Per CAN Channel).......................................................................................... 1667
Offset 01F0h: TS_Aux_TrgtLo Register ............................................................. 1668
Offset 01F4h: TS_Aux_TrgtHi Register .............................................................. 1668
Offset 0200h: L2 EtherType Register ................................................................. 1669
Offset 0204h: User Defined EtherType Register .................................................. 1669
Offset 0208h:User Defined Header Offset Register .............................................. 1670
Offset 020Ch:User Defined Header Register ....................................................... 1670
Example Expansion Bus Pin Mappings to Target Devices ...................................... 1673
Expansion Bus Address and Data Byte Steering ................................................. 1676
Multiplexed Output Pins for HPI Operation.......................................................... 1682
HPI HCNTL Control Signal Decoding .................................................................. 1682
Bus M, Device 8, Function 0: Summary of Local Expansion Bus Registers Mapped Through
CSRBAR PCI Memory BAR"............................................................................... 1697
EXP_TIMING_CS0 - Expansion Bus Timing Register ............................................. 1698
EXP_TIMING_CS[1-7] - Expansion Bus Timing Registers .................................... 1700
EXP_CNFG0 -Configuration Register 0 ............................................................... 1702
EXP_PARITY_STATUS - Expansion Bus Parity Status Register .............................. 1703
LEB Performance Calculation - Estimated AIOC Latencies ..................................... 1704
Outbound Performance Estimation Examples ...................................................... 1705
EP80579 TAPs Public Instructions...................................................................... 1710
EP80579 TAP IDCode Values ............................................................................ 1710
JTAG Instructions Summary for MCH ............................................................... 1711
Compliance Pins Excluded from Boundary Scan Chain .......................................... 1713
1149.1 Public Instructions in the IA-32 Core TAP ............................................... 1715
Device ID Register Bit-fields ............................................................................ 1716
IMCH JTAG Instructions .................................................................................. 1717
JTAG Device Identification Register Field Designations ........................................ 1718
JTAG ID Code for CMI ..................................................................................... 1718
Serial Test Mode Entry Command Field .............................................................. 1722
Test Control Register 0 ................................................................................... 1723
XOR Chains.................................................................................................... 1725
Base Features of EP80579 SKUs ....................................................................... 1730
IA-32 Core Internal Bus and DDR2 Frequencies .................................................. 1731
Tolapai Strap Options ...................................................................................... 1731
EP80579 Pre-Boot Firmware Programmable Options ............................................ 1732
Signal Type Definitions .................................................................................... 1733
XOR Chain Elements ....................................................................................... 1734
Signal Pin Description References ..................................................................... 1735
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Contents
48-4
48-5
48-6
48-7
48-8
48-9
48-10
48-11
48-12
48-13
48-14
48-15
48-16
48-17
48-18
48-19
48-20
48-21
48-22
48-23
48-24
48-25
48-26
48-27
48-28
48-29
48-30
48-31
48-32
48-33
48-34
48-35
48-36
48-37
48-38
49-1
49-2
49-3
49-4
49-5
49-6
49-7
49-8
49-9
49-10
49-11
49-12
49-13
49-14
49-15
49-16
49-17
49-18
IA-32 Core Thermal Signals ..............................................................................1736
Global Clock and Reset (CRU) Signals ................................................................1736
Sideband Miscellaneous Signals.........................................................................1737
IMCH Reset Signals .........................................................................................1739
DDR2 Interface Signals ....................................................................................1739
PCI Express Interface Signals ...........................................................................1741
Real Time Clock Interface Signals ......................................................................1744
General-Purpose IO Signals ..............................................................................1744
IICH Interrupt Signals......................................................................................1748
SPI Interface Signals .......................................................................................1749
LPC and FWH Interface Signals .........................................................................1749
SMBus Interface Signals...................................................................................1750
UART Signals ..................................................................................................1751
Serial ATA Interface Signals..............................................................................1753
USB Interface Signals ......................................................................................1755
Power Management Interface Signals.................................................................1756
IICH Miscellaneous Signals ...............................................................................1758
Controller Area Network Bus Signals ..................................................................1759
Gigabit Ethernet Interface Signals .....................................................................1760
TDM Interface Signals, .....................................................................................1764
Expansion Bus Signals .....................................................................................1765
SSP Interface Signals ......................................................................................1768
IEEE 1588-2008 Hardware Assist Interface Signals ..............................................1768
JTAG Interface Signals .....................................................................................1769
Miscellaneous Signals ......................................................................................1770
Reserved Pin List.............................................................................................1770
No Connect Pin List .........................................................................................1771
Power and Ground Summary Pin List .................................................................1772
Alphabetical Ball Listing....................................................................................1779
Alphabetical Signal Listing ................................................................................1788
EP80579 Ball Map (bottom view, left side) ..........................................................1797
EP80579 Ball Map (bottom view, right side) ........................................................1799
EP80579 Ball Map (top view, left side) ...............................................................1801
EP80579 Ball Map (top view, right side) .............................................................1803
Package Trace Length ......................................................................................1805
Absolute Maximum Ratings...............................................................................1820
Undershoot and Overshoot for PCI, JTAG, SATA and CRU Signal Groups .................1821
Undershoot and Overshoot for DDR2 Signal Group...............................................1821
Undershoot and Overshoot for GbE Signal Group .................................................1822
Undershoot and Overshoot for RTC, SPI, USB, TDM, LEBus, CAN, SSP, IEEE 1588-2008,
ICH Miscellaneous, IICH, SMBus, UART, LPC, GPIO, Sideband Miscellaneous, IMCH, PMI,
and Miscellaneous Signal Groups .......................................................................1822
Operating Conditions Power Supply Rails ............................................................1823
Maximum Supply Current Embedded SKU...........................................................1825
Maximum Supply Current Accelerated SKU .........................................................1827
Platform External/Internal Clock Interface ..........................................................1829
Power Management DC Input Characteristics ......................................................1831
Power Management DC Output Characteristics ....................................................1831
Power Sequencing Signal Timings......................................................................1832
DDR2 DC Input Characteristics..........................................................................1836
DDR2 DC Output Characteristics........................................................................1836
DDR2 Differential Input/Output AC Levels...........................................................1838
DDR2-400 Interface AC Characteristics ..............................................................1839
DDR2-533 Interface AC Characteristics ..............................................................1840
DDR2-667 Interface AC Characteristics ..............................................................1841
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Contents
49-19
49-20
49-21
49-22
49-23
49-24
49-25
49-26
49-27
49-28
49-29
49-30
49-31
49-32
49-33
49-34
49-35
49-36
49-37
49-38
49-39
49-40
49-41
49-42
49-43
49-44
49-45
49-46
49-47
49-48
49-49
49-50
49-51
49-52
49-53
49-54
49-55
49-56
49-57
49-58
49-59
49-60
49-61
49-62
49-63
49-64
49-65
49-66
49-67
49-68
49-69
49-70
49-71
49-72
49-73
DDR2-800 Interface AC Characteristics .............................................................. 1842
PCI Express* Differential Receiver (RX) Specifications ......................................... 1847
PCI Express* Differential Transmitter (TX) Specifications ..................................... 1848
PCI Express* Clock DC Specifications ................................................................ 1850
PCI Express* Clock Timings ............................................................................. 1850
SATA DC Input Characteristics (SATA_RX[P,N]) .................................................. 1854
SATA DC Input Characteristics (GPIO and SATALED#) ......................................... 1854
SATA DC Output Characteristics (SATA_TX(P,N)) ................................................ 1855
SATA DC Output Characteristics (SATALED#) ..................................................... 1855
SATA DC Clock Specifications (SATA_CLKN, SATA_CLKP) ..................................... 1855
SATA Clock (SATA_CLKp, SATA_CLKn) .............................................................. 1856
SATA Interface Timings ................................................................................... 1856
USB Overcurrent Indicators DC Input (OC[1:0]) ................................................. 1857
USB LV Differential DC Characteristics (USBn[1:0], USBp[1:0]) ............................ 1858
USB Clock (CLK48) DC Input Specifications ........................................................ 1859
USB Input Clock (CLK48) AC Specifications ........................................................ 1859
USB Timing Specifications ................................................................................ 1860
SMBus DC Input Characteristics........................................................................ 1863
SMBus DC Output Characteristics...................................................................... 1863
SMBus DC Clock Specification........................................................................... 1863
SMBus Input AC Characteristics ........................................................................ 1864
SMBus Clock Timings (SMBCLK) ....................................................................... 1865
SMBus Output AC Characteristics ...................................................................... 1865
UART DC Input Characteristics ......................................................................... 1867
UART DC Output Characteristics ....................................................................... 1867
UART DC Clock Specification ............................................................................ 1868
UART Timing .................................................................................................. 1868
UART Timing .................................................................................................. 1868
SPI DC Input Characteristics ............................................................................ 1869
SPI DC Output Characteristics .......................................................................... 1869
SPI Timing Specifications ................................................................................. 1869
LPC DC Input Characteristics ............................................................................ 1871
LPC DC Output Characteristics .......................................................................... 1871
LPC DC Clock Specifications ............................................................................. 1871
LPC Clock AC Characteristics ............................................................................ 1872
LPC Input Timing Specification ......................................................................... 1872
LPC Output Timing Specification ....................................................................... 1872
GPIO DC Input Characteristics .......................................................................... 1874
GPIO DC Output Characteristics ........................................................................ 1875
IICH Interrupt Signal DC Input Characteristics.................................................... 1875
IICH Interrupt Signal DC Output Characteristics.................................................. 1875
IICH Interrupt Signal Timing Specification.......................................................... 1876
IICH Clock (CLK14) AC Specifications ................................................................ 1876
RTC DC Input Characteristics (RTEST#) ............................................................. 1877
RTC DC Clock Input Characteristics (RTCX[2:1]) ................................................. 1878
RTC Clock Input (RTCX[2:1])Timing Values ........................................................ 1878
RTC Clock Output (SUSCLK) Timings ................................................................. 1878
DC Input Characteristics: RMII Mode of Operation............................................... 1879
DC Output Characteristics: RMII Mode of Operation............................................. 1880
DC Input Characteristics: RGMII Mode of Operation............................................. 1880
DC Output Characteristics: RGMII Mode of Operation........................................... 1880
DC Input Characteristics: MDIO Mode of Operation.............................................. 1881
DC Output Characteristics: MDIO Mode of Operation ........................................... 1881
DC Input Characteristics: EEPROM Interface....................................................... 1881
DC Output Characteristics: EEPROM Interface..................................................... 1882
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Contents
49-74
49-75
49-76
49-77
49-78
49-79
49-80
49-81
49-82
49-83
49-84
49-85
49-86
49-87
49-88
49-89
49-90
49-91
49-92
49-93
49-94
49-95
49-96
49-97
49-98
49-99
49-100
49-101
49-102
49-103
49-104
49-105
49-106
49-107
49-108
49-109
50-1
50-2
Reference Clock DC Input Specification: (GBE_REFCLK_RMII, GBE_REFCLK) ...........1882
Frequencies of All Input Clocks..........................................................................1882
GbE RGMII Reference Clock Timing Values..........................................................1883
GbE Transmit Timing Values — RGMII Mode........................................................1884
GbE Receive Timing Values — RGMII Mode .........................................................1886
GbE Transmit and Receive Timing Values — RMII 100/10 Base Mode .....................1888
MDIO Timings Values.......................................................................................1889
EEPROM Read Operation ..................................................................................1889
EEPROM Timing Values ....................................................................................1890
TDM DC Input Characteristics ...........................................................................1891
TDM DC Output Characteristics .........................................................................1892
TDM DC Clock Input Specifications (RX_CLKn) ....................................................1892
TDM DC Clock Output Specifications (TX_CLKn)...................................................1892
TDM, Serial Timings Values...............................................................................1893
LEB DC Input Characteristics ............................................................................1895
LEB DC Output Characteristics ..........................................................................1895
LEB DC Clock Input Specifications (External Clock) ..............................................1895
Local Expansion Bus Synchronous Operation Timing Values ..................................1896
CAN DC Input Characteristics............................................................................1897
CAN DC Output Characteristics..........................................................................1897
SSP DC Input Characteristics ............................................................................1898
SSP DC Output Characteristics ..........................................................................1898
SSP DC Clock Specification ...............................................................................1898
SSP Timing Values and Test Conditions ..............................................................1900
IEEE 1588-2008 Hardware Assist DC Input Characteristics....................................1901
IEEE 1588-2008 Hardware Assist DC Output Characteristics..................................1901
IICH Miscellaneous Signals DC Input Characteristics ............................................1902
IICH Miscellaneous Signals DC Output Characteristics ..........................................1902
CRU Differential Clock DC Specifications .............................................................1903
CRU Differential Input Clock Timing Specifications ...............................................1904
Sideband Miscellaneous Signals DC Input Characteristics ......................................1905
Sideband Miscellaneous Signals DC Output Characteristics ....................................1906
IMCH Reset Signals DC Input Characteristics.......................................................1906
JTAG DC Specifications (except BPM4_PRDY_OUT)...............................................1907
JTAG DC Output Specifications (BPM4_PRDY_OUT) ..............................................1907
JTAG Timing Specifications ...............................................................................1907
EP80579 Thermal Design Power (TDP) and Maximum Case Temperature Specifications
(TC-MAX) .......................................................................................................1912
PROCHOT_DTY/THTL_DTY Throttle Ratios...........................................................1916
August 2009
Order Number: 320066-003US
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Revision History
Revision History
Date
August
2009
Revision
003
Description
Changed the following signal names:
• EX_REQ_GNT# to Reserved 19
• EX_SLAVE_CS# to Reserved 20
• EX_GNT_REQ# to NC57
• EX_WAIT# to NC58
• EX_WDTXFER to NC59
Corrected signal name:
• SIU_CST1 to SIU_CST1#
• SIU_CST2 to SIU_CST2#
Updated:
• Section Product Features
• Table 1-4, “Glossary Table”
• Table 2-1, “EP80579 External Interface Summary”
• Table 5-32, “Summary of Local Expansion Bus Error Conditions”
• Table 6-5, “Powergood Reset Timings”
• Section 6.3.2.1, “Transitioning Between Power States”
• Section 11.4.6, “RCOMP”
• Section 16.5.1.64, “Offset 268h: DDRIOMC2 - DDR IO Mode Control Register 2”
• Section 23.1.1.5, “PI - Programming Interface Register”
• Section 37.5.11.6.3, “Checksum Word Calculation”
• Section 42.5, “Register Summary”
• Table 42-7, “EXP_TIMING_CS[1-7] - Expansion Bus Timing Registers”
• Table 42-9, “EXP_PARITY_STATUS - Expansion Bus Parity Status Register”
• Table 42-10, “LEB Performance Calculation - Estimated AIOC Latencies”
• Table 48-24, “Expansion Bus Signals”
• Table 48-22, “Gigabit Ethernet Interface Signals” with signal name changes
• Figure 49-28, “LPC Valid Delay from Rising Clock Edge Diagram” and Figure 49-32, “IICH Clock
(CLK14) Timing Diagram” with signal name corrections
• Table 49-10, “Power Management DC Input Characteristics” PWRBTN# pin
• Table 49-11, “Power Management DC Output Characteristics” PWRBTN# pin
• Table 49-36, “SMBus DC Input Characteristics” Intruder# pin
• Table 49-37, “SMBus DC Output Characteristics” Intruder# pin
• Table 49-106, “IMCH Reset Signals DC Input Characteristics” CLK100
(Continued Next Page)
Intel® EP80579 Integrated Processor Product Line Datasheet
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August 2009
Order Number: 320066-003US
Revision History
Date
August
2009
Revision
003
Description
Added:
• Industrial temperatures to Chapter 49.0, “Electrical Specifications” and Chapter 50.0, “Thermal
Specifications and Design Considerations”
The following changes were made due to defeaturing LEB Mastering:
• Section 2.2, “Signaling Architecture”
• Table 2-1, “EP80579 External Interface Summary” - LEB Description
• Table 2-4, “Summary of Communication” - removed “LEB Master”
• Table 3-7, “Address Space Sizes of AIOC-attached Devices” - removed LEB row
• Note E in Table 3-11, “PCI Configuration Header Support for Type 0 Headers in AIOC Devices”
• Section 4.2.2, “Other Agents” - fourth bullet removed “master”
• Table 5-32, “Summary of Local Expansion Bus Error Conditions” - Notes description
• Removed rows in Table 7-67, “Bus M, Device 8, Function 0: Summary of Local Expansion Bus
Registers Mapped Through CSRBAR PCI Memory BAR"” containing LEB content
• Removed LEB content from Section 36.3, “Local Expansion Bus Interface (LEB)”
• Removed content from Section 42.0, “Local Expansion Bus Controller”
•“EXP_MST_CONTROL - Expansion Bus Control Register”
•“EXP_LOCK0 - Expansion Bus Lock Register”
•“Offset D0500010h: CMD_TRNS1_W[0-3] - Command Translation Window Register “
• Removed LEB content from Section 42.1, “Overview” and Section 42.2, “Feature List”
• Removed LEB content from Figure 42-1, “Expansion Bus Controller”
• Removed LEB content and also “Inbound Transfers” , “Arbitration”, “Expansion Bus Inbound Timing
Diagrams” and “External Expansion Bus Timing Diagram” content from Section 42.4, “Theory of
Operation”
• Removed Table 42-16 and Section 42.5.2.6
Removed:
Removed two rows with D30/D31 content from Table 1-4, Section 6.1.2.3.1, “IICH”, Table 28-9, and
from PCIRST# description in Table 48-28.
August 2009
Order Number: 320066-003US
Intel® EP80579 Integrated Processor Product Line Datasheet
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Revision History
Date
Revision
Description
Added:
• Chapter 28.0, “IA-32 Core Interface”
December
2008
002
July 2008
001
Updated:
• Figure 6-1, “Powergood and Reset Interface”
• Table 49-12, “Power Sequencing Signal Timings”
• Table 16-26, “Offset 9Ch: DEVPRES - Device Present Register”
• Table 16-40, “Offset F6h: IMCH_TST2 - IMCH Test Byte 2 Register”
• Section 22.1, “Overview”
• Text in Section 35.12.1.9, “Offset 14h: MMBAR – Expansion Bus Base Address Register”
• Text in Section 42.5.1.2, “EXP_TIMING_CS[1-7] - Expansion Bus Timing Registers”
• Figure 42-2, “Chip Select Address Allocation When There Are no 32-MByte Devices Programmed”
• Figure 42-4, “Chip Select Address Allocation when a 32 Mbyte device is programmed”
• Figure 48-3, “FCBGA Package — Bottom View”
• Table 48-24, “Expansion Bus Signals”
• Table 48-29, “Reserved Pin List”
• Table 48-30, “No Connect Pin List”
• Table 49-7, “Maximum Supply Current Embedded SKU”
• Table 49-11, “Power Management DC Output Characteristics”
• Table 49-36, “SMBus DC Input Characteristics”
• Table 49-38, “SMBus DC Clock Specification”
• Table 49-48, “SPI DC Output Characteristics”
• Table 49-67, “DC Output Characteristics: RMII Mode of Operation”
• Table 49-82, “EEPROM Timing Values”
• Table 49-84, “TDM DC Output Characteristics”
• Table 49-89, “LEB DC Output Characteristics”
• Table 49-93, “CAN DC Output Characteristics”
• Table 49-95, “SSP DC Output Characteristics”
• Table 49-99, “IEEE 1588-2008 Hardware Assist DC Output Characteristics”
• Table 49-101, “IICH Miscellaneous Signals DC Output Characteristics”
• Table 49-108, “JTAG DC Output Specifications (BPM4_PRDY_OUT)”
Initial release of this document.
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Introduction and Overview, Volume
1 of 6
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Intel® EP80579 Integrated Processor
1.0
Introduction
1.1
Introduction
The Intel® EP80579 Integrated Processor product line is made of up of the Intel®
EP80579 Integrated Processor and the Intel® EP80579 Integrated Processor with
Intel® QuickAssist Technology. The Intel® EP80579 Integrated Processor product line is
an integrated System On a Chip (SoC). The Intel® EP80579 Integrated Processor with
Intel® QuickAssist Technology architecture combines Intel Architecture (IA)-based
communications processors, a memory hub controller (IMCH), an I/O architecture
(IICH), and high speed I/O interfaces (PCI Express*, Gigabit Ethernet). The Intel®
EP80579 Integrated Processor with Intel® QuickAssist Technology also features highperformance packet processing and security capabilities. The Intel® EP80579
Integrated Processor product line architecture is designed to provide best-in-class
processing performance, stringent power usage, and reasonable cost targets while
maintaining IA implementation and providing the required I/O throughput.
The intended audience for this document is architects, hardware/software design
engineers or designer who may need specific technical information for the development
and programming of the EP80579 integrated processor SoC. This document is also
intended for an audience that has a thorough understanding of IA-32 microprocessor,
memory controller and I/O architectures as well as a basic understanding of system
software architectures (operating system and pre-boot firmware).
1.2
Document Organization
Note:
The Intel® EP80579 Integrated Processor product line is referred to as the "EP80579".
In cases where the features are specific to a given processor we will use Intel®
EP80579 Integrated Processor or Intel® EP80579 Integrated Processor with Intel®
QuickAssist Technology.
This document first provides an overview of the Intel® EP80579 Integrated Processor
product line architecture. The overview chapter provides a block diagram and defines
the ’s external and internal interfaces. This is followed by a functional description of the
following blocks:
• IA Complex (including the IA-32 core, IMCH and IICH).
• Acceleration and I/O Complex (including ASU, SSU, and high-speed I/O interfaces
such as Gigabit Ethernet and TDM).
• Test and Debug information, including JTAG.
• Technical Specifications (SKUs, Packaging, Electrical and Thermal).
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1.3
Referenced Documents and Related Websites
Visit the Intel® EP80579 Integrated Processor product line Website for other
information:
http://www.intel.com/go/SoC
Table 1-1.
Referenced Documents
Document Title
Location
Advanced Configuration and Power Interface (ACPI)
Specification
http://www.acpi.info/
Enhanced Host Controller Specification (EHCI and UHCI)
http://www.intel.com/technology/USB/spec.htm/
IEEE 1149.1: IEEE Standard Test Access Port and
Boundary-Scan Architecture
http://ieeexplore.ieee.org
IEEE 1588:Precision Clock Synchronization Protocol for
Networked Measurement and Control Systems
http://ieeexplore.ieee.org
Intel Architecture Software Developer’s Manual, Volumes
1–3
http://developer.intel.com/design/pentium4/
manuals/index_new.htm#sdm_vol1
Intel Corporation, Advanced Host Controller Interface
Specification for Serial ATA
http://www.intel.com/technology/serialata/
ahci.htm
Intel Corporation, Enhanced Host Controller Interface
Specification for Universal Serial Bus
http://www.intel.com/technology/usb/
ehcispec.htm
Intel Corporation, Low Pin Count (LPC) Interface
Specification
http://www.intel.com/design/chipsets/industry/
lpc.htm
Intel Corporation, Multiprocessor Specification
http://www.intel.com/design/archives/processors/
pro/docs/242016.htm
Intel Corporation, Universal Host Controller Interface
(UHCI) Specification
http://www.intel.com/technology/usb/
ehcispec.htm
Intel Corporation, Universal Serial Bus (USB)
Specification
http://www.intel.com/technology/usb/spec.htm
Intel Corporation, USB2 Debug Device Functional
Specification
http://www.intel.com/technology/usb/download/
DebugDeviceSpec_R090.pdf
Intel® 82093AA I/O Advanced Programmable Interrupt
Controller (I/O APIC)
http://www.intel.com/design/chipsets/specupdt/
290710.htm?iid=search&
Intel® EP80579 Integrated Processor product line
Platform Design Guide
http://www.intel.com/go/SoC
®
Intel EP80579 Integrated Processor product line
Specification Update
http://www.intel.com/go/SoC
Intel® EP80579 Integrated Processor product line
Thermal/Mechanical Design Guide
http://www.intel.com/go/SoC
JEDEC Specification
http://www.jedec.org/default.cfm
Low Pin Count Specification (LPC)
http://www.intel.com/design/chipsets/industry/
lpc.htm
Serial ATA Specification
http://www.serialata.org/specifications.asp
SMBus Specification
http://www.smbus.org/specs/
Universal Host Controller Specification (EHCI and UHCI)
http://www.intel.com/technology/USB/spec.htm/
Universal Serial Bus Specification
http://www.usb.org/developers/docs/
http://www.intel.com/technology/USB/spec.htm/
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Table 1-2.
Related Websites
Specification or Technology
Website
http://developer.intel.com/ial/scalableplatforms/
audio/index.htm #97spec/
AC’97 Rev 2.2 Specification
ACPI and related specifications
http://www.acpi.info/spec.htm
AT Attachment-6 with Packet Interface (ATA/ATAPI-6)
http://T13.org (T13 1410D)
BIOS Boot Specifications
http://www.phoenix.com/en/customer+services/
white+papers-specs/
Communication and Network Riser Rev 1.2
Specification
http://developer.intel.com/technology/cnr/
download.htm
Front Panel I/O Connectivity Design Guide
http://www.formfactors.org/DeveloperResources.asp
PCI and PCI Express* related specifications
1.4
http://www.pcisig.com/specifications
PIRQ Routing Table Information
http://www.microsoft.com/whdc/archive/pciirq.mspx
Power Management Specifications
http://www.microsoft.com/whdc/resources/respec/
specs/pmref/default.mspx
Acronyms
This section describes acronyms that are used throughout this document.
Table 1-3.
Acronym Table
Term
Description
ACPI
Advanced Configuration and Power Interface Specification, an industry specification of the
common interfaces enabling robust operating system (OS)-directed motherboard device
configuration and power management of both devices and entire systems.
AHCI
Advanced Host Controller Interface, an industry specification of the interface between
memory and SATA devices.
AIO
AIOC
IMCH A-unit I/O Mux Leg
Acceleration and I/O Complex
AMC
Audio/Modem Codec
ARP
Address resolution protocol
ASF
Alert Specification Format. This is the next generation of “Alert on LAN*” implementation.
ASU
Acceleration Services Unit
BAR
PCI Base Address Register used to define the base and limit of an I/O or memory region
assigned to a PCI device.
BER
Bit Error Rate
BGA
Ball Grid Array
CM
Coherent Memory
CMC
Common Mode Choke
CMI
Core (IA-32 core) interface, Memory controller hub, I/O controller hub
CNR
Communications and Networking Riser
CRC
See Cyclic Redundancy Check in Table 1-4.
CSMA/CD
Carrier Sense Multiple Access/Carrier Detect
DDP
Direct Data Placement Protocol
DDR
DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory) is a
system memory technology.
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Table 1-3.
Acronym Table
Term
Description
DED
Double-bit Error Detect
DMA
See Direct Memory Access in Table 1-4.
DW
Double Word. A legacy reference to 32 bits of data on a naturally aligned four-byte
boundary (i.e. the least significant two bits of the byte address are b00). This is a legacy
term used by PCI and must not be used other than in that context.
ECC
Error Checking and Correction
EDMA
EMI
EMTS
EOP/EOF
Enhanced DMA
Electro Magnetic Interference
Electrical Mechanical Thermal Specification used for processor specifications.
End Of Packet / End Of Frame
ESD
Electrostatic Discharge
EXP
A generic designation for the I/O interconnect technology also known as PCI Express*.
FRU
Field Replaceable Unit
FS
Full-speed. Refers to USB.
FSB
Front Side Bus (a common external interface for IA processors)
FWH
Firmware Hub. A non-volatile memory device used to store the system BIOS/pre-boot
firmware.
GbE
Gigabit Ethernet controller
GMII
Gigabit MII
HBA
Host Bus Adapter - necessary when connecting a peripheral to a computer that doesn’t
have native support for that peripheral’s interface.
HCD
Host Controller Device - USB interface for programmers
HECBASE
HPET
PCI Express* Enhanced Configuration Base Register
High Precision Event Time (HPET) - The IA-PC HPET Architecture defines a set of timers
that can be used by the operating system. The timers are defined such that the OS may
be able to assign specific timers to be used directly by specific applications. Each timer
can be configured to generate a separate interrupt.
HSI
High Speed Interface. Refers to USB.
I/O
1. Input/Output. 2. When used as a qualifier to a transaction type, specifies that
transaction targets Intel Architecture™ specific I/O space (e.g., I/O read).
IA
Intel Architecture instruction set commonly known as “x86”
IA-CPU
IA-CPU, IA Complex and IA Processor are the same terminology
ICH
I/O Controller Hub, ICH and IICH are interchangeable for entire document
IICH
Integrated I/O Controller Hub, ICH and IICH are interchangeable for entire document
IMCH
Integrated Memory Controller Hub, MCH and IMCH are interchangeable for the entire
document
INTx
Legacy PCI interrupt architecture that encodes interrupts on one of four side-band signals
(INTA, INTB, INTC, and INTD).
IP
ISA
Internet Protocol
See Industry Standard Architecture in Table 1-4
LEB
Local Expansion Bus, or LE Bus
LML
Latency Measurement Logic
LPC
Low Pin Count
LS
Low-speed. Refers to USB.
LSb
Least Significant Bit
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Table 1-3.
Acronym Table
Term
Description
LSB
Least Significant Byte
MCH
Memory Controller Hub, MCH and IMCH are interchangeable for the entire document
MII
Media Independent Interface (16 pins per port)
MMIO
Memory Mapped I/O
MMR
Memory Mapped Register
MSb
Most Significant Bit
MSB
Most Significant Byte
MSI
Message-signaled interrupt that encodes interrupts as an in-band 32-bit write transaction.
MTBF
Mean Time Between Failures
NCM
Non Coherent Memory
NIC
Network interface controller
NOS
Network Operating System
NSI
North South Interface. The designation for the proprietary, internal high-speed serial
interconnect between the IMCH and the IICH.
OS
Operating System.
OSPM
Operating System directed Power Management
P2P
See Peer-to-Peer in Table 1-4
PB
Packet Buffer
PBM
Packet Buffer Memory
PCI
Peripheral Component Interconnect Local Bus. A 32- or 64-bit bus with multiplexed
address and data lines that is primarily intended for use as an interconnect mechanism
within a system between processor/memory and peripheral components or add-in cards.
PCM
Pulse Code Modulation
PEC
Packet Error Checking. This is an SMBUS 2.0 feature.
PHY
Physical Layer Device
POC
Power-on-configuration
RASUM
Reliability, Availability, Serviceability, Usability, and Manageability, which are all important
characteristics of servers.
RCBA
Root Complex Base Address register at D31:F0:RegF0h. It specifies the physical address
of the CMI Configuration Space. Also used in RCBA + offset xxxxh or RCBA + xxxxh
(where xxxxh is the offset) to indicate register location in the CMI Configuration Space.
RCRB
Root Complex Register Block, as defined in the PCI Express* Specification v1.0a. In the
IICH context, it refers to a part of the CMI Configuration Space (see RCBA, above).
RDMA
RFL
RGMII
RMII
Remote Direct Memory Access
Receive FIFO Level
Reduced GMII
Reduced MII (7 pins per port)
RMW
Read-Modify-Write operation
RTC
Real-Time Clock
RTCRESET#
RX
SATA
SATA*
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Signal that resets the RTC well (but does not clear the RTC RAM memory contents).
Receive
Serial Advanced Technology Attachment
Serial ATA, an industry specification of the interface for storage controllers and devices.
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Table 1-3.
Acronym Table
Term
Description
SEC
Single-bit Error Correct
SEC/DED
Single Error Correct/Double Error Detect - A specific data protection algorithm that
distributes data and ECC across 144 bits. Enables correction of single bit errors. Allows
detection of double bit errors.
SOP/SOF
Start Of Packet / Start Of Frame
SMM
System Management Mode
SPD
Serial Presence Detect
SSU
Security Services Unit
STR
Suspend To Ram
TAP
Test Access Port used for testability and debug of the component.
TX
1.5
Transmit
TCO
Total Cost of Ownership
TCP
Transmission Control Protocol
TDM
Time Division Multiplexed
TDR
Time Domain Reflectometry
TFL
Transit FIFO Level
TID
See Transaction Identifier in Table 1-4
USB
Universal Serial Bus
VCMI
IA-32 core, IA-32 Core interface, Memory controller hub, I/O controller hub
VLAN
Virtual Local Area Network
WDT
Watch Dog Timer
Glossary
This section presents a glossary for this document.
Table 1-4.
Glossary Table (Sheet 1 of 5)
Term
µBGA
Definition
Micro Ball Grid Array
AIOC Direct (AD)
AIOC Direct (AD) memory regions are not coherent with IA caches when accessed from AIOC
agents. Accesses to these memory regions enter the memory system through the Memory
Controller avoiding the IMCH. Memory regions that are not coherent with IA caches need not
be accessible to the IA CPU.
Agent
A logical device connected to a bus or shared interconnect that can either initiate accesses or
be the target of accesses.
ALT Access Mode
Mode to allow the reading of write-only registers, usually used when saving/restoring register
content for power management sleep state implementations.
Anti-Etch
Any plane-split, void or cutout in a VCC or GND plane is referred to as an anti-etch.
Asserted
Signal is set to a level that represents logical true.
Asynchronous
1. An event that causes a change in state with no relationship to a clock signal. 2. When
applied to transactions or a stream of transactions, a classification for those that do not require
service within a fixed time interval.
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Table 1-4.
Glossary Table (Sheet 2 of 5)
Term
Definition
Atomic operation
A series of two or more transactions to a device by the same initiator which are guaranteed to
complete without intervening accesses by a different master. Most commonly required for a
read-modify-write (RMW) operation.
Block Locking
Buffer
Ability to lock the FWH’s blocks to write-protect, read-protect, or open state.
1. A random access memory structure. 2. The term I/O buffer is also used to describe a lowlevel input receiver and output driver combination.
Cx States
Processor power states (Cx states) are processor power consumption and thermal
management states within the global working state, G0.
• C0: Processor power state - While the processor is in this state, it executes instructions.
• C1: Processor power state - This power state has the lowest latency. The hardware latency
in this state must be low enough that the operating software does not consider the latency
aspect of the state when deciding whether to use it.
• C2: Processor power state - This state offers improved power savings over the C1 state.
The worst-case hardware latency for this state is provided via the ACPI system firmware
and operating software can use this information to determine when the C1 state should be
used instead of the C2 state.
• C3: Processor power state - This state is not supported. The C3 state offers improved
power savings over the C1 and C2 states. The worst-case hardware latency for this state is
provided via the ACPI system firmware and the operating software can use this information
to determine when the C2 state should be used instead of C3 state. While in the C3 state,
the processor’s caches maintain state but ignore any snoops.
Cache Line
The unit of memory that is copied to and individually tracked in a cache. Specifically, 64 bytes
of data or instructions aligned on a 64-byte physical address boundary.
Cfg
Character
CMI
Used as a qualifier for transactions that target PCI configuration address space.
The raw data Byte in an encoded system (i.e., the 8b value in a 8b/10b encoding scheme). This
is the meaningful quantum of information to be transmitted or that is received across an
encoded transmission path.
IA-32 Core interface, Memory controller hub, I/O controller hub
Coherent (C)
Transactions that ensure that the processor’s view of memory through the cache is consistent
with that obtained through the I/O subsystem. In EP80579 integrated processor, Coherent (C)
memory regions are coherent with IA caches when accessed from AIOC agents. Accesses to
these memory regions enter the memory system through the IMCH. Memory regions that are
coherent with IA caches must be accessible to the IA CPU.
Command
The distinct phases, cycles, or packets that make up a transaction. Requests and Completions
are referred to generically as Commands.
Completion
A packet, phase, or cycle used to terminate a Transaction on a interface, or within a
component. A Completion will always refer to a preceding Request and may or may not include
data and/or other information.
Core Power Well
Cyclic Redundancy Check
Deasserted
Main system power, turns off in S3 – S5
A number derived from, and stored or transmitted with, a block of data in order to detect
corruption. By recalculating the CRC and comparing it to the value originally transmitted, the
receiver can detect some types of transmission errors.
Signal is set to a level that represents logical false.
Deferred Transaction
A processor bus Split Transaction. The requesting agent receives a Deferred Response which
allows other transactions to occur on the bus. Later, the response agent completes the original
request with a separate Deferred Reply transaction.
Delayed Transaction
A transaction where the target retries an initial request, but unknown to the initiator, forwards
or services the request on behalf of the initiator and stores the completion or the result of the
request. The original initiator subsequently reissues the request and receives the stored
completion.
Direct Memory Access
Method of accessing memory on a system without interrupting the processors on that system.
Downstream
Describes commands or data flowing away from the processor-memory complex and toward I/
O. The terms Upstream and Downstream are never used to describe transactions as a whole.
(e.g. Downstream data may be the result of an Outbound Write, or an Inbound Read. The
Completion to an Inbound Read travels Downstream.)
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Table 1-4.
Glossary Table (Sheet 3 of 5)
Term
Definition
Full Duplex
A connection or channel that allows data or messages to be transmitted in opposite directions
simultaneously.
Gb/s
Gigabits per second (109 bits per second)
GB/s
Gigabytes per second (109 bytes per second)
Global visibility
An operation is said to be globally visible when all side-effects of the operation are visible to
every observer in the system. For example, a write to some resource (e.g., memory location,
control register, etc.) R achieves global visibility when a read of R by all other agents is
guaranteed to return the new value.
Gx States
Global system states (Gx states) apply to the entire system and are visible to the user.
• G3: Mechanical off - A computer state that is entered and left by a mechanical switch. It is
implied by the entry of this off state through a mechanical means that no electrical current
is running through the circuitry and that it can be worked on without damaging the
hardware or endangering service personnel.
• G2/S5: Soft Off - A computer state where the computer consumes a minimal amount of
power.
• G1: Sleeping - A computer state where the computer consumes a small amount of power,
user mode threads are not being executed, and the system “appears” to be off (from an
end user’s perspective, the display is off, and so on).
• G0: Working - A computer state where the system dispatches user mode (application)
threads and they execute. In this state, peripheral devices are having their power state
changed dynamically.
Half Duplex
A connection or channel that allows data or messages to be transmitted in either direction, but
not simultaneously.
Implicit Writeback
A snoop-initiated data transfer from the bus agent with the modified Cache Line to the memory
controller due to an access to that line.
Inbound
A transaction where the request destination is the processor-memory complex and is sourced
from I/O. The terms Inbound and Outbound refer to transactions as a whole and never to
Requests or Completions in isolation. (e.g., an Inbound Read generates Downstream data,
whereas an Inbound Write has Upstream data. Even more confusing, the Completion to an
Inbound Read travels Downstream.)
Industry Standard Architecture
A 16-bit bus architecture associated with the IBM AT motherboard designed to connect
motherboard circuitry to expansion card devices that is now considered Legacy.
Initiator
The source of requests. [IBA] An agent sending a request packet on 3GIO is referred to as the
Initiator for that Transaction. The Initiator may receive a completion for the Request. [3GIO]
ISA Regime
A special legacy mode to support ISA-based devices which have been integrated into the
chipset. It opens a dedicated channel from the peripheral device to the processor bus. While in
this mode, the legacy device is granted exclusive accesses to memory and the ability to use
Tenured Transactions.
Isochronous
A classification of transactions or a stream of transactions that require service within a fixed
time interval.
Lane
A set of differential signal pairs, one pair for transmission and one pair for reception. A by-N
Link is composed of N Lanes.
Layer
A level of abstraction commonly used in interface specifications as a tool to group elements
related to a basic function of the interface within a layer and to identify key interactions
between layers.
Legacy
Link
LPC Bus
Master
Mbyte/s
Mem
Functional requirements handed down from previous chipsets, or PC compatibility
requirements from the past.
The collection of two Ports and their interconnecting Lanes. A Link is a dual simplex
communications path between two components.
Low Pin Count connection used to connect to the super I/O device.
A device or logical entity that is capable of initiating transactions. A Master is any potential
Initiator.
Megabytes per second (106 bytes per second)
Used as a qualifier for transactions that target memory space. (For example, a Mem read to I/
O.)
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Table 1-4.
Glossary Table (Sheet 4 of 5)
Term
Metastability
Multi Media Timer (MMT)
Definition
A characteristic of flip flops that describes the state where the output becomes nondeterministic. Most commonly caused by a setup or hold time violation.
See High Precision Event Timer (HPET) in Table 1-3.
Non-Coherent
Transactions that may cause the processor’s view of memory through the cache to be different
than that obtained through the I/O subsystem.
North
Usually refers to bridges. The bridge or device that is closer to the processor-memory complex.
Ordering
Refers to the order in which signals and/or memory accesses to different locations must reach
global visibility to ensure some behavior. Note that this excludes the “ordering” necessary to
prevent data hazards which are accesses to the same location.
Outbound
A transaction where the request destination is I/O and is sourced from the processor-memory
complex. The terms Inbound and Outbound refer to transactions as a whole and never to
Requests or Completions in isolation. (For example, an Outbound Read generates Upstream
data, whereas an Outbound Write has Downstream data. Even more confusing, the Completion
to an Outbound Read travels Upstream.)
OWord
128 bits of data on a naturally aligned sixteen-byte boundary (e.g., the least significant four
bits of the byte address are b”0000”). This is the native size of the IMCH datapath.
Packet
The indivisible unit of data transfer and routing, consisting of a header, data, and CRC.
PCI Reset
Peer-to-Peer
PCIRST#. This is the secondary PCI Bus reset signal. It is a logical OR of the primary interface
PLTRST# signal and the state of the Secondary Bus Reset bit.
Transactions that occur between two devices independent of memory or the processor.
Platform Reset
IICH asserts PLTRST# to reset devices that reside on the primary PCI bus. The IICH asserts
PLTRST# during power-up and when a hard reset sequence is initiated through the CF9h
register. PLTRST# is driven inactive a minimum of 1 ms after both PWROK and VRMPWRGD are
driven high. PLTRST# is driven for a minimum of 1 ms when initiated through the CF9h
register.
Plesiochronous
From Greek, meaning almost synchronous. Describes signals that have the same nominal
digital rate, but are synchronized on different clocks. Any variation in rate is constrained within
specified limits, which allows a device to process the data signal without buffer underflow or
overflow by making periodic compensating adjustments that repeat or delete dummy data bits.
However, there is no limit to the phase difference that can accumulate between the signals over
time.
Port
1. Logically, an interface between a component and a PCI Express* Link.
2. Physically, a group of Transmitters and Receivers located on the same chip that define a
Link.
Posted
A Transaction that is considered complete by the initiating agent or source before it actually
completes at the Target of the Request or destination. All agents or devices handling the
Request on behalf of the original Initiator must then treat the Transaction as being system
visible from the initiating interface all the way to the final destination. Commonly refers to
memory writes.
Push Model
Queue
Receiver
Method of messaging or data transfer that predominately uses writes instead of reads.
A first-in first-out (FIFO) structure.
1. The Agent that receives a Packet across an interface regardless of whether it is the ultimate
destination of the packet. 2. More narrowly, the circuitry required to convert incoming signals
from the physical medium to more perceptible forms.
Request
A packet, phase, or cycle used to initiate a Transaction on a interface, or within a component.
Reserved
The contents or undefined states or information that are not defined at this time. Using any
reserved area is not permitted. Reserved register bits must be set to 0. However, when stated,
there may be specific instances where a reserved register is either non-zero, or there may be a
requirement to make it non-zero.
Resume Power Well
Trickle from power supply, only turns off when power is disconnected from wall.
Resume Reset
Signal that resets the parts of the IICH in the resume power well, generated when the trickle
supply turns on.
RTC Power Well
Powered by a coin cell battery and only turns off when the battery is drained. Powers the RTC
and some resume events.
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Table 1-4.
Glossary Table (Sheet 5 of 5)
Term
Definition
Sx States
Sleeping states (Sx states) are types of sleeping states within the global sleeping state, G1.
• S5: Soft Off state. The main memory power plane is shut down in addition to the clock
synthesizer and core well power planes for the processor and CMI. The CMI resume well is
still powered.
• S4: Sleeping state - This state is only used to transition to or from the S5 state. The S4
state is not a supported power management state in CMI.
• S3: Suspend to RAM (STR) state - The clock synthesizer and core well power planes for the
processor and CMI are shut down, but the main memory power plane and the CMI resume
well remain active. All clocks from synthesizers are shut down during the S3 state.
• S0: Awake state - Power Management state when all power planes are active.
Simplex
A connection or channel that allows data or messages to be transmitted in one direction only.
SMBus
System Management Bus. A two-wire interface through which various system components may
communicate.
Snooping
A means of ensuring cache coherency by monitoring all memory accesses on a common multidrop bus to determine if an access is to information resident within a cache.
South
South Port
Split Lock Sequence
Usually refers to bridges. The bridge or device that is further from the processor-memory
complex.
The PCI Express* downstream root port(s) on the IICH.
A sequence of transactions that occurs when the target of a lock operation is split across a
processor bus data alignment or Cache Line boundary, resulting in two read transactions and
two write transactions to accomplish a read-modify-write operation.
Split Transaction
A transaction that consists of distinct Request and Completion phases or packets that allow use
of bus, or interconnect, by other transactions while the Target is servicing the Request.
Symbol
An expanded and encoded representation of a data Byte in an encoded system (e.g., the 10b
value in a 8b/10b encoding scheme). This is the value that is transmitted over the physical
medium.
Symbol Time
Target
Tenured Transaction
Transaction
The amount of time required to transmit a symbol.
A device that responds to bus Transactions. The agent receiving a request packet is referred to
as the Target for that Transaction.
A transaction that holds the bus or interconnect until complete, effectively blocking all other
transactions while the Target is servicing the Request.
An overloaded term that represents an operation between two or more agents that can be
comprised of multiple phases, cycles, or packets.
Transaction Identifier
A multi-bit field used to uniquely identify a transaction. Commonly used to relate a Completion
with its originating Request in a Split Transaction system.
Transmitter
1. The Agent that sends a Packet across an interface regardless of whether it was the original
generator of the packet. 2. More narrowly, the circuitry required to drive signals onto the
physical medium.
Upstream
Describes commands or data flowing toward the processor-memory complex and away from I/
O. The terms Upstream and Downstream are never used to describe transactions as a whole.
(For example, Upstream data may be the result of an Inbound Write, or an Outbound Read.
The Completion to an Outbound Read travels Upstream.)
VCMI
IA-32 core, IA-32 Core interface, Memory controller hub, I/O controller hub
§§
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2.0
Architectural Overview
2.1
Overview
This chapter provides an overview of the Intel® EP80579 Integrated Processor product
line architecture. Section 2.1.1, “Block Summary” gives a high-level summary for each
of the major blocks and their internal interfaces. Section 2.1.2, “External Interfaces”
reviews the EP80579’s external chip interfaces.
The block diagrams in Figure 2-1 and Figure 2-1 show the major EP80579 blocks.
2.1.1
Block Summary
• The EP80579 IA-32 core runs at 600, 1066, and 1200 MHz with an internal 400 or
533 MHz front-side bus (FSB) interface. The IA-32 core features a 256 Kilobyte 2way level 2 cache (L2).
• The EP80579 IMCH provides the main path to memory for the IA-32 core and all
peripherals that perform coherent I/O (e.g. PCI Express*, the IICH to coherent
memory). The IMCH includes the four channel DMA engine as well as a PCI
Express* root complex with 1x8, 2x4, or 2x1 interfaces. The memory controller
operates at 200-266-333-400 MHz, depending on external DDR and SKU
configuration. Depending on SKU, the EP80579 supports a single channel, 64-bit
with ECC, memory controller for external DDR-2 memory (400, 533, 667, and 800
MHz). The EP80579 also supports a 32-bit with ECC mode for cost-sensitive
applications.
• The EP80579 IICH provides a set of PC platform-compatible I/O devices that
include two SATA1.0/2.0, one USB1.1/2.0 host controller supporting two USB
ports, and two serial 16550 compatible UART interfaces. The IICH complex
interfaces to the MCH through the “NSI” internal bus interface.
• The EP80579 Acceleration and I/O Complex (AIOC) supports three Gigabit
Ethernet media access controllers, MDIO, Local Expansion Bus (LEB), two
Controller Area Network (CAN) interfaces, IEEE1588 (2-GbE and 2-CAN ports), and
SSP. In addition some SKU have three high-speed serial TDM interfaces that
provide up to 12 T1/E1. ASU and SSU provide the high performance packet
processing and accelerate common security capability.
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Figure 2-1.
Intel® EP80579 Integrated Processor Block Diagram
Local
Expansion
Bus
MDIO (x1)
CAN (x2)
SSP (x1)
IEEE-1588
(16b @
80 MHz)
GigE
MAC
GigE
MAC
GigE
MAC
#2
#1
#0
Acceleration and I/O Complex
IA Complex
IMCH
(256 KB)
L2 Cache
IA-32 core
Transparent
PCI-to-PCI Bridge
FSB
EDMA
Memory Controller Hub
IICH
APIC, DMA, Timers, Watch Dog
Timer, RTC, HPET (x3)
PCI
Express
Interface
(x1)
SPI
LPC1.1
SATA 2.0
USB 2.0
(x2)
(x2)
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UART (x2)
GPIO (x36)
SMBus (x2)
(Gen1,
1x8, 2x4 or
2x1 root
complex)
Memory Controller
(DDR-2 400/533/667/800,
64b with ECC)
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Figure 2-2.
Intel® EP80579 Integrated Processor with Intel® QuickAssist Technology
Block Diagram
Acceleration
‡
Services Unit
Local
Expansion
Bus
Security
‡
Services Unit
(16b @
80 MHz)
(3DES, AES, (A)RC4,
MD5, SHA-x, PKE,
TRNG)
MDIO (x1)
CAN (x2)
SSP (x1)
IEEE-1588
TDM
‡
Interface
GigE
MAC
GigE
MAC
GigE
MAC
(12 E1/T1)
#2
#1
#0
256 KB
ASU SRAM
‡ Enabling software required.
Acceleration and I/O Complex
IA Complex
IMCH
(256 KB)
L2 Cache
IA-32 core
Transparent
PCI-to-PCI Bridge
FSB
EDMA
Memory Controller Hub
IICH
APIC, DMA, Timers, Watch Dog
Timer, RTC, HPET (x3)
PCI
Express
Interface
(x1)
SPI
LPC1.1
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SATA 2.0
USB 2.0
(x2)
(x2)
UART (x2)
GPIO (x36)
SMBus (x2)
(Gen1,
1x8, 2x4 or
2x1 root
complex)
Memory Controller
(DDR-2 400/533/667/800,
64b with ECC)
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2.1.2
External Interfaces
Table 2-1 summarizes the key features of the external interfaces.
Table 2-1.
EP80579 External Interface Summary
Name
Qty.
Description
External DDR
Memory
1
Single channel memory controller with an ECC enabled 64-bit interface that,
depending on SKU, supports external DDR-2 memory (400, 533, 667 and 800
MHz). Minimum memory size is 128 MB (in 32 bit mode). Maximum memory size
is 4GB. The EP80579 integrated processor also supports a 32-bit mode (with
ECC) for cost-sensitive applications.
PCI Express*
(root)
1
Supports 1x8, 2x4, or 2x1 configurations as a root complex.
Gigabit Ethernet
3
10/100/1000 Gigabit Ethernet MACs with RGMII/RMII interface. Two of the three
ports support IEEE 1588 hardware assist.
TDM
3
8.192 MHz high-speed synchronous serial TDM interfaces that support up to 12
T1/E1 links (SKU dependent) with Intel software driver provided for HDLC
support.
Local Expansion
Bus
1
25/16-bit 80MHz local expansion bus with 8 programmable chip selects.
USB 2.0
1
Universal Serial Bus 2.0 host controller interface, supports two USB ports (shared
with USB1.1 ports)
USB 1.1
1
Universal Serial Bus 1.1 host controller interface, supports two USB ports (shared
with USB2.0 ports)
LPC
1
Low Pin Count Bus (LPC) interface to attached PC compatible boot flash memory
up to 64MB.
SPI
1
Serial Peripheral Interface (SPI).
Programmable General Purpose I/O (GPIO) pins. Note, Intel recomends using this
interface to boot from. Of the 36pins, many have alternate functions defined.
GPIO
36
SMBus/I2C
2
I2C compatible SMBus2.0 connections.
UART
2
16550 compatible asynchronous serial ports that support data rate of at least
115Kbits/sec.
SATA
2
SATA1.0 or 2.0 used to attached external hard drives.
SSP
1
Synchronous Serial Port
CAN
2
Controller Area Network interfaces.
MDIO
1
MDIO interface to support the ethernet interfaces.
IEEE-1588
1
IEEE-1588 Hardware Assist
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2.1.3
Frequencies and Gear Ratios
This section discusses frequencies and gear ratios.
The IA core used in the EP80579 is an IA-32 core, and can run at frequencies between
600 and 1200 MHz (actually supported CPU frequencies vary by SKU, see
Chapter 47.0, “SKUs, Power Savings and Pre-Boot Firmware”). Based on divider ratios
in its PLL design, the IA-32 core imposes a 6:1 minimum core/bus frequency ratio. This
limits maximum FSB frequency to 400 or 533 MHz front-side bus (FSB) interface.
The IA-32 core/FSB frequency combinations supported are listed in Table 2-2.
Table 2-2.
IA-32 core / FSB Frequency Ratios (depends on SKU and configuration)
IA-32 core
[MHz]
FSB
[MHz]
Ratio
600
400
6:1
1066
533
8:1
1200
533
9:1
Table 2-3 summarizes the memory controller clock ratios.
Table 2-3.
2.2
Memory Controller Frequencies
DDR Clock
[MHz]
DDR Technology
200
DDR2-400
266
DDR2-533
333
DDR2-667
400
DDR2-800
Signaling Architecture
As defined in Table 2-4, the EP80579 supports communication between the IA, AIOC
devices (ASU, SSU, internal I/O devices) and externally attached bus master (PCI
Express* through different memory types using a variety of operations.
Table 2-4.
Summary of Communication
Targeted Memory Typea
Operation
Read, Write
Atomic
Agent
External DRAM
(Coherent)
External DRAM
(AIOC Direct)
IA
X
Xb
ASU
X
X
PCI-E DMA, EDMA
X
Xb
GbE
X
X
IA
X
-
ASU
X
X
PCI-E DMA, EDMA
-
-
GbE
-
-
a. “X” cells are supported with normal or MMIO accesses and “-” cells are not supported.
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b. Agents in the IA-32 core may access AIOC-Direct memory (non-coherent) via uncacheable 1, 2 or 4-byte IA
loads/store, IA MMX 8-byte MOVQ instructions or 64-byte DMA transfers. While such IA-32 core accesses to
AIOC-Direct memory are not ordered with respect to other ASU memory traffic, the AIOC-Direct memory
supports limited one-way communication in which IA agent (or the Internal PCI agent) is the sole writer and
the internal PCI agent (or the IA agent) views such memory locations as read-only. Hardware will ensure that
self-aligned 1,2, 4, 8 and 64-byte updates will be atomically visible to all readers.
The EP80579 allows signaling to occur between IA, AIOC complex, and externallyattached agents in the appropriate native signaling format.
The EP80579 supports basic producer/consumer behavior between agents.
Because the AIOC complex devices are exposed to the IA platform as PCI devices, they
follow PCI ordering semantics when interacting with IA. This enables two fundamental
producer/consumer models in coherent memory: the polled and interrupt methods.
For the Polled method:
1. Producer writes data to location “X” in Coherent Memory.
2. Producer sets flag to location “Y” in Coherent Memory
3. Consumer waits for flag to be set in Coherent Memory
4. Consumer read data from location “X” in Coherent Memory
To ensure this behavior, agents generating traffic into the IMCH must ensure that the
writes originating from an agent are globally observable in the same order. In the
above case X and Y must be globally observable in the same order.
For the Interrupt method:
1. Producer writes data to location “X” in Coherent Memory.
2. Producer generates an interrupt to Consumer (asynchronous signal)
3. Consumer reads interrupt status from Producer’s address space. Consumer waits
for read to complete before issuing the next transaction.
4. Consumer reads data from location “X” in Coherent Memory
To ensure this behavior, an MMIO read issued to the PCI device (item 3 above) after a
write that originated from this PCI device (item 1 above) must not complete out of
order. The read completion must push ahead (flush) the write.
Also the MMIO read (item 3 above) should be to a location that is in the device. In the
EP80579, it should not be to the PCI configuration registers but the device registers
pointed to by the PCI BAR1. This ensures that IA device driver software for the
EP80579 is not required to include explicit memory fence operations to enable
producer-consumer synchronization for interrupt handling. Examples:
1. GigE ⇔ IA : GigE placing received data in coherent DRAM and interrupting IA, IA
issuing a GigE CSR read, whose read completion must serialize the received DRAM
data stream.
2. TDM ⇔ IA : TDM placing received data in coherent DRAM, then interrupting the IA,
then IA gets a pointer to the data. An IA pointer dereference from the IA must see
the TDM DRAM data.
3. ASU ⇔ IA : ASU placing data in coherent DRAM, then interrupting the IA, then IA
gets a pointer to the data. An IA pointer dereference from the IA must see the ASU
DRAM data.
1. The reason for this requirement is that the MCH config bus used to access the PCI configuration registers does not serialize
the EP80579 internal PCI bus.
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For communication using memory that is not coherent with the IA processor caches, or
for direct communication between AIOC agents (e.g. between ASU, TDM, and GigE
devices), the EP80579 may require software to insert explicit fencing operations to
ensure correct producer/consumer behavior. Details are discussed in Chapter 4.0,
“Signaling”.
2.3
DMA and Peer-to-Peer Data Transfers
The EP80579 provides multiple DMA and DMA-like features that are summarized here:
• IMCH EDMA Engine: The four channel IMCH “Enhanced DMA” (EDMA) engine
which supports DWORD aligned DMA. The EDMA engine supports memory-tomemory and memory-to-PCIe transfers. Read DMA granularity ranges from 1 byte
to 4 Kilobytes. Write DMA granularity ranges from 1 to 256 bytes. The EDMA engine
supports different source/target byte alignments that are important for packet
processing, and is only programmable via IA PCI configuration space with
completions signaled via IA interrupts. The EDMA engine can support burst data
movement between “AIOC-direct memory” and IA coherent memory.
• IICH DMA: Supports IICH agents to/from memory, this is only used by USB and
SATA.
• LPC DMA: Supports LPC agents. See Chapter 20.0, “LPC DMA”.
• No Peer-to-Peer Reads: The IMCH does not support peer-to-peer reads.
Table 2-5 lists the supported DMA and peer-to-peer data transfer options.
Table 2-5.
Usage
Model#
DMA and Peer-to-Peer Data Transfer Options
Operation
Source
Destination
Initiator
Owner (Software)
1
PCI DMA read
DRAM
PCI Ex device
PCI Ex Device
IA device driver
2
PCI DMA write
PCI Ex Device
DRAM
PCI Ex Device
IA device driver
3
AIOC read
DRAM or AIOC
device
AIOC device (GE)
Device
IA, ASU
4
AIOC write
AIOC device
DRAM or AIOC device
(GE)
Device
IA, ASU
5
AIOC 3rd party read
DRAM
AIOC device (SSU)
ASU
ASU
6
AIOC 3rd party write
AIOC device (SSU)
DRAM
ASU
ASU
7
Peer-to-Peer PCI
Read
8
Peer-to-Peer PCI
Write
AIOC Master or PCI
Ex Device
PCI Ex Device only
AIOC Master
or PCI Ex Device
AIOC Master Device
Driver
9
Mem-to-Mem
DRAM
DRAM
EDMA Engine
IA
10
Mem-to-Memory
Mapped IO
DRAM
PCI Ex or AIOC
device
EDMA Engine
IA
Not Supported
§§
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3.0
Platform Memory and Device Configuration
3.1
Overview
This chapter presents the views of the major address spaces and device configuration
structures as seen by various internal and external agents. Three related aspects are
covered:
• The memory maps seen by various internal and external agents.
• The endianness seen by various agents and mechanisms the EP80579 uses to allow
communication between agents with different endianness expectations.
• The PCI configuration infrastructure, which the EP80579 exposes through its
memory maps.
3.1.1
Configuration Objectives
The EP80579 device and configuration model operates in a system-on-a-chip
environment and blends the architectures of many disparate components into a unified
whole. The major goals for the device configuration and access architecture include:
• Provide a configuration and access model that is aligned with existing IA platform
algorithms.
• Support a unified address space model.
The IA-32 core is the primary agent responsible for device configuration. This is true
across all supported SKUs.
To provide device configuration and operation capabilities that are aligned with the IA
platform, the EP80579 uses the existing PCI infrastructure to expose on-die softwarevisible sub-blocks as devices on the PCI fabric. Figure 3-1 presents a logical overview
of this organization.
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Figure 3-1.
Device-Centric Logical View of EP80579 Devices
PCI Bus 0
PCI Host
Bridge
DRAM
EDMA
Transparent
PCI-to-PCI Bridge
USB
PCI Bus M
IA CPU
ASU
IMCH / IICH Devices
SSU
GbE
AIOC Devices
The on-die IMCH and IICH devices materialize on PCI bus 0 while the AIOC devices
materialize on PCI bus “M” that is behind a transparent PCI-to-PCI bridge on PCI bus 0
(the bus that the internal IMCH and IICH devices use). For simplicity, the figure does
not show external devices.
3.1.2
Terminology and Conventions
Throughout this chapter, we will use the generic term “device” to refer to either a PCI
device or a function of a PCI device. The text will be explicit when the distinction
between device and function is important.
Addresses are always in hexadecimal and broken into 16-bit segments, for example,
0_FEED_BEEF. When the distinction is important and not obvious, addresses are
subscripted with “V”, “P”, or “S” for virtual, physical, or system address spaces,
respectively.
The EP80579 addresses its DRAM in units of 8-byte quadwords. Before assigning byte
addresses to the byte lanes in DRAM, we will refer to the locations as byte lane A
through H as Table 3-1 illustrates.
Table 3-1.
Main Memory DRAM Organization
Address
Byte
Lane H
Byte
Lane G
Byte
Lane F
Byte
Lane E
Byte
Lane D
Byte
Lane C
Byte
Lane B
Byte
Lane A
0
0H
0G
0F
0E
0D
0C
0B
0A
8
8H
8G
8F
8E
8D
8C
8B
8A
16
16H
16G
16F
16E
16D
16C
16B
16A
The byte located in address 0, lane A is referred to as 0A, the byte in address 0 lane B
is 0B, etc.
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3.2
IA Platform Infrastructure
The IMCH and IICH blocks (which, along with the IA-32 core, are collectively referred
to as the VCMI) in the EP80579 provide an IA platform infrastructure with respect to
endianness, address spaces and memory maps, configuration, etc.
This section focuses on the IA views and expectations around the endianness, address
spaces and memory maps, and configuration for a basic IA platform. The EP80579
operates within this framework. These discussions highlight how and where the
EP80579 differs from the framework. For additional detailed information on the IA
infrastructure in the EP80579 specifically, see Section 9.0, “CMI Introduction”, which
discusses the IMCH implementation.
3.2.1
IA Platform View of Endianness
All memory in an EP80579 platform is little-endian to match requirements and
expectations of an IA platform. The byte lanes (see Table 3-1 on page 112) are
connected from the memory interface to the IMCH such that little-endian IA-32 core
sees “byte 0” of a quad-word in memory in byte lane A and “byte 7” of a quad-word in
memory in byte lane H.
Consider the following C code:
char c, *cp;
// 1 byte
short s, *sp;
// 2 bytes
long l, *lp;
// 4 bytes
long long ll, *llp;
// 8 bytes
cp = sp = lp = llp = (void *) 0x8;
// QW address 1
c
= *cp;
s
= *sp;
l
= *lp;
ll = *llp;
Executing this code on the IA-32 core in an EP80579 yields the following results:
c
== 8A
s
== 8B8A
l
== 8D8C8B8A
ll == 8H8G8F8E8D8C8B8A
Where the right-hand values in these results use the notation that Table 3-1 on
page 112 in Section 3.1.2 describes to identify the byte lanes and address.
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3.2.2
IA Platform View of Configuration
Because the IMCH and IICH blocks in the EP80579 come from an IA heritage, the
EP80579 exposes much of the functionality in these blocks through a PCI
infrastructure. The EP80579 extends this PCI infrastructure to expose the functionality
in the AIOC, as Section 3.7, “PCI Configuration” on page 119 describes.
Before describing how the AIOC integrates with the IA-based IMCH and IICH blocks, it
is helpful to consider how the PCI exposes IMCH and IICH functionality. Logically, the
software-visible sub-blocks of the IMCH and IICH materialize as PCI devices and
functions1 on PCI bus 0 of the system through three independent address spaces:
• Configuration Space: Each function of each device has at least 256B of
configuration space that is mapped to a fixed location by the platform (PCI
Express* devices can provide for larger configuration spaces). This space provides
system software with basic information on the device and allows for deviceindependent configuration.
• Memory-Mapped I/O (MMIO) and I/O Spaces: Each function of each device
can request up to six MMIO and I/O regions of device-specified sizes to be mapped
into physical address space through base address registers in the configuration
header. System software selects the base address of each region. These spaces
support device-specific operation such as access to device-specific control
registers.
Of the thirty-two possible device slots on bus 0, five slots are reserved for softwarevisible blocks in the EP80579 IMCH and IICH and remainder are unused.
In general, the IMCH claims configuration accesses (i.e., those accesses that target
configuration space) to device numbers 0, 1, 2, and 3 of bus 0 and routes configuration
accesses to the remaining devices to the IICH over an internal NSI interface using Type
0 PCI configuration transactions2 (see Section 13.2, “Platform Configuration Structure
Conceptual Overview” and Section 13.3, “Routing Configuration Accesses”. In the
EP80579 design, transactions to bus 0 devices that are sent through NSI to the IICH
and unclaimed by the IICH will master abort.
Figure 3-2 presents a logical view of the EP80579 infrastructure for the software-visible
blocks in the IICH and IMCH.
1. Except where the distinction is important, this document uses the term “device” to refer to both devices and functions in the
PCI sense of these words.
2. Configuration transactions take the Type 1 form while in transit through the PCI fabric to their destination bus; upon reaching
their destination bus, they become Type 0 transactions.
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Dev: 31
IICH
IMCH
IA
SATA, SPI,
LPC, SMBus
USB
Dev: 29
Dev: 2,3
PCI-Ex
Dev: 1
EDMA
IMCH, DDR
Dev: 0
PCI Bus 0
NSI
Logical Overview of the CMI PCI Infrastructure
NSI
Figure 3-2.
Table 3-2 summarizes the address space requirements (both in memory and I/O space)
of the IMCH and IICH.
Table 3-2.
Basic CMI Platform Address Space Requirements for IMCH and IICH Devices
PCI
Block
Mem,
I/O
Size
0
Northbridge
Mem
4KB
1
DRAM, Error Handling
N/A
N/A
1
0
EDMA
Mem
4KB
2
0
PCI-Express (HSI A0)
×8 or ×4
N/A
N/A
3
0
PCI-Express (HSI A1)
×4
N/A
N/A
0
USB 1.1
I/O
32B
USBIOBAR (see Section 25.1.1.9,
“USBIOBAR - Base Address Register”)
7
USB 2.0
Mem
1KB
MBAR (see Section 26.2.1.10, “Offset 10h:
MBAR - Memory Base Address Register”)
Unit
Dev.
IICH
IMCH
0
Fn.
29
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Register
SMRBASE (see Section 16.1.1.9, “Offset
14h: SMRBASE - System Memory RCOMP
Base Address Register”)
EDMALBAR (see Section 16.3.1.9, “Offset
10h: EDMALBAR - EDMA Low Base
Address Register”
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Table 3-2.
Basic CMI Platform Address Space Requirements for IMCH and IICH Devices
0
31
LPC/SPI
2
SATA
3
SMBUS
N/A
N/A
I/O
8B
PCMDBA (see Section 23.1.1.8, “Offset
10h: PCMDBA – Primary Command Block
Base Address Register”)
I/O
4B
PCTLBA (see Section 23.1.1.9, “Offset
14h: PCTLBA – Primary Control Block Base
Address Register”)
I/O
8B
SCMDBA (see Section 23.1.1.10, “Offset
18h: SCMDBA – Secondary Command
Block Base Address Register”)
I/O
4B
SCTLBA
I/O
16B
LBAR (see Section 23.1.1.12, “Offset 20h:
LBAR – Legacy Bus Master Base Address
Register”)
Mem
1KB
ABAR (see Section 23.1.1.13, “Offset 24h:
ABAR – AHCI Base Address Register”)
N/A
N/A
The IMCH and IICH devices in the EP80579 on PCI bus 0 allocate 18KB of memory
space above and beyond the PCI L allocations in Figure 3-2 and 72B of I/O space
through PCI BARs (this memory could be allocated in the “open” regions in Figure 3-2).
This table does not include any memory regions that external devices (i.e., those
attached to a IMCH PCI Express* port) or AIOC devices might allocate.
In addition to the IMCH and IICH devices, the EP80579 includes an IA-32 core that
provides MSRs and other configuration structures.
3.3
High-Level Views
This section presents an overview of some of the general characteristics of the agents
that the various EP80579 memory maps expose.
3.3.1
Characteristics of External System Memory (DRAM)
The address spaces in the EP80579 expose up to 4GB of physical system memory, in
the form of DRAM, to be accessed by both on- and off-die agents.
Table 3-3.
Memory Regions
Region
Managed By
Accesses to System Memory by AIOC
Agents Coherent with IA Caches?
Contents
IA O/S
IA O/S
Y
IA O/S and application code
and data structures
IA/ASU Shared
(Coherent)
EP80579 Drivera
Y
IA and AIOC shared data
structures
IA/ASU Shared
(AIOC-Direct)
EP80579 Drivera
N
AIOC data structures; IA-32
core may access a portion
via the EP80579 driver
a. The EP80579 Driver includes the EP80579-specific software stacks that run on the IA, ASU, etc.
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Of the regions in Table 3-3, the “IA/ASU Shared (Coherent)” and “IA/ASU Shared
(AIOC-Direct)” regions are not managed by the IA O/S. The EP80579 software expects
that the BIOS carves this memory out of the memory map early in the boot process
and sets it aside for use by the Intel® EP80579 Integrated Processor with Intel®
QuickAssist Technology software stack. As a result, the IA O/S does not allocate,
manage, page, etc. these regions of memory.
The regions in Table 3-3 fall into one of two categories with respect to IA cache
coherency: one that is coherent with IA caches for AIOC accesses and one that is not.
It is important to note that the coherent/non-coherent category of a region affects only
how the AIOC hardware handles a DRAM accesses. The category, in and of itself, does
not have any implications on how IA must always access the region.
The EP80579 expects that, in general, all agents in the system can access all memory,
consistent with their addressing capabilities, in the three regions that Table 3-3 lists.
Exceptions to this general rule may arise due to the size of the address space that an
agent supports or due to agent-specific aliasing of DRAM addresses onto other
structures. The following sections on the memory maps outline any agent-specific
exceptions. Finally, memory accesses that originate from the AIOC (or a device
attached to the AIOC) must honor the coherency requirements in Table 3-3 based on
the region they target. For consistency, software is expected to configure the EP80579
such that memory that the IA-32 core cannot access is not part of regions that are
expected to be coherent with IA caches.
3.3.2
Characteristics of Internal and External Memories
Table 3-4 defines the supported operations by memory type. The table uses the
following notation to indicate the behavior of the EP80579:
• “–” means the operation is not supported by the EP80579.
• “S” implies that the operation happens as a single atomic1 update to memory. In
other words, either the update is observable in its entirety or not at all.
• “M” implies that the operation may happen as multiple updates to memory. In
other words, other agents can observe different parts of the affected memory
location change values in any order but the end state of the memory location will
be the desired value. This “flickering lights” effect makes such memory accesses
useless for multi-agent synchronization unless a semaphore or flag variable is used
to guard access to the shared location2.
This table only applies to aligned-to-size operations; that is, a 4-byte operation is
aligned to a 4-byte boundary, an 8-byte operation is aligned to an 8-byte boundary,
etc.)
.
1. In the sense that it cannot be divided into multiple smaller writes.
2. Note that in guarding the location, visibility of the new flag must imply that the “flickering” has stopped.
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.
Table 3-5.
Supported Operations by Memory Type
Operation
Type
Read, Write
Atom ReadModify-Write
(Semaphore)
IA-32 core
Size
Bytes
Coherent
(IA WB
Cacheable)
AIOC-Directa
Coherent
AIOC-Directa
1
S
S
–
–
2
S
S
–
–
4
S
S
S
M
8
S
S
S
S
16
S
M
M
M
32
–
–
M
M
64
S
–
M
M
128
–
–
M
M
1
S
M
–
–
2
S
M
–
–
4
S
M
S
S
8
S
M
–
–
a. AIOC-Direct is a feature of the
3.3.3
AIOC Agents
Intel®
EP80579 Integrated Processor with Intel® QuickAssist Technology SKU.
Characteristics of Device Configuration
To be able to leverage existing IA BIOS, O/S, and power management software, the
EP80579’s configuration mechanisms follow existing IA platform approaches. Of the
four major components of the EP80579:
• The IA-32 core can use normal IA platform configuration algorithms.
• The IMCH and IICH can use normal IA platform configuration algorithms.
• To interoperate with normal IA platform configuration algorithms, the AIOC must be
configured by the IA processor.
With the EP80579, the boot and configuration process is:
4. The IA boots from a FLASH device on the IICH SPI (LPC) interface. System
software discovers and configures the devices on PCI bus 0 in the IMCH/IICH.
5. System software discovers and configures the devices behind the Transparent PCIto-PCI bridge into the AIOC. This may amount to allocating memory regions
specified by the BARs1.
6. System software configures other buses on the system.
Once this process completes, the EP80579 is ready for operation.
It may be necessary for software to re-order the devices on bus 0 in the IMCH/IICH/
AIOC to ensure that the AIOC can obtain the resources it needs. Since enumeration
involves either a depth-first or a breadth-first traversal of the device tree from device
zero (depending on the implementation of the platform PCI enumeration and discovery
code), the system may not be able to honor a request for a large memory region from
an AIOC device if this device is enumerated late in the process due to a large device
number. This issue is not unique to the EP80579 and is handled in whatever fashion
standard IA platform software handles such resource issues.
1. A 32-bit BAR can request a single memory size that is a power of 2 from 16B to 2GB according to the PCI specification.
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3.4
Memory Map for IA-Attached Agents
There are two constraints in the EP80579 CMI and Memory Controller designs:
• The IA-32 core only supports 32-bit physical addresses.
• The Memory Controller supports at most 4GB of physical memory.
This discussion focuses on the perspective of an IA-attached agent; Section 3.5,
“Memory Map for AIOC-Attached Devices” on page 119 provides similar discussion for
AIOC-attached agents.
Table 3-6.
Device Exposure from an IA-attached Memory Map Perspective
Device to Access
Materializes
In Region
PCIe GigE MACs
IMCH/IICH AIOC
devices
PCI L
DRAM AD
DRAM
DRAM C
3.5
Notes
•
•
•
•
PCI BAR(s) set by IA O/S or BIOS specify address mapping(s).
IA-32 core configures through I/O or PCI enhanced config spaces.
Reads, config space access between I/O agents not supported.
Region is at least 128MB per definition of TOLM, see Section
16.1.1.30, “Offset C4h: TOLM - Top of Low Memory Register”.
•
•
•
•
Contains IA/ASU Shared (AIOC-Direct) region from Table 3-3.
MENCBASE and MENCLIMIT registers define address range.
IA caches not coherent with AIOC accesses to this region.
Must include all DRAM that is inaccessible to the IA-32 core.
•
Contains I/A O/S, IA/ASU Shared (Coherent) regions from
Table 3-3.
IA caches coherent with AIOC accesses to this region.
Cannot include any DRAM that is inaccessible to the IA-32 core.
•
•
Memory Map for AIOC-Attached Devices
AIOC-attached agents support several independent target IDs that provide
independent address spaces. Table 3-7 summarizes, the addressing capabilities of
AIOC agents range from 25 to 32-bits.
Table 3-7.
3.6
Address Space Sizes of AIOC-attached Devices
Address Space Size [b]
Devices
32
Gigabit Ethernet MACs
32
ASU, SSU, TDM, SSP, CAN, 1588
Endianness
The EP80579 operates in an IA platform environment that is little-endian.
3.7
PCI Configuration
This section presents an overview of the implementation that integrates the AIOC and
memory controller with the IA PCI infrastructure for configuration.
• PCI mechanisms (configuration space, memory-mapped I/O spaces, and I/O
spaces) expose state for configuration.
• The IA-32 core performs all system configuration and initialization.
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• The IA-32 core configures the AIOC, IMCH and IICH using standard IA platform
algorithms (i.e., PCI-based discovery, enumeration, and configuration) with
modifications for the specific mix of functionality that the EP80579 CPU, IMCH, and
IICH instantiations provide.
• IA software configures external PCIe devices in the EP80579 using normal PCI
discovery and configuration algorithms. The device and bus numbers for external
devices are assigned by the BIOS and/or O/S during boot-time enumeration as
normal.
• An EP80579-specific user driver handles interaction with external non-PCI agents
attached to the EP80579 through its AIOC-side I/O interfaces. That is, the EP80579
user driver, not BIOS, will “discover” and operate any devices attached to the local
expansion bus, for example. Note that since these devices do not implement PCI
semantics, it is expected that they will not allocate MMIO regions beyond those
already allocated for the PCI view of the appropriate AIOC device.
• The O/S always allocates an aperture in the memory map for any PCI device that
defines one or more BARs, even if the device is unknown to the O/S at discovery.
The PCI abstraction that the AIOC provides for its devices is primarily a software
abstraction for the purposes of configuration; the AIOC itself does not contain PCI
devices.
3.7.1
Overview
The EP80579 integrates the AIOC and memory controller into the PCI fabric as
Figure 3-3 describes. This figure presents a logical view of the system.
Attaching the AIOC to the CMI PCI Fabric (Logical Perspective)
IICH
AIOC Complex
Devices
ASU/SSU
GigE
Bridge
FSB
PCI Bus 0
NSI
PCI Bus M
IMCH
Devices
IA
PCI Bus 0
Figure 3-3.
LEB, CAN, SSP,
1588
DRAM (AD)
Memory
Controller
DRAM (C)
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In this figure, PCI bus 0 originates in the IMCH and reaches internal IMCH PCI devices
through internal paths. Bus 0 is bridged into the IICH via an NSI interconnect and into
the AIOC. The memory controller materializes internally to the IMCH as device 0 of PCI
bus 0. The internal transparent bridge materializes the devices for the AIOC through a
bridged hierarchy as Figure 3-4 illustrates. In this hierarchy, a Transparent PCI-to-PCI
bridge appear on PCI bus 0 with the remaining AIOC devices materializing behind the
bridge on PCI bus M1.
3.7.2
Device Tree
This section describes how the devices on the EP80579 die map onto the PCI device
tree. In general, the EP80579 exposes the structures and sub-blocks that Section 3.7.1
describes through PCI devices that materialize behind a transparent bridge on bus 0.
Figure 3-4 presents an overview of the device tree for on-die EP80579 software-visible
sub-blocks (see also Figure 13-1, “Bus 0 Device Map” on page 348).
Dev: 31
Reserved
Dev: 12
TDM
Dev: 11
Reserved
Dev: 10
ASU
Dev: 9
LEB
Dev: 8
1588
Dev: 7
SSP
Dev: 6
IICH
IMCH
USB
SATA, SPI,
LPC, SMBus
Dev: 29
Dev: 2, 3
CAN 0/1
Dev: 4, 5
MDIO
Dev: 3
Dev: 0,1,2
GbE MAC
0/1/ 2
Transparent
PCI-to-PCI
Bridge
AIOC
PCI Bus 0
PCI-E
Dev: 1
EDMA
DDR (M)
IMCH
Dev: 0
PCI Bus 0
NSI
Overview of PCI infrastructure for On-die Devices
NSI
Figure 3-4.
PCI Bus M
As mentioned earlier, AIOC devices materialize on bus “M” behind a bridge on PCI bus 0
where the IA BIOS or O/S assign the secondary bus number “M” at discovery.
Devices can request space in the system memory and I/O address maps through BARs
in the configuration header. In general, the EP80579 materializes most device control
and status registers in memory-mapped regions allocated by a BAR. The only exception
1. The IA BIOS and/or O/S assigns the specific bus number during PCI discovery and enumeration.
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lies in the standard PCI configuration, status, and capability registers that PCI requires
which materialize only in PCI configuration space. The AIOC devices that lie behind the
bridge allocate by either the BIOS or OS to their regions of address and I/O space
within a contiguous region of address space that the bridge claims. It is assumed that
system software configures the aperture for the bridge to be large enough to cover all
of the address space that the devices behind the bridge request.
The remainder of this section summarizes the device tree that the EP80579
implements. This summary includes a mapping between PCI devices and the EP80579
blocks along with the value of the device ID, class code, and a summary of the
resources (i.e., registers, memory, etc.) that each device requests.
Table 3-9 summarizes the PCI devices that the IMCH and IICH materialize.
Table 3-9.
IMCH and IICH PCI Device Summary
PCI
Device Name
EP80579
Units
Memory Controller
Hub
SKU ID
Number
Resourcesa
B/D/Fb
BSPc
Device
ID
IMCH
0/0/0
060000h
5020h
1,2,3,4,5,6,
7,8
Error Reporting
IMCH
0/0/1
FF0000h
5021h
1,2,3,4,5,6,
7,8
EDMA
EDMA
0/1/0
088000h
5023h
1,2,3,4,5,6,
7,8
MSI, MBAR (4KB)
PCI-Ex Port 0
PEA0
0/2/0
060400h
5024h
1,2,3,4,5,6,
7,8
PM, MSI
PCI-Ex Port 1
PEA1
0/3/0
060400h
5025h
1,2,3,4,5,6,
7,8
PM, MSI
PCI-to-PCI Bridge
IMCH
0/4/0
060400h
5037h
1,2,3,4,5,6,
7,8
USB 1.1 Controller
USB1.1
0 / 29 / 0
0C0300h
5033h
1,2,3,4,5,6,
7,8
IOBAR (32B)
USB 2.0 Controller
USB2.0
0 / 29 / 7
0C0320h
5035h
1,2,3,4,5,6,
7,8
PM, MBAR (1KB)
LPC/SPI
LPC/SPI
0 / 31 / 0
060100h
5031h
1,2,3,4,5,6,
7,8
IOBAR (128B, 64B)
SATA
SATA
0 / 31 / 2
01018Ah,
010601h,
010401h,
010401hd
5028h,
5029h,
502Ah,
502Bhe
1,2,3,4,5,6,
7,8
PM, MSI, IOBAR (8B, 8B, 4B,
4B, 16B), MBAR (1KB)
SMBus
SMBUS
0 / 31 / 3
0C0500h
5032h
1,2,3,4,5,6,
7,8
IOBAR (32B)
MBAR (4KB and 4KB)
a. “MBAR” is a memory space BAR, “IOBAR” is an I/O space BAR, “PM” is a power management capability, and
“MSI” is an MSI capability.
b. PCI bus number, device number, and function number.
c. PCI base class code, subclass code, and programming interface PCI configuration register values.
d. SATA SC and PI values depends on the SATA mode and map value settings.
e. SATA DID value depends on the SATA mode settings.
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Table 3-10. AIOC PCI Device Summary
PCI
Device Name
EP80579
Units
B/D/Fb
BSPc
Device
ID
5040h
GigE MAC 0
GigE MAC 1
GigE MAC 2
GbE 0
GbE 1
GbE 2
M/0/0
M/1/0
M/2/0
020000h
020000h
020000h
SKU ID
Number
Resourcesa
2,4,6,8
5041h
1,3,7,5
5042h
Reservedd
5043h
Reservedd
5044h
2,4,6,8
5045h
1,3,7,5
5046h
Reservedd
5047h
Reservedd
5048h
2,4,6,8
5049h
1,3,7,5
504Ah
Reservedd
504Bh
Reservedd
PM, MSI, ST, MBAR (128KB),
IOBAR (32B)
PM, MSI, ST, MBAR (128KB),
IOBAR (32B)
PM, MSI, ST, MBAR (128KB),
IOBAR (32B)
MDIO
MDIO
M/3/0
FF0000h
503Eh
1,2,3,4,5,6,7
PM, MBAR (4KB)
,8
CAN Interface 0
CAN 0
M/4/0
0C0900h
5039h
1,2,3,4,5,6,7
PM, MSI, ST, MBAR (4KB)
,8
CAN Interface 1
CAN 1
M/5/0
0C0900h
503Ah
1,2,3,4,5,6,7
PM, MSI, ST, MBAR (4KB)
,8
SSP
SSP
M/6/0
078000h
503Bh
1,2,3,4,5,6,7
PM, MSI, ST, MBAR (4KB)
,8
IEEE 1588
1588
M/7/0
111000h
503Ch
1,2,3,4,5,6,7
PM, MSI, ST, MBAR (4KB)
,8
Local Expansion
Bus
LE Bus
M/8/0
068000h
503Dh
1,2,3,4,5,6,7 PM, MSI, ST, MBAR (4KB and
,8
0-256MBe)
502Ch
ASU
ASU
M/9/0
0B4000h
2,4,6,8
502Dh
1,3,7,5
502Eh
Reservedd
502Fh
Reservedd
Reserved
Reserved
M / 10 /
0
088000h
503Fh
TDM
TDM
M / 11 /
0
0B4000h
504Ch
Reserved
Reserved
M / 12 /
0
110100h
5030h
PM, MSI, ST, MBAR (8KB,
16KB, 16KB, and 4KB)
1,2,3,4,5,6,7
Reserved
,8
1,3,5,7
PM, MSI, ST, MBAR (4KB and
4KB)
1,2,3,4,5,6,7
Reserved
,8
a. “MBAR” is a memory space BAR, “IOBAR” is an I/O space BAR, “PM” is a power management capability, “MSI”
is an MSI capability, and “ST” is an EP80579 signal target capability.
b. PCI bus number, device number, and function number.
c. PCI base class code, subclass code, and programming interface PCI configuration register values.
d. These device IDs are reserved for future SKUs.
e. The size of the region that the 0-256MB MBAR requests is a multiple of 32MB between 0MB and 256MB
(inclusive) based on reset-time platform configuration.
A summary of the registers, memory-mapped, and I/O-mapped resources that
Table 3-9 and Table 3-10 identify can be found in Section 7.0, “Register Summary”.
Detailed descriptions of these resources can be found in the chapters that cover the
relevant block.
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3.7.3
Materializing Device Structures
The EP80579 exposes AIOC resources through standard PCI abstractions: configuration
spaces, memory-mapped I/O spaces, and I/O spaces.
Access to MMIO and I/O spaces are accessed through memory and I/O read/write
instructions, respectively. The addressing of these spaces for a given device depends
on the specific mapping that the PCI configuration header establishes through BARs.
PCI defines two mechanisms for accessing the 256B of each device/function
configuration registers located in PCI configuration space.
• PCI Mechanism: The header is accessed using 1-, 2-, or 4-byte IN and OUT
instructions that access the PCI configuration address and data I/O ports at
addresses 0CF8h - 0CFBh and 0CFCh - 0CFFh, respectively, in the IA I/O space. This
mechanism allows access only to the 256B PCI-compatible configuration space
• PCI Express* Enhanced Mechanism: The header is accessed using 1-, 2-, or 4-byte
memory accesses to the 256MB region starting at HECBASE (0_E000_0000P by
default. This mechanism allows access to an expanded 4KB configuration space
that PCI Express* defines (the first 256B are, by definition, the PCI-compatible
configuration space).
These mechanisms differ in the address space they use to access the header. The PCI
mechanism travels through IA I/O space while the PCI Express* Enhanced mechanism
travels through IA memory space. The address format that the mechanisms use is
identical to the standard IA platform format that encodes the PCI bus, device, and
function numbers along with a register offset or number (see Section 13.6.0.1, “Offset
0CF8h: CONFIG_ADDRESS - Configuration Address Register” and Section 13.8.4,
“Enhanced Configuration FSB Address Format” for details).
For either access method, the hardware in the AIOC that implements the configuration
headers must be able to process accesses of the appropriate sizes.
3.7.4
PCI Configuration Headers
The PCI specification requires each PCI device to provide a 256B configuration space.
The first 64B of this space contains a standard PCI configuration header and the
remaining 192B contains any device-specific registers, capabilities records, etc. needed
by the function. There are two flavors of configuration headers:
• All non-bridge devices provide a PCI type 0 configuration headers. This form of
header is used to represent devices on the PCI fabric.
• All bridge devices provide a PCI type 1 configuration header. This form of header is
used to represent bridge devices in the PCI fabric.
Because the AIOC devices are not PCI devices, they do not fully support all PCI
configuration header fields1. The following tables describe the support in greater detail.
Table 3-11 summarizes the fields in a PCI type 0 header (i.e., header for non-bridge
devices) and identifies which fields the EP80579 implements for AIOC devices. The
EP80579 hardware implements the appropriate PCI semantics for all supported
registers and fields in this table.
1. Configuration headers for IMCH and IICH devices follow PCI expectations as these devices are PCI compliant.
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Table 3-11. PCI Configuration Header Support for Type 0 Headers in AIOC Devices (Sheet
1 of 2)
Acc.b
00h - 01h
Vendor ID
15:0
Y
RO
Required by PCI.
02h - 03h
Device ID
15:0
Y
RO
Required by PCI.
Y
RW
Supported in devices that can use INTxc.
N
RO
Not supported in devices that do not use INTxd.
Status Register
06h - 07h
Command Register
Register and Field
04h - 05h
Bit(s)
Supt.a
Offset
Notes
Interrupt Disable
10
Fast Back-to-Back
Enable
9
N
RO
Not supported.
SERR# Enable
8
N
RO
Not supported. INTx/MSI signal AIOC errors.
Parity Error
Response
6
N
RO
Not supported. INTx/MSI signal AIOC errors.
VGA Palette Snoop
5
N
RO
Not supported.
Mem. Write &
Inval. Enable
4
N
RO
Not supported.
Special Cycles
3
N
RO
Not supported.
N
RW
ASU, GbE, TDM, LEB devices: Not supportede,
bit is implemented as RW but has no effect
Y
RO
All devices except ASU, GbE, TDM, LEB: these
devices cannot be bus masters.
Y
RW
All devices except 1588; these devices each
materialize in memory space.
N
RO
For IEEE1588; IEEE1588 does not materialize in
memory space.
Y
RW
For GbE; GbE materializes in I/O space.
N
RO
All devices except GbE; these devices do not
materialize in I/O space.
Bus Master Enable
2
Memory Space
Enable
1
I/O Space Enable
0
Detected Parity
Error
15
N
RO
Not supported; INTx/MSI signal errors.
Signalled System
Error
14
N
RO
Not supported. INTx/MSI signal AIOC errors.
Received MasterAbort
13
N
RO
Not supportede.
Received TargetAbort
12
N
RO
Not supportede.
Signalled TargetAbort
11
N
RO
Not supported; AIOC devices do not targetabort.
DEVSEL Timing
10:9
N
RO
Not supported.
Master Data Parity
Error
8
N
RO
Not supported. INTx/MSI signal AIOC errors.
Fast Back-to-Back
Capable
7
N
RO
Not supported.
66MHz Capable
5
N
RO
Not supported.
Capabilities List
4
Y
RO
Setup based on capabilities exposure by device.
Interrupt Status
3
Y
RO
Supported in devices that can use INTxc.
N
RO
Not supported in devices that do not use INTxd.
08h
Revision ID
7:0
Y
RO
Required by PCI.
09h - 0Bh
Class Code
23:0
Y
RO
Required by PCI.
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Table 3-11. PCI Configuration Header Support for Type 0 Headers in AIOC Devices (Sheet
2 of 2)
Offset
Register and Field
Bit(s)
Supt.a
Acc.b
0Ch
Cache Line Size
7:0
N
RO
Not supported.
0Dh
Latency Timer
7:0
N
RO
Not supported.
0Eh
Header Type
7:0
Y
RO
Required by PCI.
0Fh
BIST
7:0
N
RO
Not supported.
RW
Devices that materialize in I/O or memory
spaces will populate these slots as necessary
based on address space needs.
10h - 27h
Base Address (x6)
6x
31:0
Y
Notes
28h - 2Bh
CIS Pointer
31:0
N
RO
Not supported.
2Ch - 2Dh
Subsystem VID
15:0
Y
RO
Required by PCI.
2Eh - 2Fh
Subsystem ID
15:0
Y
RO
Required by PCI.
34h
Capability Pointer
7:0
Y
RO
Setup based on capabilities exposure by device.
3Ch
Interrupt Line
7:0
Y
RW
Supported in devices that can use INTxc.
N
RO
Not supported in devices that do not use INTxd.
3Dh
Interrupt Pin
7:0
Y
RO
Supported in devices that can use INTxc.
N
RO
Not supported in devices that do not use INTxd.
3Eh
Min_Gnt
7:0
N
RO
Not supported.
3Fh
Max_Lat
7:0
N
RO
Not supported.
a. Supported fields provide appropriate PCI semantics. Unsupported fields always return zero on reads unless
otherwise noted.
b. RO and RW access types indicate that the register or field supports read-only access and read/write access,
respectively.
c. AIOC devices that may signal via INTx include GbE, CAN, SSP, and IEEE1588.
d. AIOC devices that cannot signal via INTx include LEB.
e. This behavior is a deviation from the PCI specification for only the GbE and a device that can be a bus master.
Table 3-12 summarizes the fields in a PCI type 1 header (i.e., header for bridge
devices) and identifies which fields the EP80579 implements. The EP80579 hardware
implements the appropriate PCI semantics for all supported registers and fields in this
table.
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Table 3-12. PCI Configuration Header Support for Type 1 Headers in AIOC Devices (Sheet
1 of 3)
Acc.b
00h - 01h
Vendor ID
15:0
Y
RO
Required by PCI.
02h - 03h
Device ID
15:0
Y
RO
Required by PCI.
Status Register
06h - 07h
Command Register
Register and Field
04h - 05h
Bit(s)
Supt.a
Offset
Notes
Interrupt Disable
10
N
RW
Bridge-generated interrupts not supported.
Fast Back-to-Back
Enable
9
N
RO
Not supported.
SERR# Enable
8
N
RW
Bridge delivers events that would be master
aborts (primarily address decode) as SERR#.
Parity Error
Response
6
N
RW
Not supported. INTx/MSI signal AIOC errors.
VGA Palette Snoop
5
N
RO
Not supported.
Mem. Write &
Inval. Enable
4
N
RO
Not supported.
Special Cycles
3
N
RO
Not supported.
Bus Master Enable
2
N
RW
Not supportedc.
Memory Space
Enable
1
N
RW
Bridge itself does not expose any non-standard
registers via memory space.
I/O Space Enable
0
N
RW
Bridge itself does not expose any non-standard
registers via I/O space.
Detected Parity
Error
15
N
RO
Not supported. INTx/MSI signal AIOC errors.
Signalled System
Error
14
N
RO
Not supported. INTx/MSI signal AIOC errors.
Received MasterAbort
13
N
RO
Not supportedc.
Received TargetAbort
12
N
RO
Not supportedc.
Signalled TargetAbort
11
N
RO
Not supported; AIOC devices do not targetabort.
DEVSEL Timing
10:9
N
RO
Not supported.
Master Data Parity
Error
8
N
RO
Not supported. INTx/MSI signal AIOC errors.
Fast Back-to-Back
Capable
7
N
RO
Not supported.
66MHz Capable
5
N
RO
Not supported.
Capabilities List
4
Y
RO
Setup based on capabilities exposure by bridge.
Interrupt Status
3
N
RO
Bridge-generated interrupts not supported.
Revision ID
7:0
Y
RO
Required by PCI.
09 - 0Bh
Class Code
23:0
Y
RO
Required by PCI.
0Ch
Cache Line Size
7:0
N
RO
Not supported.
0Dh
Latency Timer
7:0
N
RO
Not supported.
0Eh
Header Type
7:0
Y
RO
Required by PCI.
0Fh
BIST
7:0
N
RO
Not supported.
10h - 17h
Base Address (x2)
2x
31:0
N
RO
Not supported. Bridge does not expose nonstandard registers via BAR.
18h
Primary Bus Number
7:0
Y
RW
Required by PCI.
08h
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Table 3-12. PCI Configuration Header Support for Type 1 Headers in AIOC Devices (Sheet
2 of 3)
Register and Field
Bit(s)
Supt.a
Acc.b
19h
Secondary Bus
Number
7:0
Y
RW
Required by PCI.
1Ah
Subordinate Bus
Number
7:0
Y
RW
Required by PCI.
1Bh
Secondary Latency
Timer
7:0
Y
RO
Not Supported.
1Ch
I/O Base
7:0
Y
RW
Supported, AIOC devices materialize in I/O
space.
1Dh
I/O Limit
7:0
Y
RW
Supported, AIOC devices materialize in I/O
space.
Detected Parity
Error
15
N
RO
Not supported. INTx/MSI signal AIOC errors.
Received System
Error
14
N
RO
Not supported. INTx/MSI signal AIOC errors
Received MasterAbort
13
N
RO
Not supportedc.
Received TargetAbort
12
N
RO
Not supportedc.
Signalled TargetAbort
11
N
RO
Secondary-side devices cannot target-abort.
DEVSEL Timing
10:9
N
RO
Not supported.
Master Data Parity
Error
8
N
RO
Not supported. INTx/MSI signal AIOC errors.
Fast Back-to-Back
Capable
7
N
RO
Not supported.
66MHz Capable
5
N
RO
Not supported.
1Eh - 1Fh
Secondary Status Register
Offset
Notes
20h - 21h
Memory Base
15:0
Y
RW
Supported, AIOC devices materialize in memory
space.
22h - 23h
Memory Limit
15:0
Y
RW
Supported, AIOC devices materialize in memory
space.
24h - 25h
Prefetch Memory Base
15:0
N
RWd
Prefetchable memory devices not supported.
d
Prefetchable memory devices not supported.
26h - 27h
Prefetch Memory Limit
15:0
N
RW
28h - 2Bh
Prefetch Base
(upper 32b)
31:0
N
RWd
Prefetchable memory devices not supported.
2Ch - 2Fh
Prefetch Limit
(upper 32b)
31: 0
N
RWd
Prefetchable memory devices not supported.
30h - 31h
I/O Base (upper 16b)
15:0
N
RO
I/O spaces larger than 64KB not supported.
32h - 33h
I/O Limit (upper 16b)
15:0
N
RO
I/O spaces larger than 64KB not supported.
34h
Capability Pointer
7:0
Y
RO
Setup based on capabilities exposure by bridge.
38h - 3Bh
Expansion ROM Base
31:0
N
RO
Not supported.
3Ch
Interrupt Line
7:0
N
RO
Bridge-generated interrupts not supported.
3Dh
Interrupt Pin
7:0
N
RO
Bridge-generated interrupts not supported.
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Table 3-12. PCI Configuration Header Support for Type 1 Headers in AIOC Devices (Sheet
3 of 3)
3Eh - 3Fh
Bit(s)
Supt.a
Acc.b
Discard Timer
SERR# Enable
11
N
RO
Not supported.
Discard Timer
Status
10
N
RO
Not supported.
Secondary Discard
Timeout
9
N
RO
Not supported.
Primary Discard
Timeout
8
N
RO
Not supported.
Fast Back-to-Back
Enable
7
N
RO
Not supported.
Secondary Bus
Reset
6
N
RW
Not supported.
Master Abort Mode
5
Y
RO
Bridge delivers events that would be master
aborts (primarily address decode) as SERR#.
Register and Field
Bridge Control Register
Offset
Notes
VGA Enable
3
N
RW
Not supported.
ISA Enable
2
N
RW
Not supported.
SERR# Enable
1
N
RW
Not supported.
Parity Error
Response
0
N
RW
Not supported.
a. Supported fields provide appropriate PCI semantics. Unsupported fields always return zero on reads unless
otherwise noted and need not provide PCI semantics.
b. RO and RW access types indicate that the register or field supports read-only access and read/write access,
respectively.
c. This is a known deviation from the PCI specification since the bridge can be a bus master.
d. This is a deviation from the PCI specification since this register should be RO on bridges that do not support
prefetchable regions. The registers are RW for compatibility with the base IP. Software is expected to set these
fields to indicate an empty region since no secondary-side devices (i.e., bus M) request prefethcable memory.
For additional details on the headers for AIOC devices, see Section 35.3.1, “Description
of PCI Configuration Header Space”.
The specific portion of the 256B PCI configuration space that is active in a device
depends on the needs of the specific device. In general, a device requires far less than
256B of storage to implement a typical configuration space. Regions of the 256B
configuration space that are not required are reserved and need only support default
behavior compliant with the PCI specification:
All PCI devices must treat Configuration Space write operations to reserved
registers as no-ops; that is, the access must be completed normally on the bus and
the data discarded. Read accesses to reserved or unimplemented registers must be
completed normally and a data value of 0 returned.
§§
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4.0
Signaling
4.1
Overview
This chapter presents an overview of the inter-agent signaling mechanisms supported
along with the implications on transaction ordering necessary to support producer/
consumer software algorithms. This chapter concentrates primarily signaling for
functional, not error, purposes while Section 5.0, “Error Handling” provides additional
discussion on error signaling.
The EP80579 signaling model operates in a system-on-a-chip environment and must
blend the signaling architectures of many disparate components into a unified whole.
• Allow signaling between IA agents (i.e., the IA-32 core, IMCH, IICH, and external
PCI-Express-attached devices) and AIOC agents.
• Support producer/consumer relationships between agents in the IA or AIOC.
• Provide compatibility with existing IA signaling mechanisms for internal IMCH/IICH
agents and external devices.
• Provide compatibility with IA platform signaling semantics and abstractions.
There are two tightly related parts to the signaling model:
• The signaling mechanism determines how takes a signal from a source agent,
performs any necessary translation, and delivers it to a target agent in a form the
target can understand.
• The ordering mechanism determines how orders a given signal from a source agent
with respect to the data stream that the source agent produces to meet ordering
requirements.
Figure 4-1.
Logical Overview of Signaling Architecture
EP80579
AIOC
PCI
Device(s)
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IA Complex
PCI Ex
(CPU, IMCH, IICH)
Signal
Bridging
Internal
PCI
Agents
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The IA complex attaches to the AIOC through a transparent PCI-to-PCI Bridge. Within
the AIOC, the “Signal Bridge” block in Figure 4-1 represents the hardware in the AIOC,
that converts signaling between the AIOC and IA domains and presents the appropriate
abstractions to agents on either side of the bridge.
4.1.1
Terminology and Conventions
Throughout this section, we use the following terminology:
• Global visibility: An operation is said to be globally visible when all side-effects of
the operation are visible to every observer in the system. For example, a write to
some resource (e.g., memory location, control register, etc.) R achieves global
visibility when a read of R by all other agents is guaranteed to return the new
value.
• Ordering: Ordering refers to the order in which signals and/or memory accesses to
different locations must reach global visibility to ensure some behavior. Note that
this excludes the “ordering” necessary to prevent data hazards which are accesses
to the same location.
• Signal: A message sent between agents to indicate some condition of interest. A
signal may be an interrupt, a memory write, etc. This section uses the term when
the specific transport medium is not important.
4.2
Existing Signaling Capabilities
There are several agents in the EP80579 that can be both the source and the target of
a “signal”: the IA-32 core and accelerators in the AIOC. In addition, there are several
other agents in the EP80579 that can be the source of a signal: devices in the IMCH or
IICH, the error reporting hardware, the Gigabit Ethernet MAC, the SSP interface, the
CAN interfaces, the IEEE 1588 interface, externally-attached PCI-Express devices, and
externally-attached local expansion bus devices (via GPIO or INTx interrupts). This
section summarizes the existing signaling capabilities of each of these agents.
When discussing signaling, this section classifies all signals into one of two general
categories:
• Ordered signals must maintain a particular relationship with the data stream. For
example, a MAC signals a CPU with an ordered signal after the MAC finishes writing
inbound packet data to memory.
• Unordered signals need not maintain a particular relationship with the data stream.
For example, memory interface hardware signals a CPU with an unordered signal
when the interface encounters an uncorrectable memory error.
Signals of either type may participate in producer/consumer operations between
agents; however, the operation can use only ordered signals if the producer/consumer
operation involves the data stream1. Finally, note that this classification refers
specifically to the data stream; signals may also be ordered with respect to other
events (e.g., data being available in a local device buffer).
1. For producer/consumer operation to work correctly, software and hardware must be able to establish ordering relationships
between various events in the operation. Such a relationship cannot be established between the data stream and a signal that
is unordered with respect to the data stream.
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4.2.1
IA-32 core/Platform
The IA-32 core supports two inbound signaling mechanisms that the EP80579 can use
to accept signals from other agents: a legacy interrupt (INTx) and a message-signaled
interrupt (MSI). The INTx mechanism encodes an interrupt on one of four out-of-band
interrupt signals that drive interrupt controllers in the IA platform. The MSI mechanism
encodes an interrupt as an in-band 32-bit write to a memory-mapped location. When
the platform observes a write to an MSI location, it generates an interrupt to the CPU.
The operating system or system software specifies, in large part, the data value that
travels with an MSI; the device has limited ability to change or modify this value in the
PCI MSI model.
The IA platform also supports signaling for errors through events that the platform
eventually maps onto interrupts, such as SERR or SMI. Section 5.0, “Error Handling”
discusses these mechanisms in further detail. These mechanisms are not used in
functional inter-agent signaling.
4.2.1.1
MSI and INTx Signaling
The EP80579 supports both MSI and INTx mechanisms to interoperate with IA platform
system software since not all operating systems or devices support MSIs. The PCI
configuration header of each device indicates the capabilities of the device (i.e., if it can
generate an MSI, which pin it uses in INTx mode, etc.) and also allows system software
to specify the signaling mechanism the device should use when the device is capable of
both MSI and INTx signaling. Further, when signaling the IA platform, software must
tolerate “warts” of the IA signaling model such as spurious interrupts, etc.
For outbound signaling from the IA-32 core to other agents, the EP80579 relies on
memory writes to MMIO locations to transport signals or IA can issue an MMIO read to
a device CSR.
4.2.1.2
GPIO Signaling
The EP80579 provides the ability to configure a subset of its GPIO pins as interrupts.
GPIO pins 16-21, 23-25, 27, 28, 30, 31, 33, 34, and 40 can function in either an
interrupt mode or as a GPIO. Each of these GPIO pins can be connected to a single
input on the APIC when software configures the GPIO as an interrupt. These pins are
then available to external devices, such as a device attached to the Local Expansion
Bus, for use as signals. The EP80579 handles signals arriving through a GPIO interrupt
are handled like all other interrupts connected to the APIC. For additional information,
see the GPIO material in Section 22.0, “General Purpose I/O: Bus 0, Device 31,
Function 0”.
4.2.2
Other Agents
The remaining agents that are relevant to the EP80579 signaling model can only signal
in the outbound direction; that is, they only generate signals from the agent into
EP80579. These agents operate as follows:
• IMCH, IICH, and externally-attached PCI devices generate IA platform INTx or MSI
signals based on PCI device and platform configuration. PCI mechanisms such as
SERR can also support error reporting (see Section 5.0, “Error Handling”).
• Gigabit Ethernet MAC generates a side-band interrupt signal.
• CAN, SSP, and IEEE 1588 Interfaces generate side-band interrupt signals.
• Externally-attached Local Expansion Bus devices generate side-band interrupt
signals. These signals are not carried on the Local Expansion bus itself but rather
are presented to the IA-32 core through GPIO pins that the system configures to
generate signals.
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4.3
Inter-Agent Signaling
Signals may originate from a number of sources within the system but may only target
one of the on-die agents in the EP80579: the IA-32 core or AIOC accelerator. This
section considers inter-agent signaling mechanisms available in the EP80579. This
material looks at signaling in isolation.
Because the EP80579 integrates devices from several different fabrics, signaling
between different agents may require bridge functionality to convert signals between
the various existing capabilities that Section 4.2, “Existing Signaling Capabilities” on
page 132 describes. Figure 4-2 presents a logical view of the flow of signals through
the EP80579.
.
Figure 4-2.
Logical View of Signaling Flow
Source
Agent
Destination
Agent
Signal Bridge
In- or side-band
signal from
Source Agent
Signal for Destination
Agent in Destination
Format
In this model, a signal originates from a source agent as an in- or side-band signal.
Depending on the specific situation, the signal may either reach the destination directly
or through a signal bridge. The signal bridge in EP80579 does not provide any
mechanism to ensure that a destination agent responds to a given inbound signal. As a
result, software must be able to keep up with the signaling rates if catching and
processing every signal is a requirement. If software is unable to keep up with the
signaling rate, one or more signals can be dropped.
Table 4-1 summarizes the cross product of the combinations of producer and consumer
agents that EP80579 supports for signaling between agents. This table identifies the
types of signaling allowed as well as any bridging that the EP80579 hardware must
provide to support signaling between the indicated agents.
Table 4-1.
Supported Inter-Agent Signaling
On-Die Signal Consumer
Signal Bridging
Signal Producer
IA-32 core
IA-32 core
Not Supporteda
IMCH, IICH Devices
PCI MSI / INTx via PCI
GigE MAC
Side band: PCI MSI / INTx
SSP
Side band: PCI MSI / INTx
CAN
Side band: PCI MSI / INTx
1588
b
Side band: PCI MSI / INTx
Errors
Side band: PCI MSI / INTx
External PCI Express* Device
PCI MSI / INTx via PCI
External Local Expansion Bus Device
MSI / INTx via GPIO
a. Support not required since there is only one such agent in an EP80579.
b. This includes signaling for errors in the memory controller, local expansion bus, etc.
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In this table, “:” and “via” indicates bridged and direct paths for the signaling (see
Figure 4-2), respectively. All EP80579 hardware that inter-operates with IA platform
structures for signaling, such as the signal bridge, operate in IA physical address space.
This allows it to access IA platform devices, such as the LAPIC that are accessed via
MMIO reads and writes in the PCI L memory region.
The next two sections cover the various signaling scenarios that are represented in the
cells of Table 4-1: signaling that travels around the bridge and that is bridged from a
side band signal.
4.3.1
Signaling that Travels Around the Signal Bridge
For signaling that does not need to travel through the signal bridge, the EP80579 does
not require any specific signaling support. In these cases, the signaling occurs over an
existing path. For example, an interrupt from a IICH USB controller would travel over
the existing IICH INTx or MSI path based on device configuration.
4.3.2
Signaling that is Bridged from a Side-Band Source Signal
The majority of signaling scenarios in Table 4-1 that require bridging are conversions
between side band signals and a signal that targets the IA-32 core. The EP80579 uses
a centralized agent, the signal bridge to perform this conversion. One or more sideband signals arrive at the signal bridge from each AIOC device that is capable of
signaling. The bridge is responsible for generating the appropriate outbound signal to
either an ASU device or the IA-32 core. Figure 4-3 presents an overview of the signal
bridge hardware for a subset of the EP80579 AIOC devices.
Figure 4-3.
Signal Bridging
AIOC
AIOC
GbE 0
AIOC
Signal Bridge
n
n
n
n
MSI
Signal Target
0
mar C, mdr Z
mask M0, data ?
9
mar ?, mdr ?
mask M9, data S
10
mar A, mdr X
mask M10, data ?
11
INTb
mask M11, data ?
ASU
INT<n>
IA
MSI [C], f(Z)
Logically, the signal bridge consists of the MSI and Signal Target capability records from
the PCI configuration headers for the AIOC devices. The MSI capability record for a
device includes a message address register (mar in Figure 4-3) and Message data
register (mdr in Figure 4-3) that indicate the address and data for the MSI as per the
PCI definition of this capability. The Signal Target capability record for a device includes
a mask that determines how the bridge steers the signal, data which identifies
additional signaling data, and a status that indicates which side-band signal(s) has
been asserted1. The Signal Target capability is a vendor-specific capability record
whose format the EP80579 defines.
In the example show in Figure 4-3, side band signals arrive from Gigabit Ethernet MAC
and other AIOC agents. These agents correspond to AIOC PCI devices. Here, the GbE
agent generates a signal that the signal bridge delivers as an MSI to IA based on the
1. The status is not shown in Figure 4-3.
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configuration in the MSI and Signal Target capability records in the PCI configuration
header. These records allow the signal bridge to determine how to handle an inbound
signal from a device.
All side band signals from a given source are collected at the signal bridge. For
example, a source may provide interrupt lines and error condition lines that cause the
EP80579 to send a signal when any one is asserted. Sets of side band signals are then
associated with each AIOC PCI device that can signal. When a given side band signal
asserts, the signal bridge looks up the MSI and Signal Target capability records in the
PCI configuration header that corresponds to the device. These resources tell the signal
bridge how and where to deliver the outbound signal:
• If the masks in the Signal Target capability record indicate the signal should be
delivered to the IA-32 core, the signal bridge sends an MSI or INTx signal to the IA32 core.
— If the PCI configuration header selects MSI messaging, the signal bridge
generates an MSI transaction from the device that generates the signal to the
IA-32 core in accordance with the MSI capability record.
— If the PCI configuration header selects INTx messaging, the signal bridge
generates an INTx transaction to the IA-32 core.
The status register in the Signal Target Capability provides the state of the side-band
signals associated with a given AIOC PCI device to help software disambiguate the
source of the signal.
4.3.2.1
Targeting the IA-32 core with a Bridged Signal
To remain compatible with existing IA software stacks, EP80579 hardware supports the
PCI MSI and legacy INTx signaling mechanisms into the CMI in response to signals
targeting the IA-32 core.
• MSI enable field selects the signaling mechanism an MSI-capable device uses:
— INTx legacy mode.
— MSI mode.
• MSI capability record specifies how IA system software wants MSI-capable devices
to signal the IA-32 core through a message address and message data register.
• Interrupt pin and line registers specify the interrupt pin and line that the hardware
uses for legacy INTx mode.
• Interrupt disable bit in the command register specifies whether or not the device
generates any signals.
Based on the PCI abstraction, these are per-device fields that are logically associated
with a given device and that all devices that can signal the IA-32 core must implement.
Software is free to mix signal delivery mechanisms at the device level. For example, it
may configure the EP80579 such that the Gigabit Ethernet MACs signal through MSIs
while the remaining AIOC devices signal through INTx.
When device X signals the IA-32 core, it consults the PCI configuration header for
device X to determine how to deliver the signal to IA (i.e., via MSI or INTx). For
signaling via MSI, the header identifies the address and data value in the MSI
transaction. Hardware builds the 32-bit data value for the MSI transaction from the
contents of the PCI MSI Message Data Register, mdr, according to the PCI semantics.
Specifically, the data value sent in the MSI to IA is:
• Bits 31:16 are zero.
• Bits 15:0 are mdr, the value of the PCI MSI Data Register in the PCI configuration
header of the source device1.
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The address is given directly by the PCI MSI Message Address Register, mar. Finally, the
source of the MSI transaction is set to the bus/device/function number of the device
that generates the signal.
For signaling via INTx, the header identifies the interrupt line and pin that the EP80579
should use. In this case, hardware generates the appropriate transactions for INTx
upstream into the CMI. Since the INTx mechanism cannot transport any information
beyond the fact that a signal occurred, the EP80579 needs to expose enough device
state to the software stack, via device-specific control register(s), to allow software to
be able to determine both the source and cause of the interrupt. Such state would be in
addition to the generic interrupt state that each PCI device provides through its PCI
configuration header as per the PCI specification
To integrate with the existing IMCH/IICH, the signal bridge in the EP80579 will
generate four INTx signals that it tracks based on the interrupt state of the blocks from
the AIOC that can generate signals. These four INTx signals are provided to interrupt
hardware in the IA platform hardware where they are ORed with similar signals from
other agents and converted into the appropriate signaling to the IA-32 core. This
hardware will also provide a signal back to the IMCH that indicates when the local INTx
state can be deasserted.
In addition to generating any transaction(s) necessary to send the signal to the IA, the
AIOC must preserve the semantics of PCI interrupts and signals with respect to the
state in the PCI configuration headers for the AIOC devices.
• Signaling to the IA-32 core by a device should operate in accordance with the MSI
mode and configuration in the MSI capability record.
• Signaling to the IA-32 core by a device must be disabled when the interrupt disable
bit in the PCI command register is set
• The interrupt status bit in the PCI status register should reflect the status of an
INTx signal.
This preserves the PCI abstraction for AIOC devices.
§§
1. This assumes that the device requests exactly one message in the PCI MSI capability record [PCI_3].
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5.0
Error Handling
5.1
Overview
This section presents an overview of the error handling mechanisms that the EP80579
provides. The intent of this discussion is to provide a broad background to error
handling on the chip. Register definitions and other error handling details can be found
in the discussions of the relevant units throughout this document.
5.2
EP80579 View of Error Reporting
This section describes the guiding principles on which the error logging and reporting
registers are based for the EP80579. For the purposes of this discussion, an “error” is
an exceptional condition that is beyond the control of the EP80579 hardware or
software and might result in data corruption or data loss. This definition does not cover
“functional” errors that are not beyond the control of the EP80579. For example, this
section discusses double-bit ECC errors as they involves data corruption that occurs
through no overt action of the EP80579; it does not cover an underflow error on a ring
since this is a functional condition that can be managed in software to avoid data loss.
5.2.1
Hardware Capabilities
With respect to their error handling capabilities, the blocks on the EP80579 can be
divided into three groups: the IA blocks (including the IA-32 core, IMCH exclusive of
the memory interface, IICH), the memory controller interface, and the AIOC blocks.
Generally speaking,
• The IA blocks (see Section 5.3, “Error Reporting by the IMCH” on page 141 and
Section 5.4, “Error Reporting by the IICH” on page 149) use the FERR/NERR and
PCI error reporting infrastructures.
• The memory controller block (see Section 5.5, “Error Reporting by the System
Memory Controller” on page 153) uses the FERR/NERR error reporting
infrastructure.
• The AIOC blocks (see Section 5.6, “Error Reporting by AIOC Devices” on page 155)
use their existing error reporting infrastructures that are “bridged” into the IA-32
core to report errors to IA through PCI signals (i.e., INTx or MSI depending on
device configuration). These blocks do not support other PCI error reporting
capabilities such as SERR or the IMCH FERR/NERR architecture.
This organization allows an EP80579 system to use standard IA platform reporting
abstractions and algorithms throughout the IA portion of the chip (including the
memory controller). AIOC devices then use PCI INTx or MSI signaling to present their
error handling within the IA infrastructure. Utilizing signaling in this fashion implies that
the responsibility for error handling in AIOC devices resides with Intel provided AIOC
device drivers in the EP80579 software stack.
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The EP80579 hardware, where appropriate, supports two general capabilities for error
handling. The first is support for data “poisoning” to propagate errors through the chip.
The second is support for mechanisms to allow software to inspect the cause of the
error.
To allow software to inspect the error, each unit in the EP80579 that is capable of
detecting errors typically provides hardware support to:
• Log sufficient information for software to determine what the error was along with
relevant details on the error.
• Disable error detection and reporting.
• Report if more than one error occurred. At a minimum, the unit will note that a
second error occurred. Optionally, a unit may gather additional information on
subsequent errors such as the type(s) of errors or other relevant details.
A given unit need not support all of these capabilities.To illustrate these capabilities,
consider the EP80579 DRAM interface. DRAM on the EP80579 is protected by ECC, so,
on a read with a double-bit error, the memory controller reports an error. The memory
controller can poison the data return value to inform future consumers of the data that
the data is bad.
For software, registers in the memory controller provide the ability to mask this error
along with logging registers that captures the address that was being read when the
error was encountered. On an unmasked double-bit error, the logging register captures
the address and the memory controller signals the IA-32 core through the FERR/NERR
infrastructure. The error address register is locked at this point, so subsequent errors
will not overwrite it until software handles the error and unlocks the registers by writing
a register to clear the error condition. The memory controller provides a “next error”
register that can capture information on other unmasked errors that occur before
software clears the double-bit error condition.
In general, the CMI will attempt to route requests based on their understanding of the
address space layout of the platform (that is, the amount of installed physical DRAM,
attached PCI Express* devices, etc.). There are several tables throughout the EAS that
define how various parts of the chip handle this routing task:
• Section 10.1, “Overview” and Section 10.2, “IMCH Responses to EDMA
Transactions” describes how the IMCH responses to transactions from the EDMA
engine.
• The memory controller does not perform bounds checking on addresses, error
handling behavior is determined by the upstream agents that pass the request to
the memory controller as Section 5.5.1, “Handling Out-of-Bounds Addresses” on
page 154 describes.
The IA portion uses the standard IA mechanisms to handle cases where this routing
encounters errors (e.g., accessing an unpopulated region of memory). These cases
cause aborts and are escalated through the normal error handling paths. On errors in
requests arriving from the memory target, the IMCH will drop writes (i.e., not forward
them into the IMCH) and poison data returns for reads through the appropriate push/
pull data error signals. These error conditions are reported through IMCH error
reporting registers.
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5.2.2
Software Usage Model
The software responsibilities for error handling are split between BIOS and system/
application software. The manner in which the software uses the capabilities that the
hardware provides depends on the specific software stack under consideration.
In general, BIOS does not establish a usage model for error handling. Its primary
responsibility is to configure the error handling registers throughout the EP80579 in a
manner consistent with the needs of system and application software. The EP80579
reference BIOS provides this level of support. However, in general, a BIOS
implementation may also log information on error events reported via SMI1. In this
case, BIOS populates data structures in SMBIOS2 that an operating system can later
retrieve.
Generally speaking, the software is more interested in seeing an error rather than the
specific location where it is sent. The usage model from the system or application
perspective depends on the manner in which the hardware reports the event to the
system along with the specific error event. There are two general types of reporting
that one can consider: through a kernel-trapped signal and through a non-kerneltrapped signal. A particular error event need be reported through at least one of these
mechanisms.
When the hardware reports an error event through a signal that the OS kernel handles
on its own (e.g., MCERR, SERR, etc.), the operating system takes whatever corrective
action it implements for the signal: bug check, panic, halt, reboot, event logging, clean
up and continue, etc. In this case, the OS kernel establishes the usage model. This
approach is only applicable to the IA and memory controller blocks since the AIOC
devices can only report error events through INTx or MSI signals that the OS kernel
passes off to the appropriate driver software rather than handle in the kernel.
When the hardware reports an error event error through a signal that the software
outside of the OS kernel handles on its own (e.g., INTx, MSI, etc.), it is the
responsibility of driver or other non-kernel software to take corrective action. All AIOC
agents fall into this category since their hardware uses only INTx or MSI for error
reporting. In this case, it is the responsibility of the driver software to establish the
error handling usage model. Typically, the action the driver takes in response to an
error event will match those taken by the OS kernel: panic, clean up and continue, etc.
5.3
Error Reporting by the IMCH
See Section 14.2, “Exception Handling” and Section 14.3, “Error Conditions Signaled”
for further discussion on IMCH error handling.
5.3.1
Overview of the First and Next Error Architecture
The IMCH provides a “first” and “next” error architecture wherein errors accumulate
locally in unit-level first/next error registers that the IMCH aggregates into global first/
next error registers. Once a unit records an error event in its “first” error register, it will
record all subsequent errors in its “next” error register until software clears the error
condition in the first error register. The error events are then classified into “fatal” and
“non-fatal” groups for reporting through the global first and next error registers. The
architecture allows software to mask individual error events at the unit level. In
addition, through per-unit registers, software can configure the hardware to report the
error event through IA SMI, SCI, SERR, or MCERR signals.
1. This approach only works for error events that the EP80579 can report through SMI. Specifically, this approach would not
work for error events from AIOC agents which cannot report through SMI in the EP80579.
2. System Management BIOS (SMBIOS) is a specification to lay out data structures and access methods in a BIOS which
provides for storage and retrieval of information about the PC in question
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The actions taken by the hardware in response to an error event depends on the
manner in which software has configured the IMCH to report the error. For unmasked
events that the IMCH signals through SMI, SCI, or SERR, the IMCH presents the error
to the IA-32 core indirectly through the IICH. In these cases, the IMCH sends an error
message to the IICH (via NSI) that IICH interrupt logic handles by signaling the IA-32
core through an interrupt. For unmasked events that the IMCH signals through MCERR,
the IMCH directly presents the error to the IA-32 core (via FSB). In this case, the IMCH
directly signals the IA-32 core through the MCERR protocol on the FSB.
After receiving the message, software will query the global IMCH error registers (see
Section 5.3.2, “Global Error Events”) to determine which IMCH unit is responsible for
the error. With that information, software can query the unit that generated the event
to determine the specific cause.
5.3.2
Global Error Events
Table 5-1 summarizes the error events that the IMCH captures in its GLOBAL_FERR and
GLOBAL_NERR error registers (see Section 16.2.1.12, “Offset 40h: GLOBAL_FERR Global First Error Register” and Section 16.2.1.13, “Offset 44h: GLOBAL_NERR - Global
Next Error Register”). Each of these events rolls up one or more unmasked error events
from an individual IMCH unit. To determine the specific error event that causes a
signal, software consults the unit-specific error registers that Table 5-1 indicates. The
global registers provide summary information only; masking takes place at the unit
level.
.
Table 5-1.
Summary of IMCH Global Error Conditions
Event
Fatalitya
Unit-Specific
Registers
DRAM Controller Fatal Error
Fatal
DRAM_FERR,
DRAM_NERR
FSB Fatal Error
Fatal
FSB_FERR,
FSB_NERR
Fatal error on internal CPU/IMCH FSB
interface.
NSI Fatal Error
Fatal
NSI_FERR,
NSI_NERR
Fatal error on internal IMCH/IICH NSI
interface.
DMA Fatal Error
Fatal
EDMA_FERR,
EDMA_NERR
PCI Express* Port A1, A0 Fatal
Error
Fatal
PEAFERR,
PEANERRb
Fatal error from PCI Express* Port A1
(PEA1) or A0 (PEA0).
Buffer Unit Non-Fatal Error
Non-Fatal
BUF_FERR,
BUF_NERR
Non-fatal error in posted memory write
buffer.
DRAM Controller Non-Fatal Error
Non-Fatal
DRAM_FERR,
DRAM_NERR
FSB Non-Fatal Error
Non-Fatal
FSB_FERR,
FSB_NERR
Non-fatal error on internal CPU/IMCH
FSB interface.
NSI Non-Fatal Error
Non-Fatal
NSI_FERR,
NSI_NERR
Non-fatal error on internal IMCH/IICH
NSI interface.
DMA Non-Fatal Error
Non-Fatal
EDMA_FERR,
EDMA_NERR
PCI Express* Port A1, A0 Non-Fatal
Error
Non-Fatal
PEAFERR,
PEANERRb
Notes
Fatal error in DRAM interface.
Fatal error from DMA controller.
Non-fatal error in DRAM interface.
Non-fatal error from DMA controller.
Non-fatal error from PCI Express* Port
A1 (PEA1) or A0 (PEA0).
a. Fatal versus non-fatal classification for reporting through GLOBAL_FERR and GLOBAL_NERR.
b. Each port has its own independent PEAFERR and PEANERR registers in the PCI configuration space for the port
controller device.
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Section 5.3.3, Section 5.3.4, Section 5.3.5, Section 5.3.6, Section 5.3.7, and
Section 5.3.8 discuss the specific per-unit events that the IMCH hardware captures and
rolls up into the global conditions that Table 5-1 lists.
5.3.3
Unit-Level Errors from the Buffer Unit
The IMCH buffer unit captures error events from the memory system coherent Posted
Memory Write Buffer (PMWB) in the BUF_FERR and BUF_NERR registers. The buffer
unit reports an error event to the IA-32 core through SCI, SMI, SERR, or MCERR signals
based on the settings in the BUF_SCICMD, BUF_SMICMD, BUF_SERRCMD, and
BUF_MCERRCMD registers. Software can independently configure the specific signal
that each buffer unit error event uses.
Table 5-2 summarizes the error conditions that the PMWB can generate.
.
Table 5-2.
Summary of IMCH Buffer Unit Error Conditions
Event
Type
Fatalitya
Reports viab
DRAM to PMWB
Parity
Uncorrectable
Non-Fatal
SCI, MCERR,
SMI, or SERR
Parity error detected on read from
DRAM agent by PMWB.
System Bus or I/O
to PMWB Parity
Uncorrectable
Non-Fatal
SCI, MCERR,
SMI, or SERR
Parity error detected on write to PMWB
from system bus or I/O agent.
PMWB to System
Bus Parity
Uncorrectable
Non-Fatal
SCI, MCERR,
SMI, or SERR
Parity error detected on data to the
system bus.
PMWB to DRAM
Parity
Uncorrectable
Non-Fatal
SCI, MCERR,
SMI, or SERR
Parity error detected when PMWB is
flushed to DRAM.
Notes
a. Fatal versus non-fatal classification for reporting through GLOBAL_FERR and GLOBAL_NERR.
b. Based on BUF_SCICMD, BUF_SMICMD, BUF_SERRCMD, and BUF_MCERRCMD register values.
Table 5-3 summarizes the capabilities of the IMCH buffer unit error handling for each of
the features that the unit is expected to provide.
Table 5-3.
Summary of IMCH Buffer Unit Error Reporting Capabilities
Feature
Implementation
Enabling and
Masking Error
Reporting
The BUF_EMASK (see Section 16.2.1.29, “Offset 74h: BUF_EMASK - Memory Buffer Error
Mask Register”), BUF_SCICMD, BUF_SMICMD, BUF_SERRCMD, and BUF_MCERRCMD
registers enable and mask error reporting.
The PCICMD register (see Section 16.2.1.3, “Offset 04h: PCICMD - PCI Command
Register”) also enables and masks SERR signals.
Logging Details
IMCH does not capture error logging information beyond the event flags in the BUF_FERR,
BUF_NERR and PCISTS (see Section 16.2.1.4, “Offset 06h: PCISTS - PCI Status Register”)
registers.
Reporting Multiple
Errors
The BUF_NERR register captures “next” errors. This register indicates up to one additional
error (beyond the first error) of each type.
Data Poisoning
5.3.4
IMCH passes along error information to poison data.
Unit-Level Errors from the DRAM Interface
These errors include the error events reported by the memory controller, see Section
5.5, “Error Reporting by the System Memory Controller” on page 153 for additional
details.
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5.3.5
Unit-Level Errors from the FSB Interface
The FSB interface captures error events from the FSB interface that connects the IA-32
core to the IMCH in the FSB_FERR and FSB_NERR registers. The FSB interface reports
an error event to the IA-32 core through SCI, SMI, SERR, or MCERR signals based on
the settings in the FSB_SCICMD, FSB_SMICMD, FSB_SERRCMD, and FSB_MCERRCMD
registers. Software can independently configure the specific signal that each buffer unit
error event uses.
Table 5-4 summarizes the error conditions that the FSB can generate.
.
Table 5-4.
Summary of IMCH FSB Error Conditions
Event
Type
Fatalitya
Reports viab
Notes
Outgoing I/O Data
Parity
Uncorrectable
Non-Fatal
SCI, MCERR,
SMI, or SERR
Parity error on outgoing data from I/O
subsystem.
Outgoing Memory
Data Parity
Uncorrectable
Non-Fatal
SCI, MCERR,
SMI, or SERR
Parity error on outgoing data from
memory subsystem.
FSB BINIT#
Detected
Uncorrectable
Fatal
N/Ac
Electrical high-to-low transition of
BINIT#.
FSB MCERR#
Detected
Uncorrectable
Non-Fatal
SCI, MCERR,
SMI, or SERR
Electrical high-to-low transition of
MCERR# when CMI is not driving.
Non-DRAM Lock
Error
Uncorrectable
Non-Fatal
SCI, MCERR,
SMI, or SERR
Lock detected to memory space that
does not map to DRAM.
FSB Addr. Above
TOM/TOLM
Uncorrectable
Non-Fatal
SCI, MCERR,
SMI, or SERR
Address detected above TOM/TOLM.
FSB Data Parity
Uncorrectable
Non-Fatal
N/Ac
Parity error on FSB detected.
FSB Addr. Strobe
Glitch Detected
Uncorrectable
Fatal
N/Ac
Glitch detected on FSB address strobe.
FSB Data Strobe
Glitch Detected
Uncorrectable
Fatal
N/Ac
Glitch detected on FSB data strobe.
FSB Request/Addr
Parity
Uncorrectable
Fatal
N/Ac
Party error on FSB address or request
signals.
a. Fatal versus non-fatal classification for reporting through GLOBAL_FERR and GLOBAL_NERR.
b. Based on FSB_SCICMD, FSB_SMICMD, FSB_SERRCMD, and FSB_MCERRCMD register values.
c. Although the IMCH supports these errors, the EP80579 will not ever generate them since its on-die FSB
implementation does not support BINIT# or parity.
Table 5-5 summarizes the capabilities of the FSB error handling for each of the features
that the unit is expected to provide.
Table 5-5.
Summary of IMCH FSB Error Reporting Capabilities
Feature
Enabling and
Masking Error
Reporting
Implementation
The FSB_EMASK FSB_SCICMD, FSB_SMICMD, FSB_SERRCMD, and FSB_MCERRCMD
registers enable and mask error reporting.
The PCICMD register also enables and masks SERR signals.
Logging Details
FSB does not capture error logging information beyond the event flags in the FSB_FERR,
FSB_NERR and PCISTS
Reporting Multiple
Errors
The FSB_NERR register captures “next” errors. This register indicates up to one additional
error (beyond the first error) of each type.
Data Poisoning
FSB passes along error information to poison data.
Although the IMCH supports all of the errors Table 5-4 lists with the features in
Table 5-5, the EP80579 implementation does not take full advantage of these
capabilities since its FSB implementation does not support all of the features necessary.
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For additional discussion on the IMCH responses to transactions from the FSB interface,
see Section 10.1, “Overview”.
5.3.6
Unit-Level Errors from the NSI
The IMCH hardware captures error events from the NSI interface that connects the
IMCH to the IICH in the NSI_FERR and NSI_NERR registers. The NSI interface reports
an error event to the IA-32 core through IA SCI, SMI, SERR, or MCERR signals based
on the settings in the NSI_SCICMD, NSI_SMICMD, NSI_SERRCMD, and
NSI_MCERRCMD registers. Software can independently configure the specific signal
that each buffer unit error event uses.
Table 5-6 summarizes the error conditions that the NSI can generate.
.
Table 5-6.
Summary of IMCH NSI Error Conditions
Event
Type
Fatalitya
Reports viab
Unsupported
Request
Uncorrectable
Fatal, NonFatal
SCI, MCERR,
SMI, or SERR
Unsupported request detected.
Malformed TLP
Uncorrectable
Fatal, NonFatal
SCI, MCERR,
SMI, or SERR
Malformed TLP detected.
Receiver Overflow
Uncorrectable
Fatal
SCI, MCERR,
SMI, or SERR
Overflow detected in posted, nonposted, or completion upstream queue.
Unexpected
Completion
Uncorrectable
Non-Fatal
SCI, MCERR,
SMI, or SERR
Completion received that does not
correspond to an outstanding request.
Completer Abort
Uncorrectable
Non-Fatal
SCI, MCERR,
SMI, or SERR
Completer abort detected.
Completion
Timeout
Uncorrectable
Non-Fatal
SCI, MCERR,
SMI, or SERR
Request not completed within timeout
window.
Poisoned TLP
Uncorrectable
Non-Fatal
SCI, MCERR,
SMI, or SERR
Portion of TLP data payload was
corrupt.
Data Link Protocol
Error
Uncorrectable
Fatal
SCI, MCERR,
SMI, or SERR
Error detected in data link protocol.
Replay Timer
Timeout
Uncorrectable
Non-Fatal
SCI, MCERR,
SMI, or SERR
Replay timer expired.
REPLAY_NUM
Rollover
Uncorrectable
Non-Fatal
SCI, MCERR,
SMI, or SERR
Retry buffer replay counter rolled over.
Bad DLLP CRC
Uncorrectable
Non-Fatal
SCI, MCERR,
SMI, or SERR
Calculated DLLP CRC did not equal
received value.
Bad TLP CRC
Uncorrectable
Non-Fatal
SCI, MCERR,
SMI, or SERR
Calculated TLP CRC did not equal
received value.
Receiver Error
Uncorrectable
Non-Fatal
SCI, MCERR,
SMI, or SERR
Packet framing error.
Received Fatal
Error Message
Uncorrectable
Fatal
SCI, MCERR,
SMI, or SERR
Fatal error message received over NSI
link.
Received NonFatal Error
Message
Uncorrectable
Non-Fatal
SCI, MCERR,
SMI, or SERR
Non-fatal error message received over
NSI link.
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Table 5-6.
Summary of IMCH NSI Error Conditions
Event
Type
Fatalitya
Reports viab
Received
Correctable Error
Message
Correctable
Non-Fatal
SCI, MCERR,
SMI, or SERR
Correctable error message received
over NSI link.
Parity Error on
Data from Core
Uncorrectable
Non-Fatal
SCI, MCERR,
SMI, or SERR
Parity error detected on data received
from core.
Link Down
Uncorrectable
Fatal
SCI, MCERR,
SMI, or SERR
Link transitioned from DL_UP to
DL_DOWN.
Notes
a. Fatal versus non-fatal classification for reporting through GLOBAL_FERR and GLOBAL_NERR.
b. Based on NSI_SCICMD, NSI_SMICMD, NSI_SERRCMD, and NSI_MCERRCMD register values.
Table 5-7 summarizes the capabilities of the NSI error handling for each of the features
that the unit is expected to provide.
Table 5-7.
Summary of IMCH NSI Error Reporting Capabilities
Feature
Enabling and
Masking Error
Reporting
Logging Details
Reporting Multiple
Errors
Data Poisoning
Implementation
The NSI_EMASK, NSI_SCICMD, NSI_SMICMD, NSI_SERRCMD, and NSI_MCERRCMD
registers enables and masks error reporting.
The PCICMD register also enables and masks SERR signals.
NSI captures error logging information in the following registers:
• All errors: NSI_FERR, NSI_NERR, and PCISTS capture event flags.
• Poisoned TLP: PCISTS captures event flags.
• Received fatal/non-fatal/correctable error messages: NSI_ERRSID.
All of the logging information that the NSI captures relates to the “first” error with the
exception of NSI_NERR.
The NSI_NERR register captures “next” errors. This register indicates up to one additional
error (beyond the first error) of each type.
NSI passes along error information to poison data.
For additional discussion on the IMCH responses to transactions from the NSI interface,
see Section 10.1, “Overview”.
5.3.7
Unit-Level Errors from the EDMA Engine
The IMCH EDMA unit captures error events from the EDMA engine in the EDMA_FERR
and EDMA_NERR registers (The EDMA unit reports an error event to the IA-32 core
through IA SCI, SMI, SERR, or MCERR signals based on the settings in the
EDMA_SCICMD, EDMA_SMICMD, EDMA_SERRCMD, and EDMA_MCERRCMD registers.
Software can independently configure the specific signal that each EDMA unit error
event uses.
Table 5-8 summarizes the error conditions that the EDMA can generate.
.
Table 5-8.
Summary of IMCH EDMA Error Conditions
Event
Type
Fatalitya
Reports viab
NDAR Addressing
Error
Uncorrectable
Non-Fatal
SCI, MCERR,
SMI, or SERR
Descriptor pointer is of incorrect type
or range for channels 0-3.
NDAR Alignment
Error
Uncorrectable
Non-Fatal
SCI, MCERR,
SMI, or SERR
Descriptor pointer is not aligned to an
8 DW boundary for channels 0-3.
Source Address
Error
Uncorrectable
Non-Fatal
SCI, MCERR,
SMI, or SERR
Source address does not comply with
source type or range for channels 0-3.
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Table 5-8.
Summary of IMCH EDMA Error Conditions
Event
Type
Fatalitya
Reports viab
Destination
Address Error
Uncorrectable
Non-Fatal
SCI, MCERR,
SMI, or SERR
Destination address does not comply
with destination type or range for
channels 0-3.
Parity Error
Uncorrectable
Non-Fatal
SCI, MCERR,
SMI, or SERR
Parity error during read of source data
from system memory for channels 0-3.
Write Error
Uncorrectable
Non-Fatal
SCI, MCERR,
SMI, or SERR
Write to RO descriptor registers when
DMA in normal mode for channels 0-3.
Notes
a. Fatal versus non-fatal classification for reporting through GLOBAL_FERR and GLOBAL_NERR.
b. Based on EDMA_SCICMD, EDMA_SMICMD, EDMA_SERRCMD, and EDMA_MCERRCMD register values.
Table 5-9 summarizes the capabilities of the EDMA error handling for each of the
features that the unit is expected to provide.
Table 5-9.
Summary of IMCH EDMA Error Reporting Capabilities
Feature
Enabling and
Masking Error
Reporting
Logging Details
Reporting Multiple
Errors
Data Poisoning
Implementation
The EDMA_EMASK, EDMA_SCICMD, EDMA_SMICMD, EDMA_SERRCMD, and
EDMA_MCERRCMD registers enables and masks error reporting.
The PCICMD register also enables and masks SERR signals.
EDMA does not capture error logging information beyond the event flags in the
EDMA_FERR, EDMA_NERR and PCISTS.
The EDMA_NERR register captures “next” errors. This register indicates up to one
additional error (beyond the first error) of each type.
EDMA passes along error information to poison data.
For additional discussion on the IMCH responses to transactions from the EDMA engine,
see Section 10.1, “Overview” and Section 10.2, “IMCH Responses to EDMA
Transactions”.
5.3.8
Unit-Level Errors from PCI Express* Ports A0 and A1
The IMCH PCI Express* Port Controllers capture error events from the port A0 and A1
controllers in per-port registers. The register set provides two parallel error reporting
mechanisms, one that reports standard errors defined by the PCI Express*
specification and a second that reports errors that are specific to the EP80579 PCI
Express* implementation (and thus, outside of the standard PCI Express* errors).
The PCI Express* controllers capture errors required by the PCI Express* base
specification in the UNCERRSTS and CORERRSTS registers. The controllers capture
EP80579-specific errors in the PEAUNITERR register. The errors from both sets of
errors are aggregated in the PEAFERR and PEANERR registers. The PCI Express*
controllers report an error event to the IA-32 core through IA SCI, SMI, SERR, or
MCERR signals based on the settings in the PEAERRDOCMD register.
Table 5-10 summarizes the error conditions that the PCI-Express can generate.
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Table 5-10. Summary of IMCH PCI-Express Error Conditions
Event
Type
Fatalitya
Reports viab
Unsupported
Request
Uncorrectable
UNCERRSEVc
SCI, MCERR,
SMI, or SERR
Request type unsupported.
ECRC Error
Uncorrectable
UNCERRSEVc
SCI, MCERR,
SMI, or SERR
Error in ECRC.
Malformed TLP
Uncorrectable
UNCERRSEVc
SCI, MCERR,
SMI, or SERR
Malformed TLP, like it says...
Receiver Overflow
Uncorrectable
UNCERRSEVc
SCI, MCERR,
SMI, or SERR
Overflow on upstream queue.
Unexpected
Completion
Uncorrectable
UNCERRSEVc
SCI, MCERR,
SMI, or SERR
Received completion that does not
match any outstanding requests.
Completer Abort
Uncorrectable
UNCERRSEVc
SCI, MCERR,
SMI, or SERR
Received request violates
programming model.
Completion
Timeout
Uncorrectable
UNCERRSEVc
SCI, MCERR,
SMI, or SERR
Timeout.
Flow Control
Protocol Error
Uncorrectable
UNCERRSEVc
SCI, MCERR,
SMI, or SERR
Poisoned TLP
Uncorrectable
UNCERRSEVc
SCI, MCERR,
SMI, or SERR
TLP data payload corrupt.
Data Link Protocol
Uncorrectable
UNCERRSEVc
SCI, MCERR,
SMI, or SERR
ACK/NACK has incorrect sequence
number.
Unsupported
Request
Uncorrectable
UNCERRSEVc
SCI, MCERR,
SMI, or SERR
Unsupported
Request
Uncorrectable
UNCERRSEVc
SCI, MCERR,
SMI, or SERR
Unsupported
Request
Uncorrectable
UNCERRSEVc
SCI, MCERR,
SMI, or SERR
Replay Timer
Correctable
Non-Fatal
SCI, MCERR,
SMI, or SERR
Replay timer expired.
REPLAY_NUM
Rollover
Correctable
Non-Fatal
SCI, MCERR,
SMI, or SERR
Retry buffer counter rolled over.
Bad DLLP Status
Correctable
Non-Fatal
SCI, MCERR,
SMI, or SERR
Computed DLLP CRC does not match
received value.
Bad TLP status
Correctable
Non-Fatal
SCI, MCERR,
SMI, or SERR
Computed TLP CRC does not match
received value.
Receiver Error
Correctable
Non-Fatal
SCI, MCERR,
SMI, or SERR
Received 8b/10b error.
LLE Protocol Error
Uncorrectable
Non-Fatal
SCI, MCERR,
SMI, or SERR
Transaction layer detected protocol
error.
Link Down Error
Uncorrectable
Fatal
SCI, MCERR,
SMI, or SERR
Link transitions from DL_UP to
DL_DOWN.
Downstream Data
Queue Parity
Uncorrectable
Non-Fatal
SCI, MCERR,
SMI, or SERR
Parity error occurred in downstream
data queue.
SMB Clock
Timeout
Uncorrectable
Non-Fatal
SCI, MCERR,
SMI, or SERR
SMB CLK low greater than 25ms.
Unexpected NAK
on SMB
Uncorrectable
Non-Fatal
SCI, MCERR,
SMI, or SERR
Unexpected NAK on SMB.
SMB Arbitration
Uncorrectable
Non-Fatal
SCI, MCERR,
SMI, or SERR
SMB lost bus arbitration.
Notes
a. Fatal versus non-fatal classification for reporting through GLOBAL_FERR and GLOBAL_NERR.
b. Based on PEAERRDOCMD register value.
c. Severity is set by the UNCERRSEV register.
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Table 5-11 summarizes the capabilities of the PCI-Express error handling for each of
the features that the unit is expected to provide.
Table 5-11. Summary of IMCH PCI-Express Error Reporting Capabilities
Feature
Implementation
Enabling and
Masking Error
Reporting
The UNCERRMSK, UNCEDMASK, CORERRMSK, COREDMASK, RPMERRSTS, PEAMASKERR,
RPERRCMD, and PEAERRDOCMD registers enables and masks error reporting.
The PCICMD register also enables and masks SERR signals.
Logging Details
PCI Express* controllers captures error logging information in the following registers:
• RPMERRSTS errors: ERRSID captures requester IDs.
• Errors with Header Capture: HDRLOG0, HDRLOG1, HDRLOG2, and HDRLOG3 captures
the first four 32-bit words of the headers.
This information is in addition to the status information in UNCERRSTS, CORERRSTS,
RPMERRSTS, PEAFERR, and PEANERR.
Reporting Multiple
Errors
The PEANERR and RPERRMSTS registers captures “next” errors. This register indicates up
to one additional error (beyond the first error) of each type.
Data Poisoning
PCI Express* controllers pass along error information to poison data.
See Section 16.4, “PCI Express* Port A Standard and Enhanced Registers: Bus 0,
Devices 2 and 3, Function 0” for additional details.
For additional discussion on the IMCH responses to transactions from the PCI Express*
ports, see Section 10.1, “Overview”.
5.4
Error Reporting by the IICH
The EP80579 IICH devices rely on the PCI error reporting architecture to reporting
errors. In this architecture, details on the errors are logged in the PCI status register
from the per-device PCI configuration header. A parity or other severe system error
causes the device to generate an IA SERR signal.
Errors that occur on the NSI bus between the IMCH and IICH report through the
NSI_FERR and NSI_NERR infrastructure as Section 5.3.1, “Overview of the First and
Next Error Architecture” on page 141 and Section 5.3.6, “Unit-Level Errors from the
NSI” on page 145 describe.
On the IICH backbone, IICH devices must rely entirely on the SERR signal that the
device generates on an error event to report the error. The IICH does not provide any
other capability (such as data poisoning) that would allow a consumer of IICH data to
note an error. As a result, an IICH device can return erroneous data on a request.
The remainder of this section describes the error handling capabilities of the units in
the IICH.
5.4.1
SMBus Interface
The IICH provides a SMBus controller that can generate an interrupt or SMI on error
events and can also use the PCI SERR infrastructure to report errors. The HCFG register
selects either SMI or interrupt signaling; parity and system errors always signal
through SERR. Table 5-12 summarizes the error conditions that the controller reports.
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Table 5-12. Summary of SMBus Interface Error Conditions
Event
Type
Fatalitya
Reports via
Notes
b
Device Error
Uncorrectable
Fatal
Interrupt, SMI
Bus Error
Uncorrectable
Fatal
Interrupt, SMIb Bus error.
Failed Bus
Transaction
Uncorrectable
Fatal
Interrupt, SMIb Bus transaction failed.
Parity Error
Uncorrectable
Fatal
SERR
Parity error detected.
System Error
Uncorrectable
Fatal
SERR
System error detected.
Device error.
a. “Fatal” events result in data loss or data corruption that the unit cannot repair, “Non-Fatal” events do not.
b. Based on HCFG register values.
Table 5-13 summarizes the capabilities of the SMBus controller error handling for each
of the features that the unit is expected to provide.
Table 5-13. Summary of SMBus Controller Error Reporting Capabilities
Feature
Implementation
Enabling and Masking Error
Reporting
The CMD and USBINTR registers enables and masks error reporting.
The USB 1.1 interface captures the type of event detected in the DSR,
HSTS, and AUXS registers.
Logging Details
Reporting Multiple Errors
Data Poisoning
The SMBus interface does not capture multiple events.
IICH backbone does not support data poisoning.
For additional details on error handling in the SMBus controller, see Section 24.0,
“SMBus Controller Functional Description: Bus 0, Device 31, Function 3”.
5.4.2
LPC Interface
The IICH provides a LPC interface that uses the PCI SERR infrastructure to report
errors. Table 5-14 summarizes the error conditions that the controller reports.
.
Table 5-14. Summary of LPC Interface Error Conditions
Type
Fatalitya
Reports via
Parity Error
Uncorrectable
Fatal
SERR
Parity error detected.
System Error
Uncorrectable
Fatal
SERR
System error detected.
Event
Notes
a. “Fatal” events result in data loss or data corruption that the unit cannot repair, “Non-Fatal” events do not.
Table 5-15 summarizes the capabilities of the LPC interface error handling for each of
the features that the unit is expected to provide.
Table 5-15. Summary of LPC Interface Error Reporting Capabilities
Feature
Enabling and
Masking Error
Reporting
Implementation
The CMD register supports error enabling and masking.
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Table 5-15. Summary of LPC Interface Error Reporting Capabilities
Feature
Logging Details
Reporting Multiple
Errors
Data Poisoning
Implementation
The LPC interface captures the type of event detected in the STS register.
The LPC interface does not capture multiple events.
IICH backbone does not support data poisoning.
For additional details on error handling in the LPC interface, see Section 19.0, “LPC
Interface: Bus 0, Device 31, Function 0”.
5.4.3
USB 1.1 Interface
The IICH provides a USB 1.1 controller that can generate an interrupt on error events
and can also use the PCI SERR infrastructure to report errors. Table 5-16 summarizes
the error conditions that the controller reports.
.
Table 5-16. Summary of USB 1.1 Interface Error Conditions
Event
Type
Fatalitya
Reports via
Host Controller
Process Error
Uncorrectable
Fatal
Interrupt
Consistency check by host controller
fails while processing a TD.
Host System Error
Uncorrectable
Fatal
Interrupt
Serious error during host system
access involving HC module.
USB Error
Uncorrectable
Fatal
Interrupt
USB transaction completion ended in
error.
Parity Error
Uncorrectable
Fatal
SERR
Notes
Parity error on read completion
returned to host controller or UHCI
register write.
a. “Fatal” events result in data loss or data corruption that the unit cannot repair, “Non-Fatal” events do not.
Table 5-17 summarizes the capabilities of the USB 1.1 controller error handling for each
of the features that the unit is expected to provide.
Table 5-17. Summary of USB 1.1 Interface Error Reporting Capabilities
Feature
Enabling and
Masking Error
Reporting
Logging Details
Reporting Multiple
Errors
Data Poisoning
Implementation
The CMD and USBINTR registers supports error enabling and masking.
The USB 1.1 interface captures the type of event detected in the DSR and USBSTS
registers.
The USB 1.1 interface does not capture multiple events, error events cause the interface
to halt operation until serviced by software.
IICH backbone does not support data poisoning.
For additional details on error handling in the USB 1.1 controller, see Section 25.0,
“USB (1.1) Controller: Bus 0, Device 29, Function 0”.
5.4.4
USB 2.0 Interface
The IICH provides a USB 2.0 controller that can generate an interrupt on error events
and can also use the PCI SERR infrastructure to report errors. Table 5-18 summarizes
the error conditions that the controller reports.
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Table 5-18. Summary of USB 2.0 Interface Error Conditions
Event
Type
Fatalitya
Reports via
Host System Error
Uncorrectable
Fatal
Interrupt
Serious error during host system
access involving HC module.
USB Error
Uncorrectable
Fatal
Interrupt
USB transaction completion ended in
error.
Parity Error
Uncorrectable
Fatal
SERR
Parity error on USB read completion.
System Error
Uncorrectable
Fatal
SERR
Parity error on address, command, or
data, or unsuccessful completion of
ECH-initiated read.
Notes
a. “Fatal” events result in data loss or data corruption that the unit cannot repair, “Non-Fatal” events do not.
Table 5-19 summarizes the capabilities of the USB 2.0 controller error handling for each
of the features that the unit is expected to provide.
Table 5-19. Summary of USB 2.0 Interface Error Reporting Capabilities
Feature
Implementation
Enabling and Masking Error
Reporting
The CMD and USB20INTR registers supports error enabling and masking.
Logging Details
The USB 2.0 interface captures the type of event detected in the DSR
and USB20STS registers.
Reporting Multiple Errors
The USB 2.0 interface does not capture multiple events, error events
cause the interface to halt operation until serviced by software.
Data Poisoning
IICH backbone does not support data poisoning.
For additional details on error handling in the USB 2.0 controller, see Section 26.0,
“USB 2.0 Host Controller: Bus 0, Device 29, Function 7”.
5.4.5
SATA Interface
The IICH provides a SATA interface that can generate an interrupt on error events and
can also use the PCI PERR infrastructure to report errors. Table 5-20 summarizes the
error conditions that the controller reports.
.
Table 5-20. Summary of SATA Interface Error Conditions
Event
Type
Fatalitya
Reports via
Host Bus Fatal
Error
Uncorrectable
Fatal
Interrupt
Unrecoverable host bus error
Host Bus Data
Error
Uncorrectable
Fatal
Interrupt
Uncorrectable data error.
Interface Fatal
Error
Uncorrectable
Fatal
Interrupt
Fatal error on SATA interface.
Interface NonFatal Error
Uncorrectable
Non-Fatal
Interrupt
Non-fatal error on SATA interface.
Parity Error
Uncorrectable
Fatal
SERR
Parity error detected on interface.
Notes
a. “Fatal” events result in data loss or data corruption that the unit cannot repair, “Non-Fatal” events do not.
Table 5-21 summarizes the capabilities of the SATA controller error handling for each of
the features that the unit is expected to provide.
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Table 5-21. Summary of SATA Interface Error Reporting Capabilities
Feature
Enabling and
Masking Error
Reporting
Logging Details
Reporting Multiple
Errors
Data Poisoning
Implementation
The CMD and PIE[0-3] registers support error enabling and masking.
The SATA interface captures the type of event detected in the STS and PIS[0-3] registers.
The SATA interface does not capture multiple events.
IICH backbone does not support data poisoning.
For additional details on error handling in the SATA interface, see Section 23.0, “SATA:
Bus 0, Device 31, Function 2”.
5.4.6
Serial I/O Interface
The IICH provides a serial I/O interface that can generate an interrupt on error events.
Table 5-22 summarizes the error conditions that the serial I/O interface captures.
.
Table 5-22. Summary of Serial I/O Interface Error Conditions
Event
Type
Fatalitya
Reports via
Framing Error
Uncorrectable
Fatal
Interrupt
Received character missing stop bit.
Parity Error
Uncorrectable
Fatal
Interrupt
Received character has parity error.
Overrun Error
Uncorrectable
Fatal
Interrupt
Receive buffer over-written.
Notes
a. “Fatal” events result in data loss or data corruption that the unit cannot repair, “Non-Fatal” events do not.
Table 5-23 summarizes the capabilities of the thermal sensor error handling for each of
the features that the unit is expected to provide.
Table 5-23. Summary of Serial I/O Interface Error Reporting Capabilities
Feature
Enabling and Masking Error
Reporting
Logging Details
Reporting Multiple Errors
Data Poisoning
Implementation
The IER and LCR registers supports error enabling and masking.
The serial I/O interface captures the type of event detected in the IIR and
LSR registers.
The serial I/O interface does not capture multiple events.
N/A
For additional details on error handling in the serial I/O interface, see Section 33.0,
“Serial I/O Unit and Watchdog Timer”.
5.5
Error Reporting by the System Memory Controller
The memory controller interfaces with memory to provide data movement to and from
DRAM along the AIOC-direct and coherent paths to memory. The memory controller is
designed to conform to the IMCH first and next error handling architecture that Section
5.3.1, “Overview of the First and Next Error Architecture” on page 141 describes. The
memory controller reports its unit-level first/next error events through the DRAM_FERR
and DRAM_NERR registers in the memory controller (see Section 11.5, “Error
Handling”). The flow of memory controller errors matches the IMCH behavior for its
other errors as Section 5.3.1 describes.
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5.5.1
Handling Out-of-Bounds Addresses
The memory controller does not perform any bounds checking on system addresses
that it receives from other agents. As a result, the behavior of the EP80579 in response
to an access to a DRAM location that is outside the range of populated memory
depends on the source of the transaction and the path it takes through the device.
There are two paths of relevance to this discussion: the Coherent path through the
IMCH and the AIOC-Direct path directly to the memory controller.
Accesses to locations above top of memory along the Coherent path (from either AIOC
agents via the AIOC-interface, the IA-32 core, or other agents attached to the CMI
through PCI Express*, etc.) will be aborted by the IMCH. The specific manner of the
abort depends on whether the transaction originates from the IA-32 core or a AIOC
agent.
Access to locations above top of memory along the AIOC-Direct path (from the AIOC
Memory Target) are not aborted or otherwise trapped by default. The results of such
transactions are undefined and may alias onto populated memory regions. As a result,
software must program the EP80579 so that it can never generate an AIOC-Direct
system address above TOM. The Memory Target provides the ability to log range errors
(and optionally halt the AIOC master that generated the transaction).
5.5.2
IMCH - Memory Controller
The memory controller can notify the IA-32 core of memory-related error events
through SCI, SMI, SERR, or MCERR signals based on the settings in the
DRAM_SCICMD, DRAM_SMICMD, DRAM_SERRCMD, and DRAM_MCERRCMD registers
(see Section 11.0, “System Memory Controller”). Software can configure the specific
signal used for each error event independently.
Table 5-24 summarizes the error conditions that the memory controller captures. Note
that the memory controller always reports errors through the non-fatal classification in
the error reporting registers.
.
Table 5-24. Summary of Memory Controller Error Conditions
Event
Type
Fatalitya
Reports viab
Uncorrectable
Write Error
Uncorrectable
Fatal
SCI, MCERR,
SMI, or SERR
Write of poisoned data to DRAM.
Uncorrectable
Read Error
Uncorrectable
Fatal
SCI, MCERR,
SMI, or SERR
Error during normal demand reads.
Uncorrectable
Scrubber Data
Error
Uncorrectable
Fatal
SCI, MCERR,
SMI, or SERR
Memory scrubber encountered an
uncorrectable error.
Correctable Read
Error
Correctable
Non-Fatal
SCI, MCERR,
SMI, or SERR
Hardware will correct and report if
appropriately configured
Error Threshold
Detect
Status
Non-Fatal
SCI, MCERR,
SMI, or SERR
Count of single- or double-bit errors
exceeds a programmable threshold.
Memory Test
Complete
Status
Non-Fatal
SCI, MCERR,
SMI, or SERR
Status event to indicate when memory
test hardware completes testing.
Notes
a. “Fatal” events result in data loss or data corruption that the unit cannot repair, “Non-Fatal” events do not. This
can differ from the fatal/non-fatal classification for reporting through GLOBAL_FERR and GLOBAL_NERR.
b. Based on DRAM_SCICMD, DRAM_SMICMD, DRAM_SERRCMD, and DRAM_MCERRCMD register values.
Table 5-25 summarizes the capabilities of the memory controller error handling for
each of the features that the unit is expected to provide.
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Table 5-25. Summary of Memory Controller Error Reporting Capabilities
Feature
Enabling and
Masking Error
Reporting
Logging Details
Implementation
The DRAM_EMASK, DRAM_SCICMD, DRAM_SMICMD, DRAM_SERRCMD, and
DRAM_MCERRCMD registers enable and mask error reporting.
Memory Controller captures additional error logging information in the following registers:
• Uncorrectable read errors: DRAM_DED_ADD.
• Uncorrectable scrubber data errors: DRAM_SCRB_ADD.
• Correctable read errors: DRAM_SECF_ADD, DRAM_SECF_SYNDROME,
DRAM_SECN_ADD, DRAM_SECN_SYNDROME.
• Error threshold detect: RANKTHREX, THRESH_SEC0, THRESH_SEC1, THRESH_DED,
DRAM_SEC_R0, DRAM_SEC_R1, DRAM_DED_R0, DRAM_DED_R1.
Additional logging information is not captured for the remaining errors in Table 5-24.
With the exception of DRAM_SECN_ADD and DRAM_SECN_SYNDROME, all of the logging
information that the memory controller captures relates to the “first” error.
Reporting Multiple
Errors
The DRAM_NERR register captures the “next” errors seen by the memory controller. This
register indicates up to one additional error (beyond the first error) of each type.
Data Poisoning
Memory Controller passes along error information to poison data both on inbound (from
memory) data and outbound (to memory) data.
For additional details on error handling in the memory controller, see Section 11.5,
“Error Handling”.
5.6
Error Reporting by AIOC Devices
The AIOC devices continue to use the native error reporting infrastructure that each
unit provides. Primarily, this infrastructure relies on one or more side-band error
signals from each AIOC device that can signal an error along with parity protection on
key interfaces. The AIOC native error reporting mechanisms are then bridged into the
PCI framework that the EP80579 uses to expose AIOC devices to IA. Although AIOC
devices present a PCI interface to IA, they do not implement PCI error reporting
capabilities such as SERR. As a result, the native signals from the AIOC devices are
bridged onto PCI INTx or MSI signals. This implies that the driver software provides all
error handling for AIOC units1.
The following sections describe the error reporting for each of the AIOC units along with
transaction responses. The per-unit presentations are organized by the PCI device in
which the units materialize.
5.6.1
Gigabit Ethernet MAC
The Gigabit Ethernet MAC units each signal error conditions through three interrupt
signals: Functional 0, Functional 1, and Error. Software uses the IMS0, IMS1, and IMS2
configuration registers in a Gigabit Ethernet MAC to map error conditions onto the
Functional 0, Functional 1, and Error interrupt signals, respectively. Depending on the
configuration, error and functional events may share an interrupt (e.g., software may
configure the functional 1 interrupt to signal both error and functional events);
typically, software will configure a MAC to deliver its error events separately through
only the error interrupt.
Table 5-26 summarizes the error conditions that the Gigabit Ethernet MAC captures.
1. If PCI abstractions such as SERR were used, this would not be the case. Platform and/or O/S software would also be involved
in error handling for the devices even if the involvement is limited to generating a blue screen.
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Table 5-26. Summary of Gigabit Ethernet MAC Error Conditions
Event
Type
Fatalitya
Reports viab
Statistic Register
ECC Error
Uncorrectable
Fatal
ERR, FN0, or
FN1 Interrupts
Double-bit ECC error in a statistic
register.
Internal Memory
Error
Uncorrectable
Fatal
ERR, FN0, or
FN1 Interrupts
Parity or double-bit ECC error in an
internal memory.
DMA Packet Buffer
Error
Uncorrectable
Fatal
ERR, FN0, or
FN1 Interrupts
Double-bit ECC error during read from
DMA packet buffer on Tx or Rx.
DMA Tx Desc. ECC
Error
Uncorrectable
Fatal
ERR, FN0, or
FN1 Interrupts
Double-bit ECC error during read from
DMA transmit descriptor.
DMA Rx Desc. ECC
Error
Uncorrectable
Fatal
ERR, FN0, or
FN1 Interrupts
Double-bit ECC error during read from
DAM receive descriptor.
Notes
a. “Fatal” events result in data loss or data corruption that the unit cannot repair, “Non-Fatal” events do not.
b. Based on settings in IMS0, IMS1, and IMS2 registers.
Table 5-27 summarizes the capabilities of the Gigabit Ethernet MAC error handling for
each of the features that the unit is expected to provide.
Table 5-27. Summary of Gigabit Ethernet MAC Error Reporting Capabilities
Feature
Implementation
Enabling and
Masking Error
Reporting
The IMS0, IMS1, and IMS2 interrupt mask set registers and the IMC0, IMC1, and IMC2
interrupt mask clear registers support error enabling and masking.
When software configures the GbE to deliver errors on their own interrupt, the SMIA and
SMME registers from the signal target capability in the PCI configuration header for a GbE
MAC can also support error enabling and masking.
Logging Details
The SINT register from the signal target capability in the PCI configuration header for a
GbE MAC provides read-only access to the state of the interrupt signals from a GbE MAC.
Additional logging information is not captured for the other errors in Table 5-26.
Reporting Multiple
Errors
Individual status bits in the GbE ICR0, ICR1, and ICR2 interrupt cause registers are set as
conditions occur. The unit can indicate at most one outstanding error at any time.
Data Poisoning
GbE passes along error information to poison data.
See Section 37.6, “GbE Controller Register Summary” and Section 37.5.12, “Error
Handling” for additional details.
5.6.2
CAN Interface
The CAN units signal error conditions through two interrupt signals. The CAN unit
shares one interrupt between functional signaling duties (e.g., signaling that a message
was received) and error reporting, while the second interrupt reports only parity errors.
Status and enable registers in the CAN operate and control signaling functionality in the
CAN such as error reporting.
Table 5-28 summarizes the error conditions that the CAN captures.
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Table 5-28. Summary of CAN Error Conditions
Event
Type
Fatalitya
Reports via
CRC Check Error
Uncorrectable
Fatal
CAN System
Interrupt
Mismatch between received and
computed CRC.
Acknowledge Error
Uncorrectable
Fatal
CAN System
Interrupt
Improperly formatted ACK slot.
Form Error
Uncorrectable
Fatal
CAN System
Interrupt
Improperly formatted fixed-form field.
Bit Error
Uncorrectable
Fatal
CAN System
Interrupt
Mismatch between monitored and sent
bit value.
Stuff Error
Uncorrectable
Fatal
CAN System
Interrupt
Improperly formatted message from
Start of Frame to CRC delimiter.
CAN SRAM Parity
Error
Uncorrectable
Fatal
CAN Parity
Interrupt
Notes
Parity error in interface SRAM.
Clearing the parity error requires a
reset of the CAN interface. Please see
section on CAN interrupts in Section
39.2, “Feature List” on page 1569 for
more details.
a. “Fatal” events result in data loss or data corruption that the unit cannot repair, “Non-Fatal” events do not.
Table 5-29 summarizes the capabilities of the CAN error handling for each of the
features that the unit is expected to provide.
Table 5-29. Summary of CAN Error Reporting Capabilities
Feature
Implementation
Enabling and
Masking Error
Reporting
The CAN interrupt enable register supports error enabling and masking.
The SMIA and SMME registers from the signal target capability in the PCI configuration
header for the CAN units also supports error enabling and masking. Using these registers
to mask the CAN System Interrupt masks both error and functional events since the CAN
units use this interrupt to signal both error and functional conditions.
Logging Details
The SINT register from the signal target capability in the PCI configuration header for a
CAN unit provides read-only access to the state of the interrupt signals from a CAN unit.
CAN does not log additional details on errors.
Reporting Multiple
Errors
Individual status bits in CAN interrupt status register are set as conditions occur. The unit
can indicate at most one outstanding error of each type at any time.
Data Poisoning
CAN does not require support for data poisoning. Errors during transactions cause the
transaction to abort and an error event to be signaled.
See Section 39.6, “Register Summary” and Section 39.5.2, “Error Handling” for
additional details.
5.6.3
SSP Interface
The SSP unit signals error conditions through a single interrupt signal. The SSP block
shares this interrupt between functional duties (e.g., transmit FIFO service request)
and error reporting duties. Software is expected to use status registers in the SSP to
determine the cause of a signal.
Table 5-30 summarizes the error condition that the SSP captures.
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Table 5-30. Summary of SSP Error Conditions
Event
Type
Fatalitya
Reports via
Notes
Functional
Receiver Overrun
(ROR)
Uncorrectable
Fatal
SSP Interrupt
Receive FIFO is full, any incoming data
is discarded.
a. “Fatal” events result in data loss or data corruption that the unit cannot repair, “Non-Fatal” events do not.
Table 5-31 summarizes the capabilities of the SSP error handling for each of the
features that the unit is expected to provide.
Table 5-31. Summary of SSP Error Reporting Capabilities
Feature
Implementation
Enabling and
Masking Error
Reporting
SSP does not provide the ability to enable or mask the interrupt from an ROR error
condition.
The SMIA and SMME registers from the signal target capability in the PCI configuration
header for the SSP unit also support error enabling and masking. Using these registers to
mask the SSP Interrupt masks both error and functional events since the SSP unit uses
this interrupt to signal both error and functional conditions.
Logging Details
The SINT register from the signal target capability in the PCI configuration header for the
SSP unit provides read-only access to the state of the interrupt signals from SSP.
SSP does not log additional details on its errors.
Reporting Multiple
Errors
SSP can only generate a single error. The unit can indicate at most one outstanding error
at any time.
Data Poisoning
SSP error conditions result in loss of data and system interrupt. There is no need to poison
in these cases.
See Section 40.4, “Register Summary”and Section 40.3.2, “Error Handling” for
additional details.
5.6.4
Local Expansion Bus
The Local Expansion Bus unit signals error conditions from the interface into the
EP80579 through a single interrupt signal that is used exclusively for errors. In
addition, this unit signals errors from the internal bridge through a separate interrupt.
Table 5-32 summarizes the error conditions that the local expansion bus captures.
.
Table 5-32. Summary of Local Expansion Bus Error Conditions
Event
Type
Fatalitya
Reports via
Notes
Parity Error
Uncorrectable
Fatal
LEB Parity
Error Interrupt
Parity error on outbound read from the
EP80579.
a. “Fatal” events result in data loss or data corruption that the unit cannot repair, “Non-Fatal” events do not.
Table 5-33 summarizes the capabilities of the local expansion bus error handling for
each of the features that the unit is expected to provide.
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Table 5-33. Summary of Local Expansion Bus Error Reporting Capabilities
Feature
Enabling and
Masking Error
Reporting
Logging Details
Reporting Multiple
Errors
Data Poisoning
Implementation
LEB device provides the following registers to support error enabling and masking:
• Errors from LEB: EXP_TIMING_CS[0-7].
The SMIA and SMME registers from the signal target capability in the PCI configuration
header for the LEB also support error masking and enabling.
The SINT register from the signal target capability in the PCI configuration header for the
LEB provides read-only access to the state of the interrupt signals from the LEB.
LEB device captures additional error logging information in the following registers:
• LEB parity errors: EXP_PARITY_STATUS.
LEB device reports additional errors as follows:
• LEB errors
LEB pass along error information to poison data.
See Section 42.5, “Register Summary”.
5.6.5
IEEE 1588, and GCU
The IEEE 1588 and GCU in the AIOC do not signal any non-functional error conditions.
§§
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6.0
Reset and Power Management
This chapter describes the Intel® EP80579 Integrated Processor reset and power
management.
6.1
Reset and Powergood Distribution
This section discusses the detailed sequencing of how power and clocking signals must
be applied to bring the EP80579 out of reset.
6.1.1
Types of Reset
The EP80579 has four types of reset: Power-good (cold) reset, Hard reset, CPU-only
reset, and Targeted I/O subsystem reset(s). Each of these reset subclasses have
unique effects and is described in Table 6-1.
Table 6-1.
Types of Reset and Wake-up from Power Saving States
Effect of Reset on following blocks
Type
Mechanism
CPU
6.1.1.1
IMCH/
IICH
AIOC
PCI-E
DDR
Power-good
Input pin
Reset
Reset
Reset
Reset
Reset
Hard
Input pin
Reset
Reset
Reset
Reset
Reset
Software (SW)
Controlled
Write to I/O port CF9
Reset
Reset
Reset
Reset
Reset
CPU-only
Internal to the EP80579.
Generated by IMCH
Reset
-N/A
-N/A
-N/A
-N/A
S3 -> S0
Wake Event
Reset
Reset
Reset
Reset
-N/A
S4/S5->S0
Wake Event
Reset
Reset
Reset
Reset
Reset
Powergood Implementation
The initial boot from when the power supplies are energized is facilitated by the
Powergood mechanism. The voltage sources from all platform power supplies are
routed to a system component which tracks them as they ramp-up, asserting platform
powergood (CPU_VRD_PWR_GD and SYS_PWR_OK) after a fixed interval (nominally 99
ms) after the last voltage reference has stabilized. Powergood signals are propagated
asynchronously to dedicated IICH, IMCH, and IA-32 core inputs. Generally, the devices
on AIOC fabric including the AIOC reset block do not receive a powergood signal. The
exception is the GbE MAC devices (see Section 6.1.2.3.5, “GbE MAC”).
Table 6-2 summarizes the power wells and external voltages required by the EP80579.
More detailed power supply pin information can be found in Table 6-3.
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Table 6-2.
Power Wells and External Voltages
Power
Well
Core
Suspend
RTC
6.1.1.2
Nominal
Voltage
Components
1.0-1.3 V
IA Processor: IA-CPU
1.2 V
Core Logic (IMCH, IICH, ASU, SSU, TDM, GbE MAC1, GbE MAC2), SATA pads, PCI-E
pads, Local Expansion Bus
1.8 V
PCI-E PLL, DDR2 pads. Note: 0.9V are generated from 1.8V
2.5 V
RMII/RGMII
3.3 V
SATA, PCI-E
5.0V
5V tolerance reference
1.2 V
IICH, USB pads, DDR2 core logic, GbE MAC0, USB core logic and pads
2.5 V
RMII/RGMII
3.3 V
USB pads, RMII/RGMII pads
5.0V
5V sustain reference
3.3 V
RTC
Hard Reset Implementation
A hard reset is initiated by the IICH via the PLTRST# as a result various S-state wake
events or other reset signal assertions. PLTRST# is driven to the IMCH and is
propagated from there to the reset block for AIOC fabric. The reset block in the AIOC
fabric is responsible for resetting the individual blocks.
IMCH propagates a hard reset to the FSB and subordinate PCI Express* subsystems.
The FSB components are reset via the CPURST# (internal signal) signal, while the PCI
Express* subsystems through PCIRST#.
6.1.1.3
Software Controlled Reset
Software may cause a full system reset through a write to the Reset Control Register
located at I/O port CF9. See also Section 6.1.1.4, “CPU Only Reset Implementation” for
software controlled CPU only reset mechanisms.
6.1.1.4
CPU Only Reset Implementation
For power management, error conditions and other reasons, the EP80579 supports a
targeted CPU only reset semantic. This mechanism eliminates system reset at large
when the CPU function (such as clock gearing selection) must be updated during
initialization. It only affects the IA-32 core. Other blocks such as IICH, IMCH, AIOC
complex are not reset. It is controlled by IMCH.
The IA-32 core can also be reset via the assertion of its INIT# pin which may be
accomplished by several conditions including a software write to the Reset Control
Register in IICH. Asserting the INIT# pin on the IA-32 core invokes a response similar
to that of asserting CPURST#. The major difference is that during an INIT, the internal
caches, MSRs, MTRRs, and FPU state are left unchanged (although, the TLBs and BTB
are invalidated as with a hardware reset). When INIT is signaled while the processor is
in virtual-8086 mode, the processor leaves virtual-8086 mode and enters real-address
mode. An INIT provides a method for switching from protected to real-address mode
while maintaining the contents of the internal caches.
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6.1.1.5
S-state Wake Events
Wake events for the various ACPI sleep states cause a hard reset to the EP80579 (See
Section 27.6.3, “Exiting Sleep States” ). Wake on LAN, supported by the GbE MACs,
leverages mechanisms provided for GPI and PME wake events.
6.1.1.6
Targeted Reset Implementation
The targeted reset is provided for hot-plug events, as well as for port specific error
handling under MCA or SMI software control.
A targeted reset may be requested by setting bit six (Secondary Bus Reset) of the
Bridge Control register (D2, F0, offset 3Eh) in the target root port device. Setting this
bit crashes the Link Training and Status State machine (LTSSM) of the target port to
the reset state, where it issues at least 1024 TS1 ordered sets with the reset bit
asserted. This propagates an in-band “hot” reset to the downstream device, and
consequently force an equivalent reset to any devices further downstream. This reset is
identical to a general hard reset from the perspective of destination PCI Express*
device.
6.1.2
Platform Reset and Powergood
This section describes the reset and powergood external platform interfaces.
6.1.2.1
Platform Powergood
The EP80579 receives two powergood signals from the platform. The first is
CPU_VRD_PWR_GD and the other is SYS_PWR_OK. SYS_PWR_OK is asserted after a
fixed delay from the time that CPU_VRD_PWR_GD goes active and indicates that power
has been stable for at least 99 ms. The EP80579 inputs PWRGD, PWROK, and
SYS_PWR_OK are connected to the SYS_PWR_OK platform signal. CPU_VRD_PWR_GD
and SYS_PWR_OK distribution inside the EP80579 is discussed in Section 6.1.2.3,
“Reset and Powergood Distribution”. Refer to Figure 6-1 for the block diagram showing
CPU_VRD_PWR_GD and SYS_PWR_OK interfaces.
6.1.2.2
Platform Reset
The EP80579 receives two reset signals from the platform. The first one is SYS_RESET
which includes the reset button on the platform. The second is Resume Reset which is
used for resetting the IICH resume well after power is restored from a power failure.
Reset distribution inside the EP80579 is discussed in Section 6.1.2.3, “Reset and
Powergood Distribution”. Refer to the Figure 6-1, for a block diagram showing the reset
interface.
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Figure 6-1.
Powergood and Reset Interface
VSBY3_3
EP80579
DDR2 1.8V
ITP/XDP
1k
2.5V for GbE
inverter
1.2V Logic Core
EN
Ready
DB800
SILVERBOX_PWROK
NC8
CK410
PWRGD
PCI-E x8 conn
RSTIN_N
SYS_PWR_OK
PWROK
1.0V/1.3V
EN IA-32 core
Ready
PWRGD
2ms
Delay
100ms
Delay
PCI-E switch
0 ohm empty
CPU_VRD_PWR_GD
RSMRST#
GLUE 4
FP_RESET#
PLTRST_N
VRMPWRGD
RSMRST_N
FWH
LAI
SYS_REST_N
PCIRST_N
RESET_BTN
FP_PWRON#
SIO
PWRBTN_N
WDT_N
LPC
PWRON_BTN
RTCRST#
PCI-E x4
conn
RTEST_N
PME_N
P80
RTC
TPM
SYS_PWR_OK
Vccsus25
Vccpsus
Vccsus1
2.5V
3.3V
1.2V
GBE_aux_pwr_good
GBE_AUX_PWR_GOOD
GBE_PME_WAKE
Wake signal
GBE Powergood
6.1.2.3
Reset and Powergood Distribution
The EP80579 reset follows a general path through the IICH to the IMCH and out to the
rest of the chip.
6.1.2.3.1
IICH
IICH plays the central role in reset and powergood distribution to the whole chip. IICH
receives two powergood signals from the platform (CPU_VRD_PWR_GD and
SYS_PWR_OK). The assertion of these signals starts the reset sequence for the
EP80579.
IICH generates the central reset signal (known as PLTRST#) that initiates the reset of
the rest of the chip. PLTRST# is received by IMCH. IICH also generates PCIRST# signal
for resetting the PCI device. PCIRST# is similar to PLTRST# except that PCIRST# can
be asserted using a CSR.
IICH also generates the powergood (CPUPWRGD#) signal for IA-32 core.
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IICH Signals
Inputs
VRMPWRGD - Voltage Regulator PowerGood: This signal is directly connected
to the platform signal, CPU_VRD_PWR_GD and signifies that the voltage
regulator is stable.
PWROK - IICH Power Okay: This signal is directly connected to the platform
signal, SYS_PWR_OK. When asserted, PWROK is an indication to the IICH that
power has been stable for at least 99 ms and that PCICLK has been stable for
at least 1 mS. PWROK can be driven asynchronously. When PWROK is inactive,
the IICH asserts PLTRST#.
SYS_RESET# - System Reset: This signal initiates a system reset and causes
PLTRST# to go active. SYS_RESET# must be asserted for at least 100ms.
System reset cannot occur again until SYS_RESET# has been detected
inactive, and the system is back to a full S0 state with PLTRST# inactive. If bit
3 of the Reset Control Register is set then the assertion of SYS_RESET# will
result in a full power cycle reset.
RSMRST# - Resume Well Reset: This signal resets the IICH resume power
plane logic when power is reapplied after a power failure. If the AFTERG3_EN
bit in the General Power Management Configuration 3 Register (D31 F0 Offset
A4) is set to 0, IICH transitions the system from G3 (mechanical off) to S0
state and causes the assertion of the PLTRST# output. If AFTERG3_EN is 1, the
system will transition to S5 state.
RTEST# - RTC Well Test: This signal is tied to the platform RTCRST# signal.
Normally it is held high (to VccRTC), but can be driven low on the tester or
motherboard to test the RTC well. RTEST# resets some bits in the RTC well that
are otherwise not reset by PLTRST# or RSMRST#. An external RC circuit on the
RTCRST# signal creates a time delay such that RTCRST# will go high some
time after the battery voltage is valid. The RC time delay must be in the 10-20
ms range. This allows detection when a new battery has been installed. Unless
entering a XOR Chain test mode, the RTEST# input must always be high when
all other non-RTC power planes are on.
Outputs
CPUPWRGD - CPU PowerGood: This signal is the logical AND of the IICH
VRMPWRGD and PWROK input signals. This signal is connected to the
processor's powergood input to indicate when the processor power is valid.
PLTRST# - Platform Reset: This signal is asserted by SYS_RESET#,
RSMRESET#, or software. The IICH asserts PLTRST# to reset devices on the
platform (e.g., SIO, FWH, LAN, IMCH, IDE, TPM, etc.) during power-up
(CPU_PWRGD de-asserted) and when software initiates a hard reset sequence
through the Reset Control register. The IICH drives PLTRST# active a minimum
of 1 ms when initiated through the Reset Control register. The IICH de-asserts
PLTRST# a minimum of 1 ms after CPU_PWRGD is driven high.
PCIRST# - PCI Reset: This is the secondary PCI bus reset signal. This signal is
asserted a small number of PCI clocks after PLTRST# or can be asserted
independently by the Secondary Bus Reset bit.
6.1.2.3.2
IMCH
IMCH plays a crucial role in the reset sequence for IA-32 core. IMCH receives the
powergood signal (SYS_PWR_OK) from the platform. The IICH PLTRST# drives the
IMCH RSTIN# input. IMCH drives the CPURST# (internal signal) while it is in the reset.
IMCH works with IICH to initialize the NSI link between IICH and IMCH. Once the
central reset (PLTRST#) is de-asserted, IMCH de-asserts the CPURST# (internal
signal).
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IMCH can also configure some aspects of the IA-32 core at Power On. IMCH drives
these configuration settings before CPURST# (internal signal) assertion based on the
contents of its Power-On Configuration Register (D8, F0, offset C0h).
IMCH Signals
Inputs
PWRGD - IMCH PowerGood: This signal is directly connected to the platform
signal, SYS_PWR_OK. When asserted, PWRGD is an indication to the IMCH that
power has been stable for at least 99 ms. When PWRGD is inactive, the IMCH
asserts its CPURST# (internal signal) outputs.
RSTIN# - IMCH Reset: This signal is directly connected to the IICH PLTRST#
output. When RSTIN is active, the IMCH asserts its CPURST# (internal signal)
output.
6.1.2.3.3
IA-32 core
Early in the cold reset (powergood) sequence, the IA-32 core voltage regulator drives a
default voltage to the IA-32 core to read the fuses containing the IA-32 core FSB
frequency requirements. The EP80579 then drives its BSEL pin to the appropriate value
which is latched by the platform when it is known to be stable. The platform uses the
BSEL information to update the IA-32 core voltage regulator to the appropriate
operating voltage prior to the assertion of CPU_VRD_PWR_GD. The platform also uses
the value of BSEL to drive the clock generator to the correct reference clock (BCLK)
frequency.
Reset and configuration for IA-32 core is done by IICH and IMCH. Reset for IA-32 core
starts when IMCH asserts CPURST# (internal signal) and IICH asserts CPUPWRGD. The
assertion of both of these signals initiates the PLL locking process for the IA-32 core. All
the flops and internal states are reset during the reset process. The processor’s PLL
locks before CPURST# (internal signal) is de-asserted. CPURST# (internal signal)
needs to be asserted for at least 1ms and not more than 10ms (processor spec).The
IA-32 core receives power-on configuration values on its address pins during CPURST#
(internal signal).
6.1.2.3.4
IMCH
The IMCH receives the central reset (PLTRST#) from IICH. Clocks to DIMMs are
disconnected till BIOS configures the DIMMs. Memory controller core logic boots at the
default frequency as driven by the BSEL pin. Based on the DDR type and frequency
memory controller needs to re-lock itself at the DDR frequency once BIOS has read the
DDR.
6.1.2.3.5
GbE MAC
There are three GbE MAC devices. Each GbE receives the internal system reset. Each
GbE also receives a power OK signal from the platform that is also used as a reset.
GbE0 receives this signal via the GBE_AUX_PWR_GOOD external pin. GbE1 and GbE2
receive this signal via the SYS_PWR_OK external pin. The SYS_PWR_OK pin is
connected to the SYS_PWR_OK platform signal which is also connected to the PWROK
and PWRGD pins. The GBE_AUX_PWR_GOOD pin should be connected to SYS_PWR_OK
when no auxiliary power supply is used. If an auxiliary supply is used for GbE0, then
GBE_AUX_PWR_GOOD should be connected to the power good signal from that power
supply (this signal is subject to the timing requirements documented in Figure 6-4,
“Power Rail Sequence Timings (Sustain Well Power Management)” on page 170).
Under all circumstances, GbE0 MUST be powered by either the system supply or the
auxiliary supply. Likewise, GBE_AUX_PWR_GOOD MUST be connected to the
corresponding power good signal. GbE0 must be powered to enable operation of either
GbE1 or GbE2.
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6.1.3
EP80579 Power Sequencing and Reset Sequence
The following diagrams show the reset sequencing.
Figure 6-2.
Reset Sequence
3
Reference Clock
Stable (from
clock generator)
EP80579
9
7
5
4
CRU
Clock
Stable
PLTRST#
de-asserted
CPU_PWRGD
asserted
IICH
6
CPU
FSB and
Core
Clocks
Stable
1
VRMPWRGD
PWROK
PWRGD
CPU_VRD_PWR_GD
(from platform)
SYS_PWR_OK
(from platform)
2
10
Reset
Microcode
Execution
IICH
Power Applied
to EP80579
CPURST#
de-asserted
IMCH
IMCH
Re-steer
to BIOS
DDR
Initialization
CPU
8
udrst
de-asserted
Memory Controller
Initialization
All the blocks
except the IA
CPU come out
of reset
5
1. The EP80579 receives power and drives its BSEL and V_SEL pins.
CPU_VRD_PWR_GD, SYS_PWR_OK (platform signals) are not asserted. PLTRST#,
and CPURST# (internal signal) are asserted.
2. CPU_VRD_PWR_GD is asserted (Platform signal). Internal signal name is
VRMPWRGD.
3. External Reference Clock provided from platform is stable, and is supplied to the
EP80579 internal PLLs to generate required internal clocks. Voltage regulator
output is modified to correspond to BSEL and V_SEL values.
4. The EP80579 CRU PLL locks.
5. SYS_PWR_OK (platform signal) == PWROK/PWRGD internal signal asserted
6. IO and Core PLLs lock on the CPU.
7. IICH de-asserts PLTRST#
8. IMCH de-asserts udrstb (internal reset unit). All EP80579 blocks except the IA-32
core come out of reset.
9. IMCH de-asserts CPURST# (internal signal) CPU executes the reset micro-code
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Table 6-3.
EP80579 Power Supply Pins
Nominal
Voltage
Voltage
Tolerance
Package Pin
Supply Types
Description
+/-5%
VTTDDR
DDR
DDR termination voltage
+/-2%
VCCVC
IA-32 core
IA-32 core power
VCCA[1]
IA-32 core
IA-32 core PLL1 power
VCCA[2]
IA-32 core
IA-32 core PLL2 power
VCC
CRU, CRU_PAD, DDR,
Expansion, Bus, GBE,
IMCH_PAD, MISC IO,
PCI, Express, SATA
Core power
VCCUSB12
USB2
Digital power
VCCAUSB12
USB2
Analog power
VCCAHPLL
CRU
Analog PLL power
VCCAPE0PLL12
PCI-Express
PLL digital power
WELL = CORE
0.9 V (DDR2)
1.0V@600MHz
1.3V@1066/
1200MHz
1.2 V
1.8 V (DDR2)
2.5 V
3.3 V
5V
+/-5%
+/-5%
+/-5%
+/-5%
+/-5%
VCCAPLL
SATA
Analog PLL power
VCCAPE
PCI-Express
Receiver analog power
VCCAPE
PCI-Express
Receiver analog power
VCCAPE
PCI-Express
Transmitter analog
power
VCCARX
SATA
Analog receiver power
VCCATX
SATA
Analog transmitter
power
VCCRPE
PCI-Express
Receiver digital power
VCCSATA
SATA
SATA power
VCC18
DDR
DDR IO power
VCC18
TRNG
TRNG power
VCCTMP18
Thermal Sensor
Thermal sensor power
VCCAPE0PLL18
PCI-Express
PLL VRM power
VCC25
GBE
GBE IO
VCC33
CRU_PAD, Expansion
Bus, IMCH_PAD, MISC
IO
IO power
VCCGBE33
GBE
3.3V tolerance reference
VCCSATA33
SATA
SATA power
VCCABG3P3_USB
USB2
Analog bandgap power
VCCABGP033
PCI-Express
Bandgap analog power
VCCASATABG3P3
SATA
Analog bandgap power
VCC50
Expansion Bus, MISC
IO, CRU_PAD,
IMCH_PAD
5V tolerance reference
WELL = SUSPEND
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Table 6-3.
Nominal
Voltage
EP80579 Power Supply Pins
Voltage
Tolerance
Package Pin
Supply Types
Description
VCC1P2_USBSUS
USB2
1.2V USB sustain power
1.2 V
+/-5%
VCCSUS1
IMCH_PAD
RTC core sustain power
VCCSUS1
GBE
Core GBE sustain power
2.5 V
+/-5%
VCCSUS25
GBE
Sustain GBE power
VCCPSUS
USB2, IMCH_PAD
USB and RTC IO sustain
power
VCCGBEPSUS
GBE
Sustain 3.3V tolerance
reference
+/-5%
VCC50_SUS
IMCH_PAD, USB2
5V sustain reference
+/-5%
VCCPRTC
IMCH_PAD
Real Time Clock power
3.3 V
5V
+/-5%
WELL = RTC
3.3
Figure 6-3 illustrates the sequence that power rails should follow as they are brought
up at Power On.
Figure 6-3.
EP80579 Rail Power On Sequence
VCCPRTC
1
S u s p e n d 5 .0 V
S u s p e n d 3 .3 V
S u s p e n d 2 .5 V
S u s p e n d 1 .2 V
PS_O N #2
C o r e 3 .3 V
C o r e 5 .0 V
C o r e 2 .5 V
C o r e 1 .8 V
VTTDDR
C o r e 1 .2 V
IA -3 2 c o r e 1 .0 V - 1 .3 V
Figures 6-4, 6-5, 6-6, and 6-7 accompanied by Table 6-4, Table 6-5, and Table 6-6
show the relationship between the power supply rails and key reset signals upon
EP80579 power-up. In Figures 6-4 and 6-5, the terms “Core” and “Suspend” refer to
the power wells that Table 6-2 on page 162 describes.
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Figure 6-4.
Power Rail Sequence Timings (Sustain Well Power Management)
SYS_PWR_OK
t213
VRMPWRGD/ CPU_VRD_PWR_GD
t212
IA- 32 core
1.0-1. 3 V
Core1. 2 V
t211
Core1. 8 V,
VTTDDR
Core2. 5 V
t 210
Core3. 3 V
t209
Core 5 V
GBE_AUX_PWR_ GOOD
t206
RSMRST#
t204
t205
Suspend1. 2 V
t203
Suspend2. 5 V
t202
Suspend3. 3 V
t201
Suspend5 V
RTCRST#
VCCPRTC
t200
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Figure 6-5.
Power Rail Sequence Timing (No Sustain Well Power Management)
SYS_PWROK GBE_AUX_PWR_GOOD
VRMPWRGD/ CPU_VRD_PWR_GD
Table 6-4.
Power Rail Sequence Signal Timings
Sym
t200
Parameter
VCCPRTC active to RTCRST# inactive
Min
Max
Units
18
–
ms
Notes
t201
Suspend 5 V active to Suspend 3.3 V active
0
–
ms
1
t202
Suspend 3.3 V active to Suspend 2.5 V active
0
–
ms
2
3
t203
Suspend 2.5 V active to Suspend 1.2 V active
0
–
ms
t204
Suspend supplies active to RSMRST# inactive
10
–
ms
t205
VCCPRTC supply active to Suspend supplies active
0
–
ms
4
t209
Core 5 V active to Core 3.3 V active
0
–
ms
1
NOTES:
1. The 5 V supply must power up before its associated 3.3 V supply within 0.3 V, and must power down after the 3.3 V supply
within 0.3V.
2. Ensure the following: a) Suspend 3.3 V must power up before Suspend 2.5 V or after Suspend 2.5 within 0.3 V, b) Suspend
2.5 V must power down before Suspend 3.3 V or after Suspend 3.3 V within 0.3 V.
3. Ensure the following: a) Suspend 2.5 V must power up before Suspend 1.2 V or after Suspend 1.2 V within 0.3 V, b) Suspend
1.2 V must power down before Suspend 2.5 V or after Suspend 2.5 V within 0.3 V.
4. The VccSus supplies must never be active while the VCCPRTC supply is inactive.
5. Ensure the following a) Core 3.3 V must power up before Core 2.5 V or after Core 2.5 V within 0.3 V, b) Core 2.5 V must
power down before Core 3.3 V or after Core 3.3 V within 0.3 V.
6. Ensure the following: a) Core 2.5 V must power up before Vcc1.2 V or after Core 1.2 V within 0.3 V, b) Core 1.2 V must power
down before Core 2.5 V or after Core 2.5 V within 0.3 V.
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Table 6-4.
Power Rail Sequence Signal Timings
Sym
Parameter
Min
Max
–
t210
Core 3.3 V active to Core 2.5 V active
0
t211
Core 2.5 V active to Core 1.2 V active
0
t212
Suspend supplies active to Core supplies active
t213
All core supplies active to SYS_PWR_OK (platform signal) active
Units
Notes
ms
5
ms
6
4
0
–
ms
99
–
ms
NOTES:
1. The 5 V supply must power up before its associated 3.3 V supply within 0.3 V, and must power down after the 3.3 V supply
within 0.3V.
2. Ensure the following: a) Suspend 3.3 V must power up before Suspend 2.5 V or after Suspend 2.5 within 0.3 V, b) Suspend
2.5 V must power down before Suspend 3.3 V or after Suspend 3.3 V within 0.3 V.
3. Ensure the following: a) Suspend 2.5 V must power up before Suspend 1.2 V or after Suspend 1.2 V within 0.3 V, b) Suspend
1.2 V must power down before Suspend 2.5 V or after Suspend 2.5 V within 0.3 V.
4. The VccSus supplies must never be active while the VCCPRTC supply is inactive.
5. Ensure the following a) Core 3.3 V must power up before Core 2.5 V or after Core 2.5 V within 0.3 V, b) Core 2.5 V must
power down before Core 3.3 V or after Core 3.3 V within 0.3 V.
6. Ensure the following: a) Core 2.5 V must power up before Vcc1.2 V or after Core 1.2 V within 0.3 V, b) Core 1.2 V must power
down before Core 2.5 V or after Core 2.5 V within 0.3 V.
Figure 6-6.
Powergood Reset Sequence
Power Rails
BSEL
CPU+VRD_PWR_GD/
VRMPWRGD
Reference Clock
SYS_PWR_OK/
PWROK/PWRGD
CPU_PWRGD
PLTRST#/RSTIN#
PCIRST#
CPU Power-On
Configuration
CPURST#
a
b
c
d
f
i
j
B6548-01
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Table 6-5.
Powergood Reset Timings
Timing
Description
Value
Tab
VRMPWRGD/ CPU_VRD_PWR_GD assertion to Reference Clock Stable
2 ms
Tac
VRMPWRGD/ CPU_VRD_PWR_GD assertion to SYS_PWR_OK (platform signal)
assertion
99 ms
Tcd
SYS_PWR_OK (platform signal) assertion to CPU_PWRGD assertion
(CPU_PWRGD is logical AND of VRMPWRGD/ CPU_VRD_PWR_GD and
SYS_PWR_OK)
logic delay
Tdf
CPU_PWRGD assertion to PLTRST# de-assertion
1 ms
(internal signal) de-assertion
Tfi
RSTIN# deassertion to CPURST#
Tij
CPURST# (internal signal) de-assertion to POC invalid
Figure 6-7.
1 ms + CPU_RST_DONE
transaction delay (max 10,000 PCIe clocks) + CPU_RST_DONE
capture timer (min 2000 reference
clocks)
2 reference clocks
Hard Reset Sequence
Reference Clock
SYS_PWR_OK/PWROK/
PWRGD/CPU_PWRGD
SYS_RESET#
PLTRST#/RSTIN#
CPU Power-On
Configuration
CPURST#
a
d
g
h
B6549-01
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Table 6-6.
Hard Reset Timings
Timing
Tad
Description
Value
Minimum SYS_RESET assertion duration
100 ms
Tdg
RSTIN# deassertion to CPURST#
1 ms + CPU_RST_DONE
transaction delay (max
10,000 PCI-e clocks) +
CPU_RST_DONE capture
timer (min 2000 reference
clocks)
Tgh
CPURST#
(internal signal) de-assertion
(internal signal) de-assertion to POC invalid
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6.2
BIOS Boot Flow (Initialization)
After hardware reset of the EP80579 and once IA -32 core has executed the reset
micro-code, the IA 32 core resteers to reset vector (0xFFFF_FFF0) and starts fetching
from BIOS code boot rom. BIOS starts execution from the reset vector regardless of
whether wake is from S3, S4, or S5. To determine that it is S3 resume, BIOS checks
the SUS_TYP field in the power management controller. If it is not S3, then normal boot
occurs. If it is S3, then BIOS also checks the power failure bits (PWRBTNOR_STS,
PWR_FLR, PWROK_FLR). If these are set to one, then memory contents cannot be
relied on and normal boot is followed. If it is an S3 resume and the power failure bits
are not set, then the S3 boot path is followed. The normal boot path is that used for
cold reset and for S4/S5 resume. From a BIOS perspective there is no difference
between S4 and S5. The following steps describe the boot sequence after reset before
handover to OS.
Figure 6-8.
BIOS Boot Flow (Cold Boot, S3/S4->S0)
Hard Reset
CPU POC
1) Select
BSP
2) Read/Retrieve
Memory CFG
3) Initialize
Memory
4) Shadow BIOS
5) Configure PCIExpress Ports.
This step is automatic and precedes any software influence on chipset configuration .
Power-On-Configuration is propagated across the FSB,. BREQ0# is asserted to select a
boot-strap CPU, and MCH strapping options are sampled.
* On cold reset, BIOS reads the SPD registers in DIMM via SMBus. BIOS finds the DDR
type, DDR frequency and configures the gearing ratio. BIOS uses the information to
programDRA, DRB, DRC and DRT registers in IMCH. BIOS enables the DDR clock.
* On S3->S0, BIOS retrieves the memory table intact from non-volatile memory, and
uses that information directly to program DRA, DRB, DRC, and DRT registers.
* On cold reset, BIOS calibrates and configures IMCH and DDR. BIOS may also run
diagnostic tests on populated memory at this point to verify no ill-effects from reset.
Initialize all populated memory to all "0"s with good ECC codes. If desired, BIOS may also
run diagnostic tests on populated memory at this point to verify no ill-effects from reset.
* On S3->S0, BIOS retrieves the prior configuration.
BIOS copies required BIOS code up from the FWH via ICH to the desired location in
main memory. Program the PAM registers to reflect the correct shadowing settings.
* For cold reset, BIOS reads the PCI-Express port configuration register and configure
ports which are successfully trained.
* For S3/S4->S0, BIOS retrieves the expected PCI-Express port configuration from
NVRAM/Disk. BIOS must then read the PCI-Express port status registers, configure the
ports which successfully trained, and update the MCH configuration map (device present
bits) to reflect MCH environment.
BIOS execute a standard PCI scan in incrementing BUS and DEVICE number order,
program primary/secondary/subordinate bus# registers, and aggregate the total memory
required for each logical PCI-Express port. At the end of this step, the PCI IO, M, PM,
TOLM, and HPCIM registers should be properaly configured to reflect allocated I/O and
MMIO space.
6) Enumerate PCI
At this point BIOS has access to all the error reporting information in the system.
8) Interrogate and
Clear Error Regs
9) APIC
Configuration
BIOS programs the APIC configuration registers in the MCH to allocate message space in
the processor/chipset reserved space. Identical configuration must be propagated to all
capable expander devices found during enumeration .
BIOS programs the desired SMM size, location, and configuration. At the end of this step,
set the MCH control register bit to lock-down the memory map. This prevents viruses
from reprogramming the memory configuration to compromise SMM space.
10) Enable SMM
Pass to OS (cold reset) or
context recovery (S3/S4>S0)
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6.2.1
Memory Configuration
As described in the flow chart, one of the first actions of the BIOS is to configure main
memory. This section describes the memory configuration sequence of BIOS.
At reset the memory controller disables the output clock reference drivers for all DIMM
slots, which prevents them from locking at the wrong frequency, and then relocking
after this step in the initialization process.
Memory controller core logic boots at a factory set default frequency as is indicated by
the BSEL Pin. The BIOS must first set the DDR frequency and ratio via the DRC register
because the memory controller needs to re-lock itself at the desired DDR frequency.
BIOS configures the DDR frequency by reading the FSB frequency value from a
processor internal MSR and DDR2 circuitry and sets the DDR Speed bits [3:0] of the
DRC register (d0, f0, offset 7Ch).
Once the correct frequencies have been selected BIOS updates CKDIS (d0, f0, offset
8Ch), such that only populated ranks of populated DIMM slots receive output clocks
from the memory controller.
Using the DDR SPD data, BIOS programs the IMCH DRA and DRB registers for proper
translation of physical addresses to DDR row, bank, and column addresses.
BIOS further configures the DDR configuration, timing, and impedance compensation
settings to enable reliable communication between the IMCH and the DDR DIMM
devices. The DRT registers (d0, f0, offsets 78h and 64h) defaults settings can be found
in Section 11.0, “System Memory Controller”.
BIOS further performs DDR calibration, memory initialization, and optional MemBIST.
At this stage BIOS is aware of the total amount of memory populated in the system,
and may generate the starting value for the top of memory (TOM) register setting.
BIOS will generally want to complete at least a rudimentary memory test sequence
(next step) prior to finalizing the memory size information reported to the operating
system.
For memory initialization details refer to Section 11.0, “System Memory Controller”.
Wake from S3/S4/S5 are also described in the Figure 6-8
6.2.2
Memory Initialization
At this point in the boot sequence memory contains random data from power-on, and
would therefore generate non-deterministic ECC errors on read accesses. To zero-out
memory and initialize all locations with good ECC, the memory controller provides a
hardware engine which will walk all populated DRAM space issuing cache-line sized
writes with all zeroes as data.
6.2.3
Boot from Network
Booting from network on Intel platforms is supported by PXE. PXE (Preboot eXecution
Environment) is an existing open industry specification for network clients to
automatically download software images and configuration parameters. The PXE client
software is typically implemented as a BIOS Option ROM that is executed during the
preboot phase of the client system. This Option ROM (OpROM) implements a sufficient
network stack to perform all of the necessary network operations to boot an operating
system. This OpROM image is written assuming IA-32 architecture and instruction set.
Also, each OpROM image is modified specifically for a given Network Interface
Controller (NIC).
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The BIOS must first establish an environment suitable for execution of the PXE OpROM.
This environment must provide the following:
• System memory sufficient for C-code execution. This memory will be used to load/
execute OpROM code, implement a call stack and data storage. In addition system
memory must be available for loading/execution of OS.
• BIOS runtime services sufficient for OpROM execution. These services are typically
provided by system BIOS and allow the PXE OpROM to be implemented for
platform independence.
• The PCI sub-system is enumerated with allocation of system memory space, IO
space and interrupts completed. This will establish the address location of
resources accessed by the OpROM code during execution.
After OpROM initialization, the code remains in memory and waits until the BIOS
reaches the point at which the OS-boot process begins. When a GbE is selected for
boot, code in the OpROM will be used to initiate communication with a server to supply
the images required for boot. After these images are loaded execution control passes
from the BIOS to the images loaded in memory. This transition concludes the Preboot
phase and enters in to the OS-boot phase.
6.3
Power Management
6.3.1
Power Management States
Figure 6-9.
Global System Power States and Transitions
From a user-visible level, the system can be thought of as being in one of the states
shown in Figure 6-9. In general use, computers alternate between the Working and
Sleeping states. In the Working state, the computer is used to do work. User-mode
application threads are dispatched and running. Individual devices can be in low-power
(Dx) states and processors can be in low-power (Cx) states if they are not being used.
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Any device the system turns off because it is not actively in use can be turned on with
short latency. (What “short” means depends on the device. An LCD display needs to
come on in sub-second times, while it is generally acceptable to wait a few seconds for
a printer to wake.)
Precise definitions for Gx, Dx, Sx and Cx states are given in Table 6-7, Table 6-8,
Table 6-9, and Table 6-10.
Table 6-7.
Table 6-8.
Global Power States
Global
Power State
Description
G3
Mechanical
Off
A computer state that is entered and left by a mechanical means (for example, turning off the
system's power through the movement of a large red switch). Various government agencies
and countries require this operating mode. It is implied by the entry of this off state through a
mechanical means that no electrical current is running through the circuitry and that it can be
worked on without damaging the hardware or endangering service personnel. The OS must be
restarted to return to the Working state. No hardware context is retained. Except for the realtime clock, power consumption is zero.
G2/S5 Soft
Off
A computer state where the computer consumes a minimal amount of power. No user mode or
system mode code is run. This state requires a large latency in order to return to the Working
state. The system's context will not be preserved by the hardware. The system must be
restarted to return to the Working state. It is not safe to disassemble the machine in this
state.
G1 Sleeping
A computer state where the computer consumes a small amount of power, user mode threads
are not being executed, and the system “appears” to be off (from an end user's perspective,
the display is off, and so on). Latency for returning to the Working state varies on the wake
environment selected prior to entry of this state (for example, whether the system should
answer phone calls). Work can be resumed without rebooting the OS because large elements
of system context are saved by the hardware and the rest by system software. It is not safe to
disassemble the machine in this state.
G0 Working
A computer state where the system dispatches user mode (application) threads and they
execute. In this state, peripheral devices (peripherals) are having their power state changed
dynamically. The user can select, through some UI, various performance/power characteristics
of the system to have the software optimize for performance or battery life. The system
responds to external events in real time. It is not safe to disassemble the machine in this
state.
Device States
Device
State
Description
D3 Off
Power has been fully removed from the device. The device context is lost when this state is
entered, so the OS software will reinitialize the device when powering it back on. Since device
context and power are lost, devices in this state do not decode their address lines. Devices in
this state have the longest restore times. All classes of devices define this state.
D2
The meaning of the D2 Device State is defined by each device class. Many device classes may
not define D2. In general, D2 is expected to save more power and preserve less device context
than D1 or D0. Buses in D2 may cause the device to lose some context (for example, by
reducing power on the bus, thus forcing the device to turn off some of its functions).
D1
The meaning of the D1 Device State is defined by each device class. Many device classes may
not define D1. In general, D1 is expected to save less power and preserve more device context
than D2.
D0 Fully-On
This state is assumed to be the highest level of power consumption. The device is completely
active and responsive, and is expected to remember all relevant context continuously.
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Table 6-9.
Sleeping States
Sleeping
State
Description
S0
Fully Active
S1
The S1 sleeping state is a low wake latency sleeping state. In this state, no system context is
lost (CPU or chip set) and hardware maintains all system context.
S2
The S2 sleeping state is a low wake latency sleeping state. This state is similar to the S1
sleeping state except that the CPU and system cache context is lost (the OS is responsible for
maintaining the caches and CPU context). Control starts from the processor's reset vector
after the wake event.
S3
The S3 sleeping state is a low wake latency sleeping state where all system context is lost
except system memory. CPU, cache, and chip set context are lost in this state. Hardware
maintains memory context and restores some CPU and L2 configuration context. Control starts
from the processor's reset vector after the wake event.
S4
The S4 sleeping state is the lowest power, longest wake latency sleeping state supported by
ACPI. In order to reduce power to a minimum, it is assumed that the hardware platform has
powered off all devices. Platform context is maintained.
S5 Soft Off
The S5 state is similar to the S4 state except that the OS does not save any context. The
system is in the “soft” off state and requires a complete boot when it wakes. Software uses a
different state value to distinguish between the S5 state and the S4 state to allow for initial
boot operations within the BIOS to distinguish whether or not the boot is going to wake from a
saved memory image.
Table 6-10. CPU States
6.3.2
Processor
Power State
Description
C0 - Full On
Processor core is active. All clocks are running. Processor can maintain cache coherency via
snoops. Processor responds to interrupt.
C1 - Auto Halt
Processor Core is not active after executing an Auto-Halt instruction. Processor Core clock
is internally gated. Processor can maintain cache coherency via snoops. Processor
responds to interrupts. Aside from putting the processor in a non-executing power state,
this state has no other software-visible effects.
C2 - Stop Grant
Processor Core is not active after its STPCLK# input is asserted. Processor Core clock is
internally gated. Processor can maintain cache coherency via snoops. Processor responds
to interrupts. Aside from putting the processor in a non-executing power state, this state
has no other software-visible effects.
C3 - Deep Sleep
Processor Core is not active after its SLP# input is asserted. Processor Core clock is gated
and PLLs are disabled. Processor does not respond to snoops or interrupts. While in the C3
state, the processor's caches maintain state but ignore any snoops. The operating software
is responsible for ensuring that the caches maintain coherency. The EP80579 does not
support C3 while functioning in S0 state, however, while in S1 state, The EP80579 will put
the processor in Deep Sleep state through the assertion on the SLP# signal.
Power Management Support
As a system on a chip with embedded I/O devices and many SKUs, the EP80579 power
management needs to perform multiple functions (typically under ACPI and/or BIOS
system software control):
• Minimize power consumption of software-disabled interfaces/units.
• Transition between defined ACPI states as defined in Table 6-11.
• Support system wake-up from GPIO, PCI Express* devices and GbE MAC ports
(Wake-on-LAN).
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• Support cold and warm reset for the whole chip.
Table 6-11. ACPI States
ACPI State
IICH
IMCH
IA-32 core
AIOC
S0
Full On
Full On
C0, C1, C2
Full On
S1
Full On
Full On
Deep Sleep
Full On
S2
Not Supported
Not Supported
Not Supported
Not Supported
S3-hot
Not Supported
Not Supported
Not Supported
Not Supported
S3-cold
(Suspend To RAM)
Sections stay on,
Standby wells
DDR IO Power on
but interface not
active
Power Down
D3 (Stop Clock and
Power Down,
Except GbE MAC
Wake-on LAN)
S4
(Suspend To Disk)
Sections stay on,
Standby wells
Sections stay on,
Standby wells
Power Down
Power Down
S5 Soft Off
Sections stay on,
Standby wells
Sections stay on,
Standby wells
Power Down
Power Down
Table 6-12. Power Wells Status for Supported ACPI States* (Sheet 1 of 2)
Power
Well
Supply Pin(s)
S0
S1
S3-cold
S4
S5
VTTDDR
On
On
Ona
Off
Off
On
On
Off
Off
Off
On
On
Off
Off
Off
VCC18
VCCTMP18
VCCAPE0PLL18
On
On
Onb
Off
Off
VCC25
On
On
Off
Off
Off
VCC33
VCCGBE33
VCCSATA33
VCCABG3P3_USB
VCCABGP033
VCCASATABG3P3
On
On
Off
Off
Off
VCC50
On
On
Off
Off
Off
VCCVC
VCCA[1]
VCCA[2]
Core
VCC
VCCUSB12
VCCAUSB12
VCCAHPLL
VCCAPE0PLL12
VCCAPLL
VCCAPE
VCCARX
VCCATX
VCCRPE
VCCSATA
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Table 6-12. Power Wells Status for Supported ACPI States* (Sheet 2 of 2)
Power
Well
Suspend
RTC
Supply Pin(s)
S0
S1
S3-cold
S4
S5
VCC1P2_USBSUS
VCCSUS1
On
On
On
On
On
VCCSUS25
On
On
On
On
On
VCCPSUS
VCCGBEPSUS
On
On
On
On
On
VCC50_SUS
On
On
On
On
On
VCCPRTC
On
On
On
On
On
a.
VTTDR, can optionally be powered off during S3, but typically is derived from and tracks DDR IO voltage,
VCC18, to avoid the complexity involved in timing the VTTDDR power up with the exit of S3.
b. VCCTMP18 and VCCAPE0PLL18 can optionally be powered off in S3 state. They are feed areas that consume
very little power and are grouped with VCC18, which must be on in S3, to avoid requiring an additional power
supply to support them.
6.3.2.1
Transitioning Between Power States
The EP80579 uses a cooperative power-down that is driven by software. To transition
from S0 into the S3 or S4 state under ACPI/BIOS/OS/device driver control, system
software is required to:
1. Suspend acceleration and security service application-level threads.
2. Place ASU and SSU devices into quiescent idle state, by completing all outstanding
work requests, saving internal state to memory, then disabling ASU/SSU interrupts.
3. Quiesce I/O interfaces by disabling Rx of new traffic, finalizing outstanding Tx
operations, disabling interrupts, and saving snap-shot of internal state to memory.
4. Save internal IMCH and IICH state to memory.
5. If transitioning to S4, move DRAM image to disk.
6. Drain all outstanding IMCH updates to DRAM.
7. Signal IICH to power-down the IA-32 core, the AIOC, the IMCH and the IICH. In
case of S3, the memory interface is placed into self-refresh mode. In S3/S4 state,
the GbE MAC, GPIO and LPC interfaces remain powered to process wake events.
An external wake event from GPIO, GbE MAC (received Wake-on-LAN packet) or PCI
Express* signals the IICH to initiate a complete reset sequence that transitions the
EP80579 back into the S0 state as follows:
1. All internal states outside of the IICH Resume Well are fully reset.
2. On resume from S3, BIOS does not reinitialize memory. Please refer to Section 6.2,
“BIOS Boot Flow (Initialization)” for details.
3. On resume from S3 or S4, all EP80579 device drivers (including ASU and SSU
drivers) are expected to restore internal device state from their memory resident
save area.
4. On resume from S3 or S4, resume acceleration and security service applicationlevel threads.
Note:
There is no support for wake from USB when in S3/S4/S5.
6.3.2.2
Power State Transition Timing Diagrams
For power state transition timing details, refer to Section 49.5.1.2, “Power Management
AC Characteristics”.
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6.3.3
Thermal Sensor
The EP80579 has an on-die thermal sensor. It helps to control the silicon temperature
by monitoring the silicon thermal status and activating the thermal control sequence
when the silicon reaches its maximum operating temperature. See Chapter 50.0,
“Thermal Specifications and Design Considerations” for details.
6.3.4
ACPI Implementation
The PCI device tree for the EP80579 is shown in Figure 3-4, “Overview of PCI
infrastructure for On-die Devices” on page 121. The EP80579 follows the ACPI
specification (http://www.acpi.info/DOWNLOADS/ACPIspec30a.pdf) which implies that
all the PCI devices implement the standard PCI/ACPI registers:
1. PCI Power Management Block
2. Capability ID
3. Next Item Pointer
4. Power Management Capabilities (PMC)
5. Power Management Control and Status Register (PMCSR)
§§
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7.0
Register Summary
7.1
Overview of Register Descriptions and Summaries
This chapter presents summary tables for the registers and MMIO spaces that the
components of the EP80579 define. In addition, this chapter describes how to read the
standard register description that is used throughout this document to describe the
functionality of individual registers.
The register summaries in this document follow a general formatting structure that
includes, for each register, its name, default value, offsets, and a cross-reference to its
detailed register description. Locations that are not associated with a register in the
summary table should be assumed to be reserved.
The summaries in this chapter are organized by functional unit and describe the
EP80579 registers that are visible from the IA platform perspective (e.g., PCI registers,
PCI memory-mapped I/O registers, fixed IA I/O space registers, etc.).
7.1.1
Register Description Tables
In addition to the summaries in this chapter, this document uses a standard tabular
format to describe the operation of each register in the device. These descriptions are
cross-referenced from summary tables and cover the specific content and functionality
of a register. The information in a register description table can be broken down into
three major areas:
• Materialization information that establishes how the register appears to software.
• Global information that lists the size, default, value, power well, etc. for the
register.
• Field definitions that list the name, description, default value, and attributes of all
the fields in the register.
The register definition can describe a unique register entity in the design or serve as a
template that describes several register entities are instantiated in the design. The
materialization information in the register description table can handle common
scenarios with minimal duplication of content:
• A single physical register that materializes at multiple “addresses” in the system
(i.e., a double- or triple-mapped register).
• Multiple physical registers that share the same definition but materialize within
different “device” instances.
• Multiple physical registers that share the same definition but materialize repeatedly
within a single “device”.
The register description table format handles the first two scenarios through “views”
that make up the bulk of the materialization information in a register description table
and handles the final scenario through a set of “repeated register” conventions.
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The materialization information in a table includes specification of one or more “views”.
Each view consists of a view “type” along with several type-specific fields that serve to
specify the “address” of the register in the system from a particular perspective. For
example, a PCI “view” includes, in part, the PCI bus number as a parameter since this
information is necessary to specify the location of the register. In a register description
table, each view specification occupies one row of the table. A register description table
includes one or more views depending on how the register materializes to software.
There are a number of different views that this document uses to describe how
EP80579 registers materialize to software. Table 7-1 defines the views that this
document uses along with the type-specific fields that each view includes.
Table 7-1.
Definition of the Views Used in Register Description Tables
View Type
PCI
Type-Specific Fields
Describes
Registers in
Name
B:D:F
PCI Bus, Device, and Function number that the
register is associated with through PCI configuration,
memory-mapped, or I/O-mapped spaces (see BAR).
BAR
PCI base address register in B:D:F that the register is
referenced from. This field is “Configuration” for
registers that materialize in PCI configuration space.
Otherwise, the field is the name of the BAR register in
B:D:F that provides the base address.
The register materializes in memory space unless the
BAR field contains “(IO)”; i.e., views with a BAR of
“FOOBAR” and “FOOBAR (IO)” materialize in memory
and I/O spaces, respectively.
Offset Start
Starting offset from BAR. The offset is in bytes unless
the field contains “(2B)”, “(4B)”, and “(8B)” to indicate
a single-, double-, or quad-word offset, respectivelya.
PCI configuration
space or memory/
IO spaces that are
mapped via PCI
BARs
Offset End
IA F
Description
Ending offset of register from BAR. The offset is in
bytes unless the field contains “(2B)”, “(4B)”, and
“(8B)” to indicate a single-, double-, or quad-word
offset, respectivelya.
Base Address
Base address. Typically, this field contains a number or
register name. It may contain a comma-separated list
if the register can materialize at one of several
possible bases (for example, “100h, 200h based on
FOOREG”).
The register materializes in memory space unless the
base address field contains “(IO)”; i.e., views with a
base address of “0000h” and “0000h (IO)” are in
memory and I/O space, respectively.
Offset Start
Starting address or offset from base address field. The
offset is in bytes unless the field contains “(2B)”,
“(4B)”, and “(8B)” to indicate a single-, double-, or
quad-word offset, respectivelya.
Offset End
Ending address or offset from base address field. The
offset is in bytes unless the field contains “(2B)”,
“(4B)”, and “(8B)” to indicate a single-, double-, or
quad-word offset, respectivelya.
General “fixed”
location in IA
memory or I/O
spaces
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Table 7-1.
Definition of the Views Used in Register Description Tables
View Type
IA I
Describes
Registers in
Indirect location
accessed via
index/window
register pair
Type-Specific Fields
Name
Description
Win:Idx
Name of the window and index registers that expose
the indirect register(s).
For example, W:I of “FOO:BAR” indicates that
accesses to FOO indirectly access the register that is
located at the index (i.e., offset) in BAR.
Offset Start
Starting offset to put in the index register to access
the indirect register. The index is in bytes unless the
field contains “(2B)”, “(4B)”, and “(8B)” to indicate a
single-, double-, or quad-word offset, respectivelya.
Offset End
Ending address or offset from base address field. The
offset is in bytes unless the field contains “(2B)”,
“(4B)”, and “(8B)” to indicate a single-, double-, or
quad-word offset, respectivelya.
a. In this usage, words, double words, and quad words are 16-, 32-, and 64-bits, respectively.
The register description tables adopt the convention that Table 7-2 and Table 7-3
describe for view and register name information to distinguish the three scenarios
mentioned above (single physical register, multiple physical registers in the same
device, and multiple physical registers in different devices). Table 7-2 describes how to
interpret the combination of register views and name. This table elides the type-specific
fields and simply lists the types of views for brevity.
Table 7-2.
View Convention to Describe Single Versus Multiple Physical Registers
Scenario
Register
Name
Example Views from
Register Table
Single
FOO
PCI
PCI
IA F
IA F
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Interpretation
This example shows a single physical register
FOO. FOO materializes in two different PCI
devices and at two different “fixed” memory
locations that the PCI and IA M views describe.
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Table 7-2.
View Convention to Describe Single Versus Multiple Physical Registers
Scenario
Multiple
(Different
Devices,
Same name)
Multiple
(Different
Devices and
Names)
Multiple
(Same
Device)
Register
Name
Example Views from
Register Table
Interpretation
PCI 1
PCI 2
IA F 1
IA F 2
All views for the register include a numeric suffix
that corresponds to the physical instance of the
register. Views with the same suffix address the
same physical register.
This example shows two physical registers
matching the description of BAZ. The first
instance of BAZ materializes in the PCI device
and at the memory location that the PCI 1 and IA
F 1 views describe, while the second instance of
BAZ materializes in PCI 2 and at IA F 2.
PCI 0
PCI 1
PCI 2
IA F 0
IA F 1
IA F 2
Like the Multiple scenario above, the views also
include a numeric suffix that, in this case, maps
to different register names. The {m:n} notation
in the register name indicates that each physical
instance of the register has a different name that
includes the instance number. An instance
number i is an integer such that n ≤ i ≤ m . This
implies that there are m - n + 1 distinct instances
of the register.
This example shows three physical registers
matching the description of BAZ: BAZ0, BAZ1,
and BAZ2. BAZ0 materializes in the PCI device
and at the memory location that the PCI 0 and IA
F 0 views describe, BAZ1 materializes in PCI 1
and at IA F 1, and BAZ2 materializes in PCI 2 and
at IA F 2.
PCI
PCI
IA F
IA F
The register name has a suffix indicating the
number of physical instances of the register. The
format of the suffix is “[m-n]” where m and n are
integers and implies that there are n - m + 1
distinct instances of the register.
This example shows three physical registers
matching the description of BLEH: BLEH[1],
BLEH[2], and BLEH[3]. Each register materializes
in two different PCI devices and at two different
“fixed” memory locations that the PCI and IA M
views describe.
BAZ
BAZ{2:0}
BLEH[1-3]
When describing multiple physical registers of the same “format” that materialize in the
same device, the tables use the convention that Table 7-3 describes to denote the
offsets1.
Table 7-3.
Offset Convention to Describe Multiple Physical Registers in the Same Device
Register
Name
Offset in
View(s) (Start
or End)
Interpretation
BLEH[1-3]
10h, 38h, 70h
Three BLEH registers whose offsets match the elements of the commaseparated list. The offsets are BLEH[1] = 10h, BLEH[2] = 38h, BLEH[3] =
70h.
BAZ[1-2]
103h at 2h
Two BAZ registers whose offsets stride by 2h starting from 103h. The
offsets are BAZ[1] = 103h, BAZ[2] = 105h.
The remainder of this section presents several examples that illustrates how to read
register definition tables. These examples are intended to illustrate how to interpret a
register definition table, not describe actual registers in the EP80579. As a result, some
of the examples may be contrived from the perspective of an implementation.
1. In this scenario, it is the offset that distinguishes the different materialization points of the registers; the remaining view fields
should be the same since this scenario applies to registers in the same “device”.
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Given the conventions outlined above, Table 7-4 presents an example definition for the
register EG_SINGLE which corresponds to a single physical register. This register
materializes at offset E0h in the configuration space for PCI device 4, at double-word
(i.e., 32-bit) offset 100h in the memory region defined by FOOBAR of PCI device 12,
and at the fixed offset 0A0h in IA I/O space1.
Table 7-4.
EG_SINGLE: Example Single Register with Different Views
Description: A single physical register that materializes at multiple locations.
View: PCI
BAR: Configuration
Bus:Device:Function: 0:4:0
Offset Start: E0h
Offset End: E1h
View: PCI
BAR: FOOBAR
Bus:Device:Function: 0:12:0
Offset Start: 100h (4B)
Offset End: 101h (4B)
View: IA F
Size: 16 bit
Bit Range
15 : 00
Offset Start: A0h
Offset End: A1h
Base Address: 0000h (IO)
Default: 8086h
Bit Acronym
MAGIC
Power Well: Core
Bit Description
Sticky
Magic Stuff: This field contains a magic number, 8086h.
Bit Reset
Value
Bit Access
8086h
RO
In the table, the materialization information includes the rows starting with “View” and
the title; the field definitions includes all rows below the row starting with “Bit Range”,
and the rows beginning “Description” and “Size” encompass the global information.
Table 7-5 presents an example definition for the register EG_MULTI_DIFF which
corresponds to two physical registers that materialize in different “devices”. The first
instance materializes at offset D0h in the configuration space for PCI device 20 and at
the fixed offset FFEF01B0h in IA memory space. The second instance materializes at
offset D0h in the configuration space for PCI device 21 and at the fixed offset
FFEF11C0h in IA memory space. Both registers have the same name, EG_MULTI_DIFF.
Table 7-5.
EG_MULTI_DIFF: Example Multiple Registers in Different Devices with
Different Views
Description: A set of two physical registers that materialize in different devices.
View: PCI 1
BAR: Configuration
Bus:Device:Function: 0:20:0
Offset Start: D0h
Offset End: D3h
View: PCI 2
BAR: Configuration
Bus:Device:Function: 0:21:0
Offset Start: D0h
Offset End: D3h
View: IA F 1
Base Address: 00000000h
Offset Start: FFEF01B0h
Offset End: FFEF01B3h
View: IA F 2
Base Address: 00000000h
Offset Start: FFEF11C0h
Offset End: FFEF11C3h
Size: 32 bit
Bit Range
31 : 00
Default: DEADBEEFh
Bit Acronym
BMAGIC
Power Well: Core, Reset
Bit Description
Black Magic Stuff: This field contains a magic number.
Sticky
Bit Reset
Value
Bit Access
DEADBEEFh
RO
1. Recall that offsets are in bytes unless otherwise specified with “(2B)”, “(4B)”, or “(8B)”.
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This table illustrates how the global information can be tied to a particular register in
multiple register cases. In this table, the first and second instances of EG_MULT_DIFF
are in the “Core” and “Reset” power wells, respectively. Typically, this notation is only
be used for the power well.
It is also possible to incorporate the instance number in the name as Table 7-2
describes. Using the name EG_MULTI{2:1}_DIFF in Table 7-5 would identify two
physical registers with different names. The first, EG_MULTI2_DIFF, materializes
according to the PCI 2 and IA F 2 views, while the second, EG_MULTI1_DIFF,
materializes according to the PCI 1 and IA F 1 views.
Table 7-6 presents an example definition for the register EG_MULTI_SAME which
corresponds to two physical registers that materialize in the same “device”. The
instance EG_MULT_SAME[1] materializes at offset ACE0h in the I/O region defined by
BLAHBAR of PCI device 16 and at the fixed offset 100h in IA I/O space. The instance
EG_MULT_SAME[2] materializes at offset ACE4h in the I/O region defined by BLAHBAR
of PCI device 16 and at the fixed offset 120h in IA I/O space.
Table 7-6.
EG_MULTI_SAME[1-2]: Example Multiple Registers in Same Device with
Different Views
Description: A set of two physical registers that materialize in the same device.
View: PCI
View: IA F
Size: 32 bit
Bit Range
31 : 00
BAR: BLAHBAR (IO)
Offset Start: ACE0h at 4h
Offset End: ACE3h at 4h
Bus:Device:Function: 0:16:0
Offset Start: 100h, 120h
Offset End: 103h, 123h
Base Address: 0000h (IO)
Default: DEAD8086h
Power Well: Core
Bit Acronym
Bit Description
BRMAGIC
Blacker Magic Stuff: This field contains a magic number.
Sticky
Bit Reset
Value
Bit Access
DEAD8086h
RO
Note that in this example, the strides do not need to be the same across the different
views.
Finally, Table 7-7 presents an example definition for the register EG_INDEX which
corresponds to a physical registers that materialize indirectly. To access the EG_INDEX
register, the starting offset 0100h (in double words of 32-bits) is written to the
APIC_IDX index register to select EG_INDEX which is then accessed through the
APIC_WND window registers.
Table 7-7.
EG_INDEX: Example Single Indexed Register
Description: A single indexed register.
View: IA I
Size: 32 bit
Bit Range
31 : 00
Win:Idx APIC_WND:APIC_IDX
Offset Start: 0100h (4B)
Offset End: 0100h (4B)
Default: 0ACEFACEh
Power Well: Core
Bit Acronym
MAGIC
Bit Description
Magic Stuff: This field contains a magic number.
Sticky
Bit Reset
Value
Bit Access
0ACEFACEh
RO
The offsets should always fit within the index register.
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7.1.2
Register Field Access Attributes
Table 7-8 describes the register field access attribute acronyms that this document
uses in its summaries and descriptions.
Table 7-8.
Register Field Access Attributes
Attribute
Description
RV
Reserved – A reserved field.
RO
Read-Only – Software/BIOS can only read this bit. Contents are either hardwired or set by
hardware.
WO
Write-Only – Not supported as a bit. The write causes a hardware event to take place.
WRC
RC
RW
RWC
Write/Read to Clear – Writes and reads clear. See bit descriptions.
Read to Clear – Cleared automatically when read.
Read/Write – Software/BIOS can read and write this bit.
Read/Write-Clear – Software/BIOS can read this bit and must write to a 1 to clear this bit.
RCWC
Read-Clear/Write-Clear – Cleared when read or Write one to clear.
RW0C
Read/Write zero to Clear – Software/BIOS can read this bit, and must write to a 0 to clear this
bit.
R0/W
Read zero/Write – This register will only read 0. Must read register description for write actions.
RO/RWC
Read only/Read-Write-Clear – Attribute dependent on configuration. See bit description
RS/W1C
Read-Set/Write-Clear – Read to set, write 1 to clear
RWS
Read/Write-Set – Software/BIOS can read this bit and write it to a 1. Hardware clears this bit.
RWL
Read/Write-Lock – Software/BIOS can read and write this bit. Hardware or another
configuration bit can lock this bit and prevent it from being updated.
RWO
Read/Write-Once – Software/BIOS can read this bit, but can only write this bit once. It is a
special form of RWL. Once any byte within a register with RWO bits has been written, the RWO
bits are locked and only a reset can clear its contents. Any exceptions are clearly documented.
In some cases, the access attribute for a field may depend on a setting of a fuse or a
value in another register. In this case, the access types for the field will be of the form
“X or Y”. Readers should consult the description of the field for additional information
on the conditions that enable the various access types. For example, a field FOO that is
either RO or RW based on the setting of a fuse bit would have an access type of “RO or
RW”.
7.1.3
Register Nomenclature and Values
The summary and description tables also include register and field values. In general, a
number is given by a string of digits followed by a single-character that identifies the
base as decimal, “d”, hexadecimal, “h”, or binary, “b”. Both the digits and base pieces of
a number are always case-insensitive1. That is, beefh and BEEFH represent the same
hexadecimal number. A value of 0 (zero) does not require a base character. If a value is
non-zero, the default base is assumed to be binary unless stated otherwise. All
hexadecimal and decimal numbers must always have a base character.
In addition to the legal digits for the base, the digit string can contain “x” to denote
undefined values. Typically, Xh is equivalent to XXXXb, XXh is equivalent to
XXXXXXXXb. However, a 5-bit wide field that is undefined can be represented as both
XXh and XXXXXb; that is, a nibble in a hex representation must be “x” if any of its bits
are “x”.
1. The “suggested” convention is that digits are always upper case while the base is always lower case.
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There are three special values that can be used in place of numbers to indicate cases
where the value of a register or field is not fixed at design time and depends on other
parameters:
• Fuse: The setting of one or more fuses determines the value of the register or
field.
• Strap: The setting of a strap pin determines the value of the register or field.
• Variable: The setting of other on-die state determines the value of the register or
field.
In these cases, the description of the register or field that is not fixed should contain
additional information that describes how the EP80579 arrives at the value.
Warning:
Address locations that are not listed are considered reserved register locations. Reads
to reserved registers may return non-zero values. Writes to reserved locations may
cause system failure.
7.1.4
“Sticky” Register Fields
For each field in a register, the description tables include an indication of whether or not
the bits that make up the field are “sticky” or not. Sticky bits in registers will retain
their value across a hard reset. Resetting field in a register that is designated as
“sticky” to its default/reset value requires a cold reset. Unless explicitly noted, all
register fields are assumed to not be sticky.
7.2
IA-32 core Registers
The IA-32 core registers are described in the related documentation for the Intel®
Pentium® M Processor .
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7.3
IMCH and IICH Registers
This section summarizes the registers found in the IMCH and the IICH.
7.3.1
IMCH Registers: Bus 0, Device 0, Function 0
The IMCH includes the registers listed in Table 7-9 through Table 7-11. These registers
materialize in PCI configuration and memory (via PCI BAR) spaces. See Section 16.1,
“IMCH Registers: Bus 0, Device 0, Function 0”, and Section 16.7, “Memory Mapped I/O
for NSI Registers” for detailed discussion of these registers.
Table 7-9.
Offset Start
Bus 0, Device 0, Function 0: Summary of IMCH PCI Configuration Registers
(Sheet 1 of 2)
Offset End
Register ID - Description
Default
Value
00h
01h
“Offset 00h: VID – Vendor Identification Register” on page 391
8086h
02h
03h
“Offset 02h: DID – Device Identification Register” on page 391
5020h
04h
05h
“Offset 04h: PCICMD: PCI Command Register” on page 392
0006h
06h
07h
“Offset 06h: PCISTS: PCI Status Register” on page 393
0010h
08h
08h
“Offset 8h: RID - Revision Identification Register” on page 394
Variable
0Ah
0Ah
“Offset 0Ah: SUBC - Sub-Class Code Register” on page 394
00h
0Bh
0Bh
“Offset 0Bh: BCC – Base Class Code Register” on page 394
06h
0Eh
0Eh
“Offset 0Eh: HDR - Header Type Register” on page 395
80h
14h
17h
“Offset 14h: SMRBASE - System Memory RCOMP Base Address Register” on
page 396
00000000h
2Ch
2Dh
“Offset 2Ch: SVID - Subsystem Vendor Identification Register” on page 396
0000h
2Eh
2Fh
“Offset 2Eh: SID - Subsystem Identification Register” on page 397
0000h
4Ch
4Fh
“Offset 4Ch: NSIBAR - Root Complex Block Address Register” on page 397
00000000h
50h
50h
“Offset 50h: CFG0- IMCH Configuration 0 Register” on page 398
0Ch
51h
51h
“Offset 51h: IMCH_CFG1 – IMCH Configuration 1 Register” on page 399
00000h
53h
53h
“Offset 53h: CFGNS1 - Configuration 1 (Non-Sticky) Register” on page 399
00h
58h
58h
“Offset 58h: FDHC - Fixed DRAM Hole Control Register” on page 400
00h
59h
59h
“Offset 59h: PAM0 - Programmable Attribute Map 0 Register” on page 401
00h
5Ah
5Ah
“Offset 5Ah: PAM1: Programmable Attribute Map 1 Register” on page 402
00h
5Bh
5Bh
“Offset 5Bh: PAM2 - Programmable Attribute Map 2 Register” on page 403
00h
5Ch
5Ch
“Offset 5Ch: PAM3 - Programmable Attribute Map 3 Register” on page 404
00h
5Dh
5Dh
“Offset 5Dh: PAM4 - Programmable Attribute Map 4 Register” on page 405
00h
5Eh
5Eh
“Offset 5Eh: PAM5 - Programmable Attribute Map 5 Register” on page 406
00h
5Fh
5Fh
“Offset 5FH: PAM6 - Programmable Attribute Map 6 Register” on page 407
00h
9Ch
9Ch
“Offset 9Ch: DEVPRES - Device Present Register” on page 408
33h
9Dh
9Dh
“Offset 9Dh: EXSMRC - Extended System Management RAM Control Register” on
page 409
00h
9Eh
9Eh
“Offset 9Eh: SMRAM - System Management RAM Control Register” on page 411
02h
9Fh
9Fh
“Offset 9Fh: EXSMRAMC - Expansion System Management RAM Control Register”
on page 413
07h
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Table 7-9.
Offset Start
Bus 0, Device 0, Function 0: Summary of IMCH PCI Configuration Registers
(Sheet 2 of 2)
Offset End
Default
Value
Register ID - Description
B8h
BBh
“Offset B8h: IMCH_MENCBASE: IA/ASU Shared Non-Coherent (AIOC-Direct)
Memory Base Address Register” on page 413
000FFFFFh
BCh
BFh
“Offset BCh: IMCH_MENCLIMIT - IA/ASU Shared Non-Coherent (AIOC-Direct)
Memory Limit Address Register” on page 414
00000000h
C4h
C5h
“Offset C4h: TOLM - Top of Low Memory Register” on page 415
0800h
C6h
C7h
“Offset C6h: REMAPBASE - Remap Base Address Register” on page 416
03FFh
C8h
C9h
“Offset C8h: REMAPLIMIT – Remap Limit Address Register” on page 416
0000h
CAh
CBh
“Offset CAh: REMAPOFFSET - Remap Offset Register” on page 417
0000h
CCh
CDh
“Offset CCh: TOM - Top Of Memory Register” on page 417
0000h
CEh
CFh
“Offset CEh: HECBASE - PCI Express Port A (PEA) Enhanced Configuration Base
Address Register” on page 418
E000h
D8h
D8h
“Offset D8h: CACHECTL0 - Write Cache Control 0 Register” on page 418
00h
DEh
DFh
“Offset DEh: SKPD - Scratchpad Data Register” on page 419
0000h
F6h
F6h
“Offset F6h: IMCH_TST2 - IMCH Test Byte 2 Register” on page 419
00h
60h at 1h
60h at 1h
“Offset 60h: DRB[0-3] - DRAM Row [3:0] Boundary Register” on page 421
ffh
70h at 4h
73h at 4h
“Offset 70h: DRA[0-1] - DRAM Row [0:1] Attribute Register” on page 422
00000515h
78h
7Bh
“Offset 78h: DRT0 - DRAM Timing Register 0” on page 424
242AD280h
64h
67h
“Offset 64h: DRT1 - DRAM timing Register 1” on page 431
12110000h
7Ch
7Fh
“Offset 7Ch: DRC - DRAM Controller Mode Register” on page 435
00000002h
87h
“Offset 84h: ECCDIAG - ECC Detection/Correction Diagnostic Register” on
page 437
00000000h
88h
8Bh
“Offset 88h: SDRC - DDR SDRAM Secondary Control Register” on page 439
00000002h
8Ch
8Ch
“Offset 8Ch: CKDIS - CK/CK# Clock Disable Register” on page 441
00h
8Dh
8Dh
“Offset 8Dh: CKEDIS - CKE Clock Enable Register” on page 442
00h
90h
93h
“Offset 90h: SPARECTL - SPARE Control Register” on page 443
00000000h
B0h
B3h
“Offset B0h: DDR2ODTC - DDR2 ODT Control Register” on page 444
00000000h
84h
Table 7-10. Bus 0, Device 0, Function 0: Summary of IMCH Configuration Registers
Mapped Through NSIBAR Memory BAR (Sheet 1 of 2)
Offset Start
Offset End
Default
Value
Register ID - Description
00h
03h
“Offset 00h: SNSIVCECH - NSI Virtual Channel Enhanced Capability Header
Register” on page 680
04010002h
04h
07h
“Offset 04h: NSIPVCCAP1 - NSI Port VC Capability Register 1” on page 680
00000000h
08h
0Bh
“Offset 08h: NSIPVCCAP2 - Port VC Capability Register 2” on page 681
00000001h
0Ch
0Dh
“Offset 0Ch: NSIPVCCTL - NSI Port VC Control Register” on page 682
0000h
10h
13h
“Offset 10h: NSIVC0RCAP - NSI VC0 Resource Capability Register” on page 682
00000001h
14h
17h
“Offset 14h: NSIVC0RCTL - NSI VC0 Resource Control Register” on page 683
800000FFh
1Ah
1Bh
“Offset 1Ah: NSIVC0RSTS - NSI VC0 Resource Status Register” on page 684
0002h
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Intel® EP80579 Integrated Processor
Table 7-10. Bus 0, Device 0, Function 0: Summary of IMCH Configuration Registers
Mapped Through NSIBAR Memory BAR (Sheet 2 of 2)
Offset Start
Offset End
Register ID - Description
Default
Value
80h
83h
“Offset 80h: NSIRCILCECH - NSI Root Complex Internal Link Control Enhanced
Capability Header Register” on page 684
00010006h
84h
87h
“Offset 84h: NSILCAP - NSI Link Capabilities Register” on page 685
0003A041h
Table 7-11. Bus 0, Device 0, Function 0: Summary of IMCH SMRBASE Registers (Sheet 1 of
2)
Offset Start
Offset End
Register ID - Description
Default
Value
00h
01h
“Offset 00h: NOTESPAD - Note (Sticky) Pad for BIOS Support Register” on
page 601
0000h
02h
03h
“Offset 02h: NOTEPAD - Note Pad for BIOS Support Register” on page 601
0000h
40h
43h
“Offset 40h: DCALCSR – DCAL Control and Status Register” on page 602
00000000h
44h
47h
“Offset 44h: DCALADDR - DCAL Address Register” on page 606
00000000h
00000000h
48h at 1h
48h at 1h
“Offset 48h: DCALDATA[0-71] - DRAM Calibration Data Register” on page 607
94h
96h
“Offset 94h: RCVENAC - Receiver Enable Algorithm Control Register” on page 611 180810h
98h
9Bh
“Offset 98h: DSRETC - DRAM Self-Refresh (SR) Extended Timing and Control
Register” on page 611
5c141400h
9Ch
9Ch
“Offset 9Ch: DQSFAIL1 - DQS Failure Configuration Register 1” on page 612
00h
A0h
A3h
“Offset A0h: DQSFAIL0 - DQS Failure Configuration Register 0” on page 613
00000000h
A4h
A7h
“Offset A4h: DRRTC00 - Receive Enable Reference Output Timing Control Register”
06060606h
on page 615
A8h
ABh
“Offset A8h: DRRTC01 - Receive Enable Reference Output Timing Control Register”
06060606h
on page 616
C4h
C4h
“Offset C4h: DRRTC02 - Receive Enable Reference Output Timing Control Register”
06h
on page 616
B4h
B7h
“Offset B4h: DQSOFCS00 - DQS Calibration Register” on page 617
00000000h
B8h
BBh
“Offset B8h: DQSOFCS01 - DQS Calibration Register” on page 617
00000000h
C6h
C6h
“Offset C6h: DQSOFCS02 - DQS Calibration Register” on page 618
00h
BCh
BFh
“Offset BCh: DQSOFCS10 - DQS Calibration Register” on page 618
00000000h
C0h
C3h
“Offset C0h: DQSOFCS11 - DQS Calibration Register” on page 619
00000000h
C7h
C7h
“Offset C7h: DQSOFCS12 - DQS Calibration Register” on page 619
00h
CCh
CFh
“Offset CCh: WPTRTC0 - Write Pointer Timing Control Register” on page 620
00000000h
D0h
D0h
“Offset D0h: WPTRTC1 - Write Pointer Timing Control 1 Register” on page 621
00h
D4h
D7h
“Offset D4h: DDQSCVDP0 - DQS Delay Calibration Victim Pattern 0 Register” on
page 621
aaaa0a05h
D8h
DBh
“Offset D8h: DDQSCVDP1 - DQS Delay Calibration Victim Pattern 1 Register” on
page 622
5b339c5dh
DCh
DFh
“Offset DCh: DDQSCADP0 - DQS Delay Calibration Aggressor Pattern 0 Register”
on page 622
aaabffffh
E0h
E3h
“Offset E0h: DDQSCADP1 - DQS Delay Calibration Aggressor Pattern 1 Register”
on page 623
db339ce1h
F0h
F3h
“Offset F0h: DIOMON - DDR I/O Monitor Register” on page 623
00000000h
August 2009
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Intel® EP80579 Integrated Processor Product Line Datasheet
193
Intel® EP80579 Integrated Processor
Table 7-11. Bus 0, Device 0, Function 0: Summary of IMCH SMRBASE Registers (Sheet 2 of
2)
Offset Start
Offset End
Default
Value
Register ID - Description
F8h
FBh
“Offset F8h: DRAMISCTL - Miscellaneous DRAM DDR Cluster Control Register” on
page 624
1011h
C8h
CAh
“Offset C8h: DRAMDLLC - DDR I/O DLL Control Register” on page 625
0DB6C0h
E8h
EBh
“Offset E8h: FIVESREG - Fixed 5s Pattern Register” on page 625
55555555h
ECh
EFh
“Offset ECh: AAAAREG - Fixed A Pattern Register” on page 626
AAAAAAAAh
140h
143h
“Offset 140h: MBCSR - MemBIST Control Register” on page 626
00000000h
144h
147h
“Offset 144h: MBADDR - Memory Test Address Register” on page 629
00h
148h at 4h
14Ch at 4h
“Offset 148h: MBDATA[0:9] - Memory Test Data Register” on page 629
00h
19Ch
19Fh
“Offset 19Ch: MB_START_ADDR - Memory Test Start Address Register” on
page 632
00h
1A0h
1A3h
“Offset 1A0h: MB_END_ADDR - Memory Test End Address Register” on page 632
00h
1A4h
1A7h
“Offset 1A4h: MBLFSRSED - Memory Test Circular Shift and LFSR Seed Register”
on page 633
00h
1A8h
1ABh
“Offset 1A8h: MBFADDRPTR - Memory Test Failure Address Pointer Register” on
page 633
00h
1B0h
1B3h
“Offset 1B0h: MB_ERR_DATA00 - Memory Test Error Data 0” on page 634
00h
1B4h
1B7h
“Offset 1B4h: MB_ERR_DATA01 - Memory Test Error Data 0” on page 634
00h
1B8h
1BBh
“Offset 1B8h: MB_ERR_DATA02 - Memory Test Error Data 0” on page 634
00h
1BCh
1BFh
“Offset 1BCh: MB_ERR_DATA03 - Memory Test Error Data 0” on page 635
00h
1C0h
1C1h
“Offset 1C0h: MB_ERR_DATA04 - Memory Test Error Data 0” on page 635
00h
1C4h
1C7h
“Offset 1C4h: MB_ERR_DATA10 - Memory Test Error Data 1” on page 635
00h
1C8h
1CBh
“Offset 1C8h: MB_ERR_DATA11 - Memory Test Error Data 1” on page 636
00h
1CCh
1CFh
“Offset 1CCh: MB_ERR_DATA12 - Memory Test Error Data 1” on page 636
00h
1D0h
1D3h
“Offset 1D0h: MB_ERR_DATA13 - Memory Test Error Data 1” on page 636
00h
1D4h
1D5h
“Offset 1D4h: MB_ERR_DATA14 - Memory Test Error Data 1” on page 637
00h
1D8h
1DBh
“Offset 1D8h: MB_ERR_DATA20 - Memory Test Error Data 2” on page 637
00h
1DCh
1DFh
“Offset 1DCh: MB_ERR_DATA21 - Memory Test Error Data 2” on page 637
00h
1E0h
1E3h
“Offset 1E0h: MB_ERR_DATA22 - Memory Test Error Data 2” on page 638
00h
1E4h
1E7h
“Offset 1E4h: MB_ERR_DATA23 - Memory Test Error Data 2” on page 638
00h
1E8h
1E9h
“Offset 1E8h: MB_ERR_DATA24 - Memory Test Error Data 2” on page 638
00h
1ECh
1EFh
“Offset 1ECh: MB_ERR_DATA30 - Memory Test Error Data 3” on page 639
00h
1F0h
1F4h
“Offset 1F0h: MB_ERR_DATA31 - Memory Test Error Data 3” on page 639
00h
1F4h
1F7h
“Offset 1F4h: MB_ERR_DATA32 - Memory Test Error Data 3” on page 639
00h
1F8h
1FBh
“Offset 1F8h: MB_ERR_DATA33 - Memory Test Error Data 3” on page 640
00h
1FCh
1FDh
“Offset 1FCh: MB_ERR_DATA34 - Memory Test Error Data 3” on page 640
00h
260h
263h
“Offset 260h: DDRIOMC0 - DDRIO Mode Register Control Register” on page 641
00000078h
264h
267h
“Offset 264h: DDRIOMC1 - DDRIO Mode Register Control Register 1” on page 642 52520000h
268h
26Bh
“Offset 268h: DDRIOMC2 - DDRIO Mode Control Register 2” on page 645
039E6000h
284h at 4h
294h at 4h
“Offset 284h: WL_CNTL[4:0] - Write Levelization Control Register” on page 647
00000000h
298h
29Bh
“Offset 298h: WDLL_MISC - DLL Miscellaneous Control” on page 649
00000000h
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Intel® EP80579 Integrated Processor
7.3.2
IMCH Error Reporting Registers: Bus 0, Device 0, Function 1
The IMCH includes the registers listed in Table 7-12. These registers materialize in PCI
configuration space. See Section 16.2, “DRAM Controller Error Reporting Registers: Bus
0, Device 0, Function 1” for detailed discussion of these registers.
Table 7-12. Bus 0, Device 0, Function 1: Summary of IMCH Error Reporting PCI
Configuration Registers (Sheet 1 of 2)
Offset Start
00h
Offset End
01h
Register ID - Description
“Offset 00h: VID - Vendor Identification Register” on page 447
Default
Value
8086h
02h
03h
“Offset 02h: DID - Device Identification Register” on page 447
5021h
04h
05h
“Offset 04h: PCICMD - PCI Command Register” on page 448
0000h
06h
07h
“Offset 06h: PCISTS - PCI Status Register” on page 448
0000h
08h
08h
“Offset 08h: RID - Revision Identification Register” on page 449
Variable
0Ah
0Ah
“Offset 0Ah: SUBC - Sub-Class Code Register” on page 449
00h
0Bh
0Bh
“Offset 0Bh: BCC - Base Class Code Register” on page 449
FFh
0Dh
0Dh
“Offset 0Dh: MLT - Master Latency Timer Register” on page 450
00h
0Eh
0Eh
“Offset 0Eh: HDR - Header Type Register” on page 450
00h
2Ch
2Dh
“Offset 2Ch: SVID - Subsystem Vendor Identification Register” on page 450
0000h
2Eh
2Fh
“Offset 2Eh: SID - Subsystem Identification Register” on page 451
0000h
40h
43h
“Offset 40h: GLOBAL_FERR - Global First Error Register” on page 451
00000000h
44h
47h
“Offset 44h: GLOBAL_NERR - Global Next Error Register” on page 453
00000000h
48h
4Bh
“Offset 48h: NSI_FERR - NSI First Error Register” on page 454
00000000h
4Ch
4Fh
“Offset 4Ch: NSI_NERR - NSI Next Error Register” on page 457
00000000h
50h
53h
“Offset 50h: NSI_SCICMD - NSI SCI Command Register” on page 459
00000000h
54h
57h
“Offset 54h: NSI_SMICMD: NSI SMI Command Register” on page 461
00000000h
58h
5Bh
“Offset 58h: NSI_SERRCMD - NSI SERR Command Register” on page 464
00000000h
5Ch
5Fh
“Offset 5Ch: NSI_MCERRCMD - NSI MCERR Command Register” on page 466
00000000h
60h
61h
“Offset 60h: FSB_FERR - FSB First Error Register” on page 468
0000h
62h
63h
“Offset 62h: FSB_NERR - FSB Next Error Register” on page 469
0000h
64h
65h
“Offset 64h: FSB_EMASK - FSB Error Mask Register” on page 470
0009h
68h
69h
“offset 68h: FSB_SCICMD - FSB SCI Command Register” on page 471
0000h
6Ah
6Bh
“Offset 6Ah: FSB_SMICMD - FSB SMI Command Register” on page 472
0000h
6Ch
6Dh
“Offset 6Ch: FSB_SERRCMD - FSB SERR Command Register” on page 473
0000h
6Eh
6Fh
“Offset 6Eh: FSB_MCERRCMD - FSB MCERR Command Register” on page 474
0000h
70h
70h
“Offset 70h: BUF_FERR - Memory Buffer First Error Register” on page 475
00h
72h
72h
“Offset 72h: BUF_NERR - Memory Buffer Next Error Register” on page 475
00h
74h
74h
“Offset 74h: BUF_EMASK - Memory Buffer Error Mask Register” on page 476
00h
00h
78h
78h
“Offset 78h: BUF_SCICMD - Memory Buffer SCI Command Register” on page 477
7Ah
7Ah
“Offset 7Ah: BUF_SMICMD - Memory Buffer SMI Command Register” on page 478 00h
7Ch
7Ch
“Offset 7Ch: BUF_SERRCMD - Memory Buffer SERR Command Register” on
page 479
August 2009
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00h
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Intel® EP80579 Integrated Processor
Table 7-12. Bus 0, Device 0, Function 1: Summary of IMCH Error Reporting PCI
Configuration Registers (Sheet 2 of 2)
Offset Start
Offset End
Default
Value
Register ID - Description
7Eh
7Eh
“Offset 7Eh: BUF_MCERRCMD - Memory Buffer MCERR Command Register” on
page 480
00h
E4h
E7h
“Offset E4h: NSIERRINJCTL - NSI Error Injection Control Register” on page 481
00040000h
E8h
EBh
“Offset E8h: BERRINJCTL - Buffer Error Injection Control Register” on page 482
00000000h
80h
81h
“Offset 80h: DRAM_FERR - DRAM First Error Register” on page 483
0000h
82h
83h
“Offset 82h: DRAM_NERR - DRAM Next Error Register” on page 484
0000h
84h
84h
“Offset 84h: DRAM_EMASK - DRAM Error Mask Register” on page 486
00h
88h
88h
“Offset 88h: DRAM_SCICMD - DRAM SCI Command Register” on page 487
00h
8Ah
8Ah
“Offset 8Ah: DRAM_SMICMD - DRAM SMI Command Register” on page 488
00h
8Ch
8Ch
“Offset 8Ch: DRAM_SERRCMD - DRAM SERR Command Register” on page 489
00h
8Eh
8Eh
“Offset 8Eh: DRAM_MCERRCMD - DRAM MCERR Command Register” on page 490
00h
98h
99h
“Offset 98h: THRESH_SEC0 - Rank 0 SEC Error Threshold Register” on page 491
0000h
9Ah
9Bh
“Offset 9Ah: THRESH_SEC1 - Rank 1 SEC Error Threshold Register” on page 491
0000h
A0h
A3h
“Offset A0h: DRAM_SECF_ADD - DRAM First Single Bit Error Correct Address
Register” on page 492
00000000h
A4h
A7h
“Offset A4h: DRAM_DED_ADD - DRAM Double Bit Error Address Register” on
page 492
00000000h
A8h
ABh
“Offset A8h: DRAM_SCRB_ADD - DRAM Scrub Error Address Register” on
page 493
00000000h
B0h
B1h
“Offset B0h: DRAM_SEC_R0 - DRAM Rank 0 SEC Error Counter Register” on
page 494
0000h
B2h
B3h
“Offset B2h: DRAM_DED_R0 - DRAM Rank 0 DED Error Counter Register” on
page 494
0000h
B4h
B5h
“Offset B4h: DRAM_SEC_R1 - DRAM Rank 1 SEC Error Counter Register” on
page 494
0000h
B6h
B7h
“Offset B6h: DRAM_DED_R1 - DRAM Rank 1 DED Error Counter Register” on
page 495
0000h
C2h
C3h
“Offset C2h: THRESH_DED - DED Error Threshold Register” on page 495
0000h
C4h
C5h
“Offset C4h: DRAM_SECF_SYNDROME - DRAM First Single Error Correct Syndrome
0000h
Register” on page 496
C6h
C7h
“Offset C6h: DRAM_SECN_SYNDROME - DRAM Next Single Error Correct
Syndrome Register” on page 496
0000h
C8h
CBh
“Offset C8h: DRAM_SECN_ADD - DRAM Next Single Bit Error Correct Address
Register” on page 497
00000000h
DCh
DDh
“Offset DCh: RANKTHREX - Rank Error Threshold Exceeded Register” on page 498 0000h
ECh
EFh
“Offset ECh: DERRINJCTL - DRAM Error Injection Control Register” on page 499
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00000000h
August 2009
Order Number: 320066-003US
Intel® EP80579 Integrated Processor
7.3.3
EDMA Engine Registers: Bus 0, Device 1, Function 0
The EDMA engine includes the registers listed in Table 7-13 and Table 7-14. These
registers materialize in PCI configuration and memory (via PCI BAR) spaces. See
Section 16.3, “EDMA Registers: Bus 0, Device 1, Function 0” and Section 16.6,
“Memory Mapped I/O for EDMA Registers” for detailed discussion of these registers.
Table 7-13. Bus 0, Device 1, Function 0: Summary of EDMA PCI Configuration Registers
Offset Start
00h
Offset End
01h
Register ID - Description
“Offset 00h: VID - Vendor Identification Register” on page 502
Default
Value
8086h
02h
03h
“Offset 02h: DID - Device Identification Register” on page 502
5023h
04h
05h
“Offset 04h: PCICMD - PCI Command Register” on page 503
0000h
06h
07h
“Offset 06h: PCISTS - PCI Status Register” on page 504
0010h
08h
08h
“Offset 08h: RID - Revision Identification Register” on page 504
Variable
0Ah
0Ah
“Offset 0Ah: SUBC - Sub-Class Code Register” on page 505
80h
0Bh
0Bh
“Offset 0Bh: BCC - Base Class Code Register” on page 505
08h
0Eh
0Eh
“Offset 0Eh: HDR - Header Type Register” on page 505
00h
10h
13h
“Offset 10h: EDMALBAR - EDMA Low Base Address Register” on page 506
00000000h
2Ch
2Dh
“Offset 2Ch: SVID - Subsystem Vendor Identification Register” on page 506
0000h
2Eh
2Fh
“Offset 2Eh: SID - Subsystem Identification Register” on page 507
0000h
34h
34h
“Offset 34h: CAPPTR - Capabilities Pointer Register” on page 507
B0h
3Ch
3Ch
“Offset 3Ch: INTRLINE - Interrupt Line Register” on page 507
00h
3Dh
3Dh
“Offset 3Dh: INTRPIN - Interrupt Pin Register” on page 508
01h
40h
40h
“Offset 40h: EDMACTL - EDMA Control Register” on page 508
08h
80h
83h
“Offset 80h: EDMA_FERR - EDMA First Error Register” on page 509
00000000h
84h
87h
“Offset 84h: EDMA_NERR - EDMA Next Error Register” on page 511
00000000h
88h
88h
“Offset 88h: EDMA_EMASK - EDMA Error Mask Register” on page 513
00h
A0h
A0h
“Offset A0h: EDMA_SCICMD - EDMA SCI Command Register” on page 514
00h
A4h
A4h
“Offset A4h: EDMA_SMICMD - EDMA SMI Command Register” on page 515
00h
A8h
A8h
“Offset A8h: EDMA_SERRCMD - EDMA SERR Command Register” on page 516
00h
ACh
ACh
“Offset ACh: EDMA_MCERRCMD - EDMA MCERR Command Register” on page 517
00h
B0h
B3h
“Offset B0h: MSICR - MSI Control Register” on page 518
00020005h
B4h
B7h
“Offset B4h: MSIAR - MSI Address Register” on page 519
FEE00000h
B8h
B9h
“Offset B8h: MSIDR - MSI Data Register” on page 520
0000h
Table 7-14. Bus 0, Device 1, Function 0: Summary of EDMA Configuration Registers
Mapped Through EDMALBAR Memory BAR (Sheet 1 of 3)
Offset Start
Offset End
Register ID - Description
Default
Value
00h
03h
“Offset 00h: CCR0 - Channel 0 Channel Control Register” on page 653
00000000h
04h
07h
“Offset 04h: CSR0 - Channel 0 Channel Status Register” on page 656
00000000h
August 2009
Order Number: 320066-003US
Intel® EP80579 Integrated Processor Product Line Datasheet
197
Intel® EP80579 Integrated Processor
Table 7-14. Bus 0, Device 1, Function 0: Summary of EDMA Configuration Registers
Mapped Through EDMALBAR Memory BAR (Sheet 2 of 3)
Offset Start
Offset End
Default
Value
Register ID - Description
08h
0Bh
“Offset 08h: CDAR0 - Channel 0 Current Descriptor Address Register” on page 657 00000000h
0Ch
0Fh
“Offset 0Ch: CDUAR0 - Channel 0 Current Descriptor Upper Address Register” on
page 658
00000000h
10h
13h
“Offset 10h: SAR0 - Channel 0 Source Address Register” on page 658
00000000h
14h
17h
“Offset 14h: SUAR0 - Channel 0 Source Upper Address Register” on page 659
00000000h
18h
1Bh
“Offset 18h: DAR0 - Channel 0 Destination Address Register” on page 659
00000000h
1Ch
1Fh
“Offset 1Ch: DUAR0 - Channel 0 Destination Upper Address Register” on page 660 00000000h
20h
23h
“Offset 20h: NDAR0 - Channel 0 Next Descriptor Address Register” on page 661
00000000h
24h
27h
“Offset 24h: NDUAR0 - Channel 0 Next Descriptor Upper Address Register” on
page 662
00000000h
28h
2Bh
“Offset 28h: TCR0 - Channel 0 Transfer Count Register” on page 662
00000000h
2Ch
2Fh
“Offset 2Ch: DCR0 - Channel 0 Descriptor Control Register” on page 663
00000000h
40h
43h
“Offset 40h: CCR1 - Channel 1 Channel Control Register” on page 665
00000000h
44h
47h
“Offset 44h: CSR1 - Channel 1 Channel Status Register” on page 665
00000000h
48h
4Bh
“Offset 48h: CDAR1 - Channel 1 Current Descriptor Address Register” on page 665 00000000h
4Ch
4Fh
“Offset 4Ch: CDUAR1 - Channel 1 Current Descriptor Upper Address Register” on
page 666
00000000h
50h
53h
“Offset 50h: SAR1 - Channel 1 Source Address Register” on page 666
00000000h
54h
57h
“Offset 54h: SUAR1 - Channel 1 Source Upper Address Register” on page 666
00000000h
58h
5Bh
“Offset 58h: DAR1 - Channel 1 Destination Address Register” on page 667
00000000h
5Ch
5Fh
“Offset 5Ch: DUAR1 - Channel 1 Destination Upper Address Register” on page 667 00000000h
60h
63h
“Offset 60h: NDAR1 - Channel 1 Next Descriptor Address Register” on page 667
00000000h
64h
67h
“Offset 64h: NDUAR1 - Channel 1 Next Descriptor Upper Address Register” on
page 668
00000000h
68h
6Bh
“Offset 68h: TCR1 - Channel 1 Transfer Count Register” on page 668
00000000h
6Ch
6Fh
“Offset 6Ch: DCR1 - Channel 1 Descriptor Control Register” on page 668
00000000h
80h
83h
“Offset 80h: CCR2 - Channel 2 Channel Control Register” on page 669
00000000h
84h
87h
“Offset 84h: CSR2 - Channel 2 Channel Status Register” on page 669
00000000h
88h
8Bh
“Offset 88h: CDAR2: Channel 2 Current Descriptor Address Register” on page 669 00000000h
8Ch
8Fh
“Offset 8Ch: CDUAR2 - Channel 2 Current Descriptor Upper Address Register” on
page 670
00000000h
90h
93h
“Offset 90h: SAR2 - Channel 2 Source Address Register” on page 670
00000000h
94h
97h
“Offset 94h: SUAR2 - Channel 2 Source Upper Address Register” on page 670
00000000h
98h
9Bh
“Offset 98h: DAR2 - Channel 2 Destination Address Register” on page 671
00000000h
9Ch
9Fh
“Offset 9Ch: DUAR2 - Channel 2 Destination Upper Address Register” on page 671 00000000h
A0h
A3h
“Offset A0h: NDAR2 - Channel 2 Next Descriptor Address Register” on page 671
00000000h
A4h
A7h
“Offset A4h: NDUAR2 - Channel 2 Next Descriptor Upper Address Register” on
page 672
00000000h
A8h
ABh
“Offset A8h: DCR2 - Channel 2Transfer Control Register” on page 672
00000000h
ACh
AFh
“Offset ACh: DCR2 - Channel 2 Descriptor Control Register” on page 672
00000000h
C0h
C3h
“Offset C0h: CCR3 - Channel 3 Channel Control Register” on page 673
00000000h
C4h
C7h
“Offset C4h: CSR3 - Channel 3 Channel Status Register” on page 673
00000000h
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Table 7-14. Bus 0, Device 1, Function 0: Summary of EDMA Configuration Registers
Mapped Through EDMALBAR Memory BAR (Sheet 3 of 3)
Offset Start
Offset End
Register ID - Description
Default
Value
C8h
CBh
“Offset C8h: CDAR3 - Channel 3 Current Descriptor Address Register” on page 673 00000000h
CCh
CFh
“Offset CCh: CDUAR3 - Channel 3 Current Descriptor Upper Address Register” on
page 674
00000000h
D0h
D3h
“Offset D0h: SAR3 - Channel 3 Source Address Register” on page 674
00000000h
D4h
D7h
“Offset D4h: SUAR3 - Channel 3 Source Upper Address Register” on page 674
00000000h
D8h
DBh
“Offset D8h: DAR3 - Channel 3 Destination Address Register” on page 675
00000000h
DCh
DFh
“Offset DCh: DUAR3 - Channel 3 Destination Upper Address Register” on page 675 00000000h
E0h
E3h
“Offset E0h: NDAR3 - Channel 3 Next Descriptor Address Register” on page 675
00000000h
E4h
E7h
“Offset E4h: NDUAR3 - Channel 3 Next Descriptor Upper Address Register” on
page 676
00000000h
E8h
EBh
“Offset E8h: TCR3 - Channel 3 Transfer Count Register” on page 676
00000000h
ECh
EFh
“Offset ECh: DCR3 - Channel 3 Descriptor Control Register” on page 677
00000000h
100h
103h
“Offset 100h: DCGC - EDMA Controller Global Command” on page 677
00000000h
104h
107h
“Offset 104h: DCGS - EDMA Controller Global Status” on page 678
00000000h
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7.3.4
PCI Express* Port A Registers: Bus 0, Device 2, Function 0
The PCI Express* Port A includes the registers listed in Table 7-15. These registers
materialize in PCI configuration spaces. See Section 16.4, “PCI Express* Port A
Standard and Enhanced Registers: Bus 0, Devices 2 and 3, Function 0” for detailed
discussion of these registers.
Table 7-15. Bus 0, Device 2, Function 0: Summary of PCI Express Port A Standard and
Enhanced PCI Configuration Registers (Sheet 1 of 3)
Offset Start
Offset End
Default
Value
Register ID - Description
00h
01h
“Offset 00h: VID - Vendor Identification Register” on page 527
8086h
02h
03h
“Offset 02h: DID - Device Identification Register” on page 527
5024h
04h
05h
“Offset 04h: PCICMD - PCI Command Register” on page 528
0000h
06h
07h
“Offset 06h: PCISTS - PCI Status Register” on page 530
0010h
08h
08h
“Offset 08h: RID - Revision Identification Register” on page 531
Variable
0Ah
0Ah
“Offset 0Ah: SUBC - Sub-Class Code Register” on page 532
04h
0Bh
0Bh
“Offset 0Bh: BCC - Base Class Code Register” on page 532
06h
0Ch
0Ch
“Offset 0Ch: CLS - Cache Line Size Register” on page 533
00h
0Eh
0Eh
“Offset 0Eh: HDR - Header Type Register” on page 533
01h
18h
18h
“Offset 18h: PBUSN - Primary Bus Number Register” on page 534
00h
19h
19h
“Offset 19h: SBUSN - Secondary Bus Number Register” on page 534
00h
1Ah
1Ah
“Offset 1Ah: SUBUSN: Subordinate Bus Number Register” on page 535
00h
1Ch
1Ch
“Offset 1Ch: IOBASE - I/O Base Address Register” on page 535
F0h
1Dh
1Dh
“Offset 1Dh: IOLIMIT - I/O Limit Address Register” on page 536
00h
1Eh
1Fh
“Offset 1Eh: SECSTS - Secondary Status Register” on page 536
0000h
20h
21h
“Offset 20h: MBASE - Memory Base Address Register” on page 538
FFF0h
22h
23h
“Offset 22h: MLIMIT - Memory Limit Address Register” on page 539
0000h
24h
25h
“Offset 24h: PMBASE - Prefetchable Memory Base Address Register” on page 540
FFF1h
26h
27h
“Offset 26h: PMLIMIT - Prefetchable Memory Limit Address Register” on page 540 0001h
28h
28h
“Offset 28h: PMBASU - Prefetchable Memory Base Upper Address Register” on
page 541
0Fh
2Ch
2Ch
“Offset 2Ch: PMLMTU - Prefetchable Memory Limit Upper Address Register” on
page 541
00h
34h
34h
“Offset 34h: CAPPTR - Capabilities Pointer Register” on page 542
50h
3Ch
3Ch
“Offset 3Ch: INTRLINE - Interrupt Line Register” on page 542
00h
3Dh
3Dh
“Offset 3Dh: INTRPIN - Interrupt Pin Register” on page 543
01h
3Eh
3Eh
“Offset 3Eh: BCTRL - Bridge Control Register” on page 543
00h
44h
44h
“Offset 44h: VSCMD0 - Vendor Specific Command Byte 0 Register” on page 545
00h
45h
45h
“Offset 45h: VSCMD1 - Vendor Specific Command Byte 1 Register” on page 546
00h
46h
46h
“Offset 46h: VSSTS0 - Vendor Specific Status Byte 0 Register” on page 547
00h
47h
47h
“Offset 47h: VSSTS1 - Vendor Specific Status Byte 1 Register” on page 547
00h
48h
48h
“Offset 48h: VSCMD2 - Vendor Specific Command Byte 2 Register” on page 548
00h
50h
50h
“Offset 50h: PMCAPID - Power Management Capabilities Structure Register” on
page 548
01h
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Table 7-15. Bus 0, Device 2, Function 0: Summary of PCI Express Port A Standard and
Enhanced PCI Configuration Registers (Sheet 2 of 3)
Offset Start
Offset End
Register ID - Description
Default
Value
“Offset 51h: PMNPTR - Power Management Next Capabilities Pointer Register” on
page 549
58h
53h
“Offset 52h: PMCAPA - Power Management Capabilities Register” on page 549
C822h
54h
55h
“Offset 54h: PMCSR - Power Management Status and Control Register” on
page 550
0000h
56h
56h
“Offset 56h: PMCSRBSE - Power Management Status and Control Bridge
Extensions Register” on page 551
00h
58h
58h
“Offset 58h: MSICAPID - MSI Capabilities Structure Register” on page 551
05h
51h
51h
52h
59h
59h
“Offset 59h: MSINPTR - MSI Next Capabilities Pointer Register” on page 552
64h
5Ah
5Bh
“Offset 5Ah: MSICAPA - MSI Capabilities Register” on page 553
0002h
5Ch
5Fh
“Offset 5Ch: MSIAR - MSI Address for PCI Express Register” on page 553
FEE00000h
60h
61h
“Offset 60h: MSIDR - MSI Data Register” on page 554
0000h
64h
64h
“Offset 64h: PEACAPID - PCI Express Features Capabilities ID Register” on
page 555
10h
65h
65h
“Offset 65h: PEANPTR - PCI Express Next Capabilities Pointer Register” on
page 556
00h
66h
67h
“Offset 66h: PEACAPA - PCI Express Features Capabilities Register” on page 556
0041h
68h
6Bh
“Offset 68h: PEADEVCAP - PCI Express Device Capabilities Register” on page 557
00000001h
6Ch
6Dh
“Offset 6Ch: PEADEVCTL - PCI Express Device Control Register” on page 558
0000h
6Eh
6Fh
“Offset 6Eh: PEADEVSTS - PCI Express Device Status Register” on page 560
0000h
70h
73h
“Offset 70h: PEALNKCAP - PCI Express Link Capabilities Register” on page 561
0203E481h
74h
75h
“Offset 74h: PEALNKCTL - PCI Express Link Control Register” on page 562
0001h
76h
77h
“Offset 76h: PEALNKSTS - PCI Express Link Status Register” on page 564
1001h
78h
7Bh
“Offset 78h: PEASLTCAP - PCI Express Slot Capabilities Register” on page 565
00000000h
7Ch
7Dh
“Offset 7Ch: PEASLTCTL - PCI Express Slot Control Register” on page 568
01C0h
7Eh
7Fh
“Offset 7Eh: PEASLTSTS - PCI Express Slot Status Register” on page 569
0040h
80h
83h
“Offset 80h: PEARPCTL - PCI Express Root Port Control Register” on page 570
00000000h
84h
87h
“Offset 84h: PEARPSTS - PCI Express Root Port Status Register” on page 571
00000000h
100h
103h
“Offset 100h: ENHCAPST - Enhanced Capability Structure Register” on page 571
00010001h
104h
107h
“Offset 104h: UNCERRSTS - Uncorrectable Error Status Register” on page 572
00000000h
108h
10Bh
“Offset 108h: UNCERRMSK - Uncorrectable Error Mask Register” on page 574
00000000h
10Ch
10Fh
“Offset 10Ch: UNCERRSEV - Uncorrectable Error Severity Register” on page 575
00062010h
110h
113h
“Offset 110h: CORERRSTS - Correctable Error Status Register” on page 576
00000000h
114h
117h
“Offset 114h: CORERRMSK - Correctable Error Mask Register” on page 578
00000000h
118h
11Bh
“Offset 118h: AERCACR - Advanced Error Capabilities and Control Register” on
page 579
00000000h
11Ch
11Fh
“Offset 11Ch: HDRLOG0 - Header Log DW 0 (1st 32 bits) Register” on page 580
00000000h
120h
123h
“Offset 120h: HDRLOG1 - Header Log DW 1 (2nd 32 bits) Register” on page 580
00000000h
124h
127h
“Offset 124h: HDRLOG2 - Header Log DW 2 (3rd 32 bits) Register” on page 581
00000000h
128h
12Bh
“Offset 128h: HDRLOG3 - Header Log DW 3 (4th 32 bits) Register” on page 581
00000000h
12Ch
12Fh
“Offset 12Ch: RPERRCMD - Root (Port) Error Command Register” on page 582
00000000h
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Table 7-15. Bus 0, Device 2, Function 0: Summary of PCI Express Port A Standard and
Enhanced PCI Configuration Registers (Sheet 3 of 3)
Offset Start
Offset End
Default
Value
Register ID - Description
130h
133h
“Offset 130h: RPERRMSTS - Root (Port) Error Message Status Register” on
page 583
00000000h
134h
137h
“Offset 134h: ERRSID - Error Source ID Register” on page 585
00000000h
140h
143h
“Offset 140h: PEAUNITERR - PCI Express Unit Error Register” on page 586
00000000h
144h
147h
“Offset 144h: PEAMASKERR - PCI Express Unit Mask Error Register” on page 588
0000E000h
148h
14Bh
“Offset 148h: PEAERRDOCMD - PCI Express Error Do Command Register” on
page 589
00000000h
14Ch
14Fh
“Offset 14Ch: UNCEDMASK - Uncorrectable Error Detect Mask Register” on
page 591
00000000h
150h
153h
“Offset 150h: COREDMASK - Correctable Error Detect Mask Register” on page 592 00000000h
158h
15Bh
“Offset 158h: PEAUNITEDMASK - PCI Express Unit Error Detect Mask Register” on
00000000h
page 594
160h
163h
“Offset 160h: PEAFERR - PCI Express First Error Register” on page 595
00000000h
164h
167h
“Offset 164h: PEANERR - PCI Express Next Error Register” on page 597
00000000h
168h
16Bh
“Offset 168h: PEAERRINJCTL - Error Injection Control Register” on page 597
00000000h
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7.3.5
PCI Express* Port A1 Registers: Bus 0, Device 3, Function 0
The PCI Express* Port A1 includes the registers listed in Table 7-16. These registers
materialize in PCI configuration space. See Section 16.4, “PCI Express* Port A
Standard and Enhanced Registers: Bus 0, Devices 2 and 3, Function 0” for detailed
discussion of these registers.
Table 7-16. Bus 0, Device 3, Function 0: Summary of PCI Express Port A1 Standard and
Enhanced PCI Configuration Registers (Sheet 1 of 3)
Offset Start
Offset End
Register ID - Description
Default
Value
00h
01h
“Offset 00h: VID - Vendor Identification Register” on page 527
8086h
02h
03h
“Offset 02h: DID - Device Identification Register” on page 528
5025h
04h
05h
“Offset 04h: PCICMD - PCI Command Register” on page 528
0000h
06h
07h
“Offset 06h: PCISTS - PCI Status Register” on page 530
0010h
08h
08h
“Offset 08h: RID - Revision Identification Register” on page 531
Variable
0Ah
0Ah
“Offset 0Ah: SUBC - Sub-Class Code Register” on page 532
04h
0Bh
0Bh
“Offset 0Bh: BCC - Base Class Code Register” on page 532
06h
0Ch
0Ch
“Offset 0Ch: CLS - Cache Line Size Register” on page 533
00h
0Eh
0Eh
“Offset 0Eh: HDR - Header Type Register” on page 533
01h
18h
18h
“Offset 18h: PBUSN - Primary Bus Number Register” on page 534
00h
19h
19h
“Offset 19h: SBUSN - Secondary Bus Number Register” on page 534
00h
1Ah
1Ah
“Offset 1Ah: SUBUSN: Subordinate Bus Number Register” on page 535
00h
1Ch
1Ch
“Offset 1Ch: IOBASE - I/O Base Address Register” on page 535
F0h
1Dh
1Dh
“Offset 1Dh: IOLIMIT - I/O Limit Address Register” on page 536
00h
1Eh
1Fh
“Offset 1Eh: SECSTS - Secondary Status Register” on page 536
0000h
20h
21h
“Offset 20h: MBASE - Memory Base Address Register” on page 538
FFF0h
22h
23h
“Offset 22h: MLIMIT - Memory Limit Address Register” on page 539
0000h
24h
25h
“Offset 24h: PMBASE - Prefetchable Memory Base Address Register” on page 540
FFF1h
26h
27h
“Offset 26h: PMLIMIT - Prefetchable Memory Limit Address Register” on page 540 0001h
28h
28h
“Offset 28h: PMBASU - Prefetchable Memory Base Upper Address Register” on
page 541
0Fh
2Ch
2Ch
“Offset 2Ch: PMLMTU - Prefetchable Memory Limit Upper Address Register” on
page 541
00h
34h
34h
“Offset 34h: CAPPTR - Capabilities Pointer Register” on page 542
50h
3Ch
3Ch
“Offset 3Ch: INTRLINE - Interrupt Line Register” on page 542
00h
3Dh
3Dh
“Offset 3Dh: INTRPIN - Interrupt Pin Register” on page 543
01h
3Eh
3Eh
“Offset 3Eh: BCTRL - Bridge Control Register” on page 543
00h
44h
44h
“Offset 44h: VSCMD0 - Vendor Specific Command Byte 0 Register” on page 545
00h
45h
45h
“Offset 45h: VSCMD1 - Vendor Specific Command Byte 1 Register” on page 546
00h
46h
46h
“Offset 46h: VSSTS0 - Vendor Specific Status Byte 0 Register” on page 547
00h
47h
47h
“Offset 47h: VSSTS1 - Vendor Specific Status Byte 1 Register” on page 547
00h
48h
48h
“Offset 48h: VSCMD2 - Vendor Specific Command Byte 2 Register” on page 548
00h
50h
50h
“Offset 50h: PMCAPID - Power Management Capabilities Structure Register” on
page 548
01h
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Table 7-16. Bus 0, Device 3, Function 0: Summary of PCI Express Port A1 Standard and
Enhanced PCI Configuration Registers (Sheet 2 of 3)
Offset Start
Offset End
Default
Value
Register ID - Description
51h
51h
“Offset 51h: PMNPTR - Power Management Next Capabilities Pointer Register” on
page 549
58h
52h
53h
“Offset 52h: PMCAPA - Power Management Capabilities Register” on page 549
C822h
54h
55h
“Offset 54h: PMCSR - Power Management Status and Control Register” on
page 550
0000h
56h
56h
“Offset 56h: PMCSRBSE - Power Management Status and Control Bridge
Extensions Register” on page 551
00h
58h
58h
“Offset 58h: MSICAPID - MSI Capabilities Structure Register” on page 551
05h
59h
59h
“Offset 59h: MSINPTR - MSI Next Capabilities Pointer Register” on page 552
64h
5Ah
5Bh
“Offset 5Ah: MSICAPA - MSI Capabilities Register” on page 553
0002h
5Ch
5Fh
“Offset 5Ch: MSIAR - MSI Address for PCI Express Register” on page 553
FEE00000h
60h
61h
“Offset 60h: MSIDR - MSI Data Register” on page 554
0000h
64h
64h
“Offset 64h: PEACAPID - PCI Express Features Capabilities ID Register” on
page 555
10h
65h
65h
“Offset 65h: PEANPTR - PCI Express Next Capabilities Pointer Register” on
page 556
00h
66h
67h
“Offset 66h: PEACAPA - PCI Express Features Capabilities Register” on page 556
0041h
68h
6Bh
“Offset 68h: PEADEVCAP - PCI Express Device Capabilities Register” on page 557
00000001h
6Ch
6Dh
“Offset 6Ch: PEADEVCTL - PCI Express Device Control Register” on page 558
0000h
6Eh
6Fh
“Offset 6Eh: PEADEVSTS - PCI Express Device Status Register” on page 560
0000h
70h
73h
“Offset 70h: PEA1LNKCAP - PCI Express Link Capabilities Register” on page 561
0303E441h
74h
75h
“Offset 74h: PEALNKCTL - PCI Express Link Control Register” on page 562
0001h
76h
77h
“Offset 76h: PEALNKSTS - PCI Express Link Status Register” on page 564
1001h
78h
7Bh
“Offset 78h: PEA1SLTCAP - PCI Express Slot Capabilities Register” on page 566
00000000h
7Ch
7Dh
“Offset 7Ch: PEASLTCTL - PCI Express Slot Control Register” on page 568
01C0h
7Eh
7Fh
“Offset 7Eh: PEASLTSTS - PCI Express Slot Status Register” on page 569
0040h
80h
83h
“Offset 80h: PEARPCTL - PCI Express Root Port Control Register” on page 570
00000000h
84h
87h
“Offset 84h: PEARPSTS - PCI Express Root Port Status Register” on page 571
00000000h
100h
103h
“Offset 100h: ENHCAPST - Enhanced Capability Structure Register” on page 571
00010001h
104h
107h
“Offset 104h: UNCERRSTS - Uncorrectable Error Status Register” on page 572
00000000h
108h
10Bh
“Offset 108h: UNCERRMSK - Uncorrectable Error Mask Register” on page 574
00000000h
10Ch
10Fh
“Offset 10Ch: UNCERRSEV - Uncorrectable Error Severity Register” on page 575
00062010h
110h
113h
“Offset 110h: CORERRSTS - Correctable Error Status Register” on page 576
00000000h
114h
117h
“Offset 114h: CORERRMSK - Correctable Error Mask Register” on page 578
00000000h
118h
11Bh
“Offset 118h: AERCACR - Advanced Error Capabilities and Control Register” on
page 579
00000000h
11Ch
11Fh
“Offset 11Ch: HDRLOG0 - Header Log DW 0 (1st 32 bits) Register” on page 580
00000000h
120h
123h
“Offset 120h: HDRLOG1 - Header Log DW 1 (2nd 32 bits) Register” on page 580
00000000h
124h
127h
“Offset 124h: HDRLOG2 - Header Log DW 2 (3rd 32 bits) Register” on page 581
00000000h
128h
12Bh
“Offset 128h: HDRLOG3 - Header Log DW 3 (4th 32 bits) Register” on page 581
00000000h
12Ch
12Fh
“Offset 12Ch: RPERRCMD - Root (Port) Error Command Register” on page 582
00000000h
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Intel® EP80579 Integrated Processor
Table 7-16. Bus 0, Device 3, Function 0: Summary of PCI Express Port A1 Standard and
Enhanced PCI Configuration Registers (Sheet 3 of 3)
Offset Start
130h
Offset End
133h
Register ID - Description
“Offset 130h: RPERRMSTS - Root (Port) Error Message Status Register” on
page 583
Default
Value
00000000h
134h
137h
“Offset 134h: ERRSID - Error Source ID Register” on page 585
00000000h
140h
143h
“Offset 140h: PEAUNITERR - PCI Express Unit Error Register” on page 586
00000000h
144h
147h
“Offset 144h: PEAMASKERR - PCI Express Unit Mask Error Register” on page 588
0000E000h
148h
14Bh
“Offset 148h: PEAERRDOCMD - PCI Express Error Do Command Register” on
page 589
00000000h
14Ch
14Fh
“Offset 14Ch: UNCEDMASK - Uncorrectable Error Detect Mask Register” on
page 591
00000000h
150h
153h
“Offset 150h: COREDMASK - Correctable Error Detect Mask Register” on page 592 00000000h
158h
15Bh
“Offset 158h: PEAUNITEDMASK - PCI Express Unit Error Detect Mask Register” on
00000000h
page 594
160h
163h
“Offset 160h: PEAFERR - PCI Express First Error Register” on page 595
00000000h
164h
167h
“Offset 164h: PEANERR - PCI Express Next Error Register” on page 597
00000000h
168h
16Bh
“Offset 168h: PEAERRINJCTL - Error Injection Control Register” on page 597
00000000h
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Intel® EP80579 Integrated Processor
7.3.6
USB (1.1) Controller: Bus 0, Device 29, Functions 0
The USB 1.1 controller includes the registers listed in Table 7-17 and Table 7-18. These
registers materialize in PCI configuration and I/O spaces (via PCI I/O BAR),
respectively. See Chapter 25.0, “USB (1.1) Controller: Bus 0, Device 29, Function 0”
for detailed discussion of these registers.
Table 7-17. Bus 0, Device 29, Functions 0, Summary of USB (1.1) Controller PCI
Configuration Registers
Offset Start
Offset End
Default
Value
Register ID - Description
00h
03h
“ID - Identifiers Register” on page 942
50338086h
04h
05h
“PCICMD - Command Register” on page 942
0000h
06h
07h
“PCISTS - Device Status Register” on page 943
0280h
08h
08h
“RID - Revision ID Register” on page 944
Variable
0Ah
0Ah
“SUBC - Sub Class Code Register” on page 945
03h
0Bh
0Bh
“BCC - Base Class Code Register” on page 945
0Ch
0Dh
0Dh
“MLT - Master Latency Timer Register” on page 945
00h
0Eh
0Eh
“HDR - Header Type Register” on page 946
Variable
20h
23h
“USBIOBAR - Base Address Register” on page 946
00000001h
2Ch
2Dh
“USBx_SVID - USB Subsystem Vendor ID Register” on page 947
0000h
2Eh
2Fh
“USBx_SID - USB Subsystem ID Register” on page 947
0000h
3Ch
3Ch
“INTL - Interrupt Line Register” on page 948
00h
3Dh
3Dh
“INTP - Interrupt Pin Register” on page 948
Variable
60h
60h
“SBRN - Serial Bus Release Number Register” on page 948
10h
C0h
C1h
“USBLKMCR - USB Legacy Keyboard/Mouse Control Register” on page 949
2000h
C4h
C4h
“USBREN - USB Resume Enable Register” on page 951
00h
C8h
C8h
“USBCWP - USB Core Well Policy Register” on page 951
00h
F8h
FBh
“MANID - Manufacturer ID Register” on page 952
00010F90h
Table 7-18. Summary of USB (1.1) Controller Configuration Registers Mapped Through
USBIOBAR I/O BAR
Offset Start
Offset End
Register ID - Description
Default
Value
00h
01h
“USBCMD: USB Command Register” on page 954
0000h
02h
03h
“USBSTS: USB Status Register” on page 957
0020h
04h
05h
“USBINTR: USB Interrupt Enable Register” on page 959
0000h
06h
07h
“FRNUM: Frame Number Register” on page 959
0000h
08h
0Bh
“FRBASEADD: Frame List Base Address Register” on page 960
XXXXX000h
0Ch
0Ch
“SOFMOD: Start of Frame Modify Register” on page 961
40h
10h
11h
“PSCR - Port Status and Control Register” on page 962
0080h
12h
13h
“PSCR - Port Status and Control Register” on page 962
0080h
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7.3.7
USB (2.0) Controller: Bus 0, Device 29, Function 7
The USB 2.0 controller includes the registers listed in Table 7-19 and Table 7-20. These
registers materialize in PCI configuration and I/O spaces (via PCI I/O BAR),
respectively. See Chapter 26.0, “USB 2.0 PCI Configuration Registers” for detailed
discussion of these registers.
Table 7-19. Bus 0, Device 29, Function 7: Summary of USB (2.0) Controller PCI
Configuration Registers
Offset Start
Offset End
Register ID - Description
Default
Value
00h
01h
“Offset 00h: VID - Vendor ID Register” on page 979
8086h
02h
03h
“Offset 02h: DID - Device Identification Register” on page 979
5035h
04h
05h
“Offset 04h: CMD - Command Register” on page 980
0000h
06h
07h
“Offset 06h: DSR - Device Status Register” on page 981
0290h
08h
08h
“Offset 08h: RID - Revision ID Register” on page 983
Variable
09h
09h
“Offset 09h: PI - Programming Interface Register” on page 983
20h
0Ah
0Ah
“Offset 0Ah: SCC - Sub Class Code Register” on page 983
03h
0Bh
0Bh
“Offset 0Bh: BCC - Base Class Code Register” on page 984
0Ch
0Dh
0Dh
“Offset 0Dh: MLT - Master Latency Timer Register” on page 984
00h
10h
13h
“Offset 10h: MBAR - Memory Base Address Register” on page 985
00000000h
2Ch
2Dh
“Offset 2Ch: SSVID - USB 2.0 Subsystem Vendor ID Register” on page 985
XXXXh
2Eh
2Fh
“Offset 2Eh: SSID - USB 2.0 Subsystem ID Register” on page 986
XXXXh
34h
34h
“Offset 34h: CAP_PTR - Capabilities Pointer Register” on page 986
50h
3Ch
3Ch
“Offset 3Ch: ILINE - Interrupt Line Register” on page 987
00h
Variable
3Dh
3Dh
“Offset 3Dh: IPIN - Interrupt Pin Register” on page 987
50h
50h
“Offset 50h: PM_CID - PCI Power Management Capability ID Register” on page 987 01h
51h
51h
“Offset 51h: PM_NEXT - Next Item Pointer #1 Register” on page 988
58h
52h
53h
“Offset 52h: PM_CAP - Power Management Capabilities Register” on page 989
C9C2h
54h
55h
“Offset 54h: PM_CS - Power Management Control/Status Register” on page 990
0000h
58h
58h
“Offset 58h: DP_CID - Debug Port Capability ID Register” on page 991
0Ah
59h
59h
“Offset 59h: DP_NEXT - Next Item Pointer #2 Register” on page 991
00h
5Ah
5Bh
“Offset 5Ah: DP_BASE - Debug Port Base Offset Register” on page 991
20A0h
60h
60h
“Offset 60h: SBRN - Serial Bus Release Number Register” on page 992
20h
61h
61h
“Offset 61h: FLA - Frame Length Adjustment Register” on page 992
20h
62h
63h
“Offset 62h: PWC - Port Wake Capability Register” on page 993
01FFh
64h
65h
“Offset 64h: CUO - Classic USB Override Register” on page 994
0000h
68h
6Bh
“Offset 68h: ULSEC - USB 2.0 Legacy Support Extended Capability Register” on
page 994
00000001h
6Ch
6Fh
“Offset 6Ch: ULSCS - USB 2.0 Legacy Support Control/Status Register” on
page 995
00000000h
70h
73h
“Offset 70h: ISU2SMI - Intel Specific USB 2.0 SMI Register” on page 997
00000000h
80h
80h
“Offset 80h: AC - Access Control Register” on page 999
00h
F8h
FBh
“Offset F8h: MANID - Manufacturer ID Register” on page 1000
00010F90h
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Intel® EP80579 Integrated Processor
Table 7-20. Bus 0, Device 29, Function 7: Summary of USB (2.0) Controller Configuration
Registers Mapped Through MBAR Memory BAR
Offset Start
Offset End
Default
Value
Register ID - Description
00h
00h
“Offset 00h: CAPLENGTH - Capability Length Register” on page 1002
02h
03h
“Offset 02h: HCIVERSION - Host Controller Interface Version Number Register” on
0100h
page 1003
04h
07h
“Offset 04h: HCSPARAMS - Host Controller Structural Parameters Register” on
page 1003
01001202h
08h
0Bh
“Offset 08h: HCCPARAMS - Host Controller Capability Parameters Register” on
page 1004
00006871h
20h
23h
“Offset 20h: USB2CMD - USB 2.0 Command Register” on page 1007
00080000h
24h
27h
“Offset 24h: USB2STS - USB 2.0 Status Register” on page 1009
00001000h
28h
2Bh
“Offset 28h: USB2INTR - USB 2.0 Interrupt Enable Register” on page 1012
00000000h
2Ch
2Fh
“Offset 2Ch: FRINDEX - Frame Index Register” on page 1013
00000000h
30h
33h
“Offset 30h: CTRLDSSEGMENT - Control Data Structure Segment Register” on
page 1014
00000000h
34h
37h
“Offset 34h: PERIODICLISTBASE - Periodic Frame List Base Address Register” on
page 1014
00000XXXh
38h
3Bh
“Offset 38h: ASYNCLISTADDR - Current Asynchronous List Address Register” on
page 1015
00000000h
60h
63h
“Offset 60h: CONFIGFLAG - Configure Flag Register” on page 1015
00000000h
64h
67h
“Offset 64h: PORTSC - Port N Status and Control Register” on page 1016
00003000h
68h
6Bh
“Offset 64h: PORTSC - Port N Status and Control Register” on page 1016
00003000h
A0h
A3h
“Offset A0h: CNTL_STS - Control/Status Register” on page 1037
00000000h
A4h
A4h
“Offset A4h: USBPID - USB PIDs Register” on page 1039
00000000h
A8h
AFh
“Offset A8h: DATABUF - Data Buffer Bytes 7:0” on page 1039
00000000000
00000h
B0h
B0h
“Offset B0h: CONFIG - Configuration Register” on page 1040
00007F01h
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Intel® EP80579 Integrated Processor
7.3.8
Root Complex: Bus 0, Device 31, Function 0
The Root Complex includes the registers listed in Table 7-21. These registers
materialize in memory space (via PCI memory BAR), respectively. See Chapter 17.0,
“Bridging and Configuration” for detailed discussion of these registers.
Table 7-21. Bus 0, Device 31, Function 0: Summary of Root Complex Configuration
Registers Mapped Through RCBA Memory BAR
Offset Start
Offset End
Default
Value
Register ID - Description
0000h
0003h
“Offset 0000h: VCH - Virtual Channel Capability Header Register” on page 691
10010002h
0004h
0007h
“Offset 0004h: VCAP1 - Virtual Channel Capability 1 Register” on page 691
0801h
0008h
000Bh
“Offset 0008h: VCAP2 - Virtual Channel Capability 2 Register” on page 692
0001h
000Ch
000Dh
“Offset 000Ch: PVC - Port Virtual Channel Control Register” on page 692
0h
000Eh
000Fh
“Offset 000Eh: PVS -Port Virtual Channel Status Register” on page 693
0h
0010h
0013h
“Offset 0010h: V0CAP - Virtual Channel 0 Resource Capability Register” on
page 693
00000001h
0014h
0017h
“Offset 0014h: V0CTL - Virtual Channel 0 Resource Control Register” on page 694 800000FFh
001Ah
001Bh
“Offset 001Ah: V0STS - Virtual Channel 0 Resource Status Register” on page 695
0h
0103h
“Offset 0100h: RCTCL - Root Complex Topology Capabilities List Register” on
page 696
1A010005h
0100h
0104h
0107h
“Offset 0104h: ESD - Element Self Description Register” on page 696
00000102h
0110h
0113h
“Offset 0110h: ULD - Upstream Link Description Register” on page 697
0001h
0118h
011Fh
“Offset 0118h: ULBA - Upstream Link Base Address Register” on page 697
00000000000
00000h
01A0h
01A3h
“Offset 01A0h: ILCL - Internal Link Capabilities List Register” on page 698
00010006h
01A4h
01A7h
“Offset 01A4h: LCAP - Link Capabilities Register” on page 698
0012441h
01A8h
01A9h
“Offset 01A8h: LCTL - Link Control Register” on page 699
0h
01AAh
01ABh
“Offset 01AAh: LSTS - Link Status Register” on page 700
0041h
3108h
310Bh
“Offset 3108h: D29IP - Device 29 Interrupt Pin Register” on page 702
10004321h
3140h
3141h
“Offset 3140h: D31IR - Device 31 Interrupt Route Register” on page 702
3210h
3144h
3145h
“Offset 3144h: D29IR - Device 29 Interrupt Route Register” on page 703
3210h
31FFh
31FFh
“Offset 31FFh: OIC - Other Interrupt Control Register” on page 704
0h
3400h
3403h
“Offset 3400h: RC - RTC Configuration Register” on page 704
0h
3404h
3407h
“Offset 3404h: HPTC - High Performance Precision Timer Configuration Register”
on page 705
0h
3410h
3413h
“Offset 3410h: GCS - General Control and Status Register” on page 706
Variable
3414h
3417h
“Offset 3414h: BUC - Backed Up Control Register” on page 708
Variable
3418h
341Bh
“Offset 3418h: FD - Function Disable Register” on page 709
00000080h
341Ch
341Fh
“Offset 341Ch: PRC - Power Reduction Control Register Clock Gating” on page 711 0h
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7.3.9
LPC Interface: Bus 0, Device 31, Function 0
The LPC interface includes the registers listed in Table 7-22 through Table 7-26. These
registers materialize in PCI configuration and I/O spaces (via PCI I/O BAR). See
Chapter 19.0, “LPC Interface: Bus 0, Device 31, Function 0”, Chapter 27.0, “Power
Management”, Chapter 18.0, “System Management”, and Chapter 22.0, “General
Purpose I/O: Bus 0, Device 31, Function 0” for detailed discussion of these registers.
Table 7-22. Bus 0, Device 31, Function 0: Summary of LPC Interface PCI Configuration
Registers
Offset Start
Offset End
Default
Value
Register ID - Description
00h
03h
“Offset 00h: ID: Vendor Identification Register” on page 734
50318086h
04h
05h
“Offset 04h: CMD: Device Command Register” on page 735
0007h
06h
07h
“Offset 06h: STS: Status Register” on page 736
0200h
08h
08h
“Offset 08h: RID: Revision ID Register” on page 737
Variable
09h
0Bh
“Offset 09h: CC: Class Code Register” on page 737
060100h
0Dh
0Dh
“Offset 0Dh: MLT: Master Latency Timer Register” on page 737
00h
0Eh
0Eh
“Offset 0Eh: HTYPE: Header Type Register” on page 738
80H
2Ch
2Fh
“Offset 2Ch: SID: Subsystem Identifiers Register” on page 738
00000000h
40h
43h
“Offset 40h: ABASE: ACPI Base Address Register” on page 739
00000001h
44h
47h
“Offset 44h: ACTL: ACPI Control Register” on page 739
00h
48h
48h
“Offset 48h: GBA: GPIO Base Address Register” on page 740
00000001h
4Ch
4Ch
“Offset 4Ch: GC: GPIO Control Register” on page 741
00h
60h
60h
“Offset 60h: PARC: PIRQA Routing Control Register” on page 741
80h
61h
61h
“Offset 61h: PBRC: PIRQB Routing Control Register” on page 742
80h
62h
62h
“Offset 62h: PCRC: PIRQC Routing Control Register” on page 742
80h
63h
63h
“Offset 63h: PDRC: PIRQDQ Routing Control Register” on page 743
80h
64h
64h
“Offset 64h: SCNT: Serial IRQ Control Register” on page 744
10h
68h
68h
“Offset 68h: PERC: PIRQEQ Routing Control Register” on page 745
80h
69h
69h
“Offset 69h: PFRC: PIRQF Routing Control Register” on page 745
80h
6Ah
6Ah
“Offset 6Ah: PGRC: PIRQG Routing Control Register” on page 746
80h
6Bh
6Bh
“Offset 6Bh: PHRC: PIRQH Routing Control Register” on page 747
80h
80h
81h
“Offset 80h: IOD: I/O Decode Ranges Register” on page 747
0000h
82h
83h
“Offset 82h: IOE: I/O Enables Register” on page 749
0000h
84h
85h
“Offset 84h: LG1: LPC Generic Decode Range 1 Register” on page 750
0000h
88h
88h
“Offset 88h: LG2: LPC Generic Decode Range 2 Register” on page 751
0000h
D0h
D3h
“Offset D0h: FS1: FWH ID Select 1 Register” on page 752
00112233h
D4h
D5h
“Offset D4h: FS2: FWH ID Select 2 Register” on page 753
4567h
D8h
DBh
“Offset D8h: FDE: FWH Decode Enable Register” on page 754
FFCFh
DCh
DCh
“Offset DCh: BC: BIOS Control Register” on page 756
00h
F0h
F3h
“Offset F0h: RCBA: Root Complex Base Address Register” on page 757
00000000h
F8h
FBh
“Offset F8h: MANID: Manufacturer ID Register” on page 757
00010F90h
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Table 7-23. Bus 0, Device 31, Function 0: Summary of LPC Interface Power Management
PCI Configuration Registers
Offset Start
A0h
Offset End
A0h
Register ID - Description
Default
Value
“Offset A0h: GEN_PMCON_1 - General PM Configuration 1 Register” on page 1048 0200h
A2h
A2h
“Offset A2h: GEN_PMCON_2 - General PM Configuration 2 Register” on page 1049 00h
A4h
A4h
“Offset A4h: GEN_PMCON_3 - General PM Configuration 3 Register” on page 1051 00h
B8h
BBh
“Offset B8h: GPI_ROUT - GPI Routing Control Register” on page 1053
00000000h
Table 7-24. Bus 0, Device 31, Function 0: Summary of TCO Configuration Registers
Mapped Through TCOBASE I/O BAR“
Offset Start
00h
Offset End
01h
Register ID - Description
“Offset 00h: TRLD - TCO Timer Reload and Current Value Register” on page 715
Default
Value
0000h
02h
02h
“Offset 02h: TDI - TCO Data In Register” on page 715
00h
03h
03h
“Offset 03h: TDO - TCO Data Out Register” on page 716
00h
04h
04h
“Offset 04h: TSTS1 - TCO 1 Status Register” on page 716
0000h
06h
07h
“Offset 06h: TSTS2 - TCO 2 STS Register” on page 718
0000h
08h
09h
“Offset 08h: TCTL1 - TCO 1 Control Register” on page 720
0000h
0Ah
0Bh
“Offset 0Ah: TCTL2 - TCO 2 Control Register” on page 721
0008h
0Ch at 01h
0Ch at 01h
“Offset 0Ch: TMSG[1-2] - TCO MESSAGE Register” on page 721
00h
0Eh
0Eh
“Offset 0Eh: TWDS - TCO Watchdog Status Register” on page 722
00h
10h
10h
“Offset 10h: LE - Legacy Elimination Register” on page 722
03h
12h
13h
“Offset 12h: TTMR - TCO Timer Initial Value Register” on page 723
0004h
Table 7-25. Bus 0, Device 31, Function 0: Summary of LPC Interface Power Management
General Configuration Registers Mapped Through PMBASE I/O BAR (Sheet 1
of 2)
Offset Start
Offset End
Register ID - Description
Default
Value
00h
00h
“Offset 00h: PM1_STS – Power Management 1 Status Register” on page 1056
0000h
02h
02h
“Offset 02h: PM1_EN - Power Management 1 Enables Register” on page 1058
0000h
04h
04h
“Offset 04h: PM1_CNT - Power Management 1 Control Register” on page 1059
0000h
08h
B8h
“Offset 08h: PM1_TMR - Power Management 1 Timer Register” on page 1060
00000000h
10h
10h
“Offset 10h: PROC_CNT - Processor Control Register” on page 1060
00000000h
14h
14h
“Offset 14h: LV2 - Level 2 Register” on page 1063
00h
28h
28h
“Offset 28h: GPE0_STS - General Purpose Event 0 Status Register” on page 1063
00000000h
2Ch
“Offset 2Ch: PMBASE_GPE0_EN - General Purpose Event 0 Enables Register” on
page 1067
00000000h
2Ch
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Table 7-25. Bus 0, Device 31, Function 0: Summary of LPC Interface Power Management
General Configuration Registers Mapped Through PMBASE I/O BAR (Sheet 2
of 2)
Offset Start
Offset End
Default
Value
Register ID - Description
30h
30h
“Offset 30h: SMI_EN - SMI Control and Enable Register” on page 1068
00000000h
34h
34h
“Offset 34h: SMI_STS - SMI Status Register” on page 1071
00000000h
38h
38h
“Offset 38h: ALT_GPI_SMI_EN - Alternate GPI SMI Enable Register” on page 1073 0000h
3Ah
3Ah
“Offset 3Ah: ALT_GPI_SMI_STS - Alternate GPI SMI Status Register” on page 1074 0000h
44h
44h
“Offset 44h: DEVTRAP_STS - DEVTRAP_STS Register” on page 1074
0000h
Table 7-26. Bus 0, Device 31, Function 0: Summary of General Purpose I/O Configuration
Registers Mapped Through GBA BAR IO BAR
Offset Start
00h
Offset End
Default
Value
Register ID - Description
03h
“Offset 00h: GPIO_USE_SEL1 - GPIO Use Select 1 {31:0} Register” on page 807
Variable
04h
07h
“Offset 04h: GP_IO_SEL1 - GPIO Input/Output Select 1 {31:0} Register” on
page 808
E400FFFFh
0Ch
0Fh
“Offset 0Ch: GP_LVL1 - GPIO Level 1 for Input or Output {31:0} Register” on
page 809
FF3F0000h
18h
1Bh
“Offset 18h: GPO_BLINK - GPIO Blink Enable Register” on page 810
00040000h
2Ch
2Fh
“Offset 2Ch: GPI_INV - GPIO Signal Invert Register” on page 812
00000000h
30h
33h
“Offset 30h: GPIO_USE_SEL2 - GPIO Use Select 2 {63:32} Register” on page 813 Variable
34h
37h
“Offset 34h: GP_IO_SEL2 - GPIO Input/Output Select 2 {63:32} Register” on
page 813
00000300h
38h
3Bh
“Offset 38h: GP_LVL2 - GPIO Level for Input or Output 2 {63:32} Register” on
page 814
00030207h
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Intel® EP80579 Integrated Processor
7.3.10
SATA Controller: Bus 0, Device 31, Function 2
The SATA controller includes the registers listed in Table 7-27, Table 7-28, and
Table 7-29. These registers materialize in PCI configuration, I/O, and memory spaces
(via PCI I/O and memory BARs). See Chapter 23.0, “SATA: Bus 0, Device 31, Function
2” for detailed discussion of these registers.
Table 7-27. Bus 0, Device 31, Function 2: Summary of SATA Controller PCI Configuration
Registers (Sheet 1 of 2)
Offset Start
Offset End
Register ID - Description
Default
Value
00h
03h
“Offset 00h: ID – Identifiers Register” on page 819
Variable
04h
05h
“Offset 04h: CMD - Command Register” on page 819
0000h
06h
07h
“Offset 06h: STS - Device Status Register” on page 820
02B0h
08h
08h
“Offset 08h: RID - Revision ID Register” on page 821
Variable
0Ah
0Bh
“Offset 0Ah: CC - Class Code Register” on page 823
Variable
0Dh
0Dh
“Offset 0Dh: MLT – Master Latency Timer Register” on page 823
00h
10h
13h
“Offset 10h: PCMDBA – Primary Command Block Base Address Register” on
page 824
00000001h
14h
17h
“Offset 14h: PCTLBA – Primary Control Block Base Address Register” on page 824 00000001h
18h
1Bh
“Offset 18h: SCMDBA – Secondary Command Block Base Address Register” on
page 825
00000001h
1Ch
1Fh
“Offset 1Ch: SCTLBA – Secondary Control Block Base Address Register” on
page 825
00000001h
20h
23h
“Offset 20h: LBAR – Legacy Bus Master Base Address Register when SCC is SATA
with AHCI PI” on page 826
00000001h
24h
27h
“Offset 24h: ABAR – AHCI Base Address Register” on page 826
00000000h
2Ch
2Fh
“Offset 2Ch: SS - Sub System Identifiers Register” on page 827
00000000h
34h
34h
“Offset 34h: CAP – Capabilities Pointer Register” on page 827
80h
3Ch
3Dh
“Offset 3Ch: INTR - Interrupt Information Register” on page 828
Variable
40h
41h
“Offset 40h: PTIM – Primary Timing Register” on page 829
0000h
44h
44h
“Offset 44h: D1TIM – Device 1 IDE Timing Register” on page 830
00h
48h
48h
“Offset 48h: SYNCC – Synchronous DMA Control Register” on page 831
00h
4Ah
4Bh
“Offset 4Ah: SYNCTIM – Synchronous DMA Timing Register” on page 832
0000h
54h
57h
“Offset 54h: IIOC – IDE I/O Configuration Register” on page 833
00000000h
70h
71h
“Offset 70h: PID – PCI Power Management Capability ID Register” on page 834
Variable
72h
73h
“Offset 72h: PC – PCI Power Management Capabilities Register” on page 834
4002h
74h
77h
“Offset 74h: PMCS – PCI Power Management Control And Status Register” on
page 835
0000h
80h
81h
“Offset 80h: MID – Message Signaled Interrupt Identifiers Register” on page 836
7005h
82h
83h
“Offset 82h: MC – Message Signaled Interrupt Message Control Register” on
page 837
0000h
84h
87h
“Offset 84h: MA – Message Signaled Interrupt Message Address Register” on
page 838
00000000h
88h
89h
“Offset 88h: MD – Message Signaled Interrupt Message Data Register” on
page 838
0000h
90h
90h
“Offset 90h: MAP – Port Mapping Register” on page 839
00h
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Table 7-27. Bus 0, Device 31, Function 2: Summary of SATA Controller PCI Configuration
Registers (Sheet 2 of 2)
Offset Start
92h
Offset End
Default
Value
Register ID - Description
92h
“Offset 92h: PCS – Port Control and Status Register” on page 840
00h
A8h
ABh
“Offset A8h: SATACR0 – Serial ATA Capability Register 0” on page 841
00100012h
ACh
AFh
“Offset ACh: SATACR1 – Serial ATA Capability Register 1” on page 841
00000048h
C0h
C0h
“Offset C0h: ATC – APM Trapping Control Register” on page 842
00h
C4h
C4h
“Offset C4h: ATS – ATM Trapping Status Register” on page 843
00h
D0h
D3h
“Offset D0h: SP – Scratch Pad Register” on page 844
00000000h
E0h
E3h
“Offset E0h: BFCS – BIST FIS Control/Status Register” on page 844
00000000h
E4h
E7h
“Offset E4h: BFTD1 – BIST FIS Transmit Data 1 Register” on page 846
00000000h
E8h
EBh
“Offset E8h: BFTD2 – BIST FIS Transmit Data 2 Register” on page 846
0h
F8h
FBh
“Offset F8h: MANID – Manufacturing ID Register” on page 847
Variable
Table 7-28. Bus 0, Device 31, Function 2: Summary of SATA Controller Configuration
Registers Mapped Through LBAR I/O BAR
Offset Start
Offset End
Default
Value
Register ID - Description
00h
00h
“Offset 00h: PCMD – Primary Command Register” on page 848
00h
02h
02h
“Offset 02h: PSTS – Primary Status Register” on page 849
00h
04h
07h
“Offset 04h: PDTP – Primary Descriptor Table Pointer Register” on page 849
Variable
10h
13h
“Offset 10h: INDEX – AHCI Index Register” on page 850
00000000h
14h
17h
“Offset 14h: DATA – AHCI Data Register” on page 851
Variable
Table 7-29. Bus 0, Device 31, Function 2: Summary of SATA Controller Configuration
Registers Mapped Through ABAR Memory BAR (Sheet 1 of 2)
Offset Start
Offset End
Default
Value
Register ID - Description
00h
03h
“Offset 00h: HCAP – HBA Capabilities Register” on page 853
Variable
04h
07h
“Offset 04h: GHC – Global HBA Control Register” on page 855
00000000h
08h
0Bh
“Offset 08h: IS – Interrupt Status Register” on page 856
00000000h
0Ch
0Fh
“Offset 0Ch: PI – Ports Implemented Register” on page 856
00000000h
10h
13h
“Offset 10h: VS – AHCI Version Register” on page 857
00010100h
A0h
A3h
“Offset A0h: SGPO -SPGIO Control Register” on page 857
00000000h
100h, 180h
17Fh, 1FFh
“Offset 100h: PxCLB[0-1] – Port [0-1] Command List Base Address Register” on
page 858
Variable
104h, 184h
107h, 187h
“Offset 104h: PxCLBU[0-1] – Port [0-1] Command List Base Address Register” on
page 858
Variable
108h, 188h
10Bh, 18Bh
“Offset 108h: PxFB[0-1] – Port [0-1] FIS Base Address Register” on page 859
Variable
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Table 7-29. Bus 0, Device 31, Function 2: Summary of SATA Controller Configuration
Registers Mapped Through ABAR Memory BAR (Sheet 2 of 2)
Offset Start
10Ch, 18Ch
Offset End
10Fh, 18Fh
Register ID - Description
“Offset 10Ch: PxFBU[0-1] – Port [0-1] FIS Base Address Upper 32-bits Register”
on page 859
Default
Value
Variable
110h, 190h
113h, 193h
“Offset 110h: PxIS[0-1] – Port [0-1] Interrupt Status Register” on page 860
00000000h
114h, 194h
117h, 197h
“Offset 114h: PxIE[0-1] – Port [0-1] Interrupt Enable Register” on page 861
00000000h
118h, 198h
11Bh, 19Bh
“Offset 118h: PxCMD[0-1] – Port [0-1] Command Register” on page 863
Variable
120h, 1A0h
123h, 1A3h
“Offset 120h: PxTFD[0-1] – Port [0-1] Task File Data Register” on page 866
0000007Fh
124h, 1A4h
127h, 1A7h
“Offset 124h: PxSIG[0-1] – Port [0-1] Signature Register” on page 867
FFFFFFFFh
128h, 1A8h
12Bh, 1ABh
“Offset 128h: PxSSTS[0-1] – Port [0-1] Serial ATA Status Register” on page 868
Variable
12Ch, 1ACh
12Fh, 1AFh
“Offset 12Ch: PxSCTL[0-1] – Port [0-1] Serial ATA Control Register” on page 869
00000000h
130h, 1B0h
133h, 1B3h
“Offset 130h: PxSERR[0-1] – Port [0-1] Serial ATA Error Register” on page 870
00000000h
134h, 1B4h
137h, 1B7h
“Offset 134h: PxSACT[0-1] – Port [0-1] Serial ATA Active Register” on page 872
00000000h
138h, 1B8h
13Bh, 1BBh
“Offset 138h: PxCI[0-1] – Port [0-1] Command Issue Register” on page 872
00000000h
13Ch, 1BCh
13Fh, 1BFh
“Offset 13Ch: PxSNTF[0-1] – Port [0-1] SNotification Register” on page 873
00000000h
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7.3.11
SMBus Controller: Bus 0, Device 31, Function 3
The SMBus controller includes the registers listed in Table 7-30 and Table 7-31. These
registers materialize in PCI configuration and I/O spaces (via PCI I/O BAR),
respectively. See Chapter 24.0, “SMBus Controller Functional Description: Bus 0,
Device 31, Function 3” for detailed discussion of these registers.
Table 7-30. Bus 0, Device 31, Function 3: Summary of SMBus Controller PCI Configuration
Registers
Offset Start
Offset End
Register ID - Description
Default
Value
00h
01h
“Offset 00h: VID: Vendor ID Register” on page 897
8086h
02h
03h
“Offset 02h: DID: Device ID Register” on page 897
5032h
04h
05h
“Offset 04h: CMD: Command Register” on page 897
0000h
06h
07h
“Offset 06h: DS – Device Status Register” on page 898
0280h
08h
08h
“Offset 08h: RID: Revision ID Register” on page 899
Variable
09h
09h
“Offset 09h: PI: Programming Interface Register” on page 900
00h
0Ah
0Ah
“Offset 0Ah: SCC: Sub Class Code Register” on page 900
05h
0Bh
0Bh
“Offset 0Bh: BCC: Base Class Code Register” on page 900
0Ch
20h
23h
“Offset 20h: SM_BASE: SMB Base Address Register” on page 901
00000001h
2Ch
2Dh
“Offset 2Ch: SVID: SVID Register” on page 901
0000h
2Eh
2Fh
“Offset 2Eh: SID: Subsystem Identification Register” on page 902
0000h
3Ch
3Ch
“Offset 3Ch: INTLN: Interrupt Line Register” on page 902
00h
3Dh
3Dh
“Offset 3Dh: NTPN: Interrupt Pin Register” on page 903
Variable
40h
40h
“Offset 40h: HCFG: Host Configuration Register” on page 903
00h
F8h
FBh
“Offset F8h: MANID: Manufacturer ID Register” on page 904
00010F90h
Table 7-31. Bus 0, Device 31, Function 3: Summary of SMBus Controller Configuration
Registers Mapped Through SM_BASE I/O BAR
Offset Start
Offset End
Register ID - Description
Default
Value
00h
00h
“Offset 00h: HSTS: Host Status Register” on page 906
00h
02h
02h
“Offset 02h: HCTL: Host Control Register” on page 908
00h
03h
03h
“Offset 03h: HCMD: Host Command Register” on page 912
00h
04h
04h
“Offset 04h: TSA: Transmit Slave Address Register” on page 912
00h
05h
05h
“Offset 05h: HD0: Data 0 Register” on page 913
00h
06h
06h
“Offset 06h: HD1: Data 1 Register” on page 913
00h
07h
07h
“Offset 07h: HBD: Host Block Data Register” on page 914
00h
08h
08h
“Offset 08h: PEC: Packet Error Check Data Register” on page 915
00h
0Ch
0Ch
“Offset 0Ch: AUXS: Auxiliary Status Register” on page 915
00h
0Dh
0Dh
“Offset 0Dh: AUXC: Auxiliary Control Register” on page 916
00h
0Eh
0Eh
“Offset 0Eh: SMLC: SMLINK_PIN_CTL Register” on page 916
07h
0Fh
0Fh
“Offset 0Fh: SMBC: SMBUS_PIN_CTL Register” on page 917
07h
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7.3.12
IA-32 Core Interface I/O-Mapped Register
Table 7-32. Summary of IA-32 Core Interface Registers Mapped in I/O Space
Offset Start
Offset End
Default
Value
Register ID - Description
61h
61h
“Offset 61h: NMI_STS_CNT - NMI Status and Control Register” on page 1098
00h
70h
70h
“Offset 70h: NMI_EN - NMI Enable (and Real Time Clock Index) Register” on
page 1099
80h
92h
92h
“Offset 92h: PORT92 - Fast A20 and Init Register” on page 1100
00h
F0h
F0h
“Offset F0h: COPROC_ERR - Coprocessor Error Register” on page 1100
00h
CF9h
CF9h
“Offset CF9h: RST_CNT - Reset Control Register” on page 1101
00h
7.3.13
IMCH PCI Configuration
The PCI configuration interface includes the registers listed in Table 7-33. These
registers materialize at fixed locations in I/O space.
Table 7-33. Summary of IMCH PCI Configuration Registers Mapped in I/O Space
Offset Start
Offset End
Register ID - Description
Default
Value
0CF8h
0CF8h
“Offset 0CF8h: CONFIG_ADDRESS: Configuration Address Register” on page 354
00000000h
0CFCh
0CFCh
“Offset 0CFCh: CONFIG_DATA: Configuration Data Register” on page 355
00000000h
7.3.14
APIC
The APIC includes the registers listed in Table 7-34 and Table 7-35 These registers
materialize at fixed locations in memory space and are indexed, respectively. See
Chapter 30.0 for detailed discussion of these registers.
Table 7-34. Summary of APIC Registers Mapped in Memory Space“
Offset Start
Offset End
Register ID - Description
Default
Value
0000h (4B)
0000h (4B)
“APIC_IDX - Index Register” on page 1135
00h
0010h (4B)
0010h (4B)
“APIC_DAT – Data Register” on page 1136
00h
0040h (4B)
0040h (4B)
“APIC_EOI - EOI Register” on page 1136
00h
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Table 7-35. Summary of APIC Indexed Registers
Offset Start
Offset End
Register ID - Description
Default
Value
00h (4B)
00h (4B)
“APIC_ID – Identification Register” on page 1138
0000h
01h (4B)
01h (4B)
“APIC_VS - Version Register” on page 1138
00170020h
10h at 02h
(4B)
11h at 02h
(4B)
“APIC_RTE[0-39] - Redirection Table Entry” on page 1139
XXXX0000000
1XXXXh
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7.3.15
8259 Interrupt Controller (PIC)
The 8259 Interrupt Controller includes the registers listed in Table 7-36. These
registers materialize at fixed locations in I/O space. See Chapter 30.0, “Interrupts” for
detailed discussion of these registers.
Table 7-36. Summary of 8259 Interrupt Controller (PIC) Registers Mapped in I/O Space
Offset Start
Offset End
Default
Value
Register ID - Description
020h, 0A0h
020h, 0A0h
“ICW1[0-1] - Initialization Command Word 1 Register” on page 1119
0001X0XXb
021h, 0A1h
021h, 0A1h
“ICW2[0-1] - Initialization Command Word 2 Register” on page 1120
XXh
21h
21h
“MICW3 - Master Initialization Command Word 3 Register” on page 1121
04h
A1h
A1h
“SICW3 - Slave Initialization Command Word 3 Register” on page 1121
00h
21h, 0A1h
21h, 0A1h
“ICW4[0-1] - Initialization Command Word 4 Register” on page 1122
01h
021h, 0A1h
021h, 0A1h
“OCW1[0-1]- Operational Control Word 1 (Interrupt Mask) Register” on page 1122 00h
020h, 0A0h
020h, 0A0h
“OCW2[0-1] - Operational Control Word 2 Register” on page 1123
001XXXXXb
020h, 0A0h
020h, 0A0h
“OCW3[0-1] - Operational Control Word 3 Register” on page 1124
001XX10b
4D0h
4D0h
“ELCR1 - Master Edge/Level Control Register” on page 1125
00h
4D1h
4D1h
“ELCR2 - Slave Edge/Level Control Register” on page 1126
00
7.3.16
APM Power Management
The APM power management includes the registers listed in Table 7-37. These registers
materialize at fixed locations in I/O space. See Chapter 27.0, “Power Management” for
detailed discussion of these registers.
Table 7-37. Summary of APM Registers Mapped in I/O Space
Offset Start
Offset End
Register ID - Description
Default
Value
B2h
B2h
“Offset B2h: APM_CNT - Advanced Power Management Control Port Register” on
page 1054
00h
B3h
B3h
“Offset B3h: APM_STS - Advanced Power Management Status Port Register” on
page 1054
00h
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7.3.17
LPC DMA
The LPC DMA interface includes the registers listed in Table 7-38 through Table 7-40.
These registers materialize at fixed locations in I/O space. See Chapter 20.0, “LPC
DMA” for detailed discussion of these registers.
Table 7-38. Summary of LPC DMA Registers Mapped in I/O Space
Offset Start
Offset End
Default
Value
Register ID - Description
00h at 02h
10h at 02h
“Offset 00h: DMA_BCA[0-3] - DMA Base and Current Address Registers for
Channels 0-3” on page 766
XXXX
C4h at 04h
C5h at 04h
“Offset C4h: DMA_BCA[5-7] - DMA Base and Current Address Registers for
Channels 5-7” on page 767
XXXX
01h at 02h
11h at 02h
“Offset 01h: DMA_BCC[0-3] - DMA Base and Current Count Registers for Channels
XXXX
0-3” on page 768
C6h at 04h
C7h at 04h
“Offset C6h: DMA_BCC[5-7] - DMA Base and Current Count Registers for Channels
XXXX
5-7” on page 769
87h, 83h,
81h, 82h
97h, 93h,
91h, 82h
“Offset 87h: DMA_MPL[0-3] - DMA Memory Low Page Registers for Channels 0-3”
XXXXXXX
on page 771
8Bh, 89h, 8Ah 9Bh, 99h, 9Ah
“Offset 8Bh: DMA_MPL[5-7]: DMA Memory Low Page Registers for Channels 5-7”
on page 771
XXXXXXX
Table 7-39. 0000h (IO) Base Address Registers in the IA F1 View
Offset Start
Offset End
Default
Value
Register ID - Description
08h
08h
“Offset 08h: DMA_COMMAND - DMA Command Register” on page 770
000X0X00b
18h
18h
“Offset 08h: DMA_COMMAND - DMA Command Register” on page 770
000X0X00b
08h
08h
“Offset 08h: DMA_STATUS - DMA Status Register” on page 772
XXXXXXXh
18h
18h
“Offset 08h: DMA_STATUS - DMA Status Register” on page 772
XXXXXXXh
0Ah
0Ah
“Offset 0Ah: DMA_WSM - DMA Write Single Mask Register” on page 773
000001xxb
1Ah
1Ah
“Offset 0Ah: DMA_WSM - DMA Write Single Mask Register” on page 773
000001xxb
0Bh
0Bh
“Offset 0Bh: DMA_CHM - DMA Channel Mode Register” on page 774
000000XXh
1Bh
1Bh
“Offset 0Bh: DMA_CHM - DMA Channel Mode Register” on page 774
000000XXh
0Ch
0Ch
“Offset 0Ch: DMA_CBP - DMA Clear Byte Pointer Register” on page 775
XXXXXXXXh
1Ch
1Ch
“Offset 0Ch: DMA_CBP - DMA Clear Byte Pointer Register” on page 775
XXXXXXXXh
0Dh
0Dh
“Offset 0Dh: DMA_MC - DMA Master Clear Register” on page 775
XXXXXXXXh
1Dh
1Dh
“Offset 0Dh: DMA_MC - DMA Master Clear Register” on page 775
XXXXXXXXh
0Eh
0Eh
“Offset 0Eh: DMA_CM - DMA Clear Mask Register” on page 776
XXXXXXXXh
1Eh
1Eh
“Offset 0Eh: DMA_CM - DMA Clear Mask Register” on page 776
XXXXXXXXh
0Fh
0Fh
“Offset 0Fh: DMA_WAM - DMA Write All Mask Register” on page 777
00001111b
1Fh
1Fh
“Offset 0Fh: DMA_WAM - DMA Write All Mask Register” on page 777
00001111b
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Table 7-40. 0000h (IO) Base Address Registers in the IA F2 View
Offset Start
Offset End
Register ID - Description
Default
Value
D0h
D0h
“Offset 08h: DMA_COMMAND - DMA Command Register” on page 770
000X0X00b
D1h
D1h
“Offset 08h: DMA_COMMAND - DMA Command Register” on page 770
000X0X00b
D0h
D0h
“Offset 08h: DMA_STATUS - DMA Status Register” on page 772
XXXXXXXh
D1h
D1h
“Offset 08h: DMA_STATUS - DMA Status Register” on page 772
XXXXXXXh
D4h
D4h
“Offset 0Ah: DMA_WSM - DMA Write Single Mask Register” on page 773
000001xxb
D5h
D5h
“Offset 0Ah: DMA_WSM - DMA Write Single Mask Register” on page 773
000001xxb
D6h
D6h
“Offset 0Bh: DMA_CHM - DMA Channel Mode Register” on page 774
000000XXh
D7h
D7h
“Offset 0Bh: DMA_CHM - DMA Channel Mode Register” on page 774
000000XXh
D8h
D8h
“Offset 0Ch: DMA_CBP - DMA Clear Byte Pointer Register” on page 775
XXXXXXXXh
D9h
D9h
“Offset 0Ch: DMA_CBP - DMA Clear Byte Pointer Register” on page 775
XXXXXXXXh
DAh
DAh
“Offset 0Dh: DMA_MC - DMA Master Clear Register” on page 775
XXXXXXXXh
DBh
DBh
“Offset 0Dh: DMA_MC - DMA Master Clear Register” on page 775
XXXXXXXXh
DCh
DCh
“Offset 0Eh: DMA_CM - DMA Clear Mask Register” on page 776
XXXXXXXXh
DDh
DDh
“Offset 0Eh: DMA_CM - DMA Clear Mask Register” on page 776
XXXXXXXXh
DEh
DEh
“Offset 0Fh: DMA_WAM - DMA Write All Mask Register” on page 777
00001111b
DFh
DFh
“Offset 0Fh: DMA_WAM - DMA Write All Mask Register” on page 777
00001111b
7.3.18
8254 Timers
The 8254 timers include the registers listed in Table 7-41. These registers materialize
at fixed locations in I/O space. See Chapter 31.0, “8254 Timers” for detailed discussion
of these registers.
Table 7-41. Summary of 8254 Timer Registers Mapped in I/O Space
Offset Start
Offset End
Register ID - Description
43h
43h
40h at 01h
40h at 01h
“Offset 40h: TSB[0-2] - Interval Timer Status Byte Format Register” on page 1147 0XXXXXXXb
40h at 01h
“Offset 40h: TCAP[0-2] - Interval Timer Counter Access Ports Register” on
page 1148
40h at 01h
August 2009
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“Offset 43h: TCW - Timer Control Word Register” on page 1146
Default
Value
XXh
XXh
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7.3.19
High Precision Event Timers
The High Precision Event Timers includes the registers listed in Table 7-42. These
registers materialize at fixed locations in memory space. See Chapter 32.0, “High
Precision Event Timers” for detailed discussion of these registers.
Table 7-42. Summary of HPET Registers Mapped in Memory Space
Offset Start
Offset End
Default
Value
Register ID - Description
000h
007h
“Offset 000h: GCAP_ID - General Capabilities and ID Register” on page 1155
0429B17F808
6A201h
010h
017h
“Offset 010h: GEN_CONF - General Configuration Register” on page 1156
00000000000
00000h
020h
027h
“Offset 020h: GINTR_STA - General Interrupt Status Register” on page 1157
00000000000
00000h
0F0h
0F7h
“Offset 0F0h: MAIN_CNT - Main Counter Value Register” on page 1158
Xh
100h at 20h
107h at 20h
“Offset 100h: HPTCC[0-2] - Timer n Configuration and Capabilities Register” on
page 1159
Xh
108h at 20h
10Fh at 20h
“Offset 108h: HPTCV[0-2] - Timer n Comparator Value Register” on page 1163
Xh
7.3.20
Watchdog Timer and Serial I/O
The Watchdog Timers and Serial I/O units includes the registers listed in Table 7-43
and Table 7-44. These registers materialize at fixed locations in I/O space. See
Chapter 33.0, “Serial I/O Unit and Watchdog Timer” for detailed discussion of these
registers.
Table 7-43. Summary of UART Timer registers in I/O space
Offset Start
Offset End
Register ID - Description
Default
Value
02h
02h
“Offset 02h: IIR - Interrupt Identification Register” on page 1179
01h
02h
02h
“Offset 02h: FCR - FIFO Control Register” on page 1180
00h
03h
03h
“Offset 03h: LCR - Line Control Register” on page 1182
00h
04h
04h
“Offset 04h: MCR - Modem Control Register” on page 1184
00h
05h
05h
“Offset 05h: LSR - Line Status Register” on page 1186
60h
06h
06h
“Offset 06h: MSR - Modem Status Register” on page 1189
00h
07h
07h
“Offset 07h: SCR - Scratchpad Register” on page 1190
00h
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Table 7-44. Summary of Watchdog Timer Registers in I/O Space
Offset Start
Offset End
Register ID - Description
Default
Value
00h
00h
“Offset 00h: PV1R0 - Preload Value 1 Register 0” on page 1194
FFh
01h
01h
“Offset 01h: PV1R1 - Preload Value 1 Register 1” on page 1195
FFh
02h
02h
“Offset 02h: PV1R2 - Preload Value 1 Register 2” on page 1195
0Fh
04h
04h
“Offset 04h: PV2R0 - Preload Value 2 Register 0” on page 1196
FFh
05h
05h
“Offset 05h: PV2R1 - Preload Value 2 Register 1” on page 1196
FFh
06h
06h
“Offset 06h: PV2R2 - Preload Value 2 Register 2” on page 1197
0Fh
08h
08h
“Offset 08h: GISR - General Interrupt Status Register” on page 1197
00h
0Ch
0Ch
“Offset 0Ch: RR0 - Reload Register 0” on page 1198
00h
0Dh
0Dh
“Offset 0Dh: RR1 - Reload Register 1” on page 1199
00h
10h
10h
“Offset 10h: WDTCR - WDT Configuration Register” on page 1199
00h
18h
18h
“Offset 18h: WDTLR - WDT Lock Register” on page 1201
00h
7.3.21
Real Time Clock
The Real Time Clock include the registers listed in Table 7-45. These registers
materialize at indexed locations. See Chapter 29.0, “Real Time Clock” for detailed
discussion of these registers.
Table 7-45. Summary of Real Time Clock Indexed Registers
Offset Start
Offset End
Register ID - Description
Default
Value
0Ah
0Ah
“Offset 0Ah: RTC_REGA - Register A (General Configuration)” on page 1107
XXh
0Bh
0Bh
“Offset 0Bh: RTC_REGB - Register B (General Configuration)” on page 1109
X0X00XXXb
0Ch
0Ch
“Offset 0Ch: RTC_REGC - Register C (Flag Register)” on page 1110
00X00000b
0Dh
0Dh
“Offset 0Dh: RTC_REGD - Register D (Flag Register)” on page 1111
10XXXXXXb
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7.4
AIOC Registers
This section summarizes the registers in the AIOC. The registers are presented as they
materialize from a PCI perspective.
7.4.1
PCI-to-PCI Bridge: Bus 0, Device 4, Function 0
The PCI-to-PCI Bridge includes the registers listed in Table 7-46. These registers
materialize in PCI configuration space. See Chapter 34.0, “PCI-to-PCI Bridge Detailed
Register Descriptions” for detailed discussion of these registers along with alternative
materializations.
Table 7-46. Bus 0, Device 4, Function 0: Summary of PCI-to-PCI Bridge PCI Configuration
Registers (Sheet 1 of 2)
Offset Start
Offset End
Default
Value
Register ID - Description
0h
1h
“Offset 0h: VID: Vendor Identification Register” on page 1217
8086h
2h
3h
“Offset 2h: DID: Device Identification Register” on page 1217
5037h
4h
5h
“Offset 4h: PCICMD: Device Command Register” on page 1217
0h
6h
7h
“Offset 6h: PCISTS: PCI Device Status Register” on page 1218
10h
8h
8h
“Offset 8h: RID: Revision ID Register” on page 1219
Variable
9h
Bh
“Offset 9h: CC: Class Code Register” on page 1219
060400h
Ch
Ch
“Offset Ch: CLS: Cacheline Size Register” on page 1219
00h
Dh
Dh
“Offset Dh: LT: Latency Timer Register” on page 1220
00h
Eh
Eh
“Offset Eh: HDR: Header Type Register” on page 1220
1h
10h
14h
“Offset 10h: CSRBAR0: Control and Status Registers Base Address Register” on
page 1220
00h
14h
17h
“Offset 14h: CSRBAR1: Control and Status Registers Base Address Register” on
page 1221
00h
18h
18h
“Offset 18h: PBNUM: Primary Bus Number Register” on page 1221
00h
19h
19h
“Offset 19h: SECBNM: Secondary Bus Number Register” on page 1221
00h
1Ah
1Ah
“Offset 1Ah: SUBBNM: Subordinate Bus Number Register” on page 1222
00h
1Bh
1Bh
“Offset 1Bh: SECLT: Secondary Latency Timer Register” on page 1222
00h
1Ch
1Ch
“Offset 1Ch: IOB: I/O Base Register” on page 1222
F0
1Dh
1Dh
“Offset 1Dh: IOL: I/O Limit Register” on page 1223
0
1Eh
1Fh
“Offset 1Eh: SECSTA: Secondary Status Register” on page 1223
0h
20h
21h
“Offset 20h: MEMB: Memory Base Register” on page 1224
FFF0
22h
23h
“Offset 22h: MEML: Memory Limit Register” on page 1224
0
24h
25h
“Offset 24h: PMASE: Prefetchable Memory Base Register” on page 1225
FFF1H
26h
27h
“Offset 26h: PMLIMIT: Prefetchable Memory Limit Register” on page 1225
1H
28h
28h
“Offset 28h: PMBASU: Memory Limit Register” on page 1226
Fh
2Ch
2Ch
“Offset 2Ch: PMLMTU: Prefetchable Memory Limit Upper Register” on page 1226
0
30h
31h
“Offset 30h: IOBU: I/O Base Upper Register” on page 1227
0
32h
33h
“Offset 32h: IOLU: I/O Limit Upper Register” on page 1227
0
34h
34h
“Offset 34h: CP: Capabilities Pointer Register” on page 1227
dch
3Ch
3Ch
“Offset 3Ch: IRQL: Interrupt Line Register” on page 1228
0
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Table 7-46. Bus 0, Device 4, Function 0: Summary of PCI-to-PCI Bridge PCI Configuration
Registers (Sheet 2 of 2)
Offset Start
Offset End
3Dh
3Dh
Default
Value
Register ID - Description
“Offset 3Dh: IRQP: Interrupt Pin Register” on page 1228
0
3Eh
3Fh
“Offset 3Eh: BCTL: Bridge Control Register” on page 1228
0000h
DCh
DCh
“Offset DCh: PCID: Power Management Capability ID Register” on page 1229
01h
DDh
DDh
“Offset DDh: PCP: Power Management Next Capability Pointer Register” on
page 1230
00h
DEh
DFh
“Offset DEh: PMCAP: Power Management Capability Register” on page 1230
0023h
E0h
E1h
“Offset E0h: PMCS: Power Management Control and Status Register” on
page 1231
0008h
E2h
E2h
“Offset E2h: PMCSE: Power Management Control and Status Extension Register”
on page 1232
0000h
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7.4.2
Gigabit Ethernet MAC: Bus M, Devices 0, 1, and 2, Function 0
The Gigabit Ethernet MAC includes the registers listed in Table 7-47 through
Table 7-44. These registers materialize in PCI configuration, I/O (via PCI BAR), and
memory (via PCI BAR) spaces. See Section 35.6, “Gigabit Ethernet MAC Configuration
Spaces: Bus M, Device 0-2, Function 0”, Section 35.7, “Gigabit Ethernet MAC I/O
Spaces: Bus M, Device 0-2, Function 0”, and Section 37.6, “GbE Controller Register
Summary” for detailed discussion of these registers along with alternative
materializations.
Table 7-47. Bus M, Device 0, Function 0: Summary of Gigabit Ethernet MAC Interface PCI
Configuration Registers (Sheet 1 of 2)
Offset Start
Offset End
Default
Value
Register ID - Description
00h
01h
“Offset 00h: VID: Vendor Identification Register” on page 1241
8086h
02h
03h
“Offset 02h: DID: Device Identification Register” on page 1241
5040h
04h
05h
“Offset 04h: PCICMD: Device Command Register” on page 1243
0000h
06h
07h
“Offset 06h: PCISTS: PCI Device Status Register” on page 1244
10h
08h
08h
“Offset 08h: RID: Revision ID Register” on page 1245
Variable
09h
0Bh
“Offset 09h: CC: Class Code Register” on page 1245
020000h
0Eh
0Eh
“Offset 0Eh: HDR: Header Type Register” on page 1246
00h
10h
13h
“Offset 10h: CSRBAR: Control and Status Registers Base Address Register” on
page 1246
00000000h
14h
17h
“Offset 14h: IOBAR: CSR I/O Mapped BAR Register” on page 1247
00000001h
2Ch
2Dh
“Offset 2Ch: SVID: Subsystem Vendor ID Register” on page 1248
0000h
2Eh
2Fh
“Offset 2Eh: SID: Subsystem ID Register” on page 1248
0000h
34h
34h
“Offset 34h: CP: Capabilities Pointer Register” on page 1249
DCh
3Ch
3Ch
“Offset 3Ch: IRQL: Interrupt Line Register” on page 1249
00h
3Dh
3Dh
“Offset 3Dh: IRQP: Interrupt Pin Register” on page 1250
01h
DCh
DCh
“Offset DCh: PCID: Power Management Capability ID Register” on page 1251
01h
DDh
DDh
“Offset DDh: PCP: Power Management Next Capability Pointer Register” on
page 1251
E4h
DEh
DFh
“Offset DEh: PMCAP: Power Management Capability Register” on page 1252
X023h
E0h
E1h
“Offset E0h: PMCS: Power Management Control and Status Register” on
page 1253
0000h
E4h
E4h
“Offset E4h: SCID: Signal Target Capability ID Register” on page 1254
09h
E5h
E5h
“Offset E5h: SCP: Signal Target Next Capability Pointer Register” on page 1254
F0h
E6h
E6h
“Offset E6h: SBC: Signal Target Byte Count Register” on page 1255
09h
E7h
E7h
“Offset E7h: STYP: Signal Target Capability Type Register” on page 1255
01h
E8h
E8h
“Offset E8h: SMIA: Signal Target IA Mask Register” on page 1256
0h
ECh
ECh
“Offset ECh: SINT: Signal Target Raw Interrupt Register” on page 1257
00h
F0h
F0h
“Offset F0h: MCID: Message Signalled Interrupt Capability ID Register” on
page 1258
05h
F1h
F1h
“Offset F1h: MCP: Message Signalled Interrupt Next Capability Pointer Register” on
00h
page 1258
F2h
F3h
“Offset F2h: MCTL: Message Signalled Interrupt Control Register” on page 1259
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Table 7-47. Bus M, Device 0, Function 0: Summary of Gigabit Ethernet MAC Interface PCI
Configuration Registers (Sheet 2 of 2)
Offset Start
Offset End
Default
Value
Register ID - Description
F4h
F7h
“Offset F4h: MADR: Message Signalled Interrupt Address Register” on page 1259
00000000h
F8h
F9h
“Offset F8h: MDATA: Message Signalled Interrupt Data Register” on page 1260
0000h
Table 7-48. Bus M, Device 1, Function 0: Summary of Gigabit Ethernet MAC Interface PCI
Configuration Registers (Sheet 1 of 2)
Offset Start
Offset End
Default
Value
Register ID - Description
00h
01h
“Offset 00h: VID: Vendor Identification Register” on page 1241
8086h
02h
03h
“Offset 02h: DID: Device Identification Register” on page 1242
5044h
04h
05h
“Offset 04h: PCICMD: Device Command Register” on page 1243
0000h
06h
07h
“Offset 06h: PCISTS: PCI Device Status Register” on page 1244
10h
08h
08h
“Offset 08h: RID: Revision ID Register” on page 1245
Variable
09h
0Bh
“Offset 09h: CC: Class Code Register” on page 1245
020000h
0Eh
0Eh
“Offset 0Eh: HDR: Header Type Register” on page 1246
00h
13h
“Offset 10h: CSRBAR: Control and Status Registers Base Address Register” on
page 1246
00000000h
10h
14h
17h
“Offset 14h: IOBAR: CSR I/O Mapped BAR Register” on page 1247
00000001h
2Ch
2Dh
“Offset 2Ch: SVID: Subsystem Vendor ID Register” on page 1248
0000h
2Eh
2Fh
“Offset 2Eh: SID: Subsystem ID Register” on page 1248
0000h
34h
34h
“Offset 34h: CP: Capabilities Pointer Register” on page 1249
DCh
3Ch
3Ch
“Offset 3Ch: IRQL: Interrupt Line Register” on page 1249
00h
3Dh
3Dh
“Offset 3Dh: IRQP: Interrupt Pin Register” on page 1250
01h
DCh
DCh
“Offset DCh: PCID: Power Management Capability ID Register” on page 1251
01h
DDh
DDh
“Offset DDh: PCP: Power Management Next Capability Pointer Register” on
page 1251
E4h
DEh
DFh
“Offset DEh: PMCAP: Power Management Capability Register” on page 1252
X023h
E1h
“Offset E0h: PMCS: Power Management Control and Status Register” on
page 1253
0000h
E0h
E4h
E4h
“Offset E4h: SCID: Signal Target Capability ID Register” on page 1254
09h
E5h
E5h
“Offset E5h: SCP: Signal Target Next Capability Pointer Register” on page 1254
F0h
E6h
E6h
“Offset E6h: SBC: Signal Target Byte Count Register” on page 1255
09h
E7h
E7h
“Offset E7h: STYP: Signal Target Capability Type Register” on page 1255
01h
E8h
E8h
“Offset E8h: SMIA: Signal Target IA Mask Register” on page 1256
0h
ECh
ECh
“Offset ECh: SINT: Signal Target Raw Interrupt Register” on page 1257
00h
F0h
F0h
“Offset F0h: MCID: Message Signalled Interrupt Capability ID Register” on
page 1258
05h
F1h
F1h
“Offset F1h: MCP: Message Signalled Interrupt Next Capability Pointer Register” on
00h
page 1258
F2h
F3h
“Offset F2h: MCTL: Message Signalled Interrupt Control Register” on page 1259
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0000h
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Table 7-48. Bus M, Device 1, Function 0: Summary of Gigabit Ethernet MAC Interface PCI
Configuration Registers (Sheet 2 of 2)
Offset Start
Offset End
Default
Value
Register ID - Description
F4h
F7h
“Offset F4h: MADR: Message Signalled Interrupt Address Register” on page 1259
00000000h
F8h
F9h
“Offset F8h: MDATA: Message Signalled Interrupt Data Register” on page 1260
0000h
Table 7-49. Bus M, Device2, Function 0: Summary of Gigabit Ethernet MAC Interface PCI
Configuration Registers (Sheet 1 of 2)
Offset Start
Offset End
Default
Value
Register ID - Description
00h
01h
“Offset 00h: VID: Vendor Identification Register” on page 1241
8086h
02h
03h
“Offset 02h: DID: Device Identification Register” on page 1242
5048h
04h
05h
“Offset 04h: PCICMD: Device Command Register” on page 1243
0000h
06h
07h
“Offset 06h: PCISTS: PCI Device Status Register” on page 1244
10h
08h
08h
“Offset 08h: RID: Revision ID Register” on page 1245
Variable
09h
0Bh
“Offset 09h: CC: Class Code Register” on page 1245
020000h
0Eh
0Eh
“Offset 0Eh: HDR: Header Type Register” on page 1246
00h
10h
13h
“Offset 10h: CSRBAR: Control and Status Registers Base Address Register” on
page 1246
00000000h
14h
17h
“Offset 14h: IOBAR: CSR I/O Mapped BAR Register” on page 1247
00000001h
2Ch
2Dh
“Offset 2Ch: SVID: Subsystem Vendor ID Register” on page 1248
0000h
2Eh
2Fh
“Offset 2Eh: SID: Subsystem ID Register” on page 1248
0000h
34h
34h
“Offset 34h: CP: Capabilities Pointer Register” on page 1249
DCh
3Ch
3Ch
“Offset 3Ch: IRQL: Interrupt Line Register” on page 1249
00h
3Dh
3Dh
“Offset 3Dh: IRQP: Interrupt Pin Register” on page 1250
01h
DCh
DCh
“Offset DCh: PCID: Power Management Capability ID Register” on page 1251
01h
DDh
DDh
“Offset DDh: PCP: Power Management Next Capability Pointer Register” on
page 1251
E4h
DEh
DFh
“Offset DEh: PMCAP: Power Management Capability Register” on page 1252
X023h
E0h
E1h
“Offset E0h: PMCS: Power Management Control and Status Register” on
page 1253
0000h
E4h
E4h
“Offset E4h: SCID: Signal Target Capability ID Register” on page 1254
09h
E5h
E5h
“Offset E5h: SCP: Signal Target Next Capability Pointer Register” on page 1254
F0h
E6h
E6h
“Offset E6h: SBC: Signal Target Byte Count Register” on page 1255
09h
E7h
E7h
“Offset E7h: STYP: Signal Target Capability Type Register” on page 1255
01h
E8h
E8h
“Offset E8h: SMIA: Signal Target IA Mask Register” on page 1256
0h
ECh
ECh
“Offset ECh: SINT: Signal Target Raw Interrupt Register” on page 1257
00h
F0h
F0h
“Offset F0h: MCID: Message Signalled Interrupt Capability ID Register” on
page 1258
05h
F1h
F1h
“Offset F1h: MCP: Message Signalled Interrupt Next Capability Pointer Register” on
00h
page 1258
F2h
F3h
“Offset F2h: MCTL: Message Signalled Interrupt Control Register” on page 1259
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Table 7-49. Bus M, Device2, Function 0: Summary of Gigabit Ethernet MAC Interface PCI
Configuration Registers (Sheet 2 of 2)
Offset Start
Offset End
Register ID - Description
Default
Value
F4h
F7h
“Offset F4h: MADR: Message Signalled Interrupt Address Register” on page 1259
00000000h
F8h
F9h
“Offset F8h: MDATA: Message Signalled Interrupt Data Register” on page 1260
0000h
Table 7-50. Bus M, Device 0, Function 0: Gigabit Ethernet MAC I/O Spaces Registers
Offset Start
Offset End
Register ID - Description
Default
Value
0000h
0003h
“Offset 0000h: IOADDR - IOADDR Register” on page 1263
0000000h
0004h
0007h
“Offset 0004h: IODATA - IODATA Register” on page 1264
0000000h
Table 7-51. Bus M, Device 1, Function 0: Gigabit Ethernet MAC I/O Spaces Registers
Offset Start
Offset End
Register ID - Description
Default
Value
0000h
0003h
“Offset 0000h: IOADDR - IOADDR Register” on page 1263
0000000h
0004h
0007h
“Offset 0004h: IODATA - IODATA Register” on page 1264
0000000h
Table 7-52. Bus M, Device 2, Function 0: Gigabit Ethernet MAC I/O Spaces Registers
Offset Start
Offset End
Register ID - Description
Default
Value
0000h
0003h
“Offset 0000h: IOADDR - IOADDR Register” on page 1263
0000000h
0004h
0007h
“Offset 0004h: IODATA - IODATA Register” on page 1264
0000000h
Table 7-53. Bus M, Device 0, Function 0: Summary of Gigabit Ethernet Interface Registers
Mapped Through CSRBAR Memory BAR (Sheet 1 of 4)
Offset Start
0000h
Offset End
0003h
Register ID - Description
“CTRL: Device Control Register” on page 1438
Default
Value
00000A09h
0008h
000Bh
“STATUS: Device Status Register” on page 1441
0000XXXXh
0018h
001Bh
“CTRL_EXT: Extended Device Control Register” on page 1442
00000000h
00E0h
00E3h
“CTRL_AUX: Auxiliary Device Control Register” on page 1444
00000100h
0010h
0013h
“EEPROM_CTRL - EEPROM Control Register” on page 1446
00000X1Xh
0014h
0017h
“EEPROM_RR – EEPROM Read Register” on page 1448
XXXXXX00h
0028h
002Bh
“FCAL: Flow Control Address Low Register” on page 1449
00c28001h
002Ch
002Fh
“FCAH: Flow Control Address High Register” on page 1450
00000100h
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Table 7-53. Bus M, Device 0, Function 0: Summary of Gigabit Ethernet Interface Registers
Mapped Through CSRBAR Memory BAR (Sheet 2 of 4)
Offset Start
0030h
Offset End
Default
Value
Register ID - Description
0033h
“FCT: Flow Control Type Register” on page 1451
00008808h
0038h
003Bh
“VET: VLAN EtherType Register” on page 1452
00008100h
0170h
0173h
“FCTTV: Flow Control Transmit Timer Value Register” on page 1452
00000000h
1000h
1003h
“PBA: Packet Buffer Allocation Register” on page 1453
00100030h
00C0h
00C3h
“ICR0: Interrupt 0 Cause Read Register” on page 1454
00000000h
00C4h
00C7h
“ITR0: Interrupt 0 Throttling Register” on page 1457
00000000h
00C8h
00CBh
“ICS0: Interrupt 0 Cause Set Register” on page 1458
00000000h
00D0h
00D3h
“IMS0: Interrupt 0 Mask Set/Read Register” on page 1459
00000000h
00D8h
00DBh
“IMC0: Interrupt 0 Mask Clear Register” on page 1460
00000000h
08C0h
08C3h
“ICR1: Interrupt 1Cause Read Register” on page 1462
00000000h
08C8h
08CBh
“ICS1: Interrupt 0 Cause Set Register” on page 1464
00000000h
08D0h
08D3h
“IMS1: Interrupt 1 Mask Set/Read Register” on page 1466
00000000h
08D8h
08DBh
“IMC1: Interrupt 1 Mask Clear Register” on page 1467
00000000h
08E0h
08E3h
“ICR2: Error Interrupt Cause Read Register” on page 1469
00000000h
08E8h
08EBh
“ICS2: Error Interrupt Cause Set Register” on page 1471
00000000h
08F0h
08F3h
“IMS2: Error Interrupt Mask Set/Read Register” on page 1472
00000000h
08F8h
08FBh
“IMC2: Error Interrupt Mask Clear Register” on page 1473
00000000h
0100h
0103h
“RCTL: Receive Control Register” on page 1474
00000000h
2160h
2163h
“FCRTL: Flow Control Receive Threshold Low Register” on page 1478
00000000h
2168h
216Bh
“FCRTH: Flow Control Receive Threshold High Register” on page 1479
00000000h
2800h
2803h
“RDBAL: Receive Descriptor Base Address Low Register” on page 1480
XXXXXXX0h
2804h
2807h
“RDBAH: Receive Descriptor Base Address High Register” on page 1480
XXXXXXXXh
2808h
280Bh
“RDLEN: Receive Descriptor Length Register” on page 1481
00000000h
2810h
2813h
“RDH: Receive Descriptor Head Register” on page 1481
00000000h
2818h
281Bh
“RDT: Receive Descriptor Tail Register” on page 1482
00000000h
2820h
2823h
“RDTR: RX Interrupt Delay Timer (Packet Timer) Register” on page 1483
00000000h
2828h
282Bh
“RXDCTL: Receive Descriptor Control Register” on page 1483
00010000h
282Ch
282Fh
“RADV: Receive Interrupt Absolute Delay Timer Register” on page 1485
00000000h
2C00h
2C03h
“RSRPD: Receive Small Packet Detect Interrupt Register” on page 1486
00000000h
5000h
5003h
“RXCSUM: Receive Checksum Control Register” on page 1487
00000000h
5200h at 4h
5203h at 4h
“MTA[0-127] – 128 Multicast Table Array Registers” on page 1488
XXXX_XXXXh
5400h at 8h
5403h at 8h
“RAL[0-15] - Receive Address Low Register” on page 1488
XXXXXXXXh
5404h at 8h
5407h at 8h
“RAH[0-15] - Receive Address High Register” on page 1489
000XXXXXh
5600h at 4h
5603h at 4h
“VFTA[0-127] - 128 VLAN Filter Table Array Registers” on page 1490
XXXXXXXXh
0400h
0403h
“TCTL: Transmit Control Register” on page 1491
00000008h
0410h
0413h
“TIPG: Transmit IPG Register” on page 1493
00602008h
0458h
045Bh
“AIT: Adaptive IFS Throttle Register” on page 1495
00000000h
3800h
3803h
“TDBAL: Transmit Descriptor Base Address Low Register” on page 1496
XXXXXXX0h
3804h
3807h
“TDBAH: Transmit Descriptor Base Address High Register” on page 1496
XXXXXXXXh
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Table 7-53. Bus M, Device 0, Function 0: Summary of Gigabit Ethernet Interface Registers
Mapped Through CSRBAR Memory BAR (Sheet 3 of 4)
Offset Start
Offset End
3808h
380Bh
Register ID - Description
“TDLEN: Transmit Descriptor Length Register” on page 1497
Default
Value
00000000h
3810h
3813h
“TDH: Transmit Descriptor Head Register” on page 1497
00000000h
3818h
381Bh
“TDT: Transmit Descriptor Tail Register” on page 1498
00000000h
3820h
3823h
“TIDV: Transmit Interrupt Delay Value Register” on page 1499
00000000h
3828h
382Bh
“TXDCTL: Transmit Descriptor Control Register” on page 1500
00000000h
382Ch
382Fh
“TADV: Transmit Absolute Interrupt Delay Value Register” on page 1502
00000000h
3830h
3833h
“TSPMT: TCP Segmentation Pad And Minimum Threshold Register” on page 1504
01000400h
4000h
4003h
“CRCERRS: CRC Error Count Register” on page 1505
00000000h
4004h
4007h
“ALGNERRC: Alignment Error Count Register” on page 1506
00000000h
400Ch
400Fh
“RXERRC: Receive Error Count Register” on page 1506
00000000h
4010h
4013h
“MPC: Missed Packet Count Register” on page 1507
00000000h
4014h
4017h
“SCC: Single Collision Count Register” on page 1507
0000h
4018h
401Bh
“ECOL: Excessive Collisions Count Register” on page 1508
00000000h
401Ch
401Fh
“MCC: Multiple Collision Count Register” on page 1508
00000000h
4020h
4023h
“LATECOL: Late Collisions Count Register” on page 1509
00000000h
4028h
402Bh
“COLC: Collision Count Register” on page 1509
00000000h
4030h
4033h
“DC: Defer Count Register” on page 1510
00000000h
4034h
4037h
“TNCRS: Transmit with No CRS Count Register” on page 1510
00000000h
403Ch
403Fh
“CEXTERR: Carrier Extension Error Count Register” on page 1511
00000000h
4040h
4043h
“RLEC: Receive Length Error Count Register” on page 1511
00000000h
4048h
404Bh
“XONRXC: XON Received Count Register” on page 1512
00000000h
404Ch
404Fh
“XONTXC: XON Transmitted Count Register” on page 1512
00000000h
4050h
4053h
“XOFFRXC: XOFF Received Count Register” on page 1513
00000000h
4054h
4057h
“XOFFTXC: XOFF Transmitted Count Register” on page 1513
00000000h
4058h
405Bh
“FCRUC: FC Received Unsupported Count Register” on page 1514
00000000h
405Ch
405Fh
“PRC64: Good Packets Received Count (64 Bytes) Register” on page 1514
00000000h
4060h
4063h
“PRC127: Good Packets Received Count (65-127 Bytes) Register” on page 1515
00000000h
00000000h
4064h
4067h
“PRC255: Good Packets Received Count (128-255 Bytes) Register” on page 1515
4068h
406Bh
“PRC511 - Good Packets Received Count (256-511 Bytes) Register” on page 1516 00000000h
406Ch
406Fh
“PRC1023: Good Packets Received Count (512-1023 Bytes) Register” on
page 1516
00000000h
4070h
4073h
“PRC1522: Good Packets Received Count (1024 to Max Bytes) Register” on
page 1517
00000000h
4074h
4077h
“GPRC: Good Packets Received Count (Total) Register” on page 1518
00000000h
4078h
407Bh
“BPRC: Broadcast Packets Received Count Register” on page 1518
00000000h
407Ch
407Fh
“MPRC: Multicast Packets Received Count Register” on page 1519
00000000h
4080h
4083h
“GPTC: Good Packets Transmitted Count Register” on page 1519
00000000h
4088h
408Ah
“GORCL: Good Octets Received Count Low Register” on page 1520
00000000h
408Ch
408Fh
“GORCH: Good Octets Received Count High Register” on page 1521
00000000h
4090h
4093h
“GOTCL: Good Octets Transmitted Count Low Register” on page 1522
00000000h
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Intel® EP80579 Integrated Processor
Table 7-53. Bus M, Device 0, Function 0: Summary of Gigabit Ethernet Interface Registers
Mapped Through CSRBAR Memory BAR (Sheet 4 of 4)
Offset Start
Offset End
Default
Value
Register ID - Description
4094h
4097h
“GOTCH: Good Octets Transmitted Count High Register” on page 1522
00000000h
40A0h
40A3h
“RNBC: Receive No Buffers Count Register” on page 1523
00000000h
40A4h
40A7h
“RUC: Receive Undersize Count Register” on page 1523
00000000h
40A8h
40ABh
“RFC: Receive Fragment Count Register” on page 1524
00000000h
40ACh
40AFh
“ROC: Receive Oversize Count Register” on page 1524
00000000h
40B0h
40B3h
“RJC: Receive Jabber Count Register” on page 1525
00000000h
40C0h
40C3h
“TORL: Total Octets Received Low Register” on page 1526
00000000h
40C4h
40C7h
“TORH: Total Octets Received High Register” on page 1526
00000000h
40C8h
40CFh
“TOTL: Total Octets Transmitted Low Register” on page 1527
00000000h
40CCh
40CFh
“TOTH: Total Octets Transmitted High Register” on page 1528
00000000h
40D0h
40D3h
“TPR: Total Packets Received Register” on page 1528
00000000h
40D4h
40D7h
“TPT: Total Packets Transmitted Register” on page 1529
00000000h
40D8h
40DBh
“PTC64 - Packets Transmitted Count (64 Bytes) Register” on page 1529
00000000h
40E0h
40E3h
“PTC255: Packets Transmitted Count (128-255 Bytes) Register” on page 1530
00000000h
40E4h
40E7h
“PTC511: Packets Transmitted Count (256-511 Bytes) Register” on page 1530
00000000h
40E8h
40EBh
“PTC1023: Packets Transmitted Count (512-1023 Bytes) Register” on page 1531
00000000h
40ECh
40EFh
“PTC1522: Packets Transmitted Count (1024-1522 Bytes) Register” on page 1531 00000000h
40F0h
40F3h
“MPTC: Multicast Packets Transmitted Count Register” on page 1532
00000000h
40F4h
40F7h
“BPTC: Broadcast Packets Transmitted Count Register” on page 1532
00000000h
40F8h
40FBh
“TSCTC: TCP Segmentation Context Transmitted Count Register” on page 1533
00000000h
40FCh
40FFh
“TSCTFC: TCP Segmentation Context Transmit Fail Count Register” on page 1533
00000000h
5800h
5803h
“WUC - Wake Up Control Register (0x05800; RW)” on page 1534
00000000h
5808h
580Bh
“WUFC - Wake Up Filter Control Register (0x05808; RW)” on page 1535
00000000h
5810h
5813h
“WUS - Wake Up Status Register (0x05810; RW)” on page 1536
00000000h
5838h
583Bh
“IPAV - IP Address Valid Register (0x05838; RW)” on page 1537
00000000h
5840h at 8h
5843h at 8h
“IP4AT (0x5840 - 0x5858; RW)[0-3]: IPv4 Address Table Registers” on page 1538 XXXXXXXXh
5880h
5883h
“IPV6_ADDR0BYTES_1_4 – IPv6 Address Table Register (0x5880), Bytes 1 - 4” on
XXXXXXXXh
page 1539
05884h
5887h
“IPV6_ADDR0BYTES_5_8 – IPv6 Address Table Register, Bytes 5 - 8” on page 1539 XXXXXXXXh
5888h
588Bh
“IPV6_ADDR0BYTES_9_12 – IPv6 Address Table Register, Bytes 9 - 12” on
page 1540
XXXXXXXXh
588Ch
588Fh
“IPV6_ADDR0BYTES_13_16 – IPv6 Address Table Register, Bytes 13 - 16” on
page 1541
XXXXXXXXh
5F00h at 8h
5F03h at 8h
“FFLT[0-3] - Flexible Filter Length Table Registers (0x5F00 - 0x5F18; RW)” on
page 1542
00000000h
9000h at 8h
9003h at 8h
“FFMT[0-127] - Flexible Filter Mask Table Registers (0x9000 - 0x93F8; RW)” on
page 1543
0000000Xh
9800h at 8h
9803h at 8h
“FFVT[0-127]: Flexible Filter Value Table Registers” on page 1544
XXXXXXXXh
0510h
0513h
“INTBUS_ERR_STAT - Internal Bus Error Status Register” on page 1544
00000000h
0900h
0903h
“MEM_TST - Memory Error Test Register” on page 1546
00000000h
0904h
0907h
“MEM_STS - Memory Error Status Register” on page 1547
007F0000h
Intel® EP80579 Integrated Processor Product Line Datasheet
232
August 2009
Order Number: 320066-003US
Intel® EP80579 Integrated Processor
Table 7-54. Bus M, Device 1, Function 0: Summary of Gigabit Ethernet Interface Registers
Mapped Through CSRBAR Memory BAR (Sheet 1 of 4)
Offset Start
Offset End
Register ID - Description
Default
Value
0000h
0003h
“CTRL: Device Control Register” on page 1438
00000A09h
0008h
000Bh
“STATUS: Device Status Register” on page 1441
0000XXXXh
0018h
001Bh
“CTRL_EXT: Extended Device Control Register” on page 1442
00000000h
00E0h
00E3h
“CTRL_AUX: Auxiliary Device Control Register” on page 1444
00000100h
0010h
0013h
“EEPROM_CTRL - EEPROM Control Register” on page 1446
00000X1Xh
0014h
0017h
“EEPROM_RR – EEPROM Read Register” on page 1448
XXXXXX00h
0028h
002Bh
“FCAL: Flow Control Address Low Register” on page 1449
00c28001h
002Ch
002Fh
“FCAH: Flow Control Address High Register” on page 1450
00000100h
0030h
0033h
“FCT: Flow Control Type Register” on page 1451
00008808h
0038h
003Bh
“VET: VLAN EtherType Register” on page 1452
00008100h
0170h
0173h
“FCTTV: Flow Control Transmit Timer Value Register” on page 1452
00000000h
1000h
1003h
“PBA: Packet Buffer Allocation Register” on page 1453
00100030h
00C0h
00C3h
“ICR0: Interrupt 0 Cause Read Register” on page 1454
00000000h
00C4h
00C7h
“ITR0: Interrupt 0 Throttling Register” on page 1457
00000000h
00C8h
00CBh
“ICS0: Interrupt 0 Cause Set Register” on page 1458
00000000h
00D0h
00D3h
“IMS0: Interrupt 0 Mask Set/Read Register” on page 1459
00000000h
00D8h
00DBh
“IMC0: Interrupt 0 Mask Clear Register” on page 1460
00000000h
08C0h
08C3h
“ICR1: Interrupt 1Cause Read Register” on page 1462
00000000h
08C8h
08CBh
“ICS1: Interrupt 0 Cause Set Register” on page 1464
00000000h
08D0h
08D3h
“IMS1: Interrupt 1 Mask Set/Read Register” on page 1466
00000000h
08D8h
08DBh
“IMC1: Interrupt 1 Mask Clear Register” on page 1467
00000000h
08E0h
08E3h
“ICR2: Error Interrupt Cause Read Register” on page 1469
00000000h
08E8h
08EBh
“ICS2: Error Interrupt Cause Set Register” on page 1471
00000000h
08F0h
08F3h
“IMS2: Error Interrupt Mask Set/Read Register” on page 1472
00000000h
08F8h
08FBh
“IMC2: Error Interrupt Mask Clear Register” on page 1473
00000000h
0100h
0103h
“RCTL: Receive Control Register” on page 1474
00000000h
2160h
2163h
“FCRTL: Flow Control Receive Threshold Low Register” on page 1478
00000000h
2168h
216Bh
“FCRTH: Flow Control Receive Threshold High Register” on page 1479
00000000h
2800h
2803h
“RDBAL: Receive Descriptor Base Address Low Register” on page 1480
XXXXXXX0h
2804h
2807h
“RDBAH: Receive Descriptor Base Address High Register” on page 1480
XXXXXXXXh
2808h
280Bh
“RDLEN: Receive Descriptor Length Register” on page 1481
00000000h
2810h
2813h
“RDH: Receive Descriptor Head Register” on page 1481
00000000h
2818h
281Bh
“RDT: Receive Descriptor Tail Register” on page 1482
00000000h
2820h
2823h
“RDTR: RX Interrupt Delay Timer (Packet Timer) Register” on page 1483
00000000h
2828h
282Bh
“RXDCTL: Receive Descriptor Control Register” on page 1483
00010000h
282Ch
282Fh
“RADV: Receive Interrupt Absolute Delay Timer Register” on page 1485
00000000h
August 2009
Order Number: 320066-003US
Intel® EP80579 Integrated Processor Product Line Datasheet
233
Intel® EP80579 Integrated Processor
Table 7-54. Bus M, Device 1, Function 0: Summary of Gigabit Ethernet Interface Registers
Mapped Through CSRBAR Memory BAR (Sheet 2 of 4)
Offset Start
Offset End
Default
Value
Register ID - Description
2C00h
2C03h
“RSRPD: Receive Small Packet Detect Interrupt Register” on page 1486
00000000h
5000h
5003h
“RXCSUM: Receive Checksum Control Register” on page 1487
00000000h
5200h at 4h
5203h at 4h
“MTA[0-127] – 128 Multicast Table Array Registers” on page 1488
XXXX_XXXXh
5400h at 8h
5403h at 8h
“RAL[0-15] - Receive Address Low Register” on page 1488
XXXXXXXXh
5404h at 8h
5407h at 8h
“RAH[0-15] - Receive Address High Register” on page 1489
000XXXXXh
5600h at 4h
5603h at 4h
“VFTA[0-127] - 128 VLAN Filter Table Array Registers” on page 1490
XXXXXXXXh
0400h
0403h
“TCTL: Transmit Control Register” on page 1491
00000008h
0410h
0413h
“TIPG: Transmit IPG Register” on page 1493
00602008h
0458h
045Bh
“AIT: Adaptive IFS Throttle Register” on page 1495
00000000h
3800h
3803h
“TDBAL: Transmit Descriptor Base Address Low Register” on page 1496
XXXXXXX0h
3804h
3807h
“TDBAH: Transmit Descriptor Base Address High Register” on page 1496
XXXXXXXXh
3808h
380Bh
“TDLEN: Transmit Descriptor Length Register” on page 1497
00000000h
3810h
3813h
“TDH: Transmit Descriptor Head Register” on page 1497
00000000h
3818h
381Bh
“TDT: Transmit Descriptor Tail Register” on page 1498
00000000h
3820h
3823h
“TIDV: Transmit Interrupt Delay Value Register” on page 1499
00000000h
3828h
382Bh
“TXDCTL: Transmit Descriptor Control Register” on page 1500
00000000h
382Ch
382Fh
“TADV: Transmit Absolute Interrupt Delay Value Register” on page 1502
00000000h
3830h
3833h
“TSPMT: TCP Segmentation Pad And Minimum Threshold Register” on page 1504
01000400h
4000h
4003h
“CRCERRS: CRC Error Count Register” on page 1505
00000000h
4004h
4007h
“ALGNERRC: Alignment Error Count Register” on page 1506
00000000h
400Ch
400Fh
“RXERRC: Receive Error Count Register” on page 1506
00000000h
4010h
4013h
“MPC: Missed Packet Count Register” on page 1507
00000000h
4014h
4017h
“SCC: Single Collision Count Register” on page 1507
0000h
4018h
401Bh
“ECOL: Excessive Collisions Count Register” on page 1508
00000000h
401Ch
401Fh
“MCC: Multiple Collision Count Register” on page 1508
00000000h
4020h
4023h
“LATECOL: Late Collisions Count Register” on page 1509
00000000h
4028h
402Bh
“COLC: Collision Count Register” on page 1509
00000000h
4030h
4033h
“DC: Defer Count Register” on page 1510
00000000h
4034h
4037h
“TNCRS: Transmit with No CRS Count Register” on page 1510
00000000h
403Ch
403Fh
“CEXTERR: Carrier Extension Error Count Register” on page 1511
00000000h
4040h
4043h
“RLEC: Receive Length Error Count Register” on page 1511
00000000h
4048h
404Bh
“XONRXC: XON Received Count Register” on page 1512
00000000h
404Ch
404Fh
“XONTXC: XON Transmitted Count Register” on page 1512
00000000h
4050h
4053h
“XOFFRXC: XOFF Received Count Register” on page 1513
00000000h
4054h
4057h
“XOFFTXC: XOFF Transmitted Count Register” on page 1513
00000000h
4058h
405Bh
“FCRUC: FC Received Unsupported Count Register” on page 1514
00000000h
405Ch
405Fh
“PRC64: Good Packets Received Count (64 Bytes) Register” on page 1514
00000000h
4060h
4063h
“PRC127: Good Packets Received Count (65-127 Bytes) Register” on page 1515
00000000h
4064h
4067h
“PRC255: Good Packets Received Count (128-255 Bytes) Register” on page 1515
00000000h
Intel® EP80579 Integrated Processor Product Line Datasheet
234
August 2009
Order Number: 320066-003US
Intel® EP80579 Integrated Processor
Table 7-54. Bus M, Device 1, Function 0: Summary of Gigabit Ethernet Interface Registers
Mapped Through CSRBAR Memory BAR (Sheet 3 of 4)
Offset Start
Offset End
Register ID - Description
Default
Value
4068h
406Bh
“PRC511 - Good Packets Received Count (256-511 Bytes) Register” on page 1516 00000000h
406Ch
406Fh
“PRC1023: Good Packets Received Count (512-1023 Bytes) Register” on
page 1516
00000000h
4070h
4073h
“PRC1522: Good Packets Received Count (1024 to Max Bytes) Register” on
page 1517
00000000h
4074h
4077h
“GPRC: Good Packets Received Count (Total) Register” on page 1518
00000000h
4078h
407Bh
“BPRC: Broadcast Packets Received Count Register” on page 1518
00000000h
407Ch
407Fh
“MPRC: Multicast Packets Received Count Register” on page 1519
00000000h
4080h
4083h
“GPTC: Good Packets Transmitted Count Register” on page 1519
00000000h
4088h
408Ah
“GORCL: Good Octets Received Count Low Register” on page 1520
00000000h
408Ch
408Fh
“GORCH: Good Octets Received Count High Register” on page 1521
00000000h
4090h
4093h
“GOTCL: Good Octets Transmitted Count Low Register” on page 1522
00000000h
4094h
4097h
“GOTCH: Good Octets Transmitted Count High Register” on page 1522
00000000h
40A0h
40A3h
“RNBC: Receive No Buffers Count Register” on page 1523
00000000h
40A4h
40A7h
“RUC: Receive Undersize Count Register” on page 1523
00000000h
40A8h
40ABh
“RFC: Receive Fragment Count Register” on page 1524
00000000h
40ACh
40AFh
“ROC: Receive Oversize Count Register” on page 1524
00000000h
40B0h
40B3h
“RJC: Receive Jabber Count Register” on page 1525
00000000h
40C0h
40C3h
“TORL: Total Octets Received Low Register” on page 1526
00000000h
40C4h
40C7h
“TORH: Total Octets Received High Register” on page 1526
00000000h
40C8h
40CFh
“TOTL: Total Octets Transmitted Low Register” on page 1527
00000000h
40CCh
40CFh
“TOTH: Total Octets Transmitted High Register” on page 1528
00000000h
40D0h
40D3h
“TPR: Total Packets Received Register” on page 1528
00000000h
40D4h
40D7h
“TPT: Total Packets Transmitted Register” on page 1529
00000000h
40D8h
40DBh
“PTC64 - Packets Transmitted Count (64 Bytes) Register” on page 1529
00000000h
40E0h
40E3h
“PTC255: Packets Transmitted Count (128-255 Bytes) Register” on page 1530
00000000h
40E4h
40E7h
“PTC511: Packets Transmitted Count (256-511 Bytes) Register” on page 1530
00000000h
00000000h
40E8h
40EBh
“PTC1023: Packets Transmitted Count (512-1023 Bytes) Register” on page 1531
40ECh
40EFh
“PTC1522: Packets Transmitted Count (1024-1522 Bytes) Register” on page 1531 00000000h
40F0h
40F3h
“MPTC: Multicast Packets Transmitted Count Register” on page 1532
00000000h
40F4h
40F7h
“BPTC: Broadcast Packets Transmitted Count Register” on page 1532
00000000h
40F8h
40FBh
“TSCTC: TCP Segmentation Context Transmitted Count Register” on page 1533
00000000h
40FCh
40FFh
“TSCTFC: TCP Segmentation Context Transmit Fail Count Register” on page 1533
00000000h
5800h
5803h
“WUC - Wake Up Control Register (0x05800; RW)” on page 1534
00000000h
5808h
580Bh
“WUFC - Wake Up Filter Control Register (0x05808; RW)” on page 1535
00000000h
5810h
5813h
“WUS - Wake Up Status Register (0x05810; RW)” on page 1536
00000000h
5838h
583Bh
“IPAV - IP Address Valid Register (0x05838; RW)” on page 1537
00000000h
5840h at 8h
5843h at 8h
“IP4AT (0x5840 - 0x5858; RW)[0-3]: IPv4 Address Table Registers” on page 1538 XXXXXXXXh
5883h
“IPV6_ADDR0BYTES_1_4 – IPv6 Address Table Register (0x5880), Bytes 1 - 4” on
XXXXXXXXh
page 1539
5880h
August 2009
Order Number: 320066-003US
Intel® EP80579 Integrated Processor Product Line Datasheet
235
Intel® EP80579 Integrated Processor
Table 7-54. Bus M, Device 1, Function 0: Summary of Gigabit Ethernet Interface Registers
Mapped Through CSRBAR Memory BAR (Sheet 4 of 4)
Offset Start
Offset End
Default
Value
Register ID - Description
05884h
5887h
“IPV6_ADDR0BYTES_5_8 – IPv6 Address Table Register, Bytes 5 - 8” on page 1539 XXXXXXXXh
5888h
588Bh
“IPV6_ADDR0BYTES_9_12 – IPv6 Address Table Register, Bytes 9 - 12” on
page 1540
XXXXXXXXh
588Ch
588Fh
“IPV6_ADDR0BYTES_13_16 – IPv6 Address Table Register, Bytes 13 - 16” on
page 1541
XXXXXXXXh
5F00h at 8h
5F03h at 8h
“FFLT[0-3] - Flexible Filter Length Table Registers (0x5F00 - 0x5F18; RW)” on
page 1542
00000000h
9000h at 8h
9003h at 8h
“FFMT[0-127] - Flexible Filter Mask Table Registers (0x9000 - 0x93F8; RW)” on
page 1543
0000000Xh
9800h at 8h
9803h at 8h
“FFVT[0-127]: Flexible Filter Value Table Registers” on page 1544
XXXXXXXXh
0510h
0513h
“INTBUS_ERR_STAT - Internal Bus Error Status Register” on page 1544
00000000h
0900h
0903h
“MEM_TST - Memory Error Test Register” on page 1546
00000000h
0904h
0907h
“MEM_STS - Memory Error Status Register” on page 1547
007F0000h
Table 7-55. Bus M, Devices 2, Function 0: Summary of Gigabit Ethernet Interface
Registers Mapped Through CSRBAR Memory BAR (Sheet 1 of 4)
Offset Start
Offset End
Register ID - Description
Default
Value
0000h
0003h
“CTRL: Device Control Register” on page 1438
00000A09h
0008h
000Bh
“STATUS: Device Status Register” on page 1441
0000XXXXh
0018h
001Bh
“CTRL_EXT: Extended Device Control Register” on page 1442
00000000h
00E0h
00E3h
“CTRL_AUX: Auxiliary Device Control Register” on page 1444
00000100h
0010h
0013h
“EEPROM_CTRL - EEPROM Control Register” on page 1446
00000X1Xh
0014h
0017h
“EEPROM_RR – EEPROM Read Register” on page 1448
XXXXXX00h
0028h
002Bh
“FCAL: Flow Control Address Low Register” on page 1449
00c28001h
002Ch
002Fh
“FCAH: Flow Control Address High Register” on page 1450
00000100h
0030h
0033h
“FCT: Flow Control Type Register” on page 1451
00008808h
0038h
003Bh
“VET: VLAN EtherType Register” on page 1452
00008100h
0170h
0173h
“FCTTV: Flow Control Transmit Timer Value Register” on page 1452
00000000h
1000h
1003h
“PBA: Packet Buffer Allocation Register” on page 1453
00100030h
00C0h
00C3h
“ICR0: Interrupt 0 Cause Read Register” on page 1454
00000000h
00C4h
00C7h
“ITR0: Interrupt 0 Throttling Register” on page 1457
00000000h
00C8h
00CBh
“ICS0: Interrupt 0 Cause Set Register” on page 1458
00000000h
00D0h
00D3h
“IMS0: Interrupt 0 Mask Set/Read Register” on page 1459
00000000h
00D8h
00DBh
“IMC0: Interrupt 0 Mask Clear Register” on page 1460
00000000h
08C0h
08C3h
“ICR1: Interrupt 1Cause Read Register” on page 1462
00000000h
08C8h
08CBh
“ICS1: Interrupt 0 Cause Set Register” on page 1464
00000000h
08D0h
08D3h
“IMS1: Interrupt 1 Mask Set/Read Register” on page 1466
00000000h
08D8h
08DBh
“IMC1: Interrupt 1 Mask Clear Register” on page 1467
00000000h
Intel® EP80579 Integrated Processor Product Line Datasheet
236
August 2009
Order Number: 320066-003US
Intel® EP80579 Integrated Processor
Table 7-55. Bus M, Devices 2, Function 0: Summary of Gigabit Ethernet Interface
Registers Mapped Through CSRBAR Memory BAR (Sheet 2 of 4)
Offset Start
Offset End
Register ID - Description
“ICR2: Error Interrupt Cause Read Register” on page 1469
Default
Value
08E0h
08E3h
00000000h
08E8h
08EBh
“ICS2: Error Interrupt Cause Set Register” on page 1471
00000000h
08F0h
08F3h
“IMS2: Error Interrupt Mask Set/Read Register” on page 1472
00000000h
08F8h
08FBh
“IMC2: Error Interrupt Mask Clear Register” on page 1473
00000000h
0100h
0103h
“RCTL: Receive Control Register” on page 1474
00000000h
2160h
2163h
“FCRTL: Flow Control Receive Threshold Low Register” on page 1478
00000000h
2168h
216Bh
“FCRTH: Flow Control Receive Threshold High Register” on page 1479
00000000h
2800h
2803h
“RDBAL: Receive Descriptor Base Address Low Register” on page 1480
XXXXXXX0h
2804h
2807h
“RDBAH: Receive Descriptor Base Address High Register” on page 1480
XXXXXXXXh
2808h
280Bh
“RDLEN: Receive Descriptor Length Register” on page 1481
00000000h
2810h
2813h
“RDH: Receive Descriptor Head Register” on page 1481
00000000h
2818h
281Bh
“RDT: Receive Descriptor Tail Register” on page 1482
00000000h
2820h
2823h
“RDTR: RX Interrupt Delay Timer (Packet Timer) Register” on page 1483
00000000h
2828h
282Bh
“RXDCTL: Receive Descriptor Control Register” on page 1483
00010000h
282Ch
282Fh
“RADV: Receive Interrupt Absolute Delay Timer Register” on page 1485
00000000h
2C00h
2C03h
“RSRPD: Receive Small Packet Detect Interrupt Register” on page 1486
00000000h
5000h
5003h
“RXCSUM: Receive Checksum Control Register” on page 1487
00000000h
5200h at 4h
5203h at 4h
“MTA[0-127] – 128 Multicast Table Array Registers” on page 1488
XXXX_XXXXh
5400h at 8h
5403h at 8h
“RAL[0-15] - Receive Address Low Register” on page 1488
XXXXXXXXh
5404h at 8h
5407h at 8h
“RAH[0-15] - Receive Address High Register” on page 1489
000XXXXXh
5600h at 4h
5603h at 4h
“VFTA[0-127] - 128 VLAN Filter Table Array Registers” on page 1490
XXXXXXXXh
0400h
0403h
“TCTL: Transmit Control Register” on page 1491
00000008h
0410h
0413h
“TIPG: Transmit IPG Register” on page 1493
00602008h
0458h
045Bh
“AIT: Adaptive IFS Throttle Register” on page 1495
00000000h
3800h
3803h
“TDBAL: Transmit Descriptor Base Address Low Register” on page 1496
XXXXXXX0h
3804h
3807h
“TDBAH: Transmit Descriptor Base Address High Register” on page 1496
XXXXXXXXh
3808h
380Bh
“TDLEN: Transmit Descriptor Length Register” on page 1497
00000000h
3810h
3813h
“TDH: Transmit Descriptor Head Register” on page 1497
00000000h
3818h
381Bh
“TDT: Transmit Descriptor Tail Register” on page 1498
00000000h
3820h
3823h
“TIDV: Transmit Interrupt Delay Value Register” on page 1499
00000000h
3828h
382Bh
“TXDCTL: Transmit Descriptor Control Register” on page 1500
00000000h
382Ch
382Fh
“TADV: Transmit Absolute Interrupt Delay Value Register” on page 1502
00000000h
3830h
3833h
“TSPMT: TCP Segmentation Pad And Minimum Threshold Register” on page 1504
01000400h
4000h
4003h
“CRCERRS: CRC Error Count Register” on page 1505
00000000h
4004h
4007h
“ALGNERRC: Alignment Error Count Register” on page 1506
00000000h
400Ch
400Fh
“RXERRC: Receive Error Count Register” on page 1506
00000000h
4010h
4013h
“MPC: Missed Packet Count Register” on page 1507
00000000h
4014h
4017h
“SCC: Single Collision Count Register” on page 1507
0000h
4018h
401Bh
“ECOL: Excessive Collisions Count Register” on page 1508
00000000h
August 2009
Order Number: 320066-003US
Intel® EP80579 Integrated Processor Product Line Datasheet
237
Intel® EP80579 Integrated Processor
Table 7-55. Bus M, Devices 2, Function 0: Summary of Gigabit Ethernet Interface
Registers Mapped Through CSRBAR Memory BAR (Sheet 3 of 4)
Offset Start
Offset End
Default
Value
Register ID - Description
401Ch
401Fh
“MCC: Multiple Collision Count Register” on page 1508
00000000h
4020h
4023h
“LATECOL: Late Collisions Count Register” on page 1509
00000000h
4028h
402Bh
“COLC: Collision Count Register” on page 1509
00000000h
4030h
4033h
“DC: Defer Count Register” on page 1510
00000000h
4034h
4037h
“TNCRS: Transmit with No CRS Count Register” on page 1510
00000000h
403Ch
403Fh
“CEXTERR: Carrier Extension Error Count Register” on page 1511
00000000h
4040h
4043h
“RLEC: Receive Length Error Count Register” on page 1511
00000000h
4048h
404Bh
“XONRXC: XON Received Count Register” on page 1512
00000000h
404Ch
404Fh
“XONTXC: XON Transmitted Count Register” on page 1512
00000000h
4050h
4053h
“XOFFRXC: XOFF Received Count Register” on page 1513
00000000h
4054h
4057h
“XOFFTXC: XOFF Transmitted Count Register” on page 1513
00000000h
4058h
405Bh
“FCRUC: FC Received Unsupported Count Register” on page 1514
00000000h
405Ch
405Fh
“PRC64: Good Packets Received Count (64 Bytes) Register” on page 1514
00000000h
4060h
4063h
“PRC127: Good Packets Received Count (65-127 Bytes) Register” on page 1515
00000000h
4064h
4067h
“PRC255: Good Packets Received Count (128-255 Bytes) Register” on page 1515
00000000h
4068h
406Bh
“PRC511 - Good Packets Received Count (256-511 Bytes) Register” on page 1516 00000000h
406Ch
406Fh
“PRC1023: Good Packets Received Count (512-1023 Bytes) Register” on
page 1516
00000000h
4070h
4073h
“PRC1522: Good Packets Received Count (1024 to Max Bytes) Register” on
page 1517
00000000h
4074h
4077h
“GPRC: Good Packets Received Count (Total) Register” on page 1518
00000000h
4078h
407Bh
“BPRC: Broadcast Packets Received Count Register” on page 1518
00000000h
407Ch
407Fh
“MPRC: Multicast Packets Received Count Register” on page 1519
00000000h
4080h
4083h
“GPTC: Good Packets Transmitted Count Register” on page 1519
00000000h
4088h
408Ah
“GORCL: Good Octets Received Count Low Register” on page 1520
00000000h
408Ch
408Fh
“GORCH: Good Octets Received Count High Register” on page 1521
00000000h
4090h
4093h
“GOTCL: Good Octets Transmitted Count Low Register” on page 1522
00000000h
4094h
4097h
“GOTCH: Good Octets Transmitted Count High Register” on page 1522
00000000h
40A0h
40A3h
“RNBC: Receive No Buffers Count Register” on page 1523
00000000h
40A4h
40A7h
“RUC: Receive Undersize Count Register” on page 1523
00000000h
40A8h
40ABh
“RFC: Receive Fragment Count Register” on page 1524
00000000h
40ACh
40AFh
“ROC: Receive Oversize Count Register” on page 1524
00000000h
40B0h
40B3h
“RJC: Receive Jabber Count Register” on page 1525
00000000h
40C0h
40C3h
“TORL: Total Octets Received Low Register” on page 1526
00000000h
40C4h
40C7h
“TORH: Total Octets Received High Register” on page 1526
00000000h
40C8h
40CFh
“TOTL: Total Octets Transmitted Low Register” on page 1527
00000000h
40CCh
40CFh
“TOTH: Total Octets Transmitted High Register” on page 1528
00000000h
40D0h
40D3h
“TPR: Total Packets Received Register” on page 1528
00000000h
40D4h
40D7h
“TPT: Total Packets Transmitted Register” on page 1529
00000000h
40D8h
40DBh
“PTC64 - Packets Transmitted Count (64 Bytes) Register” on page 1529
00000000h
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Table 7-55. Bus M, Devices 2, Function 0: Summary of Gigabit Ethernet Interface
Registers Mapped Through CSRBAR Memory BAR (Sheet 4 of 4)
Offset Start
40E0h
Offset End
40E3h
Register ID - Description
“PTC255: Packets Transmitted Count (128-255 Bytes) Register” on page 1530
Default
Value
00000000h
40E4h
40E7h
“PTC511: Packets Transmitted Count (256-511 Bytes) Register” on page 1530
00000000h
40E8h
40EBh
“PTC1023: Packets Transmitted Count (512-1023 Bytes) Register” on page 1531
00000000h
40ECh
40EFh
“PTC1522: Packets Transmitted Count (1024-1522 Bytes) Register” on page 1531 00000000h
40F0h
40F3h
“MPTC: Multicast Packets Transmitted Count Register” on page 1532
00000000h
40F4h
40F7h
“BPTC: Broadcast Packets Transmitted Count Register” on page 1532
00000000h
40F8h
40FBh
“TSCTC: TCP Segmentation Context Transmitted Count Register” on page 1533
00000000h
40FCh
40FFh
“TSCTFC: TCP Segmentation Context Transmit Fail Count Register” on page 1533
00000000h
5800h
5803h
“WUC - Wake Up Control Register (0x05800; RW)” on page 1534
00000000h
5808h
580Bh
“WUFC - Wake Up Filter Control Register (0x05808; RW)” on page 1535
00000000h
5810h
5813h
“WUS - Wake Up Status Register (0x05810; RW)” on page 1536
00000000h
00000000h
5838h
583Bh
“IPAV - IP Address Valid Register (0x05838; RW)” on page 1537
5840h at 8h
5607h at 8h
“IP4AT (0x5840 - 0x5858; RW)[0-3]: IPv4 Address Table Registers” on page 1538 XXXXXXXXh
5880h
5883h
“IPV6_ADDR0BYTES_1_4 – IPv6 Address Table Register (0x5880), Bytes 1 - 4” on
XXXXXXXXh
page 1539
05884h
0588Fh
“IPV6_ADDR0BYTES_5_8 – IPv6 Address Table Register, Bytes 5 - 8” on page 1539 XXXXXXXXh
5888h
588Bh
“IPV6_ADDR0BYTES_9_12 – IPv6 Address Table Register, Bytes 9 - 12” on
page 1540
XXXXXXXXh
588Ch
588Fh
“IPV6_ADDR0BYTES_13_16 – IPv6 Address Table Register, Bytes 13 - 16” on
page 1541
XXXXXXXXh
5F00h at 8h
5F03h at 8h
“FFLT[0-3] - Flexible Filter Length Table Registers (0x5F00 - 0x5F18; RW)” on
page 1542
00000000h
9000h at 8h
9003h at 8h
“FFMT[0-127] - Flexible Filter Mask Table Registers (0x9000 - 0x93F8; RW)” on
page 1543
0000000Xh
9800h at 8h
9803h at 8h
“FFVT[0-127]: Flexible Filter Value Table Registers” on page 1544
XXXXXXXXh
0510h
0513h
“INTBUS_ERR_STAT - Internal Bus Error Status Register” on page 1544
00000000h
0900h
0903h
“MEM_TST - Memory Error Test Register” on page 1546
00000000h
0904h
0907h
“MEM_STS - Memory Error Status Register” on page 1547
007F0000h
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7.4.3
GCU: Bus M, Device 3, Function 0
The GCU includes the registers listed in Table 7-56 and Table 7-57. These registers
materialize in PCI configuration and memory (via PCI BAR) spaces. See Section 35.8,
“GCU Configuration Space: Bus M, Device 3, Function 0”and Chapter 38.0, “Register
Summary” for detailed discussion of these registers along with alternative
materializations.
Table 7-56. Bus M, Device 3, Function 0: Summary of GCU PCI Configuration Registers
Offset Start
Offset End
Default
Value
Register ID - Description
00h
01h
“Offset 00h: VID: Vendor Identification Register” on page 1265
8086h
02h
03h
“Offset 02h: DID: Device Identification Register” on page 1266
503Eh
04h
05h
“Offset 04h: PCICMD: Device Command Register” on page 1266
0000h
06h
07h
“Offset 06h: PCISTS: PCI Device Status Register” on page 1267
0010h
08h
08h
“Offset 08h: RID: Revision ID Register” on page 1268
Variable
09h
0Bh
“Offset 09h: CC: Class Code Register” on page 1268
FF0000h
0Eh
0Eh
“Offset 0Eh: HDR: Header Type Register” on page 1268
00h
13h
“Offset 10h: CSRBAR: Control and Status Registers Base Address Register” on
page 1269
00000000h
2Ch
2Dh
“Offset 2Ch: SVID: Subsystem Vendor ID Register” on page 1269
0000h
2Eh
2Fh
“Offset 2Eh: SID: Subsystem ID Register” on page 1270
0000h
34h
34h
“Offset 34h: CP: Capabilities Pointer Register” on page 1270
DCh
DCh
DCh
“Offset DCh: PCID: Power Management Capability ID Register” on page 1270
01h
DDh
DDh
“Offset DDh: PCP: Power Management Next Capability Pointer Register” on
page 1271
00h
DEh
DFh
“Offset DEh: PMCAP: Power Management Capability Register” on page 1271
0023h
E0h
E1h
“Offset E0h: PMCS: Power Management Control and Status Register” on
page 1272
0000h
10h
Table 7-57. Bus M, Device 3, Function 0: Summary of GCU Registers Mapped Through
CSRBAR Memory BAR (Sheet 1 of 2)
Offset Start
Offset End
Default
Value
Register ID - Description
00000010h
00000013h
“Offset 0x00000010h: MDIO_STATUS - MDIO Status Register” on page 1562
00000000h
00000014h
00000017h
“Offset 0x00000014h: MDIO_COMMAND - MDIO Command Register” on
page 1562
00000000h
00000018h
0000001Bh
“Offset 0x00000018h: MDIO_DRIVE - MDIO Drive Register” on page 1563
03030107h
00000020h
00000023h
“Offset 0x00000020h: MDC_DRIVE - MDC Drive Register” on page 1563
0303030Fh
00000024h
00000027h
“Offset 0x00000024h: GCU_GBE_RC_CTRL - GCU GbE RCOMP Control Register”
on page 1564
0031F31Fh
00000044h
00000047h
“Offset 0x00000044h: GCU_GBE_RC_STAT - GCU GbE RCOMP Status Register” on
00000000h
page 1564
00000050h
00000053h
“Offset 0x00000050h: GCU_LEB_RC_STAT - GCU Local Expansion Bus RCOMP
Status Register” on page 1565
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Intel® EP80579 Integrated Processor
Table 7-57. Bus M, Device 3, Function 0: Summary of GCU Registers Mapped Through
CSRBAR Memory BAR (Sheet 2 of 2)
Offset Start
Offset End
Register ID - Description
Default
Value
“Offset 0x00000054h: GCU_LEB_RC_CTRL - GCU Local Expansion Bus RCOMP
Control Register” on page 1566
000030F301h
00000063h
“Offset 0x00000060h: SSP_DRIVE - SSP Drive Register” on page 1566
02000200h
00000064h
00000067h
“Offset 0x00000064h: TDM_DRIVE_3 - TDM Drive Register for TDM ports 3” on
page 1567
02000200h
00000068h
0000006Bh
“Offset 0x00000068h: TDM_DRIVE_12 - TDM Drive Register for TDM ports 1 & 2”
on page 1567
02000200h
00000028h
0000002Bh
“Offset 0x00000028h: CAN_DRIVE - CAN Drive Register” on page 1568
02000200h
00000054h
00000057h
00000060h
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7.4.4
CAN Interface: Bus M, Device 4 and 5, Function 0
The CAN interface includes the registers listed in Table 7-58 through Table 7-61. These
registers materialize in PCI configuration and memory (via PCI BAR) spaces. See
Section 35.9, “CAN Controller Configuration Spaces: Bus M, Device 4-5, Function 0”
and Chapter 39.0, “Detailed Register Descriptions” for detailed discussion of these
registers along with alternative materializations.
Table 7-58. Bus M, Device 4, Function 0: Summary of CAN Interface PCI Configuration
Registers
Offset Start
Offset End
Default
Value
Register ID - Description
00h
01h
“Offset 00h: VID: Vendor Identification Register” on page 1275
8086h
02h
03h
“Offset 02h: DID: Device Identification Register” on page 1275
5039h
04h
05h
“Offset 04h: PCICMD: Device Command Register” on page 1276
0h
06h
07h
“Offset 06h: PCISTS: PCI Device Status Register” on page 1277
10h
08h
08h
“Offset 08h: RID: Revision ID Register” on page 1278
Variable
09h
0Bh
“Offset 09h: CC: Class Code Register” on page 1278
0C0900h
0Eh
0Eh
“Offset 0Eh: HDR: Header Type Register” on page 1279
00h
10h
13h
“Offset 10h: CSRBAR: Control and Status Registers Base Address Register” on
page 1279
00000000h
2Ch
2Dh
“Offset 2Ch: SVID: Subsystem Vendor ID Register” on page 1280
0000h
2Eh
2Fh
“Offset 2Eh: SID: Subsystem ID Register” on page 1280
0000h
34h
34h
“Offset 34h: CP: Capabilities Pointer Register” on page 1281
DCh
3Ch
3Ch
“Offset 3Ch: IRQL: Interrupt Line Register” on page 1281
00h
3Dh
3Dh
“Offset 3Dh: IRQP: Interrupt Pin Register” on page 1282
01h
40h
40h
“Offset 40h: CANCTL - CAN Control Register” on page 1282
00h
DCh
DCh
“Offset DCh: PCID: Power Management Capability ID Register” on page 1283
01h
DDh
DDh
“Offset DDh: PCP: Power Management Next Capability Pointer Register” on
page 1283
E4h
DEh
DFh
“Offset DEh: PMCAP: Power Management Capability Register” on page 1284
0023h
E0h
E1h
“Offset E0h: PMCS: Power Management Control and Status Register” on
page 1284
0000h
E4h
E4h
“Offset E4h: SCID: Signal Target Capability ID Register” on page 1285
09h
E5h
E5h
“Offset E5h: SCP: Signal Target Next Capability Pointer Register” on page 1285
F0h
E6h
E6h
“Offset E6h: SBC: Signal Target Byte Count Register” on page 1286
09h
E7h
E7h
“Offset E7h: STYP: Signal Target Capability Type Register” on page 1286
01h
E8h
E8h
“Offset E8h: SMIA: Signal Target IA Mask Register” on page 1287
0h
ECh
ECh
“Offset ECh: SINT: Signal Target Raw Interrupt Register” on page 1287
00h
F0h
F0h
“Offset F0h: MCID: Message Signalled Interrupt Capability ID Register” on
page 1288
05h
F1h
F1h
“Offset F1h: MCP: Message Signalled Interrupt Next Capability Pointer Register” on
00h
page 1288
F2h
F3h
“Offset F2h: MCTL: Message Signalled Interrupt Control Register” on page 1289
0000h
F4h
F7h
“Offset F4h: MADR: Message Signalled Interrupt Address Register” on page 1289
00000000h
F8h
F9h
“Offset F8h: MDATA: Message Signalled Interrupt Data Register” on page 1290
0000h
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Intel® EP80579 Integrated Processor
Table 7-59. Bus M, Devices 5, Function 0: Summary of CAN Interface PCI Configuration
Registers
Offset Start
Offset End
Default
Value
Register ID - Description
00h
01h
“Offset 00h: VID: Vendor Identification Register” on page 1275
8086h
02h
03h
“Offset 02h: DID: Device Identification Register” on page 1276
503Ah
04h
05h
“Offset 04h: PCICMD: Device Command Register” on page 1276
0h
06h
07h
“Offset 06h: PCISTS: PCI Device Status Register” on page 1277
10h
08h
08h
“Offset 08h: RID: Revision ID Register” on page 1278
Variable
09h
0Bh
“Offset 09h: CC: Class Code Register” on page 1278
0C0900h
0Eh
0Eh
“Offset 0Eh: HDR: Header Type Register” on page 1279
00h
13h
“Offset 10h: CSRBAR: Control and Status Registers Base Address Register” on
page 1279
00000000h
10h
2Ch
2Dh
“Offset 2Ch: SVID: Subsystem Vendor ID Register” on page 1280
0000h
2Eh
2Fh
“Offset 2Eh: SID: Subsystem ID Register” on page 1280
0000h
34h
34h
“Offset 34h: CP: Capabilities Pointer Register” on page 1281
DCh
3Ch
3Ch
“Offset 3Ch: IRQL: Interrupt Line Register” on page 1281
00h
3Dh
3Dh
“Offset 3Dh: IRQP: Interrupt Pin Register” on page 1282
01h
40h
40h
“Offset 40h: CANCTL - CAN Control Register” on page 1282
00h
DCh
DCh
“Offset DCh: PCID: Power Management Capability ID Register” on page 1283
01h
DDh
DDh
“Offset DDh: PCP: Power Management Next Capability Pointer Register” on
page 1283
E4h
DEh
DFh
“Offset DEh: PMCAP: Power Management Capability Register” on page 1284
0023h
E1h
“Offset E0h: PMCS: Power Management Control and Status Register” on
page 1284
0000h
E0h
E4h
E4h
“Offset E4h: SCID: Signal Target Capability ID Register” on page 1285
09h
E5h
E5h
“Offset E5h: SCP: Signal Target Next Capability Pointer Register” on page 1285
F0h
E6h
E6h
“Offset E6h: SBC: Signal Target Byte Count Register” on page 1286
09h
E7h
E7h
“Offset E7h: STYP: Signal Target Capability Type Register” on page 1286
01h
E8h
E8h
“Offset E8h: SMIA: Signal Target IA Mask Register” on page 1287
0h
ECh
ECh
“Offset ECh: SINT: Signal Target Raw Interrupt Register” on page 1287
00h
F0h
F0h
“Offset F0h: MCID: Message Signalled Interrupt Capability ID Register” on
page 1288
05h
F1h
F1h
“Offset F1h: MCP: Message Signalled Interrupt Next Capability Pointer Register” on
00h
page 1288
F2h
F3h
“Offset F2h: MCTL: Message Signalled Interrupt Control Register” on page 1289
0000h
F4h
F7h
“Offset F4h: MADR: Message Signalled Interrupt Address Register” on page 1289
00000000h
F8h
F9h
“Offset F8h: MDATA: Message Signalled Interrupt Data Register” on page 1290
0000h
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Table 7-60. Bus M, Device 4, Function 0: Summary of CAN Registers Mapped Through
CSRBAR Memory BAR
Offset Start
Offset End
Default
Value
Register ID - Description
00000000h
00000003h
“Offset 00000000h: Int_Status - Interrupt Status Register” on page 1587
00000000h
00000004h
00000007h
“Offset 00000004h: Int_Ebl - Interrupt Enable Register” on page 1588
00000000h
00000008h
0000000Ah
“Offset 00000008h: Buffer Status Indicators” on page 1589
00000000h
0000000Ch
0000000Fh
“Offset 0000000Ch: ErrorStatus - Error Status Indicators” on page 1590
00000000h
00000010h
00000013h
“Offset 00000010h: Command - Operating Modes” on page 1591
00000000h
00000014h
00000017h
“Offset 00000014h: Config - CAN Configuration Register” on page 1592
00000000h
00000020h at 00000023h at “Offset 00000020h: TxMessageControl[0-7] - Transmit Message Control and
10h
10h
Command” on page 1593
XXXXXXXXh
00000024h at 00000027h at
“Offset 00000024h: TxMessageID[0-7] - Transmit Message ID” on page 1595
10h
10h
XXXXXXXXh
00000028h at 0000002Ah at “Offset 00000028h: TxMessageDataHigh[0-7] - Transmit Message Data High” on
10h
10h
page 1596
XXXXXXXXh
0000002Ch at 0000002Fh at “Offset 0000002Ch: TxMessageDataLow[0-7] - Transmit Message Data Low” on
10h
10h
page 1597
XXXXXXXXh
000000A0h at 000000A3h at “Offset 000000A0h: RxMessageControl[0-15] - Receive Message Command and
20h
20h
Control” on page 1598
XXXXXXXXh
000000A4h at 000000A7h at
“Offset 000000A4h: RxMessageID[0-15] - Receive Message ID” on page 1600
20h
20h
XXXXXXXXh
000000A8h at 000000ABh at “Offset 000000A8h: RxMessageDataHigh[0-15] - Receive Message Data High” on
20h
20h
page 1600
XXXXXXXXh
000000ACh at 000000AFh at “Offset 000000ACh: RxMessageDataLow[0-15] - Receive Message Data Low” on
20h
20h
page 1601
XXXXXXXXh
000000B0h at 000000B3h at
“Offset 000000B0h: RxMessageAMR[0-15] - Receive Message AMR” on page 1601 XXXXXXXh
20h
20h
000000B4h at 000000B7h at
“Offset 000000B4h: RxMessageACR[0-15] - Receive Message ACR” on page 1602
20h
20h
XXXXXXXXh
000000B8h at 000000BBh at “Offset 000000B8h: RxMessageAMR_Data[0-15] - Receive Message AMR Data” on
XXXXXXXXh
20h
20h
page 1603
000000BCh at 000000BFh at “Offset 000000BCh: RxMessageACR_Data[0-15] - Receive Message ACR Data” on
XXXXXXXXh
20h
20h
page 1604
Table 7-61. Bus M, Device 5, Function 0: Summary of CAN Registers Mapped Through
CSRBAR Memory BAR (Sheet 1 of 2)
Offset Start
Offset End
Default
Value
Register ID - Description
00000000h
00000003h
“Offset 00000000h: Int_Status - Interrupt Status Register” on page 1587
00000000h
00000004h
00000007h
“Offset 00000004h: Int_Ebl - Interrupt Enable Register” on page 1588
00000000h
00000008h
0000000Ah
“Offset 00000008h: Buffer Status Indicators” on page 1589
00000000h
0000000Ch
0000000Fh
“Offset 0000000Ch: ErrorStatus - Error Status Indicators” on page 1590
00000000h
00000010h
00000013h
“Offset 00000010h: Command - Operating Modes” on page 1591
00000000h
00000014h
00000017h
“Offset 00000014h: Config - CAN Configuration Register” on page 1592
00000000h
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Intel® EP80579 Integrated Processor
Table 7-61. Bus M, Device 5, Function 0: Summary of CAN Registers Mapped Through
CSRBAR Memory BAR (Sheet 2 of 2)
Offset Start
Offset End
Register ID - Description
Default
Value
00000020h at 00000023h at “Offset 00000020h: TxMessageControl[0-7] - Transmit Message Control and
10h
10h
Command” on page 1593
XXXXXXXXh
00000024h at 00000027h at
“Offset 00000024h: TxMessageID[0-7] - Transmit Message ID” on page 1595
10h
10h
XXXXXXXXh
00000028h at 0000002Ah at “Offset 00000028h: TxMessageDataHigh[0-7] - Transmit Message Data High” on
10h
10h
page 1596
XXXXXXXXh
0000002Ch at 0000002Fh at “Offset 0000002Ch: TxMessageDataLow[0-7] - Transmit Message Data Low” on
10h
10h
page 1597
XXXXXXXXh
000000A0h at 000000A3h at “Offset 000000A0h: RxMessageControl[0-15] - Receive Message Command and
20h
20h
Control” on page 1598
XXXXXXXXh
000000A4h at 000000A7h at
“Offset 000000A4h: RxMessageID[0-15] - Receive Message ID” on page 1600
20h
20h
XXXXXXXXh
000000A8h at 000000ABh at “Offset 000000A8h: RxMessageDataHigh[0-15] - Receive Message Data High” on
20h
20h
page 1600
XXXXXXXXh
000000ACh at 000000AFh at “Offset 000000ACh: RxMessageDataLow[0-15] - Receive Message Data Low” on
20h
20h
page 1601
XXXXXXXXh
000000B0h at 000000B3h at
“Offset 000000B0h: RxMessageAMR[0-15] - Receive Message AMR” on page 1601 XXXXXXXh
20h
20h
000000B4h at 000000B7h at
“Offset 000000B4h: RxMessageACR[0-15] - Receive Message ACR” on page 1602
20h
20h
XXXXXXXXh
000000B8h at 000000BBh at “Offset 000000B8h: RxMessageAMR_Data[0-15] - Receive Message AMR Data” on
XXXXXXXXh
20h
20h
page 1603
000000BCh at 000000BFh at “Offset 000000BCh: RxMessageACR_Data[0-15] - Receive Message ACR Data” on
XXXXXXXXh
20h
20h
page 1604
7.4.5
SSP Interface: Bus M, Device 6, Function 0
The SSP interface includes the registers listed in Table 7-62 and Table 7-63. These
registers materialize in PCI configuration and memory (via PCI BAR) spaces. See
Section 35.10, “SSP Controller Configuration Space: Bus M, Device 6, Function 0” and
Table 40.4, “Register Summary” on page 1606 for detailed discussion of these registers
along with alternative materializations.
Table 7-62. Bus M, Device 6, Function 0: Summary of SSP Controller PCI Configuration
Registers (Sheet 1 of 2)
Offset Start
Offset End
Register ID - Description
Default
Value
00h
01h
“Offset 00h: VID: Vendor Identification Register” on page 1292
8086h
02h
03h
“Offset 02h: DID: Device Identification Register” on page 1292
503Bh
04h
05h
“Offset 04h: PCICMD: Device Command Register” on page 1292
0000h
06h
07h
“Offset 06h: PCISTS: PCI Device Status Register” on page 1293
0010h
08h
08h
“Offset 08h: RID: Revision ID Register” on page 1294
Variable
09h
0Bh
“Offset 09h: CC: Class Code Register” on page 1295
078000h
0Eh
0Eh
“Offset 0Eh: HDR: Header Type Register” on page 1295
00h
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Table 7-62. Bus M, Device 6, Function 0: Summary of SSP Controller PCI Configuration
Registers (Sheet 2 of 2)
Offset Start
Offset End
Default
Value
Register ID - Description
13h
“Offset 10h: CSRBAR: Control and Status Registers Base Address Register” on
page 1295
00000000h
2Ch
2Dh
“Offset 2Ch: SVID: Subsystem Vendor ID Register” on page 1296
0000h
2Eh
2Fh
“Offset 2Eh: SID: Subsystem ID Register” on page 1296
0000h
34h
34h
“Offset 34h: CP: Capabilities Pointer Register” on page 1297
DCh
3Ch
3Ch
“Offset 3Ch: IRQL: Interrupt Line Register” on page 1297
00h
3Dh
3Dh
“Offset 3Dh: IRQP: Interrupt Pin Register” on page 1297
01h
DCh
DCh
“Offset DCh: PCID: Power Management Capability ID Register” on page 1298
01h
DDh
DDh
“Offset DDh: PCP: Power Management Next Capability Pointer Register” on
page 1298
E4h
DEh
DFh
“Offset DEh: PMCAP: Power Management Capability Register” on page 1298
0023h
E0h
E1h
“Offset E0h: PMCS: Power Management Control and Status Register” on
page 1299
0000h
E4h
E4h
“Offset E4h: SCID: Signal Target Capability ID Register” on page 1300
09h
E5h
E5h
“Offset E5h: SCP: Signal Target Next Capability Pointer Register” on page 1300
F0h
E6h
E6h
“Offset E6h: SBC: Signal Target Byte Count Register” on page 1300
09h
E7h
E7h
“Offset E7h: STYP: Signal Target Capability Type Register” on page 1301
01h
E8h
E8h
“Offset E8h: SMIA: Signal Target IA Mask Register” on page 1301
00h
ECh
ECh
“Offset ECh: SINT: Signal Target Raw Interrupt Register” on page 1302
00h
F0h
F0h
“Offset F0h: MCID: Message Signalled Interrupt Capability ID Register” on
page 1302
05h
F1h
F1h
“Offset F1h: MCP: Message Signalled Interrupt Next Capability Pointer Register” on
00h
page 1302
F2h
F3h
“Offset F2h: MCTL: Message Signalled Interrupt Control Register” on page 1303
0000h
F4h
F7h
“Offset F4h: MADR: Message Signalled Interrupt Address Register” on page 1303
00000000h
F8h
F9h
“Offset F8h: MDATA: Message Signalled Interrupt Data Register” on page 1304
0000h
10h
Table 7-63. Bus M, Device 6, Function 0: Summary of SSP CSRs
Offset Start
Offset End
Default
Value
Register ID - Description
00h
03h
“Offset 00h: SSCR0 - SSP Control Register 0 Details” on page 1607
00000000h
04h
07h
“Offset 04h: SSCR1 - SSP Control Register 1 Details” on page 1610
00000000h
08h
0Bh
“Offset 08h: SSSR - SSP Status Register Details” on page 1614
0000F004h
0Ch
0Fh
“Offset 0Ch: SSITR - SSP Interrupt Test Register Details” on page 1617
00000000
10h
13h
“Offset 10h: SSDR - SSP Data Register Details” on page 1618
00000000h
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7.4.6
IEEE 1588 Timestamp Unit: Bus M, Device 7, Function 0
The IEEE 1588 Timestamp Unit includes the registers listed in Table 7-64 and
Table 7-65. These registers materialize in PCI configuration and memory (via PCI BAR)
spaces. See Section 35.11, “IEEE 1588 Hardware Assist Unit Configuration Space: Bus
M, Device 7, Function 0” and Chapter 41.0, “Register Summary” for detailed discussion
of these registers along with alternative materializations.
Table 7-64. Bus M, Device 7, Function 0: Summary of IEEE 1588 Timestamp Unit PCI
Configuration Registers
Offset Start
00h
Offset End
01h
Register ID - Description
“Offset 00h: VID: Vendor Identification Register” on page 1306
Default
Value
8086h
02h
03h
“Offset 02h: DID: Device Identification Register” on page 1306
503Ch
04h
05h
“Offset 04h: PCICMD: Device Command Register” on page 1306
0000h
06h
07h
“Offset 06h: PCISTS: PCI Device Status Register” on page 1307
0010h
08h
08h
“Offset 08h: RID: Revision ID Register” on page 1308
Variable
09h
0Bh
“Offset 09h: CC: Class Code Register” on page 1308
111000h
0Eh
0Eh
“Offset 0Eh: HDR: Header Type Register” on page 1309
00h
10h
13h
“Offset 10h: CSRBAR: Control and Status Registers Base Address Register” on
page 1309
00000000h
2Ch
2Dh
“Offset 2Ch: SVID: Subsystem Vendor ID Register” on page 1310
0000h
2Eh
2Fh
“Offset 2Eh: SID: Subsystem ID Register” on page 1310
0000h
34h
34h
“Offset 34h: CP: Capabilities Pointer Register” on page 1310
DCh
3Ch
3Ch
“Offset 3Ch: IRQL: Interrupt Line Register” on page 1311
00h
3Dh
3Dh
“Offset 3Dh: IRQP: Interrupt Pin Register” on page 1311
01h
DCh
DCh
“Offset DCh: PCID: Power Management Capability ID Register” on page 1312
01h
DDh
DDh
“Offset DDh: PCP: Power Management Next Capability Pointer Register” on
page 1312
E4h
DEh
DFh
“Offset DEh: PMCAP: Power Management Capability Register” on page 1313
0023h
E1h
“Offset E0h: PMCS: Power Management Control and Status Register” on
page 1313
0000h
E0h
E4h
E4h
“Offset E4h: SCID: Signal Target Capability ID Register” on page 1314
09h
E5h
E5h
“Offset E5h: SCP: Signal Target Next Capability Pointer Register” on page 1314
F0h
E6h
E6h
“Offset E6h: SBC: Signal Target Byte Count Register” on page 1314
09h
E7h
E7h
“Offset E7h: STYP: Signal Target Capability Type Register” on page 1315
01h
E8h
E8h
“Offset E8h: SMIA: Signal Target IA Mask Register” on page 1315
00h
ECh
ECh
“Offset ECh: SINT: Signal Target Raw Interrupt Register” on page 1316
00h
F0h
F0h
“Offset F0h: MCID: Message Signalled Interrupt Capability ID Register” on
page 1316
05h
F1h
F1h
“Offset F1h: MCP: Message Signalled Interrupt Next Capability Pointer Register” on
00h
page 1317
F2h
F3h
“Offset F2h: MCTL: Message Signalled Interrupt Control Register” on page 1317
0000h
F4h
F7h
“Offset F4h: MADR: Message Signalled Interrupt Address Register” on page 1318
00000000h
F8h
F9h
“Offset F8h: MDATA: Message Signalled Interrupt Data Register” on page 1318
0000h
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Table 7-65. Bus M, Device 7, Function 0: Summary of IEEE 1588 TSYNC CSRs (Sheet 1 of
2)
Offset Start
Offset End
Default
Value
Register ID - Description
00000000h
00000003h
“Offset 0000h: TS_Control Register” on page 1639
00000000h
00000004h
00000007h
“Offset 0004h: TS_Event Register” on page 1641
0022h
00000008h
0000000Bh
“Offset 0008h: TS_Addend Register” on page 1643
0000h
0000000Ch
0000000Fh
“Offset 000Ch: TS_Accum Register” on page 1643
0000h
00000010h
00000013h
“Offset 0010h: TS_Test Register” on page 1644
0000h
00000014h
00000017h
“Offset 0014h: TS_PPS_Compare Register” on page 1646
FFFFFFFFh
00000018h
0000001Bh
“Offset 0018h: TS_RSysTimeLo Register” on page 1647
0000h
0000001Ch
0000001Fh
“Offset 001Ch: TS_RSysTimeHI Register” on page 1648
0000h
00000020h
00000023h
“Offset 0020h: TS_SysTimeLo Register” on page 1649
0000h
00000024h
00000027h
“Offset 0024h: TS_SysTimeHi Register” on page 1650
0000h
00000028h
0000002Bh
“Offset 0028h: TS_TrgtLo Register” on page 1650
0000h
0000002Ch
0000002Fh
“Offset 002Ch: TS_TrgtHi Register” on page 1651
0000h
00000030h
00000033h
“Offset 0030h: TS_ASMSLo Register” on page 1652
0000h
00000034h
00000037h
“Offset 0034h: TS_ASMSHi Register” on page 1653
0000h
00000038h
0000003Bh
“Offset 0038h: TS_AMMSLo Register” on page 1654
0000h
0000003Ch
0000003Fh
“Offset 003Ch: TS_AMMSHi Register” on page 1655
0000h
0040h at 20h
0043h at 20h
“Offset 0040h: TS_Ch_Control[0-7] - Time Synchronization Channel Control
Register (Per Ethernet Channel)” on page 1656
0000h
0044h at 20h
0047h at 20h
“Offset 0044h: TS_CH_EVENT[0-7] - Time Synchronization Channel Event Register
0000h
Per Ethernet Channel)” on page 1658
0048h at 20h
004Bh at 20h
“Offset 0048h: TS_TxSnapLo[0-7] - Transmit Snapshot Low Register (Per Ethernet
0000h
Channel)” on page 1659
004Ch at 20h
004Fh at 20h
“Offset 004Ch: TS_TxSnapHi[0-7] - Transmit Snapshot High Register (Per Ethernet
0000h
Channel)” on page 1660
0050h at 20h
0053h at 20h
“Offset 0050h: TS_RxSnapLo[0-7] - Receive Snapshot Low Register (Per Ethernet
0000h
Channel)” on page 1661
0054h at 20h
0057h at 20h
“Offset 0054h: TS_RxSnapHi[0-7] - Receive Snapshot High Register (Per Ethernet
0000h
Channel)” on page 1662
0058h at 20h
005Bh at 20h
“Offset 0058h: TS_SrcUUIDLo[0-7] - Source UUID0 Low Register (Per Ethernet
Channel)” on page 1663
0000h
005Ch at 20h
005Fh at 20h
“Offset 005Ch: TS_SrcUUIDHI[0-7] - SequenceID/SourceUUID High Register (Per
Ethernet Channel)” on page 1664
0000h
0140h at 10h
0143h at 10h
“Offset 0140h: TS_CANx_Status[0-1] - Time Synchronization Channel Event
Register (Per CAN Channel)” on page 1665
0000h
0144h at 10h
0147h at 10h
“Offset 0144h: TS_CANSnapLo[0-1] - Transmit Snapshot Low Register (Per CAN
Channel)” on page 1666
0000h
0148h at 10h
014Bh at 10h
“Offset 0148h: TS_CANSnapHi[0-1] - Transmit Snapshot High Register (Per CAN
Channel)” on page 1667
0000h
000001F0h
000001F3h
“Offset 01F0h: TS_Aux_TrgtLo Register” on page 1668
0000h
000001F4h
000001F7h
“Offset 01F4h: TS_Aux_TrgtHi Register” on page 1668
0000h
00000200h
00000203h
“Offset 0200h: L2 EtherType Register” on page 1669
000088F7h
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Table 7-65. Bus M, Device 7, Function 0: Summary of IEEE 1588 TSYNC CSRs (Sheet 2 of
2)
Offset Start
0000204h
Offset End
0000207h
Register ID - Description
“Offset 0204h: User Defined EtherType Register” on page 1669
Default
Value
00000000h
00000208h
0000020Bh
“Offset 0208h:User Defined Header Offset Register” on page 1670
00000000h
0000020Ch
0000020Fh
“Offset 020Ch:User Defined Header Register” on page 1670
00000000h
7.4.7
Local Expansion Bus Interface: Bus M, Device 8, Function 0:
The Local Expansion Bus interface includes the registers listed in Table 7-66 and
Table 7-67. These registers materialize in PCI configuration and memory (via PCI BAR)
spaces. See Section 35.12, “Expansion Bus Configuration Space: Bus M, Device 8,
Function 0”, and Table 42.5, “Register Summary” on page 1696 for detailed discussion
of these registers along with alternative materializations.
Table 7-66. Bus M, Device 8, Function 0: Summary of Local Expansion Bus PCI
Configuration Registers (Sheet 1 of 2)
Offset Start
00h
Offset End
01h
Register ID - Description
“Offset 00h: VID: Vendor Identification Register” on page 1320
Default
Value
8086h
02h
03h
“Offset 02h: DID: Device Identification Register” on page 1320
503Dh
04h
05h
“Offset 04h: PCICMD: Device Command Register” on page 1321
0000h
06h
07h
“Offset 06h: PCISTS: PCI Device Status Register” on page 1321
0010h
08h
08h
“Offset 08h: RID: Revision ID Register” on page 1322
Variable
09h
0Bh
“Offset 09h: CC: Class Code Register” on page 1323
068000h
0Eh
0Eh
“Offset 0Eh: HDR: Header Type Register” on page 1323
00h
10h
13h
“Offset 10h: CSRBAR: Control and Status Registers Base Address Register” on
page 1323
00000000h
14h
17h
“Offset 14h: MMBAR: Expansion Bus Base Address Register” on page 1324
00000000h
2Ch
2Dh
“Offset 2Ch: SVID: Subsystem Vendor ID Register” on page 1325
0000h
2Eh
2Fh
“Offset 2Eh: SID: Subsystem ID Register” on page 1325
0000h
34h
34h
“Offset 34h: CP: Capabilities Pointer Register” on page 1326
DCh
3Ch
3Ch
“Offset 3Ch: IRQL: Interrupt Line Register” on page 1326
00h
3Dh
3Dh
“Offset 3Dh: IRQP: Interrupt Pin Register” on page 1326
01h
40h
43h
“Offset 40h: LEBCTL: LEB Control Register” on page 1327
00h
DCh
DCh
“Offset DCh: PCID: Power Management Capability ID Register” on page 1327
01h
DDh
DDh
“Offset DDh: PCP: Power Management Next Capability Pointer Register” on
page 1328
E4h
DEh
DFh
“Offset DEh: PMCAP: Power Management Capability Register” on page 1328
0023h
E1h
“Offset E0h: PMCS: Power Management Control and Status Register” on
page 1329
0000h
E0h
E4h
E4h
“Offset E4h: SCID: Signal Target Capability ID Register” on page 1329
09h
E5h
E5h
“Offset E5h: SCP: Signal Target Next Capability Pointer Register” on page 1330
F0h
E6h
E6h
“Offset E6h: SBC: Signal Target Byte Count Register” on page 1330
09h
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Table 7-66. Bus M, Device 8, Function 0: Summary of Local Expansion Bus PCI
Configuration Registers (Sheet 2 of 2)
Offset Start
Offset End
Default
Value
Register ID - Description
E7h
E7h
“Offset E7h: STYP: Signal Target Capability Type Register” on page 1330
01h
E8h
E8h
“Offset E8h: SMIA: Signal Target IA Mask Register” on page 1331
00h
ECh
ECh
“Offset ECh: SINT: Signal Target Raw Interrupt Register” on page 1331
00h
F0h
F0h
“Offset F0h: MCID: Message Signalled Interrupt Capability ID Register” on
page 1332
05h
F1h
F1h
“Offset F1h: MCP: Message Signalled Interrupt Next Capability Pointer Register” on
00h
page 1332
F2h
F3h
“Offset F2h: MCTL: Message Signalled Interrupt Control Register” on page 1333
0000h
F4h
F7h
“Offset F4h: MADR: Message Signalled Interrupt Address Register” on page 1333
00000000h
F8h
F9h
“Offset F8h: MDATA: Message Signalled Interrupt Data Register” on page 1334
0000h
Table 7-67. Bus M, Device 8, Function 0: Summary of Local Expansion Bus Registers
Mapped Through CSRBAR PCI Memory BAR"
Offset Start
00000000h
Offset End
00000003h
Default
Value
Register ID - Description
“EXP_TIMING_CS0 - Expansion Bus Timing Register” on page 1698
BFFF3C40h
00000004h at 00000007h at
“EXP_TIMING_CS[1-7] - Expansion Bus Timing Registers” on page 1700
4h
4h
00000000h
00000020h
00000020h
“EXP_CNFG0 -Configuration Register 0” on page 1702
00000040h
00000120h
00000123h
“EXP_PARITY_STATUS - Expansion Bus Parity Status Register” on page 1703
00000000h
§§
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IA-32 Core and Integrated Memory
Controller Hub, Volume 2 of 6
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8.0
IA-32 Core
8.1
Overview
The EP80579system-on-a-chip (SoC) uses an IA-32 core, which is based on the Intel®
Pentium® M processor (90 nm). Major features include:
• 600 MHz, 1066 MHz and 1200 MHz operating frequencies
• FSB frequency of 400 MHz and 533 MHz.
• Uni-directional FSB interface (on-chip) for SoC applications
• 32 KByte L1 split instruction and data caches
• 256 KByte 2-way L2 cache with 64B lines
• Soft error protection on L2 cache data and tags (via ECC), soft error protection on
L1 cache data and tags (via parity)
• New CPU identifier (CPUID)
Note the differences between the IA-32 core and the Intel® Pentium® M processor (90
nm) are:
• Core and FSB operating frequencies
• Uni-directional FSB instead of bi-directional
• Different CPU identifier (CPUID)
• Reduced L2 cache size and ways
• De-featured Intel SpeedStep® Technology (no VRM specification required)
8.2
Theory of Operation
This section discusses several operational areas of IA-32 core.
8.2.1
L2 Cache Size
The IA-32 core reduces the size and associativity of the L2 cache on the Pentium M
processor (90 nm)from 2MB 8-way to 256KB 2-way.
8.2.2
Platform and JTAG Identifiers
The Platform ID is a project-specific value. It is used solely for selecting a microcode
update (i.e., patch) and is tightly-coupled to a specific CPUID number. BIOS and OS
software are aware of the Platform ID convention and automatically pick up the
appropriate patch. There are two views to the Platform ID: the MSR view and the Patch
view: The MSR view is a 3-bit value read out of the processor’s FUSE_MSR[52:50]. This
value is determined by three fuses and is unique per CPUID SKU. The Patch view is the
binary value which represents two raised to the power of the MSR view value. A
microcode update is considered applicable to a specific processor if, and only if, the
following condition is true:
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(((Patch.header.cpuid == Processor’s CPUID) &&
((Patch.header.platformID &
2^FUSE_MSR[52:50]) != 0))
The MSR view of the EP80579 Platform ID is 100b. Table 8-1 summarizes the format of
the processor version identification signature (CPUID).
Table 8-1.
Processor Version Identification Signature (CPUID)
31
28
27
20
8.2.3
0
0
0
0
0
0
0
0
0
0
16
1
5
1
4
Extended
Model
Extended Family
0
19
0
0
0
0
1
1
3
1
2
11
Typ
e
0
0
0
0
8
7
Model
Number
Family
0
1
1
4
0
0
1
0
3
0
Stepping
ID
1
0
0
0
0
FSB Physical Interface
The IA-32 core replaces the standard bi-directional, tri-state FSB interface found on the
Pentium M processor (90nm) with a uni-directional interface. This uni-directional
interface is better suited for SoC applications that use a single core. This modification
replaces a single bi-directional wire with two uni-directional wires.
8.2.4
IA-32 Core and FSB Frequency
The EP80579 is targeted to operate with IA-32 core frequencies of 600 MHz, 1066 MHz
and 1200 MHz and FSB frequencies of 400 MHz (600 MHz SKU) and 533 MHz (1066
MHz and 1200 MHz SKUs).
§§
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9.0
CMI Introduction
This section details the system architecture supported by the Memory Controller Hub
and I/O Controller Hub complex. The Memory Controller Hub and I/O Controller Hub
are referred to collectively as the CMI (IMCH and ICH).
Subsequent chapters cover the following aspects of the MCH and the ICH:
• Description of the CMI architecture.
• Descriptions of internal registers.
• Descriptions of all external interfaces.
The EP80579 is a single chip that integrates the functionality of an IA-32 core, Memory
Controller Hub, and an I/O Controller Hub (see Figure 9-1). In this document the
Memory Controller Hub and I/O Controller Hub in CMI are referred to as IMCH
(Integrated Memory Controller Hub) and IICH (Integrated I/O Controller Hub)
respectively. The IMCH and IICH units are connected internally through the NSI (North
South Interface). The NSI is an internal bus that is not externally accessible.
Figure 9-1.
CMI Block Diagram
DDR2 – (400, 533, 667, 800)
Unbuffered and Registered
ECC
1X8 PCI Express
Configurable as
2X4, 2x1
x8
4 channel
EDMA
IMCH
Memory
Controller
SMBus
2 DIMM Max,
2 Ranks Max
NSI
LPC Bus
2 CH SATA
2 UART’s
36 GPIOs
RTC
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IICH
2 USB-2.0
WDT
SMBus
SPI
Interrupts
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9.1
System Architecture
CMI implements numerous RASUM (Reliability, Availability, Serviceability, Usability and
Manageability) features on multiple interfaces.
The IMCH and IICH consist of:
• A Memory Controller.
• A four-channel, descriptor-chain-based Enhanced DMA (EDMA) controller.
• Several I/O devices such as USB, SATA, etc.
• One x8 PCI Express* interface, which may be split into a pair of independent x4 or
x1 PCI Express* interfaces.
Desired I/O Controller Hub (IICH) functions are integrated eliminating the requirement
for a legacy I/O bridge.
CMI also supports:
• Two USB 2.0/1.1 ports
• Two SATA ports Gen1/Gen2
• One LPC bus
• One SPI port
• Two UART port
• Two SMBus ports
For additional information see Section 11.3, “Configurations” on page 291.
9.2
PCI Express*
CMI provides one configurable x8 PCI Express interface with a maximum theoretical
bandwidth of 4 GByte/s (aggregate). The x8 PCI Express interface may alternatively be
configured as two independent x4 or x1 PCI Express interfaces.
CMI is a root-class component as defined in the PCI Express* Interface Specification,
Rev 1.0a. The PCI Express interfaces support connection of CMI to a variety of other
bridges compliant with the same revision of the PCI Express* Interface Specification,
Rev 1.0a. For example, the Intel® 82571EB Gigabit Ethernet adaptor and the Intel PCI
Express I/O processor are directly supported on any of these PCI Express ports. Other
compatible PCI Express devices implement functionality such as graphics, hardware
RAID controllers and TCP/IP off-load engines. These devices are available from Intel
and/or third-party vendors.
As required by the interface specification, CMI will automatically negotiate for and train
a single lane (x1) link if an attached device on any logical port fails to establish a viable
x4 or x8 connection. This does not imply a capability for CMI to support more than two
independent PCI Express ports of any width simultaneously on the x8 port, nor does it
imply that the remaining three lanes of a potential x4 port are useful once the
associated link has been established for x1 operation. Similarly, CMI will automatically
negotiate for and train a single lane (x1) link if an attached device on any logical port
fails to establish a viable x4 connection.
External bridge devices such as PCI or PCI-X Gigabit Ethernet or RAID storage devices
are directly supported on the PCI Express ports. This does not preclude connection of
the IMCH to other bridges compliant with the same revision of the PCI Express
Interface Specification.
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9.2.1
Supported PCI Express Configurations
CMI PCI Express ports are setup using a configuration register. This register is
“DEVPRES” BDF 000, Offset 9Ch, Bits 2 and 3 which control Device 2 and Device 3
present.
Table 9-1 shows all of the valid combinations of this register.
Table 9-1.
Supported PCI Express Configurations
DEVPRES
DEV2 En,
DEV3 En
DEV2 En,
DEV3 Dis
DEV2 Dis,
DEV3 En
DEV2 Dis,
DEV3 Dis
AUTO Negotiate
1x8,
2x4,
lower 1x4,
upper 1x4
1x8,
lower 1x4
Not supported
All Disabled
2x4
2x4
lower 1x4
upper 1x4
All Disabled
1x8
1x8
1x8
Not supported
All Disabled
Strap
9.2.1.1
Low power SKU with PCI Express ports removed
To enable low power SKU for configurations that do not utilize the PCI Express ports,
the user can disable PCI Express ports and configuration bits for power savings.
9.3
Supported Debug and Management Interfaces
The IMCH supports a target SMBus interface for access and control of the IMCH
through its configuration registers. A Test Access Port (TAP) interface is also supported
for IMCH system debug purposes. The TAP is capable of full read/write access to the
entire internal IMCH register space.
Platforms based on CMI may also make use of the Inter-Chassis Management Bus
(ICMB) architecture to extend SMBus based management throughout a desegregate
multi-chassis platform solution.
9.4
Supported IMCH Integrated Features
This section provides a brief overview of internal IMCH features. The subsections are
intended for use as an introduction and a quick reference. See Section 9.5 for more
detailed descriptions of these features.
9.4.1
EDMA Controller
The IMCH includes an integrated four-channel Enhanced Direct Memory Access (EDMA)
controller to perform background data transfers between locations in main memory, or
from main memory to a memory-mapped I/O destination. These transfers may be
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individually designated to be coherent (snooped on the FSB) or non-coherent (not
snooped on the FSB), providing improvements in system performance and utilization
when cache coherence is managed by software rather than hardware.
Each of the four channels implements an independent set of configuration and status
registers, and is capable of fully independent operation. Each channel may operate in a
single block transfer mode, or a hardware traversed linked-list scatter/gather mode.
The internal EDMA controller only supports transfers between main memory locations,
and transfers from a main memory source to an I/O subsystem destination. The
internal EDMA controller supports neither transfers between I/O interfaces, nor
transfers from an I/O interface source to a main memory destination.
9.4.2
Integrated Memory Init/Test Engine
The IMCH provides hardware-managed ECC memory auto-initialization and testing of
all populated DRAM space under software control. Once internal configuration has been
updated to reflect the type and size of populated DIMM, the IMCH can traverse the
populated address space issuing line-sized writes of all zero data, thereby initializing all
locations with good ECC memory. This greatly speeds up the mandatory memory
initialization step and frees the CPU to pursue other machine initialization and
configuration tasks.
Additional features have been added to the initialization engine to support high-speed
population and verification of a programmable memory range with one of eight known
data patterns, random data, a walking data pattern, or an explicitly specified cache line
(data plus ECC). This function facilitates a limited high-speed memory test and
provides BIOS-accessible memory testing capability for potential use by management
code or by the operating system.
For additional information see Section 11.2, “Memory Controller Feature List” on
page 289.
9.4.3
Coherent Memory Write Buffer
The IMCH includes an integrated coherent write buffer sized for 16 64-byte cache lines
(a total of 1 Kbyte of storage). This feature enables the IMCH to optimize memory read
latency, allowing reads to pass less critical writes en-route to the main memory store.
The write buffer includes a CAM structure to enforce ordering among conflicting
accesses to the same cache line, as well as to provide for read service from the write
cache. In the latter case, the access to the main memory store never occurs, which
both improves latency and conserves bandwidth on the memory interface.
The write buffer is capable of servicing processor read requests directly via a “hit” to
the internal location containing the data without initiation of any DDR subsystem
accesses. Inbound read requests such as PCI Express, i.e. not processor, which “hit”
the write buffer result in a flush of the target data, followed by retrieval via an external
read request.
Processor writes to shared non-coherent address space with the ASU result in a flush of
the current cacheline to main memory. ASU atomics will result in a DW write to the ASU
out of the write cache.
9.4.4
RASUM Features
The IMCH is designed to bring enterprise-level reliability, availability, serviceability,
usability, and manageability to the embedded platform. All internal SRAM memory
arrays are covered by parity. CMI’s PCI Express interface supports detection and
automatic recovery for all transient signaling errors. All IMCH internal configuration
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register space is accessible from the system management bus (SMBus) to facilitate
system management. The IMCH supports ACPI power management, PCI Express native
hot-plug, and wake-from-LAN to maximize platform stand-by flexibility.
9.4.4.1
SEC-DED ECC
The IMCH supports a standard (72-bit, non-interleaved) single error correction (SEC)
and double error detection (DED) ECC mechanism for the DDR memory.
The IMCH supports both ECC and non-ECC DIMMs.
For additional information see Section 11.2, “Memory Controller Feature List” on
page 289.
9.4.4.2
Integrated Memory Scrub Engine
The IMCH includes an integrated engine to walk the populated memory space
proactively seeking out soft errors in the memory subsystem. This hardware detects,
logs, and corrects any single-bit ECC errors it encounters, and logs any uncorrectable
errors it encounters. Both types of errors may be reported via multiple alternate
mechanisms under configuration control. The scrub hardware will also execute
“demand scrub” writes when correctable errors are encountered during normal
operation (on demand reads, rather than scrub-initiated reads). This functionality
provides incremental protection against time-based deterioration of soft memory errors
from correctable to uncorrectable.
An uncorrectable error encountered by the memory scrub engine is a “speculative
error.” This designation is applied because no system agent has specifically requested
use of the corrupt data, and no real error condition exists in the system until that
occurs. It is possible that the error resides in an unmodified page of memory that is
simply dropped on a swap back to disk. If that were to occur, the speculative error
would simply “vanish” from the system without any adverse consequences.
9.5
IMCH Feature List
This section provides an overview of the major IMCH architectural features. Detailed
usage information and operational flows, internal register bit information and other
specific details of the implementation are provided later in this document.
9.5.1
Memory Interface
For additional information see Section 11.2, “Memory Controller Feature List” on
page 289.
9.5.2
PCI Express Interface in IMCH
• Support for one x8 PCI Express dual-simplex, high-speed serial I/O interface with
eight striped differential pairs in each direction (outbound and inbound)
— The interface may be unpopulated; connected to PCI, Ethernet, I/O Processor,
Infiniband* bridge devices, External bridge devices (PCI or PCI-X Gigabit
Ethernet or RAID storage devices); or connected to any other device compliant
with the same revision of the PCI Express Specification as CMI.
— The x8 interface is capable of bifurcation into two logically independent x4
interfaces with full specification compliance at half the bandwidth capability
• This interface is referred to throughout this document as the PCI Express Port A
(PEA). When configured as x8, the reference is PEA. When in x4 mode there are
two available x4 ports referred to as PEA0 and PEA1.
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• Raw bit-rate on the data pins of 2.5 Gbit/s.
— Maximum theoretical realized bandwidth on the x8 PCI Express interface of 2
GByte/s in each direction simultaneously, for an aggregate of 4 GByte/s.
— Maximum theoretical realized bandwidth on the x4 PCI Express interface of 1
GByte/s in each direction simultaneously, for an aggregate of 2 GByte/s per
port.
— x8 sustainable data bandwidth is approximately 1.6 GByte/s in each direction
simultaneously
• Plesiochronous operation with automatic clock extraction and phase correction at
the receiver.
• Hierarchical PCI-compliant configuration mechanism for downstream devices
— Support for PCI Express memory-mapped enhanced configuration mechanism,
up to 4 Kbyte per device.
• 64 bit addressing support.
— 64 bit upstream addressing (full DAC support), limited to 32 bits internally to/
from system memory (external DDR).
— 32 bit downstream addressing support.
— Full 36 bit support for peer segment accesses.
Note:
Only 32-bit addresses can be snooped. Addresses larger than 32 bits will be truncated.
e.g. If a 36-bit address is snooped the upper 4 bits are ignored.
• Full-speed interface self-test and diagnostic (IBIST) functionality.
• Automatic discovery, negotiation, and training of PCI Express ports out of reset.
— Automatic detection of widest operational link; x8, x4 or x1.
• No support for Hot-plug via an external SMBus connected device.
• Run-time detection and recovery for loss of link synchronization.
• 32 bit CRC (cyclic redundancy checking) on all transaction layer packets with linklevel retry on error (recovery from transient errors without software-visible system
failure).
• 16 bit CRC on all link message information
• No support for the optional extended CRC (ECRC) mechanism
• Aggressive transceiver design to facilitate flexible system topologies
• Target BER of 10-12 for physical signaling interface
• Support for peer segment destination write traffic (no peer-to-peer read traffic)
• Support for coherent and non-coherent transactions through EDMA to PEA to
external agent
• Support for both coherent and non-coherent traffic to memory within VC#0
— Non-coherent implies a combination of Snoop-Not-Required and RelaxedOrdering attributes
— Coherent traffic implies a combination of Snoop-Required and Strong-Ordering
attributes.
• Support for lane reversal at all native widths, and for reversed x4 training on any
x8 port
• Support for peer segment PCI interrupt forwarding to the IICH for boot from I/O
— Legacy mode support for level-sensitive interrupt emulation without IOxAPIC
support
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• APIC and MSI interrupt messaging support DMA internal score-boarding to
translate messages into level-sensitive IICH pin semantics
— XTPR-based interrupt redirection for APIC messages with lowest priority tie
breaking
• Support for up to 256B read completion combining
• Support for link messaging to facilitate active link and device power state
management
• Support for ASPM L0s entry, no support for optional L1 ASPM support
• No support for inbound configuration or I/O traffic
• No support for inbound special cycles or writes requiring completions
• No support for downstream special cycle messages requiring completions
9.5.3
EDMA Controller
• Four Independent Channels
— Dedicated data transfer queue per channel
— Full register set for descriptor and transfer handling per channel
• Support for transfer between main memory locations, and from memory to the I/O
subsystem
• Supports PCI Express traffic class to allow external prioritization of traffic
• Supports transfers only between two Physical Addresses
— 32 bit (4 GB) addressing range on the Local System Memory Interface
— 32 bit addressing range on the Memory Mapped I/O Subsystem Interface
• Maximum transfer of 16 Mbyte transfers per block
• Fully programmable by the host CPU
— Configuration space mapping for DMA engine capability and control
— Memory-mapped space for DMA channel-specific register sets
• Chain mode DMA transfer with automatic data chaining for scattering/gathering of
data blocks
— DMA chaining continued until a “null” Descriptor Pointer is encountered
— Support for appending a block to the end of current DMA chain
— Automated descriptor retrieval from DDR during chaining – single read
• Programmable independent alignment between source and destination
— Byte aligned transfer on the DDR Memory Interface
— Byte aligned transfer on the I/O Subsystem Interface
• Support for non-coherent transfers both to and from system memory on a per
descriptor basis
— Independent control of coherency for source and destination
• Programmable support for interrupt generation on block–by-block basis
— Selectable MSI or legacy level-sensitive interrupt function
— End of current block transfer
— End of current chain
— For any error causing a transfer to abort
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• Increment of the source and destination address for standard transfers
• Increment of the destination and decrement of the source address to enable byte
stream reversal.
• Constant address mode for the destination address based on the transfer
granularity to enable targeting of memory mapped I/O FIFO devices
• Buffer/Memory Initialization Mode
9.5.4
Coherent Memory Write Buffer
• Support for 16 64-byte cache-lines of write data
• Fully associative conflict detection for accesses targeting memory
• Read around write support (non-conflicting) for all traffic to memory
• Read-hit support for CPU traffic to memory
— Direct data service from buffer without generation of memory traffic
• Write-hit support for memory traffic with address conflicts
— Hardware-based merging to collapse down to a single memory write
• Opportunistic and demand (buffer full) mode processing of pending writes
— Configurable “watermark” mechanism for hardware-based prioritization
— Flush on demand via software configuration mechanism
• Parity protection on all data
• Data poisoning capability in the main store for data received with errors
• Processor writes to shared non-coherent address space with the ASU result in a
flush of the current cacheline to main memory
• ASU atomics will result in a DW write to the ASU out of the write cache
9.5.5
Integrated Memory Scrub Engine
For additional information see Section 11.2, “Memory Controller Feature List” on
page 289.
• Periodic (programmable) read-modify-write algorithm
• Support for the SEC-DED mode of operation
• Automatic correction of encountered SEC errors
• Logging of detected errors with granularity to isolate DRAM device
— Support for logging of both first and next subsequent error
— Count of errors beyond the first two which are logged
• Support for on-demand hardware scrub of SEC errors detected during normal
operation
• Programming interface permits software suspend/resume of scrub in progress
9.5.6
Hardware Memory Initialization Engine
• Available via BIOS for hardware memory initialization and/or test
• Provides fast WHQL initialization of all populated DRAM space to “0” with good ECC
• Target region may be a single location, an entire rank, or all populated ranks
• Algorithm optimized for speed, runs at DDR channel saturation rate
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• Test extensions permit high-speed population of a target range with a known
pattern
— Selectable hardware-generated fixed patterns: 0, 3, 5, 6, 9, A, C, F
— Hardware generated random pattern capability
— Explicitly stipulated data pattern including ECC
• High speed verification capability
— Selectable write-only, verify-only, or write-read-verify per location
— Logs error location, optional stop and escalate on error detection
• May be made available to the operating system via BIOS for security “clear to 0”
function
9.5.7
System Management Functions
• Full SMBus target support
• Support for remote chassis management via the ICMB architecture
• Serial presence detect of memory devices via standard I2C protocol (accessed via
IICH)
• ACPI and PCI-PM compatible power management
— Includes PME support comprehending PCI Express extensions
• MSI interrupt messaging and redirection support
• Hardware relay of PCI Express legacy mode PCI interrupt messages to IICH
— Supports boot from I/O when IOxAPIC functions are unavailable
9.5.8
RASUM
• SEC/DED ECC protection of external memory DRAM data
• Parity protection on internal data propagated through the IMCH
• CRC on data packets and hardware link-level retry on NSI to the IICH
• 32-bit CRC on data packets and hardware link-level retry on PCI Express ports
• Hardware memory initialization
— True “clear-to-zero” via hardware writes to all populated devices
— Support for hardware-based fast initialization of memory with selectable
patterns
— Support for hardware-based fast verification of memory via accelerated scrub
• Hardware periodic memory scrubbing, including demand scrub support
• Flexible extended error reporting capabilities
• Configurable error containment at I/O interfaces (poison/propagate or stop/
escalate)
• Partial access to internal configuration registers via the TAP port
• Full access to internal configuration registers via SMBus port
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9.6
IICH Feature List
This section provides a listing of architectural functionality for the major features of the
IICH. Detailed usage information and operational flows, internal register bit
information, and other specific details of the implementation are provided later in this
document.
9.6.1
Low-Pin count (LPC) Interface and Firmware Hub (FWH)
Interface
• Allows connection of devices such as Super I/O, micro controllers, customer ASICs.
• Supports two master/DMA devices.
• Memory size up to 8 Mbit.
9.6.2
Serial Peripheral Interface (SPI)
Note:
Intel recommends using the SPI as your boot interface.
• Supports multiple SPI Flash vendors.
• Simplified Hardware.
• Equivalent to LPC-based Firmware Hubs.
9.6.3
Integrated Serial ATA Host Controllers
• Independent DMA operation on two ports.
— Two ports in SATA 1.0a and AHCI mode.
— Two ports in AHCI mode only.
• Data transfer rates up to 300 Mbyte/s.
• Support Gen2m electrical spec (cable not exceeding 2m).
9.6.4
USB
• One EHCI USB 2.0 Host Controller with a total of two ports (shared with the UHCI
ports).
• One UHCI Host Controller for a total of two ports (shared with the EHCI ports).
• Supports a Debug Port at USB 2.0 transfer rates.
9.6.5
Interrupt Controller
• Supports up to 8 PCI interrupt pins.
• Two cascaded 82C59 with 15 interrupts.
• Integrated I/O APIC supports a total of 40 interrupts (24 interrupts only, when
ETR3.GPIO_IRQ_STRAP_STS is 0).
• Serial Interrupt input for ISA legacy-compatible and PCI interrupts.
• Supports PCI scheme for delivering interrupts as write cycles (rather than via
PIRQ[A-H]#).
• Front-Side Message Interrupt Delivery.
• Supports EOI message.
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9.6.6
Power Management Logic
Power management logic for various environments require updates.
• ACPI 2.0 Compliant.
• Support for APM-based legacy power management for non-ACPI implementations.
• Supports ACPI defined power states S0, S1, S3 cold, S4 and S5 (SOFF).
• ACPI Power Management Timer.
• SMI# Generation.
• PCI PME#.
9.6.7
DMA Controller
• Two cascaded 8237 DMA Controllers.
• Supports LPC DMA.
9.6.8
Timers Based on 82C54
• System Timer, Refresh Request, Speaker Tone Output.
9.6.9
High Precision Event Timers (HPET)
• Three timer comparators provided.
• One-shot and periodic interrupts supported.
9.6.10
Real-Time Clock with 256-byte Battery-backed CMOS RAM
• Integrated components for the oscillator to reduce problems with incorrect external
selections.
• Lower Power DC/DC Converter implementation.
9.6.11
System TCO Reduction Circuits
• Timers to detect improper CPU reset and to generate SMI# and Reset upon
detection of stuck CPU.
• Interrupt capability to OS-specific manageability extension and OS capability to call
TCO BIOS.
• Supports CPU BIST.
• Ability to disable external devices.
9.6.12
SMBus
• Host interface allows CPU to communicate via SMBus.
• Compatible with most 2-wire components that are also I2C compatible.
• Slave interface allows internal or external microcontroller to access system
resources.
• SMBus 2.0 Compliant.
• No ASF support.
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9.6.13
Watchdog Timer
• Selectable Prescaler:
— Approximately 1 MHz (1 µs to 1 s).
— Approximately 1 KHz (1 ms to 10 min.)
• 33 MHz Clock (30 ns Clock Ticks).
• Multiple Modes (WDT and Free-Running).
• Free-Running Mode:
— One Stage Timer.
— Toggles WDT_TOUT# after programmable time.
• WDT Mode:
— Two Stage Timer (First Stage generates Interrupt, Second Stage drives
WDT_TOUT# low).
— First Stage generates an SERIRQ, NMI or SMI interrupt after Programmable
time.
— Second Stage drives WDT_OUT# low or inverts the previous value.
— Used only after first timeout occurs.
— Status bit preserved in RTC well for possible error detection and correction.
— Drives WDT_TOUT# if OUTPUT is enabled.
• Timer can be disabled (default state) or Locked (Hard Reset required to disable
WDT).
• WDT Automatic Reload of Preload value when WDT Reload Sequence is performed.
9.6.14
Serial Port
• Two Full Function 16550 Compatible Serial Ports.
• Configurable I/O addresses and interrupts.
• 16-Byte FIFOs.
• Supports up to 115 Kbps.
• Programmable Baud Rate Generator.
• Modem Control Circuitry.
• 14.7456 MHz and 48 MHz supported for UART baud clock input.
9.6.15
GPIO
• General Purpose I/Os .
• There are 36 GPIO pins of which 5 have alternate power on functions.
§§
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10.0
System Address Map
10.1
Overview
The IA-32 core addressable memory map is 32 bits or up to 4 GBytes and has
64 KBytes+3 of addressable I/O space. The I/O and memory spaces are divided by
system configuration software into non-overlapping regions. The memory ranges are
useful either as system memory or as specialized memory, while the I/O regions are
used solely to control the operation of devices in the system.
There are five basic regions of memory in the system. The regions are shown in
Table 10-1. Figure 10-1 illustrates the basic memory regions.
Table 10-1. Regions of Memory Ranges
Range
Description
Between top of main memory and 64 GBytes
High PCI Memory Range
Between 4 GBytes and top of main memory
Between TOLM Register and 4 GBytes
Low PCI Memory Address Range
Between 1 MByte and the TOLM Register
Main Memory Address Range
Below 1 MByte
DOS Legacy Address Range
Figure 10-1. Basic Memory Regions
64 GB
Additional Main
Memory Address
Range
4 GB
Lo PCI Memory
Address Range
Top of Low Memory
APIC, PCI Express, and
NSI, non overlapping
windows
Main Memory
Address Range
1 MB
DOS Legacy
AddressRange
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10.1.1
System Memory Spaces
Table 10-2. System Memory Space
From
To
DOSMEM
0_0000_0000
0_0009_FFFF
MEM1_15
0_0010_0000
0_00EF_FFFF
MAINMEM
0_0100_0000
TOLM
HIGHMEM
1_0000_0000
7_FFFF_FFFF
Table 10-2’s address ranges are always mapped to system memory, regardless of the
system configuration. The Top of Low Memory (TOLM) register (see Section 16.1.1.30,
“Offset C4h: TOLM - Top of Low Memory Register”) provides a mechanism to carve
memory out of the MAINMEM segment for use by System Management Mode (SMM)
hardware and software, PCI add-in devices, and other functions. The address of the
highest 128 MByte quantity of populated DRAM memory in the system is placed into
the DRB3 register, which will match the value in the Top of Memory (TOM) register (see
Section 16.1.1.34, “Offset CCh: TOM - Top Of Memory Register”.
10.1.2
VGA and MDA Memory Spaces
Table 10-3 lists the VGA and MDA Memory spaces. Figure 10-2 illustrates the DOS
legacy Region.
Table 10-3. IMCH VGA and MDA Memory Spaces
From
To
VGAA
0_000A_0000
0_000A_FFFF
MDA
0_000B_0000
0_000B_7FFF
VGAB
0_000B_8000
0_000B_FFFF
These legacy address ranges are used on behalf of video cards to map a frame buffer or
a character-based video buffer into a dedicated location. By default, accesses to these
ranges are forwarded to the NSI. However, if the VGAEN bit is set in one of the BCTRL
configuration registers (see Section 16.4.1.26, “Offset 3Eh: BCTRL - Bridge Control
Register”), then transactions within the VGA and MDA spaces are sent to one of the PCI
Express interfaces in IMCH.
Note:
The VGAEN bit may be set in one and only one of the BCTRL registers. Software must
not set more than one VGAEN bit.
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Figure 10-2. DOS Legacy Region
1MB
10 0000h
Upper, Lower,
Expansion Card B IOS
and Buffer Area
0C0000h
C ontrolled
PAM[6:0].
by
768 KB
VGAB
0B8000h
Standard PCI/ISA
Video Mem ory
(SMM Mem ory)
0B0000h
M onchrom e Display
A dapter Space
736 KB
704 KB
C ontrolled
by
VGA Enable and
M DA enable.
VGAA
0A0000h
640 KB
Key
= Optionally DRAM
= DRAM
If the configuration bit EXSMRC.MDAP (see Section 16.1.1.25, “Offset 9Dh: EXSMRC Extended System Management RAM Control Register”) is set, then accesses that fall
within the MDA range are sent to NSI without regard for the VGAEN bits. Legacy
support requires the ability to have a second graphics controller (monochrome display
adapter) in the system. In a CMI system with PCI graphics installed via a PCIe to PCI
bridge like PXH, accesses in the standard VGA range may be forwarded to any of the
logical PCI Express ports (depending on configuration bits). Since the monochrome
adapter may be on the NSI (or logical ISA) bus, the IMCH must decode cycles in the
MDA range and forward them to NSI. This capability is controlled via the MDAP
configuration bit. In addition to the memory range B0000h to B7FFFh, the IMCH
decodes I/O cycles at 3B4h, 3B5h, 3B8h, 3B9h, 3BAh and 3BFh and forwards them to
NSI.
An optimization allows the system to reclaim the memory displaced by these regions. If
SMM memory space is enabled by EXSMRC.G_SMRAME and either the SMRAM.D_OPEN
bit (see Section 16.1.1.25, “Offset 9Dh: EXSMRC - Extended System Management RAM
Control Register” and Section 16.1.1.26, “Offset 9Eh: SMRAM - System Management
RAM Control Register”) is set or the processor bus receives an SMM-encoded request
for code (not data), then the transaction is steered to system memory rather than NSI.
Under these conditions, both the VGAEN bits and the MDAP bit are overridden.
If any VGAEN bit is set, then all ISAEN bits (see Section 16.4.1.26, “Offset 3Eh: BCTRL
- Bridge Control Register”) must be set. The PCI Specification defines VGAEN to be 10bit decode. Therefore the other peer bridges must also be 10-bit decodes (ISAEN), so
that two or more devices don't claim same access. (Bridge C doesn't know bridge B has
its VGAEN bit set.)
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The MDA bit may only be set when one of the VGAEN bits is set. If no VGAEN bit is set,
then MDA must not be set either. When the VGA range is already mapped onto the NSI
interface, the MDA range is included as a subset, and the MDA enable is meaningless.
10.1.3
PAM Memory Spaces
The Address range for the PAM memory space is defined in Table 10-4.
Table 10-4. IMCH PAM Memory Address Ranges
From
To
PAMC0
0_000C_0000
0_000C_3FFF
PAMC4
0_000C_4000
0_000C_7FFF
PAMC8
0_000C_8000
0_000C_BFFF
PAMCC
0_000C_C000
0_000C_FFFF
PAMD0
0_000D_0000
0_000D_3FFF
PAMD4
0_000D_4000
0_000D_7FFF
PAMD8
0_000D_8000
0_000D_BFFF
PAMDC
0_000D_C000
0_000D_FFFF
PAME0
0_000E_0000
0_000E_3FFF
PAME4
0_000E_4000
0_000E_7FFF
PAME8
0_000E_8000
0_000E_BFFF
PAMEC
0_000E_C000
0_000E_FFFF
PAMF0
0_000F_0000
0_000F_FFFF
Access Region
ISA Expansion
(16KB/each)
Extended BIOS
(16KB/each)
System BIOS
(64KB)
The 256 Kbyte Programmable Access Memory (PAM) region is divided into three parts:
• ISA expansion region, a 128 Kbyte area between 0_000C_0000h – 0_000D_FFFFh.
• Extended BIOS region, a 64 Kbyte area between 0_000E_0000h – 0_000E_FFFFh.
• System BIOS region, a 64 Kbyte area between 0_000F_0000h – 0_000F_FFFFh.
Specialized programmable hardware in the IMCH supports routing of read and write
accesses within the PAM region independently to memory or to NSI.
Non-snooped transactions are treated accordingly:
• Non-snoop Reads: Memory address 0h. The result is an unsupported request (UR)
completion.
• Non-snoop Writes: Memory address 0h with byte enables deasserted.
The ISA expansion region is divided into eight 16 Kbyte segments. Each segment can
be assigned one of four Read/Write memory states: read-only, write-only, read/write,
or disabled. These segments are typically set to disabled for memory access, which
leaves them routed to NSI for ISA space.
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The extended System BIOS region is divided into four 16 Kbyte segments. Each
segment can be assigned independent read and write attributes so it can be mapped
either to main DRAM or to NSI. Typically, this area is used for RAM or ROM.
The system BIOS region is a single 64 Kbyte segment. This segment can be assigned
independent memory read and write attributes. It is by default (after reset) Read/Write
disabled and cycles are forwarded to NSI. By manipulating the Read/Write attributes,
the IMCH can “shadow” BIOS into the main DRAM. The term “shadow” is used to
describe the condition where ROM memory has been duplicated into main memory;
such that reads are serviced from memory, while writes are directed back to the
original ROM device. Such a configuration allows low-latency reads of BIOS information
from the ROM while preventing malicious or inadvertent alteration of the BIOS
information in use.
Note:
The PAM regions are generally inaccessible from the logical PCI Express ports. All
inbound writes from any port that hit the PAM regions are sent to NSI, which prevents
corruption of non-volatile data shadowed in main memory. All inbound reads from any
port that hit the PAM regions are harmlessly terminated internally; data is returned,
but not necessarily from the requested address. Transaction routing is not hardware
enforced based on the settings in the PAM configuration registers.
Note:
The PAM regions are inaccessible from the logical AIOC port. All inbound reads/writes
from any port that hit the PAM regions are master aborted by the AIOC preventing
them from ever pushed into the IMCH.
Figure 10-3. Memory Region from 1 MByte through 4 GBytes
High BIOS, Optional
Extended SMRAM
1_0000_0000 (4GB)
Key
FF00_0000
=
NSI (always)
=
Region allowed for MMIO below 4GB
=
DRAM Region
=
Optional DRAM Region
FEF0_0000
Local APIC Space
FEE0_0000
Unused I/O APIC
Space
FEC8_6000
FEC8_2000
PEA I/O APIC Space
FEC8_0000
NSI I/O APIC Space
PCI Express Enanced
Config. Aperture
FEC0_0000
F000_0000
E000_0000
Top of Low Memory (TOLM)
TSEG SMRAM Space
TOLM - TSEG
0100_0000 (16 MB)
ISA Hole
00F0_0000 (15 MB)
0010_0000 (1MB)
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The IMCH allows programmable memory attributes on 13 legacy memory segments of
various sizes in the 768 Kbyte to 1 Mbyte (C0000h – FFFFFh) and 640 Kbytes to 1
Mbyte address range. Seven Programmable Attribute Map (PAM) registers are used to
support these features. Not all seven of these registers are identical. PAM0 controls
only one segment (high), while PAM[1:6] each control two segments (high and low).
Cache ability of these areas is controlled via the MTRR registers in the processor. The
following two bits apply to both host accesses and PCI initiator accesses to the PAM
areas and are used to specify the memory attributes for each memory segment: These
bits apply to both host accesses and PCI initiator accesses to the PAM areas
RE
Read Enable. When RE = 1, the IA-32 core read accesses to the
corresponding memory segment are claimed by the IMCH and
directed to main memory. Conversely, when RE = 0, the host
read accesses are directed to the IICH’s PCI bus.
WE
Write Enable. When WE = 1, the host write accesses to the
corresponding memory segment are claimed by the IMCH and
directed to main memory. Conversely, when WE = 0, the host
write accesses are directed to the IICH’s PCI bus.
Together, these two bits specify memory attributes (Read-Only, Write Only, Read/Write
and Disabled) for each memory segment. These bits only apply to host-initiated access
to the PAM areas. The IMCH forwards to main memory any PCI Express initiated
accesses to the PAM areas. At the time such PCI Express accesses to the PAM region
may occur, the targeted PAM segment must be programmed to Read/Write. It is illegal
to issue a PCI Express initiated transaction to a PAM region with the associated PAM
register not set to Read/Write.
As an example, consider a BIOS that is implemented on the expansion bus. During the
initialization process, BIOS can be shadowed to main memory to increase system
performance. When BIOS is shadowed to main memory it must be copied to the same
address location. To shadow the BIOS, the attributes for that address range must be
set to Write-Only. The BIOS is shadowed by first doing a read of that address, which is
forwarded to the expansion bus. The host then writes the same address, which is
directed to main memory. After BIOS is completely shadowed, the attributes for that
memory area are changed to Read-Only so that all writes are forwarded to the
expansion bus. Figure 10-4 and Table 10-5 show the PAM registers and the associated
attribute bits.
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Figure 10-4. PAM Associated Attribute Bits
H I S e g m e nt
O ffse t
L O S e g m e nt
PAM6
PAM5
5F h
5Eh
PAM4
5Dh
PAM3
5Ch
PAM2
PAM1
5Bh
5 Ah
R es erve d
PAM0
5 9h
7
6
5
4
3
2
1
0
R
R
WE
RE
R
R
WE
RE
R es erve d
R ea d E nab le (R /W )
1 = E na b le
0 = D is ab le
R e se rve d
W rite E na b le (R /W )
1 = E nab le
0 = D isa b le
W rite E nab le (R /W )
1 = E na b le
0 = D is ab le
R e se rved
R e ad E na b le (R /W )
1 = E na b le
0 = D is ab le
R e se rve d
Table 10-5. PAM Associated Attribute Bits
PAM Reg
Attribute Bits
Memory Segment
Comments
D0:F0 Offset
Reserved
—
Reserved
59h
0F0000h–0FFFFFh
BIOS Area
59h
—
Reserved
5Ah
PAM0 03:00, 07:06
PAM0 05:04
WE
PAM1 03:02, 07:06
RE
Reserved
PAM1 01:00
WE
RE
0C0000h–0C3FFFh
BIOS Area
5Ah
PAM1 05:04
WE
RE
0C4000h–0C7FFFh
BIOS Area
5Ah
—
Reserved
5Bh
RE
0C8000h–0CBFFFh
BIOS Area
5Bh
RE
0CC000h–0CFFFFh
BIOS Area
5Bh
—
Reserved
5Ch
PAM2 03:02, 07:06
Reserved
PAM2 01:00
WE
PAM2 05:04
WE
PAM3 03:02, 07:06
Reserved
PAM3 01:00
WE
RE
0D0000h–0D3FFFh
BIOS Area
5Ch
PAM3 05:04
WE
RE
0D4000h–0D7FFFh
BIOS Area
5Ch
—
Reserved
5Dh
RE
0D8000h–0DBFFFh
BIOS Area
5Dh
RE
0DC000h–0DFFFFh
BIOS Area
5Dh
—
Reserved
5Eh
PAM4 03:02, 07:06
Reserved
PAM4 01:00
WE
PAM4 05:04
WE
PAM5 03:02, 07:06
Reserved
PAM5 01:00
WE
RE
0E0000h–0E3FFFh
BIOS Extension
5Eh
PAM5 05:04
WE
RE
0E4000h–0E7FFFh
BIOS Extension
5Eh
PAM6 03:02, 07:06
—
Reserved
5Fh
PAM6 01:00
WE
RE
0E8000h–0EBFFFh
BIOS Extension
5Fh
PAM6 05:04
WE
RE
0EC000h–0EFFFFh
BIOS Extension
5Fh
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See Section 16.1.1.17, “Offset 59h: PAM0 - Programmable Attribute Map 0 Register”
through Section 16.1.1.23, “Offset 5Fh: PAM6 - Programmable Attribute Map 6
Register” for more register information on PAM memory space registers.
10.1.4
TSEG SMM Memory Space
Table 10-6. TSEG SMM Memory Space
TSEGSMM
From
To
TOLM - TSEG
TOLM
The TSEG SMM space allows system management software to partition a region of main
memory just below the top of low memory (TOLM) that is accessible only by system
management software.
Size
128kB, 256kB, 512kB, or 1 MByte in size, depending upon the
EXSMRC.TSEG_SZ field (see Section 16.1.1.25).This space
must be below 4 GBytes, so it is specified relative to TOLM and
not relative to the top of physical memory.
Enabling
SMM memory is globally enabled by EXSMRC.G_SMRAME (see
Section 16.1.1.25). Requests may access SMM system memory
when either SMM space is open (see SMRAM.D_OPEN in
Section 16.1.1.26) or the IMCH receives an SMM code request
on its processor bus.
Access
In order to access the TSEG SMM space, the TSEG must be
enabled by EXSMRC.T_EN (Section 16.1.1.25). When all of
these conditions are met, then a processor bus access to the
TSEG space (between TOLM-TSEG and TOLM) is sent to system
memory. If the high SMRAM is not enabled or if the TSEG is not
enabled, then all memory requests from all interfaces are
forwarded to system memory. If the TSEG SMM space is
enabled, and an agent attempts a non-SMM access to TSEG
space, then the transaction is specially terminated.
Inbound accesses from NSI or PCI Express ports are not allowed to access SMM space.
10.1.5
PCI Express Enhanced Configuration Aperture
Table 10-7. PCI Express Enhanced Configuration Aperture
HECREGION
From
To
0_E000_0000
0_EFFF_FFFF
PCI Express defines a memory-mapped aperture mechanism through which to access 4
Kbyte of PCI configuration register space for each possible bus, device, and function
number. This 4 Kbyte space includes the compatible 256 B of register offsets that are
traditionally accessed via the legacy CF8/CFC configuration aperture mechanism in I/O
address space, making the enhanced configuration mechanism a full superset of the
legacy mechanism. The enhanced mechanism has the advantage that full destination
and type of access is specified in a single memory-mapped uncacheable transaction on
the FSB, which is both faster and more robust than the historical I/O-mapped address
and data register access pair.
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CMI places the enhanced configuration aperture at E000_0000h by default, as this is
the first contiguous 256 MByte location below the 4 GByte boundary available for such
usage.
CMI provides for relocation of this aperture via the HECBASE register (see Section
16.1.1.35, “Offset CEh: HECBASE - PCI Express Port A (PEA) Enhanced Configuration
Base Address Register”, although validation of moving the region is minimal.
10.1.6
IOAPIC Memory Space
Table 10-8. IOAPIC Memory Space
From
To
IOAPIC0 (NSI)
0_FEC0_0000
0_FEC7_FFFF
IOAPIC2 (PEA0)
0_FEC8_0000
0_FEC8_0FFF
IOAPIC3 (PEA1)
0_FEC8_1000
0_FEC8_1FFF
The IOAPIC spaces are used to communicate with IOAPIC interrupt controllers that
may be populated on NSI through PCI-Express port A (PEA). Since it is difficult to
relocate an interrupt controller using plug-and-play software, fixed address decode
regions have been allocated for them. Processor accesses to the IOAPIC0 region are
always sent to NSI. Processor accesses to the IOAPIC2 region are always sent to PEA.
These regions are subject to the APIC disable, which are cleared by BIOS after the
allocated regions have been reflected down to the base registers of APIC controllers
discovered during standard enumeration. Until this step of the initialization sequence
has been performed, accesses to these regions are treated as subtractive decode and
routed to NSI.
The IMCH does not support an IOAPIC range for the EDMA controller or the AIOC, since
there is no IOxAPIC device or corresponding register set integrated into the EDMA
controller or the AIOC.
10.1.7
FSB Interrupt Memory Space
Table 10-9. FSB Interrupt Memory Space
FSBINTR
From
To
0_FEE0_0000
0_FEEF_FFFF
The FSB Interrupt space is the address range used to deliver interrupts to the FSB. Any
device below AIOC, NSI or a PCI Express port may issue a Memory Write to
0FEEx_xxxxh. The IMCH will forward this Memory Write along with its associated data
to the FSB as a Message Signaled Interrupt (MSI) transaction. The IMCH terminates
the FSB transaction by asserting TRDY# and providing the response. This Memory
Write cycle does not go to DRAM.
Reads to this address range are aborted by the IMCH.
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10.1.8
High SMM Memory Space
Table 10-10. High SMM Memory Space
HIGHSMM
From
To
0_FEDA_0000
0_FEDB_FFFF
The HIGHSMM space allows cacheable access to the compatible SMM space by
remapping valid SMM accesses between 0_FEDA_0000 and 0_FEDB_FFFF to physical
accesses between 0_000A_0000 and 0_000B_FFFF. The accesses are remapped when
SMRAM space is enabled, an appropriate access is detected on the processor bus, and
when EXSMRC.H_SMRAME (Section 16.1.1.25) allows access to high SMRAM space.
Inbound SMM memory accesses from any port are specially terminated; reads are
provided with data retrieved from address 0, while writes are ignored entirely (all byte
enables deasserted).
10.1.9
PCI Device Memory (MMIO)
The IMCH provides two distinct regions of memory that may be mapped to populated
PCI devices. The first is the traditional (non-prefetchable) MMIO range, which must lie
below the 4 GByte boundary. The registers associated with non-prefetchable MMIO
(MBASE/MLIMIT, see Section 16.4.1.17, “Offset 20h: MBASE - Memory Base Address
Register”/Section 16.4.1.18, “Offset 22h: MLIMIT - Memory Limit Address Register”)
are unchanged from historical 32-bit architecture IMCH implementations. The second is
the prefetchable MMIO range, which has been extended in CMI such that it may lie on
either side of the 4 GByte boundary. The registers associated with prefetchable MMIO
(PMBASE/PMLIMIT, see Section 16.4.1.19, “Offset 24h: PMBASE - Prefetchable Memory
Base Address Register”/Section 16.4.1.20, “Offset 26h: PMLIMIT - Prefetchable
Memory Limit Address Register”) have been augmented by the PCI defined upper 32bit base/limit register pair (PMBASU/PMLMTU, see Section 16.4.1.21, “Offset 28h:
PMBASU - Prefetchable Memory Base Upper Address Register”/Section 16.4.1.22,
“Offset 2Ch: PMLMTU - Prefetchable Memory Limit Upper Address Register”), although
only the first nibble of each register is implemented in the IMCH.
The MBASE/MLIMIT pair must be programmed to lie between TOLM and 4 GBytes. The
PMBASE/PMLIMIT and PMBASU/PMLMTU registers must be programmed to lie between
TOLM and 4 GBytes.
Because these registers define a PCI memory space, they are subject to the memory
access enable (MAE) control bit in the standard PCI command register (see Section
16.4.1.4, “Offset 04h: PCICMD - PCI Command Register”).
Note:
Using the same address space as both cacheable and non cacheable is discouraged.
Also, assigning and writing the same host address space to two independent
downstream devices is also discouraged. Although not illegal, both of the above
conditions are very difficult to setup intelligently and validate. If 2 devices decide to use
the same memory space, and they both send write cycles to it (both either cacheable
or uncacheable), there are no guarantees that device 1 data (being older) will get there
before device 2 data (being newer) if they do not use a flagging mechanism.
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10.1.9.1
Device 2 Memory and Prefetchable Memory
Table 10-11. Device 2 Memory and Prefetchable Memory
From
To
M2
MBASE2
MLIMIT2
PM2
PMBASE2/PMBASU2
PMLIMIT2/PMLMTU2
Plug-and-play software configures the PEA a memory window in order to provide
enough memory space for the devices behind this virtual PCI-to-PCI bridge. Accesses
whose addresses fall within these windows are decoded and forwarded to PEA0 for
completion. Note that neither region should overlap with any other fixed or relocateable area of memory. Also note that PCICMD2 refers to PCICMD for device 2.
10.1.9.2
Device 3 Memory and Prefetchable Memory
Table 10-12. Device 3 Memory and Prefetchable Memory
From
To
M3
MBASE3
MLIMIT3
PM3
PMBASE3/PMBASU3
PMLIMIT3/PMLMTU3
Plug-and-play software configures the PEA1 memory window in order to provide
enough memory space for the devices behind this virtual PCI-to-PCI bridge. Accesses
whose addresses fall within this window are decoded and forwarded to PEA1 for
completion. Note that neither region should overlap with any other fixed or relocateable area of memory. Also note that PCICMD3 refers to PCICMD for device 3.
Note:
If PCI Express Port A0 is configured to operate in x8 mode, all functional space for PEA1
disappears; effectively collapsing M3/PM3 to match the limit addresses of M2/PM2.
10.1.9.3
Device 4 Memory and Prefetchable Memory
Table 10-13. Device 4 Memory and Prefetchable Memory
From
To
M4
MBASE4
MLIMIT4
PM4
PMBASE4/PMBASU4
PMLIMIT4/PMLMTU4
Plug-and-play software configures the PCI memory window in order to provide enough
memory space for the devices behind this virtual PCI-to-PCI bridge. Accesses whose
addresses fall within this window are decoded and forwarded to PCI for completion.
Note that neither region should overlap with any other fixed or relocate-able area of
memory. Also note that PCICMD4 refers to PCICMD for device 4.
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10.2
IMCH Responses to EDMA Transactions
In the following tables, the term “Abort” implies that the EDMA engine will immediately
stop the transfer in progress. The offending access will not be forwarded to the
inbound/outbound arbiter at all, an error bit will be set accordingly, and the error will
be escalated as specified by the configuration bits controlling interrupts and errors.
Note:
This behavior is quite different from the and PCI Express inbound ports, as in the latter
cases the transaction in question was requested by some other initiator elsewhere in
the platform. The EDMA engine is a source of traffic all by itself, which makes error
containment much simpler in the case of EDMA traffic.
10.2.1
Fixed Address Spaces (EDMA)
Table 10-14 summarizes IMCH responses to EDMA accesses to the various fixed
address spaces.
Table 10-14. EDMA Accesses to Fixed Address Spaces
Address
Space
Conditions
Destination
DOSMEM
-
MainMem
Transaction is sent to memory system
VGAA
VGAB
MDA
PAMC0…
PAMF0
-
Abort
Programmer’s responsibility not to target
EDMA accesses in the legacy region
between 640KB and 1 MByte
MEM1_15
-
MainMem
Transaction is sent to memory system
FDHC.HEN = 0
MainMem
Hole Disabled: Transaction is sent to
memory system
FDHC.HEN = 1
Abort
Hole Enabled: EDMA will abort on accesses
directed to the ISA hole when enabled
MAINMEM
-
MainMem
Transaction is sent to memory system
(unless address hits an enabled TSEG SMM
range. See TSEGSMM)
TSEGSMM
-
Variable
Refer to Table 10-16, “Supported SMM
Ranges”.
IOAPIC[0,2-3]
-
Abort
Programmer’s responsibility to avoid the
APIC ranges
FSBINTR
-
Abort
Programmer’s responsibility to avoid the
FSB interrupt messaging range
HIGHSMM
-
Variable
Refer to Table 10-16, “Supported SMM
Ranges”.
MainMem
Transaction is sent to memory system.
HIGHMEM
Address is below the top of
memory space defined by
TOM and the REMAP
registers
Address is above the top of
memory
Abort
Hardware will detect an attempt to access
above the populated DRAM space, and will
abort.
ISA15
10.2.2
IMCH Response
Relocatable Address Spaces (EDMA)
Table 10-15 summarizes IMCH responses to EDMA accesses to the various relocatable
address spaces.
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Note:
EDMA access is not permitted to the port, thus any address mapping to the legacy
interface will cause an abort.
Table 10-15. EDMA Accesses to Relocatable Address Spaces
Address
Space
NSI: M
NSI: PM
PEA: M[n]
PEA: PM[n]
NSI_SUB
PEA:
PM[n]
10.3
Conditions
Destination
IMCH Response
-
Abort
No support for EDMA destination on NSI
Write, MAE = 1
PEA[n]
Transaction forwarded to destination PEA
port.
Write, MAE = 0
Abort
Abort. Memory access disabled.
Read Transaction
Abort
Abort. No support for peer segment reads.
-
Abort
No support for EDMA destination on NSI
Write, MAE = 1
PEA[n]
Transaction forwarded to destination PEA
port.
Write, MAE = 0
Abort
Abort. Memory access disabled.
Read Transaction
Abort
Abort. No support for peer segment reads.
I/O Address Space
The IMCH generates outbound transactions on behalf of all IA-32 core I/O accesses.
The IMCH contains two internal registers in the IA-32 core I/O space dedicated to the
configuration access mechanism; the Configuration Address Register
(CONFIG_ADDRESS) and the Configuration Data Register (CONFIG_DATA). The
behavior of the IMCH in response to accesses to these registers is described in
Chapter 13.0, “Platform Configuration.”
The IA-32 core allows 64 K+3 bytes to be addressed within the I/O space. The IMCH
propagates the IA-32 core I/O address without any translation to the targeted
destination bus. Note that the upper three locations can be accessed only during I/O
address wrap-around; when signal A16# is asserted on the processor bus. A16# is
asserted on the processor bus whenever a Dword I/O access is made from address
0FFFDh, 0FFFEh, or 0FFFFh. In addition, A16# is asserted when software attempts a
two-byte I/O access from address 0FFFFh.
All I/O accesses (read or write) which do not map to internal IMCH registers will receive
a DEFER response on the FSB, and be forwarded to the appropriate outbound port. The
IMCH never posts an I/O write.
The IMCH never responds to inbound transactions to I/O or configuration space
initiated on any port. Inbound I/O or configuration transactions requiring a completion
are terminated with “master abort” completion packets on the originating port
interface. Inbound I/O or configuration write transactions not requiring completion are
dropped.
10.3.1
Configuration Window
The I/O addresses 0CF8h and 0CFCh are treated specially, as they define the
compatible configuration window. Dword accesses to 0CF8h address the internal IMCH
configuration address register. Accesses from 1 to 4 bytes in size to the region from
0CFC-0CFFh are treated as configuration data accesses if configuration space is
enabled (bit31 of the configuration address register is set). Refer to Chapter 13.0,
“Platform Configuration.” for further details.
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10.3.2
VGA and MDA Regions
Along with the memory space address regions described in Section 10.1.2, “VGA and
MDA Memory Spaces”, there are fixed I/O locations associated with both the VGA and
the MDA regions. Accesses to these addresses are routed to NSI by default, but this
behavior may be modified via the VGAEN, MDAP and MAE configuration settings. Refer
to the prior sections for the rules associated with the configuration settings of VGAEN,
MDAP and MAE.
The MDA region includes I/O space addresses 3B4h, 3B5h, 3B8h, 3B9h, 3BAh and
3BFh. The VGA region includes I/O space ranges 3B0-3BBh, and 3C0-3DFh. The PCI
Specification defines both MDA and VGA to be 10-bit address decode, thus all accesses
with A[9:0] matching any of these addresses are subject to the associated routing
rules. Address bits A[15:10] are ignored when the check against these fixed addresses
are applied.
The order of precedence for the routing checks is as follows:
• MAE = 0, MDA addresses will route to NSIif MDAP is set, overriding any VGAEN.
• MAE = 1, MDA addresses will route to the Peer device if MDAP is set, overriding any
VGAEN.
• MAE = 0, VGA addresses will route to the NSI.
• MAE = 1, VGA addresses will route to the PCI Express port with its VGAEN set, if
any.
• MAE = 0, MDA addresses which fall within VGA regions will route to the NSI if MDAP
is clear.
• MAE = 1, MDA addresses which fall within VGA regions will follow VGAEN if MDAP is
clear.
• Both VGA and MDA addresses default to NSI if MDAP and all VGAEN bits are clear.
Note:
Setting of MDAP or any of the VGAEN bits implies that the ISAEN bit is also set in all
virtual P2P bridges, because of the 10-bit decode requirement.
Note:
AIOC access to this space is not supported. Upstream attempted accesses to this space
are programming errors and will result in a master abort.
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10.4
Main Memory Addressing
The “High Memory” and “Extended Memory” address regions are together called “Main
Memory.” Main memory is composed of address segments that refer to DDR SDRAM
system memory. Main memory addresses are mapped to DDR SDRAM channels,
devices, banks, rows, and columns in different ways depending upon the type of
memory being used and upon the density or organization of the memory. The process
for determining the device and channel IDs for addressed devices is as follows:
• The requested address is compared against the values of all eight DRB registers.
The number of the register whose programmed value is greater than the address
and whose previous register is less than the address is the output of the
comparison.
• The value of the DRB register “below” is subtracted from the address in order to
determine the offset into the group.
• The offset determines the manner in which the row, column, and bank address bits
are extracted from the address.
10.5
System Management Mode (SMM) Space
CMI supports the use of main memory as System Management RAM (SMM RAM)
enabling the use of System Management Mode. The IMCH supports three SMM options:
• Compatible SMRAM (C_SMRAM)
• High Segment (HSEG)
• Top of Memory Segment (TSEG)
System Management RAM space provides an access protected memory area that is
available for SMI handler code and data storage. This memory resource is normally
hidden from the Operating System so that the processor has immediate access to this
memory space upon entry to SMM (cannot be swapped-out).
10.5.1
SMM Addressing Ranges
IMCH provides three SMRAM options:
• Below 1 MByte option that supports compatible SMI handlers.
• Above 1 MByte option that allows new SMI handlers to execute with write-back
cacheable SMRAM.
• Optional larger write-back cacheable T_SEG area from 128 Kbyte to 1 MByte in
size. The above 1 MByte solutions require changes to compatible SMRAM handler
code to properly execute above 1 MByte.
Note:
The first two options both map legal accesses to the same physical range of memory,
while the third defines an independent region of addresses.
10.5.1.1
SMM Space Restrictions
If any of the following conditions are violated, the results of SMM accesses are
unpredictable and may cause the system to hang:
• The Compatible SMM space must not be set-up as cacheable.
• Both D_OPEN and D_CLOSE must not be set to 1 at the same time.
• When TSEG SMM space is enabled, the TSEG space must not be reported to the OS
as available DRAM. This is a BIOS responsibility.
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BIOS and SMM code must cooperate to properly configure the IMCH in order to ensure
reliable operation of the SMM function.
10.5.1.2
SMM Space Definition
SMM space is defined by both its addressed SMM space and its DRAM SMM space. The
addressed SMM space is defined as the range of FSB addresses used by the IA-32 core
to access SMM space. DRAM SMM space is defined as the range of physical DRAM
memory locations containing SMM information.
The SMM space can be accessed at one of three transaction address ranges:
• Compatible
• High
• TSEG
The Compatible and TSEG SMM space is not remapped and therefore the addressed
and DRAM SMM physical addresses are identical. The High SMM space is remapped;
thus the addressed and DRAM SMM locations are different. Note that the High DRAM
space is the same as the Compatible Transaction Address space.
Table 10-16 describes all three unique addressing combinations:
• Compatible Transaction Address
• High Transaction Address
• TSEG Transaction Address
Table 10-16. Supported SMM Ranges
SMM Space Enabled
Transaction Address Space (Adr)
DRAM Space (DRAM)
Compatible (C)
A0000h to BFFFFh
A0000h to BFFFFh
High (H)
0FEDA0000h to 0FEDBFFFFh
A0000h to BFFFFh
TSEG (T)
(TOLM-TSEG_SZ) to TOLM
(TOLM-TSEG_SZ) to TOLM
Notes:
1.
High SMM: This implementation is consistent with the Intel E7500 and Intel E7501 designs. In prior
MCH designs the High segment was the 384 Kbyte region from A_0000h to F_FFFFh. However
C_0000h to F_FFFFh was not useful, so it has been deleted in the IMCH design.
2.
TSEG SMM: This implementation is consistent with the Intel E7500 and Intel E7501 designs. In prior
MCH designs the TSEG address space was offset by 256 MBytes to allow for simpler decoding and the
TSEG was remapped to just under the TOLM. In the IMCH the TSEG region is not offset by 256 MBytes
and it is not remapped.
3.
In Cases where DRAM TOLM is less than TOM TSEG cannot be used for SMM. For this case MENC
memory spans consecutive space from above TOLM to below TOLM and will conflict with TSEG space
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10.6
Memory Reclaim Background
The following Memory Mapped I/O devices and ranges are typically located below 4
GBytes:
• High BIOS
• H-Seg
• XAPIC
• Local APIC
• FSB Interrupts
• PEA0 through PEA1 M, PM and BAR regions
In previous generation MCH architectures, the physical DRAM memory overlapped by
the logical address space allocated to these Memory Mapped I/O devices was unusable.
In server systems the memory allocated to memory mapped I/O devices could easily
exceed 1 GByte. This creates the possibility of a large amount of physical memory
populated in the system becoming unusable.
The IMCH provides the capability to reclaim the physical memory overlapped by the
Memory Mapped I/O logical address space via remapping physical memory from the
Top of Low Memory (TOLM) boundary up the 4 GBytes boundary (or TOM if less than 4
GBytes) to an equivalent sized logical address range located just above the top of
physical memory
10.6.1
Memory Remapping Algorithm
Note:
The IA-32 core is not capable of using the remap capability and care must be taken to
ensure that no addresses sent to the IA-32 core are greater than TOLM in that it will
cause aliasing. The remap capability can be utilized by the AIOC, IICH and PCIe ports.
Terminology clarification:
Physical Address
The address presented to the IMCH is traditionally called a
“physical address,” because Intel architecture processors
contain both segmentation and paging hardware, and all
compatible software differentiates between logical addresses,
virtual addresses, and physical addresses. The algorithm for
remapping addresses presented to the IMCH to reclaim DRAM
address space must be implemented such that the mechanism
is invisible to compatible software.
System Address
The system address applies to the internal IMCH interface to
physical DRAM memory, and is not directly visible to software,
other than through certain internal logging registers used to
store decoded DRAM address information for error isolation.
An incoming address (referred to as a physical address) is checked to see if it falls in
the memory remap window. The bottom of the remap window is defined by the value in
the REMAPBASE register (see Section 16.1.1.31, “Offset C6h: REMAPBASE - Remap
Base Address Register”). The top of the remap window is defined by the value in the
REMAPLIMIT register (Section 16.1.1.32, “Offset C8h: REMAPLIMIT – Remap Limit
Address Register”). An address that falls within this window is remapped to the physical
memory starting at the address defined by the TOLM register.
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10.7
IICH Register and Memory Mappings
This section covers CMI’s IICH various address decoding ranges.
This section is for background purposes, and must not to be considered by
implementers and validators as part of the behavioral definition of CMI. Each decode
range is described elsewhere in the section associated with the corresponding function.
10.7.1
I/O Map
The I/O map is divided into separate types. Fixed ranges cannot be moved, but in some
cases can be disabled. Variable ranges can be moved and can also be disabled.
10.7.1.1
Fixed I/O Address Ranges
Table 10-17 shows the Fixed I/O decode ranges from the IA-32 core perspective. Note
that for each I/O range, there may be separate behavior for reads and writes. Cycles
that go to target ranges that are marked as Reserved will not be decoded, and are
passed to PCI to PCI Bridge where they are dropped.
Address ranges that are not listed or marked reserved are NOT positively decoded by
the IICH (unless assigned to one of the variable ranges). In subtractive mode, I/O
ranges that are not otherwise decoded are forwarded to PCI to PCI Bridge where they
are dropped.
Table 10-17. Fixed I/O Ranges Decoded by IICH (Sheet 1 of 3)
I/O Address
Read Target
Write Target
Internal Unit
Separate
Enable/
Disable
00h – 08h
DMA Controller
DMA Controller
DMA
None
09h – 0Eh
RESERVED
DMA Controller
DMA
None
0Fh
DMA Controller
DMA Controller
DMA
None
10h – 18h
DMA Controller
DMA Controller
DMA
None
19h – 1Eh
RESERVED
DMA Controller
DMA
None
1Fh
DMA Controller
DMA Controller
DMA
None
20h – 21h
Interrupt Controller
Interrupt Controller
Interrupt
None
24h – 25h
Interrupt Controller
Interrupt Controller
Interrupt
None
28h – 29h
Interrupt Controller
Interrupt Controller
Interrupt
None
2Ch – 2Dh
Interrupt Controller
Interrupt Controller
Interrupt
None
2E – 2F
LPC SIO
LPC SIO
Forwarded to LPC
Yes
30h – 31h
Interrupt Controller
Interrupt Controller
Interrupt
None
34h – 35h
Interrupt Controller
Interrupt Controller
Interrupt
None
38h – 39h
Interrupt Controller
Interrupt Controller
Interrupt
None
3Ch – 3Dh
Interrupt Controller
Interrupt Controller
Interrupt
None
40h – 42h
Timer/Counter
Timer/Counter
PIT (8254)
None
43h
RESERVED
Timer/Counter
PIT
None
4E – 4F
LPC SIO
LPC SIO
Forwarded to LPC
Yes
50h – 52h
Timer/Counter
Timer/Counter
PIT
None
53h
RESERVED
Timer/Counter
PIT
None
60h
Microcontroller
Microcontroller
Forwarded to LPC
Yes w/ 64h
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Table 10-17. Fixed I/O Ranges Decoded by IICH (Sheet 2 of 3)
I/O Address
Read Target
Write Target
Internal Unit
Separate
Enable/
Disable
61h
NMI Controller
NMI Controller
IA-32 core Interface
None
62h
Microcontroller
Microcontroller
Forwarded to LPC
Yes w/ 66h
63h
NMI Controller1
NMI Controller1
IA-32 core Interface
Yes, alias to 61h
64h
Micocontroller
Microcontroller
Forwarded to LPC
Yes w/ 60h
IA-32 core Interface
Yes, alias to 61h
Forwarded to LPC
Yes w/ 62h
IA-32 core Interface
Yes, alias to 61h
RTC
None
Controller1
Controller1
65h
NMI
66h
Microcontroller
Microcontroller
67h
NMI Controller
1
Controller1
70h
RESERVED
NMI
NMI
NMI and RTC Controller
71h
RTC Controller
RTC Controller
RTC
None
72h
RTC Controller
NMI and RTC Controller
RTC
Yes, w/ 73h
73h
RTC Controller
RTC Controller
RTC
Yes, w/ 72h
74h
RTC Controller
NMI and RTC Controller
RTC
None
75h
RTC Controller
RTC Controller
RTC
None
76h
RTC Controller
NMI and RTC Controller
RTC
None
77h
RTC Controller
RTC Controller
RTC
None
80h
DMA Controller, or LPC
DMA Controller, or LPC
DMA
None
81h – 83h
DMA Controller
DMA Controller
DMA
None
84h – 86h
DMA Controller
DMA Controller and LPC
DMA
None
87h
DMA Controller
DMA Controller
DMA
None
88h
DMA Controller
DMA Controller and LPC
DMA
None
89h – 8Bh
DMA Controller
DMA Controller
DMA
None
8Ch – 8Eh
DMA Controller
DMA Controller and LPC
DMA
None
8Fh
DMA Controller
DMA Controller
DMA
None
90h – 91h
DMA Controller
DMA Controller
DMA
Yes, alias to 8xh
92h
Reset Generator
Reset Generator
IA-32 core Interface
None
93h – 9Fh
DMA Controller
DMA Controller
DMA
Yes, alias to 8xh
A0h – A1h
Interrupt Controller
Interrupt Controller
Interrupt
None
A4h – A5h
Interrupt Controller
Interrupt Controller
Interrupt
None
A8h – A9h
Interrupt Controller
Interrupt Controller
Interrupt
None
ACh – ADh
Interrupt Controller
Interrupt Controller
Interrupt
None
B0h – B1h
Interrupt Controller
Interrupt Controller
Interrupt
None
B2h – B3h
Power Management
Power Management
Power Management
None
B4h – B5h
Interrupt Controller
Interrupt Controller
Interrupt
None
B8h - B9h
Interrupt Controller
Interrupt Controller
Interrupt
None
BCh – BDh
Interrupt Controller
Interrupt Controller
Interrupt
None
C0h – D1h
DMA Controller
DMA Controller
DMA
None
D2h – DDh
RESERVED
DMA Controller
DMA
None
DEh – DFh
DMA Controller
DMA Controller
DMA
None
170h – 177h
SATA
SATA
SATA
Yes
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Table 10-17. Fixed I/O Ranges Decoded by IICH (Sheet 3 of 3)
I/O Address
Read Target
Write Target
Internal Unit
Separate
Enable/
Disable
1F0h – 1F7h
SATA
SATA
SATA
Yes
200 – 207h
Gameport Low
Gameport Low
Forwarded to LPC
Yes
208 – 20Fh
Gameport High
Gameport High
Forwarded to LPC
Yes
376h
SATA
SATA
SATA
Yes
3F6h
SATA
SATA
SATA
Yes
4D0h – 4D1h
Interrupt Controller
Interrupt Controller
Interrupt
None
CF9h
Reset Generator
Reset Generator
IA-32 core Interface
None
Notes:
1.
Only if the Port 61 Alias Enable bit (GCS.P61AE) bit is set. Otherwise, the target is dropped.
2.
10.7.1.2
Variable I/O Decode Ranges
Table 10-18 shows the Variable I/O Decode Ranges. They are set using Base Address
Registers (BARs) or other configuration bits in the various configuration spaces. The
PnP software (PCI or ACPI) can use their configuration mechanisms to set and adjust
these values.
Warning:
The Variable I/O Ranges must not be set to conflict with the Fixed I/O Ranges. If the
configuration software allows conflicts to occur, it may produce unpredictable results.
There are no checks for conflicts.
Table 10-18. Variable I/O Decode Ranges
Range Name
Mappable
Size (Bytes)
Target
ACPI
Anywhere in 64K I/O Space
64
Power Management
USB #1
Anywhere in 64K I/O Space
(See Note 1)
32
USB1 Host Controller 1
SMBus
Anywhere in 64K I/O Space
32
SMB Unit
TCO
96 bytes above ACPI base
32
TCO Unit
GPIO
Anywhere in 64K I/O space
64
GPIO Unit
Parallel Port
3 ranges in 64K I/O Space
82
LPC Peripheral
Serial Port 1
8 Ranges in 64K I/O Space
8
LPC Peripheral
Serial Port 2
8 Ranges in 64K I/O Space
8
LPC Peripheral
Floppy Disk Controller
2 Ranges in 64K I/O Space
8
LPC Peripheral
LPC Generic 1
Anywhere in 64K I/O Space
128
LPC Peripheral
LPC Generic 2
Anywhere in 64K I/O Space
16
LPC Peripheral
I/O Trapping Ranges
Anywhere in 64K I/O Space
1 to 256 Bytes
Trap on Internal I/O Data Bus
Notes:
1.
These ranges are decoded directly.
2.
There is also an alias 400h above the parallel port range that is used for ECP parallel ports.
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10.7.2
Memory Map
Table 10-19 shows (from the IA-32 core perspective) the memory ranges that are
decoded. Cycles that arrive that are not directed to any of the internal memory targets
that decode (see Table 10-19)are dropped.
Software must not attempt locks to the IICH’s memory-mapped I/O ranges for USB
2.0, and HPET (High Precision Event Timer). If attempted, the lock is not honored
which means potential deadlock conditions may occur.
Table 10-19. IICH Memory Decode Ranges (from IA-32 core Perspective)
Memory Range
Target
Dependency/Comments
000E0000 - 000EFFFF
FWH
Bit 6 in FWH Decode Enable Register is set.
Bit 7 in FWH Decode Enable Register is set
000F0000 - 000FFFFF
FWH
FEC00000 - FEC0 0040
I/O(x)APIC inside IICH
FFC0 0000 - FFC7 FFFF
FF80 0000 - FF87 FFFF
FWH
Bit 8 in FWH Decode Enable Register
FFC8 0000 – FFCF FFFF
FF88 0000 - FF8F FFFF
FWH
Bit 9 in FWH Decode Enable Register
FFD0 0000 - FFD7 FFFF
FF90 0000 - FF97 FFFF
FWH
Bit 10 in FWH Decode Enable Register is set
FFD8 0000 – FFDF FFFF
FF98 0000 - FF9F FFFF
FWH
Bit 11 in FWH Decode Enable Register is set
FFE0 000 - FFE7 FFFF
FFA0 0000 - FFA7 FFFF
FWH
Bit 12 in FWH Decode Enable Register is set
FFE8 0000 – FFEF FFFF
FFA8 0000 – FFAF FFFF
FWH
Bit 13 in FWH Decode Enable Register is set
FFF0 0000 - FFF7 FFFF
FFB0 0000 - FFB7 FFFF
FWH
Bit 14 in FWH Decode Enable Register is set
FFF8 0000 – FFFF FFFF
FFB8 0000 – FFBF FFFF
FWH
Always enabled.
The top two 64KB blocks in this range can be
swapped by the IICH. See Section 10.5 for details.
FF70 0000 - FF7F FFFF
FF30 0000 - FF3F FFFF
FWH
Bit 3 in FWH Decode Enable 2 Register is set
FF60 0000 - FF6F FFFF
FF20 0000 - FF2F FFFF
FWH
Bit 2 in FWH Decode Enable 2 Register is set
FF50 0000 - FF5F FFFF
FF10 0000 - FF1F FFFF
FWH
Bit 1 in FWH Decode Enable 2 Register is set
FF40 0000 - FF4F FFFF
FF00 0000 - FF0F FFFF
FWH
Bit 0 in FWH Decode Enable 2 Register is set
1KB anywhere in 4GB range
USB 2.0 Host Controller
Enable via standard PCI mechanism (Device 29,
Function 7)
FED0 X000h-FED0 X3FFh
HPET
BIOS determines “fixed” location which is one of
four 1KB ranges where X (in the first column) is
0h, 1h, 2h, or 3h.
All other
N/A
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10.7.3
Boot-Block Update Scheme
The IICH supports a “Top-Block Swap” mode that swaps the top block in the FWH (the
boot block) with another location. This allows for safe update of the Boot Block (even if
a power failure occurs). When the “top-swap” enable bit is set, inverts A16 for cycles
going to the upper two 64 Kbyte blocks in the FWH. Specifically, in this mode, accesses
to FFFF_0000h-FFFF_FFFFh are directed to FFFE_0000h-FFFE_FFFFh and vice versa.
When the Top Swap Enable bit is 0, the IICH will not invert A16. This bit is
automatically set to 0 by RTEST#, but not by PLTRST#.
The scheme is based on the concept that the top block is reserved as the “boot” block,
and the block immediately below the top block is reserved for doing boot-block
updates.
The algorithm is:
1. Software copies the top block to the block immediately below the top.
2. Software checks that the copied block is correct. This could be done by performing
a checksum calculation.
3. Software sets the “Top-Block Swap” bit. This will invert A16 for cycles going to the
FWH.
4. Software erases the top block.
5. Software writes the new top block.
6. Software checks the new top block.
7. Software clears the top-block swap bit.
8. Software sets the Top_Swap Lock-Down bit.
If a power failure occurs at any point after step 3, the system is able to boot from the
copy of the boot block that is stored in the block below the top. This is because the topswap bit is backed in the RTC well.
Note:
The top-block swap mode may be forced by an external strapping option (see
Chapter 16.0, “IMCH Registers.”). When top-block swap mode is forced in this manner,
the TOP_SWAP bit cannot be cleared by software. A reboot with the strap removed will
be required to exit a forced top-block weap mode.
Note:
Top-block swap mode only affects accesses to the Firmware Hub space, not feature
space.
Note:
The top-block swap mode has no effect on accesses below FFFE_0000h.
§§
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11.0
System Memory Controller
11.1
Overview
The memory controller is responsible for controlling the off-chip DRAM devices. The
unit scheduler, control and protocol state machines access DRAM devices over a wide
range of speed bins using DDR2 DRAM technology. The EP80579 supports one memory
channel.
11.2
Memory Controller Feature List
The memory controller supports the following features
• Supports 1 DIMM
— DDR2
— 64 and 32-bit mode.
— Single rank (64 or 32-bit mode) or Dual rank (64 bit mode) device.
— DDR2-400, DDR2-533, DDR2-667, DDR2-800.
— See to “Rules for Populating DIMM Slots” for more details.
• Supports dual DIMMs
— DDR2 and 64 bit mode only
— Registered Dual DIMM support with 1T command/address timing. Unbuffered
Dual DIMM support with 2T command/address timing. Please refer to “2T
Timing Mode” for details.
— 32-bit mode dual DIMM is not supported
— Restrictions on speed, number of ranks and modes in 2 DIMM mode, refer to
“Rules for Populating DIMM Slots” for details.
— DDR2-400 is supported.
— DDR2-533 and DDR2-667 are also supported with special design guidelines.
Refer to Table 11-5 for more details.
• Supports 32-bit mode
— 32-bit mode is for memory-down configuration, thus the following modes are
not supported: dual DIMM, dual rank, registered
• Supports 256 Mb, 512 Mb, 1 Gb and 2 Gb density parts in the x8 configuration.
Table 11-1 shows the various DDR2 device densities and widths supported.
Table 11-2 and Table 11-3 shows the various memory capacity configurations
supported using these parts in the 64 bit and 32-bit modes.
— Memory Controller does not support 4 Gb density
— See Section 11.3, “Configurations” for more details.
• Supports 4-bank devices
— 256 Mb and 512 Mb DDR2 parts
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• Supports 8-bank devices.
— 1 Gb and 2 Gb DDR2 parts
• Supports unbuffered and registered DIMMs
• Supports discrete memory components soldered on the board
— supports 2 DQ loads similar to the double sided DIMM configuration.
• One 72b wide DRAM interface, 64b data + 8b ECC.
— The 64b data interface can optionally configured to be a 32b interface with 8b
ECC. The 32b option provides half the total bandwidth compared to the 64b
interface, and meets the requirements for systems that are cost sensitive and
want to populate small memory footprint soldered on the mother board.
• Supports burst-of-4 mode with a minimum access size of 32B for the 64b interface.
— On the 64b interface accesses longer than 32B are serviced as multiple burstof-4 transactions without closing the page.
— On the 32b interface, the controller supports burst-of-8 for a minimum access
size that is still 32B.
• Optional error protection using ECC bits and error code that supports SEC/DED
(single bit error correction/double bit error detection). Please see “Offset 7Ch: DRC
– DRAM Controller Mode Register” for details.
— On a single bit error, the memory controller corrects the error bit and writes
back the correct data value to DRAM, if enabled by software selection.
— Does not support DED (double-bit error detect) retries.
• Supports maximum of 4 GB DRAM capacity as shown in Table 11-2.
— One memory channel
• Support for demand scrub in hardware
— Refer to Section 16.1.1.45, “Offset 88h: SDRC – DDR SDRAM Secondary
Control Register” on page 439 for details.
• Support for background scrubbing in hardware.
— Programmable hardware scrub engine that allows background scrub at a wide
range of rates, including, but not limited to: up to 4 GB every hour, day, week,
or very fast rates, mainly used for validation purposes.
The memory controller supports the following transactions
• Simple read transactions.
— Supported lengths - 1-7B, 8B, 16B, 24B, 32B, 64B
— Read transactions smaller than 32B will result in a full 32B read on the interface
• Simple write transactions.
— Supported lengths - 8B, 16B, 24B, 32B, 64B
— Writes of lengths 8B, 16B and 24B will take the same time on the interface as a
32B write, the actual bytes that are written are specified by the DQ masks
— Writes of length 40B, 48B, 56B will be treated as a 32B write followed by an 8B,
16B or 24B write
— Writes that are smaller than 8B (i.e 1-7B) require a read-modify-write
operation and these will be supported upstream in the pipeline in other units.
The memory controller will not support read-modify-write operation.
• CSR reads and writes
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• The memory controller does not support any atomic operations. Other units
upstream support atomic operations.
• All memory controller operations are aligned on a 64B boundary
• The memory controller interleaves the memory across banks on a 64B boundary
— Any transaction that crosses a 64B alignment boundary or is larger than 64B
must be split by the upstream agent.
• Supports external DIMMs or SO-DIMMs.
11.3
Configurations
Table 11-1 shows the various DDR2 device densities and widths supported by the
memory controller.
Table 11-1. Supported DDR2 Device Densities and Width
Density (Mb)
DDR2x8
256
Supported
512
Supported
1024
Supported
2048
Supported
4096
Not Supported
Table 11-2 shows the various capacity configurations supported in 64b mode. The first
column shows the total DRAM capacity on the channel. The rest of the columns indicate
the DRAM devices features, densities and the number of devices required to achieve
the given capacity. A single sided DIMM is indicated by no parts populated on side B.
Double sided DIMM has parts populated on both sides.
For each configuration, an additional DRAM part per side is required to support ECC
bits. A x8 part provides all the bits required for ECC. Note that memory system can be
built without ECC enabled.
In the 64b configuration, the minimum capacity supported is 256 MB and the maximum
capacity supported is 4 GB.
Table 11-2. Supported DRAM Capacity for 64b Mode
Total DRAM
Capacity
256 MB
512 MB
1 GB
2 GB
4 GB
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DRAM
Density
DRAM
Part
Width
Total # of
parts on
side A
(w/o
ECC)
Total # of
parts on
side B
(w/o
ECC)
256 Mb
x8
8
0
256 Mb
x8
8
8
512 Mb
x8
8
0
512 Mb
x8
8
8
1 Gb
x8
8
0
1 Gb
x8
8
8
2 Gb
x8
8
0
2 Gb
x8
8
8
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Table 11-3 shows the various configurations supported in the 32b mode.In the 32-bit
mode only single rank DDR2 devices are supported. In this mode, the minimum
capacity supported is 128 MB and the maximum capacity supported is 1 GB.
Table 11-3. Supported DRAM Capacity for 32b Mode
Note:
Total DRAM
Capacity
DRAM Density
DRAM Part
Width
Total # of parts on
side A
(w/o ECC)
Total # of parts on side
B
(w/o ECC)
128 MB
256 Mb
x8
4
0
256M B
512 Mb
x8
4
0
512 MB
1 Gb
x8
4
0
1 GB
2 Gb
x8
4
0
The EP80579 supports only single ranks in 32-bit mode.
Table 11-4 shows the supported DIMM raw cards in the registered and unbuffered
formats.
Table 11-4. Raw Cards Supported by the EP80579
Raw Card
Number of DDR2
SDRAMs
SDRAM Organization
Number of
Ranks
A
9
1
F
9
1
B
18
2
G
18
x8, planar, single row
RDIMM
2
D
8
F
9
1
1
E
16
2
G
18
2
UDIMM
Table 11-5 shows the supported DDR2device speed grades for single and Dual DIMMs.
Dual DIMM support uses 2N or 2T command/address timing.
Table 11-5. Supported DDR2 Data Speeds
DDR Speed
1 DIMM
1 rank
1 DIMM
2 ranks
2 DIMMs
1 rank each
DDR2-400
R = 1T
UB = 1T
R = 1T
UB = 1T
R = 1T
UB = 2T
DDR2-533
R = 1T
UB = 1T
R = 1T
UB = 1T
R = 1T
UB = 2T
DDR2-667
R = 1T
UB = 1T
R = 1T
UB = 1T
R = 1T
UB = 2T
DDR2-800
R = 1T
UB = 2T
R = 1T
UB = 2T
Not supported
R = Registered
UB = Unbuffered
1T = 1T Address/Command Timing
2T = 2T Address/Command Timing
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11.3.1
Rules for Populating DIMM Slots
1. In all configurations, the speed and timing will be the lowest among the 2 DIMMs,
as determined by the SPD registers on the DIMMs
2. Dual DIMM mode supports a subset of the DDR2 data speeds as shown in
Table 11-5.
3. Table 11-6 shows the supported DIMM population of the 2 ranks. All of
configurations not shown in Table 11-6 are not supported.The rank configurations
supported are one or two ranks on a single DIMM or one rank on each of the 2
DIMMs. Two ranks in each of the 2 DIMMs (i.e., 4 ranks) is not supported.
Table 11-6. Supported DIMM Populations
DIMM 1
DIMM 0
Rank 0
Rank 1
Rank 0
Rank 1
1 - Single Rank
Empty
Empty
DRB0
CS0
ODT0
Empty
1 - Dual Rank
Empty
Empty
DRB0
CS0
ODT0
DRB2
CS1
ODT1
2 - Single Rank
DRB2
CS1
ODT1
Empty
DRB0
CS0
ODT0
Empty
TABLE KEY:
ODT0/ODT1: ODT pins. Please refer to Section 11.4.2 for more information.
CS0/CS1: Chip Selects
DRB: Dram Row Boundary Register
4. Table 11-7 shows the supported rank configurations when using 2 ranks for the
single and dual DIMM.
.
Table 11-7. Supported Rank Configurations in Single and Dual DIMM mode
Single DIMM
(DDR2)
(64 bits - rank 0 & rank 1)
(32 bits - rank 0 only)
Dual DIMM
(DDR2, 64 bit only)
Rank 0
Rank 1
Rank 0, DIMM 0
Rank 0, DIMM 1
128 MB
(32 bit only)
NA
NA
NA
256 MB
256 MB
256 MB
256 MB, 512 MB, 1 GB,
2 GB
512 MB
512 MB
512 MB
256 MB, 512 MB, 1 GB,
2 GB
1 GB
1 GB
1 GB
256 MB, 512 MB, 1 GB,
2 GB
2 GB
2 GB
2 GB
256 MB, 512 MB, 1 GB,
2 GB
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5. There are additional restrictions when 2 ranks are used. Both the ranks need to be:
— Either registered or unbuffered. No mixing of registered and unbuffered ranks.
— 64 bit mode only. 32-bit mode is not supported in dual rank.
6. For 32-bit mode, only discrete components of single rank are supported. Two ranks
in 32-bit mode is not supported. Table 11-3 shows the supported configurations in
the 32-bit mode.
11.3.2
DRAM Addressing
Table 11-8, Table 11-9, Table 11-10 and Table 11-11 show the DRAM device addressing
for the various DDR2 device densities supported by the memory controller.
Note that:
• x4 and x 16 devices are not supported.
• 4Gb and higher device density parts are not supported.
• See Table 11-7 for the supported device densities and widths.
Table 11-8. 256Mb Addressing
Configuration
DDR2
32 Mb x 8
# of Banks
Bank Address
Auto Precharge
Row Address
Column Address
Page Size
4
BA0, BA1
A10
A0-A12
A0-A9
1KB
Table 11-9. 512Mb Addressing
Configuration
DDR2
64 Mb x 8
# of Banks
Bank Address
Auto Precharge
Row Address
Column Address
Page Size
4
BA0, BA1
A10
A0-A13
A0-A9
1KB
Table 11-10. 1Gb Addressing
Configuration
DDR2
128 Mb x 8
# of Banks
Bank Address
Auto Precharge
8
BA0-BA2
A10
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Table 11-10. 1Gb Addressing
Configuration
Row Address
Column Address
Page Size
DDR2
128 Mb x 8
A0-A13
A0-A9
1KB
Table 11-11. 2Gb Addressing
Configuration
# of Banks
Bank Address
Auto Precharge
Row Address
Column Address
Page Size
11.3.3
DDR2
256 Mb x 8
8
BA0-BA2
A10
A0-A14
A0-A9
1KB
Memory Address Translation Tables
Section 11.3.3.1 shows the address bit translation from the system address to the
DRAM row/column/bank address for the different DDR2 configurations supported by
the memory controller.
256 Mb, 512 Mb, 1024 Mb and 2048 Mb DRAM device densities are shown but please
refer to Table 11-1 for supported DDR2 device densities and widths. The memory
capacity that can be achieved for each device density in the single and dual rank mode
is also shown in the address mapping tables.
11.3.3.1
DDR2 Address Translation Tables
Figure 11-1 shows the translation tables for 64 bit, burst size 4 devices in x8 width.
Note: only burst 4 is supported for a DDR2 64 data bit interface.
Figure 11-2 shows the translation tables for 32 bit, burst size 8 devices in x8 width.
Note: only burst 8 is supported for a DDR2 32 data bit interface.
For a list of memory controller supported DDR2 device types and widths see
Table 11-1.
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Figure 11-1. Memory Address Tables for 64 Bit, Burst Size 4 and x8 DDR2 Devices
T o ta l
Cap
(M B )
S in g le
R an k
256
512
1024
2048
D ev
D e v ic e ic e B u s
R /C /B
d e n s ty w id t W id
th a d d r lin e s
(M b )
h
256
8
64 13x10x2
512
8
64 14x10x2
1024
8
64 14x10x3
2048
8
64 15x10x3
Row
Col
Row
Col
Row
Col
Row
Col
BA2
B A1
B A0
A14
A13
A12
A11
A1 0
A0 9
A0 8
A0 7
A0 6
A05
A04
A03
A02
A01
A00
0
7
6
0
7
6
8
7
6
8
7
6
0
0
0
0
0
0
30
0
0
0
28
0
28
0
28
0
26
0
26
0
26
0
26
0
25
0
25
0
25
0
25
0
24
AP
24
AP
24
AP
24
AP
23
27
23
27
23
27
23
27
22
13
22
13
22
13
22
13
21
12
21
12
21
12
21
12
20
11
20
11
20
11
20
11
19
10
19
10
19
10
19
10
18
9
18
9
18
9
18
9
17
8
17
8
17
29
17
29
16
5
16
5
16
5
16
5
15
0
15
0
15
0
15
0
14
0
14
0
14
0
14
0
Figure 11-2. Memory Address Tables for 32 Bit, Burst Size 8 and x8 DDR2 Devices
D ev
D e v ic e ic e B u s
R /C /B
d e n s ty w id t W id
th
a d d r lin e s
(M b )
h
256
8
32 13x10x2
512
8
32 14x10x2
1024
8
32 14x10x3
2048
8
32 15x10x3
11.3.4
R ow
C ol
R ow
C ol
R ow
C ol
R ow
C ol
B A2
BA1
BA0
A14
A13
A12
A11
A10
A09
A08
A07
A06
A05
A04
A03
A02
A01
A00
0
7
6
0
7
6
8
7
6
8
7
6
0
0
0
0
0
0
29
0
0
0
27
0
27
0
27
0
26
0
26
0
26
0
26
0
25
0
25
0
25
0
25
0
24
AP
24
AP
24
AP
24
AP
23
13
23
13
23
13
23
13
22
5
22
5
22
5
22
5
21
12
21
12
21
12
21
12
20
11
20
11
20
11
20
11
19
10
19
10
19
10
19
10
18
9
18
9
18
9
18
9
17
8
17
8
17
28
17
28
16
0
16
0
16
0
16
0
15
0
15
0
15
0
15
0
14
0
14
0
14
0
14
0
DRAM Timings
The EP80579 is highly configurable in its DRAM timing configuration, but only a limited
subset of the setting combinations possible are verified by Intel. The approved and
expected settings for the various flavors of supported memory are listed in
Table 11-12. For more information on the DRT register see “Offset 78h: DRT0 - DRAM
Timing Register 0” and “Offset 64h: DRT1 – DRAM Timing Register 1”.
Table 11-12. Supported DRAM Timings
Memory Speed
CL
(CAS latency)
tRCD
(RAS-CAS delay)
tRP
(RAS Precharge)
DDR2-400a
3
3
3
DDR2-400b
4
4
4
DDR2-533
4
4
4
DDR2-667
DDR2-800
5
5
5
5
5
5
6
6
6
a: 3-3-3 is not supported for systems which require ODT
b: May be accomplished by programming 3-3-3 parts to 4-4-4
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11.3.4.1
2T Timing Mode
The address and command group (Bank Address BA[2:0], Address MA[14:0],
Command pins RAS_L, CAS_L and WE_L) of pins to the DRAM devices can be clocked
either by 1T or 2T timing as shown in Figure 11-3. The control group of pins (CKE, CS,
ODT) are not impacted by the 2T timing mode.
When in 1T timing mode, a new command can be issued to the DRAM devices every
DRAM clock cycle. In 2T timing mode, a new command can be issued to the DRAM
devices every other DRAM clock cycle i.e., the address and command bus needs to be
held valid for 2 cycles.
2T timing reduces the efficiency of the command bus by half but it doubles the setup
and hold time for the command and address bus. The timing for the DRAM data bus
and all other signals to the DRAM devices remain the same between 1T and 2T timing
modes.
On the EP80579, unbuffered dual DIMM configurations are supported in 2T timing
mode. Single DIMM configurations are supported in 1T timing mode. Please refer to
Table 11-5 for details. The 2T timing mode can be selected by setting the 2T or1T bit in
“Offset 64h: DRT1 – DRAM Timing Register 1”.
Note:
1T/2T timing is also referred to as 1N/2N timing.
Figure 11-3. 2T and 1T Timing Mode
2T Timing Mode
CK
Control
NOP
NOP
Address /
Command
2 cycle Address/Command
1T Timing Mode
CK
Control
NOP
NOP
Address /
Command
1 cycle Address/
Command
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11.3.5
DQ/DQS Mapping
The data signal (DQ) to data strobe (DQS) relationship is controlled by the setting in
the DRAM Row Attribute (DRA) registers (see Section 16.1.1.40, “Offset 70h: DRA[0-1]
– DRAM Row [0:1] Attribute Register” for details). Bits 7:6 and 3:2 of these registers
respectively define the device width for the odd and even rows, which is also used in
the mapping of DQS signals to DQ signals.
Table 11-13. DRA Mapping for DQS
Bits
Definition
DQS per DQ
00
Reserved
NA
01
x8 DDR
1 DQS strobe per data byte
10
Reserved
NA
11
Reserved
NA
Table 11-13 shows the mapping of DQS to DQ in general terms. Table 11-14 gives the
exact relationship.
Table 11-14. DQS to DQ Mapping for x8 Devices
x8 devices
11.3.6
DQ Byte
DQS bit
0
0
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
32-Bit Mode
DQ[31:0] and the associated DQS[3:0] are connected to the DIMMs in 32-bit mode.
Operation in 32-bit mode is invisible to software and on-chip memory controller
interfaces.
11.4
DDR2 Features
The DDR2 generation of technology introduces some new features beyond standard
DDR. This section highlights those supported.
11.4.1
Interface Signalling Voltage
The memory controller supports 1.8 V signaling for DDR2-400, DDR2-533, DDR2-667
and DDR2-800 DIMMs.
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11.4.2
On-DIMM Die Termination (ODT)
The JEDEC DDR2 DRAM Specification requires that DDR2 DIMM devices provide
selectable on-DieDIMM Termination (ODT) as an alternative to traditional discrete
termination on the motherboard. The On-DIMM termination ODT feature is enabled via
the DDR extended memory register select (EMRS) command ODTENA and supports
both 75 and 150 terminations activated dynamically via dedicated On-DIMM
termination ODT interface signals on the DIMM.
The EP80579 implements two ODT pins to control the behavior of the termination on
the two ranks of DRAM devices. The mapping of the CS & ODT pins for the various
DIMM configurations is shown in Table 11-6. The behavior of these ODT signals can
controlled by setting the appropriate bits in the Section 16.1.1.49, “Offset B0h:
DDR2ODTC - DDR2 ODT Control Register”.
The EP80579 controls operation of DDR2 devices with or without on-DIMMDie
termination enabled, but is verified by Intel only in On-Die (ODT) enabled mode of
operation. ODT can be disabled by setting the appropriate bits in DRAMODT bit in
Section 16.1.1.43, “Offset 7Ch: DRC – DRAM Controller Mode Register”.
Table 11-15 shows the ODT related timing parameters.
The EP80579 supports operation of DDR2 devices with or without on-DIMMDie
termination enabled, but is verified by Intel only in the On-Die (ODT) enabled mode of
operation. ODT can be disabled by setting the DRAMODT bit in Section 16.1.1.43,
“Offset 7Ch: DRC – DRAM Controller Mode Register”.
Table 11-15. ODT Timing Parameters
Parameter
tCK
5, 3.75, 3, 2.5ns
ODT turn on delay
2 tCK
tOFD
ODT turn off delay
2.5 tCK
CL
CAS Latency
3, 4, 5, 6
RL
Read Latency
CL
WL
Write Latency (RL - 1)
CL - 1
BL
Burst Length
4, 8
Assertion of ODT pin to inactive slot during
reads
= RL - tOND - 1
= RL - 3
Time for which the ODT pin is asserted
= tOND+1+BL/2+0.5-tONF
= 2+1+BL/2+0.5-2.5
= BL/2+1
Assertion of ODT pin to inactive slot during
writes
= WL - tOND - 1
= WL - 3
Time for which the ODT pin is asserted
= tOND+1+BL/2+0.5-tONF
= 2+1+BL/2+0.5-2.5
= BL/2+1
ODT_RD_ontime
ODT_WR_on
ODT_WR_ontime
•
Clock Period
Value
tOND
ODT_RD_on
•
Description
For WL = 2 (CL = 3), the ODT_WR_on = -1. This requires the controller to enable ODT 1 tCK before the
Write command is issued. EP80579 memory controller will not support asserting the ODT pin before it
issues the write command. The result is that for CL=3, the termination in the inactive slot will be turned
on at the same time the DQ bus is being driven by the memory controller.
The ODT turn on and off timings will be calculated by the hardware based on the DRAM configuration
parameters: CL and BL.
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11.4.2.1
ODT Control of Reads
During a read command in a 2 slot configuration as shown in Figure 11-4, the memory
controller will enable ODT on the inactive slot. The ODT pin will be asserted by the
controller such that the termination in the inactive slot will be enabled 1 tCK before the
active slot starts driving the DQ bus. The termination will be turned-off by the
controller ½ tCK after the last DQ is driven by the active slot as show in Figure 11-4.
There is no assertion of the ODT signal to the DRAM device in a 1 slot configuration.
Please refer the Section 16.1.1.49, “Offset B0h: DDR2ODTC - DDR2 ODT Control
Register” for more details on the CSR that needs to be programmed by BIOS so that
the memory controller drives the proper ODT control signals.
Figure 11-4. ODT Timing on Back-to-Back Reads to Different Slots
0
1
2
Read A
Slot 1
3
4
5
6
7
8
Read A
Slot 2
ODT
Slot 2
ODT
Slot 1
CL = 4
BL = 4
CL = 4
BL = 4
DQ
Slot 2
Rtt
tOND = 2 tCK
Termination ON Slot 2
tONF = 2.5 tCK
tOND = 2 tCK
Slot 1
Rtt
Termination ON Slot 1
tONF = 2.5 tCK
11.4.2.2
ODT Control of Writes
During a write command in a 2 slot configuration as shown in Figure 11-5, the EP80579
memory controller will enable ODT on the inactive slot. The ODT pin will asserted by
the controller such that the termination in the inactive slot will be enabled 1 tCK before
the controller starts driving the DQ bus (except for configurations where CL = 3). The
termination will be turned-off by the controller ½ tCK after the last DQ is driven by the
controller to the active slot as shown in Figure 11-5.
During a write command in a one slot configuration, the memory controller will enable
ODT to the active slot such that the termination is enabled 1 tCK before the controller
starts driving the DQ bus (except for configurations where CL = 3, see note below).
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Please refer the Section 16.1.1.49, “Offset B0h: DDR2ODTC - DDR2 ODT Control
Register” for more details on the CSR that needs to be programmed by BIOS so that
the memory controller drives the proper ODT control signals.
Note:
The memory controller will not enable ODT before the write command is issued on the
DRAM interface (See Table 11-15 for more details). For configurations with CL=3,
WL=2 the controller will assert the ODT pin along with the write command. This will
result in the termination in the inactive slot to be enabled at the same time the
controller starts driving the DQ data bus.
Figure 11-5. ODT Timing on Back-to-Back Writes to Different Slots
0
1
Write A
Slot 1
2
3
4
5
6
7
8
Write A
Slot 2
ODT
Slot 2
ODT
Slot 1
WL = 3
WL = 3
BL = 4
BL = 4
DQ
Slot 2
Rtt
tOND = 2 tCK
Termination ON Slot 2
tONF = 2.5 tCK
tOND = 2 tCK
Slot 1
Rtt
Termination ON Slot 1
tONF = 2.5 tCK
11.4.3
On-Die Termination (ODTZ) on the EP80579
The EP80579 supports ODT (referred to as ODTZ to differentiate it from the OnDIMMDie Termination, ODT that is implementation on the DRAM devices) on the DQ/
DQS buffers to improve signal integrity on the inbound path (read data from DRAM).
ODTZ will be enabled on read accesses to the DRAM devices and can be in one of the 3
states - 60ohms, 120ohms or off. ODTZ will be automatically disabled when the
EP80579 DQ/DQS buffers are enabled for a write access to the DRAM device. There are
no timing parameters implemented to control this functionality and the DDRIO pads are
responsible for ensuring that ODTZ is in the disabled state when issuing writes to the
DRAM devices.
The termination value for ODTZ can be set by programming the ODTZENA bit in Section
16.1.1.45, “Offset 88h: SDRC – DDR SDRAM Secondary Control Register”.
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11.4.4
Refresh
The EP80579 supports generation of the refresh commands (REF) that are necessary
for the DRAM devices to retain its data. When the refresh cycle is launched by memory
controller an address counter, internal to the DRAM device, supplies the bank address
during the refresh cycle. No control of the address bus is required for a refresh cycle.
When the refresh cycle has completed, all banks of the DDR2 device will be in the
precharged (idle) state. A delay between the Refresh command and the next activate
command or subsequent Refresh command must be greater than or equal to the
Refresh cycle time (tRFC). There are 3 mechanisms through which the EP80579
memory controller will generate the refresh commands:
1. Programmable counter: The refresh engine can be programmed to generate
refresh commands at programmable time intervals. The choice of intervals are
meant to cover DDR2 device tREFI specifications. Please refer to Section 16.5.1.3,
“Offset 40h: DCALCSR – DDR Calibration Control and Status Register” details on
programming the refresh engine.
2. Programmable OPCODE generation: A single refresh command can be
generated under software control using the available opcodes in Section 16.5.1.3,
“Offset 40h: DCALCSR – DDR Calibration Control and Status Register”.
3. Self-Refresh exit state machine: The self-refresh exit engine will issue one
refresh command to each rank after it brings them out of self refresh.
Note:
The EP80579 does not support posted refresh cycles.
11.4.5
Self-Refresh
The EP80579 supports the generation of self-refresh commands that can be used to
retain data in the DRAM devices without any support from the memory controller. The
DRAM device has built-in counters timers to accommodate the self-refresh operation.
There are 2 mechanisms to enter and exit the self-refresh mode:
1. Self-Refresh Entry
a.
S3: The memory controller will issue a self-refresh entry command at the end
of the S3 sequence.
b.
Programmable OPCODE generation: A self-refresh entry command can be
generated under software control using the available opcodes Section 16.5.1.3,
“Offset 40h: DCALCSR – DDR Calibration Control and Status Register”.
2. Self-Refresh Exit
a.
Power up after S3 event: The memory controller implements a self-refresh
exit engine which under software control can bring the DRAM devices out of selfrefresh. Refer to Table 16-226, “Rules about issuing Self-Refresh and Refresh
commands using DCALCSR.OPCODE” on page 604 for details on the rules that
software should follow when using this mechanism.
b.
Writing to DRC.CKE[1:0] register bits: By writing to the DRC.CKE[1:0]
registers, software can assert the CKE pins to the DRAM devices bringing them
out of self-refresh.Please refer to Section 16.5.1.59, “Offset 1F4h:
MB_ERR_DATA32 - Memory Test Error Data 3” for more details.
The de-emphasis feature on the command/clock pins should be disabled before
entering self-refresh. Please see the DEMCA bit in Section 16.5.1.63, “Offset 264h:
DDRIOMC1 - DDR IO Mode Control Register 1” for more details.
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11.4.6
RCOMP
The EP80579 supports RCOMP for the DDR pads. RCOMP control is implemented for 2
groups of DDR pads. The RCOMP used for the 2 groups can either be static or dynamic
based on DDRIOMC2.LEGOVERRIDE[5:4]. For more details on how to control the
RCOMP for the 2 groups of DDR pads please see Section 16.5.1.64, “Offset 268h:
DDRIOMC2 - DDR IO Mode Control Register 2”. The final values that are used for Group
1 and Group 2 drivers can be viewed using the bits in Section 16.5.1.29, “Offset F0h:
DIOMON - DDR I/O Monitor Register”.
• Group1: Data, data mask and data strobes:
— DDRIOMC2.LEGOVERRIDE[4:0] bits can be used in dynamic mode to achieve
the target impedance on the group 1 DDR pads. In dynamic RCOMP mode,
these CSR bits control several pull-up devices that are binary sized. The pull-up
devices are tuned using an external resistor (Rext). In Static mode,
DDRIOMC2.LEGOVERRIDE[3:0] determines the RCOMP value used by the
Group 1 DDRIO pads.
• Group2: Command, Address and Clock:
— In dynamic RCOMP mode the digital control for these group of DDR pads is
derived by multiplying the group 1 digital control by a factor determined by
DDRIOMC2.LEGOVERRIDE[6:9]. In static RCOMP mode,
DDRIOMC2.LEGOVERRIDE[6:9] directly controls the RCOMP value used by the
Group 2 DDRIO pads.
11.4.7
DDR2 MR and EMR settings
Table 11-16 shows the supported settings of DDR2 mode register (MR) and extended
mode register (EMR). Note that only the architecturally relevant settings of the MR and
EMR are listed in this table. These registers can be updated using the MRS and EMRS
commands. Please see Section 16.5.1.3, “Offset 40h: DCALCSR – DDR Calibration
Control and Status Register” and Section 16.5.1.4, “Offset 44h: DCALADDR - DDR
Calibration Address Register” for more details on generation of MRS and EMRS
commands.
Table 11-16. Supported DDR2 MR and EMR settings
MR/EMR Feature
Burst Type
Burst Length
Write Recovery for Auto-precharge
CAS Latency
ODT (EMR)
EP80579 Support
Sequential only
4 (64-bit mode) and 8 (32-bit mode)
Supported. Settings based on speed bins. Please see Section
16.0, “IMCH Registers” for details.
3, 4, 5 and 6 depending upon Speed bin. Please see Table 11-12
and Section 16.0, “IMCH Registers” for more details.
Supported.
Please see Section 11.4.2 for more details.
OCD Calibration (EMR)
Not Supported.
Additive Latency (EMR)
Not Supported.
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11.4.8
Scrubbing Support
The memory controller will support both demand scrubbing and background scrubbing
in hardware. This section provide details of the scrubbing mechanism.
11.4.8.1
Demand Scrubbing
When the controller detects a single bit error on a DRAM read, the ECC logic fixes the
single bit error and returns the corrected data to the requester. The controller also
writes the corrected data back into DRAM using the demand scrub operation.
11.4.8.2
Background Scrubbing
The controller supports a simple state machine that periodically injects read
transactions into the stream. The scrub rate meets a general requirement for scrubbing
a 4GB memory capacity every 24 hours. It can also be programmed to scrub the entire
DDR at faster rates, if that is desired. Rates available extend from an entire scrub every
few days, to every day, every hour, every minute, and even very fast rates, mainly
used for validation purposes. Data for a background scrub read operation is discarded if
no error is detected on the read. When a single bit error is detected on a background
scrub read transaction, the mechanism specified in Figure 11.4.8.1 is used to correct
the single bit error in DRAM. The read data is dropped. When a double bit error is
detected on a background scrub read transaction, the controller log the error and
interrupts the IA-32 core.
11.5
Error Handling
The memory controller accesses may encounter data with ECC violations and/or parity
errors.
• For writes with bad parity, as indicated on bits in the command from either AIOC
memory target (MT) or IMCH, the memory controller will execute the write,
poisoning the data as it writes it to DDR. Please see Table 11-17 for the granularity
of poisoned data. Poisoning is accomplished by inverting each bit of ECC calculated
for that particular write, based on the bad write data sent to the memory controller
from AIOC or IMCH.
• For reads from DDR with single bit parity errors, the memory controller will correct
all correctable errors, and return the data, to either requestor, corrected, and
without a bad parity indication. Status logging, as discussed above, will be done.
• For reads from DDR with multiple bit, uncorrectable ECC violations, the memory
controller will return the data to either requestor, however, a bad parity indication
will be driven back with the data. Please see Table 11-17 for the granularity of
poisoned data. AIOC memory target (MT) or IMCH should poison the data when
seeing the bad parity bit set, along with the read data returned.
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Table 11-17. Poisoning Granularity
Command
Error Source
Command Source
Read from DRAM
DRAM
(DED)
IMCH
Read from DRAM
DRAM
(DED)
AIOC MT
Poison parity bits on 8B granularity and return
read data to AIOC memory target (MT).
IMCH
Poison ECC bits on 16B granularity and write
to DRAM.
AIOC MT
Poison ECC bits on 8B granularity and write to
DRAM.
Write to DRAM
Write to DRAM
•
•
•
IA or IO Device
including AIOC
(Parity Error)
AIOC
(Parity Error)
Memory Controller Action
Poison parity bits on 32B granularity and
return read data to IMCH.
ECC can be enabled by setting the DDIM bit in Section 16.1.1.43, “Offset 7Ch: DRC – DRAM Controller
Mode Register”.
Poisoning of write data to DRAM can be enabled using the MEMPEN bit in Section 16.1.1.44, “Offset 84h:
ECCDIAG – ECC Detection/Correction Diagnostic Register”.
Poisoning of read data from DRAM to IMCH or AIOC MT can be enabled by using ENDP bit in Section
16.1.1.43, “Offset 7Ch: DRC – DRAM Controller Mode Register”.
For compatibility with accepted IA platform algorithms and mechanisms, the memory
controller will follow general IA error logging and reporting mechanisms as closely as
possible with the following exception:
• The memory controller does not implement uncorrectable retries (DED retries).
Therefore all registers and bit definitions that support uncorrectable retries are not
implemented in the memory controller.
§§
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12.0
Enhanced Direct Memory Access Controller
(EDMA)
The IMCH includes an integrated four-channel Enhanced Direct Memory Access (EDMA)
controller to facilitate “push model” block transfers without IA-32 core intervention for
higher overall system performance. This section details the operating modes, setup,
interfaces, register set, and high-level implementation of the EDMA controller.
12.1
Overview
The EDMA engine provides a highly efficient means to move data within local system
memory or from the local system memory to the I/O subsystem. Each EDMA channel
provides low-latency, high-throughput data transfer capability with minimal IA-32 core
intervention. For the IA-32 core, it is a “fire and forget” type of memory transfer, with a
doorbell starting mechanism and interrupt capability for signaling completion.
Each channel optimizes block transfers of data through a linked-list descriptor chaining
mechanism that supports scatter/gather operations. Each channel is responsible for
providing the EDMA programming interface, executing the data transfers, and handling
any errors encountered during operation.
Each channel initiates traffic on both the local system memory and outbound traffic
arbiter interfaces, and is designed such that each independent channel is capable of
generating at least 1 GB/s of traffic during data hauls. In the absence of competition
from other traffic sources, multiple channels could theoretically saturate the local
memory interface. See Figure 12-1.
Each channel is independently enabled by setting the Start bit in the Control
Configuration Register. The Start bit is cleared after power-up or reset and
consequently the EDMA controller is disabled until software explicitly turns each one
on.
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Figure 12-1. Concept Diagram of EDMA Data Path
Memory-to-Memory
EDMA Data Path
EP80579
EDMA Engine
CMACH0
CMACH2
CMACH3
EDMA Arbiter
CMACH1
Transaction
Requests
Memory
Memory-to-I/O
EDMA Data Path
PCI Express
Interface
Port A
PCI Express Port A
Links
B6119-01
12.1.1
Features
The following features are supported by the EDMA controller:
• Four independent channels (see Figure 12-2)
— Dedicated data transfer queue per channel
— Full register set for descriptor and transfer handling per channel
• Support for transfer between main memory locations, and from memory to the I/O
subsystem
• PCI Express* support of traffic class to provide external prioritization of traffic
• Supports transfers only between two physical addresses
— 32-bit (4 GB) addressing range on the local system memory interface
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— 32-bit addressing range on the Memory Mapped I/O Subsystem Interface (no
NSI access)
• Maximum transfer of 16 MB transfers per descriptor
• Fully programmable by the IA-32 core
— Configuration space mapping for EDMA engine capability and control
— Memory-mapped space for EDMA channel-specific register sets
• Chain Mode EDMA transfer with automatic data chaining for scattering/gathering of
data blocks
— EDMA chaining continued until a “null” descriptor pointer is encountered
— Support for appending a block to the end of current EDMA chain
— Automated descriptor retrieval from local memory during chaining – single read
• Programmable independent alignment between source and destination
— Byte aligned transfer on the local system memory interface
— Byte aligned transfer on the I/O subsystem interface
• Support for non-coherent transfers both to and from system memory on a per
descriptor basis
— Independent control of coherency for source and destination
• Programmable support for interrupt generation on block–by-block basis
— Selectable MSI or legacy level-sensitive interrupt function
— End of current block transfer
— End of current chain
— For any error causing a transfer to abort
• Increment of the source and destination address for standard transfers
• Increment of the destination and decrement of the source address to enable byte
stream reversal
• Constant address mode for the destination address based on the transfer
granularity to enable targeting of memory mapped I/O FIFO devices
• Buffer/memory initialization mode
12.1.2
Logical Block Diagram
Figure 12-2 shows the conceptual interface of the EDMA channels to different l
interfaces.
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Figure 12-2. Conceptual Diagram of Four Channel EDMA Engine
FSB Interface
Cfg/TAP Interface
EDMA Channel0
EDMA Channel2
EDMA Channel3
Memory Interface
PCI Express Interface
EDMA Channel1
EDMA Arbiter
REQs
GNTs
System Arbiter
12.2
Channel Programming Interface
The EDMA channel programming interface is accessible from the IA-32 core via a
combination of chain descriptors (shown in Figure 12-3) written to main memory and a
memory-mapped internal register set. The EDMA controller provides four channels,
each of which can be independently used to transfer data within the local system
memory or from the local system memory to the I/O subsystem. Each channel has its
own set of 12 registers. Refer to “Memory Mapped I/O for EDMA Registers” on
page 651 for a description of the channel register set.
The channel programming interface is accessible from the IA-32 core via a combination
of descriptors written to main memory and a memory-mapped internal register set.
Each channel is programmed independently.
Each channel supports full chaining capability. The chain descriptors can be cascaded
together in system memory to form a linked list. Each chain descriptor contains all the
information necessary for transferring a block of data, as well as a pointer to the next
chain descriptor in the list. The next descriptor pointer of the last chain descriptor in a
linked list will be a null pointer (address zero), indicating the end of that chain.
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Throughout this document, all register references are made using the name of the
lower 32-bit register, irrespective of whether the target is a 32-bit or 64-bit register
with lower and upper halves.
12.3
Chaining Operation
An EDMA access transfers a block of data from one address to another. The desired
transfer is specified by setting up a linked list of chain descriptors in the local system
memory, and initiated by programming the first chain descriptor start address into the
Next Descriptor Address Registers (NDAR/NDUAR) of the EDMA channel and setting the
Start bit of the Channel Control Register (CCR). Each block of the transfer is defined by
a descriptor in main memory containing the source address, destination address,
transfer length and control values. Setting the Start bit of the Channel Control Register
(CCR) causes the channel to fetch the current chain descriptor information and place it
into its corresponding register set. Once all the register information has been fetched,
the actual data transfer starts.
Note:
The Start bit will be ignored unless the Channel Status Register (CSR) is in an
appropriate state. Software must ensure that the status bits for end of chain, stopped,
aborted, and active are all clear prior to attempting to initiate a new transfer with the
start function.
12.3.1
Chain Descriptor Definition
All EDMA transfers are controlled by chain descriptors in the local system memory. A
single block transfer will specify only a single chain descriptor. Chain descriptors can be
linked together to form a linked list, providing a capability for complex EDMA scatter/
gather operations.
Figure 12-3 shows the format of a chain descriptor. Each chain descriptor consists of
eight contiguous DWords (32-bits) in the local system memory, and must be naturally
aligned to an eight Dword boundary. All eight DWords must be defined and are required
for the proper operation of the EDMA engine.
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Figure 12-3. Chain Descriptor in Memory
Chain Descriptor in Memory
Description
Source Address (SAR)
Lower 32-bit Source Memory Address Register
Source Upper Address
(SUAR)
Upper 32-bit Source Memory Address Register
Destination Address
(DAR)
Lower 32-bit Destination Memory Address Register
Destination Upper Address
(DUAR)
Upper 32-bit Address of Next Chain Descriptor Register
Next Descriptor Address
(NDAR)
Lower 32-bit Address of Next Chain Descriptor Register
Next Descriptor Upper Address
(NDAUR)
Upper 32-bit Address of Next Chain Descriptor Register
Transfer Count
(TCR)
Descriptor Control
(DCR)
Number of Bytes to Transfer Register
Descriptor Control Register
B4483-01
12.3.2
DMA Chain Descriptor in Memory
Each chain descriptor is composed of eight Dwords. Each Dword in the chain descriptor
in the local memory is analogous to the corresponding EDMA channel register value.
The bit definitions in the chain descriptor in memory are identical to those of the
corresponding channel register. Refer to the EDMA channel-specific register definitions
in “Memory Mapped I/O for EDMA Registers” on page 651 for descriptions of the fields
defined by a chain descriptor.
After a transfer has been requested, the EDMA channel reads the specified chain
descriptor from local system memory and updates its own corresponding channel
registers automatically.
12.3.3
Chain Descriptor Usage
A linked list of chain descriptors may be built in the local system memory to transfer
data within the local system memory or from local system memory to I/O subsystem
memory. An application may build multiple chain descriptors to transfer many blocks
with differing source addresses, destination addresses, data transfer counts,
alignments, and coherence attributes. The application may connect these chain
descriptors using the Next Descriptor Address in a sequence of chain descriptors,
creating a linked list of EDMA transfers, all of which may complete without any
processor intervention. Figure 12-4 shows a linked list of transfers built in local system
memory and illustrates how they are “chained” together.
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It is possible but unexpected that the source and destination address ranges defined by
chain descriptors may overlap in physical memory. While there are scenarios where this
may produce no errors in the resulting memory image, the software must ensure that
no failure results from such usage. Hardware checks are not built into the EDMA
mechanism to ensure that source and destination physical address ranges do not
overlap. Similarly, there are no hardware interlocks to ensure that independent
channels are not programmed to modify the same address range simultaneously. If
software were to create such a situation, the resultant memory image would be
indeterminate, since there are no guarantees as to the relative access ordering among
simultaneously active channels.
Figure 12-4. Chaining Mechanism
Next Descriptor Address Register (32 -bit or 64-bit)
Linked
Descriptors in
Memory
Source Address (SAR)
Source Upper Address (SUAR)
Destination Address (DAR)
Destination Upper Address (DUAR)
First
Block
Transfer
Next Descriptor Address (NDAR)
Next Descriptor Upper Address (NDUAR)
Transfer Count (TCR)
Descriptor Control (DCR)
Source Address (SAR)
Source Upper Address (SUAR)
Destination Address (DAR)
Destination Upper Address (DUAR)
Next Descriptor Address (NDAR)
Second
Block
Transfer
Next Descriptor Upper Address (NDUAR)
Transfer Count (TCR)
Descriptor Control (DCR)
Source Address (SAR)
Source Upper Address (SUAR)
Destination Address (DAR)
Destination Upper Address (DUAR)
Nth Block
Transfer
Next Descriptor Address (NDAR)
Next Descriptor Upper Address (NDUAR)
Transfer Count (TCR)
Descriptor Control (DCR)
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End of Chain
(Null Value)
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12.3.4
Scatter/Gather Transfer
The EDMA descriptors in memory may be defined such that they cause the channel to
perform typical scatter/gather data transfers. To “gather” data, software may create a
linked list of descriptors that will move non-contiguous source blocks of data into a
contiguous set of destination blocks. To “scatter” data, software may create a linked list
of descriptors that will move contiguous blocks of source data to non-contiguous
destination blocks. It is even possible to program the EDMA transfer descriptors in such
a way that some blocks of source data within a single chain are moved to new memory
locations, while other blocks are moved out to the I/O subsystem.
There is no hardware restriction limiting the nature of source and destination address
ranges, other than that the source and destination types (memory or I/O subsystem)
must match the descriptor address mappings. The IMCH aborts the EDMA operation
and reports a programming error if this requirement is not met.
12.3.5
Appending to a Descriptor Chain
After an EDMA channel has started processing a linked list of descriptors, the
application software may need to append a chain descriptor to the end of the current
chain without tearing down the transfer in progress. Such an operation requires a
mechanism to guarantee that a descriptor is never in the process of modification by the
IA-32 core while being retrieved by the EDMA channel (This would result in a hybrid
descriptor loaded into the corresponding EDMA channel register set, and spurious
operation). The suspend function of the EDMA controller is defined to facilitate this type
of usage.
The preferred mechanism for appending to a linked list currently being processed is to
suspend the current transfer, modify the terminal chain descriptor to update its Next
Descriptor Address field(s), and then allow the transfer to resume. This is accomplished
by first setting the Suspend bit in the Channel Control Register (CCR) followed by a
read of the Channel Status Register (CSR) to verify that the suspend has taken
effect.The Next Descriptor Address fields of the terminal chain descriptor in the current
linked list are updated with the address of the first descriptor to be appended. After this
update has occurred, software then clears the Suspend bit, sets the Channel Resume
bit and allows execution to proceed.
Note:
A single write to the CCR may update both bits simultaneously.
This append algorithm covers the following cases:
• The EDMA channel has completed execution of the terminal descriptor in the
original chain, and is idle. The EDMA channel examines the Channel Resume bit
when the Channel Control Register (CCR) is written. If the bit is set, the EDMA
channel will automatically clear the bit and re-read the last chain descriptor (as
indicated by CDAR/CDUAR), which updates NDAR with the appended chain
descriptor address. A non-null value in NDAR will result in a fetch of the target
chain descriptor, and resumed execution. (If the resulting NDAR/NDUAR pair
remains null, the EDMA channel will remain idle.)
• The EDMA channel is executing a descriptor prior to the terminal chain descriptor in
the linked list. Regardless of whether the channel completes execution of its
current descriptor prior to the CCR write to clear Suspend and set Channel Resume,
the channel will re-read the current chain descriptor in response to the Channel
Resume bit. The next chain descriptor in the chain will be fetched from the address
indicated by NDAR/NDUAR, and the channel will continue execution. The appended
chain descriptor (or descriptors) will be executed after the channel reaches the end
of the original chain.
• The channel is executing the terminal chain descriptor at the time of the suspend
command. The channel will complete the final chain descriptor of the original linked
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list and examine the state of the Channel Resume bit when the Suspend bit is
cleared. As in the prior case, the channel will re-read the current chain descriptor to
update NDAR/NDUAR, load the first appended chain descriptor, and resume
execution. The only difference in this case is that the re-read operation on the
current chain description was required for proper execution (in the prior case it was
wasted effort, but did not result in erroneous behavior). If the channel had
completed execution of the terminal chain descriptor and set the “end of chain”
status bit, this bit is automatically cleared when the channel resumes operation.
• If the current transfer had a non-fatal error, it follows one of the above cases. If the
error is fatal, the channel will abort, and the software must take proper action and
restart the EDMA transfer. Note that the channel will ignore the state of the
Channel Resume bit if the abort status has not been cleared from the CSR. This
simplifies the case of linked list append, as software need not take extra steps to
verify that no errors exist prior to setting the Channel Resume bit. The normal
polling or interrupt mechanism may handle the error without interacting with the
append routine.
Note:
Software is at liberty to modify the Next Descriptor Address fields of the terminal chain
descriptor at any time after setting the Suspend bit in the CCR – there is no
requirement that software verify that the channel has gone idle prior to modifying the
memory image. Also, software does not need to verify that the channel has completed
execution of the current chain descriptor and acknowledged Suspend EDMA prior to
issuing the final update to CSR that sets the Channel Resume bit. The hardware
interlock will cover the case where the end of the chain descriptor is reached during the
append sequence, but proper operation is guaranteed regardless of whether the
interlock is exercised.
A further simplification to the linked list append sequence is possible in the case of
chain descriptors located strictly below the 4 GB boundary in memory; that is, in the
case where NDUAR of the terminal descriptor is zero and only NDAR contains asserted
bits. Under these conditions, it is safe to issue the NDAR write cycle without first
suspending operation, because there is no risk of a hybrid NDAR/NDUAR pair retrieved
by the channel. If desired, software could take the simplified approach of issuing the
descriptor update followed by a CCR write to set the Channel Resume bit. In all cases,
this will result in successful execution of the appended chain irrespective of current
execution status.
12.3.6
Splicing a Descriptor Chain into a Linked List
Software may utilize a slight modification of the algorithm described in “Appending to a
Descriptor Chain” on page 314 to splice a new descriptor or chain of descriptors into
the chain already executing. Such an operation would be useful to provide service to a
higher priority EDMA transfer without aborting work already in progress.
The steps required to splice into a chain are as follows:
1. Write to the CCR to set the Suspend EDMA bit.
2. Read the CDAR/CDUAR pair to determine which chain descriptor the EDMA channel
is currently executing.
3. Read the Next Descriptor Address field of the current chain descriptor, and write the
retrieved address into the Next Descriptor Address field of the terminal chain
descriptor in the linked list to be spliced-in.
4. Write the address of the descriptor (or lead descriptor of the chain) to be spliced-in
into the Next Descriptor Address field of the current descriptor (in memory).
5. Write to the CCR to clear the Suspend bit and set the Channel Resume bit.
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The hardware interlock of the suspend function will guarantee that the channel will not
proceed beyond the current chain descriptor until the Suspend bit has been cleared in
the CCR, and the Channel Resume function will guarantee that the current chain
descriptor will be re-read to retrieve the modified NDAR/NDUAR value pointing to the
spliced chain descriptor. The channel will resume execution with the head of the spliced
linked list, and will traverse that linked list back to its original list of chain descriptors.
Note:
The channel must refrain from updating CDAR/CDUAR from NDAR/NDUAR in addition to
dropping the returned data. Were the channel to update its CDAR/CDUAR values, it
would “skip” the entire spliced chain in response to Channel Resume, because software
would have spliced in the new descriptor chain at a position “behind” the new value for
CDAR/CDUAR in the original chain.
12.4
Transfer Types
The EDMA controller is optimized to perform high throughput data transfers between
local memory locations, and from local memory to I/O subsystem memory. Supported
transfer types are summarized in the following subsections.
12.4.1
Local Memory to Local Memory
The local memory to local memory transfer will move blocks of data specified by
descriptors from one region in main memory to another. The channel control hardware
will issue read cycles to the local memory interface using an incrementing or
decrementing source address, and place the retrieved data into a channel buffer. It will
then issue write cycles back to the memory interface using an incrementing or constant
destination address. Each EDMA channel supports pipelining making it possible for a
single channel to have multiple read and write cycles active at the same time.
All read requests to memory are a full cache-line in length (64 B), so the EDMA channel
must discard data as needed to realign the initial read in a transfer to the alignment
specified by the source address. The number of cache-line reads issued by the
controller in any given internal arbitration cycle is dependent upon the number of
available cache-line spaces in the data queue, and upon the configuration of the
inbound/outbound arbiter, but is limited to a maximum of two cache-line requests.
All write requests to memory are also a full cache-line in length, although not all bytes
must be enabled for every write. The EDMA channel is responsible for translating the
alignment specified by the destination address registers and the destination alignment
bit in DCR into a corresponding set of byte enables for the initial write in a transfer.
Once the initial alignment has been enforced, the rest of the transfer on behalf of any
given descriptor is contiguous.
12.4.2
Local Memory to I/O Subsystem Memory
The local memory to I/O memory transfer will move blocks of data specified by chain
descriptors from a source region in main memory to a destination region in the I/O
subsystem. The channel control hardware will issue read cycles to the local memory
interface using an incrementing or decrementing source address, and place the
retrieved data into a channel buffer. It will then issue write cycles to the I/O subsystem
using an incrementing or constant destination address. Each EDMA channel supports
pipelining for this transfer type as well, thus multiple read and write requests may be
outstanding from the same EDMA channel at any given time during a block transfer.
All read and write requests are full cache-line size (64 B), irrespective of alignment and
length specified in the descriptors; it is up to the EDMA channel to discard read data
and calculate write byte enables to enforce the descriptor alignment specified.
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The number of reads issued by each EDMA channel in any given internal arbitration
cycle is dependent upon the number of available cache-line spaces in the data queue,
and upon the configuration of the inbound/outbound arbiter, but is limited to a
maximum of two cache-line requests. The number of writes issued in any given
arbitration cycle is dependent upon the number of cache-lines waiting in the data
queue, and upon the CCR configuration, but is limited to a maximum of two cache-line
requests. The EDMA controller never speculatively issues a write in anticipation of data
returning from the memory subsystem.
12.4.3
I/O Memory to Local Memory
The I/O memory to local memory transfer is not supported.
12.4.4
I/O Memory to I/O Memory
The I/O memory to I/O memory transfer is not supported.
12.5
Addressing
Each EDMA is capable of 36-bit addressing on both source and destination interfaces.
Alignment specification is independent for source and destination. Transfers may be
specified to be aligned to any byte boundary except in destination constant address
modes where the granularity is greater than 1-byte.
Each EDMA channel uses direct addressing for both the source and destination
interfaces. There is no internal support for any virtual address translation.
Each EDMA channel will attempt to compensate for misalignment between source and
destination. At a minimum, misalignment will result in decreased performance at either
end of the transfer, where a second read is required prior to the first write, or viceversa.
12.5.1
Address Coherence
Each EDMA channel provides support for non-coherent access specification to improve
bandwidth and provide more consistent average latency, as well as to free the FSB for
simultaneous IA-32 core traffic. The source and destination addresses for each DMA
channel may be independently specified on a chain descriptor granularity via bit
settings in the DCR to be either coherent or non-coherent. For non-coherent accesses,
no FSB snoop cycle is issued on behalf of EDMA memory accesses to snoop processor
caches. The software must verify that snoops of IA-32 core caches are not required for
proper system operation prior to setting either of the non-coherent bits in any given
descriptor. Non-coherent accesses are used for un-cacheable memory regions, or for
cacheable regions where software can guarantee no modified state in any IA-32 core
cache by some other means.
The non-coherent attribute further implies relaxed posted write ordering as defined by
PCI/PCI-X. A non-coherent write may pass coherent posted writes en route to memory.
Software should verify that snoops of IA-32 core caches are not required for proper
system operation prior to setting either of the non-coherent bits in the DCR field of any
given descriptor. Software need not take special steps to accommodate the relaxed
ordering behavior, because each channel will only generate a single stream of output
per descriptor, and no ordering is defined between competing I/O subsystem traffic
sources. Non-coherent access may be used for uncacheable memory regions, or for
cacheable regions where software can guarantee the IA-32 core cache state has not
been modified by other means.
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An example usage model for non-coherent accesses is management of data block areas
reserved for use by an EDMA-capable peripheral device, such as a network interface
controllers (NIC). The NIC writes data directly into a buffer in memory allocated for the
exclusive use of that device. Each EDMA channel would then execute a block transfer
from that buffer to an area allocated for IA-32 core use. Both integrity verification and
security functions executed by the IA-32 core could follow such a model. As long as
software ensures that the IA-32 core never traverses the device-allocated memory, the
block transfer could be accomplished using non-coherent source address reads followed
by coherent destination address writes.
Note:
I/O subsystem destination addresses are always treated as non-coherent or coherent
based on the bit setting in the DCR. Setting the destination coherency bit will result in
the PCI-Express snoop not required attribute bit being clear, snoop required.
Example: Setting BDF 010 Offset 2C DCRx register bit 7
Destination non-coherent = 0 => Snoop not required attribute bit = 1
Destination coherent
12.5.2
= 1 => Snoop not required attribute bit = 0
Addressing Modes
Many different addressing modes are available, including standard byte movement
mode, byte reversal mode, constant address mode, and memory and buffer
initialization modes. In the examples shown for each of the following modes, a 64-bit
interface is used for simplicity. The interface could be the memory interface or an
external device on an expansion bus. Internally, the EDMA data path is significantly
wider.
12.5.2.1
Standard Byte Movement Mode
Standard byte movement mode is the most common method in which data is
transferred within the memory sub-system. In this mode, the source and destination
are specified down to the byte address. The source address is incremented as data is
read and the destination address is incremented as data is written. Transfers can be
memory to memory or memory to memory mapped I/O. Figure 12-5 illustrates a
memory to memory data transfer between unaligned 64-bit, source and destination
addresses.
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Figure 12-5. Source and Destination in Increment Mode Transfer
Memory
MSB
LSB
ADDRESS
64-bit Source
7
6
5
4
3
2
1
15
14
13
12
11
10
9
8
20
19
18
17
16
A000 0200H
A000 0208H
A000 0210H
Data Block
Transfer
1
64-bit Destination
Programmed Values
EDMACTL
4001 0300H
9
8
7
6
5
4
3
2
17
16
15
14
13
12
11
10
20
19
18
4001 0308H
4001 0310H
4001 0318H
10
0000 0088H
byte number
SUAR/SAR
A000 0201H
DUAR/DAR
4001 0307H
TCR
0000 0014H
DCR
0000 001FH
Bus Operation
SOURCE
QWORD load@A0000200
QWORD load@A0000208
QWORD load@A0000210
DESTINATION
Byte store@40010307
QWORD store@40010308
QWORD store@40010310
3-Byte store@40010318
B4484-01
12.5.2.2
Decrement/Byte Reversal Mode
Decrement/byte reversal mode is useful when an entire data stream needs to be
reversed at the byte level. This must not be confused with endian swapping, as this
implies a specific word size. In this mode, the source and destination are specified
down to the byte address. The source data is read in reverse order and written to the
destination in increasing order. Transfers can be memory to memory or memory to
memory mapped I/O. Figure 12-6 illustrates a memory to memory data transfer
between unaligned 64-bit, source and destination addresses when the source is in
decrement mode and the destination is in increment mode.
August 2009
Order Number: 320066-003US
Intel® EP80579 Integrated Processor Product Line Datasheet
319
Intel® EP80579 Integrated Processor
Figure 12-6. Source in Decrement and Destination in Increment Mode Transfer (Byte
Reversal)
Memory
MSB
LSB
ADDRESS
64-bit Source
7
6
5
4
3
2
1
15
14
13
12
11
10
9
8
20
19
18
17
16
A000 0200H
A000 0208H
A000 0210H
Data Block
Transfer
20
64-bit Destination
Programmed Values
EDMACTL
4001 0300H
12
13
14
15
16
17
18
19
4
5
6
7
8
9
10
11
1
2
3
4001 0308H
4001 0310H
4001 0318H
10
0000 0088H
byte number
SUAR/SAR
DUAR/DAR
Bus Operation
A000 0214H
4001 0307H
TCR
0000 0014H
DCR
0000 101FH
SOURCE
QWORD load@A0000210
QWORD load@A0000208
QWORD load@A0000200
DESTINATION
Byte store@40010307
QWORD store@40010308
QWORD store@40010310
3-Byte store@40010318
B4485-01
12.5.2.3
Constant Address Modes
In constant address mode, there is built-in support for “mailbox” destinations in the
memory mapped I/O subsystem. A mailbox is a single or limited set of addresses used
to collect information for dispersal later to their actual destination addresses by the
receiving device. In constant address mode, one, two, or four bytes will be sent
repeatedly until the byte count is satisfied.
The source address can be byte aligned; however, unlike other transfer modes, in
constant address Mode the destination address must be align