AD667–SPECIFICATIONS Model AD667J Typ Min DIGITAL INPUTS Resolution Logic Levels (TTL, Compatible, T MIN–TMAX)1 VIH (Logic “l’’) VIL (Logic “0”) IIH (VIH = 5.5 V) IIL (VIL = 0.8 V) (@ TA = +258C, 612 V, 615 V power supplies unless otherwise noted) Max Min AD667K Typ 12 +5.5 +0.8 10 5 +2.0 0 3 1 TRANSFER CHARACTERISTICS ACCURACY Linearity Error @ +25°C TA = TMIN to TMAX Differential Linearity Error @ +25°C TA = TMIN to TMAX Gain Error 2 Unipolar Offset Error 2 Bipolar Zero 2 +2.0 0 3 1 ±2 ±5 ±1 ±5 CONVERSION SPEED Settling Time to ± 0.01% of FSR for FSR Change (2 kΩi500 pF Load) with 10 kΩ Feedback with 5 kΩ Feedback For LSB Change Slew Rate 4 3 10 ± 2.5, ± 5, ± 10, +5, +10 ±5 3 2 1 ±5 0.05 9.90 0.1 POWER SUPPLY SENSITIVITY VCC = +11.4 V to +16.5 V dc VEE = –11.4 V to –16.5 V dc POWER SUPPLY REQUIREMENTS Rated Voltages Range4 Supply Current +11.4 V to +16.5 V dc –11.4 V to –16.5 V dc 611.4 10.00 1.0 10.10 5 5 10 10 ± 12, ± 15 616.5 8 20 TEMPERATURE RANGE Specification Storage Bits +5.5 +0.8 10 5 V V µA µA ± 15 ±3 ± 10 4 3 611.4 0 –65 +70 +125 µs µs µs V/µs 0.05 mA Ω mA 10.00 1.0 10.10 V mA 5 5 10 10 ppm of FS/% ppm of FS/% 616.5 V V 12 25 mA mA +70 +125 °C °C ± 12, ± 15 8 20 12 25 ppm of FSR/°C ppm of FSR/°C ppm of FSR/°C ppm of FSR/°C V 40 9.90 0.1 LSB LSB LSB LSB % FSR3 LSB % of FSR ± 2.5, ± 5, ± 10, +5, +10 40 REFERENCE OUTPUT External Current 12 10 ANALOG OUTPUT Ranges 4 Output Current Output Impedance (DC) Short Circuit Current ±2 ±5 ± 30 ±3 ± 10 3 2 1 Units ± 1/8 61/4 ± 1/4 61/2 ± 1/4 61/2 Monotonicity Guaranteed ± 0.1 60.2 ±1 62 ± 0.05 60.1 +1/4 61/2 ± 1/2 63/4 ± 1/2 63/4 Monotonicity Guaranteed ± 0.1 60.2 ±1 62 ± 0.05 60.1 DRIFT Differential Linearity Gain (Full Scale) T A = 25°C to TMIN or TMAX Unipolar Offset T A = –25°C to TMIN or TMAX Bipolar Zero T A = 25°C to TMIN or TMAX Max 0 –65 NOTES 1 The digital input specifications are 100% tested at +25°C, and guaranteed but not tested over the full temperature range. Adjustable to zero. 3 FSR means “Full-Scale Range” and is 20 V for ± 10 V range and 10 V for the ± 5 V range. 4 A minimum power supply of ± 12.5 V is required for a ± 10 V full-scale output and ± 11.4 V is required for all other voltage ranges. 2 Specifications subject to change without notice. Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min and max specifications are guaranteed, although only those shown in boldface are tested on all production units. TIMING SPECIFICATIONS (All Models, T A = +25°C, VCC = +12 V or +15 V, V EE = –12 V or –15 V) Symbol Parameter Min Typ Max tDC tAC tCP tDH tSETT Data Valid to End of CS Address Valid to End of CS CS Pulse Width Data Hold Time Output Voltage Settling Time 50 100 100 0 – – _ – – 2 – _ – – 4 ns ns ns ns µs ABSOLUTE MAXIMUM RATINGS VCC to Power Ground . . . . . . . . . . . . . . . . . . . . . 0 V to +18 V VEE to Power Ground . . . . . . . . . . . . . . . . . . . . . 0 V to –18 V Digital Inputs (Pins 11–15, 17–28) to Power Ground . . . . . . . . . . . . . . . . . . . . –1.0 V to +7.0 V Ref In to Reference Ground . . . . . . . . . . . . . . . . . . . . . . ± 12 V Bipolar Offset to Reference Ground . . . . . . . . . . . . . . . . ± 12 V 10 V Span R to Reference Ground . . . . . . . . . . . . . . . . . ± 12 V 20 V Span R to Reference Ground . . . . . . . . . . . . . . . . . ± 24 V Ref Out, VOUT (Pins 6, 9) . . Indefinite Short to Power Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . Momentary Short to VCC Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . 1000 mW –2– REV. A AD667 Model Min DIGITAL INPUTS Resolution Logic Levels (TTL, Compatible, TMIN–TMAX)1 VIH (Logic “l’’) VIL (Logic “0”) IIH (VIH = 5.5 V) IIL (VIL = 0.8 V) TRANSFER CHARACTERISTICS ACCURACY Linearity Error @ +25°C TA = TMIN to TMAX Differential Linearity Error @ +25°C TA = TMIN to TMAX Gain Error2 Unipolar Offset Error 2 Bipolar Zero2 +2.0 0 3 1 REFERENCE OUTPUT External Current ±2 ±5 ±1 ±5 3 2 1 TEMPERATURE RANGE Specification Storage Min ±5 +2.0 0 3 1 ±2 ±5 4 3 3 2 1 ± 2.5, ± 5, ± 10, +5, +10 10.10 5 5 10 10 8 20 –25 –65 616.5 3 1 ±2 ± 15 4 3 3 2 1 Units 12 Bits +5.5 +0.7 10 5 V V µA µA 630 63 610 4 3 ±5 611.4 10.00 1.0 10.10 5 5 10 10 ± 12, ± 15 8 20 616.5 611.4 +85 +150 –55 –65 µs µs µs V/µs 0.05 mA Ω mA 10.00 10.10 V mA 5 5 10 10 ppm of FS/% ppm of FS/% 616.5 V V 12 25 mA mA +125 +150 °C °C ± 12, ± 15 8 20 12 25 ppm of FSR/°C ppm of FSR/°C ppm of FSR/°C ppm of FSR/°C V 40 9.90 1.0 LSB LSB LSB LSB % FSR3 LSB % of FSR ± 2.5, ± 5, ± 10, +5, +10 40 9.90 0.1 –25 –65 Max ± 1/8 61/2 ± 1/8 63/4 ± 1/4 63/4 Monotonicity Guaranteed ± 0.1 60.2 ±1 62 ± 0.05 60.1 ± 15 ±3 ± 10 ± 2.5, ± 5, ± 10, +5, +10 ±5 12 25 +85 +150 AD667S Typ +2.0 0 0.05 10.00 1.0 ± 12, ± 15 Min 10 40 611.4 +5.5 +0.8 10 5 10 0.05 9.90 0.1 Max ± 1/8 61/4 ± 1/4 61/2 ± 1/4 61/2 Monotonicity Guaranteed ± 0.1 60.2 ±1 62 ± 0.05 60.1 TIMING DIAGRAMS WRITE CYCLE #1 WRITE CYCLE #2 (Load Second Rank from First Rank; A2, A1, A0 = 1) (Load First Rank from Data Bus; A3 = 1) REV. A AD667B Typ 12 ± 30 ±3 ± 10 10 POWER SUPPLY SENSITIVITY VCC = +11.4 V to +16.5 V dc VEE = –11.4 V to –16.5 V dc POWER SUPPLY REQUIREMENTS Rated Voltages Range4 Supply Current +11.4 V to +16.5 V dc –11.4 V to –16.5 V dc +5.5 +0.8 10 5 +1/4 61/2 ± 1/2 63/4 ± 1/2 63/4 Monotonicity Guaranteed ± 0.1 60.2 ±1 62 ± 0.05 60.1 ANALOG OUTPUT Ranges 4 Output Current Output Impedance (DC) Short Circuit Current Max 12 DRIFT Differential Linearity Gain (Full Scale) TA = 25°C to TMIN or TMAX Unipolar Offset TA = 25°C to TMIN or TMAX Bipolar Zero T A = 25°C to TMIN or T MAX CONVERSION SPEED Settling Time to ± 0.01% of FSR for FSR Change (2 kΩi500 pF Load) with 10 kΩ Feedback with 5 kΩ Feedback For LSB Change Slew Rate AD667A Typ –3– AD667 PIN CONNECTIONS PLCC, LCC DIP from the ideal analog output (a straight line drawn from 0 to FS – 1 LSB) for any bit combination. The AD667 is laser trimmed to 1/4 LSB (0.006% of FS) maximum error at +25°C for the K and B versions and 1/2 LSB for the J, A and S versions. ORDERING GUIDE Modell Temperature Range—8C Linearity Gain Error Max TC Max @ +258C ppm/8C Package Option2 AD667JN AD667JP AD667KN AD667KP AD667AD AD667BD AD667SD AD667SE AD667/883B 0 to +70 0 to +70 0 to +70 0 to +70 25 to +85 –25 to +85 –55 to +125 –55 to +125 –55 to +125 ± 1/2 LSB ± 1/2 LSB ± 1/4 LSB ± 1/4 LSB ± 1/2 LSB ± 1/4 LSB ± 1/2 LSB ± 1/2 LSB * 30 30 15 15 30 15 30 30 * MONOTONICITY: A DAC is said to be monotonic if the output either increases or remains constant for increasing digital inputs such that the output will always be a nondecreasing function of input. All versions of the AD667 are monotonic over their full operating temperature range. Plastic DIP (N-28) PLCC (P-28A) Plastic DIP (N-28) PLCC (P-28A) Ceramic DIP (D-28) Ceramic DIP (D-28) Ceramic DIP (D-28) LCC (E-28A) * DIFFERENTIAL NONLINEARITY: Monotonic behavior requires that the differential linearity error be less than 1 LSB both at +25°C and over the temperature range of interest. Differential nonlinearity is the measure of the variation in analog value, normalized to full scale, associated with a 1 LSB change in digital input code. For example, for a 10 volt full-scale output, a change of 1 LSB in digital input code should result in a 2.44 mV change in the analog output (1 LSB = 10 V × 1/4096 = 2.44 mV). If in actual use, however, a 1 LSB change in the input code results in a change of only 0.61 mV (1/4 LSB) in analog output, the differential linearity error would be –1.83 mV, or –3/4 LSB. The AD667K and B grades have a max differential linearity error of 1/2 LSB, which specifies that every step will be at least 1/2 LSB and at most 1 1/2 LSB. NOTES *Refer to AD667/883B military data sheet. 1 For details on grade and package offerings screened in accordance with MIL-STD883, refer to the Analog Devices Military Products Databook or current AD667/ 883B data sheet. 2 D = Ceramic DIP; E = Leadless Ceramic Chip Carrier; N = Plastic DIP; P = Plastic Leaded Chip. THE AD667 OFFERS TRUE 12-BIT PERFORMANCE OVER THE FULL TEMPERATURE RANGE LINEARITY ERROR: Analog Devices defines linearity error as the maximum deviation of the actual, adjusted DAC output Table I. Output Voltage Range Connections Output Range Digital Input Codes Connect Pin 9 to Connect Pin 1 to Connect Pin 2 to Connect Pin 4 to ± 10 V ±5 V ± 2.5 V 0 V to +10 V 0 V to +5 V Offset Binary Offset Binary Offset Binary Straight Binary Straight Binary 1 1 and 2 2 1 and 2 2 9 2 and 9 3 2 and 9 3 NC 1 and 9 9 1 and 9 9 6 (Through 50 Ω Fixed or 100 Ω Trim Resistor) 6 (Through 50 Ω Fixed or 100 Ω Trim Resistor) 6 (Through 50 Ω Fixed or 100 Ω Trim Resistor) 5 (or Optional Trim—See Figure 2) 5 (or Optional Trim—See Figure 2) –4– REV. A AD667 ANALOG CIRCUIT CONNECTIONS Internal scaling resistors provided in the AD667 may be connected to produce bipolar output voltage ranges of ±10, ±5 or ±2.5 V or unipolar output voltage ranges of 0 V to +5 V or 0 V to +10 V. Gain and offset drift are minimized in the AD667 because of the thermal tracking of the scaling resistors with other device components. Connections for various output voltage ranges are shown in Table I. Figure 3. ± 5 V Bipolar Voltage Output INTERNAL/EXTERNAL REFERENCE USE The AD667 has an internal low noise buried Zener diode reference which is trimmed for absolute accuracy and temperature coefficient. This reference is buffered and optimized for use in a high speed DAC and will give long-term stability equal or superior to the best discrete Zener reference diodes. The performance of the AD667 is specified with the internal reference driving the DAC since all trimming and testing (especially for full-scale error and bipolar offset) is done in this configuration. Figure 1. Output Amplifier Voltage Range Scaling Circuit UNIPOLAR CONFIGURATION (Figure 2) This configuration will provide a unipolar 0 volt to +10 volt output range. In this mode, the bipolar offset terminal, Pin 4, should be grounded if not used for trimming. The internal reference has sufficient buffering to drive external circuitry in addition to the reference currents required for the DAC (typically 0. 5 mA to Ref In and 1.0 mA to Bipolar Offset). A minimum of 0.1 mA is available for driving external loads. The AD667 reference output should be buffered with an external op amp if it is required to supply more than 0.1 mA output current. The reference is typically trimmed to ± 0.2%, then tested and guaranteed to ± 1.0% max error. The temperature coefficient is comparable to that of the full-scale TC for a particular grade. If an external reference is used (10.000 V, for example), additional trim range must be provided, since the internal reference has a tolerance of ± 1%, and the AD667 full-scale and bipolar offset are both trimmed with the internal reference. The gain and offset trim resistors give about ± 0.25% adjustment range, which is sufficient for the AD667 when used with the internal reference. Figure 2. 0 V to +10 V Unipolar Voltage Output STEP I . . . ZERO ADJUST Turn all bits OFF and adjust zero trimmer R1, until the output reads 0.000 volts (1 LSB = 2.44 mV). In most cases this trim is not needed, and Pin 4 should be connected to Pin 5. It is also possible to use external references other than 10 volts. The recommended range of reference voltage is from +8 to +11 volts, which allows both 8.192 V and 10.24 V ranges to be used. The AD667 is optimized for fixed-reference applications. If the reference voltage is expected to vary over a wide range in a particular application, a CMOS multiplying DAC is a better choice. STEP II . . . GAIN ADJUST Turn all bits ON and adjust 100 Ω gain trimmer R2, until the output is 9.9976 volts. (Full scale is adjusted to 1 LSB less than nominal full scale of 10.000 volts.) Reduced values of reference voltage will also permit the ± 12 volt ± 5% power supply requirement to be relaxed to ± 12 volts ± 10%. BIPOLAR CONFIGURATION (Figure 3) This configuration will provide a bipolar output voltage from –5.000 to +4.9976 volts, with positive full scale occurring with all bits ON (all 1s). It is not recommended that the AD667 be used with external feedback resistors to modify the scale factor. The internal resistors are trimmed to ratio-match and temperature-track the other resistors on the chip, even though their absolute tolerances are ± 20%, and absolute temperature coefficients are approximately –50 ppm/°C. If external resistors are used, a wide trim range (± 20%) will be needed and temperature drift will be increased to reflect the mismatch between the temperature coefficients of the internal and external resistors. STEP I . . . OFFSET ADJUST Turn OFF all bits. Adjust 100 Ω trimmer R1 to give –5.000 volts output. STEP II . . . GAIN ADJUST Turn ON all bits. Adjust 100 Ω gain trimmer R2 to give a reading of +4.9976 volts. REV. A –5– AD667 Small resistors may be added to the feedback resistors in order to accomplish small modifications in the scaling. For example, if a 10.24 V full scale is desired, a 140 Ω 1% low TC metal-film resistor can be added in series with the internal (nominal) 5k feedback resistor, and the gain trim potentiometer (between Pins 6 and 7) should be increased to 200 Ω. In the bipolar mode, increase the value of the bipolar offset trim potentiometer also to 200 Ω. b. Fine-Scale Settling, CF = 0 pF GROUNDING RULES The AD667 brings out separate analog and power grounds to allow optimum connections for low noise and high speed performance. These grounds should be tied together at one point, usually the device power ground. The separate ground returns are provided to minimize current flow in low level signal paths. The analog ground at Pin 5 is the ground point for the output amplifier and is thus the “high quality” ground for the AD667; it should be connected directly to the analog reference point of the system. The power ground at Pin 16 can be connected to the most convenient ground point; analog power return is preferred. If power ground contains high frequency noise beyond 200 mV, this noise may feed through the converter, thus some caution will be required in applying these grounds. c. Fine-Scale Settling, CF = 20 pF It is also important to apply decoupling capacitors properly on the power supplies for the AD667 and the output amplifier. The correct method for decoupling is to connect a capacitor from each power supply pin of the AD667 to the analog ground pin of the AD667. Any load driven by the output amplifier should also be referred to the analog ground pin. d. Fine-Scale Settling, CF = 0 pF OPTIMIZING SETTLING TIME The dynamic performance of the AD667’s output amplifier can be optimized by adding a small (20 pF) capacitor across the feedback resistor. Figure 4 shows the improvement in both large-signal and small-signal settling for the 10 V range. In Figure 4a, the top trace shows the data inputs (DB11–DB0 tied together), the second trace shows the CS pulse (A3–A0 tied low), and the lower two traces show the analog outputs for CF = 0 pF and 20 pF respectively. Figures 4b and 4c show the settling time for the transition from all bits on to all bits off. Note that the settling time to ± 1/2 LSB for the 10 V step is improved from 2.4 microseconds to 1.6 microseconds by the addition of the 20 pF capacitor. e. Fine-Scale Settling, CF = 20 pF Figure 4. Settling Time Performance DIGITAL CIRCUIT DETAILS Figures 4d and 4e show the settling time for the transition from all bits off to all bits on. The improvement in settling time gained by adding CC = 20 pF is similar. The bus interface logic of the AD667 consists of four independently addressable registers in two ranks. The first rank consists of three four-bit registers which can be loaded directly from a 4-, 8-, 12-, or 16-bit microprocessor bus. Once the complete 12-bit data word has been assembled in the first rank, it can be loaded into the 12-bit register of the second rank. This double-buffered organization avoids the generation of spurious analog output values. Figure 5 shows the block diagram of the AD667 logic section. The latches are controlled by the address inputs, A0–A3, and the CS input. All control inputs are active low, consistent with general practice in microprocessor systems. The four address lines each enable one of the four latches, as indicated in Table II. a. Large Scale Settling All latches in the AD667 are level-triggered. This means that data present during the time when the control signals are valid will enter the latch. When any one of the control signals returns high, the data is latched. –6– REV. A AD667 The AD667 data and control inputs will float to a Logic 0 if left open. It is recommended that any unused inputs be connected to power ground to improve noise immunity. Fanout for the AD667 is 100 when used with a standard low power Schottky gate output device. 8-BIT MICROPROCESSOR INTERFACE The AD667 interfaces easily to 8-bit microprocessor systems of all types. The control logic makes possible the use of right- or left-justified data formats. Whenever a 12-bit DAC is loaded from an 8-bit bus, two bytes are required. If the program considers the data to be a 12-bit binary fraction (between 0 and 4095/4096), the data is leftjustified, with the eight most significant bits in one byte and the remaining bits in the upper half of another byte. Right-justified data calls for the eight least significant bits to occupy one byte, with the 4 most significant bits residing in the lower half of another byte, simplifying integer arithmetic. Figure 5. AD667 Block Diagram It is permissible to enable more than one of the latches simultaneously. If a first rank latch is enabled coincident with the second rank latch, the data will reach the second rank correctly if the “WRITE CYCLE #1” timing specifications are met. Table II. AD667 Truth Table CS A3 A2 A1 A0 Operation 1 X 0 0 0 0 0 X 1 1 1 1 0 0 X 1 1 1 0 1 0 X 1 1 0 1 1 0 X 1 0 1 1 1 0 No Operation No Operation Enable 4 LSBs of First Rank Enable 4 Middle Bits of First Rank Enable 4 MSBs of First Rank Loads Second Rank from First Rank All Latches Transparent “X” = Don’t Care. Figure 7. 12-Bit Data Formats for 8-Bit Systems INPUT CODING Figure 8 shows an addressing scheme for use with an AD667 set up for left-justified data in an 8-bit system. The base address is decoded from the high-order address bits and the resultant active-low signal is applied to CS. The two LSBs of the address bus are connected as shown to the AD667 address inputs. The latches now reside in two consecutive locations, with location X01 loading the four LSBs and location X10 loading the eight MSBs and updating the output. The AD667 uses positive-true binary input coding. Logic “1” is represented by an input voltage greater than 2.0 V and Logic “0” is defined as an input voltage less than 0.8 V. Unipolar coding is straight binary, where all zeroes (000H) on the data inputs yields a zero analog output and all ones (FFFH) yields an analog output 1 LSB below full scale. Bipolar coding is offset binary, where an input code of 000H yields a minus full-scale output, an input of FFFH yields an output 1 LSB below positive full scale, and zero occurs for an input code with only the MSB on (800H). The AD667 can be used with twos complement input coding if an inverter is used on the MSB (DB11). DIGITAL INPUT CONSIDERATIONS The threshold of the digital input circuitry is set at 1.4 volts and does not vary with supply voltage. The input lines can thus interface with any type of 5 volt logic. The configuration of the input circuit is shown in Figure 6. Figure 8. Left-Justified 8-Bit Bus Interface Figure 6. Equivalent Digital Input Circuit REV. A –7– AD667 Right-justified data can be similarly accommodated. The overlapping of data lines is reversed, and the address connections are slightly different. The AD667 still occupies two adjacent locations in the processor’s memory map. In the circuit of Figure 9, location X01 loads the 8 LSBs and location X10 loads the 4 MSBs and updates the output. This configuration uses the first and second rank registers simultaneously. The CS input can be driven from an active-low decoded address. It should be noted that any data bus activity during the period when CS is low will cause activity at the AD667 output. If data is not guaranteed stable during this period, the second rank register can be used to provide double buffering. C842b–22–8/87 low, and the latch is enabled by CS going low. The AD667 thus occupies a single memory location. Figure 9. Right-Justified 8-Bit Bus Interface USING THE AD667 WITH 12- AND 16-BIT BUSES Figure 10. Connections for 12- and 16-Bit Bus Interface The AD667 is easily interfaced to 12- and 16-bit data buses. In this operation, all four address lines (A0 through A3) are tied OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Pin Plastic DIP (N) PRINTED IN U.S.A. 28-Terminal Plastic Leaded Chip Carrier (P) 28-Contact LCC (E) 28-Pin Ceramic DIP (D) –8– REV. A