SP9T GSM/UMTS Dual Mode Antenna Switch CXM3512EQ Description The CXM3512EQ is one of a range of low insertion loss, high linearity, low IMD and high power MMIC antenna switch modules for GSM/UMTS or CDMA dual-mode handsets. The Sony L.F.M.* contains SP9T switch die, CMOS decoder and a dual-LPF on GSM transmit paths for suppression of transmitter harmonics. Excellent insertion loss contributes to the good sensitivity and longer talk time. This switch also provides excellent ESD performance. * L.F.M. = Lead Frame Module (Applications: GSM (4 bands) / UMTS (3 bands, class I-VI) or CDMA (2 bands) dual-mode handset) Features Low insertion loss 0.80dB (typ.) on TX1 (915MHz) 0.95dB (typ.) on TX2 (1910MHz) 0.65dB (typ.) on RX (960MHz) 0.65dB (typ.) on TRx (1980MHz) Built-in dual-LPF Att –30dB (typ.) @2fo (Tx1 path) Att –30dB (typ.) @2fo (Tx2 path) TRXs and RXs paths are changeable for band assignment. 4 CMOS compatible control lines Low voltage operation (VDD = 2.5V) Lead-free and RoHS compliant Package Small package size: 30-pin LQFN (4.4 × 4.0 × 1.3mm) Structure GaAs Junction-gate PHEMT SW, CMOS decoder and dual-LPF Sony PHEMT GaAs process is utilized for low insertion loss. This IC is ESD sensitive device. Special handling precautions are required. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- E06X09A74 CXM3512EQ Absolute Maximum Ratings (Ta = 25°C) Bias voltage VDD 4 V Control voltage (CTL-A/B/C/D) Vctl 4 V Operating temperature Topr –20 to +90 °C Storage temperature Tstg –65 to +150 °C -2- CXM3512EQ Block Diagram Ant F1 F2 F11 F10 F13 LPF2 Tx1 F8 F9 F17 F18 F19 F12 F3 LPF1 F7 F4 F14 Rx1 Tx2 F5 F15 Rx2 Rx3 F6 F16 Rx4 TRx2 TRx1 TRx3 Note) Built-in SW control circuit Tx1 GND Tx2 Pin Configuration 13 12 11 GND 14 10 GND GND 15 9 GND NC 16 GND Pin 1 Bottom View 8 NC GND 17 7 GND Rx4 18 6 ANT Top View 2 GND GND 23 1 TRx1 24 25 26 27 28 29 30 GND GND 22 GND 3 TRx2 CTLA Rx1 21 CTLB 4 TRx3 CTLC Rx2 20 CTLD 5 GND VDD Rx3 19 NC Note) Each RX path can be used from 869 to 1990MHz frequency. User can select these RX paths suitably. -3- CXM3512EQ Pin Description Pin No. Symbol Pin No. Symbol 1 TRx1 16 NC 2 GND 17 GND 3 TRx2 18 Rx4 4 TRx3 19 Rx3 5 GND 20 Rx2 6 ANT 21 Rx1 7 GND 22 GND 8 NC 23 GND 9 GND 24 VDD 10 GND 25 CTLD 11 Tx2 (DCS/PCS) 26 CTLC 12 GND 27 CTLB 13 Tx1 (GSM850/900M) 28 CTLA 14 GND 29 GND 15 GND 30 GND Truth Table *1 *2 Vctl state Switch state Active path A B C D F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 Tx1 H H L L H L L L L L L L L L L H H H H H H H H Tx2 H L L L L H L L L L L L L L H L H H H H H H H Rx1*2 L L L L L L H L L L L L L H H H L H H H H H H Rx2*2 L L H L L L L H L L L L L H H H H L H H H H H Rx3*2 L H H L L L L L H L L L L H H H H H L H H H H Rx4*2 L H L L L L L L L H L L L H H H H H H L H H H TRx1 H L H L L L L L L L H L L L H H H H H H L H H TRx2 H H H L L L L L L L L H L L H H H H H H H L H TRx3 —*1 —*1 —*1 H L L L L L L L L H L H H H H H H H H L These states are available to set either H or L. Each RX path can be used from 869 to 1990MHz frequency. User can select these RX paths suitably. -4- CXM3512EQ Electrical Characteristics (VDD = 2.5V, Vctl = 2.5V, Ta = 25°C) Item Insertion loss *1 *2 *3 *4 *5 Symbol IL Path Condition Min. Typ. Max. Tx1 – Ant *1 — 0.80 0.95 Tx2 – Ant *2 — 0.95 1.20 Ant – TRx1 (Tx) *3 — 0.40/0.65 0.55/0.85 Ant – TRx2 (Tx) *3 — 0.40/0.65 0.55/0.85 Ant – TRx3 (Tx) *3 — 0.40/0.65 0.55/0.85 Ant – Rx1 *4 — 0.65/1.10 0.80/1.25 Ant – Rx2 *4 — 0.65/1.10 0.80/1.25 Ant – Rx3 *4 — 0.65/1.10 0.80/1.25 Ant – Rx4 *4 — 0.65/1.10 0.80/1.25 Ant – TRx1 (Rx) *5 — 0.40/0.75 0.55/0.90 Ant – TRx2 (Rx) *5 — 0.40/0.75 0.55/0.90 Ant – TRx3 (Rx) *5 — 0.40/0.75 0.55/0.90 Unit dB Frequency = 824 to 849, 890 to 915MHz, Input signal is burst, Pin = +34dBm Frequency = 1710 to 1785, 1850 to 1910MHz, Input signal is burst, Pin = +32dBm Frequency = 810 to 855/1710 to 1980MHz, Input signal is CW, Pin = +29dBm Frequency = 869 to 894, 935 to 960/1805 to 1880, 1930 to 1990MHz, Input signal is CW, Pin = –5dBm Frequency = 855 to 900/1930 to 1990, 2110 to 2170MHz, Input signal is CW, Pin = –5dBm -5- CXM3512EQ (VDD = 2.5V, Vctl = 2.5V, Ta = 25°C) Item Symbol Path Condition Min. Typ. Max. TX1 – RX1 30 45 — TX1 – RX2 30 50 — 30 45 — 30 40 — 20 30 — 20 30 — 25 35 — 25 30 — 25 35 — Unit TX Path Activated Active path: TX1 – Ant TX1 – RX3 824 to 915MHz TX1 – RX4 TX1 – TX2 1760 to 1830MHz TX1 – TRX1 TX1 – TRX2 824 to 915MHz TX1 – TRX3 Active path: TX2 – Ant TX2 – RX1 32 45 — TX2 – RX2 1710 to 1785MHz 1850 to 1910MHz 32 45 — TX2 – RX3 1850 to 1880MHz 32 45 — 32 45 — 25 33 — 25 33 — 25 33 — TRX1 – RX1 30 37 — TRX1 – RX2 30 37 — TRX1 – RX3 30 40 — 30 43 — 30 37 — TRX1 – TX2 20 28 — TRX1 – TRX2 15 19 — TRX1 – TRX3 20 28 — TRX2 – RX1 30 38 — TRX2 – RX2 30 39 — TRX2 – RX3 30 41 — 30 45 — 30 37 — TRX2 – TX2 20 29 — TRX2 – TRX1 20 28 — TRX2 – TRX3 13 18 — TX2 – RX4 TX2 – TRX1 TX2 – TRX2 Isolation ISO. 1710 to 1785MHz 1850 to 1910MHz TX2 – TRX3 Active path: TRX1 – Ant TRX1 – RX4 TRX1 – TX1 810 to 855MHz 1710 to 1980MHz Active path: TRX2 – Ant TRX2 – RX4 TRX2 – TX1 810 to 855MHz 1710 to 1980MHz -6- dB CXM3512EQ Item Symbol Path Condition Min. Typ. Max. TRX3 – RX1 30 36 — TRX3 – RX2 30 37 — TRX3 – RX3 30 40 — 30 43 — 25 36 — TRX3 – TX2 20 28 — TRX3 – TRX1 20 29 — TRX3 – TRX2 15 21 — Unit Active path: TRX3 – Ant ISO. TRX3 – RX4 TRX3 – TX1 810 to 855MHz 1710 to 1980MHz dB RX Path Activated Active path: Ant – RX1 RX1 – TX1 824 to 915MHz 30 36 — RX1 – TX2 1710 to 1910MHz 20 27 — 25 30 — 25 32 — 25 34 — RX1 – TRX1 RX1 – TRX2 810 to 855MHz 1710 to 1980MHz RX1 – TRX3 Active path: Ant – RX2 Isolation RX2 – TX1 824 to 915MHz 30 36 — RX2 – TX2 1710 to 1910MHz 20 26 — 25 30 — 25 32 — 25 34 — RX2 – TRX1 RX2 – TRX2 810 to 855MHz 1710 to 1980MHz RX2 – TRX3 Active path: Ant – RX3 ISO. RX3 – TX1 824 to 915MHz 30 35 — RX3 – TX2 1710 to 1910MHz 20 26 — RX3 – TRX1 824 to 849MHz 1710 to 1980MHz 25 31 — RX3 – TRX2 824 to 849MHz 1710 to 1980MHz 25 32 — RX3 – TRX3 824 to 849MHz 1710 to 1980MHz 25 34 — Active path: Ant – RX4 RX4 – TX1 824 to 915MHz 30 36 — RX4 – TX2 1710 to 1910MHz 20 26 — RX4 – TRX1 824 to 849MHz 1710 to 1980MHz 25 31 — RX4 – TRX2 824 to 849MHz 1710 to 1980MHz 25 32 — RX4 – TRX3 824 to 849MHz 1710 to 1980MHz 25 34 — -7- dB CXM3512EQ (VDD = 2.5V, Vctl = 2.5V, Ta = 25°C) Item Band TRX1 Condition TRX2 TRX3 Min. Typ. Min. Typ. Min. Typ. IMT fcw1 = 1950MHz, Pcw1 = +20dBm fcw2 = 190MHz, Pcw2 = –15dBm +102 +115 +102 +112 +102 +112 PCS fcw1 = 1880MHz, Pcw1 = +20dBm fcw2 = 80MHz, Pcw2 = –15dBm +102 +104 +102 +104 +102 +104 DCS fcw1 = 1745MHz, Pcw1 = +20dBm fcw2 = 95MHz, Pcw2 = –15dBm +102 +106 +102 +104 +102 +104 US cell fcw1 = 835MHz, Pcw1 = +20dBm fcw2 = 45MHz, Pcw2 = –15dBm +102 +107 +102 +104 +102 +104 IMT fcw1 = 1950MHz, Pcw1 = +20dBm fcw2 = 1760MHz, Pcw2 = –15dBm +61 +67 +61 +67 +61 +67 PCS fcw1 = 1880MHz, Pcw1 = +20dBm fcw2 = 1800MHz, Pcw2 = –15dBm +61 +63 +61 +63 +61 +63 DCS fcw1 = 1745MHz, Pcw1 = +20dBm fcw2 = 1650MHz, Pcw2 = –15dBm +61 +66 +61 +66 +61 +66 US cell fcw1 = 835MHz, Pcw1 = +20dBm fcw2 = 790MHz, Pcw2 = –15dBm +61 +67 +61 +67 +61 +67 IIP2 IIP3 Unit dBm dBm (VDD = 2.5V, Vctl = 2.5V, Ta = 25°C) Item Symbol Path Tx1 – Ant*1 Harmonic Tx2 – Ant*2 TRx1 – Ant TRx2 – Ant TRx3 – Ant*3 *1 *2 *3 Condition 2nd harmonic 1648 to 1698MHz 1780 to 1830MHz 3rd harmonic 2472 to 2547MHz 2670 to 2745MHz 2nd harmonic 3420 to 3570MHz 3700 to 3820MHz 3rd harmonic 5130 to 5355MHz 5550 to 5730MHz 2nd harmonic 1620 to 1710MHz 3420 to 3960MHz 3rd harmonic 2430 to 2565MHz 5130 to 5940MHz Burst Pin = +34dBm Burst Pin = +32dBm CW, Pin = +29dBm Min. Typ. Max. — –47 –36 — –42 –36 — –47 –35 — –39 –35 — –60/ –50 –36 — –52/ –50 –36 Unit dBm Frequency = 824 to 849, 890 to 915MHz, Input signal is burst, Pin = +34dBm Frequency = 1710 to 1785, 1850 to 1910MHz, Input signal is burst, Pin = +32dBm Frequency = 810 to 855/1710 to 1980MHz, Input signal is CW, Pin = +29dBm (VDD = 2.5V, Vctl = 2.5V, Ta = 25°C) Item Symbol Path Tx1 – Ant Attenuation Tx2 – Ant Condition Min. Typ. Max. 1648 to 1830MHz 2fo 25 30 — 2472 to 2745MHz 3fo 25 30 — 3296 to 3660MHz 4fo 20 30 — 4120 to 4575MHz 5fo 15 30 — 4944 to 5490MHz 6fo 15 25 — 5768 to 6405MHz 7fo 15 20 — 3420 to 3820MHz 2fo 25 30 — 5130 to 5730MHz 3fo 25 30 — -8- Unit dB CXM3512EQ Supply voltage (Ta = 25°C) Item Bias voltage (VDD) Min. Typ. Max. Unit 2.5 2.65 3.3 V State Min. Typ. Max. High 1.5 2.65 3.3 Low 0 — 0.3 Logic value (Ta = 25°C) Item Control voltage (CTL-A/B/C) Unit V Current consumption (Ta = 25°C) Item Condition Min. Typ. Max. Bias current VDD = 2.65V — 100 130 Control current Vctl (H) = 2.65V/1-wire — 2 5 -9- Unit μA CXM3512EQ TX2 TX1 Recommended Circuit 1 GSM (4 bands)/UMTS (3 bands) 13 12 11 GND Tx2 14 GND C5 33pF Tx1 C6 56pF GND 9 15 GND 16 NC NC 8 17 GND GND 5 GND 2 23 GND GND 22 GND GND TRx2 3 CTLA 21 Rx1 CTLB TRx3 4 CTLC 20 Rx2 24 25 26 27 28 29 30 TRx1 1 CTL-A CTL-B C11 C12 C13 C14 C15 100pF 100pF 100pF 100pF 100pF CTL-C C10∗1 19 Rx3 CTLD RX1 C9∗1 ANT 6 IC CXM3512EQ CTL-D RX2 C8∗1 18 Rx4 VDD RX3 C7∗1 GND 7 VDD RX4 GND 10 ∗1 Capacitors are required on all RF ports for DC blocking. Recommended capacitance is as follows. 56pF for 800 to 960MHz signal 33pF for 1700 to 2200MHz signal ∗2 C11 to C15 are not mandatory. ∗3 L1 inductor (56nH) is recommended on Ant port for ESD protection. - 10 - ANT C4 56pF C3∗1 C2∗1 C1∗1 L1 56nH TRX3 TRX2 TRX1 CXM3512EQ TX2 TX1 Recommended Circuit 2 GSM (3 bands)/UMTS (2 bands) 13 12 11 GND Tx2 14 GND C5 33pF Tx1 C6 56pF 15 GND GND 9 16 NC NC 8 17 GND 19 Rx3 GND 2 23 GND GND 22 GND GND TRx2 3 CTLA 21 Rx1 CTLB TRx3 4 CTLC 24 25 26 27 28 29 30 C3∗1 TRx1 1 CTL-A ∗1 DC blocking capacitors are required on all RF ports. Recommended capacitance is as follows. 56pF for 800 to 960MHz signal 33pF for 1700 to 2200MHz signal ∗2 C11 to C15 are not mandatory. ∗3 L1 inductor (56nH) is recommended on Ant port for ESD protection. - 11 - L1 56nH TRX2 C2∗1 C11 C12 C13 C14 C15 100pF 100pF 100pF 100pF 100pF CTL-B C10∗1 20 Rx2 CTL-C C9∗1 ANT C4 56pF GND 5 CTLD C8∗1 ANT 6 IC CXM3512EQ CTL-D RX2 18 Rx4 C7∗1 VDD RX3 GND 7 VDD RX4 GND 10 C1∗1 TRX1 CXM3512EQ Pad Design (Unit: mm) : Land area : Mask open area : Board resist open area PKG Outline (4.4mm) 0.95 GND Pads N.C. Pads 0.85 C 4.4mm 0.675mm PKG Outline (4.0mm) D B A Detail-A 0.2 Detail-B R0.05 0.3 PKG Outline 0.36 0.46 R0.05 0.5 Detail-D 0.2 1.0 0.85 0.9 PKG Outline 0.6 R0.05 Detail-C 0.2 0.4 Sqr. 0.3 Sqr. 0.15 0.26 0.4 - 12 - 1.95 0.21 2.5 0.1 2.4 0.75 0.6 CXM3512EQ Package Outline (Unit: mm) LEAD PLATING SPECIFICATIONS ITEM - 13 - SPEC. LEAD MATERIAL COPPER ALLOY SOLDER COMPOSITION Sn-Bi Bi:1-4wt% PLATING THICKNESS 5-18μm Sony Corporation