Dual High Speed PECL Comparators ADCMP561/ADCMP562 FEATURES FUNCTIONAL BLOCK DIAGRAM HYS* Differential PECL compatible outputs 700 ps propagation delay input to output 75 ps propagation delay dispersion Input common-mode range: –2.0 V to +3.0 V Robust input protection Differential latch control Internal latch pull-up resistors Power supply rejection greater than 85 dB 700 ps minimum pulse width 1.5 GHz equivalent input rise time bandwidth Typical output rise/fall time of 500 ps ESD protection > 4kV HBM, >200V MM Programmable hysteresis NONINVERTING INPUT Q OUTPUT ADCMP561/ ADCMP562 INVERTING INPUT LATCH ENABLE INPUT LATCH ENABLE INPUT *ADCMP562 ONLY 04687-0-001 Q OUTPUT Figure 1. VDD 1 20 VDD QA 2 19 QB 16 QB QA 3 Automatic test equipment High speed instrumentation Scope and logic analyzer front ends Window comparators High speed line receivers Threshold detection Peak detection High speed triggers Patient diagnostics Disk drive read channel detection Hand-held test instruments Zero-crossing detectors Line receivers and signal restoration Clock drivers QA 2 15 QB VDD 4 ADCMP562 17 GND VDD 3 14 GND LEA 5 TOP VIEW (Not to Scale) 16 LEB 13 LEB LEA 6 15 LEB 12 LEB VEE 7 14 VCC VEE 6 11 VCC –INA 8 13 –INB –INA 7 10 –INB +INA 9 12 +INB +INA 8 9 +INB HYSA 10 11 HYSB LEA 5 ADCMP561 TOP VIEW (Not to Scale) Figure 2. ADCMP561 16-Lead QSOP 18 QB 04687-0-003 LEA 4 04687-0-002 APPLICATIONS QA 1 Figure 3. ADCMP562 20-Lead QSOP GENERAL DESCRIPTION The ADCMP561/ADCMP562 are high speed comparators fabricated on Analog Devices’ proprietary XFCB process. The devices feature a 700 ps propagation delay with less than 75 ps overdrive dispersion. Dispersion, a measure of the difference in propagation delay under differing overdrive conditions, is a particularly important characteristic of comparators. A separate programmable hysteresis pin is available on the ADCMP562. are fully compatible with PECL 10 K and 10 KH logic families. The outputs provide sufficient drive current to directly drive transmission lines terminated in 50 Ω to VDD − 2 V. A latch input, which is included, permits tracking, track-and-hold, or sample-and-hold modes of operation. The latch input pins contain internal pull-ups that set the latch in tracking mode when left open. A differential input stage permits consistent propagation delay with a wide variety of signals in the common-mode range from −2.0 V to +3.0 V. Outputs are complementary digital signals that The ADCMP561/ADCMP562 are specified over the industrial temperature range (−40°C to +85°C). Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved. ADCMP561/ADCMP562 TABLE OF CONTENTS Specifications..................................................................................... 3 Clock Timing Recovery............................................................. 11 Absolute Maximum Ratings............................................................ 5 Optimizing High Speed Performance ..................................... 11 Thermal Considerations.............................................................. 5 Comparator Propagation Delay Dispersion ........................... 11 ESD Caution.................................................................................. 5 Comparator Hysteresis .............................................................. 12 Pin Configurations and Function Descriptions ........................... 6 Minimum Input Slew Rate Requirement ................................ 12 Typical Performance Characteristics ............................................. 8 Typical Application Circuits.......................................................... 13 Timing Information ....................................................................... 10 Outline Dimensions ....................................................................... 14 Application Information................................................................ 11 Ordering Guide .......................................................................... 14 REVISION HISTORY 7/04—Data Sheet Changed from Rev. 0 to Rev. A Changes to Specification Table ....................................................... 4 Changes to Figure 14........................................................................ 9 Changes to Figure 21...................................................................... 12 Changes to Figure 23...................................................................... 13 4/04—Revision 0: Initial Version Rev. A | Page 2 of 16 ADCMP561/ADCMP562 SPECIFICATIONS VCC = +5.0 V, VEE = −5.2 V, VDD = +3.3 V, TA = −40°C to +85°C. Typical values are at TA = +25°C, unless otherwise noted. Table 1. Electrical Characteristics Parameter DC INPUT CHARACTERISTICS Input Voltage Range Input Differential Voltage Input Offset Voltage Input Offset Voltage Channel Matching Offset Voltage Tempco Input Bias Current Input Bias Current Tempco Input Offset Current Input Capacitance Input Resistance, Differential Mode Input Resistance, Common Mode Active Gain Common-Mode Rejection Ratio Hysteresis LATCH ENABLE CHARACTERISTICS Latch Enable Voltage Range Latch Enable Differential Voltage Range Latch Enable Input High Current Latch Enable Input Low Current LE Voltage, Open LE Voltage, Open Latch Setup Time Latch Hold Time Latch-to-Output Delay Latch Minimum Pulse Width DC OUTPUT CHARACTERISTICS Output Voltage—High Level Output Voltage—Low Level Rise Time Fall Time AC PERFORMANCE Propagation Delay Propagation Delay Tempco Prop Delay Skew—Rising Transition to Falling Transition Within Device Propagation Delay Skew— Channel-to-Channel Overdrive Dispersion Overdrive Dispersion Slew Rate Dispersion Pulse Width Dispersion Duty Cycle Dispersion Common-Mode Voltage Dispersion Symbol Conditions Min VOS VCM = 0 V −2.0 −5 −10.0 ∆VOS/dT IIN −IN = −2 V, +IN = +3 V −10.0 CIN AV CMRR VCM = −2.0 V to +3.0 V RHYS = ∞ VDD − 2.0 0.4 −300 −300 VDD − 0.2 VDD/2 − 0.2 Typ ±2.0 ±2.0 2.0 ±3 0.5 ±1.0 0.75 750 1800 63 80 ±1.0 Max Unit 3.0 +5 +10.0 V V mV mV µV/°C µA nA/°C µA pF kΩ kΩ dB dB mV +10.0 VDD 2.0 +300 +300 VDD + 0.1 VDD/2 + 0.2 V V µA µA V V ps ps ps ps VDD − 0.81 VDD − 1.54 550 470 V V ps ps tS tH tPLOH, tPLOL tPL @ VDD @ VDD −2.0 V Latch inputs not connected Latch inputs not connected VOD = 250 mV VOD = 250 mV VOD = 250 mV VOD = 250 mV VOH VOL tR tF PECL 50 Ω to VDD − 2.0 V PECL 50 Ω to VDD − 2.0 V 10% to 90% 10% to 90% tPD VOD = 1 V VOD = 20 mV VOD = 1 V 700 830 0.25 ps ps ps/°C VOD = 1 V 50 ps VOD = 1 V 20 mV ≤ VOD ≤ 100 mV 100 mV ≤ VOD ≤ 1.5 V 0.4 V/ns ≤ SR ≤ 1.33 V/ns 700 ps ≤ PW ≤ 10 ns 33 MHz, 1 V/ns, 0.5 V 1 V swing, −1.5 V ≤ VCM ≤ +2.5 V 50 75 75 50 25 15 10 ps ps ps ps ps ps ps ∆tPD /dT Rev. A | Page 3 of 16 VDD VDD/2 250 250 600 500 VDD − 1.15 VDD − 1.95 ADCMP561/ADCMP562 Parameter AC PERFORMANCE (continued) Equivalent Input Rise Time Bandwidth1 Maximum Toggle Rate Minimum Pulse Width RMS Random Jitter Unit-to-Unit Propagation Delay Skew POWER SUPPLY Positive Supply Current Negative Supply Current Logic Supply Current Logic Supply Current Positive Supply Voltage Negative Supply Voltage Logic Supply Voltage Power Dissipation Power Dissipation DC Power Supply Rejection Ratio—VCC DC Power Supply Rejection Ratio—VEE DC Power Supply Rejection Ratio—VDD HYSTERESIS (ADCMP562 Only) Hysteresis 1 Symbol Conditions BWEQ 0 V to 1 V swing, 2 V/ns >50% output swing ∆tPD < 25 ps VOD = 400 mV, 1.3 V/ns, 312 MHz, 50% duty cycle PWMIN IVCC IVEE IVDD VCC VEE VDD PD @ +5.0 V @ −5.2 V @ 3.3 V without load @ 3.3 V with load Dual Dual Dual Dual, without load Dual, with load PSRRVCC PSRRVEE PSRRVDD RHYS = 19.5 kΩ RHYS = 8.0 kΩ Min 2 10 6 45 4.75 −4.96 2.5 130 180 Typ Max Unit 1500 800 700 1.0 MHz MHz ps ps 100 ps 3.2 22 9 60 5.0 −5.2 3.3 160 220 85 85 85 20 70 5 28 13 70 5.25 −5.45 5.0 190 250 mA mA mA mA V V V mW mW dB dB dB mV mV Equivalent input rise time bandwidth assumes a first-order input response and is calculated by the following formula: BWEQ = 0.22/√ (trCOMP2 – trIN2), where trIN is the 20/80 input transition time applied to the comparator and trCOMP is the effective transition time as digitized by the comparator input. Rev. A | Page 4 of 16 ADCMP561/ADCMP562 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Supply Voltages Positive Supply Voltage (VCC to GND) Negative Supply Voltage (VEE to GND) Logic Supply Voltage (VDD to GND) Ground Voltage Differential Input Voltages Input Common-Mode Voltage Differential Input Voltage Input Voltage, Latch Controls Output Output Current Temperature Operating Temperature, Ambient Operating Temperature, Junction Storage Temperature Range Rating −0.5 V to +6.0 V −6.0 V to +0.5 V −0.5 V to +6.0 V −0.5 V to +0.5 V −3.0 V to +4.0 V −7.0 V to +7.0 V −0.5 V to +5.5 V 30 mA −40°C to +85°C 125°C −65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL CONSIDERATIONS The ADCMP561 QSOP 16-lead package option has a θJA (junction-to-ambient thermal resistance) of 104°C/W in still air. The ADCMP562 QSOP 20-lead package option has a θJA (junction-to-ambient thermal resistance) of 80°C/W in still air. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. A | Page 5 of 16 ADCMP561/ADCMP562 VDD 1 20 VDD QA 2 19 QB 18 QB 16 QB QA 3 QA 2 15 QB VDD 4 ADCMP562 17 GND VDD 3 14 GND LEA 5 TOP VIEW (Not to Scale) 16 LEB 13 LEB LEA 6 15 LEB 12 LEB VEE 7 14 VCC VEE 6 11 VCC –INA 8 13 –INB –INA 7 10 –INB +INA 9 12 +INB +INA 8 9 +INB HYSA 10 11 HYSB LEA 4 ADCMP561 LEA 5 TOP VIEW (Not to Scale) 04687-0-002 QA 1 Figure 4. ADCMP561 16-Lead QSOP Pin Configuration 04687-0-003 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS Figure 5. ADCMP562 20-Lead QSOP Pin Configuration Table 3. Pin Function Descriptions Pin No. ADCMP561 ADCMP562 1 1 2 Mnemonic VDD QA 2 3 QA 3 4 4 5 VDD LEA 5 6 LEA 6 7 7 8 VEE −INA 8 9 +INA 9 10 11 12 HYSA HYSB +INB 10 13 −INB 11 12 14 15 VCC LEB 13 16 LEB Function Logic Supply Terminal. One of two complementary outputs for Channel A. QA is logic high if the analog voltage at the noninverting input is greater than the analog voltage at the inverting input (provided the comparator is in compare mode). See the description of Pin LEA for more information. One of two complementary outputs for Channel A. QA is logic low if the analog voltage at the noninverting input is greater than the analog voltage at the inverting input (provided the comparator is in compare mode). See the description of Pin LEA for more information. Logic Supply Terminal. One of two complementary inputs for Channel A Latch Enable. In compare mode (logic high), the output tracks changes at the input of the comparator. In the latch mode (logic low), the output reflects the input state just prior to the comparator’s being placed in the latch mode. LEA must be driven in conjunction with LEA. If left unconnected, the comparator defaults to compare mode. One of two complementary inputs for Channel A Latch Enable. In compare mode (logic low), the output tracks changes at the input of the comparator. In latch mode (logic high), the output reflects the input state just prior to the comparator’s being placed in the latch mode. LEA must be driven in conjunction with LEA. If left unconnected, the comparator defaults to compare mode. Negative Supply Terminal. Inverting Analog Input of the Differential Input Stage for Channel A. The inverting A input must be driven in conjunction with the noninverting A input. Noninverting Analog Input of the Differential Input Stage for Channel A. The noninverting A input must be driven in conjunction with the inverting A input. Programmable Hysteresis Input. Programmable Hysteresis Input. Noninverting Analog Input of the Differential Input Stage for Channel B. The noninverting B input must be driven in conjunction with the inverting B input. Inverting Analog Input of the Differential Input Stage for Channel B. The inverting B input must be driven in conjunction with the noninverting B input. Positive Supply Terminal. One of two complementary inputs for Channel B Latch Enable. In compare mode (logic low), the output tracks changes at the input of the comparator. In latch mode (logic high), the output reflects the input state just prior to placing the comparator in the latch mode. LEB must be driven in conjunction with LEB. If left unconnected, the comparator defaults to compare mode. One of two complementary inputs for Channel B Latch Enable. In compare mode (logic high), the output tracks changes at the input of the comparator. In latch mode (logic low), the output reflects the input state just prior to placing the comparator in the latch mode. LEB must be driven in conjunction with LEB. If left unconnected, the comparator defaults to compare mode. Rev. A | Page 6 of 16 ADCMP561/ADCMP562 Pin No. ADCMP561 ADCMP562 14 17 15 18 Mnemonic GND QB 16 19 QB 20 VDD Function Analog Ground. One of two complementary outputs for Channel B. QB is logic low if the analog voltage at the noninverting input is greater than the analog voltage at the inverting input (provided the comparator is in compare mode). See the description of PIN LEB for more information. One of two complementary outputs for Channel B. QB is logic high if the analog voltage at the noninverting input is greater than the analog voltage at the inverting input (provided the comparator is in compare mode). See the description of Pin LEB for more information. Logic Supply Terminal. Rev. A | Page 7 of 16 ADCMP561/ADCMP562 TYPICAL PERFORMANCE CHARACTERISTICS VCC = +5.0 V, VEE = –5.2 V, VDD = +3.3 V, TA = 25°C, unless otherwise noted. 3.0 2.80 2.78 1.5 1.0 0.5 0 –0.5 –1.0 –2.5 –1.5 –0.5 0.5 1.5 2.5 2.76 2.74 2.72 2.70 2.68 2.66 2.64 04687-0-016 +IN INPUT BIAS CURRENT (µA) (+IN = 3V, –IN = 0V) 2.0 04687-0-013 INPUT BIAS CURRENT (µA) 2.5 2.62 2.60 –40 3.5 –20 0 NONINVERTING INPUT VOLTAGE (INVERTING VOLTAGE = 0V) 20 40 60 80 TEMPERATURE (°C) Figure 6. Input Bias Current vs. Input Voltage Figure 9. Input Bias Current vs. Temperature 2.00 2.6 1.95 2.4 OUTPUT RISE AND FALL (V) 1.85 1.80 1.75 1.70 1.65 1.60 1.50 –40 –20 0 20 40 60 2.0 1.8 1.6 04687-0-014 1.55 2.2 04687-0-017 OFFSET VOLTAGE (mV) 1.90 1.4 80 0 0.25 0.50 0.75 TEMPERATURE (°C) 500 570 495 565 490 560 485 555 480 550 545 535 460 530 30 40 2.00 470 465 20 1.75 475 540 10 1.50 50 60 70 80 04687-0-018 TIME (ps) 575 0 1.25 Figure 10. Rise and Fall of Outputs vs. Time 04687-0-015 TIME (ps) Figure 7. Input Offset Voltage vs. Temperature 525 –40 –30 –20 –10 1.00 TIME (ns) 455 450 –40 –30 –20 –10 90 TEMPERATURE (°C) 0 10 20 30 40 50 60 TEMPERATURE (°C) Figure 8. Rise Time vs. Temperature Figure 11. Fall Time vs. Temperature Rev. A | Page 8 of 16 70 80 90 715 708 710 706 PROPAGATION DELAY (ps) 705 700 695 690 680 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 702 700 698 696 04687-0-019 685 704 04687-0-022 PROPAGATION DELAY (ps) ADCMP561/ADCMP562 694 –2 90 –1 TEMPERATURE (°C) Figure 12. Propagation Delay vs. Temperature 2 3 25 100 80 60 40 04687-0-020 20 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 20 15 10 5 0 –5 0.7 1.6 04687-0-023 PROPAGATION DELAY ERROR (ps) 120 0 1.7 2.7 3.7 OVERDRIVE VOLTAGE (V) 140 140 120 100 80 60 04687-0-021 40 20 0 30 20 6.7 7.7 8.7 9.7 10 120 100 80 60 40 04687-0-024 PROGRAMMED HYSTERESIS (mV) 160 40 5.7 Figure 16. Propagation Delay Error vs. Pulse Width 160 50 4.7 PULSE WIDTH (ns) Figure 13. Propagation Delay vs. Overdrive Voltage PROGRAMMED HYSTERESIS (mV) 1 Figure 15. Propagation Delay vs. Common-Mode Voltage 140 PROPAGATION DELAY ERROR (ps) 0 INPUT COMMON-MODE VOLTAGE (V) 20 0 0 0 50 100 IHYS (µA) RHYS (kΩ) Figure 17. Comparator Hysteresis vs. IHYS Figure 14. Comparator Hysteresis vs. RHYS Rev. A | Page 9 of 16 150 ADCMP561/ADCMP562 TIMING INFORMATION LATCH ENABLE 50% LATCH ENABLE tS tPL tH DIFFERENTIAL INPUT VOLTAGE VIN VREF ± VOS VOD tPDL tPLOH Q OUTPUT 50% tF tPDH Q OUTPUT tPLOL tR 04687-0-004 50% Figure 18. System Timing Diagram Figure 18 shows the compare and latch features of the ADCMP561/ADCMP562. Table 4 describes the terms in the diagram. Table 4. Timing Descriptions Symbol tPDH Timing Input to Output High Delay tPDL Input to Output Low Delay tPLOH Latch Enable to Output High Delay tPLOL Latch Enable to Output Low Delay tH Minimum Hold Time tPL tS Minimum Latch Enable Pulse Width Minimum Setup Time tR Output Rise Time tF Output Fall Time VOD Voltage Overdrive Description Propagation delay measured from the time the input signal crosses the reference (± the input offset voltage) to the 50% point of an output low-to-high transition. Propagation delay measured from the time the input signal crosses the reference (± the input offset voltage) to the 50% point of an output high-to-low transition. Propagation delay measured from the 50% point of the latch enable signal low-to-high transition to the 50% point of an output low-to-high transition. Propagation delay measured from the 50% point of the latch enable signal low-to-high transition to the 50% point of an output high-to-low transition. Minimum time after the negative transition of the latch enable signal that the input signal must remain unchanged to be acquired and held at the outputs. Minimum time the latch enable signal must be high to acquire an input signal change. Minimum time before the negative transition of the latch enable signal that an input signal change must be present to be acquired and held at the outputs. Amount of time required to transition from a low to a high output as measured at the 20% and 80% points. Amount of time required to transition from a high to a low output as measured at the 20% and 80% points. Difference between the differential input and reference input voltages. Rev. A | Page 10 of 16 ADCMP561/ADCMP562 APPLICATION INFORMATION The ADCMP561/ADCMP562 comparators are very high speed devices. Consequently, high speed design techniques must be employed to achieve the best performance. The most critical aspect of any ADCMP561/ADCMP562 design is the use of a low impedance ground plane. A ground plane, as part of a multilayer board, is recommended for proper high speed performance. Using a continuous conductive plane over the surface of the circuit board can create this, allowing breaks in the plane only for necessary signal paths. The ground plane provides a low inductance ground, eliminating any potential differences at different ground points throughout the circuit board caused by ground bounce. A proper ground plane also minimizes the effects of stray capacitance on the circuit board. It is also important to provide bypass capacitors for the power supply in a high speed application. A 1 µF electrolytic bypass capacitor should be placed within 0.5 inches of each power supply pin to ground. These capacitors reduce any potential voltage ripples from the power supply. In addition, a 10 nF ceramic capacitor should be placed as close as possible from the power supply pins on the ADCMP561/ADCMP562 to ground. These capacitors act as a charge reservoir for the device during high frequency switching. The LATCH ENABLE input is active low (latched). If the latching function is not used, the LATCH ENABLE input may be left open or may be attached to VDD (VDD is a PECL logic high). The complementary input, LATCH ENABLE, may be left open or may be tied to VDD − 2.0 V. Leaving the latch inputs unconnected or providing the proper voltages disables the latching function. Occasionally, one of the two comparator stages within the ADCMP561/ADCMP562 is not used. The inputs of the unused comparator should not be allowed to float. The high internal gain may cause the output to oscillate (possibly affecting the comparator that is being used) unless the output is forced into a fixed state. This is easily accomplished by ensuring that the two inputs are at least one diode drop apart, while also appropriately connecting the LATCH ENABLE and LATCH ENABLE inputs as described previously. The best performance is achieved with the use of proper PECL terminations. The open emitter outputs of the ADCMP561/ ADCMP562 are designed to be terminated through 50 Ω resistors to VDD − 2.0 V, or any other equivalent PECL termination. If high speed PECL signals must be routed more than a centimeter, microstrip or stripline techniques may be required to ensure proper transition times and prevent output ringing. CLOCK TIMING RECOVERY Comparators are often used in digital systems to recover clock timing signals. High speed square waves transmitted over a distance, even tens of centimeters, can become distorted due to stray capacitance and inductance. Poor layout or improper termination can also cause reflections on the transmission line, further distorting the signal waveform. A high speed comparator can be used to recover the distorted waveform while maintaining a minimum of delay. OPTIMIZING HIGH SPEED PERFORMANCE As with any high speed comparator amplifier, proper design and layout techniques should be used to ensure optimal performance from the ADCMP561/ADCMP562. The performance limits of high speed circuitry can be a result of stray capacitance, improper ground impedance, or other layout issues. Minimizing resistance from source to the input is an important consideration in maximizing the high speed operation of the ADCMP561/ADCMP562. Source resistance in combination with equivalent input capacitance could cause a lagged response at the input, thus delaying the output. The input capacitance of the ADCMP561/ADCMP562, in combination with stray capacitance from an input pin to ground, could result in several picofarads of equivalent capacitance. A combination of 3 kΩ source resistance and 5 pF of input capacitance yields a time constant of 15 ns, which is significantly slower than the 750 ps capability of the ADCMP561/ADCMP562. Source impedances should be significantly less than 100 Ω for best performance. Sockets should be avoided due to stray capacitance and inductance. If proper high speed techniques are used, the devices should be free from oscillation when the comparator input signal passes through the switching threshold. COMPARATOR PROPAGATION DELAY DISPERSION The ADCMP561/ADCMP562 have been specifically designed to reduce propagation delay dispersion over an input overdrive range of 100 mV to 1.5 V. Propagation delay overdrive dispersion is the change in propagation delay that results from a change in the degree of overdrive (how far the switching point is exceeded by the input). The overall result is a higher degree of timing accuracy because the ADCMP561/ADCMP562 are far less sensitive to input variations than most comparator designs. Rev. A | Page 11 of 16 ADCMP561/ADCMP562 Propagation delay dispersion is a specification that is important in critical timing applications such as ATE, bench instruments, and nuclear instrumentation. Overdrive dispersion is defined as the variation in propagation delay as the input overdrive conditions are changed (Figure 19). For the ADCMP561 and ADCMP562, overdrive dispersion is typically 75 ps as the overdrive is changed from 100 mV to 1.5 V. This specification applies for both positive and negative overdrive because the ADCMP561/ADCMP562 have equal delays for positive and negative going inputs. hysteresis versus resistance curve is shown in Figure 21. A current source can also be used with the HYS pin. The relationship between the current applied to the HYS pin and the resulting hysteresis is shown in Figure 17. +VH 2 –VH 2 0V INPUT 1 1.5V OVERDRIVE INPUT VOLTAGE 20mV OVERDRIVE 04687-0-006 0 VREF ± VOS Q OUTPUT 04687-0-005 OUTPUT DISPERSION Figure 20. Comparator Hysteresis Transfer Function Figure 19. Propagation Delay Dispersion 160 COMPARATOR HYSTERESIS Positive feedback from the output to the input is often used to produce hysteresis in a comparator (Figure 24). The major problem with this approach is that the amount of hysteresis varies with the output logic levels, resulting in a hysteresis that is not symmetrical around zero. In the ADCMP562, hysteresis is generated through the programmable hysteresis pin. A resistor from the HYS pin to GND creates a current into the part that is used to generate hysteresis. Hysteresis generated in this manner is independent of output swing and is symmetrical around the trip point. The 120 100 80 60 40 04687-0-021 The addition of hysteresis to a comparator is often useful in a noisy environment, or where it is not desirable for the comparator to toggle between states when the input signal is at the switching threshold. The transfer function for a comparator with hysteresis is shown in Figure 20. If the input voltage approaches the threshold from the negative direction, the comparator switches from a 0 to a 1 when the input crosses +VH/2. The new switching threshold becomes −VH/2. The comparator remains in a 1 state until the threshold −VH/2 is crossed, coming from the positive direction. In this manner, noise centered on 0 V input does not cause the comparator to switch states unless it exceeds the region bounded by ±VH/2. PROGRAMMED HYSTERESIS (mV) 140 20 0 50 40 30 20 10 0 RHYS (kΩ) Figure 21. Comparator Hysteresis vs. RHYS MINIMUM INPUT SLEW RATE REQUIREMENT As for all high speed comparators, a minimum slew rate must be met to ensure that the device does not oscillate when the input crosses the threshold. This oscillation is due in part to the high input bandwidth of the comparator and the parasitics of the package. Analog Devices recommends a slew rate of 1 V/µs or faster to ensure a clean output transition. If slew rates less than 1 V/µs are used, hysteresis should be added to reduce the oscillation. Rev. A | Page 12 of 16 ADCMP561/ADCMP562 TYPICAL APPLICATION CIRCUITS VIN VREF VIN ADCMP561/ ADCMP562 OUTPUTS ADCMP562 VREF OUTPUTS HYS VDD – 2.0V VDD – 2V 04687-0-008 ALL RESISTORS 50Ω ALL RESISTORS 50Ω, UNLESS OTHERWISE NOTED Figure 22. High Speed Sampling Circuits +VREF VIN ADCMP561/ ADCMP562 Figure 24. Adding Hysteresis Using the HYS Control Pin OUTPUTS VIN ADCMP561/ ADCMP562 100Ω ADCMP561/ ADCMP562 50Ω 50Ω 100Ω Figure 25. How to Interface a PECL Output to an Instrument with a 50 Ω to Ground Input OUTPUTS VDD –2V ALL RESISTORS 50Ω UNLESS OTHERWISE NOTED 04687-0-009 LATCH ENABLE INPUTS 50Ω (VDD – 2V) × 2 VDD –2V –VREF 50Ω Figure 23. High Speed Window Comparator Rev. A | Page 13 of 16 04687-0-012 LATCH ENABLE INPUTS 04687-0-010 0Ω TO 80kΩ ADCMP561/ADCMP562 OUTLINE DIMENSIONS 0.193 BSC 9 16 0.154 BSC 1 0.236 BSC 8 PIN 1 0.069 0.053 0.065 0.049 0.010 0.025 0.004 BSC COPLANARITY 0.004 0.012 0.008 SEATING PLANE 0.010 0.006 8° 0° 0.050 0.016 COMPLIANT TO JEDEC STANDARDS MO-137AB Figure 26. 16-Lead Shrink Small Outline Package [QSOP] (RQ-16) Dimensions shown in inches 0.341 BSC 20 11 0.154 BSC 1 0.236 BSC 10 PIN 1 0.065 0.049 0.010 0.004 0.069 0.053 0.025 BSC 0.012 0.008 SEATING PLANE COPLANARITY 0.004 0.010 0.006 8° 0° 0.050 0.016 COMPLIANT TO JEDEC STANDARDS MO-137AD Figure 27. 20-Lead Shrink Small Outline Package [QSOP] (RQ-20) Dimensions shown in inches ORDERING GUIDE Model ADCMP561BRQ ADCMP562BRQ Temperature Range −40°C to +85°C −40°C to +85°C Package Description 16-Lead QSOP 20-Lead QSOP Rev. A | Page 14 of 16 Package Option RQ-16 RQ-20 ADCMP561/ADCMP562 NOTES Rev. A | Page 15 of 16 ADCMP561/ADCMP562 NOTES © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04687–0–7/04(A) Rev. A | Page 16 of 16