AD ADSP-BF548 Embedded processor Datasheet

Blackfin®
Embedded Processor
ADSP-BF542/BF544/BF547/BF548/BF549
•
Preliminary Technical Data
FEATURES
PERIPHERALS
Up to 600 MHz High-Performance Blackfin Processor
Two 16-Bit MACs, Two 40-Bit ALUs, Four 8-Bit Video ALUs
RISC-Like Register and Instruction Model
0.9 V to 1.3 V Core VDD with On-chip Voltage Regulation
2.5 V and 3.3 V-Tolerant I/O with Specific 5V-Tolerant Pins
400-ball Lead-Free mBGA and 360-ball Lead-Free pBGA package options.
High-Speed USB On-the-Go (OTG) with Integrated PHY
SD/SDIO Controller
ATA/ATAPI-6 Controller
Up to four Synchronous Serial Ports (SPORTs)
Up to three Serial Peripheral Interfaces (SPI-Compatible)
Up to four UARTs, two with Automatic Hardware Flow
Control
Up to two CAN (Controller Area Network) 2.0B Interfaces
Up to two TWI (Two-Wire Interface) Controllers
8- or 16-Bit Asynchronous Host DMA Interface
Multiple Enhanced Parallel Peripheral Interfaces (EPPIs), Supporting ITU-R BT.656 Video Formats and 18/24-bit LCD
Connections
Media Transceiver (MXVR) for connection to a MOST®
Network
Pixel Compositor for overlays, alpha blending, and color
conversion
Up to eleven 32-Bit Timers/Counters with PWM Support
Real-Time Clock (RTC) and Watchdog Timer
Up/Down Counter With Support for Rotary Encoder
Up to 152 General Purpose I/O (GPIOs)
On-Chip PLL Capable of 0.5x to 64x Frequency Multiplication
Debug/JTAG Interface
MEMORY
Up to 324K bytes of on-chip memory comprised of:
Instruction SRAM/cache; instruction SRAM;
data SRAM/cache; additional dedicated data SRAM;
scratchpad SRAM (see Table 1 on Page 3 for available
memory configurations
External Sync Memory Controller Supporting
DDR/Mobile DDR SDRAM
External Async Memory Controller Supporting 8/16 bit Async
Memories and Burst Flash Devices
NAND Flash Controller
Four Memory-to-Memory DMA pairs, two with ext. requests
Memory Management Unit Providing Memory Protection
Flexible Booting Options
Code Security with LockboxTM Secure Technology
One-Time-Programmable (OTP) Memory
VOLTAGE
REGULATOR
CAN (0-1)
JTAG TEST AND
EMULATION
RTC
WATCHDOG
TIMER
OTP
TWI (0-1)
PAB 16
B
TIMERS(0-10)
PORTS
HOST DMA
INTERRUPTS
UART (0-1)
COUNTER
UART (2-3)
L2
SRAM
KEYPAD
L1
INSTR ROM
L1
INSTR SRAM
L1
DATA SRAM
SPI (2)
32-BIT DMA
MXVR
DCB 32
EAB 64
DAB1
DEB 32
PORTS
SPI (0-1)
32
SPORT (2-3)
USB
16-BIT DMA
DAB0
BOOT
ROM
EXTERNAL PORT
NOR, DDR1 CONTROL
16
SPORT (0-1)
SD / SDIO
ATAPI
DDR1
ASYNC
16
16
EPPI (0-2)
NAND FLASH
CONTRLOLLER
PIXEL
COMPOSITOR
• Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.
Rev. PrG
Figure 1. ADSP-BF549 Functional Block Diagram
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel:781/329-4700
www.analog.com
Fax:781/461-3113
© 2007 Analog Devices, Inc. All rights reserved.
ADSP-BF542/4/7/8/9
Preliminary Technical Data
TABLE OF CONTENTS
General Description ................................................. 3
Dynamic Power Management ................................ 16
Low-Power Architecture ......................................... 4
Voltage Regulation .............................................. 17
System Integration ................................................ 4
Clock Signals ...................................................... 17
ADSP-BF542/4/7/8/9 Processor Peripherals ................ 4
Booting Modes ................................................... 19
Blackfin Processor Core .......................................... 4
Instruction Set Description .................................... 22
Memory Architecture ............................................ 5
Development Tools .............................................. 22
DMA Controllers ................................................ 10
Designing an Emulator-Compatible Processor Board
(Target) ......................................................... 22
Real-Time Clock ................................................. 11
Watchdog Timer ................................................ 12
Related Documents .............................................. 22
Timers ............................................................. 12
Pin Descriptions .................................................... 23
Up/Down Counter and Thumbwheel Interface .......... 12
Specifications ........................................................ 32
Serial Ports (SPORTs) .......................................... 12
Operating Conditions ........................................... 32
Serial Peripheral Interface (SPI) Ports ...................... 13
Electrical Characteristics ....................................... 34
UART Ports (UARTs) .......................................... 13
ESD Sensitivity ................................................... 34
Controller Area Network (CAN) ............................ 13
Absolute Maximum Ratings ................................... 35
TWI Controller Interface ...................................... 14
Package Information ............................................ 35
Ports ................................................................ 14
Timing Specifications ........................................... 36
Pixel Compositor (PIXC) ...................................... 14
Power Dissipation ............................................... 64
Enhanced Parallel Peripheral Interface (EPPI) ........... 14
Test Conditions .................................................. 64
USB On-The-Go Dual-Role Device Controller ........... 15
Environmental Conditions .................................... 65
ATA/ATAPI–6 Interface ...................................... 15
400-Ball CSP_BGA PACKAGE .................................. 67
Keypad Interface ................................................. 15
360-Ball pBGA PACKAGE ....................................... 73
Secure Digital (SD)/SDIO Controller ....................... 15
Outline Dimensions ................................................ 79
Code Security .................................................... 15
Surface Mount Design .......................................... 81
Media Transceiver Mac Layer (MXVR) .................... 16
Ordering Guide ..................................................... 82
REVISION HISTORY
Revision PrG: Corrections and additions to PrF:
• Addition of DDR and Mobile DDR Timing parameters.
Rev. PrG
|
Page 2 of 82 |
December 2007
ADSP-BF542/4/7/8/9
Preliminary Technical Data
GENERAL DESCRIPTION
Specific peripherals for ADSP-BF542/4/7/8/9 processors are
shown in Table 2.
Module
ADSP-BF548
ADSP-BF547
ADSP-BF544
ADSP-BF542
Table 2. ADSP-BF54x Specific Peripherals for Processors
ADSP-BF549
The ADSP-BF542/4/7/8/9 processors are members of the Blackfin family of products, incorporating the Analog Devices/Intel
Micro Signal Architecture (MSA). Blackfin processors combine
a dual-MAC state-of-the-art signal processing engine, the
advantages of a clean, orthogonal RISC-like microprocessor
instruction set, and single-instruction, multiple-data (SIMD)
multimedia capabilities into a single instruction-set
architecture.
EBIU (async)
3
3
3
3
3
NAND Flash Controller
3
3
3
3
3
Specific performance and memory configurations for
ADSP-BF542/4/7/8/9 processors are shown in Table 1.
3
–
ADSP-BF542
–
3
ADSP-BF544
3
3
EPPI0
1
1
1
1
1
EPPI1
SD/SDIO Controller
3
3
3
–
3
3
3
3
3
–
3
3
3
3
3
EPPI2
3
3
3
3
3
1
1
1
–
1
Pixel Compositor
1
1
1
1
1
SPORT0
3
3
3
–
–
3
3
3
3
3
18- or 24-bit EPPI0 with LCD
1
1
1
1
–
SPORT1
16-bit EPPI1, 8-bit EPPI2
1
1
1
1
1
SPORT2
3
3
3
3
3
3
3
3
3
3
Host DMA Port
1
1
1
1
–
SPORT3
NAND Flash Controller
1
1
1
1
1
SPI0
3
3
3
3
3
SPI1
3
3
3
3
3
ATAPI
1
1
1
–
1
High Speed USB OTG
1
1
1
–
1
SPI2
3
3
3
–
–
3
3
3
3
3
Keypad Interface
1
1
1
–
1
UART0
MXVR
1
–
–
–
–
UART1
3
3
3
3
3
3
3
3
–
–
1
TWI ports
2
2
–
2
1
UART2
2
2
2
2
1
UART3
3
3
3
3
3
3
3
3
–
3
SPI ports
3
3
3
2
2
High Speed USB OTG
UART ports
4
4
4
3
3
CAN01
3
3
–
3
3
3
3
–
3
–
SPORTs
4
4
4
3
3
CAN11
Up / Down Counter
1
1
1
1
1
TWI0
3
3
3
3
3
8
TWI1
3
3
3
3
–
Timers
11
General-purpose I/O pins
152 152 152 152 152
Timer 0-7
3
3
3
3
3
16
16
16
16
16
Timer 8-10
3
3
3
3
–
48
48
48
48
48
Up / Down Counter
3
3
3
3
3
Keypad Interface
3
3
3
–
3
L1 Instruction SRAM/Cache
Memory
Configura- L1 Instruction SRAM
tions
L1 Data SRAM/Cache
(K Bytes)
L1 Data SRAM
11
11
11
32
32
32
32
32
32
32
32
32
32
MXVR
3
–
–
–
–
GPIOs
3
3
3
3
3
L1 Scratchpad SRAM
4
4
4
4
4
L1 ROM2
64
64
64
64
64
L2
128 128 128 64
L3 Boot ROM2
Maximum Core Instruction Rate (MHz)
2
3
3
SD/SDIO Controller
CAN ports
1
3
3
ADSP-BF547
LockboxTM Code Security
ATAPI
Host DMA Port (HOSTDP)
ADSP-BF548
Processor
Features
ADSP-BF549
Table 1. ADSP-BF542/4/7/8/9 Processor Features
4
4
4
4
–
1
CAN on the ADSP-BF544 and ADSP-BF542 is only available on automotive
grade devices.
4
533 600 600 533 600
Automotive Only.
This ROM is not customer configurable.
Rev. PrG
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Page 3 of 82 |
December 2007
ADSP-BF542/4/7/8/9
Preliminary Technical Data
The ADSP-BF542/4/7/8/9 processors are completely code and
pin compatible. They differ only with respect to their performance, on-chip memory, and selection of I/O peripherals.
Specific performance, memory, and feature configurations, are
shown in Table 1.
memory spaces, including external DDR and asynchronous
memory. Multiple on-chip buses running at up to 133 MHz
provide enough bandwidth to keep the processor core running
along with activity on all of the on-chip and external
peripherals.
By integrating a rich set of industry-leading system peripherals
and memory, Blackfin processors are the platform of choice for
next-generation applications that require RISC-like programmability, multimedia support and leading-edge signal
processing in one integrated package.
The ADSP-BF542/4/7/8/9 processor includes an on-chip voltage regulator in support of the ADSP-BF542/4/7/8/9 processor
dynamic power management capability. The voltage regulator
provides a range of core voltage levels when supplied from a single 2.70 V to 3.6 V input. The voltage regulator can be bypassed
at the user's discretion.
LOW-POWER ARCHITECTURE
Blackfin processors provide world-class power management
and performance. Blackfin processors are designed in a low
power and low voltage design methodology and feature on-chip
dynamic power management, the ability to vary both the voltage
and frequency of operation to significantly lower overall power
consumption. Varying the voltage and frequency can result in a
substantial reduction in power consumption, compared with
just varying the frequency of operation. This translates into
longer battery life for portable appliances.
SYSTEM INTEGRATION
The ADSP-BF542/4/7/8/9 processors are highly integrated system-on-a-chip solutions for the next generation of embedded
network connected applications. By combining industry-standard interfaces with a high performance signal processing core,
users can develop cost-effective solutions quickly without the
need for costly external components. The system peripherals
include a high speed USB OTG (On-The-Go) controller with
integrated PHY, CAN 2.0B controllers, TWI controllers, UART
ports, SPI ports, serial ports (SPORTs), ATAPI controller,
SD/SDIO controller, a real-time clock, a watchdog timer, LCD
controller, and multiple enhanced parallel peripheral interfaces.
ADSP-BF542/4/7/8/9 PROCESSOR PERIPHERALS
The ADSP-BF542/4/7/8/9 processor contains a rich set of
peripherals connected to the core via several high bandwidth
buses, providing flexibility in system configuration as well as
excellent overall system performance (see Figure 1 on Page 1).
The general-purpose peripherals include functions such as
UARTs, SPI, TWI, timers with pulse width modulation (PWM)
and pulse measurement capability, general purpose I/O pins, a
real-time clock, and a watchdog timer. This set of functions satisfies a wide variety of typical system support needs and is
augmented by the system expansion capabilities of the part. The
ADSP-BF542/4/7/8/9 processor contains dedicated network
communication modules and high-speed serial and parallel
ports, an interrupt controller for flexible management of interrupts from the on-chip peripherals or external sources, and
power management control functions to tailor the performance
and power characteristics of the processor and system to many
application scenarios.
All of the peripherals, except for general-purpose I/O, CAN,
TWI, real-time clock, and timers, are supported by a flexible
DMA structure. There are also separate memory DMA channels
dedicated to data transfers between the processor's various
Rev. PrG
|
Page 4 of 82 |
BLACKFIN PROCESSOR CORE
As shown in Figure 2 on Page 5, the Blackfin processor core
contains two 16-bit multipliers, two 40-bit accumulators, two
40-bit ALUs, four video ALUs, and a 40-bit shifter. The computation units process 8-bit, 16-bit, or 32-bit data from the register
file.
The compute register file contains eight 32-bit registers. When
performing compute operations on 16-bit operand data, the
register file operates as 16 independent 16-bit registers. All
operands for compute operations come from the multiported
register file and instruction constant fields.
Each MAC can perform a 16-bit by 16-bit multiply in each
cycle, accumulating the results into the 40-bit accumulators.
Signed and unsigned formats, rounding, and saturation are
supported.
The ALUs perform a traditional set of arithmetic and logical
operations on 16-bit or 32-bit data. In addition, many special
instructions are included to accelerate various signal processing
tasks. These include bit operations such as field extract and population count, modulo 232 multiply, divide primitives, saturation
and rounding, and sign/exponent detection. The set of video
instructions include byte alignment and packing operations, 16bit and 8-bit adds with clipping, 8-bit average operations, and 8bit subtract/absolute value/accumulate (SAA) operations. Also
provided are the compare/select and vector search instructions.
For certain instructions, two 16-bit ALU operations can be performed simultaneously on register pairs (a 16-bit high half and
16-bit low half of a compute register). By also using the second
ALU, quad 16-bit operations are possible.
The 40-bit shifter can perform shifts and rotates and is used to
support normalization, field extract, and field deposit
instructions.
The program sequencer controls the flow of instruction execution, including instruction alignment and decoding. For
program flow control, the sequencer supports PC relative and
indirect conditional jumps (with static branch prediction), and
subroutine calls. Hardware is provided to support zero-overhead looping. The architecture is fully interlocked, meaning that
the programmer need not manage the pipeline when executing
instructions with data dependencies.
The address arithmetic unit provides two addresses for simultaneous dual fetches from memory. It contains a multiported
register file consisting of four sets of 32-bit index, modify,
December 2007
ADSP-BF542/4/7/8/9
Preliminary Technical Data
The architecture provides three modes of operation: user mode,
supervisor mode, and emulation mode. User mode has
restricted access to certain system resources, thus providing a
protected software environment, while supervisor mode has
unrestricted access to the system and core resources.
length, and base registers (for circular buffering), and eight
additional 32-bit pointer registers (for C-style indexed stack
manipulation).
Blackfin processors support a modified Harvard architecture in
combination with a hierarchical memory structure. Level 1 (L1)
memories are those that typically operate at the full processor
speed with little or no latency. At the L1 level, the instruction
memory holds instructions only. The two data memories hold
data, and a dedicated scratchpad data memory stores stack and
local variable information.
The Blackfin processor instruction set has been optimized so
that 16-bit opcodes represent the most frequently used instructions, resulting in excellent compiled code density. Complex
DSP instructions are encoded into 32-bit opcodes, representing
fully featured multifunction instructions. Blackfin processors
support a limited multi-issue capability, where a 32-bit instruction can be issued in parallel with two 16-bit instructions,
allowing the programmer to use many of the core resources in a
single instruction cycle.
In addition, multiple L1 memory blocks are provided, offering a
configurable mix of SRAM and cache. The memory management unit (MMU) provides memory protection for individual
tasks that may be operating on the core and can protect system
registers from unintended access.
The Blackfin processor assembly language uses an algebraic syntax for ease of coding and readability. The architecture has been
optimized for use in conjunction with the C/C++ compiler,
resulting in fast and efficient software implementations.
ADDRESS ARITHMETIC UNIT
I3
L3
B3
M3
I2
L2
B2
M2
I1
L1
B1
M1
I0
L0
B0
M0
SP
FP
P5
DAG1
P4
P3
DAG0
P2
DA1 32
DA0 32
P1
TO MEMORY
P0
32
PREG
32
RAB
SD 32
LD1 32
LD0 32
ASTAT
32
32
R7.H
R6.H
R7.L
R6.L
R5.H
R5.L
R4.H
R4.L
R3.H
R3.L
R2.H
R2.L
R1.H
R1.L
R0.H
R0.L
SEQUENCER
ALIGN
16
16
8
8
8
8
DECODE
BARREL
SHIFTER
40
40
40
A0
32
40
A1
LOOP BUFFER
CONTROL
UNIT
32
DATA ARITHMETIC UNIT
Figure 2. Blackfin Processor Core
MEMORY ARCHITECTURE
The ADSP-BF542/4/7/8/9 processor views memory as a single
unified 4G byte address space, using 32-bit addresses. All
Rev. PrG
|
Page 5 of 82 |
resources, including internal memory, external memory, and
I/O control registers, occupy separate sections of this common
address space. The memory portions of this address space are
December 2007
ADSP-BF542/4/7/8/9
Preliminary Technical Data
arranged in a hierarchical structure to provide a good cost/performance balance of some very fast, low-latency on-chip
memory as cache or SRAM, and larger, lower-cost and performance off-chip memory systems. See Figure 3 on Page 6.
The on-chip L1 memory system is the highest-performance
memory available to the Blackfin processor. The off-chip memory system, accessed through the external bus interface unit
(EBIU), provides expansion with flash memory, SRAM, and
double-rate SDRAM (DDR1), optionally accessing up to
516M bytes of physical memory.
0 xFFFF FFFF
Most of the ADSP-BF542/4/7/8/9 processors also include an L2
SRAM memory array which provides up to 128K bytes of high
speed SRAM operating at one half the frequency of the core, and
slightly longer latency than the L1 memory banks (For information on L2 memory in each processor, see Table 1.) The L2
memory is a unified instruction and data memory and can hold
any mixture of code and data required by the system design.
The Blackfin cores share a dedicated low latency 64-bit wide
data path port into the L2 SRAM memory.
0 xFFA2 4000
CORE MMR REGISTERS (2M BYTE)
0xFFE0 0000
SYSTEM MMR REGISTERS (2M BYTE)
0 xFFC0 0000
RESERVED
0 xFFB0 1000
SCRATCHPAD SRAM (4K BYTE)
0 xFFB0 0000
RESERVED
L1 ROM (64K BYTE)
0 xFFA1 4000
RESERVED
0 xFFA0 C000
INSTRUCTION BANK B SRA M (16K BYTE)
0 xFFA0 8000
INSTRUCTION BANK A SRA M (32K BYTE)
0 xFFA0 0000
RESERVED
0 xFF90 8000
DATA BANK B SRAM / CACHE (16K BYTE)
0 xFF90 4000
DATA BANK B SRAM (16 K BYTE)
The memory DMA controllers (DMAC1 and DMAC0) provides high-bandwidth data-movement capability. They can
perform block transfers of code or data between the internal
memory and the external memory spaces.
INTERNAL MEMORY MAP
INSTRUCTION SRAM / CACHE (16K BYTE)
0 xFFA1 0000
0 xFF90 0000
RESERVED
0 xFF80 8000
DATA BANK A SRAM / CACHE (16K BYTE)
0 xFF80 4000
DATA BANK A SRAM (16 K BYTE)
0 xFF80 0000
RESERVED
0x FEB2 0000
L2 SRAM (128K BYTE)
0x FEB0 0000
RESERVED
0x EF00 1000
B OOT ROM (4K BYTE)
0x EF00 0000
ASYNC MEMORY BANK 3 (64M BYTE)
0x 2C00 0000
ASYNC MEMORY BANK 2 (64M BYTE)
0x 2800 0000
ASYNC MEMORY BANK 1 (64M BYTE)
0x 2400 0000
ASYNC MEMORY BANK 0 (64M BYTE)
0x 2000 0000
TOP OF LAST
DDR PAGE
RESERVED
DDR1 MEM BANK 1 (8M BYTE 256M BYTE)
EXTERNAL MEMORY MAP
RESERVED
0x 3000 0000
DDR1 MEM BANK 0 (8M BYTE 256M BYTE)
0x 0000 0000
Figure 3. ADSP-BF547BF548/BF549 Internal/External Memory Map1
1
This memory map applies to all ADSP-BF542/4/7/8/9 processors, except for L2
memory population. ADSP-BF544 includes 64K Byte of L2 memory: 0xFEB0
0000 - 0xFEB0 FFFF. ADSP-BF542 includes no L2 memory. See also Table 1.
Internal (On-Chip) Memory
The ADSP-BF542/4/7/8/9 processor has several blocks of onchip memory providing high-bandwidth access to the core.
The first block is the L1 instruction memory, consisting of
48K bytes SRAM, and also 16K bytes that can be configured as a
four-way set-associative cache or SRAM. This memory is
accessed at full processor speed.
The second on-chip memory block is the L1 data memory, consisting of 64K bytes SRAM, of which 32K bytes can be
configured as a two-way set associative cache. This memory
block is accessed at full processor speed.
Rev. PrG
|
Page 6 of 82 |
December 2007
ADSP-BF542/4/7/8/9
Preliminary Technical Data
The third memory block is a 4K byte scratchpad SRAM which
runs at the same speed as the L1 memories, but is only accessible
as data SRAM and cannot be configured as cache memory.
The fourth memory block is the factory programmed L1
instruction ROM, operating at full processor speed. This ROM
is not customer configurable.
The fifth memory block is the L2 SRAM, providing 128K bytes
of unified instruction and data memory, operating at one half
the frequency of the core.
Finally, there is a 4K boot ROM connected as L3 memory. It
operates at full SCLK rate.
Through the External Bus Interface Unit (EBIU) the
ADSP-BF542/4/7/8/9 processors provide glueless connectivity
to external 16-bit wide memories, such as DDR SDRAM,
Mobile DDR, SRAM, NOR flash, NAND flash, and FIFO
devices. To provide the best performance, the bus system of the
DDR interface is completely separate from the other parallel
interfaces.
The DDR/Mobile DDR memory controller can gluelessly manage up to two banks of double-rate synchronous dynamic
memory (DDR1 SDRAM). The 16-bit wide interface operates at
SCLK frequency, enabling maximum throughput of 532
Mbyte/s. The DDR controller is augmented with a queuing
mechanism that performs efficient bursts into the DDR. The
controller is an industry standard DDR1 SDRAM controller
with each bank supporting from 64 Mbit to 512 Mbit device
sizes and 4-, 8-, or 16-bit widths. The controller supports up to
256 Mbytes per external bank. With 2 external banks, the controller supports up to 512 Mbytes total. Each bank is
independently programmable and is contiguous with adjacent
banks regardless of the sizes of the different banks or their
placement.
Traditional 16-bit asynchronous memories, such as SRAM,
EPROM, and flash devices, can be connected to one of the four
64 MByte asynchronous memory banks, represented by four
memory select strobes. Alternatively, these strobes can function
as bank-specific read or write strobes preventing further glue
logic when connecting to asynchronous FIFO devices.
In addition, the external bus can connect to advanced flash
device technologies, such as:
• Page-mode NOR flash devices
• Synchronous burst-mode NOR flash devices
• NAND flash devices
NAND Flash Controller (NFC)
The ADSP-BF542/4/7/8/9 provides a NAND Flash Controller
(NFC) as part of the external bus interface. NAND flash devices
provide high-density, low-cost memory. However, NAND flash
devices also have long random access times, invalid blocks, and
lower reliability over device lifetimes. Because of this, NAND
flash is often used for read-only code storage. In this case, all
DSP code can be stored in NAND flash and then transferred to a
faster memory (such as DDR or SRAM) before execution.
|
• Support for page program, page read, and block erase of
NAND flash devices, with accesses aligned to page
boundaries.
• Error checking and correction (ECC) hardware that facilitates error detection and correction.
External (Off-Chip) Memory
Rev. PrG
Another common use of NAND flash is for storage of multimedia files or other large data segments. In this case, a software file
system may be used to manage reading and writing of the
NAND flash device. The file system selects memory segments
for storage with the goal of avoiding bad blocks and equally distributing memory accesses across all address locations.
Hardware features of the NFC include:
Page 7 of 82 |
• A single 8-bit or 16-bit external bus interface for commands, addresses and data.
• Support for SLC (single level cell) NAND flash devices
unlimited in size, with page sizes of 256 and 512 bytes.
Larger page sizes can be supported in software.
• Capability of releasing external bus interface pins during
long accesses.
• Support for internal bus requests of 16 or 32 bits.
• DMA engine to transfer data between internal memory and
NAND flash device.
One-time-Programmable Memory
The ADSP-BF542/4/7/8/9 has 64K bits of one-time programmable (OTP) non-volatile memory that can be programmed by
the developer only one time. It includes the array and logic to
support read access and programming. Additionally, its pages
can be write protected.
OTP enables developers to store both public and private data
on-chip. In addition to storing public and private key data for
applications requiring security, it also allows developers to store
completely user-definable data such as customer ID, product
ID, MAC address, etc. Hence generic parts can be shipped
which are then programmed and protected by the developer
within this non-volatile memory.
I/O Memory Space
The ADSP-BF542/4/7/8/9 processors do not define a separate
I/O space. All resources are mapped through the flat 32-bit
address space. On-chip I/O devices have their control registers
mapped into memory-mapped registers (MMRs) at addresses
near the top of the 4G byte address space. These are separated
into two smaller blocks, one which contains the control MMRs
for all core functions, and the other which contains the registers
needed for setup and control of the on-chip peripherals outside
of the core. The MMRs are accessible only in supervisor mode
and appear as reserved space to on-chip peripherals.
Booting
The ADSP-BF542/4/7/8/9 processor contains a small on-chip
boot kernel, which configures the appropriate peripheral for
booting. If the ADSP-BF542/4/7/8/9 processor is configured to
December 2007
ADSP-BF542/4/7/8/9
Preliminary Technical Data
boot from boot ROM memory space, the processor starts executing from the on-chip boot ROM. For more information, see
Booting Modes on Page 19.
Event Handling
The event controller on the ADSP-BF542/4/7/8/9 processor
handles all asynchronous and synchronous events to the processor. The ADSP-BF542/4/7/8/9 processor provides event
handling that supports both nesting and prioritization. Nesting
allows multiple event service routines to be active simultaneously. Prioritization ensures that servicing of a higherpriority event takes precedence over servicing of a lower-priority event. The controller provides support for five different types
of events:
• Emulation. An emulation event causes the processor to
enter emulation mode, allowing command and control of
the processor via the JTAG interface.
• Reset. This event resets the processor.
• Non-Maskable Interrupt (NMI). The NMI event can be
generated by the software watchdog timer or by the NMI
input signal to the processor. The NMI event is frequently
used as a power-down indicator to initiate an orderly shutdown of the system.
• Exceptions. Events that occur synchronously to program
flow (that is, the exception is taken before the instruction is
allowed to complete). Conditions such as data alignment
violations and undefined instructions cause exceptions.
• Interrupts. Events that occur asynchronously to program
flow. They are caused by input pins, timers, and other
peripherals, as well as by an explicit software instruction.
Each event type has an associated register to hold the return
address and an associated return-from-event instruction. When
an event is triggered, the state of the processor is saved on the
supervisor stack.
Table 3. Core Event Controller (CEC)
Priority
(0 is Highest)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Event Class
EVT Entry
Emulation/Test Control
Reset
Non-Maskable Interrupt
Exception
Reserved
Hardware Error
Core Timer
General Interrupt 7
General Interrupt 8
General Interrupt 9
General Interrupt 10
General Interrupt 11
General Interrupt 12
General Interrupt 13
General Interrupt 14
General Interrupt 15
EMU
RST
NMI
EVX
—
IVHW
IVTMR
IVG7
IVG8
IVG9
IVG10
IVG11
IVG12
IVG13
IVG14
IVG15
Although the ADSP-BF542/4/7/8/9 processor provides a default
mapping, the user can alter the mappings and priorities of
interrupt events by writing the appropriate values into the interrupt assignment registers (IAR). Table 4 describes the inputs
into the SIC and the default mappings into the CEC.
Table 4. System Interrupt Controller (SIC)
Peripheral IRQ
(IRQ) Source
IRQ
GP IRQ
ID (at Reset)
Core
IRQ ID
PLL Wakeup IRQ
0
IVG7
0
DMAC0 Status (generic)
1
IVG7
0
The ADSP-BF542/4/7/8/9 processor event controller consists of
two stages, the core event controller (CEC) and the system
interrupt controller (SIC). The core event controller works with
the system interrupt controller to prioritize and control all system events. Conceptually, interrupts from the peripherals enter
into the SIC, and are then routed directly into the general-purpose interrupts of the CEC.
EPPI0 Error IRQ
2
IVG7
0
SPORT0 Error IRQ
3
IVG7
0
SPORT1 Error IRQ
4
IVG7
0
SPI0 Status IRQ
5
IVG7
0
UART0 Status IRQ
6
IVG7
0
Core Event Controller (CEC)
Real-Time Clock IRQ
7
IVG8
1
DMA12 IRQ (EPPI0)
8
IVG8
1
The CEC supports nine general-purpose interrupts (IVG15–7),
in addition to the dedicated interrupt and exception events. Of
these general-purpose interrupts, the two lowest-priority interrupts (IVG15–14) are recommended to be reserved for software
interrupt handlers, leaving seven prioritized interrupt inputs to
support the peripherals of the ADSP-BF542/4/7/8/9 processor.
Table 3 describes the inputs to the CEC, identifies their names
in the event vector table (EVT), and lists their priorities.
System Interrupt Controller (SIC)
The system interrupt controller provides the mapping and routing of events from the many peripheral interrupt sources to the
prioritized general-purpose interrupt inputs of the CEC.
Rev. PrG
|
Page 8 of 82 |
DMA0 IRQ (SPORT0 RX)
9
IVG9
2
DMA1 IRQ (SPORT0 TX)
10
IVG9
2
DMA2 IRQ (SPORT1 RX)
11
IVG9
2
DMA3 IRQ (SPORT1 TX)
12
IVG9
2
DMA4 IRQ (SPI0)
13
IVG10
3
DMA6 IRQ (UART0 RX)
14
IVG10
3
DMA7 IRQ (UART0 TX)
15
IVG10
3
Timer 8 IRQ
16
IVG11
4
Timer 9 IRQ
17
IVG11
4
December 2007
ADSP-BF542/4/7/8/9
Preliminary Technical Data
Table 4. System Interrupt Controller (SIC) (Continued)
Peripheral IRQ
(IRQ) Source
IRQ
GP IRQ
ID (at Reset)
Timer 10 IRQ
18
Pin IRQ 0 (PINT0)
Pin IRQ 1 (PINT1)
Table 4. System Interrupt Controller (SIC) (Continued)
Core
IRQ ID
Peripheral IRQ
(IRQ) Source
IRQ
GP IRQ
ID (at Reset)
Core
IRQ ID
IVG11
4
Host DMA Status
57
IVG7
0
19
IVG12
5
Reserved
58
IVG7
0
20
IVG12
5
Pixel Compositor (PIXC) Status IRQ
59
IVG7
0
MDMA Stream 0 IRQ
21
IVG13
6
NFC Status IRQ
60
IVG7
0
MDMA Stream 1 IRQ
22
IVG13
6
ATAPI Status IRQ
61
IVG7
0
Software Watchdog Timer IRQ
23
IVG13
6
CAN1 Status IRQ
62
IVG7
0
DMAC1 Status (generic)
24
IVG7
0
DMAR0 Block IRQ
63
IVG7
0
SPORT2 Error IRQ
25
IVG7
0
DMAR1 Block IRQ
63
IVG7
0
SPORT3 Error IRQ
26
IVG7
0
DMAR0 Overflow Error IRQ
63
IVG7
0
MXVR Synchronous Data IRQ
27
IVG7
0
DMAR1 Overflow Error IRQ
63
IVG7
0
SPI1 Status IRQ
28
IVG7
0
DMA15 IRQ (PIXC IN0)
64
IVG8
1
SPI2 Status IRQ
29
IVG7
0
DMA16 IRQ (PIXC IN1)
65
IVG8
1
UART1 Status IRQ
30
IVG7
0
DMA17 IRQ (PIXC OUT)
66
IVG8
1
UART2 Status IRQ
31
IVG7
0
DMA22 IRQ (SDH/NFC)
67
IVG8
1
CAN0 Status IRQ
32
IVG7
0
Counter (CNT) IRQ
68
IVG8
1
DMA18 IRQ (SPORT2 RX)
33
IVG9
2
Keypad (KEY) IRQ
69
IVG8
1
DMA19 IRQ (SPORT2 TX)
34
IVG9
2
CAN1 RX IRQ
70
IVG11
4
DMA20 IRQ (SPORT3 RX)
35
IVG9
2
CAN1 TX IRQ
71
IVG11
4
DMA21 IRQ (SPORT3 TX)
36
IVG9
2
SDH Mask 0 IRQ
72
IVG11
4
DMA13 IRQ (EPPI1)
37
IVG9
2
SDH Mask 1 IRQ
73
IVG11
4
DMA14 IRQ (EPPI2, Host DMA)
38
IVG9
2
Reserved
74
IVG11
4
DMA5 IRQ (SPI1)
39
IVG10
3
USB_INT0 IRQ
75
IVG11
4
DMA23 IRQ (SPI2)
40
IVG10
3
USB_INT1 IRQ
76
IVG11
4
DMA8 IRQ (UART1 RX)
41
IVG10
3
USB_INT2 IRQ
77
IVG11
4
DMA9 IRQ (UART1 TX)
42
IVG10
3
USB_DMAINT IRQ
78
IVG11
4
DMA10 IRQ (ATAPI RX)
43
IVG10
3
OTPSEC IRQ
79
IVG11
4
DMA11 IRQ (ATAPI TX)
44
IVG10
3
Reserved
80
IVG11
4
TWI0 IRQ
45
IVG11
4
Reserved
81
IVG11
4
TWI1 IRQ
46
IVG11
4
Reserved
82
IVG11
4
CAN0 Receive IRQ
47
IVG11
4
Reserved
83
IVG11
4
CAN0 Transmit IRQ
48
IVG11
4
Reserved
84
IVG11
4
MDMA Stream 2 IRQ
49
IVG13
6
Reserved
85
IVG11
4
MDMA Stream 3 IRQ
50
IVG13
6
Timer 0 IRQ
86
IVG11
4
MXVR Status IRQ
51
IVG11
4
Timer 1 IRQ
87
IVG11
4
MXVR Control Message IRQ
52
IVG11
4
Timer 2 IRQ
88
IVG11
4
MXVR Asynchronous Packet IRQ
53
IVG11
4
Timer 3 IRQ
89
IVG11
4
EPPI1 Error IRQ
54
IVG7
0
Timer 4 IRQ
90
IVG11
4
EPPI2 Error IRQ
55
IVG7
0
Timer 5 IRQ
91
IVG11
4
UART3 Status IRQ
56
IVG7
0
Timer 6 IRQ
92
IVG11
4
Rev. PrG
|
Page 9 of 82 |
December 2007
ADSP-BF542/4/7/8/9
Preliminary Technical Data
triggered the interrupt. A set bit indicates the peripheral is
asserting the interrupt, and a cleared bit indicates the
peripheral is not asserting the event.
Table 4. System Interrupt Controller (SIC) (Continued)
Peripheral IRQ
(IRQ) Source
IRQ
GP IRQ
ID (at Reset)
Core
IRQ ID
Timer 7 IRQ
93
IVG11
4
Pin IRQ 2 (PINT2)
94
IVG12
5
Pin IRQ 3 (PINT3)
95
IVG12
5
Event Control
The ADSP-BF542/4/7/8/9 processor provides the user with a
very flexible mechanism to control the processing of events. In
the CEC, three registers are used to coordinate and control
events. Each register is 16 bits wide:
• CEC interrupt latch register (ILAT). The ILAT register
indicates when events have been latched. The appropriate
bit is set when the processor has latched the event and
cleared when the event has been accepted into the system.
This register is updated automatically by the controller, but
it may be written only when its corresponding IMASK bit
is cleared.
• CEC interrupt mask register (IMASK). The IMASK register controls the masking and unmasking of individual
events. When a bit is set in the IMASK register, that event is
unmasked and is processed by the CEC when asserted. A
cleared bit in the IMASK register masks the event, preventing the processor from servicing the event even though the
event may be latched in the ILAT register. This register
may be read or written while in supervisor mode. (Note
that general-purpose interrupts can be globally enabled and
disabled with the STI and CLI instructions, respectively.)
• CEC interrupt pending register (IPEND). The IPEND register keeps track of all nested events. A set bit in the IPEND
register indicates the event is currently active or nested at
some level. This register is updated automatically by the
controller but may be read while in supervisor mode.
The SIC allows further control of event processing by providing
three 32-bit interrupt control and status registers. Each register
contains a bit corresponding to each of the peripheral interrupt
events shown in Table 4 on Page 8.
• SIC interrupt mask register (SIC_IMASK). This register
controls the masking and unmasking of each peripheral
interrupt event. When a bit is set in the register, that
peripheral event is unmasked and is processed by the system when asserted. A cleared bit in the register masks the
peripheral event, preventing the processor from servicing
the event.
• SIC interrupt status register (SIC_ISR). As multiple peripherals can be mapped to a single event, this register allows
the software to determine which peripheral event source
Rev. PrG
|
• SIC interrupt wakeup enable register (SIC_IWR). By
enabling the corresponding bit in this register, a peripheral
can be configured to wake up the processor, should the
core be idled when the event is generated. (For more information, see Dynamic Power Management on Page 16.)
Because multiple interrupt sources can map to a single generalpurpose interrupt, multiple pulse assertions can occur simultaneously, before or during interrupt processing for an interrupt
event already detected on this interrupt input. The IPEND register contents are monitored by the SIC as the interrupt
acknowledgement.
The appropriate ILAT register bit is set when an interrupt rising
edge is detected (detection requires two core clock cycles). The
bit is cleared when the respective IPEND register bit is set. The
IPEND bit indicates that the event has entered into the processor pipeline. At this point the CEC recognizes and queues the
next rising edge event on the corresponding event input. The
minimum latency from the rising edge transition of the generalpurpose interrupt to the IPEND output asserted is three core
clock cycles; however, the latency can be much higher, depending on the activity within and the state of the processor.
DMA CONTROLLERS
ADSP-BF542/4/7/8/9 processors have multiple, independent
DMA channels that support automated data transfers with minimal overhead for the processor core. DMA transfers can occur
between the ADSP-BF542/4/7/8/9 processor’s internal memories and any of its DMA-capable peripherals. Additionally,
DMA transfers can be accomplished between any of the DMAcapable peripherals and external devices connected to the external memory interfaces, including DDR and asynchronous
memory controllers.
While the USB controller and MXVR have their own dedicated
DMA controllers, the other on-chip peripherals are managed by
two centralized DMA controllers, called DMAC1 (32-bit) and
DMAC0 (16-bit). Both operate in the SCLK domain. Each DMA
controller manages twelve independent peripheral DMA channels, as well as 2 independent memory DMA streams. The
DMAC1 controller masters high-bandwidth peripherals over a
dedicated 32-bit DMA access bus (DAB32). Similarly, the
DMAC0 controller masters most of serial interfaces over the 16bit DAB16 bus. Individual DMA channels have fixed access priority on the DAB buses. DMA priority of peripherals is
managed by flexible peripheral-to-DMA channel assignment.
All four DMA controllers use the same 32-bit DCB bus to
exchange data with L1 memory. This includes L1 ROM, but
excludes scratchpad memory. Fine granulation of L1 memory
and special DMA buffers minimize potential memory conflicts,
if the L1 memory is accessed by the core contemporaneously.
Similarly, there are dedicated DMA buses between the DMAC1,
DMAC0, and USB DMA controllers and the external bus interface unit (EBIU) that arbitrates DMA accesses to external
memories and boot ROM.
Page 10 of 82 |
December 2007
ADSP-BF542/4/7/8/9
Preliminary Technical Data
The ADSP-BF542/4/7/8/9 processor DMA controllers support
both 1-dimensional (1D) and 2-dimensional (2D) DMA transfers. DMA transfer initialization can be implemented from
registers or from sets of parameters called descriptor blocks.
configuration words in order to send/receive data to any valid
internal or external memory location. The Host DMA Port controller includes the following features:
• Allows an external master to configure DMA read/write
data transfers and read port status
The 2D DMA capability supports arbitrary row and column
sizes up to 64K elements by 64K elements, and arbitrary row
and column step sizes up to ±32K elements. Furthermore, the
column step size can be less than the row step size, allowing
implementation of interleaved data streams. This feature is
especially useful in video applications where data can be deinterleaved on the fly.
• Uses a flexible asynchronous memory protocol for its
external interface
• Allows an 8- or 16-bit external data interface to the host
device
• Supports half-duplex operation
Examples of DMA types supported by the ADSP-BF542/4/7/8/9
processor DMA controller include:
• Supports Little/Big Endian data transfers
• A single, linear buffer that stops upon completion
• Acknowledge mode allows flow control on host
transactions
• A circular, auto-refreshing buffer that interrupts on each
full or fractionally full buffer
• Interrupt mode guarantees a burst of FIFO depth host
transactions
• 1-D or 2-D DMA using a linked list of descriptors
REAL-TIME CLOCK
• 2-D DMA using an array of descriptors, specifying only the
base DMA address within a common page
In addition to the dedicated peripheral DMA channels, both the
DMAC1 and the DMAC0 controllers feature two memory
DMA channel pairs for transfers between the various memories
of the ADSP-BF542/4/7/8/9 processor system. This enables
transfers of blocks of data between any of the memories—
including external DDR, ROM, SRAM, and flash memory—
with minimal processor intervention. Like peripheral DMAs,
memory DMA transfers can be controlled by a very flexible
descriptor-based methodology or by a standard register-based
autobuffer mechanism.
The memory DMA channels of the DMAC1 controller
(MDMA2 and MDMA3) can be optionally controlled by the
external DMA request input pins. When used in conjunction
with the External Bus Interface Unit (EBIU), this so-called
Handshaked Memory DMA (HMDMA) scheme can be used to
efficiently exchange data with block-buffered or FIFO-style
devices connected externally. Users can select whether the DMA
request pins control the source or the destination side of the
memory DMA. It allows control of the number of data transfers
for memory DMA. The number of transfers per edge is programmable. This feature can be programmed to allow memory
DMA to have an increased priority on the external bus relative
to the core.
Host DMA Port Interface
The Host DMA port (HOSTDP) facilitates a host device external to the ADSP-BF542/4/7/8/9 to be a DMA master and
transfer data back and forth. The host device always masters the
transactions and the processor is always a DMA slave device.
The ADSP-BF542/4/7/8/9 processor Real-Time Clock (RTC)
provides a robust set of digital watch features, including current
time, stopwatch, and alarm. The RTC is clocked by a
32.768 KHz crystal external to the ADSP-BF542/4/7/8/9 processors. The RTC peripheral has dedicated power supply pins so
that it can remain powered up and clocked even when the rest of
the processor is in a low-power state. The RTC provides several
programmable interrupt options, including interrupt per second, minute, hour, or day clock ticks, interrupt on
programmable stopwatch countdown, or interrupt at a programmed alarm time.
The 32.768 KHz input clock frequency is divided down to a
1 Hz signal by a prescaler. The counter function of the timer
consists of four counters: a 60-second counter, a 60-minute
counter, a 24-hour counter, and an 32,768-day counter.
When enabled, the alarm function generates an interrupt when
the output of the timer matches the programmed value in the
alarm control register. There are two alarms: The first alarm is
for a time of day. The second alarm is for a day and time of that
day.
The stopwatch function counts down from a programmed
value, with one-second resolution. When the stopwatch is
enabled and the counter underflows, an interrupt is generated.
Like the other peripherals, the RTC can wake up the
ADSP-BF542/4/7/8/9 processor from sleep mode upon generation of any RTC wakeup event. Additionally, an RTC wakeup
event can wake up the ADSP-BF542/4/7/8/9 processor from
deep sleep mode, and wake up the on-chip internal voltage regulator from the hibernate operating mode.
The HOSTDP port is enabled through the peripheral access bus.
Once the port has been enabled, the transaction are controlled
by the external host. The external host programs standard DMA
Rev. PrG
|
Page 11 of 82 |
December 2007
ADSP-BF542/4/7/8/9
Preliminary Technical Data
Connect RTC pins RTXI and RTXO with external components
as shown in Figure 4.
RTXI
The timers can generate interrupts to the processor core providing periodic events for synchronization, either to the system
clock or to a count of external signals.
RTXO
R1
In addition to the general-purpose programmable timers,
another timer is also provided by the processor core. This extra
timer is clocked by the internal processor clock and is typically
used as a system tick clock for generation of operating system
periodic interrupts.
X1
C1
The timer units can be used in conjunction with the two UARTs
and the CAN controller to measure the width of the pulses in
the data stream to provide a software auto-baud detect function
for the respective serial channels.
C2
UP/DOWN COUNTER AND THUMBWHEEL
INTERFACE
SUGGESTED COMPONENTS:
ECLIPTEK EC38J (THROUGH-HOLE PACKAGE)
EPSON MC405 12 PF LOAD (SURFACE MOUNT PACKAGE)
C1 = 22 PF
C2 = 22 PF
R1 = 10 M:
A 32-bit up/down counter is provided that can sense 2-bit
quadrature or binary codes as typically emitted by industrial
drives or manual thumb wheels. The counter can also operate in
general-purpose up/down count modes. Then, count direction
is either controlled by a level-sensitive input pin or by two edge
detectors.
NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.
CONTACT CRYSTAL MANUFACTURER FOR DETAILS. C1 AND C2
SPECIFICATIONS ASSUME BOARD TRACE CAPACITANCE OF 3 PF.
Figure 4. External Components for RTC
WATCHDOG TIMER
The ADSP-BF542/4/7/8/9 processor includes a 32-bit timer that
can be used to implement a software watchdog function. A software watchdog can improve system availability by forcing the
processor to a known state through generation of a hardware
reset, non-maskable interrupt (NMI), or general-purpose interrupt, if the timer expires before being reset by software. The
programmer initializes the count value of the timer, enables the
appropriate interrupt, then enables the timer. Thereafter, the
software must reload the counter before it counts to zero from
the programmed value. This protects the system from remaining in an unknown state where software, which would normally
reset the timer, has stopped running due to an external noise
condition or software error.
A third input can provide flexible zero marker support and can
alternatively be used to input the push-button signal of thumb
wheels. All three pins have a programmable debouncing circuit.
An internal signal forwarded to the timer unit enables one timer
to measure the intervals between count events. Boundary registers enable auto-zero operation or simple system warning by
interrupts when programmable count values are exceeded.
SERIAL PORTS (SPORTS)
The ADSP-BF542/4/7/8/9 processor incorporates up to four
dual-channel synchronous serial ports (SPORT0, SPORT1,
SPORT2, SPORT3) for serial and multiprocessor communications. The SPORTs support the following features:
If configured to generate a hardware reset, the watchdog timer
resets both the core and the ADSP-BF542/4/7/8/9 processor
peripherals. After a reset, software can determine if the watchdog was the source of the hardware reset by interrogating a
status bit in the watchdog timer control register.
The timer is clocked by the system clock (SCLK), at a maximum
frequency of fSCLK.
TIMERS
There are up to two timer units in the ADSP-BF542/4/7/8/9
processors. One unit provides eight general-purpose programmable timers and the other unit provides three. Each timer has
an external pin that can be configured either as a Pulse Width
Modulator (PWM) or timer output, as an input to clock the
timer, or as a mechanism for measuring pulse widths and periods of external events. These timers can be synchronized to an
external clock input on the TMRx pins, an external clock
TMRCLK input pin, or to the internal SCLK.
Rev. PrG
|
Page 12 of 82 |
• I2S capable operation.
• Bidirectional operation. Each SPORT has two sets of independent transmit and receive pins, enabling eight channels
of I2S stereo audio.
• Buffered (8-deep) transmit and receive ports. Each port has
a data register for transferring data words to and from
other processor components and shift registers for shifting
data in and out of the data registers.
• Clocking. Each transmit and receive port can either use an
external serial clock or generate its own, in frequencies
ranging from (fSCLK/131,070) Hz to (fSCLK/2) Hz.
• Word length. Each SPORT supports serial data words from
3 to 32 bits in length, transferred most-significant-bit first
or least-significant-bit first.
• Framing. Each transmit and receive port can run with or
without frame sync signals for each data word. Frame sync
signals can be generated internally or externally, active high
or low, and with either of two pulsewidths and early or late
frame sync.
December 2007
ADSP-BF542/4/7/8/9
Preliminary Technical Data
• Companding in hardware. Each SPORT can perform
A-law or μ-law companding according to ITU recommendation G.711. Companding can be selected on the transmit
and/or receive channel of the SPORT without additional
latencies.
includes support for 5 to 8 data bits, 1 or 2 stop bits, and none,
even, or odd parity. Each UART port supports two modes of
operation:
• PIO (programmed I/O). The processor sends or receives
data by writing or reading I/O-mapped UART registers.
The data is double-buffered on both transmit and receive.
• DMA operations with single-cycle overhead. Each SPORT
can automatically receive and transmit multiple buffers of
memory data. The processor can link or chain sequences of
DMA transfers between a SPORT and memory.
• DMA (Direct Memory Access). The DMA controller transfers both transmit and receive data. This reduces the
number and frequency of interrupts required to transfer
data to and from memory. Each UART has two dedicated
DMA channels, one for transmit and one for receive. These
DMA channels have lower default priority than most DMA
channels because of their relatively low service rates. Flexible interrupt timing options are available on the transmit
side.
• Interrupts. Each transmit and receive port generates an
interrupt upon completing the transfer of a data word or
after transferring an entire data buffer or buffers through
DMA.
• Multichannel capability. Each SPORT supports 128 channels out of a 1024-channel window and is compatible with
the H.100, H.110, MVIP-90, and HMVIP standards.
SERIAL PERIPHERAL INTERFACE (SPI) PORTS
Each UART port's baud rate, serial data format, error code generation and status, and interrupts are programmable:
• Supporting bit rates ranging from (fSCLK/ 1,048,576) to
(fSCLK) bits per second.
The ADSP-BF542/4/7/8/9 processor has up to three SPI-compatible ports that allow the processor to communicate with
multiple SPI-compatible devices.
Each SPI port uses three pins for transferring data: two data pins
(master output-slave input, MOSI, and master input-slave output, MISO) and a clock pin (serial clock, SCK). An SPI chip
select input pin (SPISS) lets other SPI devices select the processor, and three SPI chip select output pins per SPI port let the
processor select other SPI devices. The SPI select pins are reconfigured programmable flag pins. Using these pins, the SPI ports
provide a full-duplex, synchronous serial interface, which supports both master/slave modes and multimaster environments.
The SPI port’s baud rate and clock phase/polarities are programmable, and it has an integrated DMA controller,
configurable to support transmit or receive data streams. The
SPI’s DMA controller can only service unidirectional accesses at
any given time.
The SPI port’s clock rate is calculated as:
f SCLK
SPI Clock Rate = -------------------------------2 × SPI_Baud
Where the 16-bit SPI_BAUD register contains a value of 2 to
65,535.
During transfers, the SPI port simultaneously transmits and
receives by serially shifting data in and out on its two serial data
lines. The serial clock line synchronizes the shifting and sampling of data on the two serial data lines.
UART PORTS (UARTS)
The ADSP-BF542/4/7/8/9 processor provides up to four fullduplex Universal Asynchronous Receiver/Transmitter (UART)
ports. Each UART port provides a simplified UART interface to
other peripherals or hosts, supporting full-duplex, DMA-supported, asynchronous transfers of serial data. A UART port
Rev. PrG
|
• Supporting data formats from 7 to 12 bits per frame.
• Both transmit and receive operations can be configured to
generate maskable interrupts to the processor.
The UART port’s clock rate is calculated as:
f SCLK
UART Clock Rate = -----------------------------------------------------------------------------( 1 – EDBO )
16
× UART_Divisor
Where the 16-bit UART Divisor comes from the UARTx_DLH
register (most significant 8 bits) and UARTx_DLL register (least
significant 8 bits, and EDBO is a bit in the UARTx_GCTL
register).
In conjunction with the general-purpose timer functions, autobaud detection is supported.
UART1 and UART3 feature a pair of RTS (request to send) and
CTS (clear to send) signals for hardware flow purposes. The
transmitter hardware is automatically prevented from sending
further data when the CTS input is de-asserted. The receiver can
automatically de-assert its RTS output when the enhanced
receive FIFO exceeds a certain high-water level. The capabilities
of the UARTs are further extended with support for the Infrared
Data Association (IrDA®) Serial Infrared Physical Layer Link
Specification (SIR) protocol.
CONTROLLER AREA NETWORK (CAN)
The ADSP-BF542/4/9 processor offers up to two CAN controllers that are communication controllers that implement the
Controller Area Network (CAN) 2.0B (active) protocol. This
protocol is an asynchronous communications protocol used in
both industrial and automotive control systems. The CAN protocol is well suited for control applications due to its capability
to communicate reliably over a network since the protocol
incorporates CRC checking message error tracking, and fault
node confinement. CAN controllers are only available on the
Automotive Grade versions for ADSP-BF542 and ADSP-BF544
processors. CAN is always available on the Industrial Grade ver-
Page 13 of 82 |
December 2007
ADSP-BF542/4/7/8/9
Preliminary Technical Data
sion of the ADSP-BF548 processor and the Automotive Grade
version of the ADSP-BF549 processor since those only have one
version each offered.
functions, the richness of GPIO functionality guarantees unrestrictive pin usage. Every pin that is not used by any function
can be configured in GPIO mode on an individual basis.
The ADSP-BF542/4/9 CAN controllers offer the following
features:
After reset, all pins are in GPIO mode by default. Neither GPIO
output nor input drivers are active by default. Unused pins can
be left unconnected, therefore. GPIO data and direction control
registers provide flexible write-one-to-set and write-one-toclear mechanisms so that independent software threads do not
need to protect against each other because of expensive readmodify-write operations when accessing the same port.
• 32 mailboxes (8 receive only, 8 transmit only, 16 configurable for receive or transmit).
• Dedicated acceptance masks for each mailbox.
• Additional data filtering on first two bytes.
• Support for both the standard (11-bit) and extended (29bit) identifier (ID) message formats.
• Support for remote frames.
• Active or passive network support.
• CAN wakeup from hibernation mode (lowest static power
consumption mode).
• Interrupts, including: TX complete, RX complete, error,
global.
The electrical characteristics of each network connection are
very demanding so the CAN interface is typically divided into
two parts: a controller and a transceiver. This allows a single
controller to support different drivers and CAN networks. The
ADSP-BF542/4/9 CAN module represents only the controller
part of the interface. The controller interface supports connection to 3.3V high-speed, fault-tolerant, single-wire transceivers.
TWI CONTROLLER INTERFACE
The ADSP-BF542/4/7/8/9 processor includes up to two Two
Wire Interface (TWI) modules for providing a simple exchange
method of control data between multiple devices. The modules
are compatible with the widely used I2C bus standard. The TWI
modules offer the capabilities of simultaneous Master and Slave
operation, support for both 7-bit addressing and multimedia
data arbitration. Each TWI interface uses two pins for transferring clock (SCL) and data (SDA) and supports the protocol at
speeds up to 400k bits/sec. The TWI interface pins are compatible with 5 V logic levels.
Additionally, the ADSP-BF542/4/7/8/9 processor’s TWI modules are fully compatible with Serial Camera Control Bus
(SCCB) functionality for easier control of various CMOS camera sensor devices.
PORTS
Because of their rich set of peripherals, the
ADSP-BF542/4/7/8/9 processors group the many peripheral
signals to ten ports—referred to as Port A to Port J. Most ports
contain 16 pins, a few have less. Many of the associated pins are
shared by multiple signals. The ports function as multiplexer
controls. Every port has its own set of memory-mapped registers to control port muxing and GPIO functionality.
General-Purpose I/O (GPIO)
Pin Interrupts
Due to its large number of port pins, the ADSP-BF542/4/7/8/9
processors introduce a new scheme to manage pin interrupts.
Every port pin can request interrupts in either an edge-sensitive
or a level-sensitive manner with programmable polarity. Interrupt functionality is decoupled from GPIO operation. Four
system-level interrupt channels (INT0, INT1, INT2 and INT3)
are reserved for this purpose. Each of these interrupt channels
can manage up to 32 interrupt pins. The assignment from pin to
interrupt is not performed at a pin by pin level. Rather, groups
of eight pins (half ports) can be flexibly assigned to interrupt
channels.
Every pin interrupt channel features a special set of 32-bit memory-mapped registers that enable half-port assignment and
interrupt management. This not only includes masking, identification, and clearing of requests, it also enables access to the
respective pin states and use of the interrupt latches regardless
of whether the interrupt is masked or not. Most control registers
feature multiple MMR address entries to write-one-to-set or
write-one-to-clear them individually.
PIXEL COMPOSITOR (PIXC)
The pixel compositor (PIXC) provides image overlay with
transparent-color support, alpha blending, and color space conversion capability for output to TFT-LCDs as well as
NTSC/PAL video encoders. It provides all of the control to
allow two data streams from two separate data buffers to be
combined, blended, and converted into appropriate forms for
both LCD panels and digital video outputs. The main image
buffer provides the basic background image, which is presented
in the data stream. The overlay image buffer allows the user to
add multiple foreground text, graphics, or video objects on top
of the main image or video data stream.
ENHANCED PARALLEL PERIPHERAL INTERFACE
(EPPI)
The ADSP-BF542/4/7/8/9 processor provides up to three
Enhanced Parallel Peripheral Interfaces (EPPIs), supporting
data widths up to 24 bits wide. The EPPI supports direct connection to TFT LCD panels, parallel A/D and D/A converters,
video encoders and decoders, image sensor modules and other
general purpose peripherals.
Every pin in Port A to Port J can function as a GPIO pin resulting in a GPIO pin count of 154. While it is unlikely that all
GPIOs will be used in an application as all pins have multiple
Rev. PrG
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December 2007
ADSP-BF542/4/7/8/9
Preliminary Technical Data
ATA/ATAPI–6 INTERFACE
The following features are supported in the EPPI module.
• Programmable data length: 8, 10, 12, 14, 16, 18, and 24 bits
per clock.
• Bi-directional and half-duplex port.
• Clock can be provided externally or can be generated
internally.
• Various framed and non-framed operating modes. Frame
syncs can be generated internally or can be supplied by an
external device.
The ATAPI interface connects to CD/DVD and HDD drives,
and is ATAPI-6 compliant. The controller implements the
peripheral I/O mode, the multi-DMA mode, and the Ultra
DMA mode. The DMA modes enable faster data transfer and
reduced host management. The ATAPI Controller supports
PIO, Multi-DMA, and Ultra DMA ATAPI accesses. Key features include:
• Supports PIO modes 0,1,2,3,4
• Supports Multiword DMA modes 0,1,2
• Various general purpose modes with one frame syncs, two
frame syncs, three frame syncs and zero frame sync modes
for both receive and transmit directions.
• ITU-656 status word error detection and correction for
ITU-656 Receive modes.
• ITU-656 preamble and status word decode.
• Three different modes for ITU-656 receive modes: active
video only, vertical blanking only, and entire field mode.
• Horizontal and vertical windowing for GP 2 and 3 frame
sync modes.
• Optional packing and unpacking of data to/from 32 bits
from/to 8, 16 and 24 bits. If packing/unpacking is enabled,
endianness can be changed to change the order of packing/unpacking of bytes/words.
• Optional sign extension or zero fill for receive modes.
• During receive modes, alternate even or odd data samples
can be filtered out.
• Programmable clipping of data values for 8-bit transmit
modes.
• RGB888 can be converted to RGB666 or RGB565 for transmit modes.
• Various de-interleaving/interleaving modes for receiving/transmitting 4:2:2 YCrCb data.
• Supports Ultra DMA modes 0,1,2,3,4,5 (up to UDMA 100)
• Programmable timing for ATA interface unit
• Supports CompactFlash Card using True IDE mode
KEYPAD INTERFACE
The keypad interface is a 16-pin interface module that is used to
detect the key pressed in a 8x8 (maximum) keypad matrix. The
size of the input keypad matrix is programmable. The interface
is capable of filtering the bounce on the input pins, which is
common in keypad applications. The width of the filtered
bounce is programmable. The module is capable of generating
an interrupt request to the core once it identifies that any key
has been pressed.
The interface supports a press-release-press mode and infrastructure for a press-hold mode. The former mode identifies a
press, release and press of a key as two consecutive presses of the
same key whereas the later mode checks the input key’s state in
periodic intervals to determine the number of times the same
key is meant to be pressed. It is possible to detect when multiple
keys are pressed simultaneously, and to provide limited key resolution capability when this happens.
SECURE DIGITAL (SD)/SDIO CONTROLLER
The SD/SDIO controller is a serial interface that stores data at a
data rate of up to 10M bytes per second using a 4-bit data line.
The interface runs at 25 MHz.
• FIFO watermarks and urgent DMA features.
• Clock gating by an external device asserting the clock gating control signal.
• Configurable LCD Data Enable (DEN) output available on
Frame Sync 3.
USB ON-THE-GO DUAL-ROLE DEVICE CONTROLLER
The USB OTG controller provides a low-cost connectivity solution for consumer mobile devices such as cell phones, digital
still cameras and MP3 players, allowing these devices to transfer
data using a point-to-point USB connection without the need
for a PC host. The USBDRC module can operate in a traditional
USB peripheral-only mode as well as the host mode presented
in the On-The-Go (OTG) supplement [1] to the USB 2.0 Specification [2]. In host mode, the USB module supports transfers at
high-speed (480Mbps), full-speed (12Mbps), and low-speed
(1.5Mbps) rates. Peripheral-only mode supports the high- and
full-speed transfer rates.
The SD/SDIO controller supports the SD memory mode only.
The interface supports all the power modes and performs error
checking by CRC.
CODE SECURITY
An OTP/security system consisting of a blend of hardware and
software provides customers with a flexible and rich set of code
security features with LockboxTM1 secure technology. Key features include:
• OTP memory
• Unique chip ID
• Code authentication
• Secure mode of operation
1
Rev. PrG
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Page 15 of 82 |
Lockbox is a trademark of Analog Devices, Inc.
December 2007
ADSP-BF542/4/7/8/9
Preliminary Technical Data
In the active mode, the PLL is enabled but bypassed. Because the
PLL is bypassed, the processor’s core clock (CCLK) and system
clock (SCLK) run at the input clock (CLKIN) frequency. In this
mode, the CLKIN to CCLK multiplier ratio can be changed,
although the changes are not realized until the Full-On mode is
entered. DMA access is available to appropriately configured L1
memories.
In the active mode, it is possible to disable the PLL through the
PLL Control register (PLL_CTL). If disabled, the PLL must be
re-enabled before transitioning to the full-on or sleep modes.
Full On
Active
Interrupts are generated when a user defined amount of synchronous data has been sent or received by the processor or
when asynchronous packets or control messages have been sent
or received.
The MXVR peripheral can wake up the ADSP-BF549 processor
from sleep mode when a wakeup preamble is received over the
network or based on any other MXVR interrupt event. Additionally, detection of network activity by the MXVR can be used
to wake up the ADSP-BF549 processor from sleep mode or
hibernate. These features allow the ADSP-BF549 to operate in a
low-power state when there is no network activity or when data
is not currently being received or transmitted by the MXVR.
The MXVR clock is provided through a dedicated external crystal or crystal oscillator. The frequency of external crystal or
crystal oscillator can be 256Fs, 384Fs, 512Fs, or 1024Fs for
Fs = 38kHz, 44.1kHz, or 48kHz. If using a crystal to provide the
MXVR clock, use a parallel-resonant, fundamental mode,
microprocessor-grade crystal.
DYNAMIC POWER MANAGEMENT
The ADSP-BF542/4/7/8/9 processor provides five operating
modes, each with a different performance/power profile. In
addition, dynamic power management provides the control
functions to dynamically alter the processor core supply voltage,
further reducing power dissipation. Control of clocking to each
1
MOST is a registered trademark of Standard Microsystems, Corp.
Rev. PrG
|
Sleep
Deep Sleep
Hibernate
Enabled
Enabled/
Disabled
Enabled
Disabled
Disabled
Core
Power
Table 5. Power Settings
System
Clock
(SCLK)
The MXVR supports synchronous data, asynchronous packets,
and control messages using dedicated DMA channels which
operate autonomously from the processor core moving data to
and from L1 and/or L2 memory. Synchronous data is transferred to or from the synchronous data physical channels on the
MOST bus through eight programmable DMA channels. The
synchronous data DMA channels can operate in various modes
including modes which trigger DMA operation when data patterns are detected in the receive data stream. Furthermore two
DMA channels support asynchronous traffic and a further two
support control message traffic.
Active Operating Mode – Moderate Power Savings
Core
Clock
(CCLK)
The MXVR is fully compatible with the industry standard standalone MOST controller devices, supporting 22.579 Mbps or
24.576 Mbps data transfer. It offers faster lock times, greater jitter immunity, a sophisticated DMA scheme for data transfers,
and the high-speed internal interface to the core and L1 memory allows the full bandwidth of the network to be utilized. The
MXVR can operate as either the network master or as a network
slave.
In the full-on mode, the PLL is enabled and is not bypassed,
providing capability for maximum operational frequency. This
is the power-up default execution state in which maximum performance can be achieved. The processor core and all enabled
peripherals run at full speed.
PLL
Bypassed
The ADSP-BF549 processor provides a Media Transceiver
(MXVR) MAC layer, allowing the processor to be connected
directly to a MOST®1 network through just an FOT or Electrical
PHY.
Full-On Operating Mode – Maximum Performance
PLL
MEDIA TRANSCEIVER MAC LAYER (MXVR)
of the ADSP-BF542/4/7/8/9 processor peripherals also reduces
power consumption. See Table 5 for a summary of the power
settings for each mode.
Mode
The security scheme is based upon the concept of authentication of digital signatures using standards-based algorithms and
provides a secure processing environment in which to execute
code and protect assets.
No
Yes
Enabled
Enabled
Enabled
Enabled
On
On
-
Disabled
Disabled
Disabled
Enabled
Disabled
Disabled
On
On
Off
Sleep Operating Mode – High Dynamic Power Savings
The sleep mode reduces dynamic power dissipation by disabling
the clock to the processor core (CCLK). The PLL and system
clock (SCLK), however, continue to operate in this mode. Typically an external event or RTC activity will wake up the
processor. When in the sleep mode, assertion of wakeup will
cause the processor to sense the value of the BYPASS bit in the
PLL control register (PLL_CTL). If BYPASS is disabled, the processor will transition to the full on mode. If BYPASS is enabled,
the processor will transition to the active mode.
When in the sleep mode, system DMA access to L1 memory is
not supported.
Deep Sleep Operating Mode – Maximum Dynamic Power
Savings
The deep sleep mode maximizes dynamic power savings by disabling the clocks to the processor core (CCLK) and to all
synchronous peripherals (SCLK). Asynchronous peripherals,
such as the RTC, may still be running but will not be able to
access internal resources or external memory. This powered-
Page 16 of 82 |
December 2007
ADSP-BF542/4/7/8/9
Preliminary Technical Data
down mode can only be exited by assertion of the reset interrupt
(RESET) or by an asynchronous interrupt generated by the
RTC. When in deep sleep mode, an RTC asynchronous interrupt causes the processor to transition to the active mode.
Assertion of RESET while in deep sleep mode causes the processor to transition to the full on mode.
Hibernate State – Maximum Static Power Savings
The hibernate state maximizes static power savings by disabling
the voltage and clocks to the processor core (CCLK) and to all
the synchronous peripherals (SCLK). The internal voltage regulator for the processor can be shut off by writing b#00 to the
FREQ bits of the VR_CTL register. This disables both CCLK
and SCLK. Furthermore, it sets the internal power supply voltage (VDDINT) to 0V to provide the greatest power savings mode.
Any critical information stored internally (memory contents,
register contents, etc.) must be written to a non-volatile storage
device prior to removing power if the processor state is to be
preserved.
VOLTAGE REGULATION
The ADSP-BF542/4/7/8/9 processor provides an on-chip voltage regulator that can generate processor core voltage levels
from an external supply. (Note specifications as indicated in
Operating Conditions on Page 32.) Figure 5 shows the typical
external components required to complete the power management system. The regulator controls the internal logic voltage
levels and is programmable with the voltage regulator control
register (VR_CTL) in increments of 50 mV. To reduce standby
power consumption, the internal voltage regulator can be programmed to remove power to the processor core while keeping
I/O power supplied. While in hibernate mode, VDDEXT, VDDRTC,
VDDDDR, VDDUSB, and VDDVR can still be applied, eliminating the
need for external buffers. The voltage regulator can be activated
from this power down state by assertion of the RESET pin,
which will then initiate a boot sequence. The regulator can also
be disabled and bypassed at the user’s discretion. For additional
information, see “Switching Regulator Design Considerations
for the ASDP-BF533 Blackfin Processors” (EE-228).
Since VDDEXT is still supplied in this mode, all of the external
pins tri-state, unless otherwise specified. This allows other
devices that may be connected to the processor to have power
still applied without drawing unwanted current.
The internal supply regulator can be woken up by CAN, by the
MXVR, by the keypad, by the up/down counter, by the USB,
and by some GPIO pins. It can also be woken up by a real-time
clock wakeup event or by asserting the RESET pin. Waking up
from hibernate state initiates the hardware reset sequence.
2.70V TO 3.6V
INPUT VOLTAGE
RANGE
V DDVR
(L OW-INDUC T A NC E )
S E T OF DE C OUP L ING
C A P A C IT OR S
+
V DDVR
100μF
With the exception of the VR_CTL and the RTC registers, all
internal registers and memories lose their content in hibernate
state. State variables may be held in external SRAM or SDRAM.
10μH
100nF
+
100μF
+
F DS 9431A
100μF
10μF
L OW E S R
Power Savings
As shown in Table 6, the ADSP-BF542/4/7/8/9 processor supports different power domains. The use of multiple power
domains maximizes flexibility, while maintaining compliance
with industry standards and conventions. By isolating the internal logic of the ADSP-BF542/4/7/8/9 processor into its own
power domain, separate from the RTC and other I/O, the processor can take advantage of dynamic power management,
without affecting the RTC or other I/O devices. There are no
sequencing requirements for the various power domains.
V DDINT
ZHC S 1000
S HOR T A ND L OWINDUC T A NC E WIR E
NOT E : DE S IG NE R S HOUL D MINIMIZE
T R A C E L E NG T H T O F DS 9431A .
V R OUT
V R OUT
G ND
Figure 5. Voltage Regulator Circuit
Table 6. Power Domains
Power Domain
All internal logic, except RTC, DDR, and USB
RTC internal logic and crystal I/O
DDR external memory supply
USB internal logic and crystal I/O
Internal voltage regulator
MXVR PLL and logic
All other I/O
VDD Range
VDDINT
VDDRTC
VDDDDR
VDDUSB
VDDVR
VDDMP
VDDEXT
CLOCK SIGNALS
The ADSP-BF542/4/7/8/9 processor can be clocked by an external crystal, a sine wave input, or a buffered, shaped clock
derived from an external clock oscillator.
If an external clock is used, it should be a TTL compatible signal
and must not be halted, changed, or operated below the specified frequency during normal operation. This signal is
connected to the processor’s CLKIN pin. When an external
clock is used, the XTAL pin must be left unconnected.
Alternatively, because the ADSP-BF542/4/7/8/9 processor
includes an on-chip oscillator circuit, an external crystal may be
used. For fundamental frequency operation, use the circuit
Rev. PrG
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Page 17 of 82 |
December 2007
ADSP-BF542/4/7/8/9
Preliminary Technical Data
shown in Figure 6. A parallel-resonant, fundamental frequency,
microprocessor-grade crystal is connected across the CLKIN
and XTAL pins. The on-chip resistance between CLKIN and the
XTAL pin is in the 500 kΩ range. Further parallel resistors are
typically not recommended. The two capacitors and the series
resistor shown in Figure 6 fine tune phase and amplitude of the
sine frequency.
voltages VDDINT and VDDEXT, the VCO is always permitted to run
up to the frequency specified by the part’s speed grade. The
CLKOUT pin reflects the SCLK frequency to the off-chip world.
It functions as reference for many timing specifications. While
inactive by default, it can be enabled using the EBIU_SDGCTL
and EBIU_AMGCTL registers.
The capacitor and resistor values shown in Figure 6 are typical
values only. The capacitor values are dependent upon the crystal
manufacturers’ load capacitance recommendations and the PCB
physical layout. The resistor value depends on the drive level
specified by the crystal manufacturer. System designs should
verify the customized values based on careful investigations on
multiple devices over temperature range.
DYNAMIC MODIFICATION
REQUIRES PLL SEQUENCING
PLL
0.5x - 64x
CLKIN
DYNAMIC MODIFICATION
ON-THE-FLY
1, 2, 4, 8
CCLK
1:15
SCLK
VCO
BLACKFIN
SCLK CCLK/2
SCLK 133MHz
CLKOUT
TO PLL CIRCUITRY
EN
CLKBUF
Figure 7. Frequency Modification Methods
EN
All on-chip peripherals are clocked by the system clock (SCLK).
The system clock frequency is programmable by means of the
SSEL3–0 bits of the PLL_DIV register. The values programmed
into the SSEL fields define a divide ratio between the PLL output
(VCO) and the system clock. SCLK divider values are two
through 15. Table 7 illustrates typical system clock ratios. The
default ratio is 4.
XTAL
CLKIN
3306*
FOR OVERTONE
OPERATION ONLY:
18 pF*
18 pF*
NOTE: VALUES MARKED WITH * MUST BE CUSTOMIZED
DEPENDING ON THE CRYSTAL AND LAYOUT. PLEASE
ANALYZE CAREFULLY.
Table 7. Example System Clock Ratios
Signal Name
SSEL3–0
0010
0110
1010
Figure 6. External Crystal Connections
A third-overtone crystal can be used at frequencies above 25
MHz. The circuit is then modified to ensure crystal operation
only at the third overtone, by adding a tuned inductor circuit as
shown in Figure 6. A design procedure for third-overtone operation is discussed in detail in application note EE-168.
The Blackfin core runs at a different clock rate than the on-chip
peripherals. As shown in Figure 7 on Page 18, the core clock
(CCLK) and system peripheral clock (SCLK) are derived from
the input clock (CLKIN) signal. An on-chip PLL is capable of
multiplying the CLKIN signal by a programmable
0.5ⴛ to 64ⴛ multiplication factor (bounded by specified minimum and maximum VCO frequencies). The default multiplier
is 8ⴛ, but it can be modified by a software instruction sequence.
On-the-fly frequency changes can be effected by simply writing
to the PLL_DIV register.
Note that the divisor ratio must be chosen to limit the system
clock frequency to its maximum of fSCLK. The SSEL value can be
changed dynamically without any PLL lock latencies by writing
the appropriate values to the PLL divisor register (PLL_DIV).
The core clock (CCLK) frequency can also be dynamically
changed by means of the CSEL1–0 bits of the PLL_DIV register.
Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in
Table 8. The default ratio is 1. This programmable core clock
capability is useful for fast core frequency modifications.
On-the-fly CCLK and SCLK frequency changes can be effected
by simply writing to the PLL_DIV register. Whereas the maximum allowed CCLK and SCLK rates depend on the applied
Rev. PrG
|
Example Frequency Ratios
Divider Ratio (MHz)
VCO/SCLK
VCO
SCLK
2:1
200
100
6:1
300
50
10:1
500
50
Page 18 of 82 |
December 2007
ADSP-BF542/4/7/8/9
Preliminary Technical Data
The maximum CCLK frequency not only depends on the part's
speed grade, it also depends on the applied VDDINT voltage. See
Table 16 through Table 18 for details.
pins of the reset configuration register, sampled during poweron resets and software-initiated resets, implement the following
modes:
Table 8. Core Clock Ratios
Signal Name
CSEL1–0
00
01
10
11
Divider Ratio Example Frequency Ratios
VCO/CCLK
(MHz)
VCO
CCLK
1:1
300
300
2:1
300
150
4:1
500
125
8:1
200
25
BOOTING MODES
The ADSP-BF542/4/7/8/9 processor has many mechanisms
(listed in Table 9) for automatically loading internal and external memory after a reset. The boot mode is defined by four
BMODE input pins dedicated to this purpose. There are two
categories of boot modes: In master boot modes the processor
actively loads data from parallel or serial memories. In slave
boot modes the processor receives data from an external host
devices.
Table 9. Booting Modes
BMODE3–0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Description
Idle–no boot
Boot from 8- or 16-bit external flash memory
Boot from 16-bit asynchronous FIFO
Boot from serial SPI memory (EEPROM or flash)
Boot from SPI host device
Boot from serial TWI memory (EEPROM/flash)
Boot from TWI host
Boot from UART host
Reserved
Reserved
Boot from (DDR) SDRAM
Boot from OTP memory
Reserved
Boot from 8- or 16-bit NAND flash memory via NFC
Boot from 16-Bit Host DMA
Boot from 8-Bit Host DMA
The boot modes listed in Table 9 provide a number of mechanisms for automatically loading the processor’s internal and
external memories after a reset. By default all boot modes use
the slowest meaningful configuration settings. Default settings
can be altered via the initialization code feature at boot time or
by proper OTP programming at pre-boot time.The BMODE
Rev. PrG
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Page 19 of 82 |
• Idle–no boot mode (BMODE=0x0) — In this mode, the
processor goes into idle. The idle boot mode helps to
recover from illegal operating modes, in the case the user
misconfigured the OTP memory.
• Boot from 8- or 16-bit external flash memory
(BMODE=0x1) — In this mode, the boot kernel loads the
first block header from address 0x2000 0000 and—depending on instructions containing in the header—the boot
kernel performs 8-bit or 16-bit boot or starts program execution at the address provided by the header. By default, all
configuration settings are set for the slowest device possible
(3-cycle hold time; 15-cycle R/W access times; 4-cycle
setup).
The ARDY is not enabled by default. It can however, be
enabled by OTP programming. Similarly, all interface
behavior and timings can customized up by OTP programming. This includes activation of burst-mode or pagemode operation. In this mode, all signals belonging to the
asynchronous interface are enabled at port muxing level.
• Boot from 16-bit asynchronous FIFO (BMODE=0x2) — In
this mode, the boot kernel starts booting from address
0x2030 0000. Every 16-bit word that boot kernel has to read
from the FIFO must be requested by an low pulse on the
DMAR1 pin.
• Boot from serial SPI memory, EEPROM or flash
(BMODE=0x3) — Eight-, 16-, 24- or 32-bit addressable
devices are supported. (internal note: no special support for
DataFlashes, as they understand now also standard SPI
protocol). The processor uses the PE4 GPIO pin to select a
single SPI EEPROM/flash device, submits a read command
and successive address bytes (0x00) until a valid 8-, 16-,
24-, or 32-bit addressable device is detected. Pull-up resistors are required on the SSEL and MISO pins. By default, a
value of 0x85 is written to the SPI_BAUD register.
• Boot from SPI host device (BMODE=0x4) — The processor operates in SPI slave mode (using SPI0) and is
configured to receive the bytes of the.LDR file from an SPI
host (master) agent. In the host, the HWAIT signal must be
interrogated by the host before every transmitted byte. A
pull-up resistor is required on the SPISS input. A pulldown on the serial clock may improve signal quality and
booting robustness.
• Boot from serial TWI memory, EEPROM/flash
(BMODE=0x5) — The processor operates in master mode
(using TWI0) and selects the TWI slave with the unique id
0xA0. The processor submits successive read commands to
the memory device starting at two byte internal address
0x0000 and begins clocking data into the processor. The
TWI memory device should comply with Philips I2C Bus
Specification version 2.1 and have the capability to autoincrement its internal address counter such that the contents of the memory device can be read sequentially. By
default, a prescale value of 0xA and CLKDIV value of
December 2007
ADSP-BF542/4/7/8/9
Preliminary Technical Data
0x0811 is used. Unless, altered by OTP settings an I2C
memory that takes two address bytes is assumed. Development tools ensure that data that is booted to memories that
cannot be accessed by the Blackfin core is written to intermediate storage place and then copied to final destination
via Memory DMA.
• Boot from TWI host (BMODE=0x6) — The TWI host
agent selects the slave with the unique id 0x5F. The processor (using TWI0) replies with an acknowledgement and the
host can then download the boot stream. The TWI host
agent should comply with Philips I2C Bus Specification version 2.1. An I2C multiplexer can be used to select one
processor at a time when booting multiple processors from
a single TWI.
• Boot from UART host (BMODE=0x7) — In this mode, the
processor uses UART1 as booting source. Using an autobaud handshake sequence, a boot-stream-formatted
program is downloaded by the host. The host agent selects
a bit rate within the UART’s clocking capabilities.
When performing the autobaud, the UART expects a “@”
(0x40) character (eight bits data, one start bit, one stop bit,
no parity bit) on the RXD pin to determine the bit rate. It
then replies with an acknowledgement which is composed
of 4 bytes: 0xBF, the value of UART_DLL, the value of
UART_DLH, 0x00. The host can then download the boot
stream. The processor deasserts the RTS output to hold off
the host; CTS functionality is not enabled at boot time.
• Boot from (DDR) SDRAM (BMODE=0xA) — In this
mode, the boot kernel starts booting from address
0x0000 0010. This is a warm boot scenario only. The
SDRAM is expected to contain a valid boot stream and the
SDRAM controller must have been configured by the OTP
settings.
• Boot from 8-bit and 16-bit external NAND flash memory
(BMODE=0xD) - In this mode, auto detection of the
NAND flash device is performed. The processor configures
PORTJ GPIO pins PJ1 and PJ2 to enable the NAND CE
and NAND RB signals respectively. For correct device
operation pull-up resistors are required on both CE (PJ1)
and RB (PJ2) signals. By default a value of 0x0033 is written
to the NFC_CTL register. The booting procedure always
starts by booting from byte 0 of block 0 of the NAND flash
device.
NAND flash boot supports the following features:
• Device Auto Detection.
• Error Detection & Correction for maximum
reliability.
• No boot stream size limitation.
• Peripheral DMA via channel 22 providing efficient
transfer of all data (excluding the ECC parity data).
• Software configurable boot mode for booting from
boot streams expanding multiple blocks including bad
blocks.
• Software configurable boot mode for booting from
multiple copies of the boot stream allowing for handling of bad blocks and uncorrectable errors.
• Configurable timing via OTP memory.
Small page NAND flash devices must have a 512 byte page
size, 32 pages per block, a 16 byte spare area size and a bus
configuration of 8 bits. By default all read requests from the
NAND flash are followed by 4 address cycles. If the NAND
flash device requires only 3 address cycles the device must
be capable of ignoring the additional address cycles.
The small page NAND flash device must comply with the
following command set:
Reset: 0xFF
Read lower half of page: 0x00
Read upper half of page: 0x01
Read spare area: 0x50
For large page NAND flash devices the 4 byte electronic
signature is read in order to configure the kernel for booting, this allows support for multiple large page devices.
Byte 4 of the electronic signature must comply with the following specification in Table 10 on page 21.
Any configuration from Table 10 that also complies with
the command set listed below is directly supported by the
boot kernel. There are no restrictions on the page size or
block size as imposed by the small page boot kernel.
Large page devices must support the following command
set:
Reset: 0xFF
Read Electronic Signature: 0x90
Read: 0x00, 0x30 (confirm command)
Large page devices must not support or react to NAND
flash command 0x50. This is a small page NAND flash
command used for device auto detection.
By default the boot kernel will always issue 5 address cycles,
therefore if a large page device requires only 4 cycles, the
device must be capable of ignoring the additional address
cycles.
Rev. PrG
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December 2007
ADSP-BF542/4/7/8/9
Preliminary Technical Data
as the SDRAM controller, then returns using an RTS
instruction. The routine may also by the final application
which will never return to the boot kernel.
16-bit NAND flash memory devices must only support the
issuing of command and address cycles via the lower 8 bits
of the data bus. Devices that make use of the full 16-bit bus
for command and address cycles are not supported.
• Boot from 8-Bit Host DMA (BMODE=0xF) — In this
mode, the Host DMA port is configured in 8-bit interrupt
mode, little endian. Unlike in other modes, here the host is
responsible for interpreting the boot stream. It writes data
block per data block into the Host DMA port. Before configuring the DMA settings for each block, the host may
either poll the ALLOW_CONFIG bit in HOST_STATUS
or wait to be interrupted by the HWAIT signal. When
using HWAIT, the host must still check ALLOW_CONFIG
at least once before beginning to configure the Host DMA
Port. The host will receive an interrupt from the
HOST_ACK signal every time it is allowed to send the next
FIFO depth (Sixteen 32-bit words) of information. When
the host sends an HIRQ control command, the boot kernel
issues a CALL instruction to address 0xFFA0 0000. It is the
host's responsibility to ensure valid code has been place at
this address. The routine at 0xFFA0 0000 can be a simple
initialization routine to configure internal resources, such
as the SDRAM controller, then returns using an RTS
instruction. The routine may also by the final application
which will never return to the boot kernel.
Table 10. Byte 4 Electronic Signature Specification
Page Size (excluding D1:D0
spare area)
Spare Area Size
D2
Block Size (excluding D5:4
spare area)
Bus width
Not Used for
configuration
D6
00
1KBytes
01
2KBytes
10
4KBytes
11
8KBytes
0
8Bytes / 512Bytes
1
16Bytes /
512Bytes
00
64KBytes
01
128 kBytes
10
256KBytes
11
512KBytes
0
x8
1
x16
For each of the boot modes, a 16-byte header is first read from
an external memory device. The header specifies the number of
bytes to be transferred and the memory destination address.
Multiple memory blocks may be loaded by any boot sequence.
Once all blocks are loaded, program execution commences from
the address stored in the EVT1 register.
D3, D7
• Boot from OTP memory (BMODE=0xB) — This provides
a stand-alone booting method. The boot stream is loaded
from on-chip OTP memory. By default the boot stream is
expected to start from OTP page 0x40 on and can occupy
all public OTP memory up to page 0xDF. This is 2560
bytes. Since the start page is programmable the maximum
size of the boot stream can be extended to 3072 bytes.
• Boot from 16-Bit Host DMA (BMODE=0xE) — In this
mode, the host DMA port is configured in 16-bit Acknowledge mode, little endian. Unlike in other modes, here the
host is responsible for interpreting the boot stream. It
writes data block per data block into the Host DMA port.
Before configuring the DMA settings for each block, the
host may either poll the ALLOW_CONFIG bit in
HOST_STATUS or wait to be interrupted by the HWAIT
signal. When using HWAIT, the host must still check
ALLOW_CONFIG at least once before beginning to configure the Host DMA Port. After completing the
configuration the host is required to poll the READY bit in
HOST_STATUS before beginning to transfer data. When
the host sends an HIRQ control command, the boot kernel
issues a CALL instruction to 0xFFA0 0000 address. It is the
host's responsibility to ensure valid code has been placed at
this address. The routine at 0xFFA0 0000 can be a simple
initialization routine to configure internal resources, such
Rev. PrG
|
Prior to booting, the pre-boot routine interrogates the OTP
memory. Individual boot modes can be customized or even disabled based on OTP programming. External hardware,
especially booting hosts may watch the HWAIT signal to determine when the pre-boot has finished and the boot kernel starts
the boot process. By programming OTP memory, the user can
instruct the preboot routine to also customize: PLL and Voltage
Regulator; DDR Controller; and Asynchronous Interface.
The boot kernel differentiates between a regular hardware reset
and a wakeup-from-hibernate event to speed up booting in the
later case. Bits 6-4 in the system reset configuration (SYSCR)
register can be used to bypass pre-boot routine and/or boot kernel in case of a software reset. They can also be used to simulate
a wakeup-from-hibernate boot in the software reset case.
The boot process can be further customized by “initialization
code.” This is a piece of code that is loaded and executed prior to
the regular application boot. Typically, this is used to configure
the DDR controller or to speed up booting by managing PLL,
clock frequencies, wait states, or serial bit rates.
The boot ROM also features C-callable function entries that can
be called by the user application at run time. This enables second-stage boot or boot management schemes to be
implemented with ease.
Page 21 of 82 |
December 2007
ADSP-BF542/4/7/8/9
Preliminary Technical Data
INSTRUCTION SET DESCRIPTION
The Blackfin processor family assembly language instruction set
employs an algebraic syntax designed for ease of coding and
readability. The instructions have been specifically tuned to provide a flexible, densely encoded instruction set that compiles to
a very small final memory size. The instruction set also provides
fully featured multifunction instructions that allow the programmer to use many of the processor core resources in a single
instruction. Coupled with many features more often seen on
microcontrollers, this instruction set is very efficient when compiling C and C++ source code. In addition, the architecture
supports both user (algorithm/application code) and supervisor
(O/S kernel, device drivers, debuggers, ISRs) modes of operation, allowing multiple levels of access to core processor
resources.
The assembly language, which takes advantage of the processor’s unique architecture, offers the following advantages:
• Seamlessly integrated DSP/MCU features are optimized for
both 8-bit and 16-bit operations.
• A multi-issue load/store modified-Harvard architecture,
which supports two 16-bit MAC or four 8-bit ALU + two
load/store + two pointer updates per cycle.
allowing the developer to load code, set breakpoints, observe
variables, observe memory, and examine registers. The processor must be halted to send data and commands, but once an
operation has been completed by the emulator, the processor
system is set running at full speed with no impact on system
timing.
To use these emulators, the target board must include a header
that connects the processor’s JTAG port to the emulator.
For details on target board design issues including mechanical
layout, single processor connections, multiprocessor scan
chains, signal buffering, signal termination, and emulator pod
logic, see Analog Devices JTAG Emulation Technical Reference
(EE-68) on the Analog Devices web site under
www.analog.com/ee-notes. This document is updated regularly
to keep pace with improvements to emulator support.
RELATED DOCUMENTS
The following publications that describe the
ADSP-BF542/4/7/8/9 processors (and related processors) can
be ordered from any Analog Devices sales office or accessed
electronically on our Website:
• All registers, I/O, and memory are mapped into a unified
4G byte memory space, providing a simplified programming model.
• Microcontroller features, such as arbitrary bit and bit-field
manipulation, insertion, and extraction; integer operations
on 8-, 16-, and 32-bit data-types; and separate user and
supervisor stack pointers.
• Code density enhancements, which include intermixing of
16- and 32-bit instructions (no mode switching, no code
segregation). Frequently used instructions are encoded in
16 bits.
• ADSP-BF54x Blackfin Processor Hardware Reference
• ADSP-BF54x Blackfin Processor Peripheral Reference
• ADSP-BF54x Blackfin Processor Programming Reference
• ADSP-BF542 Blackfin Embedded Processor Silicon Anomaly List (in preparation)
• ADSP-BF544 Blackfin Embedded Processor Silicon Anomaly List (in preparation)
• ADSP-BF548 Blackfin Embedded Processor Silicon Anomaly List (in preparation)
• ADSP-BF549 Blackfin Embedded Processor Silicon Anomaly List
DEVELOPMENT TOOLS
The ADSP-BF542/4/7/8/9 processor is supported with a complete set of CROSSCORE® software and hardware development
tools, including Analog Devices emulators and VisualDSP++®
development environment. The same emulator hardware that
supports other Blackfin processors also fully emulates the
ADSP-BF542/4/7/8/9 processor.
EZ-KIT Lite® Evaluation Board
For evaluation of ADSP-BF542/4/7/8/9 processors, use the
ADSP-BF548 EZ-KIT Lite board available from Analog Devices.
Order part number ADDS-BF548-EZLITE. The board comes
with on-chip emulation capabilities and is equipped to enable
software development. Multiple daughter cards are available.
DESIGNING AN EMULATOR-COMPATIBLE
PROCESSOR BOARD (TARGET)
The Analog Devices family of emulators are tools that every system developer needs to test and debug hardware and software
systems. Analog Devices has supplied an IEEE 1149.1 JTAG
Test Access Port (TAP) on each JTAG processor. The emulator
uses the TAP to access the internal features of the processor,
Rev. PrG
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December 2007
ADSP-BF542/4/7/8/9
Preliminary Technical Data
PIN DESCRIPTIONS
ADSP-BF542/4/7/8/9 processor pin multiplexing scheme is
listed in Table 11 and the pin definitions are listed in Table 12.
Table 11. Pin Multiplexing
Primary Pin
Function
(Number of
Pins)1, 2
Port A
GPIO (16 pins)
First Peripheral
Function
Second Peripheral
Function
Third Peripheral
Function
SPORT2 (8 pins)
TMR4 (1 pin)
TMR5 (1 pin)
TMR6 (1 pin)
TMR7 (1 pin)
TACI7 (1 shared pin)
TACLK7-0 (8 pins)
Interrupts (16 pins)
TACI2-3 (2 pins)
Interrupts (15 pins)
SPORT3 (8 pins)
Port B
GPIO (15 pins)
Port C
GPIO (16 pins)
TWI1 (2 pins)
HWAIT (1 pin)
UART2 or 3 CTL (2 pins)
UART2 (2 pins)
UART3 (2 pins)
SPI2 SEL (4 pins)
TMR0–2 (3 pins)
SPI2 (3 pins)
TMR3 (1 pin)
SPORT0 (8 pins)
Fourth Peripheral
Function
HWAIT (1 pin)
Interrupts (8 pins)3
MXVR MMCLK, MBCLK
(2 pins)
SDH (6 pins)
Port D
GPIO (16 pins)
Port E
GPIO (16 pins)
Interrupts (8 pins)
EPPI1 D0–15 (16 pins) Host D0–15 (16 pins)
SPI0 (7 pins)
UART0 TX (1 pin)
UART0 RX (1 pin)
UART0 or 1 CTL (2 pins)
EPPI1 CLK,FS (3 pins)
5V-Tolerant inputs TWI0 (2 pins)
Port F
GPIO (16 pins)
EPPI0 D0–15 (16 pins)
Interrupt Capability
Keypad
Row 4–6
Col 4–7 (7 pins)
Keypad R7 (1 pin)
SPORT1 (8 pins)
EPPI0 D18– 23 (6 pins) Interrupts (8 pins)
EPPI2 D0–7 (8 pins)
Keypad
Row 0–3
Col 0–3 (8 pins)
TACI0 (1 pin)
Interrupts (8 pins)
Interrupts (8 pins)
Interrupts (8 pins)
Interrupts (8 pins)
Interrupts (8 pins)
Rev. PrG
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Page 23 of 82 |
December 2007
ADSP-BF542/4/7/8/9
Preliminary Technical Data
Table 11. Pin Multiplexing
Primary Pin
Function
(Number of
Pins)1, 2
Port G
GPIO (16 pins)
Port H
GPIO (14 pins)
First Peripheral
Function
Second Peripheral
Function
Third Peripheral
Function
EPPI0 CLK,FS (3 pins)
DATA 16–17 (2 pins)
SPI1 SEL1–3 (3 pins)
SPI1 (4 pins)
CAN0 (2 pins)
CAN1 (2 pins)
TMRCLK (1 pin)
Host CTL (3 pins)
MXVR MTXON (1 pin)
EPPI2 CLK,FS (3 pins)
TACI4-5 (2 pins)
UART1 (2 pins)
ATAPI_RST (1 pin)
HOST_ADDR (1 pin)
EPPI0-1_FS3 (2 pins)
TMR8 (1 pin)
TMR9 (1 pin)
HOST_ACK (1 pin)
TMR10 (1 pin)
TACI1 (1 pin)
EPPI2_FS3 (1 pin)
Counter Down/Gate
(1 pin)
Counter Up/Dir
(1 pin)
DMAR 0–1 (2 pins)
Interrupt Capability
Interrupts (8 pins)
MXVR MRX, MTX,
MRXON (3 pins)
AMC Addr 4-9 (6 pins)
Port I
GPIO (16 pins)
Fourth Peripheral
Function
CZM (1 pin)
Interrupts (8 pins)
Interrupts (8 pins)
TACI8-10 (3 shared
pins)
TACLK8-10 (3 shared
pins)
HWAIT
Interrupts (6 pins)
Async Addr10–25
(16 pins)
Interrupts (8 pins)
Interrupts (8 pins)
Port J
GPIO (14 pins)
Async CTL and MISC
Interrupts (8 pins)
Interrupts (6 pins)
1
Port connections may be inputs or outputs after power up depending on BF54x family member number and boot mode chosen.
All Port connections always power up as inputs for some period of time and require resistive termination to a safe condition if used as outputs in the system.
3
A total of 32 interrupts at once are available from Ports C through J, configurable in byte-wide blocks.
2
ADSP-BF542/4/7/8/9 processor pin definitions are listed in
Table 12. To see the pin multiplexing scheme, see Table 11.
Rev. PrG
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December 2007
ADSP-BF542/4/7/8/9
Preliminary Technical Data
Table 12. Pin Descriptions
Pin Name
Port A: GPIO/SPORT2–3/TMR4–7
PA0/TFS2
PA1/DT2SEC/TMR4
PA2/DT2PRI
PA3/TSCLK2
PA4/RFS2
PA5/DR2SEC/TMR5
PA6/DR2PRI
PA7/RSCLK2/TACLK0
PA8/TFS3/TACLK1
PA9/DT3SEC/TMR6
PA10/DT3PRI/TACLK2
PA11/TSCLK3/TACLK3
PA12/RFS3/TACLK4
PA13/DR3SEC/TMR7/TACLK5
PA14/DR3PRI/TACLK6
PA15/RSCLK3/TACLK7 and TACI7
Port B: GPIO/TWI1/UART2–3/SPI2/TMR0–3
PB0/SCL1
PB1/SDA1
PB2/UART3RTS
PB3/UART3CTS
PB4/UART2TX
PB5/UART2RX/TACI2
PB6/UART3TX
PB7/UART3RX/TACI3
PB8/SPI2SS/TMR0
PB9/SPI2SEL1/TMR1
PB10/SPI2SEL2/TMR2
PB11/SPI2SEL3/TMR3/ HWAIT5
PB12/SPI2SCK
PB13/SPI2MOSI
PB14/SPIMISO
I/O1 Function (First/Second/Third/Fourth)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GPIO/SPORT2 Transmit Frame Sync
GPIO/SPORT2 Transmit Data Secondary/Timer 4
GPIO/SPORT2 Transmit Data Primary
GPIO/SPORT2 Transmit Serial Clock
GPIO/SPORT2 Receive Frame Sync
GPIO/SPORT2 Receive Data Secondary/Timer 5
GPIO/SPORT2 Receive Data Primary
GPIO/SPORT2 Receive Serial Clock/Alternate Input Clock 0
GPIO/SPORT3 Transmit Frame Sync/Alternate Input Clock 1
GPIO/SPORT3 Transmit Data Secondary/Timer 6
GPIO/SPORT3 Transmit Data Primary/Alternate Input Clock 2
GPIO/SPORT3 Transmit Serial Clock/Alternate Input Clock 3
GPIO/SPORT3 Receive Frame Sync/Alternate Input Clock 4
GPIO/SPORT3 Receive Data Secondary/Timer 7/Alternate Input Clock 5
GPIO/SPORT3 Receive Data Primary/Alternate Input Clock 6
GPIO/SPORT3 Receive Serial Clock/Alt Input Clock 7 and Alt Capture Input 7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GPIO/TWI1 Serial Clock
GPIO/TWI1 Serial Data
GPIO/UART3 Request To Send
GPIO/UART3 Clear To Send
GPIO/UART2 Transmit
GPIO/UART2 Receive/Alternate Capture Input 2
GPIO/UART3 Transmit
GPIO/UART3 Receive/Alternate Capture Input 3
GPIO/SPI2 Slave Select Input/Timer 0
GPIO/SPI2 Slave Select Enable 1/Timer 1
GPIO/SPI2 Slave Select Enable 2/Timer 2
GPIO/SPI2 Slave Select Enable 3/Timer 3/Boot Host Wait
GPIO/SPI2 Clock
GPIO/SPI2 Master Out Slave In
GPIO/SPI2 Master In Slave Out
Rev. PrG
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Page 25 of 82 |
December 2007
ADSP-BF542/4/7/8/9
Preliminary Technical Data
Table 12. Pin Descriptions (Continued)
Pin Name
Port C: GPIO/SPORT0/SD Controller/MXVR (MOST)
PC0/TFS0
PC1/DT0SEC/MMCLK
PC2/DT0PRI
PC3/TSCLK0
PC4/RFS0
PC5/DR0SEC/MBCLK
PC6/DR0PRI
PC7/RSCLK0
PC8/SD_D0
PC9/SD_D1
PC10/SD_D2
PC11/SD_D3
PC12/SD_CLK
PC13/SD_CMD
Port D: GPIO/EPPI0–2/SPORT 1/Keypad/Host DMA
PD0/PPI1_D0/HOST_D8/ TFS1/PPI0_D18
PD1/PPI1_D1/HOST_D9/ DT1SEC/PPI0_D19
PD2/PPI1_D2/HOST_D10/ DT1PRI/PPI0_D20
PD3/PPI1_D3/HOST_D11/ TSCLK1/PPI0_D21
PD4/PPI1_D4 / HOST_D12/RFS1/PPI0_D22
PD5/PPI1_D5/HOST_D13/DR1SEC/PPI0_D23
PD6/PPI1_D6/HOST_D14/DR1PRI
PD7/PPI1_D7/HOST_D15/RSCLK1
PD8/PPI1_D8/HOST_D0/ PPI2_D0/KEY_ROW0
PD9/PPI1_D9/HOST_D1/PPI2_D1/KEY_ROW1
PD10/PPI1_D10/HOST_D2/PPI2_D2/KEY_ROW2
PD11/PPI1_D11/HOST_D3/PPI2_D3/KEY_ROW3
PD12/PPI1_D12/HOST_D4/PPI2_D4/KEY_COL0
PD13/PPI1_D13/HOST_D5/PPI2_D5/KEY_COL1
PD14/PPI1_D14/HOST_D6/PPI2_D6/KEY_COL2
PD15/PPI1_D15/HOST_D7/PPI2_D7/KEY_COL3
I/O1 Function (First/Second/Third/Fourth)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GPIO/SPORT0 Transmit Frame Sync
GPIO/SPORT0 Transmit Data Secondary/MXVR Master Clock
GPIO/SPORT0 Transmit Data Primary
GPIO/SPORT0 Transmit Serial Clock
GPIO/SPORT0 Receive Frame Sync
GPIO/SPORT0 Receive Data Secondary/MXVR Bit Clock
GPIO/SPORT0 Receive Data Primary
GPIO/SPORT0 Receive Serial Clock
GPIO/SD Data Bus
GPIO/SD Data Bus
GPIO/SD Data Bus
GPIO/SD Data Bus
GPIO/SD Clock Output
GPIO/SD Command
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GPIO/EPPI1 Data/Host DMA/SPORT 1 Transmit Frame Sync/EPPI0 Data
GPIO/EPPI1 Data/Host DMA/SPORT 1 Transmit Data Secondary/EPPI0 Data
GPIO/EPPI1 Data/Host DMA/SPORT 1 Transmit Data Primary/EPPI0 Data
GPIO/EPPI1 Data/Host DMA/SPORT 1 Transmit Serial Clock/EPPI0 Data
GPIO/EPPI1 Data/Host DMA/SPORT 1 Receive Frame Sync/EPPI0 Data
GPIO/EPPI1 Data/Host DMA/SPORT 1 Receive Data Secondary/EPPI0 Data
GPIO/EPPI1 Data/Host DMA/SPORT 1 Receive Data Primary
GPIO/EPPI1 Data /Host DMA/SPORT 1 Receive Serial Clock
GPIO/EPPI1 Data/Host DMA/EPPI2 Data/Keypad Row Input
GPIO/EPPI1 Data/Host DMA/EPPI2 Data/Keypad Row Input
GPIO/EPPI1 Data/Host DMA/EPPI2 Data/Keypad Row Input
GPIO/EPPI1 Data/Host DMA/EPPI2 Data/Keypad Row Input
GPIO/EPPI1 Data/Host DMA/EPPI2 Data/Keypad Column Output
GPIO/EPPI1 Data/Host DMA/EPPI2 Data/Keypad Column Output
GPIO/EPPI1 Data/Host DMA/EPPI2 Data/Keypad Column Output
GPIO/EPPI1 Data/Host DMA/EPPI2 Data/Keypad Column Output
Rev. PrG
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December 2007
ADSP-BF542/4/7/8/9
Preliminary Technical Data
Table 12. Pin Descriptions (Continued)
I/O1 Function (First/Second/Third/Fourth)
Pin Name
Port E: GPIO/SPI0/UART0-1/EPPI1/TWI0/Keypad
PE0/SPI0SCK/KEY_COL72
PE1/SPI0MISO/KEY_ROW62
PE2/SPI0MOSI/KEY_COL6
PE3/SPI0SS/KEY_ROW5
PE4/SPI0SEL1/KEY_COL52
PE5/SPI0SEL2/KEY_ROW4
PE6/SPI0SEL3/KEY_COL4
PE7/UART0TX/KEY_ROW7
PE8/UART0RX/TACI0
PE9/UART1RTS
PE10/UART1CTS
PE11/PPI1_CLK
PE12/PPI1_FS1
PE13/PPI1_FS2
PE14/SCL03
PE15/SDA03
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GPIO/SPI0 Clock/Keypad Column Output
GPIO/SPI0 Master In Slave Out/Keypad Row Input
GPIO/SPI0 Master Out Slave In/Keypad Column Output
GPIO/SPI0 Slave Select Input/Keypad Row Input
GPIO/SPI0 Slave Select Enable 1/Keypad Column Output
GPIO/SPI0 Slave Select Enable 2/Keypad Row Input
GPIO/SPI0 Slave Select Enable 3/Keypad Column Output
GPIO/UART0 Transmit/Keypad Row Input
GPIO/UART0 Receive/Alternate Capture Input 0
GPIO/UART1 Request To Send
GPIO/UART1 Clear To Send
GPIO / EPPI1Clock
GPIO/EPPI1 Frame Sync 1
GPIO/EPPI1 Frame Sync 2
GPIO/TWI0 Serial Clock
GPIO/TWI0 Serial Data
Port F: GPIO / EPPI0 / Alternate ATAPI Data
PF0/PPI0_D0/ATAPI_D0A4
PF1/PPI0_D1/ATAPI_D1A4
PF2/PPI0_D2/ATAPI_D2A4
PF3/PPI0_D3/ATAPI_D3A4
PF4/PPI0_D4/ATAPI_D4A4
PF5/PPI0_D5/ATAPI_D5A4
PF6/PPI0_D6/ATAPI_D6A4
PF7/PPI0_D7/ATAPI_D7A4
PF8/PPI0_D8/ATAPI_D8A4
PF9/PPI0_D9/ATAPI_D9A4
PF10/PPI0_D10/ATAPI_D10A4
PF11/PPI0_D11/ATAPI_D11A4
PF12/PPI0_D12/ATAPI_D12A4
PF13/PPI0_D13/ATAPI_D13A4
PF14/PPI0_D14/ATAPI_D14A4
PF15/PPI0_D15/ATAPI_D15A4
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GPIO/EPPI0 Data/Alternate ATAPI Data
GPIO/EPPI0 Data/Alternate ATAPI Data
GPIO/EPPI0 Data/Alternate ATAPI Data
GPIO/EPPI0 Data/Alternate ATAPI Data
GPIO/EPPI0 Data/Alternate ATAPI Data
GPIO/EPPI0 Data/Alternate ATAPI Data
GPIO/EPPI0 Data/Alternate ATAPI Data
GPIO/EPPI0 Data/Alternate ATAPI Data
GPIO/EPPI0 Data/Alternate ATAPI Data
GPIO/EPPI0 Data/Alternate ATAPI Data
GPIO/EPPI0 Data/Alternate ATAPI Data
GPIO/EPPI0 Data/Alternate ATAPI Data
GPIO/EPPI0 Data/Alternate ATAPI Data
GPIO/EPPI0 Data/Alternate ATAPI Data
GPIO/EPPI0 Data/Alternate ATAPI Data
GPIO/EPPI0 Data/Alternate ATAPI Data
Rev. PrG
|
Page 27 of 82 |
December 2007
ADSP-BF542/4/7/8/9
Preliminary Technical Data
Table 12. Pin Descriptions (Continued)
Pin Name
I/O1 Function (First/Second/Third/Fourth)
Port G: GPIO / EPPI0 / SPI1 / EPPI2 / Up-Down Counter / CAN0–1 / Host DMA/ MXVR (MOST)
PG0/PPI0_CLK/TMRCLK
I/O GPIO/EPPI0 Clock/External Timer Reference
PG1/PPI0_FS1
I/O GPIO/EPPI0 Frame Sync 1
PG2/PPI0_FS2/ATAPI_A0A4
I/O GPIO/EPPI0 Frame Sync 2/Alternate ATAPI Address
PG3/PPI0_D16/ATAPI_A1A4
I/O GPIO/EPPI0 Data/Alternate ATAPI Address
PG4/PPI0_D17/ATAPI_A2A4
I/O GPIO/EPPI0 Data/Alternate ATAPI Address
PG5/SPI1SEL1/HOST_CE/PPI2_FS2/ CZM
I/O GPIO/SPI1 Slave Select/Host DMA Chip Enable/EPPI2 Frame Sync 2/Counter Zero
Marker
PG6/SPI1SEL2/HOST_RD/ PPI2_FS1
I/O GPIO/SPI1 Slave Select/ Host DMA Read/EPPI2 Frame Sync 1
PG7/SPI1SEL3/HOST_WR/ PPI2_CLK
I/O GPIO/SPI1 Slave Select/Host DMA Write/EPPI2 Clock
PG8/SPI1SCK
I/O GPIO/SPI1 Clock
PG9/SPI1MISO
I/O GPIO/SPI1 Master In Slave Out
PG10/SPI1MOSI
I/O GPIO/SPI1 Master Out Slave In
PG11/SPI1SS/MTXON
I/O GPIO/SPI1 Slave Select Input/MXVR Transmit Phy On
PG12/CAN0TX
I/O GPIO/CAN0 Transmit
PG13/CAN0RX/TACI4
I/O GPIO/CAN0 Receive/Alternate Capture Input 4
PG14/CAN1TX
I/O GPIO/CAN1 Transmit
PG15/CAN1RX/TACI5
I/O GPIO/CAN1 Receive/Alternate Capture Input 5
Port H: GPIO/AMC / EXTDMA / UART1 / EPPI0–2 / ATAPI Interface / Up-Down Counter /TMR8-10/ Host DMA / MXVR (MOST)
PH0/UART1TX/PPI1_FS3_DEN
I/O GPIO/UART1 Transmit/EPPI1 Frame Sync 3
PH1/UART1RX/PPI0_FS3_DEN/TACI1
I/O GPIO/UART 1 Receive/ EPPI0 Frame Sync 3/Alternate Capture Input 1
PH2/ATAPI_RESET/TMR8/PPI2_FS3_DEN
I/O GPIO/ATAPI Interface Hard Reset Signal/Timer 8/EPPI2 Frame Sync 3
PH3/HOST_ADDR/TMR9/CDG
I/O GPIO/HOST Address/Timer 9/Count Down and Gate
PH4/HOST_ACK/TMR10/CUD
I/O GPIO/HOST Acknowledge/Timer 10/Count Up and Direction
PH5/MTX/DMAR0/TACI8 and TACLK8
I/O GPIO/MXVR Transmit Data/Ext. DMA Request/Alt Capt. In. 8 /Alt In. Clk 8
PH6/MRX/DMAR1/TACI9 and TACLK9
I/O GPIO/MXVR Receive Data/Ext. DMA Request/Alt Capt. In. 9 /Alt In. Clk 9
PH7/MRXON/TACI10 and TACLK10/HWAITA 5
I/O GPIO/MXVR Receive Phy On /Alt Capt. In. 10 /Alt In. Clk 10/Alternate Boot Host Wait
PH8/A46
I/O GPIO/Address Bus for Async Access
6
PH9/A5
I/O GPIO/Address Bus for Async Access
PH10/A66
I/O GPIO/Address Bus for Async Access
PH11/A76
I/O GPIO/Address Bus for Async Access
6
I/O GPIO/Address Bus for Async Access
PH12/A8
PH13/A96
I/O GPIO/Address Bus for Async Access
Rev. PrG
|
Page 28 of 82 |
December 2007
ADSP-BF542/4/7/8/9
Preliminary Technical Data
Table 12. Pin Descriptions (Continued)
Pin Name
Port I: GPIO / AMC
PI0/A106
PI1/A116
PI2/A126
PI3/A136
PI4/A146
PI5/A156
PI6/A166
PI7/A176
PI8/A186
PI9/A196
PI10/A206
PI11/A216
PI12/A226
PI13/A236
PI14/A246
PI15/A25/NR_CLK6
Port J: GPIO / AMC / ATAPI Controller
PJ0/ARDY/WAIT
PJ1/ND_CE7
PJ2/ND_RB
PJ3/ATAPI_DIOR
PJ4/ATAPI_DIOW
PJ5/ATAPI_CS0
PJ6/ATAPI_CS1
PJ7/ATAPI_DMACK
PJ8/ATAPI_DMARQ
PJ9/ATAPI_INTRQ
PJ10/ATAPI_IORDY
PJ11/BR8
PJ12/BG6
PJ13/BGH6
Memory Interface
DA0–12
DBA0–1
DQ0–15
DQS0–1
DQM0–1
DCLK0–1
DCLK0–1
DCS0–1
DCLKE
DRAS
DCAS
DWE
I/O1 Function (First/Second/Third/Fourth)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GPIO/Address Bus for Async Access
GPIO/Address Bus for Async Access
GPIO/Address Bus for Async Access
GPIO/Address Bus for Async Access
GPIO/Address Bus for Async Access
GPIO/Address Bus for Async Access
GPIO/Address Bus for Async Access
GPIO/Address Bus for Async Access
GPIO/Address Bus for Async Access
GPIO/Address Bus for Async Access
GPIO/Address Bus for Async Access
GPIO/Address Bus for Async Access
GPIO/Address Bus for Async Access
GPIO/Address Bus for Async Access
GPIO/Address Bus for Async Access
GPIO/Address Bus for Async Access/ NOR clock
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GPIO/Async Ready/NOR Wait
GPIO/NAND Chip Enable
GPIO/Ready Busy Signal
GPIO/ATAPI Read
GPIO/ATAPI Write
GPIO/ATAPI Chip Select Signal Command Block
GPIO/ATAPI Chip Select Signal
GPIO/ATAPI DMA Acknowledge Signal
GPIO/ATAPI DMA Request Signal
GPIO/Interrupt Request from the Device
GPIO/ATAPI Ready Handshake Signal
GPIO/Bus Request
GPIO/Bus Grant
GPIO/Bus Grant Hang
O
O
I/O
I/O
O
O
O
O
O
O
O
O
DDR Address Bus
DDR Bank Active Strobe
DDR Data Bus
DDR Data Strobe
DDR Data Mask for Reads and Writes
DDR Output Clock
DDR Complementary Output Clock
DDR Chip Selects
DDR Clock Enable
DDR Row Address Strobe
DDR Column Address Strobe
DDR Write Enable
Rev. PrG
|
Page 29 of 82 |
December 2007
ADSP-BF542/4/7/8/9
Preliminary Technical Data
Table 12. Pin Descriptions (Continued)
Pin Name
Memory Interface (Continued)
DDR_VREF
DDR_VSSR
Asynchronous Memory Interface
A1-3
D0-15/ND_D0-15/ATAPI_D0-15
AMS0–3
ABE0 /ND_CLE
ABE1/ND_ALE
AOE/NR_ADV
ARE
AWE
ATAPI Controller Pins
ATAPI_PDIAG
High Speed USB OTG Pins9
USB_DP
USB_DM
USB_XI
USB_XO
USB_ID10
USB_VBUS
USB_VREF
USB_RSET
MXVR (MOST) Interface
MFS
MLF_P
MLF_M
MXI11
MXO
Mode Control Pins
BMODE0–3
JTAG Port Pins
TDI
TDO
TRST12
TMS
TCK
EMU
Voltage Regulator
VROUT0, VROUT113
Real Time Clock
RTXO
RTXI11
I/O1 Function (First/Second/Third/Fourth)
I
I
DDR Voltage Reference
DDR Voltage Reference Shield (connect to GND)
O
I/O
O
O
O
O
O
O
Address Bus for Async and ATAPI Addresses
Data Bus for Async, NAND and ATAPI Accesses
Bank Selects
Byte Enables:Data Masks for Asynchronous Access/NAND Command Latch Enable
Byte Enables:Data Masks for Asynchronous Access/NAND Address Latch Enable
Output Enable/NOR Address Data Valid
Read Enable/NOR Output Enable
Write Enable
I
I/O
I/O
C
C
I
I/O
A
A
USB D+ pin
USB D- pin
Clock XTAL input
Clock XTAL output
USB ID pin
USB VBUS pin
USB voltage reference. Connect 0.1 ␮F capacitor between USB_VREF and GND.
USB resistance set. Preliminary designs should connect USB_RSET to an unpopulated resistor pad. Connect the other terminal of the unpopulated resistor to GND.
O
A
A
C
C
MXVR Frame Sync
MXVR Loop Filter Plus
MXVR Loop Filter Minus
MXVR Crystal Input
MXVR Crystal Output
I
Boot Mode Strap 0–3
I
O
I
I
I
O
JTAG Serial Data In
JTAG Serial Data Out
JTAG Reset
JTAG Mode Select
JTAG Clock
Emulation Output
O
External FET/BJT Drivers
C
C
RTC Crystal Output
RTC Crystal Input
Rev. PrG
|
Page 30 of 82 |
December 2007
ADSP-BF542/4/7/8/9
Preliminary Technical Data
Table 12. Pin Descriptions (Continued)
Pin Name
Clock (PLL) Pins
CLKIN
CLKOUT
XTAL
CLKBUF
EXT_WAKE
RESET
NMI14
Supplies
VDDINT
VDDEXT15
VDDDDR
VDDUSB15
VDDRTC
VDDVR16
GND
VDDMP15
GNDMP17, 18
I/O1 Function (First/Second/Third/Fourth)
C
O
C
O
O
I
I
Clock/Crystal Input
Clock Output
Crystal Output
Buffered Oscillator output
External Wakeup from hibernate output
Reset
Non-maskable Interrupt
P
P
P
P
P
P
G
P
G
Internal Power Supply
External Power Supply
External DDR Power Supply
External USB Power Supply
RTC Clock Supply
Internal Voltage Regulator Power Supply
Ground
MXVR PLL Power Supply
MXVR PLL Ground
1
I = Input, O = Output, P =Power, G = Ground, C = Crystal, A = Analog.
To use the SPI memory boot, SCLK0 should have a pulldown, MISO should have a pullup, and SPISEL1 is used as CS with a pullup.
3
To use the serial TWI memory boot, SDA0 and SCL0 should have a pullup.
4
By default the ATAPI bus shares the data pins D0-15 and the address pins A0-2 with the asynchronous memory interface and the NAND controller. When PORTF_MUX[1:0]
= b#01, then the ATAPI data bus is available through Port F and the address line can be found at Port G.
5
The Boot Host Wait (HWAIT) signal on PB11 is a GPIO output that is driven and toggled by the boot kernel at boot time. An external pulling resistor is required for proper
operation. A pull-up resistor instructs the HWAIT signal to behave active high (low when ready for data). A pull-down resistor instructs the HWAIT signal to behave active
low (high when ready for data). After boot it can be used for other purposes. If the PB11 pin is required for other purposes (for example, timer or SPI operation) the Alternate
Boot Host Wait (HWAITA) on PH7 can be used instead. This is enabled by programming the OTP_ALTERNATE_HWAIT bit in the PBS00L OTP memory page.
6
This pin should not be used as GPIO if booting in mode 1.
7
This pin should always be enabled as ND_CE in software and pulled HIGH with a resistor when using NAND flash.
8
This pin should always be enabled as bus request in software and pulled HIGH to enable the Async access.
9
For the ADSP-BF542/4/7/8/9, the unused USB pins should be terminated as follows: USB_DP --> GND; USB_DM -->GND; USB_XTALIN --> GND; USB_XTALOUT -->
NC (No Connect); USB_ID --> VSS; USB_VREF --> NC; USB_RSET --> NC; USB_VBUS --> VSS; VDDUSB --> VDDEXT
10
In the case that USB is used in device mode only, the USB_ID pin should be either pulled HIGH or left unconnected.
11
This pin should always be pulled either HIGH or LOW, but must not be left floating.
12
This pin should be pulled LOW if the JTAG port will not be used.
13
Always connect VROUT0 and VROUT1 together to reduce signal impedance.
14
This pin should always be pulled HIGH when not used.
15
Power and ground pins of peripherals should be driven to their specified level even if the associated peripheral is not used in the application.
16
The VDDVR pin must always be connected. If the internal voltage regulator is not being used, this pin may be connected to VDDEXT. Otherwise it should be powered
according to the VDDVR specification.
17
Analog ground for MXVR.
18
Connect to GND when MXVR is not used.
2
Rev. PrG
|
Page 31 of 82 |
December 2007
ADSP-BF542/4/7/8/9
Preliminary Technical Data
SPECIFICATIONS
Note that component specifications are subject to change
without notice.
OPERATING CONDITIONS
Parameter1
VDDINT2
VDDEXT3,4
VDDUSB4
VDDMP5
VDDRTC4
VDDDDR4
VDDVR6
VIH
VIHCLKIN
VIHDDR
VIH5V
VIHUSB
VIL
VIL5V
VILDDR
VREFDDR
TJ15
TJ15
Internal Supply Voltage
Internal Supply Voltage for Automotive Grade
External Supply Voltage for 3.3V I/O
External Supply Voltage for 2.5V I/O7
External Supply Voltage for Automotive Grade
USB External Supply Voltage
MXVR PLL Supply Voltage
MXVR PLL Supply Voltage for Automotive Grade
Real Time Clock Power Supply Voltage
Real Time Clock Power Supply Voltage for Automotive Grade
DDR Memory Supply Voltage
DDR Memory Supply Voltage for Mobile DDR
Internal Voltage Regulator Supply Voltage
High Level Input Voltage for 3.3V I/O7,8 @ VDDEXT =maximum
High Level Input Voltage for 2.5V I/O7,8 @ VDDEXT =maximum
High Level Input Voltage for 3.3V I/O9 @ VDDEXT =maximum
High Level Input Voltage for 2.5V I/O9 @ VDDEXT =maximum
High Level Input Voltage10
High Level Input Voltage for Mobile DDR10
High Level Input Voltage for 3.3V I/O11, @ VDDEXT =maximum
High Level Input Voltage for 2.5V I/O11, @ VDDEXT =maximum
High Level Input Voltage for USB_DP, USB_DM, and USB_VBUS12
Low Level Input Voltage for 3.3V I/O7, 13, @ VDDEXT =minimum
Low Level Input Voltage for 2.5V I/O7, 13 @ VDDEXT =minimum
Low Level Input Voltage for 3.3V I/O14, @ VDDEXT =minimum
Low Level Input Voltage for 2.5V I/O14 @ VDDEXT =minimum
Low Level Input Voltage10
Low Level Input Voltage for Mobile DDR10
DDR VREF Pin Input Voltage
Junction Temperature @TAMBIENT = –40ºC to +85ºC
Junction Temperature @TAMBIENT = 0ºC to +70ºC
1
Minimum
0.9
1.0
2.7
2.25
2.7
3.0
0.9
1.0
2.25
2.7
2.3
1.7
2.7
2.0
TBD
2.2
TBD
VREFDDR + 0.15
0.8 x VDDDDR
2.0
TBD
Nominal
3.3
2.5
3.3
3.3
3.3
2.5
1.8
3.3
–0.3
–0.3
–0.3
–0.3
–0.3
-0.3
0.49 x VDDDDR 0.50 x VDDDDR
–40
0
Maximum
1.43
1.38
3.6
2.75
3.6
3.6
1.43
1.38
3.6
3.6
2.7
1.9
3.6
3.6
3.6
3.6
3.6
VDDDDR + 0.3
VDDDDR + 0.3
5.5
5.5
5.5
0.6
TBD
0.8
TBD
VREFDDR - 0.15
0.2 x VDDDDR
0.51 x VDDDDR
+105
+90
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
ºC
ºC
Specifications subject to change without notice.
VDDINT maximum is 1.10 V during One-Time-Programmable (OTP) memory programming operations. VDDINT maximum is per the operating conditions table for OTP
memory read operations.
3
VDDEXT is 3.0 V min and 3.6 V max during OTP memory programming operations. VDDEXT is specified per the operating conditions table for OTP memory read operations.
4
Must remain powered (even if associated function not used).
5
Connect to VDDINT if MXVR is not used.
6
VDDVR must always be connected. If the internal voltage regulator is not being used, this pin may be connected to VDDEXT. Otherwise it should be powered according to
this specification.
7
The ADSP-BF542/4/7/8/9 processor is 3.3 V tolerant (always accepts up to 3.6 V maximum VIH), but voltage compliance (on outputs, VOH) depends on the input VDDEXT,
because VOH (maximum) approximately equals VDDEXT (maximum). This 3.3 V tolerance applies to bi-directional pins (D15–0, PA15–0, PB14–0, PC15–0, PD15–0, PE15–0,
PF15–0, PG15–0, PH13–0, PI15–0, PJ14–0) and input only pins (ATAPI_PDIAG, USB_ID, TCK, TDI, TMS, TRST, CLKIN, RESET, NMI, and BMODE3–0).
8
Parameter value applies to all input and bi-directional pins, except CLKIN, PB0, PB1, PE14, PE15, PG15–11, PH6, PH7, and the pins listed in table note 10 of the Operating
Conditions table.
2
Rev. PrG
|
Page 32 of 82 |
December 2007
ADSP-BF542/4/7/8/9
Preliminary Technical Data
9
Parameter value applies to CLKIN pin only.
Parameter value applies to DA0–12, DBA0–1, DQ0–15, DQS0–1, DQM0–1, DCLK1–2, DCLK1–2, DCS0–1, DCLKE, DRAS, DCAS, and DWE pins only.
11
Certain ADSP-BF542/4/7/8/9 processor pins are 5.0 V tolerant (accept up to 5.5 V maximum VIH when power is applied to VDDEXT pins). Voltage compliance on outputs
(VOH) depends on the input VDDEXT, because VOH (maximum) approximately equals VDDEXT (maximum). The 5.0 V tolerance feature applies to PB0, PB1, PE14, PE15, PG15–11,
PH6, and PH7 pins only. The 5.0 V tolerance exists only when power is applied to the VDDEXT pins. The PB0, PB1, PE14, and PE15 pins are open drain (regardless of pin
functionality) and therefore require a pullup resistor. Consult the I2C specification version 2.1 for the proper resistor value and other open drain pin electrical parameters.
12
See Absolute Maximum Ratings.
13
Parameter value applies to all input and bi-directional pins, except PB0, PB1, PE14, PE15, PG15–11, PH6, and PH7.
14
Parameter value applies to the following pins only: PB0, PB1, PE14, PE15, PG15–11, PH6, and PH7.
15
Tj must meet the following conditions during OTP memory programming operations: 0⬚C < Tj < 55⬚C. During OTP memory read operations, Tj should meet the conditions
specified in the operating conditions table.
10
Rev. PrG
|
Page 33 of 82 |
December 2007
ADSP-BF542/4/7/8/9
Preliminary Technical Data
ELECTRICAL CHARACTERISTICS
Parameter
VOH
High Level Output Voltage for 3.3V
I/O1
High Level Output Voltage for 2.5V
I/O1
VOHDDR
High Level Output Voltage2
High Level Output Voltage for
Mobile DDR2
VOL
Low Level Output Voltage for 3.3V
I/O1
Low Level Output Voltage for 2.5V
I/O1
VOLDDR
Low Level Output Voltage2
Low Level Output Voltage for
Mobile DDR2
IIH
High Level Input Current3
High Level Input Current JTAG4
IIHP
5
IIL
Low Level Input Current3
5
IILP
Low Level Input Current JTAG4
IOZH6
Three-State Leakage Current7
5
IOZL
Three-State Leakage Current7
CIN
Input Capacitance8
TBD
IDDHIBERNATE
IDDDEEPSLEEP
TBD
IDDSLEEP
TBD
IDDTYP
TBD
IDDRTC
TBD
Test Conditions
@ VDDEXT = 2.7V, IOH = –0.5 mA
Min
2.4
Typical
Max
Unit
V
@ VDDEXT = 2.25V, IOH = -0.5 mA
TBD
V
@ VDDDDR = 2.3V, IOH = -8.1 mA
@ VDDDDR = 1.7V, IOH = -8.1 mA
1.74
TBD
V
V
@ VDDEXT = 2.7V, IOL = 2.0 mA
0.4
V
@ VDDEXT = 2.25V, IOL = 2.0 mA
TBD
V
@ VDDDDR = 2.3V, IOL = 8.1 mA
@ VDDDDR = 1.7V, IOL = 8.1 mA
0.56
TBD
V
V
@ VDDEXT = 3.6V, VIN = VIH Maximum
@ VDDEXT = 3.6V, VIN = VIH Maximum
@ VDDEXT = 3.6V, VIN = 0 V
@ VDDEXT = 3.6V, VIN = 0 V
@ VDDEXT = 3.6V, VIN = VIH Maximum
@ VDDEXT = 3.6V, VIN = 0 V
fIN = TBD MHz, TAMBIENT = TBD°C, VIN = TBD V
TBD
TBD
TBD
TBD
TBD
10.0
50.0
10.0
TBD
10.0
10.0
88
μA
μA
μA
μA
μA
μA
pF
μA
mA
mA
mA
μA
1
Applies to output and bidirectional pins, except the pins listed in table note 10 of the Operating Conditions table.
Applies to output and bidirectional pins listed in table note 10 of the Operating Conditions table.
3
Applies to input pins except JTAG inputs.
4
Applies to JTAG input pins (TCK, TDI, TMS, TRST).
5
Absolute value.
6
For DDR pins (DQ0-15, DQS0-1), test conditions are VDDDDR = Maximum, VIN = VDDDDR Maximum.
7
Applies to three-statable pins.
8
Guaranteed, but not tested.
2
ESD SENSITIVITY
ESD (electrostatic discharge) sensitive device.
Charged devices and circuit boards can discharge
without detection. Although this product features
patented or proprietary circuitry, damage may occur
on devices subjected to high energy ESD. Therefore,
proper ESD precautions should be taken to avoid
performance degradation or loss of functionality.
Rev. PrG
|
Page 34 of 82 |
December 2007
48
TBD
TBD
TBD
TBD
TBD
ADSP-BF542/4/7/8/9
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
Internal (Core) Supply Voltage1 (VDDINT)
External (I/O) Supply Voltage1 (VDDEXT)
Input Voltage1,2, 3
Output Voltage Swing1
Load Capacitance1
Storage Temperature Range1
Junction Temperature Underbias1
–0.3 V to +1.43 V
–0.3 V to +3.8 V
–0.5 V to +3.6 V
–0.5 V to VDDEXT +0.5 V
200 pF
–65ºC to +150ºC
+125ºC
1
Stresses greater than those listed above may cause permanent damage to the
device. These are stress ratings only. Functional operation of the device at these
or any other conditions greater than those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Applies to all bidirectional and input only pins except PB0, PB1, PE14, PE15,
PG15–11, PH6, and PH7. Absolute maximum input voltage range on pins PB0,
PB1, PE14, PE15, PG15–11, PH6, and PH7 is –0.5 V to +5.5 V.
3
Pins USB_DP, USB_DM, and USB_VBUS are 5 V tolerant when VDDUSB is
powered according to the operating conditions table. If VDDUSB supply
voltage does not meet the specification in the operating conditions table, these
pins could suffer long term damage when driven to +5V. If this condition is
seen in the application, it can be corrected with additional circuitry to use the
external host to power only the VDDUSB pins. Contact factory for application
detail and reliability information.
Table 13. Maximum Duty Cycle for Input1 Transient Voltage
VIN Max (V)
3.63
3.80
3.90
4.00
4.10
4.20
4.30
1
VIN Min (V)
–0.33
–0.50
–0.60
–0.70
–0.80
–0.90
–1.00
Maximum Duty Cycle
100%
48%
30%
20%
10%
8%
5%
Does not apply to CLKIN. Absolute maximum for pins PBO, PB1, PE14, PE15,
PG15-11, PH6, AND PH7 is +5.5V.
PACKAGE INFORMATION
The information presented in Figure 8 and Table 14 provides
information about how to read the package brand and relate it
to specific product features. For a complete listing of product
offerings, see the Ordering Guide on Page 82.
Table 14. Package Information
a
ADSP-BF54x
tppZ-cc
Brand Key
t
pp
Z
cc
vvvvvv.x-q
n.n
yyww
vvvvvv.x-q n.n
yyww country_of_origin
B
Figure 8. Product Information on Package
Rev. PrG
|
Page 35 of 82 |
December 2007
Description
Temperature Range
Package Type
RoHS Compliant part
See Ordering Guide
Assembly Lot Code
Silicon Revision
Date Code
ADSP-BF542/4/7/8/9
Preliminary Technical Data
TIMING SPECIFICATIONS
Table 15, Table 16, Table 17, and Table 18 describe the timing
requirements for the ADSP-BF542/4/7/8/9 processor clocks.
Take care in selecting MSEL, SSEL, and CSEL ratios so as not to
exceed the maximum core clock and system clock. Table 19
describes phase-locked loop operating conditions. Table 20 and
Figure 9 describe Clock Input and Reset Timing. Table 21
describes Clock Out Timing.
Clock Signals
Table 15. System Clock Requirements
Parameter
fSCLK
fSCLK
fSCLK
fSCLK
tSCLKH
tSCLKL
Condition
VDDEXT = 3.3 V, VDDINT ≥ TBD
VDDEXT = 3.3 V, VDDINT < TBD
VDDEXT = 2.5 V, VDDINT ≥ TBD
VDDEXT = 2.5 V, VDDINT < TBD
CLKOUT Width High
CLKOUT Width Low
Minimum
Maximum
133
100
133
100
Unit
MHz
MHz
MHz
MHz
ns
ns
Maximum
600
TBD
TBD
TBD
TBD
Unit
MHz
MHz
MHz
MHz
MHz
2.5
2.5
Table 16. Core Clock Requirements—600 MHz Speed Grade1
Parameter
fCCLK
fCCLK
fCCLK
fCCLK
fCCLK
1
Minimum
Core Clock Frequency (VDDINT =TBD V minimum)
Core Clock Frequency (VDDINT =TBD V minimum)
Core Clock Frequency (VDDINT =TBD V minimum)
Core Clock Frequency (VDDINT =TBD V minimum)
Core Clock Frequency (VDDINT =TBD V )
The speed grade of a given part may be seen on the Ordering Guide on Page 82. It stands for the maximum allowed CCLK frequency at VDDINT = minimum and the maximum
allowed VCO frequency at any supply voltage.
Table 17. Core Clock Requirements—533 MHz Speed Grade1
Parameter
fCCLK
fCCLK
fCCLK
fCCLK
fCCLK
1
Minimum
Core Clock Frequency (VDDINT =1.188 V minimum)
Core Clock Frequency (VDDINT =TBD V minimum)
Core Clock Frequency (VDDINT =TBD V minimum)
Core Clock Frequency (VDDINT =TBD V minimum)
Core Clock Frequency (VDDINT =TBD V )
Maximum
533
TBD
TBD
TBD
TBD
Unit
MHz
MHz
MHz
MHz
MHz
The speed grade of a given part may be seen on the Ordering Guide on Page 82. It stands for the maximum allowed CCLK frequency at VDDINT = minimum and the maximum
allowed VCO frequency at any supply voltage.
Table 18. Core Clock Requirements—400 MHz Speed Grade1
Parameter
fCCLK
fCCLK
fCCLK
fCCLK
fCCLK
1
Minimum
Core Clock Frequency (VDDINT =TBD V minimum)
Core Clock Frequency (VDDINT =TBD V minimum)
Core Clock Frequency (VDDINT = TBD V minimum)
Core Clock Frequency (VDDINT =TBD V minimum)
Core Clock Frequency (VDDINT =TBD V )
Maximum
400
TBD
TBD
TBD
TBD
Unit
MHz
MHz
MHz
MHz
MHz
The speed grade of a given part may be seen on the Ordering Guide on Page 82. It stands for the maximum allowed CCLK frequency at VDDINT = minimum and the maximum
allowed VCO frequency at any supply voltage.
Rev. PrG
|
Page 36 of 82 |
December 2007
ADSP-BF542/4/7/8/9
Preliminary Technical Data
Table 19. Phase-Locked Loop Operating Conditions
Parameter
fVCO
1
Minimum
50
Voltage Controlled Oscillator (VCO) Frequency
Maximum Unit
Speed Grade1 MHz
The speed grade of a given part may be seen on the “Ordering Guide” on page 82. It stands for the Maximum allowed CCLK frequency at VDDINT = minimum and the maximum
allowed VCO frequency at any supply voltage.
Table 20. Clock Input and Reset Timing
Parameter
Timing Requirements
tCKIN
CLKIN Period1,2,3,4
tCKINL
CLKIN Low Pulse2
CLKIN High Pulse2
tCKINH
tBUFDLAY
CLKIN to CLKBUF Delay
tWRST
RESET Asserted Pulsewidth Low5
tRHWFT
RESET High to First HWAIT/HWAITA transition (Boot Host Wait Mode)6
tRHWFT
RESET High to First HWAIT/HWAITA transition (Reset Output Mode)7
Minimum
Maximum
Unit
20.0
8.0
8.0
100.0
ns
ns
ns
ns
ns
ns
ns
10
11 tCKIN
TBD tCKIN
TBD tCKIN
1
TBD tCKIN
Combinations of the CLKIN frequency and the PLL clock multiplier must not exceed the allowed fVCO, fCCLK, and fSCLK settings discussed in the previous Clock tables.
2
Applies to PLL bypass mode and PLL nonbypass mode.
3
CLKIN frequency and duty cycle must not change on the fly.
4
If the DF bit in the PLL_CTL register is set, then the maximum tCKIN period is 50 ns.
5
Applies after power-up sequence is complete. At power-up, the processor’s internal phase locked loop requires no more than 2000 CLKIN cycles, while RESET is asserted,
assuming stable power supplies and CLKIN (not including startup time of external clock oscillator).
6
Maximum value varies with OTP memory programming and boot mode.
7
When enabled by OTP_RESETOUT_HWAIT bit. If regular HWAIT is not required in an application, the OTP_RESETOUT_HWAIT bit in the same page instructs the
HWAIT or HWAITA to simulate Reset Output functionality. Then an external resistor is expected to pull the signal to the reset level, as the pin itself is in high-performance
mode during reset.
t CKIN
CLKIN
t CKINL
t CKINH
t BUFDLAY
CLKBUF
t WRST
RESET
t RHWFT
HWAIT(A)
Figure 9. Clock and Reset Timing
Rev. PrG
|
Page 37 of 82 |
December 2007
t
BUFDLAY
ADSP-BF542/4/7/8/9
Preliminary Technical Data
Table 21. Clock Out Timing
Parameter
Switching Characteristics
tSCLK
CLKOUT Period1
tSCLKH
CLKOUT Width High
tSCLKL
CLKOUT Width Low
1
Min
TBD
TBD
TBD
The tSCLK value is the inverse of the fSCLK specification. Reduced supply voltages affect the best-case value of TBD ns listed here.
tSCLK
t SCLKH
CLKOUT
t SCLKL
Figure 10. CLKOUT Interface Timing
Rev. PrG
|
Page 38 of 82 |
December 2007
Max
Unit
ns
ns
ns
ADSP-BF542/4/7/8/9
Preliminary Technical Data
Asynchronous Memory Read Cycle Timing
Table 22 and Table 23 on Page 40 and Figure 11 and Figure 12
on Page 40 describe asynchronous memory read cycle operations for synchronous and for asynchronous ARDY.
Table 22. Asynchronous Memory Read Cycle Timing with Synchronous ARDY
Parameter
Min
Max
Unit
Timing Requirements
tSDAT
DATA15–0 Setup Before CLKOUT
2.1
ns
ns
tHDAT
DATA15–0 Hold After CLKOUT
0.8
tSARDY
ARDY Setup Before the Falling Edge of CLKOUT
4.0
ns
tHARDY
ARDY Hold After the Falling Edge of CLKOUT
0.0
ns
tDO
Output Delay After CLKOUT1
tHO
1
Output Hold After CLKOUT
6.0
1
0.8
ns
ns
Output pins include AMS3–0, ABE1–0, ADDR19–1, AOE, ARE.
SETUP
2 CYCLES
PROGRAMMED READ ACCESS
4 CYCLES
HOLD
1 CYCLE
ACCESS EXTENDED
3 CYCLES
CLKOUT
tDO
tHO
AMSx
ABE1–0
BE, ADDRESS
ADDR19–1
AOE
tDO
tHO
ARE
tHARDY
tSARDY
tHARDY
ARDY
tSARDY
tSDAT
tHDAT
DATA15–0
READ
Figure 11. Asynchronous Memory Read Cycle Timing with Synchronous ARDY
Rev. PrG
|
Page 39 of 82 |
December 2007
ADSP-BF542/4/7/8/9
Preliminary Technical Data
Table 23. Asynchronous Memory Read Cycle Timing with Asynchronous ARDY
Parameter
Min
Max
Unit
Timing Requirements
tSDAT
DATA15–0 Setup Before CLKOUT
2.1
0.8
tHDAT
DATA15–0 Hold After CLKOUT
tDANR
ARDY Negated Delay from AMSx Asserted1
tHAA
ARDY Asserted Hold After ARE Negated
tDO
Output Delay After CLKOUT2
tHO
Output Hold After CLKOUT2
ns
ns
(S+RA–2)*tSCLK ns
0.0
ns
6.0
0.8
ns
1
S = number of programmed setup cycles, RA = number of programmed read access cycles.
2
Output pins include AMS3–0, ABE1–0, ADDR19–1, AOE, ARE.
SETUP
2 CYCLES
PROGRAMMED READ ACCESS
4 CYCLES
HOLD
1 CYCLE
ACCESS EXTENDED
CLKOUT
tDO
tHO
AMSx
ABE1–0
BE, ADDRESS
ADDR19–1
AOE
tDO
tHO
ARE
tHAA
tDANR
ARDY
tSDAT
tHDAT
DATA15–0
READ
Figure 12. Asynchronous Memory Read Cycle Timing with Asynchronous ARDY
Rev. PrG
|
Page 40 of 82 |
December 2007
ns
ADSP-BF542/4/7/8/9
Preliminary Technical Data
Asynchronous Memory Write Cycle Timing
Table 24 and Table 25 on Page 42 and Figure 13 and Figure 14
on Page 42 describe asynchronous memory write cycle operations for synchronous and for asynchronous ARDY.
Table 24. Asynchronous Memory Write Cycle Timing with Synchronous ARDY
Parameter
Min
Max
Unit
Timing Requirements
tSARDY
ARDY Setup Before the Falling Edge of CLKOUT
4.0
ns
tHARDY
ARDY Hold After the Falling Edge of CLKOUT
0.0
ns
Switching Characteristics
tDDAT
DATA15–0 Disable After CLKOUT
tENDAT
DATA15–0 Enable After CLKOUT
tDO
Output Delay After CLKOUT
tHO
Output Hold After CLKOUT1
1
6.0
1.0
1
Output pins include AMS3–0, ABE1–0, ADDR19–1, DATA15–0, AOE, AWE.
SETUP
2 CYCLES
ACCESS
EXTENDED
1 CYCLE
PROGRAMMED WRITE
ACCESS 2 CYCLES
HOLD
1 CYCLE
CLKOUT
t DO
t HO
AMSx
ABE1–0
BE, ADDRESS
ADDR19–1
tDO
tHO
AWE
t SARDY
ARDY
t SARDY
t HARDY
t END AT
DATA15–0
ns
6.0
0.8
t HARDY
t DDAT
WRITE DATA
Figure 13. Asynchronous Memory Write Cycle Timing with Synchronous ARDY
Rev. PrG
|
Page 41 of 82 |
December 2007
ns
ns
ns
ADSP-BF542/4/7/8/9
Preliminary Technical Data
Table 25. Asynchronous Memory Write Cycle Timing with Asynchronous ARDY
Parameter
Min
Max
Unit
Timing Requirements
tDANR
ARDY Negated Delay from AMSx Asserted1
tHAA
ARDY Asserted Hold After ARE Negated
(S+WA–2)*tSCLK ns
0.0
ns
Switching Characteristics
tDDAT
DATA15–0 Disable After CLKOUT
tENDAT
DATA15–0 Enable After CLKOUT
tDO
Output Delay After CLKOUT
tHO
Output Hold After CLKOUT2
1
2
6.0
1.0
2
S = number of programmed setup cycles, WA = number of programmed write access cycles.
Output pins include AMS3–0, ABE1–0, ADDR19–1, DATA15–0, AOE, AWE.
SETUP
2 CYCLES
PROGRAMMED WRITE
ACCESS 2 CYCLES
ACCESS
EXTENDED
HOLD
1 CYCLE
CLKOUT
t DO
t HO
AMSx
ABE1–0
BE, ADDRESS
ADDR19–1
tDO
tHO
AWE
tDANW
tHAA
ARDY
t ENDAT
DATA15–0
ns
6.0
0.8
WRITE DATA
Figure 14. Asynchronous Memory Write Cycle Timing with Asynchronous ARDY
Rev. PrG
|
Page 42 of 82 |
December 2007
ns
ns
ns
ADSP-BF542/4/7/8/9
Preliminary Technical Data
DDR SDRAM Read Cycle Timing
Table 26. DDR SDRAM Read Cycle Timing, VDDDDR nominal 2.5V
Parameter
Timing Requirements
Access window of DQ to CK
Access window of DQS to CK
DQS-DQ skew, DQS to last DQ
valid
DQ-DQS hold, DQS to first DQ to
go invalid
DQS Read preamble
DQS Read postamble
Switching Characteristic
Clock Period
Address and Control output
SETUP time relative to clock, CK
Address and Control output
HOLD time relative to clock, CK
TBD
Symbol
Minimum
Maximum
Unit
tAC
tDQSCK
tDQSQ
TBD
TBD
TBD
TBD
0.90
ns
ns
ns
tQH
2.50
ns
tRPRE
tRPST
TBD
TBD
tCK
tCK
tCK
tAS
7.50
TBD
ns
ns
tAH
TBD
ns
TBD
TBD
ns
Mobile DDR SDRAM Read Cycle Timing
Table 27. Mobile DDR SDRAM Read Cycle Timing, VDDDDR nominal 1.8 V
Parameter
Timing Requirements
Access window of DQ to CK
Access window of DQS to CK
DQS-DQ skew, DQS to last DQ
valid
DQ-DQS hold, DQS to first DQ to
go invalid
DQS Read preamble
DQS Read postamble
Switching Characteristic
Clock Period
Address and Control output
SETUP time relative to clock, CK
Address and Control output
HOLD time relative to clock, CK
TBD
Symbol
Minimum
Maximum
Unit
tAC
tDQSCK
tDQSQ
TBD
TBD
TBD
ns
ns
ns
tQH
TBD
ns
tRPRE
tRPST
TBD
TBD
tCK
tCK
tCK
tAS
TBD
TBD
ns
ns
tAH
TBD
ns
TBD
TBD
TBD
Rev. PrG
|
Page 43 of 82 |
December 2007
ns
ADSP-BF542/4/7/8/9
Preliminary Technical Data
tDQSCK (MAX)
tDQSCK (Min)
CK
tAC (MIN)
tAC (MAX)
tRPST
tRPRE
DQS
DQ15-0
tDQSQ
tDQSQ
tQH
tQH
Figure 15. DDR SDRAM Controller Input AC Timing
Rev. PrG
|
Page 44 of 82 |
December 2007
ADSP-BF542/4/7/8/9
Preliminary Technical Data
DDR SDRAM Write Cycle Timing
Table 28. DDR SDRAM Write Cycle Timing, VDDDDR nominal 2.5V
Parameter
Switching Characteristics
Clock Period
Write cmd to first DQS
DQ/DQM setup to DQS
DQ/DQM hold to DQS
DQS falling to CK rising (DQS
setup)
DQS falling to CK rising (DQS
hold)
DQS Hi pulse width
DQS Lo pulse width
DQS Write preamble
DQS Write postamble
Address and Control output
SETUP time relative to clock, CK
Address and Control output
HOLD time relative to clock, CK
TBD
Symbol
Minimum
tCK
tDQSS
tDS
tDH
tDSS
7.50
TBD
0.90
0.90
TBD
tDSH
TBD
tCK
tDQSH
tDQSL
tWPRE
tWPST
tAS
TBD
TBD
TBD
TBD
TBD
tCK
tCK
tCK
tCK
ns
tAH
TBD
ns
TBD
Maximum
TBD
Unit
ns
tCK
ns
ns
tCK
TBD
ns
Maximum
Unit
Mobile DDR SDRAM Write Cycle Timing
Table 29. Mobile DDR SDRAM Write Cycle Timing, VDDDDR nominal 1.8V
Parameter
Switching Characteristics
Clock Period
Write cmd to first DQS
DQ/DQM setup to DQS
DQ/DQM hold to DQS
DQS falling to CK rising (DQS
setup)
DQS falling to CK rising (DQS
hold)
DQS Hi pulse width
DQS Lo pulse width
DQS Write preamble
DQS Write postamble
Address and Control output
SETUP time relative to clock, CK
Address and Control output
HOLD time relative to clock, CK
TBD
Symbol
Minimum
tCK
tDQSS
tDS
tDH
tDSS
TBD
TBD
TBD
TBD
TBD
tDSH
TBD
tCK
tDQSH
tDQSL
tWPRE
tWPST
tAS
TBD
TBD
TBD
TBD
TBD
tCK
tCK
tCK
tCK
ns
tAH
TBD
ns
TBD
TBD
TBD
Rev. PrG
|
Page 45 of 82 |
December 2007
ns
tCK
ns
ns
tCK
ns
ADSP-BF542/4/7/8/9
Preliminary Technical Data
tCK
CK
tDSH
tDQSS
tDSS
DQS
tDQSL
tWPRE
DQ/DM
tAS
tAH
tDS
tDH
ADDR
CTL
Figure 16. DDR SDRAM Controller Output AC Timing
Rev. PrG
|
Page 46 of 82 |
December 2007
tDQSH
tWPST
ADSP-BF542/4/7/8/9
Preliminary Technical Data
External Port Bus Request and Grant Cycle Timing
Table 30 and Table 31 on Page 48 and Figure 17 and Figure 18
on Page 48 describe external port bus request and grant cycle
operations for synchronous and for asynchronous BR.
Table 30. External Port Bus Request and Grant Cycle Timing with Synchronous BR
Parameter
Min
Max
Unit
Timing Requirements
tBS
BR Setup to Falling Edge of CLKOUT
4.0
ns
tBH
Falling Edge of CLKOUT to BR Deasserted Hold Time
0.0
ns
Switching Characteristics
tSD
CLKOUT Low to xMS, Address, and RD/WR disable
4.5
ns
tSE
CLKOUT Low to AMSx, Address, and ARE/AWE enable
4.5
ns
tDBG
CLKOUT High to BG High Setup
3.6
ns
tEBG
CLKOUT High to BG Deasserted Hold Time
3.6
ns
tDBH
CLKOUT High to BGH High Setup
3.6
ns
tEBH
CLKOUT High to BGH Deasserted Hold Time
3.6
ns
CLKOUT
tBS
tBH
BR
tSD
tSE
AMSx
tSD
ADDR19-1
ABE1-0
tSE
tSD
tSE
AWE
ARE
tDBG
tEBG
BG
tDBH
BGH
Figure 17. External Port Bus Request and Grant Cycle Timing with Synchronous BR
Rev. PrG
|
Page 47 of 82 |
December 2007
tEBH
ADSP-BF542/4/7/8/9
Preliminary Technical Data
Table 31. External Port Bus Request and Grant Cycle Timing with Asynchronous BR
Parameter
Min
Max
Unit
Timing Requirements
tWBR
BR Pulsewidth
2 x tSCLK
ns
Switching Characteristics
tSD
CLKOUT Low to xMS, Address, and RD/WR disable
4.5
ns
tSE
CLKOUT Low to AMSx, Address, and ARE/AWE enable
4.5
ns
tDBG
CLKOUT High to BG High Setup
3.6
ns
tEBG
CLKOUT High to BG Deasserted Hold Time
3.6
ns
tDBH
CLKOUT High to BGH High Setup
3.6
ns
tEBH
CLKOUT High to BGH Deasserted Hold Time
3.6
ns
CLKOUT
tWBR
BR
tSD
tSE
AMSx
tSD
ADDR19-1
ABE1-0
tSE
tSD
tSE
AWE
ARE
tDBG
tEBG
BG
tDBH
BGH
Figure 18. External Port Bus Request and Grant Cycle Timing with Asynchronous BR
Rev. PrG
|
Page 48 of 82 |
December 2007
tEBH
ADSP-BF542/4/7/8/9
Preliminary Technical Data
Enhanced Parallel Peripheral Interface Timing
Table 32 and Figure 19 on Page 49 describes Enhanced Parallel
Peripheral Interface operations.
Table 32. Enhanced Parallel Peripheral Interface Timing
Parameter
Timing Requirements
tPCLKW
PPI_CLK Width
tPCLK
PPI_CLK Period
Timing Requirements - GP Input and Frame Capture Modes
tSFSPE
External Frame Sync Setup Before PPI_CLK
External Frame Sync Hold After PPI_CLK
tHFSPE
tSDRPE
Receive Data Setup Before PPI_CLK
tHDRPE
Receive Data Hold After PPI_CLK
Switching Characteristics - GP Output and Frame Capture Modes
tDFSPE
Internal Frame Sync Delay After PPI_CLK
tHOFSPE
Internal Frame Sync Hold After PPI_CLK
Transmit Data Delay After PPI_CLK
tDDTPE
tHDTPE
Transmit Data Hold After PPI_CLK
h
Perip
l
e
l
l
a
ar
ced P
n
a
h
En
Minimum
|
ns
ns
TBD
TBD
TBD
TBD
ns
ns
ns
ns
TBD
TBD
TBD
era
is
iming
T
e
rfac
l Inte
Page 49 of 82 |
December 2007
Unit
TBD
TBD
TBD
Figure 19. Enhanced Parallel Peripheral Interface Timing
Rev. PrG
Maximum
TB D
ns
ns
ns
ns
ADSP-BF542/4/7/8/9
Preliminary Technical Data
Serial Ports Timing
Table 33 through Table 36 on Page 51 and Figure 20 on Page 52
through Figure 22 on Page 54 describe Serial Port operations.
Table 33. Serial Ports—External Clock
Parameter
Min
Max
Unit
Timing Requirements
tSFSE
TFS/RFS Setup Before TSCLK/RSCLK (externally generated TFS/RFS)1
tHFSE
TFS/RFS Hold After TSCLK/RSCLK (externally generated TFS/RFS)
tSDRE
Receive Data Setup Before RSCLK1
1
1
3.0
ns
3.0
ns
3.0
ns
tHDRE
Receive Data Hold After RSCLK
3.0
ns
tSCLKEW
TSCLK/RSCLK Width
4.5
ns
tSCLKE
TSCLK/RSCLK Period
15.0
ns
tRCLKE
RSCLK Period2
11.1
ns
Switching Characteristics
tDFSE
TFS/RFS Delay After TSCLK/RSCLK (Internally Generated TFS/RFS)3
tHOFSE
TFS/RFS Hold After TSCLK/RSCLK (Internally Generated TFS/RFS
tDDTE
Transmit Data Delay After TSCLK3
tHDTE
Transmit Data Hold After TSCLK
3
10.0
0.0
ns
10.0
3
ns
0.0
ns
ns
1
Referenced to sample edge.
For serial port receive with external clock and external frame sync only.
3
Referenced to drive edge.
2
Table 34. Serial Ports—Internal Clock
Parameter
Min
Max
Unit
Timing Requirements
tSFSI
TFS/RFS Setup Before TSCLK/RSCLK (externally generated TFS/RFS)1
8.0
ns
tHFSI
TFS/RFS Hold After TSCLK/RSCLK (externally generated TFS/RFS)1
–1.5
ns
tSDRI
Receive Data Setup Before RSCLK1
8.0
ns
tHDRI
Receive Data Hold After RSCLK1
–1.5
ns
tSCLKEW
TSCLK/RSCLK Width
4.5
ns
tSCLKE
TSCLK/RSCLK Period
15.0
ns
Switching Characteristics
tDFSI
TFS/RFS Delay After TSCLK/RSCLK (Internally Generated TFS/RFS)2
tHOFSI
TFS/RFS Hold After TSCLK/RSCLK (Internally Generated TFS/RFS)
tDDTI
Transmit Data Delay After TSCLK2
tHDTI
Transmit Data Hold After TSCLK
tSCLKIW
TSCLK/RSCLK Width
1
2
2
–1.0
Referenced to sample edge.
Referenced to drive edge.
|
Page 50 of 82 |
December 2007
ns
ns
3.0
2
Rev. PrG
3.0
ns
–2.0
ns
4.5
ns
ADSP-BF542/4/7/8/9
Preliminary Technical Data
Table 35. Serial Ports—Enable and Three-State
Parameter
Min
Max
Unit
Switching Characteristics
tDTENE
Data Enable Delay from External TSCLK1
tDDTTE
Data Disable Delay from External TSCLK
tDTENI
Data Enable Delay from Internal TSCLK1
tDDTTI
Data Disable Delay from Internal TSCLK1
1
0
1
ns
10.0
–2.0
ns
ns
3.0
ns
Max
Unit
10.0
ns
Referenced to drive edge.
Table 36. External Late Frame Sync
Parameter
Min
Switching Characteristics
tDDTLFSE
Data Delay from Late External TFS or External RFS with MCE = 1, MFD = 01, 2
tDTENLFS
Data Enable from late Frame Sync or MCE = 1, MFD = 01, 2
1
2
0
MCE = 1, TFS enable and TFS valid follow tDTENLFS and tDDTLFSE.
If external RFS/TFS setup to RSCLK/TSCLK > tSCLKE/2, then tDDTE/I and tDTENE/I apply; otherwise tDDTLFSE and tDTENLFS apply.
Rev. PrG
|
Page 51 of 82 |
December 2007
ns
ADSP-BF542/4/7/8/9
Preliminary Technical Data
DATA RECEIVE- INTERNAL CLOCK
DATA RECEIVE- EXTERNAL CLOCK
DRIVE
EDGE
SAMPLE
EDGE
DRIVE
EDGE
SAMPLE
EDGE
tSCLKIW
tSCLKEW
RSCLK
RSCLK
tDFSE
tDFSE
tHOFSE
tSFSI
tHFSI
tHOFSE
RFS
tSFSE
tHFSE
tSDRE
tHDRE
RFS
tSDRI
tHDRI
DR
DR
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK OR TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DATA TRANSMIT- INTERNAL CLOCK
DATA TRANSMIT- EXTERNAL CLOCK
DRIVE
EDGE
SAMPLE
EDGE
DRIVE
EDGE
SAMPLE
EDGE
tSCLKIW
tSCLKEW
TSCLK
TSCLK
tDFSI
tHOFSI
tDFSE
tSFSI
tHFSI
tHOFSE
TFS
tSFSE
TFS
tDDTI
tDDTE
tHDTI
tHDTE
DT
DT
NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK OR TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.
DRIVE
EDGE
DRIVE
EDGE
TSCLK (EXT)
TFS ("LATE", EXT.)
TSCLK / RSCLK
tDDTTE
tDTENE
DT
DRIVE
EDGE
DRIVE
EDGE
TSCLK (INT)
TFS ("LATE", INT.)
TSCLK / RSCLK
tDTENI
tDDTTI
DT
Figure 20. Serial Ports
Rev. PrG
|
Page 52 of 82 |
December 2007
tHFSE
ADSP-BF542/4/7/8/9
Preliminary Technical Data
EXTERNAL RFS WITH MCE = 1, MFD = 0 (INTERNAL OR EXTERNAL CLOCK)
DRIVE
SAMPLE
DRIVE
RSCLK
t HOFSE/I
t SFSE/I
RFS
tDDTE/I
t DTENLFS
tHDTE/I
1ST BIT
DT
2ND BIT
t DDTLFSE
LATE EXTERNAL TFS (I NTERNAL OR EXTERNAL CLOCK)
DRIVE
SAMPLE
DRIVE
TSCLK
t SFSE/I
tHOFSE /I
TFS
t DDTE/I
T DTENLFS
DT
t HDTE/I
1ST BIT
2ND BIT
t DDTLFSE
Figure 21. External Late Frame Sync (Frame Sync Setup < tSCLKE/2)
Rev. PrG
|
Page 53 of 82 |
December 2007
ADSP-BF542/4/7/8/9
Preliminary Technical Data
EXTERNAL RFS WITH MCE = 1, MFD = 0
DRIVE
SAMPLE
DRIVE
RSCLK
tSFSE/I
tHOFSE/I
RFS
tDDTE/I
tDTENLSCK
DT
tHDTE/I
1ST BIT
2ND BIT
tDDTLSCK
LATE EXTERNAL TFS
DRIVE
SAMPLE
DRIVE
TSCLK
tSFSE/I
tHOFSE/I
TFS
tDDTE/I
tDTENLSCK
DT
tHDTE/I
1ST BIT
2ND BIT
tDDTLSCK
Figure 22. External Late Frame Sync (Frame Sync Setup > tSCLKE/2)
Rev. PrG
|
Page 54 of 82 |
December 2007
ADSP-BF542/4/7/8/9
Preliminary Technical Data
Serial Peripheral Interface (SPI) Port—Master Timing
Table 37 and Figure 23 describe SPI port master operations.
Table 37. Serial Peripheral Interface (SPI) Port—Master Timing
Parameter
Timing Requirements
tSSPIDM
Data input valid to SCK edge (data input setup)
tHSPIDM
SCK sampling edge to data input invalid
Switching Characteristics
tSDSCIM
SPISELx low to first SCK edge (x=0 or 1)
tSPICHM
Serial clock high period
tSPICLM
Serial clock low period
tSPICLK
Serial clock period
tHDSM
Last SCK edge to SPISELx high (x=0 or 1)
Sequential transfer delay
tSPITDM
tDDSPIDM
SCK edge to data out valid (data out delay)
tHDSPIDM
SCK edge to data out invalid (data out hold)
Minimum
tSPICHM
tSPICLM
tSPICLM
tSPICHM
tSPICLK
tHDSM
SCK
(CPOL = 0)
(OUTPUT)
SCK
(CPOL = 1)
(OUTPUT)
tDDSPIDM
MOSI
(OUTPUT)
tHDSPIDM
MSB
CPHA=1
tSSPIDM
MISO
(INPUT)
LSB
tHSPIDM
tSSPIDM
MSB VALID
LSB VALID
tDDSPIDM
MOSI
(OUTPUT)
CPHA=0
MISO
(INPUT)
tHSPIDM
tHDSPIDM
MSB
tSSPIDM
LSB
tHSPIDM
MSB VALID
LSB VALID
Figure 23. Serial Peripheral Interface (SPI) Port—Master Timing
Rev. PrG
|
Page 55 of 82 |
December 2007
Unit
7.5
–1.5
ns
ns
2tSCLK –1.5
2tSCLK –1.5
2tSCLK –1.5
4tSCLK –1.5
2tSCLK –1.5
2tSCLK –1.5
0
–1.0
ns
ns
ns
ns
ns
ns
ns
ns
SPISELx
(OUTPUT)
tSDSCIM
Maximum
tSPITDM
6
4.0
ADSP-BF542/4/7/8/9
Preliminary Technical Data
Serial Peripheral Interface (SPI) Port—Slave Timing
Table 38 and Figure 24 describe SPI port slave operations.
Table 38. Serial Peripheral Interface (SPI) Port—Slave Timing
Parameter
Timing Requirements
tSPICHS
Serial clock high period
tSPICLS
Serial clock low period
Serial clock period
tSPICLK
tHDS
Last SCK edge to SPISS not asserted
tSPITDS
Sequential Transfer Delay
tSDSCI
SPISS assertion to first SCK edge
tSSPID
Data input valid to SCK edge (data input setup)
tHSPID
SCK sampling edge to data input invalid
Switching Characteristics
tDSOE
SPISS assertion to data out active
tDSDHI
SPISS deassertion to data high impedance
tDDSPID
SCK edge to data out valid (data out delay)
tHDSPID
SCK edge to data out invalid (data out hold)
Minimum
2tSCLK –1.5
2tSCLK –1.5
4tSCLK –1.5
2tSCLK –1.5
2tSCLK –1.5
2tSCLK –1.5
1.6
1.6
0
0
0
0
tSPICLS
tSPICLS
tSPICHS
tSPICLK
tHDS
tSPITDS
SCK
(CPOL = 0)
(INPUT)
tSDSCI
SCK
(CPOL = 1)
(INPUT)
tDSOE
tDDSPID
tHDSPID
MISO
(OUTPUT)
tSSPID
MOSI
(INPUT)
LSB
tHSPID
tSSPID
tHSPID
MSB VALID
tDSOE
LSB VALID
tDDSPID
tDSDHI
MSB
LSB
tHSPID
CPHA=0
MOSI
(INPUT)
tDSDHI
MSB
CPHA=1
MISO
(OUTPUT)
tDDSPID
tSSPID
MSB VALID
LSB VALID
Figure 24. Serial Peripheral Interface (SPI) Port—Slave Timing
Rev. PrG
|
Page 56 of 82 |
December 2007
Unit
ns
ns
ns
ns
ns
ns
ns
ns
8
8
10
10
SPISS
(INPUT)
tSPICHS
Maximum
ns
ns
ns
ns
ADSP-BF542/4/7/8/9
Preliminary Technical Data
Universal Asynchronous Receiver-Transmitter
(UART) Ports—Receive and Transmit Timing
Figure 25 describes the UART ports receive and transmit operations. The maximum baud rate is SCLK/16. There is some
latency between the generation of internal UART interrupts
and the external data operations. These latencies are negligible
at the data transmission rates for the UART.
CLKOUT
(SAMPLE
CLOCK)
UARTx Rx
DATA(5-8)
STOP
RECEIVE
INTERNAL
UART RECEIVE
UART RECEIVE BIT SET BY
DATA STOP ;
CLEARED BY FIFO READ
INTERRUPT
START
UARTx Tx
DATA(5-8)
STOP (1-2)
TRANSMIT
INTERNAL
UART TRANSMIT
INTERRUPT
UART TRANSMIT BIT SET BY PROGRAM;
CLEARED BY WRITE TO TRANSMIT
Figure 25. UART Ports—Receive and Transmit Timing
General-Purpose Port Timing
Table 39 and Figure 26 describe general-purpose
port operations.
Table 39. General-Purpose Port Timing
Parameter
Timing Requirement
tWFI
General-Purpose Port Pin Input Pulse Width
Switching Characteristic
General-Purpose Port Pin Output Delay from CLKOUT Low
tGPOD
CLKOUT
tGPOD
GPP OUTPUT
tWFI
GPP INPUT
Figure 26. General-Purpose Port Timing
Rev. PrG
|
Page 57 of 82 |
December 2007
Minimum
Maximum
tSCLK + 1
0
Unit
ns
6
ns
ADSP-BF542/4/7/8/9
Preliminary Technical Data
Timer Cycle Timing
Table 40 and Figure 27 describe timer expired operations. The
input signal is asynchronous in “width capture mode” and
“external clock mode” and has an absolute maximum input frequency of (fSCLK/2) MHz.
Table 40. Timer Cycle Timing
Parameter
Timing Characteristics
tWL
Timer Pulse Width Input Low (Measured In SCLK Cycles)1
tWH
Timer Pulse Width Input High (Measured In SCLK Cycles)1
Timer Input Setup Time Before CLKOUT Low2
tTIS
tTIH
Timer Input Hold Time After CLKOUT Low2
Switching Characteristic
tHTO
Timer Pulse Width Output (Measured In SCLK Cycles)
tTOD
Timer Output Update Delay After CLKOUT High
1
2
Minimum
1tSCLK
1tSCLK
5
–2
1tSCLK
The minimum pulse widths apply for TMRx signals in width capture and external clock modes.
Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize timer flag inputs.
CLK OUT
t TOD
TIMER OUTPUT
t HTO
tTIS
t TIH
TIMER INPUT
tWH, tWL
Figure 27. Timer Cycle Timing
Rev. PrG
|
Page 58 of 82 |
Maximum
December 2007
Unit
ns
ns
ns
ns
(232–1)tSCLK
6
ns
ns
ADSP-BF542/4/7/8/9
Preliminary Technical Data
ATA/ATAPI Controller Timing
Table 41. ATA/ATAPI Controller Timing
Parameter
Timing Requirements
TBD
TBD
Switching Characteristic
TBD
TBD
Minimum
Maximum
TBD
AT
A TA /
ll
ontro
C
I
AP
Unit
ns
TBD
ns
Maximum
Unit
D
is TB
g
n
i
m
e r Ti
Figure 28. ATA/ATAPI Controller Timing
Up/Down Counter/Rotary Encoder Timing
Table 42. Up/Down Counter/Rotary Encoder Timing
Parameter
Timing Requirements
tWCOUNT
Up/Down Counter/Rotary Encoder Input Pulse Width
Switching Characteristic
tCIS
Counter Input Setup Time Before CLKOUT Low1
tCIH
Counter Input Hold Time After CLKOUT Low1
1
Minimum
tSCLK + 1
TBD
TBS
Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize counter inputs.
CLK OUT
tCIS
tCIH
CUD/CDG/CZM
tWCOUNT
Figure 29. Up/Down Counter/Rotary Encoder Timing
Rev. PrG
|
Page 59 of 82 |
December 2007
ns
TBD
TBD
ns
ns
ADSP-BF542/4/7/8/9
Preliminary Technical Data
SD/SDIO Controller Timing
Table 43. SD/SDIO Controller Timing
Parameter
Timing Requirements
TBD
TBD
Switching Characteristic
TBD
TBD
Minimum
Maximum
TBD
ns
TBD
DI
SD/S
OC
is
iming
T
r
e
ll
ontro
Unit
ns
TBD
Figure 30. SD/SDIO Controller Timing
MXVR Timing
Table 44 and Table 45 describe the MXVR timing requirements.
Table 44. MXVR Timing—MXI Center Frequency Requirements
Parameter
fMXI_256
fMXI_384
fMXI_512
fMXI_1024
Fs = 38 KHz
9.728
14.592
19.456
38.912
MXI Center Frequency (256Fs)
MXI Center Frequency (384Fs)
MXI Center Frequency (512Fs)
MXI Center Frequency (1024Fs)
Fs = 44.1 KHz
11.2896
16.9344
22.5792
45.1584
Fs = 48 KHz
12.288
18.432
24.576
49.152
Unit
MHz
MHz
MHz
MHz
Table 45. MXVR Timing— MXI Clock Requirements
Parameter
Timing Requirements
FSMXI
MXI Clock Frequency Stability
FTMXI
MXI Frequency Tolerance Over Temperature
DCMXI
MXI Clock Duty Cycle
Rev. PrG
|
Page 60 of 82 |
December 2007
Min
Max
Unit
–50
–300
40
+50
+300
60
ppm
ppm
%
ADSP-BF542/4/7/8/9
Preliminary Technical Data
HOSTDP A/C Timing- Host Read Cycle
Table 46 describe the HOSTDP A/C Host Read Cycle timing
requirements.
Table 46. Host Read Cycle Timing Requirements
Parameter
Timing Requirements
Minimum
Maximum
Units
tSADRDL
tHADRDH
tRDWL
HOST_ADDR and Host_CE Setup before Host_RD assertion 1.5 * tsclk
HOST_ADDR and Host_CE Hold after Host_RD assertion
2.5
Host_RD pulse width low
tDRDYRDL + tRDYPRD + tDRDHRDY (ACK
mode)
1.5 * tsclk + 8.7 (INT mode)
ns
tRDWH
Host_RD pulse width high
2 * tsclk
ns
tDRDHRDY
Host_RD de-assertion delay after Host_ACK de-assertion
TBD
ns
ns
ns
ns
Switching Characteristics
tSDATRDY
Data valid after Host_ACK assertion
tsclk
tDRDYRDL
Host_ACK assertion delay after Host_RD
1.5 * tsclk + 8.7
ns
tRDYPRD
Host_ACK low pulse-width for Read access
Data Delay
ns
tHDARWH
Data disable after Host_RD
1.0
ns
HOST_ADDR
HOST_CE
tHADRDH
tSADRDL
tRDWH
tRDWL
HOST_RD
tDRDYRDL
tRDYPRD
tDRDHRDY
HOST_ACK
tHDARWH
tSDATRDY
HOST_D15-0
Figure 31. HOSTDP A/C- Host Read Cycle
Rev. PrG
|
Page 61 of 82 |
December 2007
ns
ADSP-BF542/4/7/8/9
Preliminary Technical Data
HOSTDP A/C Timing- Host Write Cycle
Table 47 describes the HOSTDP A/C Host Write Cycle timing
requirements.
Table 47. Host Write Cycle Timing Requirements
Parameter
Timing Requirements
tSADWRH
HOST_ADDR/Host_CE Setup before Host_WR
tHADWRH
HOST_ADDR/Host_CE Hold after Host_WR
tWRWL
Host_WR pulse width low
Minimum
tWRWH
tDWRHRDY
Host_WR pulse width high
Host_WR de-assertion delay after Host_ACK
de-assertion
tHDATWH
Data Hold after Host_WR de-assertion
tSDATWH
Data Setup before Host_WR de-assertion
Switching Characteristics
tDRDYWRL
Host_ACK low delay after Host_WR/Host_CE
tRDYPWR
Host_ACK low pulse-width for Write access
Maximum
Units
(1.5 * tsclk)+ 10.8
2.5
tDRDYWRL + tRDYPRD + tDWRHRDY (ACK
mode)
1.5 * tsclk + 8.7 (INT mode)
2 * tsclk
TBD
ns
ns
ns
ns
ns
2.5
2.5
ns
ns
1.5 * tsclk
HOST_ADDR
HOST_CE
tSADWRH
tWRWL
ns
tHADWRH
tWRWH
wrh
HOST_WR
tDWRHRDY
tDRDYWRL
tRDYPWR
HOST_ACK
tHDATWH
tSDATWH
HOST_D15-0
Figure 32. HOSTDP A/C- Host Write Cycle
Table 48. OTP Timing Parameters1
Parameter
tFACC
tRPGM
tCPS
tCPH
tPGM
1
Minimum
400
1
OTP Memory Bit Read Access Time
OTP Memory Charge Pump Release Time
OTP Memory Charge Pump Setup Time
OTP Memory Charge Pump Hold Time
OTP Memory Bit Program Time
0
0
10
These parameters are programmed into the OTP_TIMING register. See ADSP-BF54x Blackfin Processor Hardware Reference for details.
Rev. PrG
|
Maximum
Page 62 of 82 |
December 2007
Unit
ns
␮s
␮s
␮s
␮s
ADSP-BF542/4/7/8/9
Preliminary Technical Data
JTAG Test And Emulation Port Timing
Table 49 and Figure 33 describe JTAG port operations.
Table 49. JTAG Port Timing
Parameter
Timing Parameters
tTCK
TCK Period
tSTAP
TDI, TMS Setup Before TCK High
TDI, TMS Hold After TCK High
tHTAP
tSSYS
System Inputs Setup Before TCK High1
tHSYS
System Inputs Hold After TCK High1
tTRSTW
TRST Pulsewidth2 (measured in TCK cycles)
Switching Characteristics
tDTDO
TDO Delay from TCK Low
System Outputs Delay After TCK Low3
tDSYS
Minimum
Maximum
20
4
4
4
5
4
0
1
Unit
ns
ns
ns
ns
ns
TCK
10
12
ns
ns
System Inputs=PA15–0, PB14–0, PC15–0, PD15–0, PE15–0, PF15–0, PG15–0, PH13–0, PI15–0, PJ14–0, DQ15–0, DQS1–0, D15–0, ATAPI_PDIAG, CLKIN, RESET, NMI,
BMODE3–0, MFS, MLF_P, and MLF_M.
2
50 MHz Maximum
3
System Outputs=PA15–0, PB14–0, PC15–0, PD15–0, PE15–0, PF15–0, PG15–0, PH13–0, PI15–0, PJ14–0, DQ15–0, DQS1–0, D15–0, DA12–0, DBA1–0, DQM1–0,
DCLK0-1, DCLK0–1, DCS1–0, DCLKE, DRAS, DCAS, DWE, AMS3–0, ABE1–0, AOE, ARE, AWE, EMU, CLKOUT, CLKBUF, EXT_WAKE.
tTCK
TCK
tSTAP
tHTAP
TMS
TDI
tDTDO
TDO
tHSYS
tSSYS
SYSTEM
INPUTS
tDSYS
SYSTEM
OUTPUTS
Figure 33. JTAG Port Timing
Rev. PrG
|
Page 63 of 82 |
December 2007
ADSP-BF542/4/7/8/9
Preliminary Technical Data
POWER DISSIPATION
TEST CONDITIONS
Total power dissipation has two components: one due to internal circuitry (PINT) and one due to the switching of external
output drivers (PEXT). Table 50 through Table 52 show the
power dissipation for internal circuitry (VDDINT).
All timing parameters appearing in this data sheet were measured under the conditions described in this section.
See the ADSP-BF549 Blackfin Processor Hardware Reference for
definitions of the various operating modes and for instructions
on how to minimize system power.
Output pins are considered to be enabled when they have made
a transition from a high impedance state to the point when they
start driving. The output enable time tENA is the interval from
the point when a reference signal reaches a high or low voltage
level to the point when the output starts driving as shown in the
Output Enable/Disable diagram (Figure 34). The time
tENA_MEASURED is the interval from when the reference signal
switches to when the output voltage reaches 2.0 V (output high)
or 1.0 V (output low). Time tTRIP is the interval from when the
output starts driving to when the output reaches the 1.0 V or
2.0 V trip voltage. Time tENA is calculated as shown in the
equation:
Many operating conditions can affect power dissipation. System
designers should refer to Estimating Power for ADSPBF542/BF544/BF547/BF548/BF549 Blackfin Processors (EETBD) on the Analog Devices website (www.analog.com)—use
site search on “EE-TBD.” This document provides detailed
information for optimizing your design for lowest power.
Table 50. Internal Power Dissipation (Hibernate mode)
IDDHIBERNATE
IDDRTC
1
2
IDD (nominal)
Unit
TBD
μA
TBD
μA
1
Measured at VDDEXT = 3.65 V with voltage regulator off (VDDINT = 0 V).
2
Measured at VDDRTC = 3.3 V at 25°C.
Output Enable Time
t ENA = t ENA_MEASURED – t TRIP
If multiple pins (such as the data bus) are enabled, the measurement value is that of the first pin to start driving.
Output Disable Time
Table 51. Internal Power Dissipation (Deep Sleep mode)
VDDINT
1
2
IDD (nominal )
Unit
0.8
TBD
mA
0.9
TBD
mA
1.0
TBD
mA
1.1
TBD
mA
1.26
TBD
mA
1
2
Assumes VDDINT is regulated externally.
Nominal assumes an operating temperature of 25°C.
Table 52. Internal Power Dissipation (Full On1 mode)
VDDINT2 @ fCCLK
IDD (nominal3)
Unit
0.8 @ TBD MHz
TBD
mA
0.8 @ TBD MHz
TBD
mA
0.9 @ TBD MHz
TBD
mA
1.0 @ TBD MHz
TBD
mA
1.1 @ TBD MHz
TBD
mA
1.26 @ TBD MHz
TBD
mA
Output pins are considered to be disabled when they stop driving, go into a high impedance state, and start to decay from their
output high or low voltage. The time for the voltage on the bus
to decay by ΔV is dependent on the capacitive load, CL and the
load current, IL. This decay time can be approximated by the
equation:
t DECAY = ( C L ΔV ) ⁄ I L
The output disable time tDIS is the difference between
tDIS_MEASURED and tDECAY as shown in Figure 34. The time
tDIS_MEASURED is the interval from when the reference signal
switches to when the output voltage decays ΔV from the measured output high or output low voltage. The time tDECAY is
calculated with test loads CL and IL, and with ΔV equal to 0.5 V.
1
Processor executing 75% dual MAC, 25% ADD with moderate data bus activity.
Assumes VDDINT is regulated externally.
3
Nominal assumes an operating temperature of 25°C.
2
Rev. PrG
|
Page 64 of 82 |
December 2007
ADSP-BF542/4/7/8/9
Preliminary Technical Data
ENVIRONMENTAL CONDITIONS
To determine the junction temperature on the application
printed circuit board use:
T J = T CASE + ( Ψ JT × P D )
REFERENCE
SIGNAL
tDIS_MEASURED
tDIS
t ENA-MEASURED
TJ = Junction temperature (ⴗC)
t ENA
VOH
(MEASURED)
VOL
(MEASURED)
where:
VOH (MEASURED) $ V
VOH
2.0V (MEASURED)
TCASE = Case temperature (ⴗC) measured by customer at top
center of package.
VOL (MEASURED) + $ V
1.0V
ΨJT = From Table 53
VOL
(MEASURED)
t DECAY
tTRIP
OUTPUT STOPS DRIVING
PD = Power dissipation (see Power Dissipation on Page 64 for
the method to calculate PD)
OUTPUT STARTS DRIVING
HIGH IMPEDANCE STATE.
TEST CONDITIONS CAUSE THIS
VOLTAGE TO BE APPROXIMATELY 1.5V.
Values of θJA are provided for package comparison and printed
circuit board design considerations. θJA can be used for a first
order approximation of TJ by the equation:
T J = T A + ( θ JA × P D )
Figure 34. Output Enable/Disable
where:
Example System Hold Time Calculation
TA = Ambient temperature (ⴗC)
To determine the data output hold time in a particular system,
first calculate tDECAY using the equation given above. Choose ΔV
to be the difference between the ADSP-BF542/4/7/8/9 processor’s output voltage and the input threshold for the device
requiring the hold time. A typical ΔV will be 0.4 V. CL is the total
bus capacitance (per data line), and IL is the total leakage or
three-state current (per data line). The hold time will be tDECAY
plus the minimum disable time (for example, tDDAT for an asynchronous memory write cycle).
Values of θJC are provided for package comparison and printed
circuit board design considerations when an external heatsink is
required.
In Table 53, airflow measurements comply with JEDEC standards JESD51-2 and JESD51-6, and the junction-to-board
measurement complies with JESD51-8. The junction-to-case
measurement complies with MIL-STD-883 (Method 1012.1).
All measurements use a 2S2P JEDEC test board.
Table 53. Thermal Characteristics, 400-Ball CSP_BGA
506
TO
OUTPUT
PIN
Values of θJB are provided for package comparison and printed
circuit board design considerations.
1.5V
Parameter
θJA
30pF
θJB
θJC
ΨJT
Figure 35. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
INPUT
OR
OUTPUT
1.5V
1.5V
Figure 36. Voltage Reference Levels for AC
Measurements (Except Output Enable/Disable)
Rev. PrG
|
Page 65 of 82 |
December 2007
Condition
0 linear m/s air flow
1 linear m/s air flow
2 linear m/s air flow
0 linear m/s air flow
1 linear m/s air flow
2 linear m/s air flow
Typical
18.4
15.8
15.0
9.75
6.37
0.27
0.60
0.66
Unit
ⴗC/W
ⴗC/W
ⴗC/W
ⴗC/W
ⴗC/W
ⴗC/W
ⴗC/W
ⴗC/W
ADSP-BF542/4/7/8/9
Preliminary Technical Data
In Table 54, airflow measurements comply with JEDEC standards JESD51-2 and JESD51-6, and the junction-to-board
measurement complies with JESD51-8. The junction-to-case
measurement complies with MIL-STD-883 (Method 1012.1).
All measurements use a 2S2P JEDEC test board.
Table 54. Thermal Characteristics, 360-Ball PBGA
Parameter
θJA
θJB
θJC
ΨJT
Condition
0 linear m/s air flow
1 linear m/s air flow
2 linear m/s air flow
0 linear m/s air flow
1 linear m/s air flow
2 linear m/s air flow
Typical
17.5
15.2
14.4
7.2
5.9
0.22
0.35
0.42
Rev. PrG
Unit
ⴗC/W
ⴗC/W
ⴗC/W
ⴗC/W
ⴗC/W
ⴗC/W
ⴗC/W
ⴗC/W
|
Page 66 of 82 |
December 2007
ADSP-BF542/4/7/8/9
Preliminary Technical Data
400-BALL CSP_BGA PACKAGE
Table 55 lists the CSP_BGA package by signal for the ADSPBF549. Table 56 on Page 70 lists the CSP_BGA package by ball
number.
Table 55. 400-Ball CSP_BGA Ball Assignment (Alphabetically by Signal)
Signal
A1
A2
A3
ABE0
ABE1
AMS0
AMS1
AMS2
AMS3
AOE
ARE
ATAPI_PDIAG
AWE
BMODE0
BMODE1
BMODE2
BMODE3
CLKBUF
CLKIN
CLKOUT
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
DA0
DA1
DA2
DA3
Ball No.
B2
A2
B3
C17
C16
A10
D9
B10
D10
C10
B12
P19
D12
W1
W2
W3
W4
D11
A11
L16
D13
C13
B13
B15
A15
B16
A16
B17
C14
C15
A17
D14
D15
E15
E14
D17
G19
G17
E20
G18
Signal
DA4
DA5
DA6
DA7
DA8
DA9
DA10
DA11
DA12
DBA0
DBA1
DCAS
DCLK0
DCLK0
DCLK1
DCLK1
DCLKE
DCS0
DCS1
DDR_VREF
DDR_VSSR
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQM0
DQM1
DQS0
Ball No.
G16
F19
D20
C20
F18
E19
B20
F17
D19
H17
H16
F16
E16
D16
C18
D18
B18
C19
B19
M20
N20
L18
M19
L19
L20
L17
K16
K20
K17
K19
J20
K18
H20
J19
J18
J17
J16
G20
H19
F20
Rev. PrG
|
Signal
DQS1
DRAS
DWE
EMU
EXT_WAKE
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Page 67 of 82 |
Ball No.
H18
E17
E18
R5
M18
A1
A13
A20
B11
D1
D4
E3
F3
F6
F14
G9
G10
G11
H7
H8
H9
H10
H11
H12
J7
J8
J9
J10
J11
J12
K7
K8
K9
K10
K11
K12
K13
L7
L8
L9
December 2007
Signal
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GNDMP
MFS
MLF_M
Ball No.
L10
L11
L12
L13
L14
M6
M7
M8
M9
M10
M11
M12
M13
M14
N6
N7
N8
N9
N10
N11
N12
N13
N14
P8
P9
P10
P11
P12
P13
R9
R13
R14
R16
U8
V6
Y1
Y20
E7
E6
F4
ADSP-BF542/4/7/8/9
Preliminary Technical Data
Table 55. 400-Ball CSP_BGA Ball Assignment (Alphabetically by Signal) (Continued)
Signal
MLF_P
MXI
MXO
NMI
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
PA11
PA12
PA13
PA14
PA15
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PB10
PB11
PB12
PB13
PB14
PC0
PC1
PC2
PC3
PC4
Ball No.
E4
C2
C1
C11
U12
V12
W12
Y12
W11
V11
Y11
U11
U10
Y10
Y9
V10
Y8
W10
Y7
W9
W5
Y2
T6
U6
Y4
Y3
W6
V7
W8
V8
U7
W7
Y6
V9
Y5
H2
J3
J2
H1
G2
Signal
PC5
PC6
PC7
PC8
PC9
PC10
PC11
PC12
PC13
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
PD10
PD11
PD12
PD13
PD14
PD15
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
PE8
PE9
PE10
PE11
PE12
PE13
PE14
Ball No.
G1
J5
H3
Y14
V13
U13
W14
Y15
W15
P3
P4
R1
R2
T1
R3
T2
R4
U1
U2
T3
V1
T4
V2
U4
U3
V19
T17
U18
V14
Y16
W20
W19
R17
V20
U19
T18
P2
M5
P5
U16
Rev. PrG
|
Signal
PE15
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
PF8
PF9
PF10
PF11
PF12
PF13
PF14
PF15
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
PG8
PG9
PG10
PG11
PG12
PG13
PG14
PG15
PH0
PH1
PH2
PH3
PH4
PH5
PH6
Page 68 of 82 |
Ball No.
W17
K3
J1
K2
K1
L2
L1
L4
K4
L3
M1
M2
M3
M4
N4
N1
N2
J4
K5
L5
N3
P1
V15
Y17
W16
V16
Y19
Y18
U15
P16
R18
Y13
W13
W18
U14
V17
V18
U17
C3
D6
December 2007
Signal
PH7
PH8
PH9
PH10
PH11
PH12
PH13
PI0
PI1
PI2
PI3
PI4
PI5
PI6
PI7
PI8
PI9
PI10
PI11
PI12
PI13
PI14
PI15
PJ0
PJ1
PJ2
PJ3
PJ4
PJ5
PJ6
PJ7
PJ8
PJ9
PJ10
PJ11
PJ12
PJ13
RESET
RTXI
RTXO
Ball No.
H4
D5
C4
C7
C5
D7
C6
A3
B4
A4
B5
A5
B6
A6
B7
A7
C8
B8
A8
A9
C9
D8
B9
R20
N18
M16
T20
N17
U20
P18
N16
R19
P17
T19
M17
P20
N19
C12
A14
B14
ADSP-BF542/4/7/8/9
Preliminary Technical Data
Table 55. 400-Ball CSP_BGA Ball Assignment (Alphabetically by Signal) (Continued)
Signal
TCK
TDI
TDO
TMS
TRST
USB_DM
USB_DP
USB_ID
USB_RSET
USB_VBUS
USB_VREF
USB_XI
USB_XO
VDDDDR
VDDDDR
VDDDDR
VDDDDR
VDDDDR
VDDDDR
VDDDDR
Ball No.
V3
V5
V4
U5
T5
E2
E1
G3
D3
D2
B1
F1
F2
F10
F11
F12
G15
H13
H14
H15
Signal
VDDDDR
VDDDDR
VDDDDR
VDDDDR
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
Ball No.
J14
J15
K14
K15
E5
E9
E10
E11
E12
F7
F8
F13
G5
G6
G7
G14
H5
H6
K6
M15
Rev. PrG
|
Signal
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDINT
VDDINT
VDDINT
Page 69 of 82 |
Ball No.
N5
N15
P15
R6
R7
R8
R15
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
F9
G8
G12
December 2007
Signal
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDMP
VDDRTC
VDDUSB
VDDUSB
VDDVR
VROUT0
VROUT1
XTAL
Ball No.
G13
J6
J13
L6
L15
P6
P7
P14
R10
R11
R12
U9
E8
E13
F5
G4
F15
A18
A19
A12
ADSP-BF542/4/7/8/9
Preliminary Technical Data
Table 56 lists the CSP_BGA package by ball number for the
ADSP-BF549. Table 55 on Page 67 lists the CSP_BGA package
by signal.
Table 56. 400-Ball CSP_BGA Ball Assignment (Numerically by Ball Number)
Ball No.
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
Signal
GND
A2
PI0
PI2
PI4
PI6
PI8
PI11
PI12
AMS0
CLKIN
XTAL
GND
RTXI
D4
D6
D10
VROUT0
VROUT1
GND
USB_VREF
A1
A3
PI1
PI3
PI5
PI7
PI10
PI15
AMS2
GND
ARE
D2
RTXO
D3
D5
D7
DCLKE
DCS1
DA10
Ball No.
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
Signal
MXO
MXI
PH5
PH9
PH11
PH13
PH10
PI9
PI13
AOE
NMI
RESET
D1
D8
D9
ABE1
ABE0
DCLK1
DCS0
DA7
GND
USB_VBUS
USB_RSET
GND
PH8
PH6
PH12
PI14
AMS1
AMS3
CLKBUF
AWE
D0
D11
D12
DCLK0
D15
DCLK1
DA12
DA6
Rev. PrG
|
Ball No.
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
Page 70 of 82 |
Signal
USB_DP
USB_DM
GND
MLF_P
VDDEXT
MFS
GNDMP
VDDMP
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDRTC
D14
D13
DCLK0
DRAS
DWE
DA9
DA2
USB_XI
USB_XO
GND
MLF_M
VDDUSB
GND
VDDEXT
VDDEXT
VDDINT
VDDDDR
VDDDDR
VDDDDR
VDDEXT
GND
VDDVR
DCAS
DA11
DA8
DA5
DQS0
December 2007
Ball No.
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
H11
H12
H13
H14
H15
H16
H17
H18
H19
H20
Signal
PC5
PC4
USB_ID
VDDUSB
VDDEXT
VDDEXT
VDDEXT
VDDINT
GND
GND
GND
VDDINT
VDDINT
VDDEXT
VDDDDR
DA4
DA1
DA3
DA0
DQM0
PC3
PC0
PC7
PH7
VDDEXT
VDDEXT
GND
GND
GND
GND
GND
GND
VDDDDR
VDDDDR
VDDDDR
DBA1
DBA0
DQS1
DQM1
DQ11
ADSP-BF542/4/7/8/9
Preliminary Technical Data
Table 56. 400-Ball CSP_BGA Ball Assignment (Numerically by Ball Number) (Continued)
Ball No.
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
J11
J12
J13
J14
J15
J16
J17
J18
J19
J20
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11
K12
K13
K14
K15
K16
K17
K18
K19
K20
Signal
PF1
PC2
PC1
PG0
PC6
VDDINT
GND
GND
GND
GND
GND
GND
VDDINT
VDDDDR
VDDDDR
DQ15
DQ14
DQ13
DQ12
DQ9
PF3
PF2
PF0
PF7
PG1
VDDEXT
GND
GND
GND
GND
GND
GND
GND
VDDDDR
VDDDDR
DQ5
DQ7
DQ10
DQ8
DQ6
Ball No.
L1
L2
L3
L4
L5
L6
L7
L8
L9
L10
L11
L12
L13
L14
L15
L16
L17
L18
L19
L20
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
M13
M14
M15
M16
M17
M18
M19
M20
Signal
PF5
PF4
PF8
PF6
PG2
VDDINT
GND
GND
GND
GND
GND
GND
GND
GND
VDDINT
CLKOUT
DQ4
DQ0
DQ2
DQ3
PF9
PF10
PF11
PF12
PE12
GND
GND
GND
GND
GND
GND
GND
GND
GND
VDDEXT
PJ2
PJ11
EXT_WAKE
DQ1
DDR_VREF
Rev. PrG
|
Ball No.
N1
N2
N3
N4
N5
N6
N7
N8
N9
N10
N11
N12
N13
N14
N15
N16
N17
N18
N19
N20
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
Page 71 of 82 |
Signal
PF14
PF15
PG3
PF13
VDDEXT
GND
GND
GND
GND
GND
GND
GND
GND
GND
VDDEXT
PJ7
PJ4
PJ1
PJ13
DDR_VSSR
PG4
PE11
PD0
PD1
PE13
VDDINT
VDDINT
GND
GND
GND
GND
GND
GND
VDDINT
VDDEXT
PG12
PJ9
PJ6
ATAPI_PDIAG
PJ12
December 2007
Ball No.
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
Signal
PD2
PD3
PD5
PD7
EMU
VDDEXT
VDDEXT
VDDEXT
GND
VDDINT
VDDINT
VDDINT
GND
GND
VDDEXT
GND
PE7
PG13
PJ8
PJ0
PD4
PD6
PD10
PD12
TRST
PB2
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
PE1
PE10
PJ10
PJ3
ADSP-BF542/4/7/8/9
Preliminary Technical Data
Table 56. 400-Ball CSP_BGA Ball Assignment (Numerically by Ball Number) (Continued)
Ball No.
U1
U2
U3
U4
U5
U6
U7
U8
U9
U10
U11
U12
U13
U14
U15
U16
U17
U18
U19
U20
1
2
Signal
PD8
PD9
PD15
PD14
TMS
PB3
PB10
GND
VDDINT
PA8
PA7
PA0
PC10
PH1
PG11
PE14
PH4
PE2
PE9
PJ5
3
4
5
6
7
8
Ball No.
V1
V2
V3
V4
V5
V6
V7
V8
V9
V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
V20
9
Signal
PD11
PD13
TCK
TDO
TDI
GND
PB7
PB9
PB13
PA11
PA5
PA1
PC9
PE3
PG5
PG8
PH2
PH3
PE0
PE8
Ball No.
W1
W2
W3
W4
W5
W6
W7
W8
W9
W10
W11
W12
W13
W14
W15
W16
W17
W18
W19
W20
Signal
BMODE0
BMODE1
BMODE2
BMODE3
PB0
PB6
PB11
PB8
PA15
PA13
PA4
PA2
PG15
PC11
PC13
PG7
PE15
PH0
PE6
PE5
10 11 12 13 14 15 16 17 18 19 20
R
A
R
B
R
C
D
G
S
S
S
E
S
S
S
F
S
G
S
S
H
S
S
J
S
S
K
S
S
S
L
R
M
G
N
P
R
T
U
V
W
Y
KEY:
VDDINT
S
SUPPLIES: VDDDDR, VDDMP, VDDUSB , VDDRTC , VDDVR
VDDEXT
R
REFERENCES: VROUT0, VROUT1,DDR_VREF , USB_VREF
GND
G
GROUNDS: GNDMP, DDR_VSSR
NC
I/O SIGNALS
Figure 37. 400-Ball Mini-BGA Ground Configuration (Top View)
Rev. PrG
|
Page 72 of 82 |
December 2007
Ball No.
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Signal
GND
PB1
PB5
PB4
PB14
PB12
PA14
PA12
PA10
PA9
PA6
PA3
PG14
PC8
PC12
PE4
PG6
PG10
PG9
GND
ADSP-BF542/4/7/8/9
Preliminary Technical Data
360-BALL PBGA PACKAGE
Table 57 lists the 360-Ball PBGA package by signal for the
ADSP-BF549. Table 58 on Page 76 lists the 360-Ball PBGA
package by ball number.
Table 57. 360-Ball PBGA Ball Assignment (Alphabetically by Signal)
Signal
A1
A2
A3
ABE0
ABE1
AMS0
AMS1
AMS2
AMS3
AOE
ARE
ATAPI_PDIAG
AWE
BMODE0
BMODE1
BMODE2
BMODE3
CLKBUF
CLKIN
CLKOUT
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
Ball No.
A2
B3
A3
C20
C19
B13
C11
C10
C9
C12
A12
P24
B12
AD12
AD13
AD14
AD15
D3
A15
A25
B17
A17
B18
A18
B19
A19
B20
A20
B21
A21
B22
A22
B23
A23
B24
A24
Signal
DA0
DA1
DA2
DA3
DA4
DA5
DA6
DA7
DA8
DA9
DA10
DA11
DA12
DBA0
DBA1
DCAS
DCLK0
DCLK0
DCLK1
DCLK1
DCLKE
DCS0
DCS1
DDR_VREF
DDR_VSSR
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
Ball No.
F26
E26
D26
C26
D25
E25
F25
G25
H25
J25
G26
K25
K26
J26
H26
M26
G24
H24
E24
F24
M25
L25
AC26
AE26
AE25
AC25
AB25
AA25
Y25
W25
V25
U25
T25
R26
T26
U26
Rev. PrG
|
Signal
DQ11
DQ12
DQ13
DQ14
DQ15
DQM0
DQM1
DQS0
DQS1
DRAS
DWE
EMU
EXT_WAKE
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Page 73 of 82 |
Ball No.
V26
W26
Y26
AA26
AB26
N26
P25
P26
R25
L26
N25
AD6
D24
A1
A26
B15
B2
B25
C24
C3
D23
D4
L13
M12
M13
M14
M15
N12
N13
N14
N15
P11
P12
P13
P14
P15
December 2007
Signal
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GNDMP
MFS
MLF_M
MLF_P
MXI
MXO
NMI
PA0
PA1
PA2
PA3
PA4
Ball No.
R12
R13
R14
R15
T12
T13
T14
T15
U12
U13
U14
U15
V12
V13
V14
V15
AB24
AC23
AC4
AD24
AD3
AE2
AF1
AF26
N11
C6
C7
C8
C4
C5
C14
AE13
AE12
AF13
AF12
AE11
ADSP-BF542/4/7/8/9
Preliminary Technical Data
Table 57. 360-Ball PBGA Ball Assignment (Alphabetically by Signal) (Continued)
Signal
PA5
PA6
PA7
PA8
PA9
PA10
PA11
PA12
PA13
PA14
PA15
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PB10
PB11
PB12
PB13
PB14
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
Ball No.
AF11
AE10
AF10
AE9
AF9
AE8
AF8
AE7
AF7
AE6
AF6
AD4
AD5
AB1
AC1
AC2
AD2
AD1
AE1
AF2
AE3
AF3
AE4
AF4
AE5
AF5
H2
H1
J2
J1
F1
G1
K2
G2
AE14
AF14
Signal
PC10
PC11
PC12
PC13
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
PD10
PD11
PD12
PD13
PD14
PD15
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
PE8
PE9
PE10
PE11
PE12
PE13
PE14
PE15
Ball No.
AE15
AF15
AE16
AF16
P1
R2
R1
T2
T1
U2
U1
V2
V1
W2
W1
Y2
Y1
AA2
AA1
AB2
AF23
AF24
AF25
AE23
AE24
AD23
AC24
AD20
AD21
AE22
AD22
N1
P2
M1
AD25
AD26
Rev. PrG
|
Signal
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
PF8
PF9
PF10
PF11
PF12
PF13
PF14
PF15
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
PG8
PG9
PG10
PG11
PG12
PG13
PG14
PG15
PH0
PH1
PH2
PH3
Page 74 of 82 |
Ball No.
H3
J3
L2
K3
M2
L3
N2
M3
N3
P3
R3
T3
U3
V3
W3
Y3
K1
L1
AA3
AB3
AC3
AE21
AE20
AF20
AE19
AF19
AE18
AF18
AD19
AD18
AD17
AD16
AF21
AF22
Y24
AE17
December 2007
Signal
PH4
PH5
PH6
PH7
PH8
PH9
PH10
PH11
PH12
PH13
PI0
PI1
PI2
PI3
PI4
PI5
PI6
PI7
PI8
PI9
PI10
PI11
PI12
PI13
PI14
PI15
PJ0
PJ1
PJ2
PJ3
PJ4
PJ5
PJ6
PJ7
PJ8
PJ9
Ball No.
AF17
G3
F3
E3
B4
A4
B5
A5
B6
A6
B7
A7
B8
A8
B9
A9
B10
A10
B11
A11
B14
A14
C13
C17
C18
A13
C21
C22
C23
M24
N24
R24
T24
U24
V24
AA24
ADSP-BF542/4/7/8/9
Preliminary Technical Data
Table 57. 360-Ball PBGA Ball Assignment (Alphabetically by Signal) (Continued)
Signal
PJ10
PJ11
PJ12
PJ13
RESET
RTXI
RTXO
TCK
TDI
TDO
TMS
TRST
USB_DM
USB_DP
USB_ID
USB_RSET
USB_VBUS
USB_VREF
Ball No.
W24
J24
K24
L24
B16
C15
C16
AD11
AD10
AD9
AD8
AD7
D1
E1
E2
D2
F2
C2
Signal
USB_XI
USB_XO
VDDDDR
VDDDDR
VDDDDR
VDDDDR
VDDDDR
VDDDDR
VDDDDR
VDDDDR
VDDDDR
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
Ball No.
B1
C1
N16
P16
P17
R16
R17
T16
T17
U16
U17
J12
J13
K10
K11
K12
K13
K14
Rev. PrG
|
Signal
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDINT
Page 75 of 82 |
Ball No.
L10
L11
L12
L14
L15
M10
M11
N10
P10
P9
R10
R11
R9
T10
T11
U10
U11
K15
December 2007
Signal
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDINT
VDDMP
VDDRTC
VDDUSB
VDDUSB
VDDVR
VROUT0
VROUT1
XTAL
Ball No.
K17
L16
L17
M16
M17
M18
N17
N18
P18
R18
K16
J14
M9
N9
J15
B26
C25
A16
ADSP-BF542/4/7/8/9
Preliminary Technical Data
Table 58 lists the 360-Ball PBGA package by ball number for the
ADSP-BF549. Table 59 on Page 81 lists the 360-Ball PBGA
package by signal.
Table 58. 360-Ball PBGA Ball Assignment (Numerically by Ball Number)
Ball No.
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
Signal
GND
A1
A3
PH9
PH11
PH13
PI1
PI3
PI5
PI7
PI9
ARE
PI15
PI11
CLKIN
XTAL
D1
D3
D5
D7
D9
D11
D13
D15
CLKOUT
GND
USB_XI
GND
A2
PH8
PH10
PH12
PI0
PI2
PI4
PI6
PI8
AWE
AMS0
PI10
Ball No.
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
D1
D2
Signal
GND
RESET
D0
D2
D4
D6
D8
D10
D12
D14
GND
VROUT0
USB_XO
USB_VREF
GND
MXI
MXO
MFS
MLF_M
MLF_P
AMS3
AMS2
AMS1
AOE
PI12
NMI
RTXI
RTXO
PI13
PI14
ABE1
ABE0
PJ0
PJ1
PJ2
GND
VROUT1
DA3
USB_DM
USB_RSET
Rev. PrG
|
Ball No.
D3
D4
D23
D24
D25
D26
E1
E2
E3
E24
E25
E26
F1
F2
F3
F24
F25
F26
G1
G2
G3
G24
G25
G26
H1
H2
H3
H24
H25
H26
J1
J2
J3
J12
J13
J14
J15
J24
J25
J26
Page 76 of 82 |
Signal
CLKBUF
GND
GND
EXT_WAKE
DA4
DA2
USB_DP
USB_ID
PH7
DCLK1
DA5
DA1
PC4
USB_VBUS
PH6
DCLK1
DA6
DA0
PC5
PC7
PH5
DCLK0
DA7
DA10
PC1
PC0
PF0
DCLK0
DA8
DBA1
PC3
PC2
PF1
VDDEXT
VDDEXT
VDDRTC
VDDVR
PJ11
DA9
DBA0
December 2007
Ball No.
K1
K2
K3
K10
K11
K12
K13
K14
K15
K16
K17
K24
K25
K26
L1
L2
L3
L10
L11
L12
L13
L14
L15
L16
L17
L24
L25
L26
M1
M2
M3
M9
M10
M11
M12
M13
M14
M15
M16
M17
Signal
PG0
PC6
PF3
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDEXT
VDDINT
VDDMP
VDDINT
PJ12
DA11
DA12
PG1
PF2
PF5
VDDEXT
VDDEXT
VDDEXT
GND
VDDEXT
VDDEXT
VDDINT
VDDINT
PJ13
DCS0
DRAS
PE13
PF4
PF7
VDDUSB
VDDEXT
VDDEXT
GND
GND
GND
GND
VDDINT
VDDINT
ADSP-BF542/4/7/8/9
Preliminary Technical Data
Table 58. 360-Ball PBGA Ball Assignment (Numerically by Ball Number) (Continued)
Ball No.
M18
M24
M25
M26
N1
N2
N3
N9
N10
N11
N12
N13
N14
N15
N16
N17
N18
N24
N25
N26
P1
P2
P3
P9
P10
P11
P12
P13
P14
P15
P16
P17
P18
P24
P25
P26
R1
R2
R3
R9
Signal
VDDINT
PJ3
DCKE
DCAS
PE11
PF6
PF8
VDDUSB
VDDEXT
GNDMP
GND
GND
GND
GND
VDDDDR
VDDINT
VDDINT
PJ4
DWE
DQM0
PD0
PE12
PF9
VDDEXT
VDDEXT
GND
GND
GND
GND
GND
VDDDDR
VDDDDR
VDDINT
ATAPI_PDIAG
DQM1
DQS0
PD2
PD1
PF10
VDDEXT
Ball No.
R10
R11
R12
R13
R14
R15
R16
R17
R18
R24
R25
R26
T1
T2
T3
T10
T11
T12
T13
T14
T15
T16
T17
T24
T25
T26
U1
U2
U3
U10
U11
U12
U13
U14
U15
U16
U17
U24
U25
U26
Signal
VDDEXT
VDDEXT
GND
GND
GND
GND
VDDDDR
VDDDDR
VDDINT
PJ5
DQS1
DQ8
PD4
PD3
PF11
VDDEXT
VDDEXT
GND
GND
GND
GND
VDDDDR
VDDDDR
PJ6
DQ7
DQ9
PD6
PD5
PF12
VDDEXT
VDDEXT
GND
GND
GND
GND
VDDDDR
VDDDDR
PJ7
DQ6
DQ10
Rev. PrG
|
Ball No.
V1
V2
V3
V12
V13
V14
V15
V24
V25
V26
W1
W2
W3
W24
W25
W26
Y1
Y2
Y3
Y24
Y25
Y26
AA1
AA2
AA3
AA24
AA25
AA26
AB1
AB2
AB3
AB24
AB25
AB26
AC1
AC2
AC3
AC4
AC23
AC24
Page 77 of 82 |
Signal
PD8
PD7
PF13
GND
GND
GND
GND
PJ8
DQ5
DQ11
PD10
PD9
PF14
PJ10
DQ4
DQ12
PD12
PD11
PF15
PH2
DQ3
DQ13
PD14
PD13
PG2
PJ9
DQ2
DQ14
PB2
PD15
PG3
GND
DQ1
DQ15
PB3
PB4
PG4
GND
GND
PE6
December 2007
Ball No.
AC25
AC26
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AE1
AE2
AE3
AE4
AE5
AE6
AE7
AE8
AE9
AE10
AE11
AE12
Signal
DQ0
DCS1
PB6
PB5
GND
PB0
PB1
EMU
TRST
TMS
TDO
TDI
TCK
BMODE0
BMODE1
BMODE2
BMODE3
PG15
PG14
PG13
PG12
PE7
PE8
PE10
PE5
GND
PE14
PE15
PB7
GND
PB9
PB11
PB13
PA14
PA12
PA10
PA8
PA6
PA4
PA1
ADSP-BF542/4/7/8/9
Preliminary Technical Data
Table 58. 360-Ball PBGA Ball Assignment (Numerically by Ball Number) (Continued)
Ball No.
AE13
AE14
AE15
AE16
AE17
AE18
AE19
AE20
Signal
PA0
PC8
PC10
PC12
PH3
PG10
PG8
PG6
Ball No.
AE24
AE25
AE26
AF1
AF2
AF3
AF4
AF5
Signal
PE4
DDR_VSSR
DDR_VREF
GND
PB8
PB10
PB12
PB14
Ball No.
AF9
AF10
AF11
AF12
AF13
AF14
AF15
AF16
Signal
PA9
PA7
PA5
PA3
PA2
PC9
PC11
PC13
AE21
PG5
AF6
PA15
AF17
PH4
AE22
PE9
AF7
PA13
AF18
PG11
AE23
PE3
AF8
PA11
AF19
PG9
2
1
4
3
6
5
8
7
10
9
12
14 16 18
20 22 24 26
11 13 15 17 19 21 23 25
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
R
R
R
S S
S
S
S
G
S
S
S
S
S
S
S
S
S
G R
VDDINT
S
SUPPLIES: VDDDDR, VDDMP, VDDUSB , VDDRTC , VDDVR
VDDEXT
R
REFERENCES: VROUT0, VROUT1, DDR_VREF, USB_VREF
GND
G
GROUNDS: GNDMP, DDR_VSSR
NC
I/O SIGNALS
Figure 38. 360-Ball PBGA Ground Configuration (Top View)
Rev. PrG
|
Page 78 of 82 |
December 2007
Ball No.
AF20
AF21
AF22
AF23
AF24
AF25
AF26
Signal
PG7
PH0
PH1
PE0
PE1
PE2
GND
ADSP-BF542/4/7/8/9
Preliminary Technical Data
OUTLINE DIMENSIONS
Dimensions for the 17 mm ⫻ 17 mm CSP_BGA package in
Figure 39 are shown in millimeters.
15.20 BSC SQ
17.00 BSC SQ
A1 BALL
0.80 BSC BALL PITCH
A1 BALL INDICATOR
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
BOTTOM VIEW
TOP VIEW
0.28 MIN
0.12 MAX
COPLANARITY
1.70 MAX
SIDE VIEW
0.50
BALL DIAMETER 0.45
0.40
DETAIL A
SEATING PLANE
DETAIL A
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. COMPLIANT TO JEDEC REGISTERED OUTLINE MO-205, VARIATION AM,
WITH THE EXCEPTION OF BALL DIAMETER.
3. CENTER DIMENSIONS ARE NOMINAL.
Figure 39. 400-Ball, 17 mm ⫻ 17 mm CSP_BGA (Chip Scale Package Ball Grid Array) (BC-400)
Rev. PrG
|
Page 79 of 82 |
December 2007
ADSP-BF542/4/7/8/9
Preliminary Technical Data
Dimensions for the 360-ball PBGA 27 mm ⫻ 27 mm package in
Figure 40 are shown in millimeters.
360-Ball Plastic Ball Grid Array [PBGA]
(B-360-1)
Dimensions shown in millimeters
27.20
27.00 SQ
26.80
A1 BALL
PAD CORNER
6.75 BSC
26
A1 BALL
PAD
CORNER
25
6
24 22 20 18 16 14 12 10 8
4
2
23 21 19 17 15 13 11 9
3
5
7
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
24.20
24.00 SQ
23.80
25.00
BSC SQ
1.00
BSC
TOP VIEW
BOTTOM VIEW
DETAIL A
DETAIL A
0.66
0.61
0.56
0.50 NOM
0.45 MIN
0.70
0.60
0.50
BALL DIAMETER
COMPLIANT TO JEDEC STANDARDS MS-034-AAL-1
Figure 40. 360-Ball, 27 mm ⫻ 27 mm PBGA (B-360-1)
Rev. PrG
|
Page 80 of 82 |
December 2007
1.22
1.17
1.12
COPLANARITY
0.20 MAX
SEATING
PLANE
091007-A
2.40
2.28
2.13
1.00 REF
ADSP-BF542/4/7/8/9
Preliminary Technical Data
SURFACE MOUNT DESIGN
Table 59 is provided as an aid to PCB design. For industrystandard design recommendations, refer to IPC-7351, Generic
Requirements for Surface Mount Design and Land Pattern
Standard.
Table 59. BGA Data for Use with Surface Mount Design
Package
Ball Attach Type
400-Ball CSP_BGA (Chip Scale Package Ball Grid Array) BC-400 Solder Mask Defined
360-Ball PBGA (B-360-1)
Soldier Mask Defined
Rev. PrG
|
Page 81 of 82 |
Solder Mask Opening
0.40 mm diameter
0.43 mm diameter
December 2007
Ball Pad Size
0.50 mm diameter
0.56 mm diameter
ADSP-BF542/4/7/8/9
Preliminary Technical Data
ORDERING GUIDE
Part numbers that include “Z” are RoHS Compliant.
Part Number
Temperature
Range (Ambient)
ADSP-BF549BBCZ-ENG -40⬚C to 85⬚C
ADSP-BF549BBZ-ENG -40⬚C to 85⬚C
ADSP-BF548BBCZ-5X -40⬚C to 85⬚C
ADSP-BF547BBCZ-5X -40⬚C to 85⬚C
ADSP-BF544BBCZ-5X -40⬚C to 85⬚C
ADSP-BF542BBCZ-5X -40⬚C to 85⬚C
Speed Grade
(Max)
533 MHZ
533 MHZ
533 MHZ
533 MHZ
533 MHZ
533 MHZ
Operating Voltage (Nominal) Package Description Package Option
1.25 V internal, 2.5 V or 3.3 V I/O
1.25 V internal, 2.5 V or 3.3 V I/O
1.25 V internal, 2.5 V or 3.3 V I/O
1.25 V internal, 2.5 V or 3.3 V I/O
1.25 V internal, 2.5 V or 3.3 V I/O
1.25 V internal, 2.5 V or 3.3 V I/O
© 2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR06512-0-12/07(PrG)
Rev. PrG
|
Page 82 of 82 |
December 2007
400-Ball CSP_BGA
360-Ball PBGA
400-Ball CSP_BGA
400-Ball CSP_BGA
400-Ball CSP_BGA
400-Ball CSP_BGA
BC-400
B-360
BC-400
BC-400
BC-400
BC-400