PHILIPS FBL22033 3.3v btl 8-bit latched/registered/pass-thru futurebus universal interface transceiver Datasheet

INTEGRATED CIRCUITS
FBL22033
3.3V BTL 8-bit latched/registered/pass-thru
Futurebus+ universal interface transceiver
Product specification
IC23 data handbook
Philips Semiconductors
1999 Apr 15
Philips Semiconductors
Product specification
3.3V BTL 8-bit latched/registered/pass-thru
universal transceiver with 30Ω termination
FBL22033
• Controlled output ramp and multiple GND pins minimize ground
FEATURES
• 8-bit transceivers
• Latched, registered or straight through in either A to B or B to A
bounce
• Glitch-free power up/power down operation
• Low ICC current
• Tight output skew
• Supports live insertion
• Pins for the optional JTAG boundary scan function are provided
• High density packaging in plastic Quad Flatpack
• 5V compatible I/O on A-port
• Same pinout and function as the FBL2033 except for 30Ω series
path
• Drives heavily loaded backplanes with equivalent load
impedances down to 10Ω.
• High drive 100mA BTL Open Collector drivers on B-port
• Allows incident wave switching in heavily loaded backplane buses
• Reduced BTL voltage swing produces less noise and reduces
power consumption
• Built-in precision band-gap reference provides accurate receiver
termination on 4 outputs making external resistors unnecessary
thresholds and improved noise immunity
• A port outputs include 30Ω termination to reduce overshoot and
• Compatible with IEEE Futurebus+ or proprietary BTL backplanes
• Each BTL driver has a dedicated Bus GND for a signal return
undershoot
QUICK REFERENCE DATA
SYMBOL
tPLH
tPHL
tPLH
tPHL
COB
IOL
ICC
PARAMETER
Propagation delay
AIn to Bn
Propagation delay
Bn to AOn
Output capacitance (B0 – Bn only)
Output current (B0 – Bn only)
AIn to Bn
outputs Low
outputs High
Supply
Su
ly current
TYPICAL
3.0
3.0
5.1
5.5
6
100
Bn to AOn (outputs Low)
Bn to AOn (outputs High)
9
14
UNIT
ns
ns
pF
mA
mA
17
14
ORDERING INFORMATION
PACKAGE
52-pin Plastic Quad Flat Pack (PQFP)
NOTE: Thermal mounting or forced air is recommended
1999 Apr 15
COMMERCIAL RANGE
VCC = 3.3V±10%; Tamb = –40°C to +85°C
FBL2033BB
2
DWG
No.
SOT379-1
853–2157 21253
Philips Semiconductors
Product specification
3.3V BTL 8-bit latched/registered/pass-thru
universal transceiver with 30Ω termination
FBL22033
BIAS V
B0
BG GND
BG VCC
OEA
SBA0
SBA1
VCC
LCAB
LOGIC GND
AI0
AI1
AO0
PIN CONFIGURATION
52 51 50 49 48 47 46 45 44 43 42 41 40
LOGIC GND
1
39
AO1
2
38
B1
AI2
3
37
BUS GND
AO2
4
36
B2
AI3
5
35
BUS GND
AO3
6
34
B3
LOOPBACK
7
33
BUS GND
AI4
8
32
B4
AO4
9
31
BUS GND
AI5
10
30
B5
AO5
11
29
BUS GND
AI6
12
28
B6
LOGIC GND
13
27
BUS GND
8-Bit Universal Transceiver
FBL22033
52-lead PQFP
BUS GND
B7
OEB1
BUS GND
OEB0
VCC
SAB1
SG00092
by reducing voltage swing (1V p-p, between 1V and 2V) and
reduced capacitive loading by placing an internal series diode on the
drivers. BTL also provides incident wave switching, a necessity for
high performance backplanes.
DESCRIPTION
The FBL22033 is an 8-bit transceiver featuring a split input (AI) and
output (AO) bus on the TTL-level side.
The common I/O, open collector B port operates at BTL signal
levels. The logic element for data flow in each direction is controlled
by two pairs of mode select inputs (SBA0 and SBA1 for B-to-A,
SAB0 and SAB1 for A-to-B). It can be configured as a buffer, a
register, or a D-type latch.
Output clamps are provided on the BTL outputs to further reduce
switching noise. The “VOH” clamp reduces inductive ringing effects
during a Low-to-High transition. The “VOH” clamp is always active.
The other clamp, the “trapped reflection” clamp, clamps out ringing
below the BTL 0.5V VOL level. This clamp remains active for
approximately 100ns after a High-to-Low transition.
When configured in the buffer mode, the inverse of the input data
appears at the output port. In the flip-flop mode, data is stored on
the rising edge of the appropriate clock input (LCAB or LCBA). In the
latch mode, clock pins serve as transparent-High latch enables.
Regardless of the mode, data is inverted from input to output.
To support live insertion, OEB0 is held Low during power on/off
cycles to ensure glitch- free B port drivers. Proper bias for B port
drivers during live insertion is provided by the BIAS V pin when at a
3.3V level while VCC is Low. The BIAS V pin is a low current input
which will reverse-bias the BTL driver series Schottky diode, and
also bias the B port output pins to a voltage between 1.62V and
2.1V. This bias function is in accordance with IEEE BTL Standard
1194.1. If live insertion is not a requirement, the BIAS V pin should
be tied to a VCC pin.
Data flow in the B-to-A direction, regardless of the logic element
selected, is further controlled by the Loopback input. When the
Loopback input is High the output of the selected A-to-B logic
element (not inverted) becomes the B-to-A input.
The 3-State AO port is enabled by asserting a High level on OEA.
The B port has two output enables, OEB0 and OEB1. Only when
OEB0 is High and OEB1 is Low is the output enabled. When either
OEB0 is Low or OEB1 is High, the B-port is inactive and is pulled to
the level of the pull-up voltage. New data can be entered in the
flip-flop and latched modes or can be retained while the associated
outputs are in 3-State (AO port) or inactive (B port).
The LOGIC GND and BUS GND pins are isolated inside the
package to minimize noise coupling between the BTL and TTL
sides. These pins should be tied to a common ground external to the
package.
Each BTL driver has an associated BUS GND pin that acts as a
signal return path and these BUS GND pins are internally isolated
from each other. In the event of a ground return fault, a “hard” signal
failure occurs instead of a pattern dependent error that may be very
infrequent and impossible to trouble- shoot.
The B-port drivers are Low-capacitance open collectors with
controlled ramp and are designed to sink 100mA. Precision band
gap references on the B-port ensure very good noise margins by
limiting the switching threshold to a narrow region centered at 1.55V.
As with any high power device thermal considerations are
critical. It is recommended that airflow (300Ifpm) and/or thermal
mounting be used to ensure proper junction temperature.
The B-port interfaces to “Backplane Transceiver Logic” (see the
IEEE 1194.1 BTL standard). BTL features low power consumption
1999 Apr 15
SAB0
LCBA
VCC
AO7
LGOIC GND
AI7
AO6
14 15 16 17 18 19 20 21 22 23 24 25 26
3
Philips Semiconductors
Product specification
3.3V BTL 8-bit latched/registered/pass-thru
universal transceiver with 30Ω termination
FBL22033
PIN DESCRIPTION
SYMBOL
PIN NUMBER
TYPE
NAME AND FUNCTION
AI0 – AI7
50, 52, 3, 5, 8, 10, 12, 15
Input
AO0 – AO7
51, 2, 4, 6, 9, 11, 14, 16
Output
B0 – B7
40, 38, 36, 34, 32, 30, 28, 26
I/O
OEB0
23
Input
Enables the B outputs when High
OEB1
24
Input
Enables the B outputs when Low
OEA
43
Input
Enables the AO outputs when High
BUS GND
39, 37, 35, 33, 31, 29, 27, 25
GND
Bus ground (0V)
LOGIC GND
1, 13, 17, 49
GND
Logic ground (0V)
Data inputs (TTL)
3-State outputs (TTL)
Data inputs/Open Collector outputs, High current drive (BTL)
VCC
18, 22, 48
Power
Positive supply voltage
BIAS V
41
Power
Live insertion pre-bias pin
BG VCC
44
Power
Band Gap threshold voltage reference
BG GND
42
GND
Band Gap threshold voltage reference ground
SABn
20, 21
Input
Mode select from AI to B
SBAn
45, 46
Input
Mode select from B to AO
LCAB
47
Input
A-to-B clock/latch enable (transparent latch when High)
LCBA
19
Input
B-to-A clock/latch enable (transparent latch when High)
Loopback
7
Input
Enables loopback function when High (from AIn to AOn)
FUNCTION TABLE
INPUTS
MODE
AIn to Bn thru mode
AIn to Bn transparent latch
AIn to Bn latch and read
AIn to Bn register
Bn outputs latched and read
(preconditioned latch)
Bn to AOn thru mode
Bn to AOn transparent latch
Bn to AOn latch and read
Bn to AOn register
AOn outputs latched and read
(preconditioned latch)
1999 Apr 15
OUTPUTS
AIn
Bn*
OEB0
OEB1
OEA
LCAB
LCBA
SAB1
SBA1
0
0
L
—
H
L
L
X
X
LL
H
—
H
L
L
X
X
AOn
Bn
XX
Z
H**
LL
XX
Z
L
L
—
H
L
L
H
X
HX
XX
Z
H**
H
—
H
L
L
H
X
HX
XX
Z
L
l
—
H
L
L
↓
X
HX
XX
Z
H**
h
—
H
L
L
↓
X
HX
XX
Z
L
L
—
H
L
L
↑
X
LH
XX
Z
H**
H
—
H
L
L
↑
X
LH
XX
Z
L
X
—
H
L
L
L
X
HX
XX
Z
latched
data
X
L
L
H
H
X
X
XX
LL
H
input
X
H
L
H
H
X
X
XX
LL
L
input
X
L
L
H
H
X
H
XX
HX
H
input
X
H
L
H
H
X
H
XX
HX
L
input
X
l
L
H
H
X
↓
XX
HX
H
input
X
h
L
H
H
X
↓
XX
HX
L
input
X
L
L
H
H
X
↑
XX
LH
H
input
X
H
L
H
H
X
↑
XX
LH
L
input
X
X
L
H
H
X
L
XX
HX
latched
data
X
4
Philips Semiconductors
Product specification
3.3V BTL 8-bit latched/registered/pass-thru
universal transceiver with 30Ω termination
Disable Bn outputs
Disable AOn outputs
FBL22033
X
X
L
X
X
X
X
XX
XX
X
H**
X
X
X
H
X
X
X
XX
XX
X
H**
X
X
X
X
L
X
X
XX
XX
Z
X
FUNCTION SELECT TABLE
MODE SELECTED
SXX1
SXX0
L
L
Register mode
L
H
Latch mode
H
X
Thru mode
NOTES:
H =
L
=
h
=
l
=
X
=
Z
=
— =
↑
=
↓
=
H** =
Bn* =
High voltage level
Low voltage level
High voltage level one set-up time prior to the High-to-Low LCXX transition
Low voltage level one set-up time prior to the High-to-Low LCXX transition
Don’t care
High-impedance (OFF) state
Input not externally driven
Low-to-High transition
High-to-Low transition
Goes to level of pull-up voltage
Precaution should be taken to ensure B inputs do not float. If they do, they are equal to Low state.
NOTE: In Loopback mode (Loopback = High), AIn inputs are routed to the AOn outputs. The Bn inputs are blocked out.
1999 Apr 15
5
Philips Semiconductors
Product specification
3.3V BTL 8-bit latched/registered/pass-thru
universal transceiver with 30Ω termination
FBL22033
LOGIC DIAGRAM
23
OEB0
24
OEB1
SAB0
SAB1
LCAB
AIn
20
21
47
50
D
En
52,
2, 5,
8, 10,
12, 15
40
Bn
38,
36, 34,
32, 30,
28, 26
D
Clk
1 of 8 cells
LCBA
SBA0
SBA1
OEA
19
45
46
43
D
En
AOn
51
2, 4, 6, 9,
11, 14, 16
D
Clk
1 of 8 cells
BGref
Loopback
7
BGGnd
42
SG00069
ABSOLUTE MAXIMUM RATINGS
Operation beyond the limits set forth in this table may impair the useful life of the device. Unless otherwise noted these limits are over the
operating free-air temperature range.
SYMBOL
VCC
PARAMETER
Supply voltage
VIN
Input
In
ut voltage
IIN
Input current
VOUT
IOUT
TSTG
1999 Apr 15
RATING
UNIT
-0.5 to +4.6
V
AI0 – AI7, OEB0, OEBn, OEAn
-0.5 to +7.0
V
B0 – B7
-0.5 to +3.5
VIN 0
Voltage applied to output in High output state
-50
-0.5 to +7.0
Current applied to output in
Low output state/High output state
Storage temperature
AO0 – AO7
–24, 24
B0 – B7
200
-65 to +150
6
V
mA
°C
Philips Semiconductors
Product specification
3.3V BTL 8-bit latched/registered/pass-thru
universal transceiver with 30Ω termination
FBL22033
LIVE INSERTION SPECIFICATIONS
SYMBOL
PARAMETER
VBIASV
Bias pin voltage
IBIASV
Bias pin ((IBIASV) input
DC current
VBn
ILM
IHM
IBnPEAK
Bus voltage during prebias
Fall current during prebias
Rise current during prebias
Peak bus current during
insertion
IOLOFF
Power up
u current
tGR
Input glitch rejection
MIN
Voltage difference between the Bias voltage
and VCC after the PCB is plugged in.
VCC = 0 V, Bias V = 3.6V
VCC = 3.3V, Bias V = 3.6V
B0 – B7 = 0V, Bias V = 3.3V
B0 – B7 = 2V, Bias V = 1.3 to 2.5V
B0 – B7 = 1V, Bias V = 3 to 3.6V
VCC = 0 to 3.3V, B0 – B7 = 0 to 2.0V,
Bias V = 2.7 to 3.6V, OEB0 = 0.8V, tr = 2ns
VCC = 0 to 3.3V, OEB0 = 0.8V
VCC = 0 to 1.2V, OEB0 = 0 to 5V
VCC = 3.3V
–
LIMITS
TYP
–
1.62
UNIT
MAX
0.5
V
1.2
10
2.1
1
mA
µA
V
µA
µA
10
mA
100
100
µA
-1
1.0
1.35
ns
DC ELECTRICAL CHARACTERISTICS
Over recommended operating free-air temperature range unless otherwise noted.
symbol
test conditions1
parameter
arameter
IOH
High level output current
B0 – B7
IOFF
output
Power-off out
ut current
B0 – B7
VOH
O
High level output
High-level
out ut
voltage
VOL
Low-level output voltage
AO0 –
AO0 – AO73
B0 – B7
VIK
II
Input clamp voltage
Input leakage
g current
Control pins
Control/
AI0 – AI7
AI0 – AI7
Note 4
IIH
High-level input current
B0 – B7
IIL
IOZH
IOZL
Low-level in
input
ut current
Off-state output current
Off-state output current
B0 – B7
AO0 – AO7
AO0 – AO7
ICCH
ICCL
Supply
Su
ly current (total)
ICCZ
Supply current
ICCH
ICCL
Supply
Su
ly current (total)
B→A
A→B
limits
typ2
VCC = MAX, VIL = MAX, VOH = 1.9V
VCC = 0V, VIL = MAX, VOH = 1.9V
VCC = 0V, VIL = MAX, VOH = 1.9V@85°C
VCC = MIN to MAX; IOH = -100µA
AO73
min
VCC = MIN; IOH = -8mA
VCC = MIN; IOH = -32mA
VCC = MIN; IOL = 16mA
VCC = MIN; IOL = 32mA
VCC = MIN, IOL = 4mA
VCC = MIN, IOL = 100mA
VCC = MIN, II = IIK = –18mA
VCC = 3.6V; VI = VCC or 300mV
max
100
100
300
VCC
–0.2
2.4
2.0
µA
µA
V
0.4
0.8
0.5
0.75
unit
1.0
–0.85
1.20
-1.2
±1.0
VCC = 0V or 3.6V; VI = 5.5V
10
VCC = 3.6V; VI = VCC
VCC = 3.6V; VI = 300mV
MAX VI = 1
9V
VCC = MAX,
1.9V
VCC = MAX, VI = 3.5V, note 5
VCC = MAX, VI = 3.75V, Note 5 @ –40°C
VCC = MAX,
MAX VI = 0.75V
0 75V
VCC = MAX, VO =3V
VCC = MAX, VO = 0.5V
VCC = MAX, outputs High
VCC = MAX, outputs Low
VCC = MAX
VCC = MAX, outputs High
VCC = MAX, outputs Low
VCC = MAX
1
–5
100
100
100
V
V
V
V
V
V
µA
µ
µA
mA
14
17
22
14
9
14
-100
5
-5
31
38
55
32
18
33
µA
µA
µA
mA
mA
mA
ICCZ
Supply current
mA
NOTES:
1. For conditions shown as MIN or MAX, use the appropriate value specified under recommended operation conditions for the applicable type.
2. All typical values are at VCC = 3.3V, TA = 25°C.
3. Due to test equipment limitations, actual test conditions are VIH = 1.8V and VIL = 1.3V for the B side.
4. Unused pins are at VCC or GND.
5. For B port input voltage between 3 and 5 volt; IIH will be greater than 100mA but the part will continue to function normally (clamping circuit
is active).
1999 Apr 15
7
Philips Semiconductors
Product specification
3.3V BTL 8-bit latched/registered/pass-thru
universal transceiver with 30Ω termination
FBL22033
AC ELECTRICAL CHARACTERISTICS INDUSTRIAL AND COMMERCIAL (A TO B)
SYMBOL
PARAMETER
Tamb = +25°C, VCC = 3.3V,
RL = 9Ω
TEST CONDITION
Tamb = –40 to +85°C,
VCC = 3.3V±10%,
RL = 9Ω
UNIT
MIN
TYP
MAX
MIN
MAX
tPLH
tPHL
Propagation delay,
An to Bn through latch
1.2
1.2
2.7
2.6
4.8
4.3
1.0
1.0
5.3
4.9
ns
tPLH
tPHL
Propagation delay,
An to Bn transparent latch
1.3
1.8
3.2
3.7
5.2
5.6
1.0
1.6
6.1
6.3
ns
tPLH
tPHL
Propagation delay,
LCAB to Bn latch
2.0
2.3
3.8
4.3
5.8
6.3
1.2
1.8
7.0
7.3
ns
tPLH
tPHL
Propagation delay,
LCAB to Bn register
2.1
2.0
3.8
4.3
5.7
6.5
1.4
1.8
6.9
7.3
ns
tPLH
tPHL
Propagation delay,
SABX to Bn inverting
1.2
2.3
4.3
5.1
7.6
8.0
1.0
2.0
9.2
8.7
ns
tPLH
tPHL
Propagation delay,
SABX to Bn non-inverting
1.8
1.8
4.0
5.0
6.4
8.5
1.1
1.6
8.0
9.8
ns
tPLH
tPHL
OEBn to Bn
1.6
1.6
3.4
3.4
5.4
5.3
1.0
1.0
6.0
7.2
ns
AC ELECTRICAL CHARACTERISTICS INDUSTRIAL AND COMMERCIAL (A TO B)
SYMBOL
PARAMETER
Tamb = +25°C, VCC = 3.3V,
RL = 16.5Ω
TEST CONDITION
Tamb = –40 to +85°C,
VCC = 3.3V±10%,
RL = 16.5Ω
UNIT
MIN
TYP
MAX
MIN
MAX
tPLH
tPHL
Propagation delay,
An to Bn through latch
1.2
1.2
2.8
2.4
4.5
4.0
1.0
1.0
5.7
4.6
ns
tPLH
tPHL
Propagation delay,
An to Bn transparent latch
1.4
1.7
3.2
3.5
5.1
5.4
1.0
1.3
6.1
5.9
ns
tPLH
tPHL
Propagation delay,
LCAB to Bn latch
2.0
2.2
3.8
4.1
5.6
6.1
1.3
1.6
6.9
7.0
ns
tPLH
tPHL
Propagation delay,
LCAB to Bn register
2.0
2.2
3.9
4.1
5.9
6.1
1.2
1.6
7.7
7.0
ns
tPLH
tPHL
Propagation delay,
SABX to Bn inverting
1.2
1.8
4.6
4.7
8.6
7.9
1.0
1.6
10.4
8.7
ns
tPLH
tPHL
Propagation delay,
SABX to Bn non-inverting
1.3
1.5
4.5
4.6
8.2
8.2
1.0
1.2
10.0
9.1
ns
tPLH
tPHL
OEBn to Bn
1.5
1.5
3.4
3.2
5.2
5.0
1.0
1.0
6.3
7.0
ns
1999 Apr 15
8
Philips Semiconductors
Product specification
3.3V BTL 8-bit latched/registered/pass-thru
universal transceiver with 30Ω termination
FBL22033
AC ELECTRICAL CHARACTERISTICS INDUSTRIAL AND COMMERCIAL (B TO A)
SYMBOL
PARAMETER
TEST CONDITION
Tamb = +25°C, VCC = 3.3V
Tamb = –40 to +85°C,
VCC = 3.3V±10%
MIN
TYP
MAX
MIN
MAX
UNIT
tPLH
tPHL
Propagation delay,
Bn to An through mode
2.2
2.9
4.6
5.4
7.0
7.8
1.6
2.5
8.1
9.2
ns
tPLH
tPHL
Propagation delay,
Bn to An transparent latch
3.1
3.0
5.6
5.6
8.1
8.1
2.1
2.8
9.6
9.4
ns
tPLH
tPHL
Propagation delay,
LCAB to An latch
1.9
1.7
3.7
3.5
6.1
5.2
1.3
1.2
7.5
6.0
ns
tPLH
tPHL
Propagation delay,
LCAB to An register
1.7
2.3
3.9
4.3
6.0
6.2
1.1
1.9
7.1
7.0
ns
tPLH
tPHL
Propagation delay,
SABX to An inverting
2.1
2.6
4.5
4.9
6.8
7.1
1.6
2.1
8.2
7.7
ns
tPLH
tPHL
Propagation delay,
SABX to An non-inverting
1.2
1.9
4.1
4.3
9.2
6.6
1.0
1.6
9.9
7.5
ns
tPLH
tPHL
Propagation delay,
AIn to AOn loopback
2.2
2.2
4.5
4.5
6.7
6.7
1.5
1.6
7.9
7.8
ns
tPLH
tPHL
Propagation delay,
LPBK to An non-inverting or inverting
1.7
1.2
4.6
5.4
7.5
9.6
1.5
1.0
9.3
11.1
ns
tPZH
tPHZ
Propagation delay,
OEA to An
2.1
2.3
4.6
5.2
6.8
8.1
1.8
2.0
7.7
9.2
ns
tPZH
tPHZ
Propagation delay,
OEA to An
2.0
1.2
4.5
3.0
7.0
4.7
1.8
1.0
7.6
5.3
ns
1999 Apr 15
9
Philips Semiconductors
Product specification
3.3V BTL 8-bit latched/registered/pass-thru
universal transceiver with 30Ω termination
FBL22033
AC SETUP REQUIREMENTS INDUSTRIAL AND COMMERCIAL
LIMITS
SYMBOL
PARAMETER
TEST
CONDITION
Tamb = +25°C, VCC
= 3.3V
Tamb = –40 to +85°C,
VCC = 3.3V±10%
UNIT
CL = 50pF (A side) / CD = 30pF (B side)
RL = 500Ω (A side) / RU = 9Ω (B side)
MIN
MIN
ts(H)
ts(L)
Setup time
AIn to LCAB or Bn to LCBA
3.0
3.0
4.0
4.0
ns
th(H)
th(L)
Hold time (latch mode)
AIn to LCAB
6.0
5.0
6.5
5.5
ns
th(H)
th(L)
Hold time (register mode)
AIn to LCAB
1.0
1.0
1.3
1.3
ns
th(H)
th(L)
Hold time (latch mode)
Bn to LCAB
1.5
1.5
2.0
2.0
ns
th(H)
th(L)
Hold time (register mode)
Bn to LCAB
1.0
1.0
1.3
1.3
ns
tw(H)
tw(L)
Pulse width, High or Low
AIn to LCAB or Bn to LCBA
3.0
3.0
4.0
4.0
ns
AC SETUP REQUIREMENTS INDUSTRIAL AND COMMERCIAL
LIMITS
SYMBOL
PARAMETER
TEST
CONDITION
Tamb = +25°C, VCC
= 3.3V
Tamb = –40 to +85°C,
VCC = 3.3V±10%
UNIT
CL = 50pF (A side) / CD = 30pF (B side)
RL = 500Ω (A side) / RU = 16.5Ω (B side)
MIN
MIN
ts(H)
ts(L)
Setup time
AIn to LCAB or Bn to LCBA
3.0
3.0
4.0
4.0
ns
th(H)
th(L)
Hold time (latch mode)
AIn to LCAB
6.0
5.0
6.5
5.5
ns
th(H)
th(L)
Hold time (register mode)
AIn to LCAB
1.0
1.0
1.3
1.3
ns
th(H)
th(L)
Hold time (latch mode)
Bn to LCAB
1.5
1.5
2.0
2.0
ns
th(H)
th(L)
Hold time (register mode)
Bn to LCAB
1.0
1.0
1.3
1.3
ns
tw(H)
tw(L)
Pulse width, High or Low
AIn to LCAB or Bn to LCBA
3.0
3.0
4.0
4.0
ns
1999 Apr 15
10
Philips Semiconductors
Product specification
3.3V BTL 8-bit latched/registered/pass-thru
universal transceiver with 30Ω termination
FBL22033
AC WAVEFORMS
VM
Input
tPLH
VM
tPLH
Output
VM
VM
Waveform 2. Propagation Delay for Data
or Output Enable to Output
ÍÍÍ
ÍÍÍÍ
ÍÍ
ÍÍÍÍÍÍÍÍÍ
AIn, Bn
VM
VM
ts
tSK(o)
AOn, Bn
VM
tPHL
Waveform 1. Propagation Delay for Data
or Output Enable to Output
AIn, Bn
VM
tPHL
VM
Output
Input
VM
LCAB, LCBA
VM
th
VM
ts
tw(L)
tw(H)
th
VM
1/fMAX
Waveform 3. Output to Output Skew
OEA
VM
VM
tPZH
AOn
Waveform 4. Setup and Hold Times,
Pulse Widths and Maximum Frequency
OEA
tPHZ
VM
VOH -0.3V
VM
VM
tPZL
OV
AOn
Waveform 5. 3-State Output Enable Time to High Level
and Output Disable Time from High Level
tPLZ
VM
VOL +0.3V
Waveform 6. 3-State Output Enable Time to Low Level
and Output Disable Time from Low Level
NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance.
SG00070
1999 Apr 15
11
Philips Semiconductors
Product specification
3.3V BTL 8-bit latched/registered/pass-thru
universal transceiver with 30Ω termination
FBL22033
TEST CIRCUIT AND WAVEFORMS
VCC
VIN
RL
VOUT
PULSE
GENERATOR
tW
90%
7.0V
NEGATIVE
PULSE
VM
VM
10%
D.U.T.
RT
CL
AMP (V)
90%
RL
10%
tTHL
(tf)
tTLH
(tr)
LOW V
tTLH
(tr)
tTHL
(tf)
AMP (V)
90%
90%
POSITIVE
PULSE
Test Circuit for 3-State Outputs on A Port
LOW V
VM = 1.55V for Bn, VM = 1.5V for all others.
Input Pulse Definitions
SWITCH
tPLZ, tPZL
All other
closed
open
VCC
BIAS
V
VIN
2.0V (for RU = 9 Ω)
2.1V (for RU = 16.5 Ω)
VOUT
PULSE
GENERATOR
RU
D.U.T.
RT
Test Circuit for Outputs on B Port
1999 Apr 15
10%
tW
SWITCH POSITION
TEST
VM
VM
10%
CD
INPUT PULSE REQUIREMENTS
Family
FB+
Amplitude
Low V
Rep. Rate
A Port
3.0V
0.0V
1MHz
500ns 2.5ns
2.5ns
B Port
2.0V
1.0V
1MHz
500ns 2.0ns
2.0ns
tW
tTLH
tTHL
DEFINITIONS:
RL = Load Resistor; see AC CHARACTERISTICS for value.
CL = Load capacitance includes jig and probe capacitance; see AC
CHARACTERISTICS for value.
RT = Termination resistance should be equal to ZOUT of pulse generators.
CD = Load capacitance includes jig and probe capacitance; see AC
CHARACTERISTICS for value.
RU = Pull up resistor; see AC CHARACTERISTICS for value.
SG00063
12
Philips Semiconductors
Product specification
3.3V BTL 8-bit latched/registered/pass-thru
Futurebus+ universal interface transceiver
QFP52: plastic quad flat package; 52 leads (lead length 1.6 mm); body 10 x 10 x 2.0 mm
1999 Apr 15
13
FBL22033
SOT379-1
Philips Semiconductors
Product specification
3.3V BTL 8-bit latched/registered/pass-thru
Futurebus+ universal interface transceiver
FBL22033
Data sheet status
Data sheet
status
Product
status
Definition [1]
Objective
specification
Development
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
Preliminary
specification
Qualification
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
Product
specification
Production
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
 Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
print code
Document order number:
yyyy mmm dd
14
Date of release: 07-98
9397-750-05518