AD AD7825BRU 3 v/5 v, 2 msps, 8-bit, 1-, 4-, 8-channel sampling adc Datasheet

a
3 V/5 V, 2 MSPS, 8-Bit, 1-, 4-, 8-Channel
Sampling ADCs
AD7822/AD7825/AD7829
FEATURES
8-Bit Half-Flash ADC with 420 ns Conversion Time
1, 4 and 8 Single-Ended Analog Input Channels
Available with Input Offset Adjust
On-Chip Track-and-Hold
SNR Performance Given for Input Frequencies Up to
10 MHz
On-Chip Reference (2.5 V)
Automatic Power-Down at the End of Conversion
Wide Operating Supply Range
3 V ⴞ 10% and 5 V ⴞ 10%
Input Ranges
0 V to 2 V p-p, VDD = 3 V ⴞ 10%
0 V to 2.5 V p-p, VDD = 5 V ⴞ 10%
Flexible Parallel Interface with EOC Pulse to Allow
Stand-Alone Operation
APPLICATIONS
Data Acquisition Systems, DSP Front Ends
Disk Drives
Mobile Communication Systems, Subsampling
Applications
GENERAL DESCRIPTION
The AD7822, AD7825, and AD7829 are high speed, 1-, 4-, and
8-channel, microprocessor-compatible, 8-bit analog-to-digital
converters with a maximum throughput of 2 MSPS. The AD7822,
AD7825, and AD7829 contain an on-chip reference of 2.5 V
(2% tolerance), a track/hold amplifier, a 420 ns 8-bit half-flash
ADC and a high speed parallel interface. The converters can
operate from a single 3 V ± 10% and 5 V ± 10% supply.
The AD7822, AD7825, and AD7829 combine the convert start
and power-down functions at one pin, i.e., the CONVST pin.
This allows a unique automatic power-down at the end of a
conversion to be implemented. The logic level on the CONVST
pin is sampled after the end of a conversion when an EOC (End
of Conversion) signal goes high, and if it is logic low at that
point, the ADC is powered down. The AD7822 and AD7825
also have a separate power-down pin. (See Operating Modes
section of the data sheet.)
The parallel interface is designed to allow easy interfacing to
microprocessors and DSPs. Using only address decoding logic,
the parts are easily mapped into the microprocessor address
space. The EOC pulse allows the ADCs to be used in a standalone manner. (See Parallel Interface section of the data sheet.)
FUNCTIONAL BLOCK DIAGRAM
VDD
CONVST EOC A0* A1* A2* PD*
CONTROL
LOGIC
VIN1
VIN2*
VIN3*
VIN4*
VIN5*
VIN6*
VIN7*
VIN8*
COMP
2.5V
REF
BUF
INPUT
MUX
T/H
VMID
*A0, A1
*A2
*PD
*VIN2 TO VIN4
*VIN4 TO VIN8
8-BIT
HALF
FLASH
ADC
AGND
DGND
PARALLEL
PORT
VREFIN / OUT
DB7
DB0
CS RD
AD7825/AD7829
AD7829
AD7822/AD7825
AD7825/AD7829
AD7829
The AD7822 and AD7825 are available in a 20-/24-lead 0.3"
wide, plastic dual-in-line package (DIP), a 20-/24-lead small outline IC (SOIC) and a 20-/24-lead thin shrink small outline package
(TSSOP). The AD7829 is available in a 28-lead 0.6" wide, plastic
dual-in-line package (DIP), a 28-lead small outline IC (SOIC) and
in a 28-lead thin shrink small outline package (TSSOP).
PRODUCT HIGHLIGHTS
1. Fast Conversion Time
The AD7822, AD7825, and AD7829 have a conversion time
of 420 ns. Faster conversion times maximize the DSP processing time in a real-time system.
2. Analog Input Span Adjustment
The VMID pin allows the user to offset the input span. This
feature can reduce the requirements of single-supply op amps
and take into account any system offsets.
3. FPBW (Full Power Bandwidth) of Track-and-Hold
The track-and-hold amplifier has an excellent high-frequency
performance. The AD7822, AD7825, and AD7829 are
capable of converting full-scale input signals up to a frequency of 10 MHz. This makes the parts ideally suited to
subsampling applications.
4. Channel Selection
Channel selection is made without the necessity of writing to
the part.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
(V
AD7822/AD7825/AD7829–SPECIFICATIONS
V
= 2.5 V. All specifications –40ⴗC to +85ⴗC unless otherwise noted.)
DD
= 3 V ⴞ 10%, VDD = 5 V ⴞ 10%, GND = 0 V,
REF IN/OUT
Parameter
DYNAMIC PERFORMANCE
Signal to (Noise + Distortion) Ratio1
Total Harmonic Distortion1
Peak Harmonic or Spurious Noise1
Intermodulation Distortion1
2nd Order Terms
3rd Order Terms
Channel-to-Channel Isolation1
DC ACCURACY
Resolution
Minimum Resolution for Which
No Missing Codes Are Guaranteed
Integral Nonlinearity (INL)1
Differential Nonlinearity (DNL)1
Gain Error1
Gain Error Match1
Offset Error1
Offset Error Match1
ANALOG INPUTS2
VDD = 5 V ± 10%
VIN1 to VIN8 Input Voltage
Version B
Unit
48
–55
–55
dB min
dB max
dB max
–65
–65
–70
dB typ
dB typ
dB typ
8
Bits
8
± 0.75
± 0.75
±2
± 0.1
±1
± 0.1
Bits
LSB max
LSB max
LSB max
LSB typ
LSB max
LSB typ
fIN = 30 kHz. fSAMPLE = 2 MHz
fa = 27.3 kHz, fb = 28.3 kHz
V max
V min
V max
V min
VDD
0
VDD – 1
1
±1
15
6
V max
V min
V max
V min
µA max
pF max
kΩ typ
2.55
2.45
1
100
V max
V min
µA typ
µA max
ON-CHIP REFERENCE
Reference Error
Temperature Coefficient
± 50
50
mV max
ppm/°C typ
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
Input Capacitance, CIN
2.4
0.8
2
0.4
±1
10
V min
V max
V min
V max
µA max
pF max
4
2.4
V min
V min
0.4
0.2
±1
10
V max
V max
µA max
pF max
VDD = 3 V ± 10%
VIN1 to VIN8 Input Voltage
VMID Input Voltage
VIN Input Leakage Current
VIN Input Capacitance
VMID Input Impedance
REFERENCE INPUT
VREF IN/OUT Input Voltage Range
Input Current
Default VMID = 1.25 V
Input Voltage Span = 2 V
Default VMID = 1 V
2.5 V + 2%
2.5 V – 2%
Nominal 2.5 V
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
High Impedance Leakage Current
High Impedance Capacitance
fIN = 20 kHz
See Analog Input Section
Input Voltage Span = 2.5 V
VDD
0
VDD – 1.25
1.25
VMID Input Voltage
Test Condition/Comment
–2–
VDD = 5 V ± 10%
VDD = 5 V ± 10%
VDD = 3 V ± 10%
VDD = 3 V ± 10%
Typically 10 nA, VIN = 0 V to VDD
ISOURCE = 200 µA
VDD = 5 V ± 10%
VDD = 3 V ± 10%
ISINK = 200 µA
VDD = 5 V ± 10%
VDD = 3 V ± 10%
REV. B
AD7822/AD7825/AD7829
Parameter
Version B
Unit
Test Condition/Comment
CONVERSION RATE
Track/Hold Acquisition Time
Conversion Time
200
420
ns max
ns max
See Functional Description Section
POWER SUPPLY REJECTION
VDD ± 10%
±1
LSB max
4.5
5.5
2.7
3.3
V min
V max
V min
V max
5 V ± 10%. For Specified Performance
12
5
0.2
mA max
µA max
µA typ
8 mA Typically
Logic Inputs = 0 V or VDD
36
mW max
9.58
23.94
mW typ
mW typ
POWER REQUIREMENTS
VDD
VDD
IDD
Normal Operation
Power-Down
Power Dissipation
Normal Operation
Power-Down
200 kSPS
500 kSPS
3 V ± 10%. For Specified Performance
VDD = 3 V
Typically 24 mW
NOTES
1
See Terminology section of this data sheet.
2
Refer to the Analog Input section for an explanation of the Analog Input(s).
Specifications subject to change without notice.
ORDERING GUIDE
200␮A
IOL
TO
OUTPUT
PIN
2.1V
CL
50pF
200␮A
IOH
Figure 1. Load Circuit for Access Time and Bus
Relinquish Time
REV. B
–3–
Model
Linearity
Error
Package
Description
Package
Option
AD7822BN
AD7822BR
AD7822BRU
± 0.75 LSB
± 0.75 LSB
± 0.75 LSB
N-20
R-20
RU-20
AD7825BN
AD7825BR
AD7825BRU
± 0.75 LSB
± 0.75 LSB
± 0.75 LSB
AD7829BN
AD7829BR
AD7829BRU
± 0.75 LSB
± 0.75 LSB
± 0.75 LSB
Plastic DIP
Small Outline IC
Thin Shrink Small
Outline (TSSOP)
Plastic DIP
Small Outline IC
Thin Shrink Small
Outline (TSSOP)
Plastic DIP
Small Outline IC
Thin Shrink Small
Outline (TSSOP)
N-24
R-24
RU-24
N-28
R-28
RU-28
AD7822/AD7825/AD7829
TIMING CHARACTERISTICS1, 2 (V
Parameter 5 V ⴞ 10%
t1
t2
t3
t4
t5
t6
t7
t8
t9 3
t104
t11
t12
t13
tPOWER UP
tPOWER UP
420
20
30
110
70
10
0
0
30
10
5
20
10
15
200
25
1
REF IN/OUT
= 2.5 V. All specifications –40ⴗC to +85ⴗC unless otherwise noted.)
3 V ⴞ 10%
Unit
Conditions/Comments
420
20
30
110
70
10
0
0
30
20
5
20
10
15
200
25
1
ns max
ns min
ns min
ns max
ns min
ns max
ns min
ns min
ns min
ns max
ns min
ns max
ns min
ns min
ns min
µs typ
µs max
Conversion Time.
Minimum CONVST Pulsewidth.
Minimum time between the rising edge of RD and next falling edge of convert start.
EOC Pulsewidth.
RD rising edge to EOC pulse high.
CS to RD setup time.
CS to RD hold time.
Minimum RD Pulsewidth.
Data access time after RD low.
Bus relinquish time after RD high.
Address setup time before falling edge of RD.
Address hold time after falling edge of RD.
Minimum time between new channel selection and convert start.
Power-up time from rising edge of CONVST using on-chip reference.
Power-up time from rising edge of CONVST using external 2.5 V reference.
NOTES
1
Sample tested to ensure compliance.
2
See Figures 20, 21, and 22.
3
Measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V with V DD = 5 V ± 10%, and time required for
an output to cross 0.4 V or 2.0 V with V DD = 3 V ± 10%.
4
Derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back
to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t 10, quoted in the timing characteristics is the true bus relinquish time
of the part and as such is independent of external bus loading capacitances.
SOIC Package, Power Dissipation . . . . . . . . . . . . . . . 450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 75°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
TSSOP Package, Power Dissipation . . . . . . . . . . . . . 450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 128°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
ESD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 kV
ABSOLUTE MAXIMUM RATINGS*
(TA = 25°C unless otherwise noted)
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Analog Input Voltage to AGND
VIN1 to VIN8 . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Reference Input Voltage to AGND . . . –0.3 V to VDD + 0.3 V
VMID Input Voltage to AGND . . . . . . . –0.3 V to VDD + 0.3 V
Digital Input Voltage to DGND . . . . . –0.3 V to VDD + 0.3 V
Digital Output Voltage to DGND . . . . –0.3 V to VDD + 0.3 V
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Plastic DIP Package, Power Dissipation . . . . . . . . . . 450 mW
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 105°C/W
Lead Temperature, (Soldering, 10 sec) . . . . . . . . . . . 260°C
*Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7822/AD7825/AD7829 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore,
proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
–4–
WARNING!
ESD SENSITIVE DEVICE
REV. B
AD7822/AD7825/AD7829
PIN FUNCTION DESCRIPTIONS
Mnemonic
Description
VIN1 to VIN8
Analog Input Channels. The AD7822 has a single input channel; the AD7825 and AD7829 have four and eight
analog input channels respectively. The inputs have an input span of 2.5 V and 2 V depending on the supply voltage (VDD). This span may be centered anywhere in the range AGND to VDD using the VMID Pin. The
default input range (VMID unconnected) is AGND to 2 V (VDD = 3 V ± 10%) or AGND to 2.5 V (VDD = 5 V
± 10%). See Analog Input section of the data sheet for more information.
Positive supply voltage, 3 V ± 10% and 5 V ± 10%.
Analog Ground. Ground reference for track/hold, comparators, reference circuit and multiplexer.
Digital Ground. Ground reference for digital circuitry.
Logic Input Signal. The convert start signal initiates an 8-bit analog-to-digital conversion on the falling edge of
this signal. The falling edge of this signal places the track/hold in hold mode. The track/hold goes into track
mode again 120 ns after the start of a conversion. The state of the CONVST signal is checked at the end of
a conversion. If it is logic low, the AD7822/AD7825/AD7829 will power down. (See Operating Modes section
of the data sheet.)
Logic Output. The End of Conversion signal indicates when a conversion has finished. The signal can be used
to interrupt a microcontroller when a conversion has finished or latch data into a gate array. (See Parallel Interface section of this data sheet.)
Logic input signal. The chip select signal is used to enable the parallel port of the AD7822, AD7825, and AD7829.
This is necessary if the ADC is sharing a common data bus with another device.
Logic Input. The Power-Down pin is present on the AD7822 and AD7825 only. Bringing the PD pin low
places the AD7822 and AD7825 in Power-Down mode. The ADCs will power up when PD is brought logic
high again.
Logic Input Signal. The read signal is used to take the output buffers out of their high impedance state and
drive data onto the data bus. The signal is internally gated with the CS signal. Both RD and CS must be logic
low to enable the data bus.
Channel Address Inputs. The address of the next multiplexer channel must be present on these inputs when the
RD signal goes low.
Data Output Lines. They are normally held in a high impedance state. Data is driven onto the data bus when
both RD and CS go active low.
Analog Input and Output. An external reference can be connected to the AD7822, AD7825, and AD7829 at this
pin. The on-chip reference is also available at this pin. When using the internal reference, this pin can be
left unconnected or, in some cases, it can be decoupled to AGND with a 0.1 ␮F capacitor.
VDD
AGND
DGND
CONVST
EOC
CS
PD
RD
A0–A2
DB0–DB7
VREF IN/OUT
PIN CONFIGURATIONS
DIP/SOIC/TSSOP
20 DB3
DB2 1
DB1 2
DB0 3
CONVST 4
CS 5
AD7822
DB1 2
23 DB4
18 DB5
DB0 3
22 DB5
17 DB6
CONVST 4
21 DB6
16 DB7
CS 5
TOP VIEW 15 AGND
(Not to Scale)
14 VDD
DGND 7
13 VREF IN / OUT
RD 6
AD7825
20 DB7
TOP VIEW 19 AGND
DGND 7 (Not to Scale) 18 VDD
EOC 8
17 VREF IN /OUT
A1 9
PD 9
12 VMID
16 VMID
A0 10
15 VIN1
NC 10
11 VIN1
PD 11
14 VIN2
VIN4 12
13 VIN3
NC = NO CONNECT
REV. B
24 DB3
19 DB4
RD 6
EOC 8
DB2 1
–5–
DB2 1
28 DB3
DB1 2
27 DB4
DB0 3
26 DB5
CONVST 4
25 DB6
CS 5
24 DB7
RD 6
DGND 7
23 AGND
AD7829
22 VDD
TOP VIEW
EOC 8 (Not to Scale) 21 VREF IN / OUT
A2 9
20 VMID
A1 10
19 VIN1
A0 11
18 VIN2
VIN8 12
17 VIN3
VIN7 13
16 VIN4
VIN6 14
15 VIN5
AD7822/AD7825/AD7829
Relative Accuracy
TERMINOLOGY
Signal-to-(Noise + Distortion) Ratio
Relative accuracy or endpoint nonlinearity is the maximum
deviation from a straight line passing through the endpoints of
the ADC transfer function.
This is the measured ratio of signal-to-(noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the rms sum of all nonfundamental
signals up to half the sampling frequency (fS/2), excluding dc.
The ratio is dependent upon the number of quantization levels
in the digitization process; the more levels, the smaller the quantization noise. The theoretical signal-to-(noise + distortion) ratio
for an ideal N-bit converter with a sine wave input is given by:
Differential Nonlinearity
The difference between the measured and the ideal 1 LSB change
between any two adjacent codes in the ADC.
Offset Error
The deviation of the 128th code transition (01111111) to
(10000000) from the ideal, i.e., VMID.
Signal-to-(Noise + Distortion) = (6.02N + 1.76) dB
Offset Error Match
Thus, for an 8-bit converter, this is 50 dB.
The difference in offset error between any two channels.
Total Harmonic Distortion
Zero-Scale Error
Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7822/AD7825/AD7829
it is defined as:
THD (dB) = 20 log
The deviation of the first code transition (00000000) to
(00000001) from the ideal, i.e., VMID – 1.25 V + 1 LSB (VDD =
5 V ± 10%), or VMID – 1.0 V + 1 LSB (VDD = 3 V ± 10%).
Full-Scale Error
V22 +V32 +V42 +V52 +V62
The deviation of the last code transition (11111110) to
(11111111) from the ideal, i.e., VMID + 1.25 V – 1 LSB (VDD =
5 V ± 10%), or VMID + 1.0 V – 1 LSB (VDD = 3 V ± 10%).
V1
where V1 is the rms amplitude of the fundamental and V2, V3,
V4, V5, and V6 are the rms amplitudes of the second through the
sixth harmonics.
Gain Error
The deviation of the last code transition (1111 . . . 110) to
(1111 . . . 111) from the ideal, i.e., VREF – 1 LSB, after the offset error has been adjusted out.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for parts
where the harmonics are buried in the noise floor, it will be a
noise peak.
Gain Error Match
The difference in gain error between any two channels.
Track/Hold Acquisition Time
Intermodulation Distortion
The time required for the output of the track/hold amplifier to
reach its final value, within ± 1/2 LSB, after the point at which
the track/hold returns to track mode. This happens approximately 120 ns after the falling edge of CONVST.
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which
neither m nor n are equal to zero. For example, the second order
terms include (fa + fb) and (fa – fb), while the third order terms
include (2fa + fb), (2fa – fb), (fa + 2fb) and (fa – 2fb).
It also applies to situations where a change in the selected input
channel takes place or where there is a step input change on the
input voltage applied to the selected VIN input of the AD7822/
AD7825/AD7829. It means that the user must wait for the duration of the track/hold acquisition time after a channel change/step
input change to VIN before starting another conversion, to
ensure that the part operates to specification.
The AD7822/AD7825/AD7829 are tested using the CCIF standard where two input frequencies near the top end of the input
bandwidth are used. In this case, the second and third order
terms are of different significance. The second order terms are
usually distanced in frequency from the original sine waves
while the third order terms are usually at a frequency close to
the input frequencies. As a result, the second and third order
terms are specified separately. The calculation of the intermodulation distortion is as per the THD specification where it is the
ratio of the rms sum of the individual distortion products to the
rms amplitude of the fundamental expressed in dBs.
PSR (Power Supply Rejection)
Variations in power supply will affect the full-scale transition,
but not the converter’s linearity. Power supply rejection is the
maximum change in the full-scale transition point due to a
change in power supply voltage from the nominal value.
CIRCUIT DESCRIPTION
The AD7822, AD7825, and AD7829 consist of a track-and-hold
amplifier followed by a half-flash analog-to-digital converter.
These devices use a half-flash conversion technique where one
4-bit flash ADC is used to achieve an 8-bit result. The 4-bit
flash ADC contains a sampling capacitor followed by fifteen
comparators that compare the unknown input to a reference
ladder to achieve a 4-bit result. This first flash, i.e., coarse conversion, provides the 4 MSBs. For a full 8-bit reading to be
realized, a second flash, i.e., a fine conversion, must be performed to provide the 4 LSBs. The 8-bit word is then placed on
the data output bus.
Channel-to-Channel Isolation
Channel-to-channel isolation is a measure of the level of crosstalk
between channels. It is measured by applying a full-scale 20 kHz
sine wave signal to one input channel and determining how
much that signal is attenuated in each of the other channels.
The figure given is the worst case across all four or eight channels of the AD7825 and AD7829, respectively.
–6–
REV. B
AD7822/AD7825/AD7829
Figures 2 and 3 below show simplified schematics of the ADC.
When the ADC starts a conversion, the track-and-hold goes into
hold mode and holds the analog input for 120 ns. This is the
acquisition phase as shown in Figure 2, when Switch 2 is in Position A. At the point when the track-and-hold returns to its track
mode, this signal is sampled by the sampling capacitor as Switch 2
moves into Position B. The first flash occurs at this instant and
is then followed by the second flash. Typically, the first flash is
complete after 100 ns, i.e., at 220 ns, while the end of the second
flash and hence the 8-bit conversion result is available at 330 ns
(minimum). The maximum conversion time is 420 ns. As shown
in Figure 4, the track-and-hold returns to track mode after 120 ns,
and starts the next acquisition before the end of the current
conversion. Figure 6 shows the ADC transfer function.
120ns
TRACK
CONVST
Figure 4. Track-and-Hold Timing
TYPICAL CONNECTION DIAGRAM
Figure 5 shows a typical connection diagram for the AD7822,
AD7825, and AD7829. The AGND and DGND are connected
together at the device for good noise suppression. The parallel
interface is implemented using an 8-bit data bus. The end of
conversion signal (EOC) idles high, the falling edge of CONVST
initiates a conversion and at the end of conversion the falling
edge of EOC is used to initiate an Interrupt Service Routine
(ISR) on a microprocessor. (See Parallel Interface section for
more details.) VREF and VMID are connected to a voltage source
such as the AD780, while VDD is connected to a voltage source
that can vary from 4.5 V to 5.5 V. (See Table I in Analog Input
section.) When VDD is first connected, the AD7822, AD7825, and
AD7829 power up in a low current mode, i.e., power-down, with
the default logic level on the EOC pin on the AD7822 and
AD7825 equal to a low. Ensure the CONVST line is not floating
when VDD is applied, as this could put the AD7822/AD7825/
AD7829 into an unknown state. A suggestion is to tie CONVST
to VDD or DGND through a pull-up or pull-down resistor. A rising
edge on the CONVST pin will cause the AD7829 to fully power up
while a rising edge on the PD pin will cause the AD7822 and
AD7825 to fully power up. For applications where power
consumption is of concern, the automatic power-down at the
end of a conversion should be used to improve power performance.
(See Power-Down Options section of the data sheet.)
D5
HOLD
SAMPLING
CAPACITOR
R14
13
OUTPUT
DRIVERS
14
B
OUTPUT
REGISTER
T/H 1
D4
D3
D2
R13
D1
D0
1
VALID
DATA
DB0–DB7
D6
DECODE
LOGIC
VIN
t3
RD
D7
R15
SW2
t1
CS
R16
A
HOLD
t2
EOC
REFERENCE
15
TRACK
HOLD
R1
TIMING AND
CONTROL
LOGIC
Figure 2. ADC Acquisition Phase
REFERENCE
2.5V
AD780
SUPPLY
4.5V TO 5.5V
10␮F
0.1␮F
PARALLEL
INTERFACE
R16
15
SW2
R14
13
OUTPUT
DRIVERS
HOLD
SAMPLING
CAPACITOR
OUTPUT
REGISTER
B
VIN1
1.25V TO
3.75V INPUT
D4
VIN2
D3
D2
R13
VIN4(8)
D1
1
VMID
EOC
AD7822/
AD7825/
AD7829
RD
CS
CONVST
A0
D0
AGND
R1
DGND
TIMING AND
CONTROL
LOGIC
A1
A2
PD
Figure 5. Typical Connection Diagram
Figure 3. ADC Conversion Phase
REV. B
VREF
DB0–DB7
D5
14
T/H 1
VDD
D6
R15
DECODE
LOGIC
A
VIN
D7
–7–
␮C/␮P
AD7822/AD7825/AD7829
ADC TRANSFER FUNCTION
The output coding of the AD7822, AD7825, and AD7829 is
straight binary. The designed code transitions occur at successive integer LSB values (i.e., 1 LSB, 2 LSBs, etc.). The LSB size
is = V REF/256 (VDD = 5 V) or the LSB size = (0.8 VREF)/256
(VDD = 3 V). The ideal transfer characteristic for the AD7822,
AD7825, and AD7829 is shown in Figure 6, below.
VDD = 5V
5V
4V
VMID = 3.75V
3V
ADC CODE
11111111
111...110
(VDD = 5V)
1LSB = VREF /256
VMID = 2.5V
2V
111...000
VMID = N/C (1.25V)
10000000
000...010
000...001
00000000
1V
(VDD = 3V)
1LSB = 0.8VREF /256
000...111
1LSB
INPUT SIGNAL RANGE
FOR VARIOUS VMID
VMID
(VDD = 5V) VMID – 1.25V
(VDD = 3V) VMID – 1V
VMID + 1.25V – 1LSB
VMID + 1V – 1LSB
VDD = 3V
ANALOG INPUT VOLTAGE
3V
Figure 6. Transfer Characteristic
ANALOG INPUT
The AD7822 has a single input channel and the AD7825 and
AD7829 have four and eight input channels respectively. Each
input channel has an input span of 2.5 V or 2.0 V, depending on
the supply voltage (VDD). This input span is automatically set
up by an on-chip “VDD Detector” circuit. 5 V operation of the
ADCs is detected when VDD exceeds 4.1 V and 3 V operation is
detected when VDD falls below 3.8 V. This circuit also possesses
a degree of glitch rejection; for example, a glitch from 5.5 V to
2.7 V up to 60 ns wide will not trip the VDD detector.
The VMID pin is used to center this input span anywhere in the
range AGND to VDD. If no input voltage is applied to VMID, the
default input range is AGND to 2.0 V (VDD = 3 V ± 10%) i.e.,
centered about 1.0 V, or AGND to 2.5 V (VDD = 5 V ± 10%)
i.e., centered about 1.25 V. When using the default input range,
the VMID pin can be left unconnected or, in some cases, it can be
decoupled to AGND with a 0.1␮F capacitor.
If, however, an external VMID is applied, the analog input range
will be from VMID – 1.0 V to VMID + 1.0 V (VDD = 3 V ± 10%),
or from VMID – 1.25 V to VMID + 1.25 V (VDD = 5 V ± 10%).
The range of values of VMID that can be applied depends on the
value of VDD. For VDD = 3 V ± 10%, the range of values that
can be applied to VMID is from 1.0 V to VDD – 1.0 V and is 1.25 V
to VDD – 1.25 V when VDD = 5 V ± 10%. Table I shows the relevant ranges of VMID and the input span for various values of
V DD. Figure 7 illustrates the input signal range available with
various values of VMID.
VMID = 2V
VMID = 1.5V
VMID = N/C (1V)
1V
INPUT SIGNAL RANGE
FOR VARIOUS VMID
Figure 7. Analog Input Span Variation with VMID
VMID may be used to remove offsets in a system by applying the
offset to the VMID pin as shown in Figure 8, or it may be used to
accommodate bipolar signals by applying VMID to a level-shifting
circuit before VIN, as shown in Figure 9. When VMID is being
driven by an external source, the source may be directly tied to
the level-shifting circuitry (see Figure 9); however, if the internal
VMID, i.e., the default value, is being used as an output, it must
be buffered before applying it to the level-shifting circuitry, as
the V MID pin has an impedance of approximately 6 kΩ (see
Figure 10).
VIN
VIN
AD7822/
AD7825/
AD7829
VMID
VMID
Table I.
VDD
VMID
VMID Ext
Internal Max
VIN Span
VMID Ext
Min
VIN Span
5.5
5.0
4.5
3.3
3.0
2.7
1.25
1.25
1.25
1.00
1.00
1.00
3.0 to 5.5
2.5 to 5.0
2.0 to 4.5
1.3 to 3.3
1.0 to 3.0
0.7 to 2.7
1.25
1.25
1.25
1.00
1.00
1.00
0 to 2.5
0 to 2.5
0 to 2.5
0 to 2.0
0 to 2.0
0 to 2.0
4.25
3.75
3.25
2.3
2.0
1.7
2V
VMID
Figure 8. Removing Offsets Using VMID
–8–
REV. B
AD7822/AD7825/AD7829
being conducted into the substrate due to an over voltage on an
unselected channel, can cause inaccurate conversions on a
selected channel. The capacitor C2 in Figure 11 is typically
about 4 pF and can be primarily attributed to pin capacitance.
The resistor, R1, is a lumped component made up of the on
resistance of several components, including that of the multiplexer and the track and hold. This resistor is typically about
310 Ω. The capacitor C1 is the track-and-hold capacitor and
has a capacitance of 0.5 pF. Switch 1 is the track-and-hold switch,
while Switch 2 is that of the sampling capacitor as shown in
Figures 2 and 3.
2.5V
VREF
VMID
R4
R3
V
V
AD7822/
AD7825/
AD7829
VIN
R2
R1
0V
VIN
2.5V
VDD
0V
D1
Figure 9. Accommodating Bipolar Signals Using
External VMID
C2
4pF
EXTERNAL
2.5V
AD7822/
AD7825/
AD7829
R4
R3
VIN
R2
B
Figure 11. Equivalent Analog Input Circuit
VREF
V
SW1
D2
When in track phase, Switch 1 is closed and Switch 2 is in
Position A; when in hold mode, Switch 1 opens while Switch
2 remains in Position A. The track-and-hold remains in hold
mode for 120 ns—see Circuit Description—after which it returns
to track mode and the ADC enters its conversion phase. At this
point, Switch 1 opens and Switch 2 moves to Position B. At the
end of the conversion, Switch 2 moves back to Position A.
VMID
V
C1
0.5pF A SW2
R1
310⍀
VIN
Analog Input Selection
R1
On power-up, the default VIN selection is VIN1. When returning
to normal operation from power-down, the VIN selected will be
the same one that was selected prior to power-down being initiated.
Table II below shows the multiplexer address corresponding to
each analog input from VIN1 to VIN4(8) for the AD7825 or AD7829.
0V
VIN
VMID
0V
Table II.
Figure 10. Accommodating Bipolar Signals Using
Internal VMID
NOTE: Although there is a VREF pin from which a voltage reference of 2.5 V may be sourced, or to which an external reference
may be applied, this does not provide an option of varying
the value of the voltage reference. As stated in the specifications
for the AD7822, AD7825, and AD7829, the input voltage range
at this pin is 2.5 V ± 2%.
Analog Input Structure
Figure 11 shows an equivalent circuit of the analog input structure
of the AD7822, AD7825, and the AD7829. The two diodes, D1
and D2, provide ESD protection for the analog inputs. Care
must be taken to ensure that the analog input signal never exceeds
the supply rails by more than 200 mV. This will cause these
diodes to become forward biased and start conducting current into
the substrate. 20 mA is the maximum current these diodes can
conduct without causing irreversible damage to the part. However, it is worth noting that a small amount of current (1 mA)
REV. B
A2
A1
A0
Analog Input Selected
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
VIN1
VIN2
VIN3
VIN4
VIN5
VIN6
VIN7
VIN8
Channel selection on the AD7825 and AD7829 is made without
the necessity of a write operation. The address of the next channel
to be converted is latched at the start of the current read operation,
i.e., on the falling edge of RD while CS is low, as shown in Figure
12. This allows for improved throughput rates in “channel
hopping” applications.
–9–
AD7822/AD7825/AD7829
120ns
50
TRACK CHx
HOLD CHx
TRACK CHx
TRACK CHy
HOLD CHy
fSAMPLE = 2MHz
48
t2
CONVST
46
SNR – dB
t1
EOC
CS
44
42
t3
RD
40
t13
38
0.2
VALID
DATA
DB0–DB7
A0–A2
Figure 12. Channel Hopping Timing
The AD7822/AD7825/AD7829 have a 1 µs power-up time when
using an external reference and a 25 µs power-up time when using
the on-chip reference. When VDD is first connected, the AD7822,
AD7825, and AD7829 are in a low current mode of operation.
Ensure that the CONVST line is not floating when VDD is applied,
as if there is a glitch on CONVST while VDD is rising, the part will
attempt to power up before VDD has fully settled and could enter
an unknown state. In order to carry out a conversion, the AD7822,
AD7825, and AD7829 must first be powered up. The AD7829 is
powered up by a rising edge on the CONVST pin and a conversion
is initiated on the falling edge of CONVST. Figure 15 shows how
to power up the AD7829 when VDD is first connected or after the
AD7829 has been powered down using the CONVST pin when
using either the on-chip, or an external, reference. When using
an external reference, the falling edge of CONVST may occur
before the required power-up time has elapsed; however, the
conversion will not be initiated on the falling edge of CONVST but
rather at the moment when the part has completely powered up,
i.e., after 1 µs. If the falling edge of CONVST occurs after the required
power-up time has elapsed, then it is upon this falling edge that a
conversion is initiated. When using the on-chip reference, it is necessary to wait the required power-up time of approximately 25 µs
before initiating a conversion; i.e., a falling edge on CONVST
may not occur before the required power-up time has elapsed,
when VDD is first connected or after the AD7829 has been powered
down using the CONVST pin as shown in Figure 15.
8.5
8.0
ENOB
7.5
7.0
6.5
6.0
5.5
100
50
40
30
20
ACQUISITION TIME – ns
10
POWER-UP TIMES
There is a minimum time delay between the falling edge of RD
and the next falling edge of the CONVST signal, t13. This is the
minimum acquisition time required of the track-and-hold in
order to maintain 8-bit performance. Figure 13 shows the typical
performance of the AD7825 when channel hopping for various
acquisition times. These results were obtained using an external
reference and internal VMID while channel hopping between
VIN1 and VIN4 with 0 V on Channel 4 and 0.5 V on Channel 1.
200
8
Figure 14. SNR vs. Input Frequency on the AD7825
ADDRESS CHANNEL y
5.0
500
3
4
5
6
INPUT FREQUENCY – MHz
1
15
10
Figure 13. Effective Number of Bits vs. Acquisition Time
for the AD7825
The on-chip track-and-hold can accommodate input frequencies to 10 MHz, making the AD7822, AD7825, and AD7829
ideal for subsampling applications. When the AD7825 is converting a 10 MHz input signal at a sampling rate of 2 MSPS,
the effective number of bits typically remains above seven,
corresponding to a signal-to-noise ratio of 42 dBs as shown
in Figure 14.
EXTERNAL REFERENCE
VDD
tPOWER-UP
1␮s
CONVST
CONVERSION
INITIATED HERE
ON-CHIP REFERENCE
VDD
tPOWER-UP
25␮s
CONVST
CONVERSION
INITIATED HERE
Figure 15. AD7829 Power-Up Time
–10–
REV. B
AD7822/AD7825/AD7829
Figure 16 shows how to power up the AD7822 or AD7825 when
VDD is first connected or after the ADCs have been powered
down using the PD pin, or the CONVST pin, with either the
on-chip or an external reference. When the supplies are first
connected or after the part has been powered down by the PD
pin, only a rising edge on the PD pin will cause the part to
power up. When the part has been powered down using the
CONVST pin, a rising edge on either the PD pin or the CONVST
pin will power the part up again.
tPOWER-UP tCONVERT
1␮s
330ns
POWER-DOWN
CONVST
tCYCLE
10␮s @ 100kSPS
Figure 17. Automatic Power-Down
As with the AD7829, when using an external reference with the
AD7822 or AD7825, the falling edge of CONVST may occur
before the required power-up time has elapsed, however, if this
is the case, the conversion will not be initiated on the falling edge
of CONVST, but rather at the moment when the part has powered
up completely, i.e., after 1 µs. If the falling edge of CONVST
occurs after the required power-up time has elapsed, it is upon
this falling edge that a conversion is initiated. When using the
on-chip reference, it is necessary to wait the required powerup time of approximately 25 µs before initiating a conversion;
i.e., a falling edge on CONVST may not occur before the
required power-up time has elapsed, when supplies are first
connected to the AD7822 or AD7825, or when the ADCs have
been powered down using the PD pin or the CONVST pin as
shown in Figure 16.
For example, if the AD7822 is operated in a continuous sampling mode, with a throughput rate of 100 kSPS and using an
external reference, the power consumption is calculated as follows. The power dissipation during normal operation is 36 mW,
VDD = 3 V. If the power-up time is 1 µs and the conversion time
is 330 ns (@ +25°C), the AD7822 can be said to dissipate
36 mW (maximum) for 1.33 µs during each conversion cycle.
If the throughput rate is 100 kSPS, the cycle time is 10 µs
and the average power dissipated during each cycle is (1.33/10)
× (36 mW) = 4.79 mW. This calculation uses the minimum
conversion time, thus giving the best case power dissipation
at this throughput rate. However, the actual power dissipated during each conversion cycle could increase depending
on the actual conversion time (up to a maximum of 420 ns).
Figure 18 shows the power vs. throughput rate for automatic
full power-down.
100
EXTERNAL REFERENCE
VDD
10
PD
tPOWER-UP
1␮s
POWER – mW
tPOWER-UP
1␮s
CONVST
CONVERSION
INITIATED HERE
CONVERSION
INITIATED HERE
1
0.1
ON-CHIP REFERENCE
VDD
0
0
PD
tPOWER-UP
tPOWER-UP
25␮s
25␮s
50
100
150 200 250 300 350
THROUGHPUT – kSPS
400
450
500
Figure 18. AD7822/AD7825/AD7829 Power vs. Throughput
CONVST
0
CONVERSION
INITIATED HERE
2048 POINT FFT
SAMPLING
2MSPS
fIN = 200kHz
–10
CONVERSION
INITIATED HERE
–20
Figure 16. AD7822/AD7825 Power-Up Time
–30
dB
POWER VS. THROUGHPUT
Superior power performance can be achieved by using the automatic power-down (Mode 2) at the end of a conversion—see
Operating Modes section of the data sheet.
–50
–60
–11–
–70
–80
0
28
57
85
113
142
170
198
227
255
283
312
340
368
396
425
453
481
510
538
566
595
623
651
680
708
736
765
793
821
850
878
906
935
963
991
Figure 17 shows how the automatic power-down is implemented
using the CONVST signal to achieve the optimum power performance for the AD7822, AD7825, and AD7829. The duration
of the CONVST pulse is set to be equal to or less than the
power-up time of the devices—see Operating Modes section. As
the throughput rate is reduced, the device remains in its powerdown state longer and the average power consumption over time
drops accordingly.
REV. B
–40
FREQUENCY – kHz
Figure 19. AD7822/AD7825/AD7829 SNR
AD7822/AD7825/AD7829
OPERATING MODES
Mode 2 Operation (Automatic Power-Down)
The AD7822, AD7825, and AD7829 have two possible modes
of operation, depending on the state of the CONVST pulse
approximately 100 ns after the end of a conversion, i.e., upon
the rising edge of the EOC pulse.
When the AD7822, AD7825, and AD7829 are operated in
Mode 2 (see Figure 21), they automatically power down at the
end of a conversion. The CONVST signal is brought low to initiate a conversion and is left logic low until after the EOC goes
high, i.e., approximately 100 ns after the end of the conversion.
The state of the CONVST signal is sampled at this point (i.e.,
530 ns maximum after CONVST falling edge) and the AD7822,
AD7825, and AD7829 will power down as long as CONVST
is low. The ADC is powered up again on the rising edge of the
CONVST signal. Superior power performance can be achieved
in this mode of operation by only powering up the AD7822,
AD7825, and AD7829 to carry out a conversion. The parallel
interface of the AD7822, AD7825, and AD7829 is still fully
operational while the ADCs are powered down. A read may occur
while the part is powered down, and so it does not necessarily
need to be placed within the EOC pulse as shown in Figure 21.
Mode 1 Operation (High-Speed Sampling)
When the AD7822, AD7825, and AD7829 are operated in
Mode 1 they are not powered-down between conversions. This
mode of operation allows high throughput rates to be achieved.
Figure 20 shows how this optimum throughput rate is achieved
by bringing CONVST high before the end of a conversion, i.e.,
before the EOC pulses low. When operating in this mode, a new
conversion should not be initiated until 30 ns after the end of a
read operation. This is to allow the track/hold to acquire the
analog signal to 0.5 LSB accuracy.
120ns
TRACK
HOLD
TRACK
HOLD
t2
CONVST
t1
EOC
CS
t3
RD
VALID
DATA
DB0–DB7
Figure 20. Mode 1 Operation
tPOWER-UP
POWER
DOWN
HERE
CONVST
t1
EOC
CS
RD
VALID
DATA
DB0–DB7
Figure 21. Mode 2 Operation
–12–
REV. B
AD7822/AD7825/AD7829
PARALLEL INTERFACE
The parallel interface of the AD7822, AD7825, and AD7829 is
eight bits wide. Figure 22 shows a timing diagram illustrating
the operational sequence of the AD7822/AD7825/AD7829
parallel interface. The multiplexer address is latched into the
AD7822/AD7825/AD7829 on the falling edge of the RD input.
The on-chip track/hold goes into hold mode on the falling
edge of CONVST and a conversion is also initiated at this
point. When the conversion is complete, the end of conversion
line (EOC) pulses low to indicate that new data is available in
the output register of the AD7822, AD7825, and AD7829. The
EOC pulse will stay logic low for a maximum time of 110 ns.
However, the EOC pulse can be reset high by a rising edge of
RD. This EOC line can be used to drive an edge-triggered interrupt of a microprocessor. CS and RD going low accesses the
8-bit conversion result. It is possible to tie CS permanently low
and use only RD to access the data. In systems where the part is
interfaced to a gate array or ASIC, this EOC pulse can be applied
to the CS and RD inputs to latch data out of the AD7822,
AD7825, and AD7829 and into the gate array or ASIC. This
means that the gate array or ASIC does not need any conversion status recognition logic and it also eliminates the logic
required in the gate array or ASIC to generate the read signal
for the AD7822, AD7825, and AD7829.
t2
CONVST
t1
t4
EOC
t5
CS
t7
t6
t8
RD
t9
t3
t10
VALID
DATA
DB0–DB7
t11
t12
t13
NEXT
CHANNEL
ADDRESS
A0–A2
Figure 22. AD7822/AD7825/AD7829 Parallel Port Timing
REV. B
–13–
AD7822/AD7825/AD7829
MICROPROCESSOR INTERFACING
parallel slave port when control bit PSPMODE in the TRISE
register is set. Setting PSPMODE enables the port pin RE0 to
be the RD output and RE2 to be the CS (chip select) output.
For this functionality, the corresponding data direction bits
of the TRISE register must be configured as outputs (reset to
0). See PIC16/17 Microcontroller User Manual.
The parallel port on the AD7822/AD7825/AD7829 allows the
ADCs to be interfaced to a range of many different microcontrollers. This section explains how to interface the AD7822,
AD7825, and AD7829 with some of the more common microcontroller parallel interface protocols.
AD7822/AD7825/AD7829 to 8051
Figure 23 below shows a parallel interface between the AD7822,
AD7825, and AD7829 and the 8051 microcontroller. The EOC
signal on the AD7822, AD7825, and AD7829 provides an interrupt request to the 8051 when a conversion ends and data is
ready. Port 0 of the 8051 may serve as an input or output port,
or, as in this case when used together, may be used as a bidirectional low order address and data bus. The address latch enable
output of the 8051 is used to latch the low byte of the address
during accesses to the device, while the high order address byte
is supplied from Port 2. Port 2 latches remain stable when the
AD7822, AD7825, and AD7829 are addressed, as they do not have
to be turned around (set to 1) for data input as is the case for Port 0.
AD7822/
AD7825/
AD7829*
PIC16C6x/7x*
DB0–DB7
PSP0–PSP7
CS
CS
RD
RD
INT
EOC
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 24. Interfacing to the PIC16C6x/7x
8051*
AD7822/AD7825/AD7829 to ADSP-21xx
DB0–DB7
AD0–AD7
LATCH
AD7822/
AD7825/
AD7829*
DECODER
ALE
Figure 25 below shows a parallel interface between the AD7822,
AD7825, and AD7829 and the ADSP-21xx series of DSPs. As
before, the EOC signal on the AD7822, AD7825, and AD7829
provides an interrupt request to the DSP when a conversion ends.
CS
ADSP-21xx*
A8–A15
RD
RD
INT
EOC
D7–D0
DB0–DB7
A13–A0
AD7822/
AD7825/
AD7829*
*ADDITIONAL PINS OMITTED FOR CLARITY
ADDRESS
DECODE
LOGIC
Figure 23. Interfacing to the 8051
DMS
AD7822/AD7825/AD7829 to PIC16C6x/7x
Figure 24 shows a parallel interface between the AD7822,
AD7825, and AD7829 and the PIC16C64/65/74. The EOC
signal on the AD7822, AD7825, and AD7829 provides an
interrupt request to the microcontroller when a conversion
begins. Of the PIC16C6x/7x range of microcontrollers only
the PIC16C64/65/74 can provide the option of a parallel slave
port. Port D of the microcontroller will operate as an 8-bit wide
–14–
EN
RD
IRQ
CS
RD
EOC
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 25. Interfacing to the ADSP-21xx
REV. B
AD7822/AD7825/AD7829
Interfacing Multiplexer Address Inputs
AD7822 Stand–Alone Operation
Figure 26 shows a simplified interfacing scheme between the
AD7825/AD7829 and any microprocessor or microcontroller,
which facilitates easy channel selection on the ADCs. The multiplexer address is latched on the falling edge of the RD signal,
as outlined in the Parallel Interface section, which allows the use
of the 3 LSBs of the address bus to select the channel address.
As shown in Figure 26, only address bits A3 to A15 are address
decoded allowing A0 to A2 to be changed according to desired
channel selection without affecting chip selection.
The AD7822, being the single channel device, does not have
any multiplexer addressing associated with it and can in fact be
controlled with just one signal, i.e., the CONVST signal. As
shown in Figure 27, the RD and CS pins are both tied to the
EOC pin, and the resulting signal may be used as an interrupt
request signal (IRQ) on a DSP, as a WR signal to memory, or as
a CLK to a latch or ASIC. The timing for this interface,
as shown in Figure 27, demonstrates how with the CONVST
signal alone, a conversion may be initiated, data is latched out,
and the operating mode of the AD7822 can be selected.
MICROPROCESSOR READ CYCLE
SYSTEM BUS
A0
A1
A2
A15–A3
ADDRESS
DECODE
CS
CS
AD7825/
AD7829
RD
ADC I/O ADDRESS
A15–A3
RD
A2–A0
MUX ADDRESS
DB7–DB0
DB0–DB7
A/D RESULT
MUX ADDRESS
(CHANNEL SELECTION A0–A2)
LATCHED
Figure 26. AD7825/AD7829 Simplified Microinterfacing Scheme
t1
CONVST
RD
AD7822
CS
DSP/
LATCH/ASIC
CONVST
t4
EOC
CS
EOC
RD
DB7–DB0
DB0–DB7
Figure 27. AD7822 Stand-Alone Operation
REV. B
–15–
A/D RESULT
AD7822/AD7825/AD7829
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
20-Lead Plastic DIP
(N-20)
1.060 (26.90)
0.925 (23.50)
20
11
1
10
0.280 (7.11)
0.240 (6.10)
PIN 1
0.060 (1.52)
0.015 (0.38)
0.210 (5.33)
MAX
0.325 (8.25)
0.300 (7.62) 0.195 (4.95)
0.115 (2.93)
0.130
(3.30)
MIN
0.160 (4.06)
0.115 (2.93)
0.022 (0.558)
0.014 (0.356)
0.100
(2.54)
BSC
0.015 (0.381)
0.008 (0.204)
0.070 (1.77) SEATING
0.045 (1.15) PLANE
20-Lead Small Outline Package
(R-20)
11
1
10
PIN 1
0.4193 (10.65)
0.3937 (10.00)
20
0.2992 (7.60)
0.2914 (7.40)
0.5118 (13.00)
0.4961 (12.60)
0.1043 (2.65)
0.0926 (2.35)
0.0291 (0.74)
x 45°
0.0098 (0.25)
8° 0.0500 (1.27)
0.0500 0.0192 (0.49)
0° 0.0157 (0.40)
SEATING
0.0125
(0.32)
(1.27) 0.0138 (0.35)
PLANE
0.0091 (0.23)
BSC
0.0118 (0.30)
0.0040 (0.10)
20-Lead Thin Shrink Small Outline Package
(RU-20)
0.260 (6.60)
0.252 (6.40)
11
0.256 (6.50)
0.246 (6.25)
0.177 (4.50)
0.169 (4.30)
20
1
0.006 (0.15)
0.002 (0.05)
SEATING
PLANE
10
PIN 1
0.0433
(1.10)
MAX
0.0256 (0.65) 0.0118 (0.30)
BSC
0.0075 (0.19)
0.0079 (0.20)
0.0035 (0.090)
–16–
8°
0°
0.028 (0.70)
0.020 (0.50)
REV. B
AD7822/AD7825/AD7829
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
24-Lead Plastic DIP
(N-24)
1.275 (32.30)
1.125 (28.60)
24
13
1
12
PIN 1
0.210
(5.33)
MAX
0.200 (5.05)
0.125 (3.18)
0.280 (7.11)
0.240 (6.10)
0.325 (8.25)
0.300 (7.62) 0.195 (4.95)
0.060 (1.52)
0.115 (2.93)
0.015 (0.38)
0.150
(3.81)
MIN
0.100 (2.54)
BSC
0.022 (0.558)
0.014 (0.356)
0.015 (0.381)
0.008 (0.204)
0.070 (1.77) SEATING
0.045 (1.15) PLANE
24-Lead Small Outline Package
(R-24)
24
13
1
12
PIN 1
0.1043 (2.65)
0.0926 (2.35)
0.0500
(1.27)
BSC
0.0118 (0.30)
0.0040 (0.10)
0.2992 (7.60)
0.2914 (7.40)
0.4193 (10.65)
0.3937 (10.00)
0.6141 (15.60)
0.5985 (15.20)
0.0291 (0.74)
x 45°
0.0098 (0.25)
8°
0.0192 (0.49)
0°
SEATING
0.0125
(0.32)
0.0138 (0.35) PLANE
0.0091 (0.23)
0.0500 (1.27)
0.0157 (0.40)
24-Lead Thin Shrink Small Outline Package
(RU-24)
0.311 (7.90)
0.303 (7.70)
13
0.256 (6.50)
0.246 (6.25)
0.177 (4.50)
0.169 (4.30)
24
1
0.006 (0.15)
0.002 (0.05)
SEATING
PLANE
REV. B
12
PIN 1
0.0433
(1.10)
MAX
0.0256 (0.65) 0.0118 (0.30)
BSC
0.0075 (0.19)
–17–
0.0079 (0.20)
0.0035 (0.090)
8°
0°
0.028 (0.70)
0.020 (0.50)
AD7822/AD7825/AD7829
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Lead Plastic DIP
(N-28)
1.565 (39.70)
1.380 (35.10)
28
15
0.580 (14.73)
0.485 (12.32)
1
14
0.060 (1.52)
0.015 (0.38)
PIN 1
0.250
(6.35)
MAX
0.625 (15.87)
0.600 (15.24)
0.150
(3.81)
MIN
0.200 (5.05) 0.022 (0.558)
0.125 (3.18) 0.014 (0.356)
0.100
(2.54)
BSC
0.070
(1.77)
MAX
0.195 (4.95)
0.125 (3.18)
0.015 (0.381)
0.008 (0.204)
SEATING
PLANE
28-Lead Small Outline Package
(R-28)
15
1
14
0.1043 (2.65)
0.0926 (2.35)
PIN 1
0.0118 (0.30)
0.0040 (0.10)
0.4193 (10.65)
0.3937 (10.00)
28
0.2992 (7.60)
0.2914 (7.40)
0.7125 (18.10)
0.6969 (17.70)
0.0500
(1.27)
BSC
0.0291 (0.74)
x 45°
0.0098 (0.25)
8° 0.0500 (1.27)
0.0192 (0.49)
0° 0.0157 (0.40)
SEATING 0.0125 (0.32)
0.0138 (0.35)
PLANE 0.0091 (0.23)
28-Lead Thin Shrink Small Outline Package
(RU-28)
0.386 (9.80)
0.378 (9.60)
15
0.256 (6.50)
0.246 (6.25)
0.177 (4.50)
0.169 (4.30)
28
1
14
PIN 1
0.006 (0.15)
0.002 (0.05)
SEATING
PLANE
0.0433
(1.10)
MAX
0.0256 (0.65) 0.0118 (0.30)
BSC
0.0075 (0.19)
–18–
0.0079 (0.20)
0.0035 (0.090)
8°
0°
0.028 (0.70)
0.020 (0.50)
REV. B
10/24/01 10:15 AM_LM
AD7822/AD7825/AD7829
Revision History
Location
Page
Data Sheet changed from REV. A to REV. B.
Edit to POWER REQUIREMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Edit to PIN FUNCTION DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Edit to CIRCUIT DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Edit toTYPICAL CONNECTION DIAGRAM section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Edit to ANALOG INPUT section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Edit to ANALOG INPUT SELECTION section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Edit to POWER-UP TIMES section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Edit to POWER vs. THROUGHPUT section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
AD7822 Stand-Alone Operation section created . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
REV. B
–19–
–20–
PRINTED IN U.S.A.
C01321a–0–10/01(B)